svn commit: r356746 - stable/12/sys/amd64/vmm/amd
Author: anish
Date: Wed Jan 15 02:31:03 2020
New Revision: 356746
URL: https://svnweb.freebsd.org/changeset/base/356746
Log:
MFC r355258: Bhyve AMD IOMMU log the last timeout command.
Differential Revision:https://reviews.freebsd.org/D22566
Modified:
stable/12/sys/amd64/vmm/amd/amdvi_hw.c
Modified: stable/12/sys/amd64/vmm/amd/amdvi_hw.c
==
--- stable/12/sys/amd64/vmm/amd/amdvi_hw.c Wed Jan 15 01:34:05 2020
(r356745)
+++ stable/12/sys/amd64/vmm/amd/amdvi_hw.c Wed Jan 15 02:31:03 2020
(r356746)
@@ -66,7 +66,7 @@ SYSCTL_NODE(_hw_vmm, OID_AUTO, amdvi, CTLFLAG_RW, NULL
/* Print RID or device ID in PCI string format. */
#define RID2PCI_STR(d) PCI_RID2BUS(d), PCI_RID2SLOT(d), PCI_RID2FUNC(d)
-static void amdvi_dump_cmds(struct amdvi_softc *softc);
+static void amdvi_dump_cmds(struct amdvi_softc *softc, int count);
static void amdvi_print_dev_cap(struct amdvi_softc *softc);
MALLOC_DEFINE(M_AMDVI, "amdvi", "amdvi");
@@ -321,9 +321,7 @@ amdvi_cmd_cmp(struct amdvi_softc *softc, const uint64_
pa = vtophys(>cmp_data);
cmd->opcode = AMDVI_CMP_WAIT_OPCODE;
- cmd->word0 = (pa & 0xFFF8) |
- (AMDVI_CMP_WAIT_STORE);
- //(AMDVI_CMP_WAIT_FLUSH | AMDVI_CMP_WAIT_STORE);
+ cmd->word0 = (pa & 0xFFF8) | AMDVI_CMP_WAIT_STORE;
cmd->word1 = (pa >> 32) & 0xF;
cmd->addr = data;
@@ -492,26 +490,26 @@ amdvi_wait(struct amdvi_softc *softc)
device_printf(softc->dev, "Error: completion failed"
" tail:0x%x, head:0x%x.\n",
ctrl->cmd_tail, ctrl->cmd_head);
- amdvi_dump_cmds(softc);
+ /* Dump the last command. */
+ amdvi_dump_cmds(softc, 1);
}
static void
-amdvi_dump_cmds(struct amdvi_softc *softc)
+amdvi_dump_cmds(struct amdvi_softc *softc, int count)
{
struct amdvi_ctrl *ctrl;
struct amdvi_cmd *cmd;
int off, i;
ctrl = softc->ctrl;
- device_printf(softc->dev, "Dump all the commands:\n");
+ device_printf(softc->dev, "Dump last %d command(s):\n", count);
/*
* If h/w is stuck in completion, it is the previous command,
* start dumping from previous command onward.
*/
off = MOD_DEC(ctrl->cmd_head, sizeof(struct amdvi_cmd),
softc->cmd_max);
- for (i = 0; off != ctrl->cmd_tail &&
- i < softc->cmd_max; i++) {
+ for (i = 0; off != ctrl->cmd_tail && i < count; i++) {
cmd = (struct amdvi_cmd *)((uint8_t *)softc->cmd + off);
printf(" [CMD%d, off:0x%x] opcode= 0x%x 0x%x"
" 0x%x 0x%lx\n", i, off, cmd->opcode,
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svn commit: r355258 - head/sys/amd64/vmm/amd
Author: anish
Date: Sun Dec 1 04:00:08 2019
New Revision: 355258
URL: https://svnweb.freebsd.org/changeset/base/355258
Log:
bhyve amd: amdvi_dump_cmds() log the command for which the command completion
failed. Completion is checked in poll mode although it can be done using
interrupts.
No need to log all the commands in command ring but only the last one for
which completion failed.
Reported by: n...@freebsd.org
Reviewed by: np, markj
MFC after: 2 weeks
Differential Revision: https://reviews.freebsd.org/D22566
Modified:
head/sys/amd64/vmm/amd/amdvi_hw.c
Modified: head/sys/amd64/vmm/amd/amdvi_hw.c
==
--- head/sys/amd64/vmm/amd/amdvi_hw.c Sun Dec 1 03:56:18 2019
(r355257)
+++ head/sys/amd64/vmm/amd/amdvi_hw.c Sun Dec 1 04:00:08 2019
(r355258)
@@ -66,7 +66,7 @@ SYSCTL_NODE(_hw_vmm, OID_AUTO, amdvi, CTLFLAG_RW, NULL
/* Print RID or device ID in PCI string format. */
#define RID2PCI_STR(d) PCI_RID2BUS(d), PCI_RID2SLOT(d), PCI_RID2FUNC(d)
-static void amdvi_dump_cmds(struct amdvi_softc *softc);
+static void amdvi_dump_cmds(struct amdvi_softc *softc, int count);
static void amdvi_print_dev_cap(struct amdvi_softc *softc);
MALLOC_DEFINE(M_AMDVI, "amdvi", "amdvi");
@@ -321,9 +321,7 @@ amdvi_cmd_cmp(struct amdvi_softc *softc, const uint64_
pa = vtophys(>cmp_data);
cmd->opcode = AMDVI_CMP_WAIT_OPCODE;
- cmd->word0 = (pa & 0xFFF8) |
- (AMDVI_CMP_WAIT_STORE);
- //(AMDVI_CMP_WAIT_FLUSH | AMDVI_CMP_WAIT_STORE);
+ cmd->word0 = (pa & 0xFFF8) | AMDVI_CMP_WAIT_STORE;
cmd->word1 = (pa >> 32) & 0xF;
cmd->addr = data;
@@ -492,26 +490,26 @@ amdvi_wait(struct amdvi_softc *softc)
device_printf(softc->dev, "Error: completion failed"
" tail:0x%x, head:0x%x.\n",
ctrl->cmd_tail, ctrl->cmd_head);
- amdvi_dump_cmds(softc);
+ /* Dump the last command. */
+ amdvi_dump_cmds(softc, 1);
}
static void
-amdvi_dump_cmds(struct amdvi_softc *softc)
+amdvi_dump_cmds(struct amdvi_softc *softc, int count)
{
struct amdvi_ctrl *ctrl;
struct amdvi_cmd *cmd;
int off, i;
ctrl = softc->ctrl;
- device_printf(softc->dev, "Dump all the commands:\n");
+ device_printf(softc->dev, "Dump last %d command(s):\n", count);
/*
* If h/w is stuck in completion, it is the previous command,
* start dumping from previous command onward.
*/
off = MOD_DEC(ctrl->cmd_head, sizeof(struct amdvi_cmd),
softc->cmd_max);
- for (i = 0; off != ctrl->cmd_tail &&
- i < softc->cmd_max; i++) {
+ for (i = 0; off != ctrl->cmd_tail && i < count; i++) {
cmd = (struct amdvi_cmd *)((uint8_t *)softc->cmd + off);
printf(" [CMD%d, off:0x%x] opcode= 0x%x 0x%x"
" 0x%x 0x%lx\n", i, off, cmd->opcode,
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svn commit: r330439 - in head/sys: amd64/vmm/amd contrib/dev/acpica/include
Author: anish
Date: Mon Mar 5 02:28:25 2018
New Revision: 330439
URL: https://svnweb.freebsd.org/changeset/base/330439
Log:
Move the new AMD-Vi IVHD [ACPI_IVRS_HARDWARE_NEW]definitions added in r329360
in contrib ACPI to local files till ACPI code adds new definitions reported by
jkim.
Rename ACPI_IVRS_HARDWARE_NEW to ACPI_IVRS_HARDWARE_EFRSUP, since new
definitions add Extended Feature Register support. Use IvrsType to distinguish
three types of IVHD - 0x10(legacy), 0x11 and 0x40(with EFR). IVHD 0x40 is also
called mixed type since it supports HID device entries.
Fix 2 coverity bugs reported by cem.
Reported by:jkim, cem
Approved by:grehan
Differential Revision://reviews.freebsd.org/D14501
Modified:
head/sys/amd64/vmm/amd/amdvi_priv.h
head/sys/amd64/vmm/amd/ivrs_drv.c
head/sys/contrib/dev/acpica/include/actbl2.h
Modified: head/sys/amd64/vmm/amd/amdvi_priv.h
==
--- head/sys/amd64/vmm/amd/amdvi_priv.h Mon Mar 5 02:13:28 2018
(r330438)
+++ head/sys/amd64/vmm/amd/amdvi_priv.h Mon Mar 5 02:28:25 2018
(r330439)
@@ -355,12 +355,43 @@ struct amdvi_domain {
};
/*
+ * I/O Virtualization Hardware Definition Block (IVHD) type 0x10 (legacy)
+ * uses ACPI_IVRS_HARDWARE define in contrib/dev/acpica/include/actbl2.h
+ * New IVHD types 0x11 and 0x40 as defined in AMD IOMMU spec[48882] are
missing in
+ * ACPI code. These new types add extra field EFR(Extended Feature Register).
+ * XXX : Use definition from ACPI when it is available.
+ */
+typedef struct acpi_ivrs_hardware_efr_sup
+{
+ ACPI_IVRS_HEADER Header;
+ UINT16 CapabilityOffset; /* Offset for IOMMU control fields */
+ UINT64 BaseAddress;/* IOMMU control registers */
+ UINT16 PciSegmentGroup;
+ UINT16 Info; /* MSI number and unit ID */
+ UINT32 Attr; /* IOMMU Feature */
+ UINT64 ExtFR; /* IOMMU Extended Feature */
+ UINT64 Reserved; /* v1 feature or v2 attribute */
+} __attribute__ ((__packed__)) ACPI_IVRS_HARDWARE_EFRSUP;
+CTASSERT(sizeof(ACPI_IVRS_HARDWARE_EFRSUP) == 40);
+
+/*
+ * Different type of IVHD.
+ * XXX: Use AcpiIvrsType once new IVHD types are available.
+*/
+enum IvrsType
+{
+ IVRS_TYPE_HARDWARE_LEGACY = 0x10, /* Legacy without EFRi support. */
+ IVRS_TYPE_HARDWARE_EFR= 0x11, /* With EFR support. */
+ IVRS_TYPE_HARDWARE_MIXED = 0x40, /* Mixed with EFR support. */
+};
+
+/*
* AMD IOMMU softc.
*/
struct amdvi_softc {
struct amdvi_ctrl *ctrl;/* Control area. */
device_tdev;/* IOMMU device. */
- enum AcpiIvrsType ivhd_type;/* IOMMU IVHD type 0x10/0x11 or 0x40 */
+ enum IvrsType ivhd_type; /* IOMMU IVHD type. */
booliotlb; /* IOTLB supported by IOMMU */
struct amdvi_cmd *cmd; /* Command descriptor area. */
int cmd_max;/* Max number of commands. */
Modified: head/sys/amd64/vmm/amd/ivrs_drv.c
==
--- head/sys/amd64/vmm/amd/ivrs_drv.c Mon Mar 5 02:13:28 2018
(r330438)
+++ head/sys/amd64/vmm/amd/ivrs_drv.c Mon Mar 5 02:28:25 2018
(r330439)
@@ -86,9 +86,9 @@ ivrs_hdr_iterate_tbl(ivhd_iter_t iter, void *arg)
}
switch (ivrs_hdr->Type) {
- case ACPI_IVRS_TYPE_HARDWARE: /* Legacy */
- case 0x11:
- case 0x40: /* ACPI HID */
+ case IVRS_TYPE_HARDWARE_LEGACY: /* Legacy */
+ case IVRS_TYPE_HARDWARE_EFR:
+ case IVRS_TYPE_HARDWARE_MIXED:
if (!iter(ivrs_hdr, arg))
return;
break;
@@ -116,9 +116,9 @@ ivrs_is_ivhd(UINT8 type)
{
switch(type) {
- case ACPI_IVRS_TYPE_HARDWARE:
- case ACPI_IVRS_TYPE_HARDWARE_EXT1:
- case ACPI_IVRS_TYPE_HARDWARE_EXT2:
+ case IVRS_TYPE_HARDWARE_LEGACY:
+ case IVRS_TYPE_HARDWARE_EFR:
+ case IVRS_TYPE_HARDWARE_MIXED:
return (true);
default:
@@ -206,17 +206,13 @@ ivhd_dev_parse(ACPI_IVRS_HARDWARE* ivhd, struct amdvi_
softc->end_dev_rid = 0;
switch (ivhd->Header.Type) {
- case ACPI_IVRS_TYPE_HARDWARE_EXT1:
- case ACPI_IVRS_TYPE_HARDWARE_EXT2:
- p = (uint8_t *)ivhd + sizeof(ACPI_IVRS_HARDWARE_NEW);
- de = (ACPI_IVRS_DE_HEADER *) ((uint8_t *)ivhd +
- sizeof(ACPI_IVRS_HARDWARE_NEW));
+ case IVRS_TYPE_HARDWARE_LEGACY:
+ p = (uint8_t *)ivhd + sizeof(ACPI_IVRS_HARDWARE);
break;
- case ACPI_IVRS_TYPE_HARDWARE:
- p = (uint8_t *)ivhd +
svn commit: r329360 - in head/sys: amd64/vmm/amd contrib/dev/acpica/include
Author: anish
Date: Fri Feb 16 05:17:00 2018
New Revision: 329360
URL: https://svnweb.freebsd.org/changeset/base/329360
Log:
This change fixes duplicate detection of same IOMMU/AMD-Vi device for Ryzen
with EFR support.
IVRS can have entry of type legacy and non-legacy present at same time for
same AMD-Vi device. ivhd driver will ignore legacy if new IVHD type is present
as specified in AMD-Vi specification. Earlier both of IVHD entries used and two
ivhd devices were created.
Add support for new IVHD type 0x11 and 0x40 in ACPI. Create new struct of
type acpi_ivrs_hardware_new for these new type of IVHDs. Legacy type 0x10 will
continue to use acpi_ivrs_hardware.
Reviewed by: avg
Approved by: grehan
Differential Revision:https://reviews.freebsd.org/D13160
Modified:
head/sys/amd64/vmm/amd/amdvi_hw.c
head/sys/amd64/vmm/amd/amdvi_priv.h
head/sys/amd64/vmm/amd/ivrs_drv.c
head/sys/contrib/dev/acpica/include/actbl2.h
Modified: head/sys/amd64/vmm/amd/amdvi_hw.c
==
--- head/sys/amd64/vmm/amd/amdvi_hw.c Fri Feb 16 04:59:21 2018
(r329359)
+++ head/sys/amd64/vmm/amd/amdvi_hw.c Fri Feb 16 05:17:00 2018
(r329360)
@@ -745,23 +745,8 @@ amdvi_print_pci_cap(device_t dev)
softc->pci_cap = cap >> 24;
device_printf(softc->dev, "PCI cap 0x%x@0x%x feature:%b\n",
cap, off, softc->pci_cap,
- "\020\001IOTLB\002HT\003NPCache\004EFR");
+ "\20\1IOTLB\2HT\3NPCache\4EFR\5CapExt");
- /* IOMMU spec Rev 2.0, section 3.7.2.1 */
- softc->pci_efr = softc->ctrl->ex_feature;
- if (softc->pci_efr) {
- device_printf(softc->dev, "PCI extended Feature:%b\n",
- (int)softc->pci_efr,
- "\020\001PreFSup\002PPRSup\003XTSup\004NXSup\006IASup"
- "\007GASup\008HESup\009PCSup");
- device_printf(softc->dev,
- "PCI HATS = %d GATS = %d GLXSup = %d, max PASID: 0x%x ",
- (int)((softc->pci_efr >> 10) & 0x3),
- (int)((softc->pci_efr >> 12) & 0x3),
- (int)((softc->pci_efr >> 14) & 0x3),
- (int)((softc->pci_efr >> 32) & 0x1F) + 1);
- }
-
return (0);
}
@@ -1040,7 +1025,7 @@ amdvi_init(void)
}
if (!amdvi_enable_user && ivhd_count) {
printf("bhyve: Found %d AMD-Vi/IOMMU device(s), "
- "use hw.vmm.amdvi_enable=1 to enable pass-through.\n",
+ "use hw.vmm.amdvi.enable=1 to enable pass-through.\n",
ivhd_count);
return (EINVAL);
}
@@ -1315,40 +1300,41 @@ static void
amdvi_set_dte(struct amdvi_domain *domain, uint16_t devid, bool enable)
{
struct amdvi_softc *softc;
- struct amdvi_dte temp;
+ struct amdvi_dte* temp;
+ KASSERT(domain, ("domain is NULL for pci_rid:0x%x\n", devid));
+
softc = amdvi_find_iommu(devid);
KASSERT(softc, ("softc is NULL for pci_rid:0x%x\n", devid));
- memset(, 0, sizeof(struct amdvi_dte));
+ temp = _dte[devid];
#ifdef AMDVI_ATS_ENABLE
/* If IOMMU and device support IOTLB, enable it. */
if (amdvi_dev_support_iotlb(softc, devid) && softc->iotlb)
- temp.iotlb_enable = 1;
+ temp->iotlb_enable = 1;
#endif
/* Avoid duplicate I/O faults. */
- temp.sup_second_io_fault = 1;
- temp.sup_all_io_fault = amdvi_disable_io_fault;
+ temp->sup_second_io_fault = 1;
+ temp->sup_all_io_fault = amdvi_disable_io_fault;
- temp.dt_valid = 1;
- temp.domain_id = domain->id;
+ temp->dt_valid = 1;
+ temp->domain_id = domain->id;
if (enable) {
if (domain->ptp) {
- temp.pt_base = vtophys(domain->ptp) >> 12;
- temp.pt_level = amdvi_ptp_level;
+ temp->pt_base = vtophys(domain->ptp) >> 12;
+ temp->pt_level = amdvi_ptp_level;
}
/*
* XXX: Page table valid[TV] bit must be set even if host domain
* page tables are not enabled.
*/
- temp.pt_valid = 1;
- temp.read_allow = 1;
- temp.write_allow = 1;
+ temp->pt_valid = 1;
+ temp->read_allow = 1;
+ temp->write_allow = 1;
}
- amdvi_dte[devid] = temp;
}
static void
Modified: head/sys/amd64/vmm/amd/amdvi_priv.h
==
--- head/sys/amd64/vmm/amd/amdvi_priv.h Fri Feb 16 04:59:21 2018
(r329359)
+++ head/sys/amd64/vmm/amd/amdvi_priv.h Fri Feb 16 05:17:00 2018
(r329360)
@@ -29,6 +29,8 @@
#ifndef _AMDVI_PRIV_H_
#define _AMDVI_PRIV_H_
+#include
+
#defineBIT(n) (1ULL <<
svn commit: r317600 - in head/sys: amd64/vmm/amd modules/vmm
Author: anish
Date: Sun Apr 30 02:08:46 2017
New Revision: 317600
URL: https://svnweb.freebsd.org/changeset/base/317600
Log:
Add AMD IOMMU/AMD-Vi support in bhyve for passthrough/direct assignment to
VMs. To enable AMD-Vi, set hw.vmm.amdvi.enable=1.
Reviewed by:bcr
Approved by:grehan
Tested by:rgrimes
Differential Revision:https://reviews.freebsd.org/D10049
Added:
head/sys/amd64/vmm/amd/amdvi_hw.c (contents, props changed)
head/sys/amd64/vmm/amd/amdvi_priv.h (contents, props changed)
head/sys/amd64/vmm/amd/ivrs_drv.c (contents, props changed)
Modified:
head/sys/modules/vmm/Makefile
Added: head/sys/amd64/vmm/amd/amdvi_hw.c
==
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/amd64/vmm/amd/amdvi_hw.c Sun Apr 30 02:08:46 2017
(r317600)
@@ -0,0 +1,1509 @@
+/*-
+ * Copyright (c) 2016, Anish Gupta (an...@freebsd.org)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice unmodified, this list of conditions, and the following
+ *disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+__FBSDID("$FreeBSD$");
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include "pcib_if.h"
+
+#include "io/iommu.h"
+#include "amdvi_priv.h"
+
+SYSCTL_DECL(_hw_vmm);
+SYSCTL_NODE(_hw_vmm, OID_AUTO, amdvi, CTLFLAG_RW, NULL, NULL);
+
+#define MOD_INC(a, s, m) (((a) + (s)) % ((m) * (s)))
+#define MOD_DEC(a, s, m) (((a) - (s)) % ((m) * (s)))
+
+/* Print RID or device ID in PCI string format. */
+#define RID2PCI_STR(d) PCI_RID2BUS(d), PCI_RID2SLOT(d), PCI_RID2FUNC(d)
+
+static void amdvi_dump_cmds(struct amdvi_softc *softc);
+static void amdvi_print_dev_cap(struct amdvi_softc *softc);
+
+MALLOC_DEFINE(M_AMDVI, "amdvi", "amdvi");
+
+extern device_t *ivhd_devs;
+
+extern int ivhd_count;
+SYSCTL_INT(_hw_vmm_amdvi, OID_AUTO, count, CTLFLAG_RDTUN, _count,
+0, NULL);
+
+static int amdvi_enable_user = 0;
+SYSCTL_INT(_hw_vmm_amdvi, OID_AUTO, enable, CTLFLAG_RDTUN,
+_enable_user, 0, NULL);
+TUNABLE_INT("hw.vmm.amdvi_enable", _enable_user);
+
+#ifdef AMDVI_ATS_ENABLE
+/* XXX: ATS is not tested. */
+static int amdvi_enable_iotlb = 1;
+SYSCTL_INT(_hw_vmm_amdvi, OID_AUTO, iotlb_enabled, CTLFLAG_RDTUN,
+_enable_iotlb, 0, NULL);
+TUNABLE_INT("hw.vmm.enable_iotlb", _enable_iotlb);
+#endif
+
+static int amdvi_host_ptp = 1; /* Use page tables for host. */
+SYSCTL_INT(_hw_vmm_amdvi, OID_AUTO, host_ptp, CTLFLAG_RDTUN,
+_host_ptp, 0, NULL);
+TUNABLE_INT("hw.vmm.amdvi.host_ptp", _host_ptp);
+
+/* Page table level used <= supported by h/w[v1=7]. */
+static int amdvi_ptp_level = 4;
+SYSCTL_INT(_hw_vmm_amdvi, OID_AUTO, ptp_level, CTLFLAG_RDTUN,
+_ptp_level, 0, NULL);
+TUNABLE_INT("hw.vmm.amdvi.ptp_level", _ptp_level);
+
+/* Disable fault event reporting. */
+static int amdvi_disable_io_fault = 0;
+SYSCTL_INT(_hw_vmm_amdvi, OID_AUTO, disable_io_fault, CTLFLAG_RDTUN,
+_disable_io_fault, 0, NULL);
+TUNABLE_INT("hw.vmm.amdvi.disable_io_fault", _disable_io_fault);
+
+static uint32_t amdvi_dom_id = 0; /* 0 is reserved for host. */
+SYSCTL_UINT(_hw_vmm_amdvi, OID_AUTO, domain_id, CTLFLAG_RD,
+_dom_id, 0, NULL);
+/*
+ * Device table entry.
+ * Bus(256) x Dev(32) x Fun(8) x DTE(256 bits or 32 bytes).
+ * = 256 * 2 * PAGE_SIZE.
+ */
+static struct amdvi_dte amdvi_dte[PCI_NUM_DEV_MAX] __aligned(PAGE_SIZE);
+CTASSERT(PCI_NUM_DEV_MAX == 0x1);
+CTASSERT(sizeof(amdvi_dte) == 0x20);
+
+static SLIST_HEAD (, amdvi_domain) dom_head;
+
+static inline void
+amdvi_pci
svn commit: r297806 - head/sys/amd64/vmm/amd
Author: anish Date: Mon Apr 11 05:09:43 2016 New Revision: 297806 URL: https://svnweb.freebsd.org/changeset/base/297806 Log: Allow guest writes to AMD microcode update[0xc0010020] MSR without updating actual hardware MSR. This allows guest microcode update to go through which otherwise failing because wrmsr() was returning EINVAL. Submitted by:Yamagi Burmeister Approved by:grehan MFC after:2 weeks Modified: head/sys/amd64/vmm/amd/svm_msr.c Modified: head/sys/amd64/vmm/amd/svm_msr.c == --- head/sys/amd64/vmm/amd/svm_msr.cMon Apr 11 04:56:23 2016 (r297805) +++ head/sys/amd64/vmm/amd/svm_msr.cMon Apr 11 05:09:43 2016 (r297806) @@ -156,6 +156,11 @@ svm_wrmsr(struct svm_softc *sc, int vcpu * Ignore writes to the "Interrupt Pending Message" MSR. */ break; + case MSR_K8_UCODE_UPDATE: + /* +* Ignore writes to microcode update register. +*/ + break; default: error = EINVAL; break; ___ svn-src-all@freebsd.org mailing list https://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscr...@freebsd.org"
