svn commit: r352503 - stable/12/sys/arm64/arm64
Author: jchandra
Date: Wed Sep 18 23:33:38 2019
New Revision: 352503
URL: https://svnweb.freebsd.org/changeset/base/352503
Log:
MFC r348380:
arm64 gicv3_its: Fix a typo
Fix 'Cavium' spelling in errata description.
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D20418
Modified:
stable/12/sys/arm64/arm64/gicv3_its.c
Directory Properties:
stable/12/ (props changed)
Modified: stable/12/sys/arm64/arm64/gicv3_its.c
==
--- stable/12/sys/arm64/arm64/gicv3_its.c Wed Sep 18 23:30:27 2019
(r352502)
+++ stable/12/sys/arm64/arm64/gicv3_its.c Wed Sep 18 23:33:38 2019
(r352503)
@@ -272,7 +272,7 @@ static const struct {
} its_quirks[] = {
{
/* Cavium ThunderX Pass 1.x */
- .desc = "Cavoum ThunderX errata: 22375, 24313",
+ .desc = "Cavium ThunderX errata: 22375, 24313",
.iidr = GITS_IIDR_RAW(GITS_IIDR_IMPL_CAVIUM,
GITS_IIDR_PROD_THUNDER, GITS_IIDR_VAR_THUNDER_1, 0),
.iidr_mask = ~GITS_IIDR_REVISION_MASK,
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svn commit: r352502 - stable/12/sys/arm/arm
Author: jchandra
Date: Wed Sep 18 23:30:27 2019
New Revision: 352502
URL: https://svnweb.freebsd.org/changeset/base/352502
Log:
MFC r339517:
arm generic_timer: fix armv8 timer desc
In the FDT based probe, check for "arm,armv8-timer" before "arm,armv7-timer".
This gets the description right when the timer node has both entries in
compatible list.
Modified:
stable/12/sys/arm/arm/generic_timer.c
Directory Properties:
stable/12/ (props changed)
Modified: stable/12/sys/arm/arm/generic_timer.c
==
--- stable/12/sys/arm/arm/generic_timer.c Wed Sep 18 23:23:34 2019
(r352501)
+++ stable/12/sys/arm/arm/generic_timer.c Wed Sep 18 23:30:27 2019
(r352502)
@@ -322,11 +322,11 @@ arm_tmr_fdt_probe(device_t dev)
if (!ofw_bus_status_okay(dev))
return (ENXIO);
- if (ofw_bus_is_compatible(dev, "arm,armv7-timer")) {
- device_set_desc(dev, "ARMv7 Generic Timer");
- return (BUS_PROBE_DEFAULT);
- } else if (ofw_bus_is_compatible(dev, "arm,armv8-timer")) {
+ if (ofw_bus_is_compatible(dev, "arm,armv8-timer")) {
device_set_desc(dev, "ARMv8 Generic Timer");
+ return (BUS_PROBE_DEFAULT);
+ } else if (ofw_bus_is_compatible(dev, "arm,armv7-timer")) {
+ device_set_desc(dev, "ARMv7 Generic Timer");
return (BUS_PROBE_DEFAULT);
}
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svn commit: r352501 - stable/12/sys/arm64/arm64
Author: jchandra
Date: Wed Sep 18 23:23:34 2019
New Revision: 352501
URL: https://svnweb.freebsd.org/changeset/base/352501
Log:
MFC r348377-r348379, r349347
r348377:
gic_v3: consolidate per-cpu redistributor information
Update 'struct gic_redists' to consolidate all per-cpu redistributor
information into a new 'struct redist_pcpu'. Provide a new interface
(GICV3_IVAR_REDIST) for the GIC driver, which can be used to retrieve
the per-cpu data.
This per-cpu redistributor struct will be later used to improve the
GIC ITS setup.
While there, remove some unused fields in gic_v3_var.h interface.
No functional changes.
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D19842
r348378:
gicv3_its: refactor LPI init into a new function
Move the per-cpu LPI intialization to a separate function. This is
in preparation for a commit that does LPI init only once for a CPU,
even when there are multiple ITS blocks associated with the CPU.
No functional changes in this commit.
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D19843
r348379:
gicv3_its: do LPI init only once per CPU
The initialization required for LPIs (setting up pending tables etc.)
has to be done just once per CPU, even in the case where there are
multiple ITS blocks associated with the CPU.
Add a flag lpi_enabled in the per-cpu distributor info for this and
use it to ensure that we call its_init_cpu_lpi() just once.
This enables us to support platforms where multiple GIC ITS blocks
can generate LPIs to a CPU.
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D19844
r349347:
arm64 gicv3_its: enable all ITS blocks for a CPU
We now support multiple ITS blocks raising interrupts to a CPU.
Add all available CPUs to the ITS when no NUMA information is
available.
This reverts the check added in r340602, at that tim we did not
suppport multiple ITS blocks for a CPU.
Differential Revision:https://reviews.freebsd.org/D20417
Modified:
stable/12/sys/arm64/arm64/gic_v3.c
stable/12/sys/arm64/arm64/gic_v3_var.h
stable/12/sys/arm64/arm64/gicv3_its.c
Directory Properties:
stable/12/ (props changed)
Modified: stable/12/sys/arm64/arm64/gic_v3.c
==
--- stable/12/sys/arm64/arm64/gic_v3.c Wed Sep 18 23:18:26 2019
(r352500)
+++ stable/12/sys/arm64/arm64/gic_v3.c Wed Sep 18 23:23:34 2019
(r352501)
@@ -183,36 +183,44 @@ uint32_t
gic_r_read_4(device_t dev, bus_size_t offset)
{
struct gic_v3_softc *sc;
+ struct resource *rdist;
sc = device_get_softc(dev);
- return (bus_read_4(sc->gic_redists.pcpu[PCPU_GET(cpuid)], offset));
+ rdist = >gic_redists.pcpu[PCPU_GET(cpuid)]->res;
+ return (bus_read_4(rdist, offset));
}
uint64_t
gic_r_read_8(device_t dev, bus_size_t offset)
{
struct gic_v3_softc *sc;
+ struct resource *rdist;
sc = device_get_softc(dev);
- return (bus_read_8(sc->gic_redists.pcpu[PCPU_GET(cpuid)], offset));
+ rdist = >gic_redists.pcpu[PCPU_GET(cpuid)]->res;
+ return (bus_read_8(rdist, offset));
}
void
gic_r_write_4(device_t dev, bus_size_t offset, uint32_t val)
{
struct gic_v3_softc *sc;
+ struct resource *rdist;
sc = device_get_softc(dev);
- bus_write_4(sc->gic_redists.pcpu[PCPU_GET(cpuid)], offset, val);
+ rdist = >gic_redists.pcpu[PCPU_GET(cpuid)]->res;
+ bus_write_4(rdist, offset, val);
}
void
gic_r_write_8(device_t dev, bus_size_t offset, uint64_t val)
{
struct gic_v3_softc *sc;
+ struct resource *rdist;
sc = device_get_softc(dev);
- bus_write_8(sc->gic_redists.pcpu[PCPU_GET(cpuid)], offset, val);
+ rdist = >gic_redists.pcpu[PCPU_GET(cpuid)]->res;
+ bus_write_8(rdist, offset, val);
}
/*
@@ -384,8 +392,11 @@ gic_v3_read_ivar(device_t dev, device_t child, int whi
return (0);
case GICV3_IVAR_REDIST_VADDR:
*result = (uintptr_t)rman_get_virtual(
- sc->gic_redists.pcpu[PCPU_GET(cpuid)]);
+ >gic_redists.pcpu[PCPU_GET(cpuid)]->res);
return (0);
+ case GICV3_IVAR_REDIST:
+ *result = (uintptr_t)sc->gic_redists.pcpu[PCPU_GET(cpuid)];
+ return (0);
case GIC_IVAR_HW_REV:
KASSERT(
GICR_PIDR2_ARCH(sc->gic_pidr2) == GICR_PIDR2_ARCH_GICv3 ||
@@ -979,7 +990,7 @@ gic_v3_wait_for_rwp(struct gic_v3_softc *sc, enum gic_
res = sc->gic_dist;
break;
case REDIST:
- res = sc->gic_redists.pcpu[cpuid];
+ res = >gic_redists.pcpu[cpuid]->res;
break;
default:
KASSERT(0, ("%s: Attempt to wait for unknown RWP",
svn commit: r352500 - stable/12/sys/arm64/acpica
Author: jchandra
Date: Wed Sep 18 23:18:26 2019
New Revision: 352500
URL: https://svnweb.freebsd.org/changeset/base/352500
Log:
MFC r349348:
arm64 acpi_iort: add some error handling
Print warnings for some bad kernel configurations (like NUMA disabled
with multiple domains). Check and report some firmware errors (like
incorrect proximity domain entries).
Differential Revision:https://reviews.freebsd.org/D20416
Modified:
stable/12/sys/arm64/acpica/acpi_iort.c
Directory Properties:
stable/12/ (props changed)
Modified: stable/12/sys/arm64/acpica/acpi_iort.c
==
--- stable/12/sys/arm64/acpica/acpi_iort.c Wed Sep 18 23:12:07 2019
(r352499)
+++ stable/12/sys/arm64/acpica/acpi_iort.c Wed Sep 18 23:18:26 2019
(r352500)
@@ -370,19 +370,44 @@ srat_resolve_its_pxm(ACPI_SUBTABLE_HEADER *entry, void
ACPI_SRAT_GIC_ITS_AFFINITY *gicits;
struct iort_node *its_node;
struct iort_its_entry *its_entry;
- int i, matches;
+ int *map_counts;
+ int i, matches, dom;
if (entry->Type != ACPI_SRAT_TYPE_GIC_ITS_AFFINITY)
return;
matches = 0;
+ map_counts = arg;
gicits = (ACPI_SRAT_GIC_ITS_AFFINITY *)entry;
+ dom = acpi_map_pxm_to_vm_domainid(gicits->ProximityDomain);
+
+ /*
+* Catch firmware and config errors. map_counts keeps a
+* count of ProximityDomain values mapping to a domain ID
+*/
+#if MAXMEMDOM > 1
+ if (dom == -1)
+ printf("Firmware Error: Proximity Domain %d could not be"
+ " mapped for GIC ITS ID %d!\n",
+ gicits->ProximityDomain, gicits->ItsId);
+#endif
+ /* use dom + 1 as index to handle the case where dom == -1 */
+ i = ++map_counts[dom + 1];
+ if (i > 1) {
+#ifdef NUMA
+ if (dom != -1)
+ printf("ERROR: Multiple Proximity Domains map to the"
+ " same NUMA domain %d!\n", dom);
+#else
+ printf("WARNING: multiple Proximity Domains in SRAT but NUMA"
+ " NOT enabled!\n");
+#endif
+ }
TAILQ_FOREACH(its_node, _groups, next) {
its_entry = its_node->entries.its;
for (i = 0; i < its_node->nentries; i++, its_entry++) {
if (its_entry->its_id == gicits->ItsId) {
- its_entry->pxm = acpi_map_pxm_to_vm_domainid(
- gicits->ProximityDomain);
+ its_entry->pxm = dom;
matches++;
}
}
@@ -401,6 +426,7 @@ iort_post_process_its(void)
ACPI_TABLE_MADT *madt;
ACPI_TABLE_SRAT *srat;
vm_paddr_t madt_pa, srat_pa;
+ int map_counts[MAXMEMDOM + 1] = { 0 };
/* Check ITS block in MADT */
madt_pa = acpi_find_table(ACPI_SIG_MADT);
@@ -417,7 +443,7 @@ iort_post_process_its(void)
srat = acpi_map_table(srat_pa, ACPI_SIG_SRAT);
KASSERT(srat != NULL, ("can't map SRAT!"));
acpi_walk_subtables(srat + 1, (char *)srat +
srat->Header.Length,
- srat_resolve_its_pxm, NULL);
+ srat_resolve_its_pxm, map_counts);
acpi_unmap_table(srat);
}
return (0);
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svn commit: r352499 - stable/12/sys/arm64/arm64
Author: jchandra
Date: Wed Sep 18 23:12:07 2019
New Revision: 352499
URL: https://svnweb.freebsd.org/changeset/base/352499
Log:
MFC r348291:
arm64 nexus: remove incorrect warning
acpi_config_intr() will be called when an arm64 system booted with ACPI.
We do the interrupt mapping for ACPI interrupts in nexus_acpi_map_intr()
on arm64, so acpi_config_intr() has to just return success without
printing this error message.
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D19432
Modified:
stable/12/sys/arm64/arm64/nexus.c
Directory Properties:
stable/12/ (props changed)
Modified: stable/12/sys/arm64/arm64/nexus.c
==
--- stable/12/sys/arm64/arm64/nexus.c Wed Sep 18 23:08:51 2019
(r352498)
+++ stable/12/sys/arm64/arm64/nexus.c Wed Sep 18 23:12:07 2019
(r352499)
@@ -292,9 +292,11 @@ nexus_config_intr(device_t dev, int irq, enum intr_tri
enum intr_polarity pol)
{
- /* TODO: This is wrong, it's needed for ACPI */
- device_printf(dev, "bus_config_intr is obsolete and not supported!\n");
- return (EOPNOTSUPP);
+ /*
+* On arm64 (due to INTRNG), ACPI interrupt configuration is
+* done in nexus_acpi_map_intr().
+*/
+ return (0);
}
static int
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svn commit: r352498 - in stable/12/sys: arm64/acpica arm64/arm64 conf dev/acpica dev/pci
Author: jchandra
Date: Wed Sep 18 23:08:51 2019
New Revision: 352498
URL: https://svnweb.freebsd.org/changeset/base/352498
Log:
MFC r343853, r343856, r343860
r343853:
arm64 acpi: Add support for IORT table
Add new file arm64/acpica/acpi_iort.c to support the "IO Remapping
Table" (IORT). The table is specified in ARM document "ARM DEN 0049D"
titled "IO Remapping Table Platform Design Document". The IORT table
has information on the associations between PCI root complexes, SMMU
blocks and GIC ITS blocks in the system.
The changes are to parse and save the information in the IORT table.
The API to use this information is added to sys/dev/acpica/acpivar.h.
The acpi_iort.c also has code to check the GIC ITS nodes seen in the
IORT table with corresponding entries in MADT table (for validity)
and with entries in SRAT table (for proximity information).
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D18002
r343856:
arm64 gicv3: add IORT and NUMA support
acpi_iort.c has added support to query GIC proximity and MSI XREF
ID for GIC ITS blocks. Use this when GIC ITS blocks are initialized
from ACPI.
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D18003
r343860:
pci_host_generic_acpi: use IORT data for MSI/MSI-X
Use the information from IORT parsing to translate the PCI RID to
GIC ITS device ID. And similarly, use the information to find the
PIC XREF identifier to be used for PCI devices.
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D18004
Added:
stable/12/sys/arm64/acpica/acpi_iort.c
- copied unchanged from r343853, head/sys/arm64/acpica/acpi_iort.c
Modified:
stable/12/sys/arm64/arm64/gic_v3_acpi.c
stable/12/sys/arm64/arm64/gic_v3_var.h
stable/12/sys/arm64/arm64/gicv3_its.c
stable/12/sys/conf/files.arm64
stable/12/sys/dev/acpica/acpivar.h
stable/12/sys/dev/pci/pci_host_generic_acpi.c
Directory Properties:
stable/12/ (props changed)
Copied: stable/12/sys/arm64/acpica/acpi_iort.c (from r343853,
head/sys/arm64/acpica/acpi_iort.c)
==
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ stable/12/sys/arm64/acpica/acpi_iort.c Wed Sep 18 23:08:51 2019
(r352498, copy of r343853, head/sys/arm64/acpica/acpi_iort.c)
@@ -0,0 +1,502 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * Author: Jayachandran C Nair
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "opt_acpi.h"
+
+#include
+__FBSDID("$FreeBSD$");
+
+#include
+#include
+#include
+#include
+
+#include
+
+#include
+#include
+#include
+
+#include
+
+/*
+ * Track next XREF available for ITS groups.
+ */
+static u_int acpi_its_xref = ACPI_MSI_XREF;
+
+/*
+ * Some types of IORT nodes have a set of mappings. Each of them map
+ * a range of device IDs [base..end] from the current node to another
+ * node. The corresponding device IDs on destination node starts at
+ * outbase.
+ */
+struct iort_map_entry {
+ u_int base;
+ u_int end;
+ u_int outbase;
+ u_int flags;
+ u_int out_node_offset;
+ struct iort_node*out_node;
+};
+
+/*
+ * The ITS group node does not have any outgoing mappings. It has a
+ * of a list of GIC ITS blocks which can handle the device ID. We
+ * will store the PIC XREF used by the block and the blocks proximity
+ * data here,
svn commit: r352497 - in stable/12/sys: arm64/acpica arm64/arm64 conf dev/acpica
Author: jchandra
Date: Wed Sep 18 22:55:24 2019
New Revision: 352497
URL: https://svnweb.freebsd.org/changeset/base/352497
Log:
MFC r341743-r341744
r341743:
acpica: support parsing of arm64 affinity in acpi_pxm.c
ACPI SRAT table on arm64 uses GICC entries to provide CPU locality
information. These entries use an AcpiProcessorUid to identify the
CPU (unlike on x86 where the entries have an APIC ID).
Update acpi_pxm.c to extend the cpu_add/cpu_find/cpu_get_info
functions to handle AcpiProcessorUid. Use the updated functions
while parsing ACPI_SRAT_GICC_AFFINITY entry for arm64.
Also update sys/conf/files.arm64 to build acpi_pxm.c when ACPI is
enabled.
Reviewed by: markj (previous version)
Differential Revision:https://reviews.freebsd.org/D17942
r341744:
arm64: add ACPI based NUMA support
Use the newly defined SRAT/SLIT parsing APIs in arm64 to support
ACPI based NUMA.
Reviewed by: markj
Modified:
stable/12/sys/arm64/acpica/acpi_machdep.c
stable/12/sys/arm64/arm64/mp_machdep.c
stable/12/sys/conf/files.arm64
stable/12/sys/dev/acpica/acpi_pxm.c
Directory Properties:
stable/12/ (props changed)
Modified: stable/12/sys/arm64/acpica/acpi_machdep.c
==
--- stable/12/sys/arm64/acpica/acpi_machdep.c Wed Sep 18 22:44:59 2019
(r352496)
+++ stable/12/sys/arm64/acpica/acpi_machdep.c Wed Sep 18 22:55:24 2019
(r352497)
@@ -233,3 +233,16 @@ acpi_map_addr(struct acpi_generic_address *addr, bus_s
return (bus_space_map(*tag, phys, size, 0, handle));
}
+
+#if MAXMEMDOM > 1
+static void
+parse_pxm_tables(void *dummy)
+{
+
+ acpi_pxm_init(MAXCPU, (vm_paddr_t)1 << 40);
+ acpi_pxm_parse_tables();
+ acpi_pxm_set_mem_locality();
+}
+SYSINIT(parse_pxm_tables, SI_SUB_VM - 1, SI_ORDER_FIRST, parse_pxm_tables,
+NULL);
+#endif
Modified: stable/12/sys/arm64/arm64/mp_machdep.c
==
--- stable/12/sys/arm64/arm64/mp_machdep.c Wed Sep 18 22:44:59 2019
(r352496)
+++ stable/12/sys/arm64/arm64/mp_machdep.c Wed Sep 18 22:55:24 2019
(r352497)
@@ -520,13 +520,15 @@ madt_handler(ACPI_SUBTABLE_HEADER *entry, void *arg)
{
ACPI_MADT_GENERIC_INTERRUPT *intr;
u_int *cpuid;
+ u_int id;
switch(entry->Type) {
case ACPI_MADT_TYPE_GENERIC_INTERRUPT:
intr = (ACPI_MADT_GENERIC_INTERRUPT *)entry;
cpuid = arg;
-
- start_cpu((*cpuid), intr->ArmMpidr);
+ id = *cpuid;
+ start_cpu(id, intr->ArmMpidr);
+ __pcpu[id].pc_acpi_id = intr->Uid;
(*cpuid)++;
break;
default:
@@ -556,6 +558,12 @@ cpu_init_acpi(void)
madt_handler, );
acpi_unmap_table(madt);
+
+#if MAXMEMDOM > 1
+ /* set proximity info */
+ acpi_pxm_set_cpu_locality();
+ acpi_pxm_free();
+#endif
}
#endif
Modified: stable/12/sys/conf/files.arm64
==
--- stable/12/sys/conf/files.arm64 Wed Sep 18 22:44:59 2019
(r352496)
+++ stable/12/sys/conf/files.arm64 Wed Sep 18 22:55:24 2019
(r352497)
@@ -203,6 +203,7 @@ dev/acpica/acpi_bus_if.moptionalacpi
dev/acpica/acpi_if.m optionalacpi
dev/acpica/acpi_pci_link.c optionalacpi pci
dev/acpica/acpi_pcib.c optionalacpi pci
+dev/acpica/acpi_pxm.c optionalacpi
dev/ahci/ahci_generic.coptionalahci
dev/axgbe/if_axgbe.c optionalaxgbe
dev/axgbe/xgbe-desc.c optionalaxgbe
Modified: stable/12/sys/dev/acpica/acpi_pxm.c
==
--- stable/12/sys/dev/acpica/acpi_pxm.c Wed Sep 18 22:44:59 2019
(r352496)
+++ stable/12/sys/dev/acpica/acpi_pxm.c Wed Sep 18 22:55:24 2019
(r352497)
@@ -59,6 +59,7 @@ static struct cpu_info {
int enabled:1;
int has_memory:1;
int domain;
+ int id;
} *cpus;
static int max_cpus;
@@ -182,14 +183,33 @@ overlaps_phys_avail(vm_paddr_t start, vm_paddr_t end)
}
/*
- * Find CPU by processor ID (APIC ID on x86).
+ * On x86 we can use the cpuid to index the cpus array, but on arm64
+ * we have an ACPI Processor UID with a larger range.
+ *
+ * Use this variable to indicate if the cpus can be stored by index.
*/
+#ifdef __aarch64__
+static const int cpus_use_indexing = 0;
+#else
+static const int cpus_use_indexing = 1;
+#endif
+
+/*
+ * Find CPU by processor ID (APIC ID on x86, Processor UID on arm64)
+ */
static struct cpu_info *
cpu_find(int cpuid)
{
+ int i;
- if (cpuid <= last_cpu && cpus[cpuid].enabled)
- return ([cpuid]);
+ if (cpus_use_indexing) {
+
svn commit: r352496 - in stable/12/sys: conf dev/acpica x86/acpica
Author: jchandra
Date: Wed Sep 18 22:44:59 2019
New Revision: 352496
URL: https://svnweb.freebsd.org/changeset/base/352496
Log:
MFC r341741-r341742
r341741:
x86/acpica/srat.c: Add API for parsing proximity tables
The SLIT and SRAT ACPI tables needs to be parsed on arm64 as well, on
systems that use UEFI/ACPI firmware and support NUMA. To do this, we
need to move most of the logic of x86/acpica/srat.c to dev/acpica and
provide an API that architectures can use to parse and configure ACPI
NUMA information.
This commit adds the API in srat.c as a first step, without making any
functional changes. We will move the common code to sys/dev/acpica
as the next step.
The functions added are:
* int acpi_pxm_init(int ncpus, vm_paddr_t maxphys) - to allocate and
initialize data structures used
* void acpi_pxm_parse_tables(void) - parse SRAT/SLIT, save the cpu and
memory proximity information
* void acpi_pxm_set_mem_locality(void) - use the saved data to set
memory locality
* void acpi_pxm_set_cpu_locality(void) - use the saved data to set cpu
locality
* void acpi_pxm_free(void) - free data structures allocated by init
On arm64, we do not have an cpu APIC id that can be used as index to
store CPU data, we need to use the Processor Uid. To help with this,
define internal functions cpu_add, cpu_find, cpu_get_info to store
and get CPU proximity information.
Reviewed by: markj, jhb (previous version)
Differential Revision:https://reviews.freebsd.org/D17940
r341742:
acpica : move SRAT/SLIT parsing to sys/dev/acpica
This moves the architecture independent parts of sys/x86/acpica/srat.c
to sys/dev/acpica/acpi_pxm.c, to be used later on arm64. The function
declarations are moved to sys/dev/acpica/acpivar.h
We also need to update sys/conf/files.{i386,amd64} to use the new file.
No functional changes.
Reviewed by: markj, imp
Differential Revision:https://reviews.freebsd.org/D17941
Added:
stable/12/sys/dev/acpica/acpi_pxm.c
- copied unchanged from r341742, head/sys/dev/acpica/acpi_pxm.c
Modified:
stable/12/sys/conf/files.amd64
stable/12/sys/conf/files.i386
stable/12/sys/dev/acpica/acpivar.h
stable/12/sys/x86/acpica/srat.c
Directory Properties:
stable/12/ (props changed)
Modified: stable/12/sys/conf/files.amd64
==
--- stable/12/sys/conf/files.amd64 Wed Sep 18 21:00:32 2019
(r352495)
+++ stable/12/sys/conf/files.amd64 Wed Sep 18 22:44:59 2019
(r352496)
@@ -208,6 +208,7 @@ dev/acpica/acpi_pci_link.c optional acpi pci
dev/acpica/acpi_pcib.c optional acpi pci
dev/acpica/acpi_pcib_acpi.coptional acpi pci
dev/acpica/acpi_pcib_pci.c optional acpi pci
+dev/acpica/acpi_pxm.c optionalacpi
dev/acpica/acpi_timer.coptionalacpi
dev/acpi_support/acpi_wmi_if.m standard
dev/agp/agp_amd64.coptionalagp
Modified: stable/12/sys/conf/files.i386
==
--- stable/12/sys/conf/files.i386 Wed Sep 18 21:00:32 2019
(r352495)
+++ stable/12/sys/conf/files.i386 Wed Sep 18 22:44:59 2019
(r352496)
@@ -342,6 +342,7 @@ dev/vmware/vmci/vmci_resource.c optional
vmci
dev/acpica/acpi_if.m standard
dev/acpica/acpi_hpet.c optional acpi
dev/acpica/acpi_timer.coptional acpi
+dev/acpica/acpi_pxm.c optional acpi
dev/acpi_support/acpi_wmi_if.m standard
dev/wbwd/wbwd.coptional wbwd
dev/isci/isci.c
optional isci
Copied: stable/12/sys/dev/acpica/acpi_pxm.c (from r341742,
head/sys/dev/acpica/acpi_pxm.c)
==
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ stable/12/sys/dev/acpica/acpi_pxm.c Wed Sep 18 22:44:59 2019
(r352496, copy of r341742, head/sys/dev/acpica/acpi_pxm.c)
@@ -0,0 +1,649 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright (c) 2010 Hudson River Trading LLC
+ * Written by: John H. Baldwin
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES,
svn commit: r352473 - stable/12/sys/arm64/arm64
Author: jchandra
Date: Wed Sep 18 07:22:37 2019
New Revision: 352473
URL: https://svnweb.freebsd.org/changeset/base/352473
Log:
MFC r340602:
gitv3_its: fixes for multiple GIC ITS blocks
First pass of support for multiple GIC ITS blocks with ACPI.
Changes are to:
* register the correct subset of interrupts with pic_register
in case of ACPI.
* initialize just the cpu interface for the first ITS, when
domain information is not avialable. This has to be done
until we split the per-CPU init to do LPI setup just once.
* remove duplicate check for the GIC ITS domain, the sc_cpus
are setup from domain, so the check again in per-CPU init
seems unnecessary.
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D17841
Modified:
stable/12/sys/arm64/arm64/gicv3_its.c
Directory Properties:
stable/12/ (props changed)
Modified: stable/12/sys/arm64/arm64/gicv3_its.c
==
--- stable/12/sys/arm64/arm64/gicv3_its.c Wed Sep 18 07:21:08 2019
(r352472)
+++ stable/12/sys/arm64/arm64/gicv3_its.c Wed Sep 18 07:22:37 2019
(r352473)
@@ -580,18 +580,11 @@ its_init_cpu(device_t dev, struct gicv3_its_softc *sc)
uint64_t xbaser, tmp;
uint32_t ctlr;
u_int cpuid;
- int domain;
- if (!CPU_ISSET(PCPU_GET(cpuid), >sc_cpus))
- return (0);
-
- if (bus_get_domain(dev, ) == 0) {
- if (PCPU_GET(domain) != domain)
- return (0);
- }
-
gicv3 = device_get_parent(dev);
cpuid = PCPU_GET(cpuid);
+ if (!CPU_ISSET(cpuid, >sc_cpus))
+ return (0);
/* Check if the ITS is enabled on this CPU */
if ((gic_r_read_4(gicv3, GICR_TYPER) & GICR_TYPER_PLPIS) == 0) {
@@ -729,12 +722,14 @@ gicv3_its_attach(device_t dev)
/* Protects access to the ITS command circular buffer. */
mtx_init(>sc_its_cmd_lock, "ITS cmd lock", NULL, MTX_SPIN);
+ CPU_ZERO(>sc_cpus);
if (bus_get_domain(dev, ) == 0) {
- CPU_ZERO(>sc_cpus);
if (domain < MAXMEMDOM)
CPU_COPY(_domain[domain], >sc_cpus);
} else {
- CPU_COPY(_cpus, >sc_cpus);
+ /* XXX : cannot handle more than one ITS per cpu */
+ if (device_get_unit(dev) == 0)
+ CPU_COPY(_cpus, >sc_cpus);
}
/* Allocate the command circular buffer */
@@ -1737,7 +1732,7 @@ gicv3_its_acpi_attach(device_t dev)
sc->sc_pic = intr_pic_register(dev,
device_get_unit(dev) + ACPI_MSI_XREF);
intr_pic_add_handler(device_get_parent(dev), sc->sc_pic,
- gicv3_its_intr, sc, GIC_FIRST_LPI, LPI_NIRQS);
+ gicv3_its_intr, sc, sc->sc_irq_base, sc->sc_irq_length);
/* Register this device to handle MSI interrupts */
intr_msi_register(dev, device_get_unit(dev) + ACPI_MSI_XREF);
___
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svn commit: r352471 - in stable/12/sys/dev: acpica pci
Author: jchandra
Date: Wed Sep 18 07:16:00 2019
New Revision: 352471
URL: https://svnweb.freebsd.org/changeset/base/352471
Log:
MFC r340599-r340601
r340599:
acpica, pci_host_generic_acpi: redo pci_host_generic_acpi.c
This is a major update for pci_host_generic_acpi.c, the current
implementation has some gaps that are better fixed up in one go.
The changes are to:
* Follow x86 method of not adding PCI resources to PCI host bridge in
ACPI code. This has been moved to pci_host_generic_acpi.c, where we
walk thru its resources of the host bridge and add them.
* Fixup code in pci_host_generic_acpi.c to read all decoded ranges
and update the 'ranges' property. This allows us to share most of
the code with generic implementation (and the FDT one).
* Parse and setup IO ranges and bus ranges when walking the resources
above. Drop most of the changes related to this from acpica code.
* Add the ECAM memory area as mem resource 0. Implement the logic to
get the ECAM area from MCFG (using bus range which we now decode),
or from _CBA (using _BBN/bus range). Drop aarch64 ifdefs from acpica
code which did part of this.
* Switch resource activation to similar code as FDT implementation,
this can be moved into generic implementation in a later pass.
* Drop the mechanism of using the 7th bit of bus number as the domain,
this is not correct and will work only in very specific cases. Use
_SEG as PCI domain and use the bus ranges of the host bridge to
provide start bus number.
This commit should not make any functional change to dev/acpica/acpi.c
for other architectures, almost all the changes there are to revert
earlier additions in this file done for aarch64.
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D17791
r340600:
pci_host_generic, acpi_resource: drop unneeded code
Now that we are handling PCI resources in pci_host_generic_acpi.c, we
don't need these change (made by r336129)
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D17792
r340601:
pci_host_generic : move activate/release to generic code
Now that the ACPI and FDT implementations for activating and
deactivating resources are the same, we can move it to
pci_host_generic.c. No functional changes.
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D17793
Modified:
stable/12/sys/dev/acpica/acpi.c
stable/12/sys/dev/acpica/acpi_resource.c
stable/12/sys/dev/pci/pci_host_generic.c
stable/12/sys/dev/pci/pci_host_generic_acpi.c
stable/12/sys/dev/pci/pci_host_generic_fdt.c
Directory Properties:
stable/12/ (props changed)
Modified: stable/12/sys/dev/acpica/acpi.c
==
--- stable/12/sys/dev/acpica/acpi.c Wed Sep 18 07:09:16 2019
(r352470)
+++ stable/12/sys/dev/acpica/acpi.c Wed Sep 18 07:16:00 2019
(r352471)
@@ -179,9 +179,7 @@ static int acpi_child_location_str_method(device_t acd
char *buf, size_t buflen);
static int acpi_child_pnpinfo_str_method(device_t acdev, device_t child,
char *buf, size_t buflen);
-#if defined(__i386__) || defined(__amd64__)
static voidacpi_enable_pcie(void);
-#endif
static voidacpi_hint_device_unit(device_t acdev, device_t child,
const char *name, int *unitp);
static voidacpi_reset_interfaces(device_t dev);
@@ -502,10 +500,8 @@ acpi_attach(device_t dev)
goto out;
}
-#if defined(__i386__) || defined(__amd64__)
/* Handle MCFG table if present. */
acpi_enable_pcie();
-#endif
/*
* Note that some systems (specifically, those with namespace evaluation
@@ -1286,11 +1282,10 @@ acpi_set_resource(device_t dev, device_t child, int ty
struct acpi_softc *sc = device_get_softc(dev);
struct acpi_device *ad = device_get_ivars(child);
struct resource_list *rl = >ad_rl;
-#if defined(__i386__) || defined(__amd64__)
ACPI_DEVICE_INFO *devinfo;
-#endif
rman_res_t end;
-
+int allow;
+
/* Ignore IRQ resources for PCI link devices. */
if (type == SYS_RES_IRQ && ACPI_ID_PROBE(dev, child, pcilink_ids) != NULL)
return (0);
@@ -1304,11 +1299,15 @@ acpi_set_resource(device_t dev, device_t child, int ty
* x86 of a PCI bridge claiming the I/O ports used for PCI config
* access.
*/
-#if defined(__i386__) || defined(__amd64__)
if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) {
if (ACPI_SUCCESS(AcpiGetObjectInfo(ad->ad_handle, ))) {
if ((devinfo->Flags & ACPI_PCI_ROOT_BRIDGE) != 0) {
- if (!(type == SYS_RES_IOPORT && start == CONF1_ADDR_PORT)) {
+#if defined(__i386__) || defined(__amd64__)
+ allow = (type == SYS_RES_IOPORT && start ==
svn commit: r352470 - in stable/12/sys: arm/arm dev/acpica
Author: jchandra
Date: Wed Sep 18 07:09:16 2019
New Revision: 352470
URL: https://svnweb.freebsd.org/changeset/base/352470
Log:
MFC r340598:
acpica: rework INTRNG interrupts
On arm64 (where INTRNG is enabled), the interrupts have to be mapped
with ACPI_BUS_MAP_INTR() before adding them as resources to devices.
The earlier code did the mapping before calling acpi_set_resource(),
which bypassed code that checked for PCI link interrupts.
To fix this, move the call to map interrupts into acpi_set_resource()
and that requires additional work to lookup interrupt properties.
The changes here are to:
* extend acpi_lookup_irq_handler() to lookup an irq in the ACPI
resources
* create a helper function acpi_map_intr() which uses the updated
acpi_lookup_irq_handler() to look up an irq, and then map it
with ACPI_BUS_MAP_INTR()
* use acpi_map_intr() in acpi_pcib_route_interrupt() to map
pci link interrupts.
With these changes, we can drop the ifdefs in acpi_resource.c, and
we can also drop the call for mapping interrupts in generic_timer.c
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D17790
Modified:
stable/12/sys/arm/arm/generic_timer.c
stable/12/sys/dev/acpica/acpi.c
stable/12/sys/dev/acpica/acpi_pcib.c
stable/12/sys/dev/acpica/acpi_resource.c
stable/12/sys/dev/acpica/acpivar.h
Directory Properties:
stable/12/ (props changed)
Modified: stable/12/sys/arm/arm/generic_timer.c
==
--- stable/12/sys/arm/arm/generic_timer.c Wed Sep 18 07:01:01 2019
(r352469)
+++ stable/12/sys/arm/arm/generic_timer.c Wed Sep 18 07:09:16 2019
(r352470)
@@ -72,7 +72,6 @@ __FBSDID("$FreeBSD$");
#ifdef DEV_ACPI
#include
#include
-#include "acpi_bus_if.h"
#endif
#defineGT_CTRL_ENABLE (1 << 0)
@@ -340,8 +339,6 @@ static void
arm_tmr_acpi_add_irq(device_t parent, device_t dev, int rid, u_int irq)
{
- irq = ACPI_BUS_MAP_INTR(parent, dev, irq,
- INTR_TRIGGER_LEVEL, INTR_POLARITY_HIGH);
BUS_SET_RESOURCE(parent, dev, SYS_RES_IRQ, rid, irq, 1);
}
Modified: stable/12/sys/dev/acpica/acpi.c
==
--- stable/12/sys/dev/acpica/acpi.c Wed Sep 18 07:01:01 2019
(r352469)
+++ stable/12/sys/dev/acpica/acpi.c Wed Sep 18 07:09:16 2019
(r352470)
@@ -1318,6 +1318,13 @@ acpi_set_resource(device_t dev, device_t child, int ty
}
#endif
+#ifdef INTRNG
+/* map with default for now */
+if (type == SYS_RES_IRQ)
+ start = (rman_res_t)acpi_map_intr(child, (u_int)start,
+ acpi_get_handle(child));
+#endif
+
/* If the resource is already allocated, fail. */
if (resource_list_busy(rl, type, rid))
return (EBUSY);
Modified: stable/12/sys/dev/acpica/acpi_pcib.c
==
--- stable/12/sys/dev/acpica/acpi_pcib.cWed Sep 18 07:01:01 2019
(r352469)
+++ stable/12/sys/dev/acpica/acpi_pcib.cWed Sep 18 07:09:16 2019
(r352470)
@@ -188,6 +188,7 @@ acpi_pcib_route_interrupt(device_t pcib, device_t dev,
ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
+lnkdev = NULL;
interrupt = PCI_INVALID_IRQ;
/* ACPI numbers pins 0-3, not 1-4 like the BIOS. */
@@ -252,7 +253,12 @@ acpi_pcib_route_interrupt(device_t pcib, device_t dev,
out:
ACPI_SERIAL_END(pcib);
-
+#ifdef INTRNG
+if (PCI_INTERRUPT_VALID(interrupt)) {
+ interrupt = acpi_map_intr(dev, interrupt, lnkdev);
+ KASSERT(PCI_INTERRUPT_VALID(interrupt), ("mapping fail"));
+}
+#endif
return_VALUE(interrupt);
}
Modified: stable/12/sys/dev/acpica/acpi_resource.c
==
--- stable/12/sys/dev/acpica/acpi_resource.cWed Sep 18 07:01:01 2019
(r352469)
+++ stable/12/sys/dev/acpica/acpi_resource.cWed Sep 18 07:09:16 2019
(r352470)
@@ -55,10 +55,13 @@ ACPI_MODULE_NAME("RESOURCE")
struct lookup_irq_request {
ACPI_RESOURCE *acpi_res;
-struct resource *res;
+u_int irq;
intcounter;
intrid;
intfound;
+intcheckrid;
+inttrig;
+intpol;
};
static ACPI_STATUS
@@ -66,18 +69,22 @@ acpi_lookup_irq_handler(ACPI_RESOURCE *res, void *cont
{
struct lookup_irq_request *req;
size_t len;
-u_int irqnum, irq;
+u_int irqnum, irq, trig, pol;
switch (res->Type) {
case ACPI_RESOURCE_TYPE_IRQ:
irqnum = res->Data.Irq.InterruptCount;
irq = res->Data.Irq.Interrupts[0];
len = ACPI_RS_SIZE(ACPI_RESOURCE_IRQ);
+ trig = res->Data.Irq.Triggering;
+ pol = res->Data.Irq.Polarity;
svn commit: r352468 - stable/12/sys/dev/pci
Author: jchandra
Date: Wed Sep 18 06:50:29 2019
New Revision: 352468
URL: https://svnweb.freebsd.org/changeset/base/352468
Log:
MFC r340595-r340597
r340595:
pci_host_generic: remove unneeded ThunderX2 quirk
The current quirk implementation writes a fixed address to the PCI BAR
to fix a firmware bug. The PCI BARs are allocated by firmware and will
change depending on PCI devices present. So using a fixed address here
is not correct.
This quirk worked around a firmware bug that programmed the MSI-X bar
of the SATA controller incorrectly. The newer firmware does not have
this issue, so it is better to drop this quirk altogether.
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D17655
r340596:
pci_host_generic: allocate resources against devices
Fix up pci_host_generic.c and pci_host_generic_fdt.c to allocate
resources against devices that requested them. Currently the
allocation happens against the pcib, which is incorrect.
This is needed for the upcoming changes for fixing up
pci_host_generic_acpi.c
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D17656
r340597:
pci_host_generic*: basic implementation of bus range
Both ACPI and FDT support bus ranges for pci host bridges. Update
pci_host_generic*.[ch] with a default implementation to support this.
This will be used in the next set of changes for ACPI based host
bridge. No functional changes in this commit.
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D17657
Modified:
stable/12/sys/dev/pci/pci_host_generic.c
stable/12/sys/dev/pci/pci_host_generic.h
stable/12/sys/dev/pci/pci_host_generic_acpi.c
stable/12/sys/dev/pci/pci_host_generic_fdt.c
Directory Properties:
stable/12/ (props changed)
Modified: stable/12/sys/dev/pci/pci_host_generic.c
==
--- stable/12/sys/dev/pci/pci_host_generic.cWed Sep 18 02:04:41 2019
(r352467)
+++ stable/12/sys/dev/pci/pci_host_generic.cWed Sep 18 06:50:29 2019
(r352468)
@@ -69,25 +69,6 @@ __FBSDID("$FreeBSD$");
(((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \
((reg) & PCIE_REG_MASK))
-typedef void (*pci_host_generic_quirk_function)(device_t);
-
-struct pci_host_generic_quirk_entry {
- int impl;
- int part;
- int var;
- int rev;
- pci_host_generic_quirk_function func;
-};
-
-struct pci_host_generic_block_entry {
- int impl;
- int part;
- int var;
- int rev;
- int bus;
- int slot;
-};
-
/* Forward prototypes */
static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
@@ -100,24 +81,6 @@ static int generic_pcie_read_ivar(device_t dev, device
static int generic_pcie_write_ivar(device_t dev, device_t child, int index,
uintptr_t value);
-#if defined(__aarch64__)
-static void pci_host_generic_apply_quirks(device_t);
-static void thunderx2_ahci_bar_quirk(device_t);
-
-struct pci_host_generic_quirk_entry pci_host_generic_quirks[] =
-{
- {CPU_IMPL_CAVIUM, CPU_PART_THUNDERX2, 0, 0, thunderx2_ahci_bar_quirk},
- {0, 0, 0, 0, NULL}
-};
-
-struct pci_host_generic_block_entry pci_host_generic_blocked[] =
-{
- /* ThunderX2 AHCI on second socket */
- {CPU_IMPL_CAVIUM, CPU_PART_THUNDERX2, 0, 0, 0x80, 0x10},
- {0, 0, 0, 0, 0, 0}
-};
-#endif
-
int
pci_host_generic_core_attach(device_t dev)
{
@@ -171,34 +134,9 @@ pci_host_generic_core_attach(device_t dev)
return (error);
}
-#if defined(__aarch64__)
- pci_host_generic_apply_quirks(dev);
-#endif
-
return (0);
}
-#if defined(__aarch64__)
-static void
-pci_host_generic_apply_quirks(device_t dev)
-{
- struct pci_host_generic_quirk_entry *quirk;
-
- quirk = pci_host_generic_quirks;
- while (1) {
- if (quirk->impl == 0)
- break;
-
- if (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK,
- quirk->impl, quirk->part, quirk->var, quirk->rev) &&
- quirk->func != NULL)
- quirk->func(dev);
-
- quirk++;
- }
-}
-#endif
-
static uint32_t
generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
u_int func, u_int reg, int bytes)
@@ -208,32 +146,15 @@ generic_pcie_read_config(device_t dev, u_int bus, u_in
bus_space_tag_t t;
uint64_t offset;
uint32_t data;
-#if defined(__aarch64__)
- struct pci_host_generic_block_entry *block;
-#endif
- if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) ||
- (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))
+ sc = device_get_softc(dev);
+ if ((bus < sc->bus_start) || (bus > sc->bus_end))
return (~0U);
+ if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) ||
+ (reg >
svn commit: r349348 - head/sys/arm64/acpica
Author: jchandra
Date: Mon Jun 24 21:24:55 2019
New Revision: 349348
URL: https://svnweb.freebsd.org/changeset/base/349348
Log:
arm64 acpi_iort: add some error handling
Print warnings for some bad kernel configurations (like NUMA disabled
with multiple domains). Check and report some firmware errors (like
incorrect proximity domain entries).
Differential Revision:https://reviews.freebsd.org/D20416
Modified:
head/sys/arm64/acpica/acpi_iort.c
Modified: head/sys/arm64/acpica/acpi_iort.c
==
--- head/sys/arm64/acpica/acpi_iort.c Mon Jun 24 21:13:45 2019
(r349347)
+++ head/sys/arm64/acpica/acpi_iort.c Mon Jun 24 21:24:55 2019
(r349348)
@@ -370,19 +370,44 @@ srat_resolve_its_pxm(ACPI_SUBTABLE_HEADER *entry, void
ACPI_SRAT_GIC_ITS_AFFINITY *gicits;
struct iort_node *its_node;
struct iort_its_entry *its_entry;
- int i, matches;
+ int *map_counts;
+ int i, matches, dom;
if (entry->Type != ACPI_SRAT_TYPE_GIC_ITS_AFFINITY)
return;
matches = 0;
+ map_counts = arg;
gicits = (ACPI_SRAT_GIC_ITS_AFFINITY *)entry;
+ dom = acpi_map_pxm_to_vm_domainid(gicits->ProximityDomain);
+
+ /*
+* Catch firmware and config errors. map_counts keeps a
+* count of ProximityDomain values mapping to a domain ID
+*/
+#if MAXMEMDOM > 1
+ if (dom == -1)
+ printf("Firmware Error: Proximity Domain %d could not be"
+ " mapped for GIC ITS ID %d!\n",
+ gicits->ProximityDomain, gicits->ItsId);
+#endif
+ /* use dom + 1 as index to handle the case where dom == -1 */
+ i = ++map_counts[dom + 1];
+ if (i > 1) {
+#ifdef NUMA
+ if (dom != -1)
+ printf("ERROR: Multiple Proximity Domains map to the"
+ " same NUMA domain %d!\n", dom);
+#else
+ printf("WARNING: multiple Proximity Domains in SRAT but NUMA"
+ " NOT enabled!\n");
+#endif
+ }
TAILQ_FOREACH(its_node, _groups, next) {
its_entry = its_node->entries.its;
for (i = 0; i < its_node->nentries; i++, its_entry++) {
if (its_entry->its_id == gicits->ItsId) {
- its_entry->pxm = acpi_map_pxm_to_vm_domainid(
- gicits->ProximityDomain);
+ its_entry->pxm = dom;
matches++;
}
}
@@ -401,6 +426,7 @@ iort_post_process_its(void)
ACPI_TABLE_MADT *madt;
ACPI_TABLE_SRAT *srat;
vm_paddr_t madt_pa, srat_pa;
+ int map_counts[MAXMEMDOM + 1] = { 0 };
/* Check ITS block in MADT */
madt_pa = acpi_find_table(ACPI_SIG_MADT);
@@ -417,7 +443,7 @@ iort_post_process_its(void)
srat = acpi_map_table(srat_pa, ACPI_SIG_SRAT);
KASSERT(srat != NULL, ("can't map SRAT!"));
acpi_walk_subtables(srat + 1, (char *)srat +
srat->Header.Length,
- srat_resolve_its_pxm, NULL);
+ srat_resolve_its_pxm, map_counts);
acpi_unmap_table(srat);
}
return (0);
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svn commit: r349347 - head/sys/arm64/arm64
Author: jchandra
Date: Mon Jun 24 21:13:45 2019
New Revision: 349347
URL: https://svnweb.freebsd.org/changeset/base/349347
Log:
arm64 gicv3_its: enable all ITS blocks for a CPU
We now support multiple ITS blocks raising interrupts to a CPU.
Add all available CPUs to the ITS when no NUMA information is
available.
This reverts the check added in r340602, at that tim we did not
suppport multiple ITS blocks for a CPU.
Differential Revision:https://reviews.freebsd.org/D20417
Modified:
head/sys/arm64/arm64/gicv3_its.c
Modified: head/sys/arm64/arm64/gicv3_its.c
==
--- head/sys/arm64/arm64/gicv3_its.cMon Jun 24 21:05:14 2019
(r349346)
+++ head/sys/arm64/arm64/gicv3_its.cMon Jun 24 21:13:45 2019
(r349347)
@@ -747,9 +747,7 @@ gicv3_its_attach(device_t dev)
if (domain < MAXMEMDOM)
CPU_COPY(_domain[domain], >sc_cpus);
} else {
- /* XXX : cannot handle more than one ITS per cpu */
- if (device_get_unit(dev) == 0)
- CPU_COPY(_cpus, >sc_cpus);
+ CPU_COPY(_cpus, >sc_cpus);
}
/* Allocate the command circular buffer */
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svn commit: r349345 - head/sys/arm64/arm64
Author: jchandra Date: Mon Jun 24 21:00:28 2019 New Revision: 349345 URL: https://svnweb.freebsd.org/changeset/base/349345 Log: arm64 gic: Drop unused GICV3_IVAR_REDIST_VADDR Now that GICV3_IVAR_REDIST is available, GICV3_IVAR_REDIST_VADDR is unused and can be removed. Drop the define and add a comment. Reviewed by: andrew Differential Revision:https://reviews.freebsd.org/D20454 Modified: head/sys/arm64/arm64/gic_v3.c head/sys/arm64/arm64/gic_v3_var.h Modified: head/sys/arm64/arm64/gic_v3.c == --- head/sys/arm64/arm64/gic_v3.c Mon Jun 24 20:52:21 2019 (r349344) +++ head/sys/arm64/arm64/gic_v3.c Mon Jun 24 21:00:28 2019 (r349345) @@ -390,10 +390,6 @@ gic_v3_read_ivar(device_t dev, device_t child, int whi case GICV3_IVAR_NIRQS: *result = (NIRQ - sc->gic_nirqs) / sc->gic_nchildren; return (0); - case GICV3_IVAR_REDIST_VADDR: - *result = (uintptr_t)rman_get_virtual( - >gic_redists.pcpu[PCPU_GET(cpuid)]->res); - return (0); case GICV3_IVAR_REDIST: *result = (uintptr_t)sc->gic_redists.pcpu[PCPU_GET(cpuid)]; return (0); Modified: head/sys/arm64/arm64/gic_v3_var.h == --- head/sys/arm64/arm64/gic_v3_var.h Mon Jun 24 20:52:21 2019 (r349344) +++ head/sys/arm64/arm64/gic_v3_var.h Mon Jun 24 21:00:28 2019 (r349345) @@ -94,11 +94,10 @@ MALLOC_DECLARE(M_GIC_V3); /* ivars */ #defineGICV3_IVAR_NIRQS1000 -#defineGICV3_IVAR_REDIST_VADDR 1001 +/* 1001 was GICV3_IVAR_REDIST_VADDR */ #defineGICV3_IVAR_REDIST 1002 __BUS_ACCESSOR(gicv3, nirqs, GICV3, NIRQS, u_int); -__BUS_ACCESSOR(gicv3, redist_vaddr, GICV3, REDIST_VADDR, void *); __BUS_ACCESSOR(gicv3, redist, GICV3, REDIST, void *); /* Device methods */ ___ svn-src-all@freebsd.org mailing list https://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscr...@freebsd.org"
svn commit: r348380 - head/sys/arm64/arm64
Author: jchandra
Date: Thu May 30 01:39:07 2019
New Revision: 348380
URL: https://svnweb.freebsd.org/changeset/base/348380
Log:
arm64 gicv3_its: Fix a typo
Fix 'Cavium' spelling in errata description.
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D20418
Modified:
head/sys/arm64/arm64/gicv3_its.c
Modified: head/sys/arm64/arm64/gicv3_its.c
==
--- head/sys/arm64/arm64/gicv3_its.cThu May 30 01:32:00 2019
(r348379)
+++ head/sys/arm64/arm64/gicv3_its.cThu May 30 01:39:07 2019
(r348380)
@@ -274,7 +274,7 @@ static const struct {
} its_quirks[] = {
{
/* Cavium ThunderX Pass 1.x */
- .desc = "Cavoum ThunderX errata: 22375, 24313",
+ .desc = "Cavium ThunderX errata: 22375, 24313",
.iidr = GITS_IIDR_RAW(GITS_IIDR_IMPL_CAVIUM,
GITS_IIDR_PROD_THUNDER, GITS_IIDR_VAR_THUNDER_1, 0),
.iidr_mask = ~GITS_IIDR_REVISION_MASK,
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svn commit: r348379 - head/sys/arm64/arm64
Author: jchandra
Date: Thu May 30 01:32:00 2019
New Revision: 348379
URL: https://svnweb.freebsd.org/changeset/base/348379
Log:
gicv3_its: do LPI init only once per CPU
The initialization required for LPIs (setting up pending tables etc.)
has to be done just once per CPU, even in the case where there are
multiple ITS blocks associated with the CPU.
Add a flag lpi_enabled in the per-cpu distributor info for this and
use it to ensure that we call its_init_cpu_lpi() just once.
This enables us to support platforms where multiple GIC ITS blocks
can generate LPIs to a CPU.
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D19844
Modified:
head/sys/arm64/arm64/gic_v3.c
head/sys/arm64/arm64/gic_v3_var.h
head/sys/arm64/arm64/gicv3_its.c
Modified: head/sys/arm64/arm64/gic_v3.c
==
--- head/sys/arm64/arm64/gic_v3.c Thu May 30 01:24:47 2019
(r348378)
+++ head/sys/arm64/arm64/gic_v3.c Thu May 30 01:32:00 2019
(r348379)
@@ -1185,6 +1185,7 @@ gic_v3_redist_find(struct gic_v3_softc *sc)
("Invalid pointer to per-CPU
redistributor"));
/* Copy res contents to its final destination */
sc->gic_redists.pcpu[cpuid]->res = r_res;
+ sc->gic_redists.pcpu[cpuid]->lpi_enabled =
false;
if (bootverbose) {
device_printf(sc->dev,
"CPU%u Re-Distributor has been
found\n",
Modified: head/sys/arm64/arm64/gic_v3_var.h
==
--- head/sys/arm64/arm64/gic_v3_var.h Thu May 30 01:24:47 2019
(r348378)
+++ head/sys/arm64/arm64/gic_v3_var.h Thu May 30 01:32:00 2019
(r348379)
@@ -41,8 +41,9 @@ DECLARE_CLASS(gic_v3_driver);
struct gic_v3_irqsrc;
struct redist_pcpu {
- struct resource res;
+ struct resource res;/* mem resource for redist */
vm_offset_t pend_base;
+ boollpi_enabled;/* redist LPI configured? */
};
struct gic_redists {
Modified: head/sys/arm64/arm64/gicv3_its.c
==
--- head/sys/arm64/arm64/gicv3_its.cThu May 30 01:24:47 2019
(r348378)
+++ head/sys/arm64/arm64/gicv3_its.cThu May 30 01:32:00 2019
(r348379)
@@ -672,11 +672,16 @@ its_init_cpu(device_t dev, struct gicv3_its_softc *sc)
if ((gic_r_read_4(gicv3, GICR_TYPER) & GICR_TYPER_PLPIS) == 0)
return (ENXIO);
- its_init_cpu_lpi(dev, sc);
+ rpcpu = gicv3_get_redist(dev);
+ /* Do per-cpu LPI init once */
+ if (!rpcpu->lpi_enabled) {
+ its_init_cpu_lpi(dev, sc);
+ rpcpu->lpi_enabled = true;
+ }
+
if ((gic_its_read_8(sc, GITS_TYPER) & GITS_TYPER_PTA) != 0) {
/* This ITS wants the redistributor physical address */
- rpcpu = gicv3_get_redist(dev);
target = vtophys(rman_get_virtual(>res));
} else {
/* This ITS wants the unique processor number */
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svn commit: r348378 - head/sys/arm64/arm64
Author: jchandra
Date: Thu May 30 01:24:47 2019
New Revision: 348378
URL: https://svnweb.freebsd.org/changeset/base/348378
Log:
gicv3_its: refactor LPI init into a new function
Move the per-cpu LPI intialization to a separate function. This is
in preparation for a commit that does LPI init only once for a CPU,
even when there are multiple ITS blocks associated with the CPU.
No functional changes in this commit.
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D19843
Modified:
head/sys/arm64/arm64/gicv3_its.c
Modified: head/sys/arm64/arm64/gicv3_its.c
==
--- head/sys/arm64/arm64/gicv3_its.cThu May 30 01:21:08 2019
(r348377)
+++ head/sys/arm64/arm64/gicv3_its.cThu May 30 01:24:47 2019
(r348378)
@@ -574,26 +574,17 @@ gicv3_its_pendtables_init(struct gicv3_its_softc *sc)
}
}
-static int
-its_init_cpu(device_t dev, struct gicv3_its_softc *sc)
+static void
+its_init_cpu_lpi(device_t dev, struct gicv3_its_softc *sc)
{
- struct redist_pcpu *rpcpu;
device_t gicv3;
- vm_paddr_t target;
uint64_t xbaser, tmp;
uint32_t ctlr;
u_int cpuid;
gicv3 = device_get_parent(dev);
cpuid = PCPU_GET(cpuid);
- if (!CPU_ISSET(cpuid, >sc_cpus))
- return (0);
- /* Check if the ITS is enabled on this CPU */
- if ((gic_r_read_4(gicv3, GICR_TYPER) & GICR_TYPER_PLPIS) == 0) {
- return (ENXIO);
- }
-
/* Disable LPIs */
ctlr = gic_r_read_4(gicv3, GICR_CTLR);
ctlr &= ~GICR_CTLR_LPI_ENABLE;
@@ -662,6 +653,26 @@ its_init_cpu(device_t dev, struct gicv3_its_softc *sc)
/* Make sure the GIC has seen everything */
dsb(sy);
+}
+
+static int
+its_init_cpu(device_t dev, struct gicv3_its_softc *sc)
+{
+ device_t gicv3;
+ vm_paddr_t target;
+ u_int cpuid;
+ struct redist_pcpu *rpcpu;
+
+ gicv3 = device_get_parent(dev);
+ cpuid = PCPU_GET(cpuid);
+ if (!CPU_ISSET(cpuid, >sc_cpus))
+ return (0);
+
+ /* Check if the ITS is enabled on this CPU */
+ if ((gic_r_read_4(gicv3, GICR_TYPER) & GICR_TYPER_PLPIS) == 0)
+ return (ENXIO);
+
+ its_init_cpu_lpi(dev, sc);
if ((gic_its_read_8(sc, GITS_TYPER) & GITS_TYPER_PTA) != 0) {
/* This ITS wants the redistributor physical address */
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svn commit: r348377 - head/sys/arm64/arm64
Author: jchandra
Date: Thu May 30 01:21:08 2019
New Revision: 348377
URL: https://svnweb.freebsd.org/changeset/base/348377
Log:
gic_v3: consolidate per-cpu redistributor information
Update 'struct gic_redists' to consolidate all per-cpu redistributor
information into a new 'struct redist_pcpu'. Provide a new interface
(GICV3_IVAR_REDIST) for the GIC driver, which can be used to retrieve
the per-cpu data.
This per-cpu redistributor struct will be later used to improve the
GIC ITS setup.
While there, remove some unused fields in gic_v3_var.h interface.
No functional changes.
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D19842
Modified:
head/sys/arm64/arm64/gic_v3.c
head/sys/arm64/arm64/gic_v3_var.h
head/sys/arm64/arm64/gicv3_its.c
Modified: head/sys/arm64/arm64/gic_v3.c
==
--- head/sys/arm64/arm64/gic_v3.c Wed May 29 23:50:31 2019
(r348376)
+++ head/sys/arm64/arm64/gic_v3.c Thu May 30 01:21:08 2019
(r348377)
@@ -183,36 +183,44 @@ uint32_t
gic_r_read_4(device_t dev, bus_size_t offset)
{
struct gic_v3_softc *sc;
+ struct resource *rdist;
sc = device_get_softc(dev);
- return (bus_read_4(sc->gic_redists.pcpu[PCPU_GET(cpuid)], offset));
+ rdist = >gic_redists.pcpu[PCPU_GET(cpuid)]->res;
+ return (bus_read_4(rdist, offset));
}
uint64_t
gic_r_read_8(device_t dev, bus_size_t offset)
{
struct gic_v3_softc *sc;
+ struct resource *rdist;
sc = device_get_softc(dev);
- return (bus_read_8(sc->gic_redists.pcpu[PCPU_GET(cpuid)], offset));
+ rdist = >gic_redists.pcpu[PCPU_GET(cpuid)]->res;
+ return (bus_read_8(rdist, offset));
}
void
gic_r_write_4(device_t dev, bus_size_t offset, uint32_t val)
{
struct gic_v3_softc *sc;
+ struct resource *rdist;
sc = device_get_softc(dev);
- bus_write_4(sc->gic_redists.pcpu[PCPU_GET(cpuid)], offset, val);
+ rdist = >gic_redists.pcpu[PCPU_GET(cpuid)]->res;
+ bus_write_4(rdist, offset, val);
}
void
gic_r_write_8(device_t dev, bus_size_t offset, uint64_t val)
{
struct gic_v3_softc *sc;
+ struct resource *rdist;
sc = device_get_softc(dev);
- bus_write_8(sc->gic_redists.pcpu[PCPU_GET(cpuid)], offset, val);
+ rdist = >gic_redists.pcpu[PCPU_GET(cpuid)]->res;
+ bus_write_8(rdist, offset, val);
}
/*
@@ -384,8 +392,11 @@ gic_v3_read_ivar(device_t dev, device_t child, int whi
return (0);
case GICV3_IVAR_REDIST_VADDR:
*result = (uintptr_t)rman_get_virtual(
- sc->gic_redists.pcpu[PCPU_GET(cpuid)]);
+ >gic_redists.pcpu[PCPU_GET(cpuid)]->res);
return (0);
+ case GICV3_IVAR_REDIST:
+ *result = (uintptr_t)sc->gic_redists.pcpu[PCPU_GET(cpuid)];
+ return (0);
case GIC_IVAR_HW_REV:
KASSERT(
GICR_PIDR2_ARCH(sc->gic_pidr2) == GICR_PIDR2_ARCH_GICv3 ||
@@ -979,7 +990,7 @@ gic_v3_wait_for_rwp(struct gic_v3_softc *sc, enum gic_
res = sc->gic_dist;
break;
case REDIST:
- res = sc->gic_redists.pcpu[cpuid];
+ res = >gic_redists.pcpu[cpuid]->res;
break;
default:
KASSERT(0, ("%s: Attempt to wait for unknown RWP", __func__));
@@ -1173,7 +1184,7 @@ gic_v3_redist_find(struct gic_v3_softc *sc)
KASSERT(sc->gic_redists.pcpu[cpuid] != NULL,
("Invalid pointer to per-CPU
redistributor"));
/* Copy res contents to its final destination */
- *sc->gic_redists.pcpu[cpuid] = r_res;
+ sc->gic_redists.pcpu[cpuid]->res = r_res;
if (bootverbose) {
device_printf(sc->dev,
"CPU%u Re-Distributor has been
found\n",
Modified: head/sys/arm64/arm64/gic_v3_var.h
==
--- head/sys/arm64/arm64/gic_v3_var.h Wed May 29 23:50:31 2019
(r348376)
+++ head/sys/arm64/arm64/gic_v3_var.h Thu May 30 01:21:08 2019
(r348377)
@@ -40,10 +40,9 @@ DECLARE_CLASS(gic_v3_driver);
struct gic_v3_irqsrc;
-struct redist_lpis {
- vm_offset_t conf_base;
- vm_offset_t pend_base[MAXCPU];
- uint64_tflags;
+struct redist_pcpu {
+ struct resource res;
+ vm_offset_t pend_base;
};
struct gic_redists {
@@ -55,10 +54,8 @@ struct gic_redists {
struct resource ** regions;
/* Number of Re-Distributor regions */
u_int nregions;
- /*
svn commit: r348291 - head/sys/arm64/arm64
Author: jchandra
Date: Sun May 26 23:04:21 2019
New Revision: 348291
URL: https://svnweb.freebsd.org/changeset/base/348291
Log:
arm64 nexus: remove incorrect warning
acpi_config_intr() will be called when an arm64 system booted with ACPI.
We do the interrupt mapping for ACPI interrupts in nexus_acpi_map_intr()
on arm64, so acpi_config_intr() has to just return success without
printing this error message.
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D19432
Modified:
head/sys/arm64/arm64/nexus.c
Modified: head/sys/arm64/arm64/nexus.c
==
--- head/sys/arm64/arm64/nexus.cSun May 26 17:18:14 2019
(r348290)
+++ head/sys/arm64/arm64/nexus.cSun May 26 23:04:21 2019
(r348291)
@@ -292,9 +292,11 @@ nexus_config_intr(device_t dev, int irq, enum intr_tri
enum intr_polarity pol)
{
- /* TODO: This is wrong, it's needed for ACPI */
- device_printf(dev, "bus_config_intr is obsolete and not supported!\n");
- return (EOPNOTSUPP);
+ /*
+* On arm64 (due to INTRNG), ACPI interrupt configuration is
+* done in nexus_acpi_map_intr().
+*/
+ return (0);
}
static int
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svn commit: r343860 - head/sys/dev/pci
Author: jchandra
Date: Thu Feb 7 04:50:16 2019
New Revision: 343860
URL: https://svnweb.freebsd.org/changeset/base/343860
Log:
pci_host_generic_acpi: use IORT data for MSI/MSI-X
Use the information from IORT parsing to translate the PCI RID to
GIC ITS device ID. And similarly, use the information to find the
PIC XREF identifier to be used for PCI devices.
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D18004
Modified:
head/sys/dev/pci/pci_host_generic_acpi.c
Modified: head/sys/dev/pci/pci_host_generic_acpi.c
==
--- head/sys/dev/pci/pci_host_generic_acpi.cThu Feb 7 03:58:29 2019
(r343859)
+++ head/sys/dev/pci/pci_host_generic_acpi.cThu Feb 7 04:50:16 2019
(r343860)
@@ -348,14 +348,52 @@ generic_pcie_acpi_route_interrupt(device_t bus, device
return (acpi_pcib_route_interrupt(bus, dev, pin, >ap_prt));
}
+static u_int
+generic_pcie_get_xref(device_t pci, device_t child)
+{
+ struct generic_pcie_acpi_softc *sc;
+ uintptr_t rid;
+ u_int xref, devid;
+ int err;
+
+ sc = device_get_softc(pci);
+ err = pcib_get_id(pci, child, PCI_ID_RID, );
+ if (err != 0)
+ return (ACPI_MSI_XREF);
+ err = acpi_iort_map_pci_msi(sc->base.ecam, rid, , );
+ if (err != 0)
+ return (ACPI_MSI_XREF);
+ return (xref);
+}
+
+static u_int
+generic_pcie_map_id(device_t pci, device_t child, uintptr_t *id)
+{
+ struct generic_pcie_acpi_softc *sc;
+ uintptr_t rid;
+ u_int xref, devid;
+ int err;
+
+ sc = device_get_softc(pci);
+ err = pcib_get_id(pci, child, PCI_ID_RID, );
+ if (err != 0)
+ return (err);
+err = acpi_iort_map_pci_msi(sc->base.ecam, rid, , );
+ if (err == 0)
+ *id = devid;
+ else
+ *id = rid; /* RID not in IORT, likely FW bug, ignore */
+ return (0);
+}
+
static int
generic_pcie_acpi_alloc_msi(device_t pci, device_t child, int count,
int maxcount, int *irqs)
{
#if defined(INTRNG)
- return (intr_alloc_msi(pci, child, ACPI_MSI_XREF, count, maxcount,
- irqs));
+ return (intr_alloc_msi(pci, child, generic_pcie_get_xref(pci, child),
+ count, maxcount, irqs));
#else
return (ENXIO);
#endif
@@ -367,7 +405,8 @@ generic_pcie_acpi_release_msi(device_t pci, device_t c
{
#if defined(INTRNG)
- return (intr_release_msi(pci, child, ACPI_MSI_XREF, count, irqs));
+ return (intr_release_msi(pci, child, generic_pcie_get_xref(pci, child),
+ count, irqs));
#else
return (ENXIO);
#endif
@@ -379,7 +418,8 @@ generic_pcie_acpi_map_msi(device_t pci, device_t child
{
#if defined(INTRNG)
- return (intr_map_msi(pci, child, ACPI_MSI_XREF, irq, addr, data));
+ return (intr_map_msi(pci, child, generic_pcie_get_xref(pci, child), irq,
+ addr, data));
#else
return (ENXIO);
#endif
@@ -390,7 +430,8 @@ generic_pcie_acpi_alloc_msix(device_t pci, device_t ch
{
#if defined(INTRNG)
- return (intr_alloc_msix(pci, child, ACPI_MSI_XREF, irq));
+ return (intr_alloc_msix(pci, child, generic_pcie_get_xref(pci, child),
+ irq));
#else
return (ENXIO);
#endif
@@ -401,7 +442,8 @@ generic_pcie_acpi_release_msix(device_t pci, device_t
{
#if defined(INTRNG)
- return (intr_release_msix(pci, child, ACPI_MSI_XREF, irq));
+ return (intr_release_msix(pci, child, generic_pcie_get_xref(pci, child),
+ irq));
#else
return (ENXIO);
#endif
@@ -412,14 +454,8 @@ generic_pcie_acpi_get_id(device_t pci, device_t child,
uintptr_t *id)
{
- /*
-* Use the PCI RID to find the MSI ID for now, we support only 1:1
-* mapping
-*
-* On aarch64, more complex mapping would come from IORT table
-*/
if (type == PCI_ID_MSI)
- return (pcib_get_id(pci, child, PCI_ID_RID, id));
+ return (generic_pcie_map_id(pci, child, id));
else
return (pcib_get_id(pci, child, type, id));
}
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svn commit: r343856 - head/sys/arm64/arm64
Author: jchandra
Date: Thu Feb 7 03:01:54 2019
New Revision: 343856
URL: https://svnweb.freebsd.org/changeset/base/343856
Log:
arm64 gicv3: add IORT and NUMA support
acpi_iort.c has added support to query GIC proximity and MSI XREF
ID for GIC ITS blocks. Use this when GIC ITS blocks are initialized
from ACPI.
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D18003
Modified:
head/sys/arm64/arm64/gic_v3_acpi.c
head/sys/arm64/arm64/gic_v3_var.h
head/sys/arm64/arm64/gicv3_its.c
Modified: head/sys/arm64/arm64/gic_v3_acpi.c
==
--- head/sys/arm64/arm64/gic_v3_acpi.c Thu Feb 7 02:56:10 2019
(r343855)
+++ head/sys/arm64/arm64/gic_v3_acpi.c Thu Feb 7 03:01:54 2019
(r343856)
@@ -305,6 +305,8 @@ gic_v3_add_children(ACPI_SUBTABLE_HEADER *entry, void
struct gic_v3_acpi_devinfo *di;
struct gic_v3_softc *sc;
device_t child, dev;
+ u_int xref;
+ int err, pxm;
if (entry->Type == ACPI_MADT_TYPE_GENERIC_TRANSLATOR) {
/* We have an ITS, add it as a child */
@@ -321,7 +323,14 @@ gic_v3_add_children(ACPI_SUBTABLE_HEADER *entry, void
resource_list_add(>di_rl, SYS_RES_MEMORY, 0,
gict->BaseAddress, gict->BaseAddress + 128 * 1024 - 1,
128 * 1024);
- di->di_gic_dinfo.gic_domain = -1;
+ err = acpi_iort_its_lookup(gict->TranslationId, , );
+ if (err == 0) {
+ di->di_gic_dinfo.gic_domain = pxm;
+ di->di_gic_dinfo.msi_xref = xref;
+ } else {
+ di->di_gic_dinfo.gic_domain = -1;
+ di->di_gic_dinfo.msi_xref = ACPI_MSI_XREF;
+ }
sc->gic_nchildren++;
device_set_ivars(child, di);
}
Modified: head/sys/arm64/arm64/gic_v3_var.h
==
--- head/sys/arm64/arm64/gic_v3_var.h Thu Feb 7 02:56:10 2019
(r343855)
+++ head/sys/arm64/arm64/gic_v3_var.h Thu Feb 7 03:01:54 2019
(r343856)
@@ -87,6 +87,7 @@ struct gic_v3_softc {
struct gic_v3_devinfo {
int gic_domain;
+ int msi_xref;
};
#define GIC_INTR_ISRC(sc, irq) (>gic_irqs[irq].gi_isrc)
Modified: head/sys/arm64/arm64/gicv3_its.c
==
--- head/sys/arm64/arm64/gicv3_its.cThu Feb 7 02:56:10 2019
(r343855)
+++ head/sys/arm64/arm64/gicv3_its.cThu Feb 7 03:01:54 2019
(r343856)
@@ -1722,6 +1722,7 @@ static int
gicv3_its_acpi_attach(device_t dev)
{
struct gicv3_its_softc *sc;
+ struct gic_v3_devinfo *di;
int err;
sc = device_get_softc(dev);
@@ -1729,13 +1730,13 @@ gicv3_its_acpi_attach(device_t dev)
if (err != 0)
return (err);
- sc->sc_pic = intr_pic_register(dev,
- device_get_unit(dev) + ACPI_MSI_XREF);
+ di = device_get_ivars(dev);
+ sc->sc_pic = intr_pic_register(dev, di->msi_xref);
intr_pic_add_handler(device_get_parent(dev), sc->sc_pic,
gicv3_its_intr, sc, sc->sc_irq_base, sc->sc_irq_length);
/* Register this device to handle MSI interrupts */
- intr_msi_register(dev, device_get_unit(dev) + ACPI_MSI_XREF);
+ intr_msi_register(dev, di->msi_xref);
return (0);
}
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svn commit: r343853 - in head/sys: arm64/acpica conf dev/acpica
Author: jchandra
Date: Thu Feb 7 02:30:33 2019
New Revision: 343853
URL: https://svnweb.freebsd.org/changeset/base/343853
Log:
arm64 acpi: Add support for IORT table
Add new file arm64/acpica/acpi_iort.c to support the "IO Remapping
Table" (IORT). The table is specified in ARM document "ARM DEN 0049D"
titled "IO Remapping Table Platform Design Document". The IORT table
has information on the associations between PCI root complexes, SMMU
blocks and GIC ITS blocks in the system.
The changes are to parse and save the information in the IORT table.
The API to use this information is added to sys/dev/acpica/acpivar.h.
The acpi_iort.c also has code to check the GIC ITS nodes seen in the
IORT table with corresponding entries in MADT table (for validity)
and with entries in SRAT table (for proximity information).
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D18002
Added:
head/sys/arm64/acpica/acpi_iort.c (contents, props changed)
Modified:
head/sys/conf/files.arm64
head/sys/dev/acpica/acpivar.h
Added: head/sys/arm64/acpica/acpi_iort.c
==
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/arm64/acpica/acpi_iort.c Thu Feb 7 02:30:33 2019
(r343853)
@@ -0,0 +1,502 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * Author: Jayachandran C Nair
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "opt_acpi.h"
+
+#include
+__FBSDID("$FreeBSD$");
+
+#include
+#include
+#include
+#include
+
+#include
+
+#include
+#include
+#include
+
+#include
+
+/*
+ * Track next XREF available for ITS groups.
+ */
+static u_int acpi_its_xref = ACPI_MSI_XREF;
+
+/*
+ * Some types of IORT nodes have a set of mappings. Each of them map
+ * a range of device IDs [base..end] from the current node to another
+ * node. The corresponding device IDs on destination node starts at
+ * outbase.
+ */
+struct iort_map_entry {
+ u_int base;
+ u_int end;
+ u_int outbase;
+ u_int flags;
+ u_int out_node_offset;
+ struct iort_node*out_node;
+};
+
+/*
+ * The ITS group node does not have any outgoing mappings. It has a
+ * of a list of GIC ITS blocks which can handle the device ID. We
+ * will store the PIC XREF used by the block and the blocks proximity
+ * data here, so that it can be retrieved together.
+ */
+struct iort_its_entry {
+ u_int its_id;
+ u_int xref;
+ int pxm;
+};
+
+/*
+ * IORT node. Each node has some device specific data depending on the
+ * type of the node. The node can also have a set of mappings, OR in
+ * case of ITS group nodes a set of ITS entries.
+ * The nodes are kept in a TAILQ by type.
+ */
+struct iort_node {
+ TAILQ_ENTRY(iort_node) next; /* next entry with same type */
+ enum AcpiIortNodeType type; /* ACPI type */
+ u_int node_offset;/* offset in IORT - node ID */
+ u_int nentries; /* items in array below */
+ u_int usecount; /* for bookkeeping */
+ union {
+ ACPI_IORT_ROOT_COMPLEX pci_rc; /* PCI root complex */
+ ACPI_IORT_SMMU smmu;
+ ACPI_IORT_SMMU_V3 smmu_v3;
+ } data;
+ union {
+ struct iort_map_entry *mappings
svn commit: r343764 - head/sys/arm/arm
Author: jchandra
Date: Tue Feb 5 06:25:35 2019
New Revision: 343764
URL: https://svnweb.freebsd.org/changeset/base/343764
Log:
arm, acpi: increase size of memory region arrays
Bump up MAX_HWCNT and MAX_EXCNT to 32 when ACPI is enabled. These are
the sizes of the hwregions and exregions arrays respectively. ACPI
firmware typically has more memory regions and the current value of
16 is not sufficient for some platforms.
This commit fixes a failure seen with AMI firmware on Cavium's Sabre
ThunderX2 reference platform. This platform needs 21 physical memory
regions and 18 excluded regions to boot correctly with the current
firmware release.
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D19073
Modified:
head/sys/arm/arm/physmem.c
Modified: head/sys/arm/arm/physmem.c
==
--- head/sys/arm/arm/physmem.c Tue Feb 5 04:47:41 2019(r343763)
+++ head/sys/arm/arm/physmem.c Tue Feb 5 06:25:35 2019(r343764)
@@ -29,6 +29,7 @@
#include
__FBSDID("$FreeBSD$");
+#include "opt_acpi.h"
#include "opt_ddb.h"
/*
@@ -48,8 +49,13 @@ __FBSDID("$FreeBSD$");
* that can be allocated, or both, depending on the exclusion flags associated
* with the region.
*/
+#ifdef DEV_ACPI
+#defineMAX_HWCNT 32 /* ACPI needs more regions */
+#defineMAX_EXCNT 32
+#else
#defineMAX_HWCNT 16
#defineMAX_EXCNT 16
+#endif
#if defined(__arm__)
#defineMAX_PHYS_ADDR 0xull
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svn commit: r341744 - in head/sys/arm64: acpica arm64
Author: jchandra
Date: Sat Dec 8 19:42:01 2018
New Revision: 341744
URL: https://svnweb.freebsd.org/changeset/base/341744
Log:
arm64: add ACPI based NUMA support
Use the newly defined SRAT/SLIT parsing APIs in arm64 to support
ACPI based NUMA.
Reviewed by: markj
Differential Revision:https://reviews.freebsd.org/D17943
Modified:
head/sys/arm64/acpica/acpi_machdep.c
head/sys/arm64/arm64/mp_machdep.c
Modified: head/sys/arm64/acpica/acpi_machdep.c
==
--- head/sys/arm64/acpica/acpi_machdep.cSat Dec 8 19:32:23 2018
(r341743)
+++ head/sys/arm64/acpica/acpi_machdep.cSat Dec 8 19:42:01 2018
(r341744)
@@ -233,3 +233,16 @@ acpi_map_addr(struct acpi_generic_address *addr, bus_s
return (bus_space_map(*tag, phys, size, 0, handle));
}
+
+#if MAXMEMDOM > 1
+static void
+parse_pxm_tables(void *dummy)
+{
+
+ acpi_pxm_init(MAXCPU, (vm_paddr_t)1 << 40);
+ acpi_pxm_parse_tables();
+ acpi_pxm_set_mem_locality();
+}
+SYSINIT(parse_pxm_tables, SI_SUB_VM - 1, SI_ORDER_FIRST, parse_pxm_tables,
+NULL);
+#endif
Modified: head/sys/arm64/arm64/mp_machdep.c
==
--- head/sys/arm64/arm64/mp_machdep.c Sat Dec 8 19:32:23 2018
(r341743)
+++ head/sys/arm64/arm64/mp_machdep.c Sat Dec 8 19:42:01 2018
(r341744)
@@ -442,13 +442,15 @@ madt_handler(ACPI_SUBTABLE_HEADER *entry, void *arg)
{
ACPI_MADT_GENERIC_INTERRUPT *intr;
u_int *cpuid;
+ u_int id;
switch(entry->Type) {
case ACPI_MADT_TYPE_GENERIC_INTERRUPT:
intr = (ACPI_MADT_GENERIC_INTERRUPT *)entry;
cpuid = arg;
-
- start_cpu((*cpuid), intr->ArmMpidr);
+ id = *cpuid;
+ start_cpu(id, intr->ArmMpidr);
+ __pcpu[id].pc_acpi_id = intr->Uid;
(*cpuid)++;
break;
default:
@@ -478,6 +480,12 @@ cpu_init_acpi(void)
madt_handler, );
acpi_unmap_table(madt);
+
+#if MAXMEMDOM > 1
+ /* set proximity info */
+ acpi_pxm_set_cpu_locality();
+ acpi_pxm_free();
+#endif
}
#endif
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svn commit: r341743 - in head/sys: conf dev/acpica
Author: jchandra
Date: Sat Dec 8 19:32:23 2018
New Revision: 341743
URL: https://svnweb.freebsd.org/changeset/base/341743
Log:
acpica: support parsing of arm64 affinity in acpi_pxm.c
ACPI SRAT table on arm64 uses GICC entries to provide CPU locality
information. These entries use an AcpiProcessorUid to identify the
CPU (unlike on x86 where the entries have an APIC ID).
Update acpi_pxm.c to extend the cpu_add/cpu_find/cpu_get_info
functions to handle AcpiProcessorUid. Use the updated functions
while parsing ACPI_SRAT_GICC_AFFINITY entry for arm64.
Also update sys/conf/files.arm64 to build acpi_pxm.c when ACPI is
enabled.
Reviewed by: markj (previous version)
Differential Revision:https://reviews.freebsd.org/D17942
Modified:
head/sys/conf/files.arm64
head/sys/dev/acpica/acpi_pxm.c
Modified: head/sys/conf/files.arm64
==
--- head/sys/conf/files.arm64 Sat Dec 8 19:10:58 2018(r341742)
+++ head/sys/conf/files.arm64 Sat Dec 8 19:32:23 2018(r341743)
@@ -188,6 +188,7 @@ dev/acpica/acpi_bus_if.moptionalacpi
dev/acpica/acpi_if.m optionalacpi
dev/acpica/acpi_pci_link.c optionalacpi pci
dev/acpica/acpi_pcib.c optionalacpi pci
+dev/acpica/acpi_pxm.c optionalacpi
dev/ahci/ahci_generic.coptionalahci
dev/axgbe/if_axgbe.c optionalaxgbe
dev/axgbe/xgbe-desc.c optionalaxgbe
Modified: head/sys/dev/acpica/acpi_pxm.c
==
--- head/sys/dev/acpica/acpi_pxm.c Sat Dec 8 19:10:58 2018
(r341742)
+++ head/sys/dev/acpica/acpi_pxm.c Sat Dec 8 19:32:23 2018
(r341743)
@@ -59,6 +59,7 @@ static struct cpu_info {
int enabled:1;
int has_memory:1;
int domain;
+ int id;
} *cpus;
static int max_cpus;
@@ -182,14 +183,33 @@ overlaps_phys_avail(vm_paddr_t start, vm_paddr_t end)
}
/*
- * Find CPU by processor ID (APIC ID on x86).
+ * On x86 we can use the cpuid to index the cpus array, but on arm64
+ * we have an ACPI Processor UID with a larger range.
+ *
+ * Use this variable to indicate if the cpus can be stored by index.
*/
+#ifdef __aarch64__
+static const int cpus_use_indexing = 0;
+#else
+static const int cpus_use_indexing = 1;
+#endif
+
+/*
+ * Find CPU by processor ID (APIC ID on x86, Processor UID on arm64)
+ */
static struct cpu_info *
cpu_find(int cpuid)
{
+ int i;
- if (cpuid <= last_cpu && cpus[cpuid].enabled)
- return ([cpuid]);
+ if (cpus_use_indexing) {
+ if (cpuid <= last_cpu && cpus[cpuid].enabled)
+ return ([cpuid]);
+ } else {
+ for (i = 0; i <= last_cpu; i++)
+ if (cpus[i].id == cpuid)
+ return ([i]);
+ }
return (NULL);
}
@@ -202,10 +222,14 @@ cpu_get_info(struct pcpu *pc)
struct cpu_info *cpup;
int id;
+#ifdef __aarch64__
+ id = pc->pc_acpi_id;
+#else
id = pc->pc_apic_id;
+#endif
cpup = cpu_find(id);
if (cpup == NULL)
- panic("SRAT: CPU with APIC ID %u is not known", id);
+ panic("SRAT: CPU with ID %u is not known", id);
return (cpup);
}
@@ -217,11 +241,18 @@ cpu_add(int cpuid, int domain)
{
struct cpu_info *cpup;
- if (cpuid >= max_cpus)
- return (NULL);
- last_cpu = imax(last_cpu, cpuid);
- cpup = [cpuid];
+ if (cpus_use_indexing) {
+ if (cpuid >= max_cpus)
+ return (NULL);
+ last_cpu = imax(last_cpu, cpuid);
+ cpup = [cpuid];
+ } else {
+ if (last_cpu >= max_cpus - 1)
+ return (NULL);
+ cpup = [++last_cpu];
+ }
cpup->domain = domain;
+ cpup->id = cpuid;
cpup->enabled = 1;
return (cpup);
}
@@ -232,6 +263,7 @@ srat_parse_entry(ACPI_SUBTABLE_HEADER *entry, void *ar
ACPI_SRAT_CPU_AFFINITY *cpu;
ACPI_SRAT_X2APIC_CPU_AFFINITY *x2apic;
ACPI_SRAT_MEM_AFFINITY *mem;
+ ACPI_SRAT_GICC_AFFINITY *gicc;
static struct cpu_info *cpup;
int domain, i, slot;
@@ -276,6 +308,22 @@ srat_parse_entry(ACPI_SUBTABLE_HEADER *entry, void *ar
if (cpup == NULL)
printf("SRAT: Ignoring local APIC ID %u (too high)\n",
x2apic->ApicId);
+ break;
+ case ACPI_SRAT_TYPE_GICC_AFFINITY:
+ gicc = (ACPI_SRAT_GICC_AFFINITY *)entry;
+ if (bootverbose)
+ printf("SRAT: Found CPU UID %u domain %d: %s\n",
+ gicc->AcpiProcessorUid, gicc->ProximityDomain,
+ (gicc->Flags &
svn commit: r341742 - in head/sys: conf dev/acpica x86/acpica
Author: jchandra
Date: Sat Dec 8 19:10:58 2018
New Revision: 341742
URL: https://svnweb.freebsd.org/changeset/base/341742
Log:
acpica : move SRAT/SLIT parsing to sys/dev/acpica
This moves the architecture independent parts of sys/x86/acpica/srat.c
to sys/dev/acpica/acpi_pxm.c, to be used later on arm64. The function
declarations are moved to sys/dev/acpica/acpivar.h
We also need to update sys/conf/files.{i386,amd64} to use the new file.
No functional changes.
Reviewed by: markj, imp
Differential Revision:https://reviews.freebsd.org/D17941
Added:
head/sys/dev/acpica/acpi_pxm.c (contents, props changed)
Modified:
head/sys/conf/files.amd64
head/sys/conf/files.i386
head/sys/dev/acpica/acpivar.h
head/sys/x86/acpica/srat.c
Modified: head/sys/conf/files.amd64
==
--- head/sys/conf/files.amd64 Sat Dec 8 18:34:05 2018(r341741)
+++ head/sys/conf/files.amd64 Sat Dec 8 19:10:58 2018(r341742)
@@ -203,6 +203,7 @@ dev/acpica/acpi_pci_link.c optional acpi pci
dev/acpica/acpi_pcib.c optional acpi pci
dev/acpica/acpi_pcib_acpi.coptional acpi pci
dev/acpica/acpi_pcib_pci.c optional acpi pci
+dev/acpica/acpi_pxm.c optionalacpi
dev/acpica/acpi_timer.coptionalacpi
dev/acpi_support/acpi_wmi_if.m standard
dev/agp/agp_amd64.coptionalagp
Modified: head/sys/conf/files.i386
==
--- head/sys/conf/files.i386Sat Dec 8 18:34:05 2018(r341741)
+++ head/sys/conf/files.i386Sat Dec 8 19:10:58 2018(r341742)
@@ -332,6 +332,7 @@ dev/vmware/vmci/vmci_resource.c optional
vmci
dev/acpica/acpi_if.m standard
dev/acpica/acpi_hpet.c optional acpi
dev/acpica/acpi_timer.coptional acpi
+dev/acpica/acpi_pxm.c optional acpi
dev/acpi_support/acpi_wmi_if.m standard
dev/wbwd/wbwd.coptional wbwd
dev/isci/isci.c
optional isci
Added: head/sys/dev/acpica/acpi_pxm.c
==
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/dev/acpica/acpi_pxm.c Sat Dec 8 19:10:58 2018
(r341742)
@@ -0,0 +1,649 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright (c) 2010 Hudson River Trading LLC
+ * Written by: John H. Baldwin
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include
+__FBSDID("$FreeBSD$");
+
+#include "opt_vm.h"
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+
+#include
+
+#if MAXMEMDOM > 1
+static struct cpu_info {
+ int enabled:1;
+ int has_memory:1;
+ int domain;
+} *cpus;
+
+static int max_cpus;
+static int last_cpu;
+
+struct mem_affinity mem_info[VM_PHYSSEG_MAX + 1];
+int num_mem;
+
+static ACPI_TABLE_SRAT *srat;
+static vm_paddr_t srat_physaddr;
+
+static int domain_pxm[MAXMEMDOM];
+static int ndomain;
+static vm_paddr_t maxphyaddr;
+
+static ACPI_TABLE_SLIT *slit;
+static vm_paddr_t slit_physaddr;
+static int vm_locality_table[MAXMEMDOM * MAXMEMDOM];
+
+static voidsrat_walk_table(acpi_subtable_handler *handler, void *arg);
+
+/*
+ * SLIT parsing.
+ */
+
+static void
+slit_parse_table(ACPI_TABLE_SLIT *s)
+{
+ int i, j;
+ int i_domain, j_domain;
+ int offset = 0;
+ uint8_t e;
+
+ /*
svn commit: r341741 - head/sys/x86/acpica
Author: jchandra
Date: Sat Dec 8 18:34:05 2018
New Revision: 341741
URL: https://svnweb.freebsd.org/changeset/base/341741
Log:
x86/acpica/srat.c: Add API for parsing proximity tables
The SLIT and SRAT ACPI tables needs to be parsed on arm64 as well, on
systems that use UEFI/ACPI firmware and support NUMA. To do this, we
need to move most of the logic of x86/acpica/srat.c to dev/acpica and
provide an API that architectures can use to parse and configure ACPI
NUMA information.
This commit adds the API in srat.c as a first step, without making any
functional changes. We will move the common code to sys/dev/acpica
as the next step.
The functions added are:
* int acpi_pxm_init(int ncpus, vm_paddr_t maxphys) - to allocate and
initialize data structures used
* void acpi_pxm_parse_tables(void) - parse SRAT/SLIT, save the cpu and
memory proximity information
* void acpi_pxm_set_mem_locality(void) - use the saved data to set
memory locality
* void acpi_pxm_set_cpu_locality(void) - use the saved data to set cpu
locality
* void acpi_pxm_free(void) - free data structures allocated by init
On arm64, we do not have an cpu APIC id that can be used as index to
store CPU data, we need to use the Processor Uid. To help with this,
define internal functions cpu_add, cpu_find, cpu_get_info to store
and get CPU proximity information.
Reviewed by: markj, jhb (previous version)
Differential Revision:https://reviews.freebsd.org/D17940
Modified:
head/sys/x86/acpica/srat.c
Modified: head/sys/x86/acpica/srat.c
==
--- head/sys/x86/acpica/srat.c Sat Dec 8 17:50:00 2018(r341740)
+++ head/sys/x86/acpica/srat.c Sat Dec 8 18:34:05 2018(r341741)
@@ -56,6 +56,15 @@ __FBSDID("$FreeBSD$");
#include
+/*
+ * Parse and use proximity information in SRAT and SLIT.
+ */
+intacpi_pxm_init(int ncpus, vm_paddr_t maxphys);
+void acpi_pxm_parse_tables(void);
+void acpi_pxm_set_mem_locality(void);
+void acpi_pxm_set_cpu_locality(void);
+void acpi_pxm_free(void);
+
#if MAXMEMDOM > 1
static struct cpu_info {
int enabled:1;
@@ -63,6 +72,9 @@ static struct cpu_info {
int domain;
} *cpus;
+static int max_cpus;
+static int last_cpu;
+
struct mem_affinity mem_info[VM_PHYSSEG_MAX + 1];
int num_mem;
@@ -71,6 +83,7 @@ static vm_paddr_t srat_physaddr;
static int domain_pxm[MAXMEMDOM];
static int ndomain;
+static vm_paddr_t maxphyaddr;
static ACPI_TABLE_SLIT *slit;
static vm_paddr_t slit_physaddr;
@@ -177,15 +190,60 @@ overlaps_phys_avail(vm_paddr_t start, vm_paddr_t end)
break;
}
return (0);
-
}
+/*
+ * Find CPU by processor ID (APIC ID on x86).
+ */
+static struct cpu_info *
+cpu_find(int cpuid)
+{
+
+ if (cpuid <= last_cpu && cpus[cpuid].enabled)
+ return ([cpuid]);
+ return (NULL);
+}
+
+/*
+ * Find CPU by pcpu pointer.
+ */
+static struct cpu_info *
+cpu_get_info(struct pcpu *pc)
+{
+ struct cpu_info *cpup;
+ int id;
+
+ id = pc->pc_apic_id;
+ cpup = cpu_find(id);
+ if (cpup == NULL)
+ panic("SRAT: CPU with APIC ID %u is not known", id);
+ return (cpup);
+}
+
+/*
+ * Add proximity information for a new CPU.
+ */
+static struct cpu_info *
+cpu_add(int cpuid, int domain)
+{
+ struct cpu_info *cpup;
+
+ if (cpuid >= max_cpus)
+ return (NULL);
+ last_cpu = imax(last_cpu, cpuid);
+ cpup = [cpuid];
+ cpup->domain = domain;
+ cpup->enabled = 1;
+ return (cpup);
+}
+
static void
srat_parse_entry(ACPI_SUBTABLE_HEADER *entry, void *arg)
{
ACPI_SRAT_CPU_AFFINITY *cpu;
ACPI_SRAT_X2APIC_CPU_AFFINITY *x2apic;
ACPI_SRAT_MEM_AFFINITY *mem;
+ static struct cpu_info *cpup;
int domain, i, slot;
switch (entry->Type) {
@@ -202,20 +260,17 @@ srat_parse_entry(ACPI_SUBTABLE_HEADER *entry, void *ar
"enabled" : "disabled");
if (!(cpu->Flags & ACPI_SRAT_CPU_ENABLED))
break;
- if (cpu->ApicId > max_apic_id) {
- printf("SRAT: Ignoring local APIC ID %u (too high)\n",
- cpu->ApicId);
- break;
- }
-
- if (cpus[cpu->ApicId].enabled) {
+ cpup = cpu_find(cpu->ApicId);
+ if (cpup != NULL) {
printf("SRAT: Duplicate local APIC ID %u\n",
cpu->ApicId);
*(int *)arg = ENXIO;
break;
}
- cpus[cpu->ApicId].domain = domain;
- cpus[cpu->ApicId].enabled = 1;
+ cpup = cpu_add(cpu->ApicId, domain);
+ if (cpup == NULL)
+
svn commit: r340602 - head/sys/arm64/arm64
Author: jchandra
Date: Mon Nov 19 03:52:56 2018
New Revision: 340602
URL: https://svnweb.freebsd.org/changeset/base/340602
Log:
gitv3_its: fixes for multiple GIC ITS blocks
First pass of support for multiple GIC ITS blocks with ACPI.
Changes are to:
* register the correct subset of interrupts with pic_register
in case of ACPI.
* initialize just the cpu interface for the first ITS, when
domain information is not avialable. This has to be done
until we split the per-CPU init to do LPI setup just once.
* remove duplicate check for the GIC ITS domain, the sc_cpus
are setup from domain, so the check again in per-CPU init
seems unnecessary.
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D17841
Modified:
head/sys/arm64/arm64/gicv3_its.c
Modified: head/sys/arm64/arm64/gicv3_its.c
==
--- head/sys/arm64/arm64/gicv3_its.cMon Nov 19 03:43:10 2018
(r340601)
+++ head/sys/arm64/arm64/gicv3_its.cMon Nov 19 03:52:56 2018
(r340602)
@@ -580,18 +580,11 @@ its_init_cpu(device_t dev, struct gicv3_its_softc *sc)
uint64_t xbaser, tmp;
uint32_t ctlr;
u_int cpuid;
- int domain;
- if (!CPU_ISSET(PCPU_GET(cpuid), >sc_cpus))
- return (0);
-
- if (bus_get_domain(dev, ) == 0) {
- if (PCPU_GET(domain) != domain)
- return (0);
- }
-
gicv3 = device_get_parent(dev);
cpuid = PCPU_GET(cpuid);
+ if (!CPU_ISSET(cpuid, >sc_cpus))
+ return (0);
/* Check if the ITS is enabled on this CPU */
if ((gic_r_read_4(gicv3, GICR_TYPER) & GICR_TYPER_PLPIS) == 0) {
@@ -729,12 +722,14 @@ gicv3_its_attach(device_t dev)
/* Protects access to the ITS command circular buffer. */
mtx_init(>sc_its_cmd_lock, "ITS cmd lock", NULL, MTX_SPIN);
+ CPU_ZERO(>sc_cpus);
if (bus_get_domain(dev, ) == 0) {
- CPU_ZERO(>sc_cpus);
if (domain < MAXMEMDOM)
CPU_COPY(_domain[domain], >sc_cpus);
} else {
- CPU_COPY(_cpus, >sc_cpus);
+ /* XXX : cannot handle more than one ITS per cpu */
+ if (device_get_unit(dev) == 0)
+ CPU_COPY(_cpus, >sc_cpus);
}
/* Allocate the command circular buffer */
@@ -1737,7 +1732,7 @@ gicv3_its_acpi_attach(device_t dev)
sc->sc_pic = intr_pic_register(dev,
device_get_unit(dev) + ACPI_MSI_XREF);
intr_pic_add_handler(device_get_parent(dev), sc->sc_pic,
- gicv3_its_intr, sc, GIC_FIRST_LPI, LPI_NIRQS);
+ gicv3_its_intr, sc, sc->sc_irq_base, sc->sc_irq_length);
/* Register this device to handle MSI interrupts */
intr_msi_register(dev, device_get_unit(dev) + ACPI_MSI_XREF);
___
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svn commit: r340601 - head/sys/dev/pci
Author: jchandra
Date: Mon Nov 19 03:43:10 2018
New Revision: 340601
URL: https://svnweb.freebsd.org/changeset/base/340601
Log:
pci_host_generic : move activate/release to generic code
Now that the ACPI and FDT implementations for activating and
deactivating resources are the same, we can move it to
pci_host_generic.c. No functional changes.
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D17793
Modified:
head/sys/dev/pci/pci_host_generic.c
head/sys/dev/pci/pci_host_generic_acpi.c
head/sys/dev/pci/pci_host_generic_fdt.c
Modified: head/sys/dev/pci/pci_host_generic.c
==
--- head/sys/dev/pci/pci_host_generic.c Mon Nov 19 03:34:15 2018
(r340600)
+++ head/sys/dev/pci/pci_host_generic.c Mon Nov 19 03:43:10 2018
(r340601)
@@ -341,6 +341,82 @@ fail:
}
static int
+generic_pcie_activate_resource(device_t dev, device_t child, int type,
+int rid, struct resource *r)
+{
+ struct generic_pcie_core_softc *sc;
+ uint64_t phys_base;
+ uint64_t pci_base;
+ uint64_t size;
+ int found;
+ int res;
+ int i;
+
+ sc = device_get_softc(dev);
+
+ if ((res = rman_activate_resource(r)) != 0)
+ return (res);
+
+ switch (type) {
+ case SYS_RES_IOPORT:
+ found = 0;
+ for (i = 0; i < MAX_RANGES_TUPLES; i++) {
+ pci_base = sc->ranges[i].pci_base;
+ phys_base = sc->ranges[i].phys_base;
+ size = sc->ranges[i].size;
+
+ if ((rid > pci_base) && (rid < (pci_base + size))) {
+ found = 1;
+ break;
+ }
+ }
+ if (found) {
+ rman_set_start(r, rman_get_start(r) + phys_base);
+ rman_set_end(r, rman_get_end(r) + phys_base);
+ res = BUS_ACTIVATE_RESOURCE(device_get_parent(dev),
+ child, type, rid, r);
+ } else {
+ device_printf(dev,
+ "Failed to activate IOPORT resource\n");
+ res = 0;
+ }
+ break;
+ case SYS_RES_MEMORY:
+ case SYS_RES_IRQ:
+ res = BUS_ACTIVATE_RESOURCE(device_get_parent(dev), child,
+ type, rid, r);
+ break;
+ default:
+ break;
+ }
+
+ return (res);
+}
+
+static int
+generic_pcie_deactivate_resource(device_t dev, device_t child, int type,
+int rid, struct resource *r)
+{
+ int res;
+
+ if ((res = rman_deactivate_resource(r)) != 0)
+ return (res);
+
+ switch (type) {
+ case SYS_RES_IOPORT:
+ case SYS_RES_MEMORY:
+ case SYS_RES_IRQ:
+ res = BUS_DEACTIVATE_RESOURCE(device_get_parent(dev), child,
+ type, rid, r);
+ break;
+ default:
+ break;
+ }
+
+ return (res);
+}
+
+static int
generic_pcie_adjust_resource(device_t dev, device_t child, int type,
struct resource *res, rman_res_t start, rman_res_t end)
{
@@ -375,6 +451,8 @@ static device_method_t generic_pcie_methods[] = {
DEVMETHOD(bus_write_ivar, generic_pcie_write_ivar),
DEVMETHOD(bus_alloc_resource,
pci_host_generic_core_alloc_resource),
DEVMETHOD(bus_adjust_resource, generic_pcie_adjust_resource),
+ DEVMETHOD(bus_activate_resource,generic_pcie_activate_resource),
+ DEVMETHOD(bus_deactivate_resource,
generic_pcie_deactivate_resource),
DEVMETHOD(bus_release_resource,
pci_host_generic_core_release_resource),
DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
DEVMETHOD(bus_teardown_intr,bus_generic_teardown_intr),
Modified: head/sys/dev/pci/pci_host_generic_acpi.c
==
--- head/sys/dev/pci/pci_host_generic_acpi.cMon Nov 19 03:34:15 2018
(r340600)
+++ head/sys/dev/pci/pci_host_generic_acpi.cMon Nov 19 03:43:10 2018
(r340601)
@@ -348,86 +348,7 @@ generic_pcie_acpi_route_interrupt(device_t bus, device
return (acpi_pcib_route_interrupt(bus, dev, pin, >ap_prt));
}
-/*
- * Follow logic of FDT activate
- */
static int
-generic_pcie_acpi_activate_resource(device_t dev, device_t child, int type,
-int rid, struct resource *r)
-{
- struct generic_pcie_acpi_softc *sc;
- uint64_t phys_base;
- uint64_t pci_base;
- uint64_t size;
- int found;
- int res;
- int i;
-
- sc = device_get_softc(dev);
-
- if ((res = rman_activate_resource(r)) != 0)
- return (res);
-
- switch (type) {
- case
svn commit: r340600 - in head/sys/dev: acpica pci
Author: jchandra
Date: Mon Nov 19 03:34:15 2018
New Revision: 340600
URL: https://svnweb.freebsd.org/changeset/base/340600
Log:
pci_host_generic, acpi_resource: drop unneeded code
Now that we are handling PCI resources in pci_host_generic_acpi.c, we
don't need these change (made by r336129)
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D17792
Modified:
head/sys/dev/acpica/acpi_resource.c
head/sys/dev/pci/pci_host_generic.c
Modified: head/sys/dev/acpica/acpi_resource.c
==
--- head/sys/dev/acpica/acpi_resource.c Mon Nov 19 03:16:16 2018
(r340599)
+++ head/sys/dev/acpica/acpi_resource.c Mon Nov 19 03:34:15 2018
(r340600)
@@ -602,10 +602,6 @@ acpi_res_set_memory(device_t dev, void *context, uint6
if (cp == NULL)
return;
-
-while (bus_get_resource_start(dev, SYS_RES_MEMORY, cp->ar_nmem))
- cp->ar_nmem++;
-
bus_set_resource(dev, SYS_RES_MEMORY, cp->ar_nmem++, base, length);
}
Modified: head/sys/dev/pci/pci_host_generic.c
==
--- head/sys/dev/pci/pci_host_generic.c Mon Nov 19 03:16:16 2018
(r340599)
+++ head/sys/dev/pci/pci_host_generic.c Mon Nov 19 03:34:15 2018
(r340600)
@@ -107,7 +107,7 @@ pci_host_generic_core_attach(device_t dev)
return (error);
rid = 0;
- sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, , RF_ACTIVE |
RF_SHAREABLE);
+ sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, , RF_ACTIVE);
if (sc->res == NULL) {
device_printf(dev, "could not map memory.\n");
return (ENXIO);
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svn commit: r340599 - in head/sys/dev: acpica pci
Author: jchandra
Date: Mon Nov 19 03:16:16 2018
New Revision: 340599
URL: https://svnweb.freebsd.org/changeset/base/340599
Log:
acpica, pci_host_generic_acpi: redo pci_host_generic_acpi.c
This is a major update for pci_host_generic_acpi.c, the current
implementation has some gaps that are better fixed up in one go.
The changes are to:
* Follow x86 method of not adding PCI resources to PCI host bridge in
ACPI code. This has been moved to pci_host_generic_acpi.c, where we
walk thru its resources of the host bridge and add them.
* Fixup code in pci_host_generic_acpi.c to read all decoded ranges
and update the 'ranges' property. This allows us to share most of
the code with generic implementation (and the FDT one).
* Parse and setup IO ranges and bus ranges when walking the resources
above. Drop most of the changes related to this from acpica code.
* Add the ECAM memory area as mem resource 0. Implement the logic to
get the ECAM area from MCFG (using bus range which we now decode),
or from _CBA (using _BBN/bus range). Drop aarch64 ifdefs from acpica
code which did part of this.
* Switch resource activation to similar code as FDT implementation,
this can be moved into generic implementation in a later pass.
* Drop the mechanism of using the 7th bit of bus number as the domain,
this is not correct and will work only in very specific cases. Use
_SEG as PCI domain and use the bus ranges of the host bridge to
provide start bus number.
This commit should not make any functional change to dev/acpica/acpi.c
for other architectures, almost all the changes there are to revert
earlier additions in this file done for aarch64.
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D17791
Modified:
head/sys/dev/acpica/acpi.c
head/sys/dev/pci/pci_host_generic_acpi.c
Modified: head/sys/dev/acpica/acpi.c
==
--- head/sys/dev/acpica/acpi.c Mon Nov 19 03:02:47 2018(r340598)
+++ head/sys/dev/acpica/acpi.c Mon Nov 19 03:16:16 2018(r340599)
@@ -179,9 +179,7 @@ static int acpi_child_location_str_method(device_t acd
char *buf, size_t buflen);
static int acpi_child_pnpinfo_str_method(device_t acdev, device_t child,
char *buf, size_t buflen);
-#if defined(__i386__) || defined(__amd64__)
static voidacpi_enable_pcie(void);
-#endif
static voidacpi_hint_device_unit(device_t acdev, device_t child,
const char *name, int *unitp);
static voidacpi_reset_interfaces(device_t dev);
@@ -502,10 +500,8 @@ acpi_attach(device_t dev)
goto out;
}
-#if defined(__i386__) || defined(__amd64__)
/* Handle MCFG table if present. */
acpi_enable_pcie();
-#endif
/*
* Note that some systems (specifically, those with namespace evaluation
@@ -1286,11 +1282,10 @@ acpi_set_resource(device_t dev, device_t child, int ty
struct acpi_softc *sc = device_get_softc(dev);
struct acpi_device *ad = device_get_ivars(child);
struct resource_list *rl = >ad_rl;
-#if defined(__i386__) || defined(__amd64__)
ACPI_DEVICE_INFO *devinfo;
-#endif
rman_res_t end;
-
+int allow;
+
/* Ignore IRQ resources for PCI link devices. */
if (type == SYS_RES_IRQ &&
ACPI_ID_PROBE(dev, child, pcilink_ids, NULL) <= 0)
@@ -1305,11 +1300,15 @@ acpi_set_resource(device_t dev, device_t child, int ty
* x86 of a PCI bridge claiming the I/O ports used for PCI config
* access.
*/
-#if defined(__i386__) || defined(__amd64__)
if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) {
if (ACPI_SUCCESS(AcpiGetObjectInfo(ad->ad_handle, ))) {
if ((devinfo->Flags & ACPI_PCI_ROOT_BRIDGE) != 0) {
- if (!(type == SYS_RES_IOPORT && start == CONF1_ADDR_PORT)) {
+#if defined(__i386__) || defined(__amd64__)
+ allow = (type == SYS_RES_IOPORT && start == CONF1_ADDR_PORT);
+#else
+ allow = 0;
+#endif
+ if (!allow) {
AcpiOsFree(devinfo);
return (0);
}
@@ -1317,7 +1316,6 @@ acpi_set_resource(device_t dev, device_t child, int ty
AcpiOsFree(devinfo);
}
}
-#endif
#ifdef INTRNG
/* map with default for now */
@@ -1874,15 +1872,18 @@ acpi_isa_pnp_probe(device_t bus, device_t child, struc
return_VALUE (result);
}
-#if defined(__i386__) || defined(__amd64__)
/*
* Look for a MCFG table. If it is present, use the settings for
* domain (segment) 0 to setup PCI config space access via the memory
* map.
+ *
+ * On non-x86 architectures (arm64 for now), this will be done from the
+ * PCI host bridge driver.
*/
static void
acpi_enable_pcie(void)
{
+#if defined(__i386__) || defined(__amd64__)
svn commit: r340598 - in head/sys: arm/arm dev/acpica
Author: jchandra
Date: Mon Nov 19 03:02:47 2018
New Revision: 340598
URL: https://svnweb.freebsd.org/changeset/base/340598
Log:
acpica: rework INTRNG interrupts
On arm64 (where INTRNG is enabled), the interrupts have to be mapped
with ACPI_BUS_MAP_INTR() before adding them as resources to devices.
The earlier code did the mapping before calling acpi_set_resource(),
which bypassed code that checked for PCI link interrupts.
To fix this, move the call to map interrupts into acpi_set_resource()
and that requires additional work to lookup interrupt properties.
The changes here are to:
* extend acpi_lookup_irq_handler() to lookup an irq in the ACPI
resources
* create a helper function acpi_map_intr() which uses the updated
acpi_lookup_irq_handler() to look up an irq, and then map it
with ACPI_BUS_MAP_INTR()
* use acpi_map_intr() in acpi_pcib_route_interrupt() to map
pci link interrupts.
With these changes, we can drop the ifdefs in acpi_resource.c, and
we can also drop the call for mapping interrupts in generic_timer.c
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D17790
Modified:
head/sys/arm/arm/generic_timer.c
head/sys/dev/acpica/acpi.c
head/sys/dev/acpica/acpi_pcib.c
head/sys/dev/acpica/acpi_resource.c
head/sys/dev/acpica/acpivar.h
Modified: head/sys/arm/arm/generic_timer.c
==
--- head/sys/arm/arm/generic_timer.cMon Nov 19 02:55:18 2018
(r340597)
+++ head/sys/arm/arm/generic_timer.cMon Nov 19 03:02:47 2018
(r340598)
@@ -72,7 +72,6 @@ __FBSDID("$FreeBSD$");
#ifdef DEV_ACPI
#include
#include
-#include "acpi_bus_if.h"
#endif
#defineGT_CTRL_ENABLE (1 << 0)
@@ -340,8 +339,6 @@ static void
arm_tmr_acpi_add_irq(device_t parent, device_t dev, int rid, u_int irq)
{
- irq = ACPI_BUS_MAP_INTR(parent, dev, irq,
- INTR_TRIGGER_LEVEL, INTR_POLARITY_HIGH);
BUS_SET_RESOURCE(parent, dev, SYS_RES_IRQ, rid, irq, 1);
}
Modified: head/sys/dev/acpica/acpi.c
==
--- head/sys/dev/acpica/acpi.c Mon Nov 19 02:55:18 2018(r340597)
+++ head/sys/dev/acpica/acpi.c Mon Nov 19 03:02:47 2018(r340598)
@@ -1319,6 +1319,13 @@ acpi_set_resource(device_t dev, device_t child, int ty
}
#endif
+#ifdef INTRNG
+/* map with default for now */
+if (type == SYS_RES_IRQ)
+ start = (rman_res_t)acpi_map_intr(child, (u_int)start,
+ acpi_get_handle(child));
+#endif
+
/* If the resource is already allocated, fail. */
if (resource_list_busy(rl, type, rid))
return (EBUSY);
Modified: head/sys/dev/acpica/acpi_pcib.c
==
--- head/sys/dev/acpica/acpi_pcib.c Mon Nov 19 02:55:18 2018
(r340597)
+++ head/sys/dev/acpica/acpi_pcib.c Mon Nov 19 03:02:47 2018
(r340598)
@@ -188,6 +188,7 @@ acpi_pcib_route_interrupt(device_t pcib, device_t dev,
ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
+lnkdev = NULL;
interrupt = PCI_INVALID_IRQ;
/* ACPI numbers pins 0-3, not 1-4 like the BIOS. */
@@ -252,7 +253,12 @@ acpi_pcib_route_interrupt(device_t pcib, device_t dev,
out:
ACPI_SERIAL_END(pcib);
-
+#ifdef INTRNG
+if (PCI_INTERRUPT_VALID(interrupt)) {
+ interrupt = acpi_map_intr(dev, interrupt, lnkdev);
+ KASSERT(PCI_INTERRUPT_VALID(interrupt), ("mapping fail"));
+}
+#endif
return_VALUE(interrupt);
}
Modified: head/sys/dev/acpica/acpi_resource.c
==
--- head/sys/dev/acpica/acpi_resource.c Mon Nov 19 02:55:18 2018
(r340597)
+++ head/sys/dev/acpica/acpi_resource.c Mon Nov 19 03:02:47 2018
(r340598)
@@ -55,10 +55,13 @@ ACPI_MODULE_NAME("RESOURCE")
struct lookup_irq_request {
ACPI_RESOURCE *acpi_res;
-struct resource *res;
+u_int irq;
intcounter;
intrid;
intfound;
+intcheckrid;
+inttrig;
+intpol;
};
static ACPI_STATUS
@@ -66,18 +69,22 @@ acpi_lookup_irq_handler(ACPI_RESOURCE *res, void *cont
{
struct lookup_irq_request *req;
size_t len;
-u_int irqnum, irq;
+u_int irqnum, irq, trig, pol;
switch (res->Type) {
case ACPI_RESOURCE_TYPE_IRQ:
irqnum = res->Data.Irq.InterruptCount;
irq = res->Data.Irq.Interrupts[0];
len = ACPI_RS_SIZE(ACPI_RESOURCE_IRQ);
+ trig = res->Data.Irq.Triggering;
+ pol = res->Data.Irq.Polarity;
break;
case ACPI_RESOURCE_TYPE_EXTENDED_IRQ:
irqnum = res->Data.ExtendedIrq.InterruptCount;
irq = res->Data.ExtendedIrq.Interrupts[0];
len =
svn commit: r340597 - head/sys/dev/pci
Author: jchandra
Date: Mon Nov 19 02:55:18 2018
New Revision: 340597
URL: https://svnweb.freebsd.org/changeset/base/340597
Log:
pci_host_generic*: basic implementation of bus range
Both ACPI and FDT support bus ranges for pci host bridges. Update
pci_host_generic*.[ch] with a default implementation to support this.
This will be used in the next set of changes for ACPI based host
bridge. No functional changes in this commit.
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D17657
Modified:
head/sys/dev/pci/pci_host_generic.c
head/sys/dev/pci/pci_host_generic.h
head/sys/dev/pci/pci_host_generic_acpi.c
head/sys/dev/pci/pci_host_generic_fdt.c
Modified: head/sys/dev/pci/pci_host_generic.c
==
--- head/sys/dev/pci/pci_host_generic.c Mon Nov 19 02:43:34 2018
(r340596)
+++ head/sys/dev/pci/pci_host_generic.c Mon Nov 19 02:55:18 2018
(r340597)
@@ -147,13 +147,14 @@ generic_pcie_read_config(device_t dev, u_int bus, u_in
uint64_t offset;
uint32_t data;
- if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) ||
- (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))
+ sc = device_get_softc(dev);
+ if ((bus < sc->bus_start) || (bus > sc->bus_end))
return (~0U);
+ if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) ||
+ (reg > PCIE_REGMAX))
+ return (~0U);
- sc = device_get_softc(dev);
-
- offset = PCIE_ADDR_OFFSET(bus, slot, func, reg);
+ offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg);
t = sc->bst;
h = sc->bsh;
@@ -183,14 +184,15 @@ generic_pcie_write_config(device_t dev, u_int bus, u_i
bus_space_tag_t t;
uint64_t offset;
- if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) ||
- (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))
+ sc = device_get_softc(dev);
+ if ((bus < sc->bus_start) || (bus > sc->bus_end))
return;
+ if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) ||
+ (reg > PCIE_REGMAX))
+ return;
- sc = device_get_softc(dev);
+ offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg);
- offset = PCIE_ADDR_OFFSET(bus, slot, func, reg);
-
t = sc->bst;
h = sc->bsh;
@@ -221,14 +223,11 @@ generic_pcie_read_ivar(device_t dev, device_t child, i
uintptr_t *result)
{
struct generic_pcie_core_softc *sc;
- int secondary_bus;
sc = device_get_softc(dev);
if (index == PCIB_IVAR_BUS) {
- /* this pcib adds only pci bus 0 as child */
- secondary_bus = 0;
- *result = secondary_bus;
+ *result = sc->bus_start;
return (0);
}
Modified: head/sys/dev/pci/pci_host_generic.h
==
--- head/sys/dev/pci/pci_host_generic.h Mon Nov 19 02:43:34 2018
(r340596)
+++ head/sys/dev/pci/pci_host_generic.h Mon Nov 19 02:55:18 2018
(r340597)
@@ -56,6 +56,8 @@ struct generic_pcie_core_softc {
struct rman io_rman;
struct resource *res;
struct resource *res1;
+ int bus_start;
+ int bus_end;
int ecam;
bus_space_tag_t bst;
bus_space_handle_t bsh;
Modified: head/sys/dev/pci/pci_host_generic_acpi.c
==
--- head/sys/dev/pci/pci_host_generic_acpi.cMon Nov 19 02:43:34 2018
(r340596)
+++ head/sys/dev/pci/pci_host_generic_acpi.cMon Nov 19 02:55:18 2018
(r340597)
@@ -125,7 +125,7 @@ pci_host_generic_acpi_attach(device_t dev)
struct generic_pcie_acpi_softc *sc;
ACPI_HANDLE handle;
ACPI_STATUS status;
- int error;
+ int error, bus_start;
sc = device_get_softc(dev);
@@ -136,10 +136,14 @@ pci_host_generic_acpi_attach(device_t dev)
device_printf(dev, "Bus is%s cache-coherent\n",
sc->base.coherent ? "" : " not");
- if (!ACPI_FAILURE(acpi_GetInteger(handle, "_BBN", >base.ecam)))
- sc->base.ecam >>= 7;
- else
+ if (!ACPI_FAILURE(acpi_GetInteger(handle, "_BBN", _start))) {
+ sc->base.ecam = bus_start >> 7;
+ sc->base.bus_start = bus_start & 0x7F;
+ } else {
sc->base.ecam = 0;
+ sc->base.bus_start = 0;
+ }
+ sc->base.bus_end = 0xFF;
acpi_pcib_fetch_prt(dev, >ap_prt);
@@ -194,17 +198,12 @@ static int
generic_pcie_acpi_read_ivar(device_t dev, device_t child, int index,
uintptr_t *result)
{
- ACPI_HANDLE handle;
struct generic_pcie_acpi_softc *sc;
- int secondary_bus;
sc =
svn commit: r340596 - head/sys/dev/pci
Author: jchandra
Date: Mon Nov 19 02:43:34 2018
New Revision: 340596
URL: https://svnweb.freebsd.org/changeset/base/340596
Log:
pci_host_generic: allocate resources against devices
Fix up pci_host_generic.c and pci_host_generic_fdt.c to allocate
resources against devices that requested them. Currently the
allocation happens against the pcib, which is incorrect.
This is needed for the upcoming changes for fixing up
pci_host_generic_acpi.c
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D17656
Modified:
head/sys/dev/pci/pci_host_generic.c
head/sys/dev/pci/pci_host_generic_fdt.c
Modified: head/sys/dev/pci/pci_host_generic.c
==
--- head/sys/dev/pci/pci_host_generic.c Mon Nov 19 02:38:02 2018
(r340595)
+++ head/sys/dev/pci/pci_host_generic.c Mon Nov 19 02:43:34 2018
(r340596)
@@ -310,7 +310,7 @@ pci_host_generic_core_alloc_resource(device_t dev, dev
rm = generic_pcie_rman(sc, type);
if (rm == NULL)
- return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
+ return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
type, rid, start, end, count, flags));
if (bootverbose) {
Modified: head/sys/dev/pci/pci_host_generic_fdt.c
==
--- head/sys/dev/pci/pci_host_generic_fdt.c Mon Nov 19 02:38:02 2018
(r340595)
+++ head/sys/dev/pci/pci_host_generic_fdt.c Mon Nov 19 02:43:34 2018
(r340596)
@@ -423,6 +423,7 @@ generic_pcie_fdt_activate_resource(device_t dev, devic
}
break;
case SYS_RES_MEMORY:
+ case SYS_RES_IRQ:
res = BUS_ACTIVATE_RESOURCE(device_get_parent(dev), child,
type, rid, r);
break;
@@ -445,6 +446,7 @@ generic_pcie_fdt_deactivate_resource(device_t dev, dev
switch(type) {
case SYS_RES_IOPORT:
case SYS_RES_MEMORY:
+ case SYS_RES_IRQ:
res = BUS_DEACTIVATE_RESOURCE(device_get_parent(dev), child,
type, rid, r);
break;
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svn commit: r340595 - head/sys/dev/pci
Author: jchandra
Date: Mon Nov 19 02:38:02 2018
New Revision: 340595
URL: https://svnweb.freebsd.org/changeset/base/340595
Log:
pci_host_generic: remove unneeded ThunderX2 quirk
The current quirk implementation writes a fixed address to the PCI BAR
to fix a firmware bug. The PCI BARs are allocated by firmware and will
change depending on PCI devices present. So using a fixed address here
is not correct.
This quirk worked around a firmware bug that programmed the MSI-X bar
of the SATA controller incorrectly. The newer firmware does not have
this issue, so it is better to drop this quirk altogether.
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D17655
Modified:
head/sys/dev/pci/pci_host_generic.c
Modified: head/sys/dev/pci/pci_host_generic.c
==
--- head/sys/dev/pci/pci_host_generic.c Mon Nov 19 02:30:12 2018
(r340594)
+++ head/sys/dev/pci/pci_host_generic.c Mon Nov 19 02:38:02 2018
(r340595)
@@ -69,25 +69,6 @@ __FBSDID("$FreeBSD$");
(((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \
((reg) & PCIE_REG_MASK))
-typedef void (*pci_host_generic_quirk_function)(device_t);
-
-struct pci_host_generic_quirk_entry {
- int impl;
- int part;
- int var;
- int rev;
- pci_host_generic_quirk_function func;
-};
-
-struct pci_host_generic_block_entry {
- int impl;
- int part;
- int var;
- int rev;
- int bus;
- int slot;
-};
-
/* Forward prototypes */
static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
@@ -100,24 +81,6 @@ static int generic_pcie_read_ivar(device_t dev, device
static int generic_pcie_write_ivar(device_t dev, device_t child, int index,
uintptr_t value);
-#if defined(__aarch64__)
-static void pci_host_generic_apply_quirks(device_t);
-static void thunderx2_ahci_bar_quirk(device_t);
-
-struct pci_host_generic_quirk_entry pci_host_generic_quirks[] =
-{
- {CPU_IMPL_CAVIUM, CPU_PART_THUNDERX2, 0, 0, thunderx2_ahci_bar_quirk},
- {0, 0, 0, 0, NULL}
-};
-
-struct pci_host_generic_block_entry pci_host_generic_blocked[] =
-{
- /* ThunderX2 AHCI on second socket */
- {CPU_IMPL_CAVIUM, CPU_PART_THUNDERX2, 0, 0, 0x80, 0x10},
- {0, 0, 0, 0, 0, 0}
-};
-#endif
-
int
pci_host_generic_core_attach(device_t dev)
{
@@ -171,34 +134,9 @@ pci_host_generic_core_attach(device_t dev)
return (error);
}
-#if defined(__aarch64__)
- pci_host_generic_apply_quirks(dev);
-#endif
-
return (0);
}
-#if defined(__aarch64__)
-static void
-pci_host_generic_apply_quirks(device_t dev)
-{
- struct pci_host_generic_quirk_entry *quirk;
-
- quirk = pci_host_generic_quirks;
- while (1) {
- if (quirk->impl == 0)
- break;
-
- if (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK,
- quirk->impl, quirk->part, quirk->var, quirk->rev) &&
- quirk->func != NULL)
- quirk->func(dev);
-
- quirk++;
- }
-}
-#endif
-
static uint32_t
generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
u_int func, u_int reg, int bytes)
@@ -208,29 +146,11 @@ generic_pcie_read_config(device_t dev, u_int bus, u_in
bus_space_tag_t t;
uint64_t offset;
uint32_t data;
-#if defined(__aarch64__)
- struct pci_host_generic_block_entry *block;
-#endif
if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) ||
(func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))
return (~0U);
-#if defined(__aarch64__)
- block = pci_host_generic_blocked;
- while (1) {
- if (block->impl == 0)
- break;
-
- if (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK,
- block->impl, block->part, block->var, block->rev) &&
- block->bus == bus && block->slot == slot)
- return (~0);
-
- block++;
- }
-#endif
-
sc = device_get_softc(dev);
offset = PCIE_ADDR_OFFSET(bus, slot, func, reg);
@@ -472,22 +392,3 @@ static device_method_t generic_pcie_methods[] = {
DEFINE_CLASS_0(pcib, generic_pcie_core_driver,
generic_pcie_methods, sizeof(struct generic_pcie_core_softc));
-
-#if defined(__aarch64__)
-static void thunderx2_ahci_bar_quirk(device_t dev)
-{
-
- /*
-* XXX:
-* On ThunderX2, AHCI BAR2 address is wrong. It needs to precisely
-* match the one described in datasheet. Fixup it unconditionally.
-*/
- if (device_get_unit(dev) == 0) {
- device_printf(dev, "running AHCI BAR fixup\n");
- PCIB_WRITE_CONFIG(dev, 0, 16, 0, 0x18, 0x0144, 4);
- PCIB_WRITE_CONFIG(dev, 0, 16, 0, 0x1c, 0x40, 4);
- PCIB_WRITE_CONFIG(dev, 0, 16, 1, 0x18,
svn commit: r339517 - head/sys/arm/arm
Author: jchandra
Date: Sun Oct 21 02:12:26 2018
New Revision: 339517
URL: https://svnweb.freebsd.org/changeset/base/339517
Log:
arm generic_timer: fix armv8 timer desc
In the FDT based probe, check for "arm,armv8-timer" before "arm,armv7-timer".
This gets the description right when the timer node has both entries in
compatible list.
Modified:
head/sys/arm/arm/generic_timer.c
Modified: head/sys/arm/arm/generic_timer.c
==
--- head/sys/arm/arm/generic_timer.cSun Oct 21 02:08:57 2018
(r339516)
+++ head/sys/arm/arm/generic_timer.cSun Oct 21 02:12:26 2018
(r339517)
@@ -323,11 +323,11 @@ arm_tmr_fdt_probe(device_t dev)
if (!ofw_bus_status_okay(dev))
return (ENXIO);
- if (ofw_bus_is_compatible(dev, "arm,armv7-timer")) {
- device_set_desc(dev, "ARMv7 Generic Timer");
- return (BUS_PROBE_DEFAULT);
- } else if (ofw_bus_is_compatible(dev, "arm,armv8-timer")) {
+ if (ofw_bus_is_compatible(dev, "arm,armv8-timer")) {
device_set_desc(dev, "ARMv8 Generic Timer");
+ return (BUS_PROBE_DEFAULT);
+ } else if (ofw_bus_is_compatible(dev, "arm,armv7-timer")) {
+ device_set_desc(dev, "ARMv7 Generic Timer");
return (BUS_PROBE_DEFAULT);
}
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svn commit: r314318 - head/sys/dev/uart
Author: jchandra
Date: Sun Feb 26 22:05:22 2017
New Revision: 314318
URL: https://svnweb.freebsd.org/changeset/base/314318
Log:
Enable pl011 UART FIFOs
The pl011 UART has a 16 entry Tx FIFO and a 16 entry Rx FIFO that
have not been used so far. Update the driver to enable the FIFOs
and use them in transmit and receive.
Reviewed by: andrew
Differential Revision:https://reviews.freebsd.org/D8819
Modified:
head/sys/dev/uart/uart_dev_pl011.c
Modified: head/sys/dev/uart/uart_dev_pl011.c
==
--- head/sys/dev/uart/uart_dev_pl011.c Sun Feb 26 21:33:18 2017
(r314317)
+++ head/sys/dev/uart/uart_dev_pl011.c Sun Feb 26 22:05:22 2017
(r314318)
@@ -61,6 +61,7 @@ __FBSDID("$FreeBSD$");
#defineDR_OE (1 << 11) /* Overrun error */
#defineUART_FR 0x06/* Flag register */
+#defineFR_RXFE (1 << 4)/* Receive FIFO/reg empty */
#defineFR_TXFF (1 << 5)/* Transmit FIFO/reg full */
#defineFR_RXFF (1 << 6)/* Receive FIFO/reg full */
#defineFR_TXFE (1 << 7)/* Transmit FIFO/reg empty */
@@ -171,9 +172,9 @@ uart_pl011_param(struct uart_bas *bas, i
line |= LCR_H_PEN;
else
line &= ~LCR_H_PEN;
+ line |= LCR_H_FEN;
/* Configure the rest */
- line &= ~LCR_H_FEN;
ctrl |= (CR_RXE | CR_TXE | CR_UARTEN);
if (bas->rclk != 0 && baudrate != 0) {
@@ -219,7 +220,7 @@ static int
uart_pl011_rxready(struct uart_bas *bas)
{
- return (__uart_getreg(bas, UART_FR) & FR_RXFF);
+ return !(__uart_getreg(bas, UART_FR) & FR_RXFE);
}
static int
@@ -417,8 +418,8 @@ uart_pl011_bus_probe(struct uart_softc *
device_set_desc(sc->sc_dev, "PrimeCell UART (PL011)");
- sc->sc_rxfifosz = 1;
- sc->sc_txfifosz = 1;
+ sc->sc_rxfifosz = 16;
+ sc->sc_txfifosz = 16;
return (0);
}
@@ -440,7 +441,6 @@ uart_pl011_bus_receive(struct uart_softc
break;
}
- __uart_setreg(bas, UART_ICR, (UART_RXREADY | RIS_RTIM));
xc = __uart_getreg(bas, UART_DR);
rx = xc & 0xff;
@@ -481,20 +481,12 @@ uart_pl011_bus_transmit(struct uart_soft
uart_barrier(bas);
}
- /* If not empty wait until it is */
- if ((__uart_getreg(bas, UART_FR) & FR_TXFE) != FR_TXFE) {
- sc->sc_txbusy = 1;
-
- /* Enable TX interrupt */
- __uart_setreg(bas, UART_IMSC, psc->imsc);
- }
+ /* Mark busy and enable TX interrupt */
+ sc->sc_txbusy = 1;
+ __uart_setreg(bas, UART_IMSC, psc->imsc);
uart_unlock(sc->sc_hwmtx);
- /* No interrupt expected, schedule the next fifo write */
- if (!sc->sc_txbusy)
- uart_sched_softih(sc, SER_INT_TXIDLE);
-
return (0);
}
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svn commit: r310289 - head/sys/dev/uart
Author: jchandra
Date: Mon Dec 19 19:40:11 2016
New Revision: 310289
URL: https://svnweb.freebsd.org/changeset/base/310289
Log:
Fix whitespace issues in pl011 uart driver
Fix up trailing whitespace introduced by r310190. While there,
fix a couple of earlier whitespace errors as well.
Modified:
head/sys/dev/uart/uart_dev_pl011.c
Modified: head/sys/dev/uart/uart_dev_pl011.c
==
--- head/sys/dev/uart/uart_dev_pl011.c Mon Dec 19 19:39:02 2016
(r310288)
+++ head/sys/dev/uart/uart_dev_pl011.c Mon Dec 19 19:40:11 2016
(r310289)
@@ -173,7 +173,7 @@ uart_pl011_param(struct uart_bas *bas, i
line &= ~LCR_H_PEN;
/* Configure the rest */
- line &= ~LCR_H_FEN;
+ line &= ~LCR_H_FEN;
ctrl |= (CR_RXE | CR_TXE | CR_UARTEN);
if (bas->rclk != 0 && baudrate != 0) {
@@ -196,7 +196,7 @@ uart_pl011_init(struct uart_bas *bas, in
/* Mask all interrupts */
__uart_setreg(bas, UART_IMSC, __uart_getreg(bas, UART_IMSC) &
~IMSC_MASK_ALL);
-
+
uart_pl011_param(bas, baudrate, databits, stopbits, parity);
}
@@ -307,7 +307,7 @@ uart_pl011_bus_attach(struct uart_softc
struct uart_pl011_softc *psc;
struct uart_bas *bas;
- psc = (struct uart_pl011_softc *)sc;
+ psc = (struct uart_pl011_softc *)sc;
bas = >sc_bas;
/* Enable interrupts */
@@ -373,7 +373,7 @@ uart_pl011_bus_ipend(struct uart_softc *
uint32_t ints;
int ipend;
- psc = (struct uart_pl011_softc *)sc;
+ psc = (struct uart_pl011_softc *)sc;
bas = >sc_bas;
uart_lock(sc->sc_hwmtx);
@@ -472,7 +472,7 @@ uart_pl011_bus_transmit(struct uart_soft
struct uart_bas *bas;
int i;
- psc = (struct uart_pl011_softc *)sc;
+ psc = (struct uart_pl011_softc *)sc;
bas = >sc_bas;
uart_lock(sc->sc_hwmtx);
@@ -504,7 +504,7 @@ uart_pl011_bus_grab(struct uart_softc *s
struct uart_pl011_softc *psc;
struct uart_bas *bas;
- psc = (struct uart_pl011_softc *)sc;
+ psc = (struct uart_pl011_softc *)sc;
bas = >sc_bas;
/* Disable interrupts on switch to polling */
@@ -519,7 +519,7 @@ uart_pl011_bus_ungrab(struct uart_softc
struct uart_pl011_softc *psc;
struct uart_bas *bas;
- psc = (struct uart_pl011_softc *) sc;
+ psc = (struct uart_pl011_softc *)sc;
bas = >sc_bas;
/* Switch to using interrupts while not grabbed */
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svn commit: r310206 - head/sys/arm64/conf
Author: jchandra Date: Sun Dec 18 11:15:31 2016 New Revision: 310206 URL: https://svnweb.freebsd.org/changeset/base/310206 Log: Add virtio_pci to GENERIC arm64 conf virtio_pci was missing from the GENERIC arm64 configuration, while other virtio devices are present. Adding it will allow us to boot the GENERIC kernel on QEMU with virtio storage and networking. Modified: head/sys/arm64/conf/GENERIC Modified: head/sys/arm64/conf/GENERIC == --- head/sys/arm64/conf/GENERIC Sun Dec 18 09:32:23 2016(r310205) +++ head/sys/arm64/conf/GENERIC Sun Dec 18 11:15:31 2016(r310206) @@ -101,6 +101,7 @@ device al_udma # Universal DMA # VirtIO support device virtio +device virtio_pci device virtio_mmio device virtio_blk device vtnet ___ svn-src-all@freebsd.org mailing list https://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscr...@freebsd.org"
svn commit: r310204 - in head/sys: arm/arm arm64/arm64
Author: jchandra Date: Sun Dec 18 08:31:01 2016 New Revision: 310204 URL: https://svnweb.freebsd.org/changeset/base/310204 Log: Initialize GIC[DR]_IGROUPRn registers for GICv3 In case where GICD_CTLR.DS is 1, the IGROUPR registers are RW in non-secure state and has to be initialized to 1 for the corresponding interrupts to be delivered as Group 1 interrupts. Update gic_v3_dist_init() and gic_v3_redist_init() to initialize GICD_IGROUPRn and GICR_IGROUPRn respectively to address this. The registers can be set unconditionally since the writes are ignored in non-secure state when GICD_CTLR.DS is 0. This fixes the hang on boot seen when running qemu-system-aarch64 with machine virt,gic-version=3 Modified: head/sys/arm/arm/gic_common.h head/sys/arm64/arm64/gic_v3.c head/sys/arm64/arm64/gic_v3_reg.h Modified: head/sys/arm/arm/gic_common.h == --- head/sys/arm/arm/gic_common.h Sun Dec 18 05:36:04 2016 (r310203) +++ head/sys/arm/arm/gic_common.h Sun Dec 18 08:31:01 2016 (r310204) @@ -66,6 +66,7 @@ __BUS_ACCESSOR(gic, bus, GIC, BUS, u_int #define GICD_IIDR_IMPL(x) \ (((x) & GICD_IIDR_IMPL_MASK) >> GICD_IIDR_IMPL_SHIFT) #defineGICD_IGROUPR(n) (0x0080 + (((n) >> 5) * 4)) /* v1 ICDISER */ +#define GICD_I_PER_IGROUPRn32 #defineGICD_ISENABLER(n) (0x0100 + (((n) >> 5) * 4)) /* v1 ICDISER */ #define GICD_I_MASK(n) (1ul << ((n) & 0x1f)) #define GICD_I_PER_ISENABLERn 32 Modified: head/sys/arm64/arm64/gic_v3.c == --- head/sys/arm64/arm64/gic_v3.c Sun Dec 18 05:36:04 2016 (r310203) +++ head/sys/arm64/arm64/gic_v3.c Sun Dec 18 08:31:01 2016 (r310204) @@ -1040,6 +1040,10 @@ gic_v3_dist_init(struct gic_v3_softc *sc /* * 2. Configure the Distributor */ + /* Set all SPIs to be Group 1 Non-secure */ + for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i += GICD_I_PER_IGROUPRn) + gic_d_write(sc, 4, GICD_IGROUPR(i), 0x); + /* Set all global interrupts to be level triggered, active low. */ for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i += GICD_I_PER_ICFGRn) gic_d_write(sc, 4, GICD_ICFGR(i), 0x); @@ -1206,6 +1210,10 @@ gic_v3_redist_init(struct gic_v3_softc * if (err != 0) return (err); + /* Configure SGIs and PPIs to be Group1 Non-secure */ + gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_IGROUPR0, + 0x); + /* Disable SPIs */ gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_ICENABLER0, GICR_I_ENABLER_PPI_MASK); Modified: head/sys/arm64/arm64/gic_v3_reg.h == --- head/sys/arm64/arm64/gic_v3_reg.h Sun Dec 18 05:36:04 2016 (r310203) +++ head/sys/arm64/arm64/gic_v3_reg.h Sun Dec 18 08:31:01 2016 (r310204) @@ -194,6 +194,7 @@ #defineGICR_VLPI_BASE_SIZE PAGE_SIZE_64K #defineGICR_RESERVED_SIZE PAGE_SIZE_64K +#defineGICR_IGROUPR0 (0x0080) #defineGICR_ISENABLER0 (0x0100) #defineGICR_ICENABLER0 (0x0180) #defineGICR_I_ENABLER_SGI_MASK (0x) ___ svn-src-all@freebsd.org mailing list https://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscr...@freebsd.org"
svn commit: r310190 - head/sys/dev/uart
Author: jchandra
Date: Sat Dec 17 18:04:59 2016
New Revision: 310190
URL: https://svnweb.freebsd.org/changeset/base/310190
Log:
Simplify interrupt mask programming in pl011 uart
Remove unused fields from uart_pl011_softc. Add an interrupt mask
field to the softc and use it to set the interrupt mask register.
There should be no functional change introduced here except in the
grab and ungrab functions. In these functions, we now disable and
enable all interrupts rather than just the receive interrupt.
Modified:
head/sys/dev/uart/uart_dev_pl011.c
Modified: head/sys/dev/uart/uart_dev_pl011.c
==
--- head/sys/dev/uart/uart_dev_pl011.c Sat Dec 17 18:03:03 2016
(r310189)
+++ head/sys/dev/uart/uart_dev_pl011.c Sat Dec 17 18:04:59 2016
(r310190)
@@ -238,13 +238,8 @@ uart_pl011_getc(struct uart_bas *bas, st
* High-level UART interface.
*/
struct uart_pl011_softc {
- struct uart_softc base;
- uint8_t fcr;
- uint8_t ier;
- uint8_t mcr;
-
- uint8_t ier_mask;
- uint8_t ier_rxbits;
+ struct uart_softc base;
+ uint16_timsc; /* Interrupt mask */
};
static int uart_pl011_bus_attach(struct uart_softc *);
@@ -309,14 +304,15 @@ UART_ACPI_CLASS_AND_DEVICE(acpi_compat_d
static int
uart_pl011_bus_attach(struct uart_softc *sc)
{
+ struct uart_pl011_softc *psc;
struct uart_bas *bas;
- int reg;
+ psc = (struct uart_pl011_softc *)sc;
bas = >sc_bas;
/* Enable interrupts */
- reg = (UART_RXREADY | RIS_RTIM | UART_TXEMPTY);
- __uart_setreg(bas, UART_IMSC, reg);
+ psc->imsc = (UART_RXREADY | RIS_RTIM | UART_TXEMPTY);
+ __uart_setreg(bas, UART_IMSC, psc->imsc);
/* Clear interrupts */
__uart_setreg(bas, UART_ICR, IMSC_MASK_ALL);
@@ -372,12 +368,14 @@ uart_pl011_bus_ioctl(struct uart_softc *
static int
uart_pl011_bus_ipend(struct uart_softc *sc)
{
+ struct uart_pl011_softc *psc;
struct uart_bas *bas;
uint32_t ints;
int ipend;
- int reg;
+ psc = (struct uart_pl011_softc *)sc;
bas = >sc_bas;
+
uart_lock(sc->sc_hwmtx);
ints = __uart_getreg(bas, UART_MIS);
ipend = 0;
@@ -393,9 +391,7 @@ uart_pl011_bus_ipend(struct uart_softc *
ipend |= SER_INT_TXIDLE;
/* Disable TX interrupt */
- reg = __uart_getreg(bas, UART_IMSC);
- reg &= ~(UART_TXEMPTY);
- __uart_setreg(bas, UART_IMSC, reg);
+ __uart_setreg(bas, UART_IMSC, psc->imsc & ~UART_TXEMPTY);
}
uart_unlock(sc->sc_hwmtx);
@@ -472,10 +468,11 @@ uart_pl011_bus_setsig(struct uart_softc
static int
uart_pl011_bus_transmit(struct uart_softc *sc)
{
+ struct uart_pl011_softc *psc;
struct uart_bas *bas;
- int reg;
int i;
+ psc = (struct uart_pl011_softc *)sc;
bas = >sc_bas;
uart_lock(sc->sc_hwmtx);
@@ -489,9 +486,7 @@ uart_pl011_bus_transmit(struct uart_soft
sc->sc_txbusy = 1;
/* Enable TX interrupt */
- reg = __uart_getreg(bas, UART_IMSC);
- reg |= (UART_TXEMPTY);
- __uart_setreg(bas, UART_IMSC, reg);
+ __uart_setreg(bas, UART_IMSC, psc->imsc);
}
uart_unlock(sc->sc_hwmtx);
@@ -506,23 +501,29 @@ uart_pl011_bus_transmit(struct uart_soft
static void
uart_pl011_bus_grab(struct uart_softc *sc)
{
+ struct uart_pl011_softc *psc;
struct uart_bas *bas;
+ psc = (struct uart_pl011_softc *)sc;
bas = >sc_bas;
+
+ /* Disable interrupts on switch to polling */
uart_lock(sc->sc_hwmtx);
- __uart_setreg(bas, UART_IMSC, /* Switch to RX polling while grabbed */
- ~UART_RXREADY & __uart_getreg(bas, UART_IMSC));
+ __uart_setreg(bas, UART_IMSC, psc->imsc & ~IMSC_MASK_ALL);
uart_unlock(sc->sc_hwmtx);
}
static void
uart_pl011_bus_ungrab(struct uart_softc *sc)
{
+ struct uart_pl011_softc *psc;
struct uart_bas *bas;
+ psc = (struct uart_pl011_softc *) sc;
bas = >sc_bas;
+
+ /* Switch to using interrupts while not grabbed */
uart_lock(sc->sc_hwmtx);
- __uart_setreg(bas, UART_IMSC, /* Switch to RX interrupts while not
grabbed */
- UART_RXREADY | __uart_getreg(bas, UART_IMSC));
+ __uart_setreg(bas, UART_IMSC, psc->imsc);
uart_unlock(sc->sc_hwmtx);
}
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svn commit: r309892 - head/sys/arm/arm
Author: jchandra
Date: Mon Dec 12 15:35:57 2016
New Revision: 309892
URL: https://svnweb.freebsd.org/changeset/base/309892
Log:
Fix gic_cpu_mask() calculation in ARM GIC
r309616 changed the definition of GICD_ITARGETSR(n) to take the irq
id as argument, but the usage of the macro in gic_cpu_mask() was not
updated to reflect this. This causes the cpu mask to be computed
incorrectly.
Update the GICD_ITARGETSR() call to fix this, this fixes a hang seen
while booting freebsd on qemu-system-aarch64 with SMP enabled.
Modified:
head/sys/arm/arm/gic.c
Modified: head/sys/arm/arm/gic.c
==
--- head/sys/arm/arm/gic.c Mon Dec 12 15:22:21 2016(r309891)
+++ head/sys/arm/arm/gic.c Mon Dec 12 15:35:57 2016(r309892)
@@ -190,7 +190,7 @@ gic_cpu_mask(struct arm_gic_softc *sc)
/* Read the current cpuid mask by reading ITARGETSR{0..7} */
for (i = 0; i < 8; i++) {
- mask = gic_d_read_4(sc, GICD_ITARGETSR(i));
+ mask = gic_d_read_4(sc, GICD_ITARGETSR(4 * i));
if (mask != 0)
break;
}
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svn commit: r309890 - head/sys/dev/pci
Author: jchandra
Date: Mon Dec 12 15:17:56 2016
New Revision: 309890
URL: https://svnweb.freebsd.org/changeset/base/309890
Log:
Increase interrupt cells in generic_pcie_fdt_route_interrupt
ARM GIC specification in device trees use 3 cells, so the current
limit of 2 causes the last cell to be dropped. This in turn can
cause the interrupt polarity and trigger settings to be incorrect.
Increase the limit to 4 which should handle all reasonable cases.
This fixes issues seen in QEMU when registering PCI interrupts.
Modified:
head/sys/dev/pci/pci_host_generic_fdt.c
Modified: head/sys/dev/pci/pci_host_generic_fdt.c
==
--- head/sys/dev/pci/pci_host_generic_fdt.c Mon Dec 12 13:13:48 2016
(r309889)
+++ head/sys/dev/pci/pci_host_generic_fdt.c Mon Dec 12 15:17:56 2016
(r309890)
@@ -269,7 +269,7 @@ generic_pcie_fdt_route_interrupt(device_
{
struct generic_pcie_fdt_softc *sc;
struct ofw_pci_register reg;
- uint32_t pintr, mintr[2];
+ uint32_t pintr, mintr[4];
phandle_t iparent;
int intrcells;
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svn commit: r309276 - head/sys/dev/uart
Author: jchandra Date: Tue Nov 29 04:32:14 2016 New Revision: 309276 URL: https://svnweb.freebsd.org/changeset/base/309276 Log: Fix interrupt clear in pl011 uart receive function Clear the interrupt state before reading the input char from the input FIFO. In the current code there is a window between the read to the data register and the write to the the ICR, during which an input char will not cause an interrupt. This fixes the issue by which the serial port input on QEMU freezes when using the emulated pl011 serial port. Modified: head/sys/dev/uart/uart_dev_pl011.c Modified: head/sys/dev/uart/uart_dev_pl011.c == --- head/sys/dev/uart/uart_dev_pl011.c Tue Nov 29 01:08:09 2016 (r309275) +++ head/sys/dev/uart/uart_dev_pl011.c Tue Nov 29 04:32:14 2016 (r309276) @@ -443,6 +443,8 @@ uart_pl011_bus_receive(struct uart_softc sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; break; } + + __uart_setreg(bas, UART_ICR, (UART_RXREADY | RIS_RTIM)); xc = __uart_getreg(bas, UART_DR); rx = xc & 0xff; @@ -451,8 +453,6 @@ uart_pl011_bus_receive(struct uart_softc if (xc & DR_PE) rx |= UART_STAT_PARERR; - __uart_setreg(bas, UART_ICR, (UART_RXREADY | RIS_RTIM)); - uart_rx_put(sc, rx); ints = __uart_getreg(bas, UART_MIS); } ___ svn-src-all@freebsd.org mailing list https://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscr...@freebsd.org"
svn commit: r279368 - head/sys/dev/fdt
Author: jchandra
Date: Fri Feb 27 20:11:02 2015
New Revision: 279368
URL: https://svnweb.freebsd.org/changeset/base/279368
Log:
Allow creating subclass of FDT simplebus
Provide sys/dev/fdt/simplebus.h with the class declaration so that it
is possible to subclass FDT simplebus.
Differential Revision:https://reviews.freebsd.org/D1886
Reviewed by: nwhitehorn, imp
Added:
head/sys/dev/fdt/simplebus.h (contents, props changed)
Modified:
head/sys/dev/fdt/simplebus.c
Modified: head/sys/dev/fdt/simplebus.c
==
--- head/sys/dev/fdt/simplebus.cFri Feb 27 19:23:01 2015
(r279367)
+++ head/sys/dev/fdt/simplebus.cFri Feb 27 20:11:02 2015
(r279368)
@@ -38,26 +38,7 @@ __FBSDID($FreeBSD$);
#include dev/ofw/ofw_bus.h
#include dev/ofw/ofw_bus_subr.h
-struct simplebus_range {
- uint64_t bus;
- uint64_t host;
- uint64_t size;
-};
-
-struct simplebus_softc {
- device_t dev;
- phandle_t node;
-
- struct simplebus_range *ranges;
- int nranges;
-
- pcell_t acells, scells;
-};
-
-struct simplebus_devinfo {
- struct ofw_bus_devinfo obdinfo;
- struct resource_listrl;
-};
+#include dev/fdt/simplebus.h
/*
* Bus interface.
@@ -115,11 +96,9 @@ static device_method_t simplebus_methods
DEVMETHOD_END
};
-static driver_t simplebus_driver = {
- simplebus,
- simplebus_methods,
- sizeof(struct simplebus_softc)
-};
+DEFINE_CLASS_0(simplebus, simplebus_driver, simplebus_methods,
+sizeof(struct simplebus_softc));
+
static devclass_t simplebus_devclass;
EARLY_DRIVER_MODULE(simplebus, ofwbus, simplebus_driver, simplebus_devclass,
0, 0, BUS_PASS_BUS);
Added: head/sys/dev/fdt/simplebus.h
==
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/dev/fdt/simplebus.hFri Feb 27 20:11:02 2015
(r279368)
@@ -0,0 +1,56 @@
+/*-
+ * Copyright (c) 2013 Nathan Whitehorn
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef_FDT_SIMPLEBUS_PRIVATE_H
+#define_FDT_SIMPLEBUS_PRIVATE_H
+
+/* FDT simplebus */
+DECLARE_CLASS(simplebus_driver);
+
+struct simplebus_range {
+ uint64_t bus;
+ uint64_t host;
+ uint64_t size;
+};
+
+/* devinfo and softc */
+struct simplebus_softc {
+ device_t dev;
+ phandle_t node;
+
+ struct simplebus_range *ranges;
+ int nranges;
+
+ pcell_t acells, scells;
+};
+
+struct simplebus_devinfo {
+ struct ofw_bus_devinfo obdinfo;
+ struct resource_listrl;
+};
+#endif /* _FDT_SIMPLEBUS_PRIVATE_H */
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svn commit: r279387 - in head/sys/mips/nlm: . hal
Author: jchandra
Date: Sat Feb 28 00:17:29 2015
New Revision: 279387
URL: https://svnweb.freebsd.org/changeset/base/279387
Log:
Whitespace fixes for files in sys/mips/nlm
Clean up whitespace issues under sys/mips/nlm (except dev). No
functional change in this commit.
Modified:
head/sys/mips/nlm/board.c
head/sys/mips/nlm/board.h
head/sys/mips/nlm/board_cpld.c
head/sys/mips/nlm/board_eeprom.c
head/sys/mips/nlm/bus_space_rmi_pci.c
head/sys/mips/nlm/cms.c
head/sys/mips/nlm/hal/fmn.h
head/sys/mips/nlm/hal/gbu.h
head/sys/mips/nlm/hal/interlaken.h
head/sys/mips/nlm/hal/mdio.h
head/sys/mips/nlm/hal/mips-extns.h
head/sys/mips/nlm/hal/mmu.h
head/sys/mips/nlm/hal/nae.h
head/sys/mips/nlm/hal/nlm_hal.c
head/sys/mips/nlm/hal/nlmsaelib.h
head/sys/mips/nlm/hal/pcibus.h
head/sys/mips/nlm/hal/poe.h
head/sys/mips/nlm/hal/sgmii.h
head/sys/mips/nlm/hal/ucore_loader.h
head/sys/mips/nlm/hal/usb.h
head/sys/mips/nlm/hal/xaui.h
head/sys/mips/nlm/interrupt.h
head/sys/mips/nlm/intr_machdep.c
head/sys/mips/nlm/mpreset.S
head/sys/mips/nlm/msgring.h
head/sys/mips/nlm/tick.c
head/sys/mips/nlm/uart_cpu_xlp.c
head/sys/mips/nlm/usb_init.c
head/sys/mips/nlm/xlp.h
head/sys/mips/nlm/xlp_machdep.c
head/sys/mips/nlm/xlp_pci.c
Modified: head/sys/mips/nlm/board.c
==
--- head/sys/mips/nlm/board.c Sat Feb 28 00:16:36 2015(r279386)
+++ head/sys/mips/nlm/board.c Sat Feb 28 00:17:29 2015(r279387)
@@ -71,7 +71,7 @@ static struct vfbid_tbl nlm_vfbid[] = {
{43, 1011}, {42, 1010}, {41, 1009}, {40, 1008},
{39, 1007}, {38, 1006}, {37, 1005}, {36, 1004},
{35, 1003}, {34, 1002}, {33, 1001}, {32, 1000},
- /* NAE - CPU mappings, freeback got to vc 3 of each thread */
+ /* NAE - CPU mappings, freeback got to vc 3 of each thread */
{31, 127}, {30, 123}, {29, 119}, {28, 115},
{27, 111}, {26, 107}, {25, 103}, {24, 99},
{23, 95}, {22, 91}, {21, 87}, {20, 83},
@@ -87,7 +87,7 @@ static struct vfbid_tbl nlm3xx_vfbid[] =
{127, 0}, /* NAE - NAE mappings */
{39, 503}, {38, 502}, {37, 501}, {36, 500},
{35, 499}, {34, 498}, {33, 497}, {32, 496},
- /* NAE - CPU mappings, freeback got to vc 3 of each thread */
+ /* NAE - CPU mappings, freeback got to vc 3 of each thread */
{31, 127}, {30, 123}, {29, 119}, {28, 115},
{27, 111}, {26, 107}, {25, 103}, {24, 99},
{23, 95}, {22, 91}, {21, 87}, {20, 83},
@@ -240,7 +240,7 @@ nlm_setup_port_defaults(struct xlp_port_
/* XLP 8XX evaluation boards have the following phy-addr
* assignment. There are two external mdio buses in XLP --
* bus 0 and bus 1. The management ports (16 and 17) are
- * on mdio bus 0 while blocks/complexes[0 to 3] are all
+ * on mdio bus 0 while blocks/complexes[0 to 3] are all
* on mdio bus 1. The phy_addr on bus 0 (mgmt ports 16
* and 17) match the port numbers.
* These are the details:
@@ -263,7 +263,7 @@ nlm_setup_port_defaults(struct xlp_port_
* 3 2 14 1
* 3 3 13 1
*
- * 4 0 16 0
+ * 4 0 16 0
* 4 1 17 0
*
* The XLP 3XX evaluation boards have the following phy-addr
@@ -366,7 +366,7 @@ nlm_print_processor_info(void)
}
/*
- * All our knowledge of chip and board that cannot be detected by probing
+ * All our knowledge of chip and board that cannot be detected by probing
* at run-time goes here
*/
static int
Modified: head/sys/mips/nlm/board.h
==
--- head/sys/mips/nlm/board.h Sat Feb 28 00:16:36 2015(r279386)
+++ head/sys/mips/nlm/board.h Sat Feb 28 00:17:29 2015(r279387)
@@ -5,7 +5,7 @@
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright
*notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
@@ -40,7 +40,7 @@
*/
#defineEEPROM_I2CBUS 1
#defineEEPROM_I2CADDR 0xAE
-#defineEEPROM_SIZE 48
+#defineEEPROM_SIZE 48
#defineEEPROM_MACADDR_OFFSET 2
/* used if there is no FDT */
@@ -113,7 +113,7 @@ struct xlp_block_ivars {
};
struct xlp_nae_ivars {
- int node;
+ int node;
int nblocks;
u_int blockmask;
u_int ilmask;
Modified: head/sys/mips/nlm/board_cpld.c
==
--- head/sys/mips/nlm/board_cpld.c Sat Feb 28 00:16:36 2015
(r279386)
+++ head/sys/mips/nlm/board_cpld.c Sat Feb
svn commit: r279388 - in head/sys/mips/nlm/dev: net net/ucore sec
Author: jchandra
Date: Sat Feb 28 00:22:10 2015
New Revision: 279388
URL: https://svnweb.freebsd.org/changeset/base/279388
Log:
Whitespace fixes for sys/mips/nlm/dev
Clean up whitespace issues under sys/mips/nlm/dev. No functional
change in this commit.
Modified:
head/sys/mips/nlm/dev/net/mdio.c
head/sys/mips/nlm/dev/net/nae.c
head/sys/mips/nlm/dev/net/sgmii.c
head/sys/mips/nlm/dev/net/ucore/crt0_basic.S
head/sys/mips/nlm/dev/net/ucore/ld.ucore.S
head/sys/mips/nlm/dev/net/ucore/ucore.h
head/sys/mips/nlm/dev/net/ucore/ucore_app.c
head/sys/mips/nlm/dev/net/xaui.c
head/sys/mips/nlm/dev/net/xlpge.c
head/sys/mips/nlm/dev/net/xlpge.h
head/sys/mips/nlm/dev/sec/nlmrsa.c
head/sys/mips/nlm/dev/sec/nlmrsalib.h
head/sys/mips/nlm/dev/sec/nlmsec.c
head/sys/mips/nlm/dev/sec/nlmseclib.c
head/sys/mips/nlm/dev/sec/nlmseclib.h
head/sys/mips/nlm/dev/sec/rsa_ucode.h
Modified: head/sys/mips/nlm/dev/net/mdio.c
==
--- head/sys/mips/nlm/dev/net/mdio.cSat Feb 28 00:17:29 2015
(r279387)
+++ head/sys/mips/nlm/dev/net/mdio.cSat Feb 28 00:22:10 2015
(r279388)
@@ -12,7 +12,7 @@
*notice, this list of conditions and the following disclaimer in
*the documentation and/or other materials provided with the
*distribution.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -48,14 +48,14 @@ nlm_int_gmac_mdio_read(uint64_t nae_base
uint32_t mdio_ld_cmd;
uint32_t ctrlval;
- ctrlval = INT_MDIO_CTRL_SMP |
+ ctrlval = INT_MDIO_CTRL_SMP |
(phyaddr INT_MDIO_CTRL_PHYADDR_POS) |
(regidx INT_MDIO_CTRL_DEVTYPE_POS) |
(2 INT_MDIO_CTRL_OP_POS) |
(1 INT_MDIO_CTRL_ST_POS) |
- (7 INT_MDIO_CTRL_XDIV_POS) |
+ (7 INT_MDIO_CTRL_XDIV_POS) |
(2 INT_MDIO_CTRL_TA_POS) |
- (2 INT_MDIO_CTRL_MIIM_POS) |
+ (2 INT_MDIO_CTRL_MIIM_POS) |
(1 INT_MDIO_CTRL_MCDIV_POS);
mdio_ld_cmd = nlm_read_nae_reg(nae_base,
@@ -148,16 +148,16 @@ nlm_int_gmac_mdio_reset(uint64_t nae_bas
{
uint32_t val;
- val = (7 INT_MDIO_CTRL_XDIV_POS) |
+ val = (7 INT_MDIO_CTRL_XDIV_POS) |
(1 INT_MDIO_CTRL_MCDIV_POS) |
(INT_MDIO_CTRL_SMP);
nlm_write_nae_reg(nae_base,
- NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
+ NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
val | INT_MDIO_CTRL_RST);
nlm_write_nae_reg(nae_base,
- NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
+ NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
val);
return (0);
@@ -185,7 +185,7 @@ nlm_gmac_mdio_read(uint64_t nae_base, in
(EXT_G0_MDIO_CTRL + bus * 4)));
if (mdio_ld_cmd EXT_G_MDIO_CMD_LCD) {
nlm_write_nae_reg(nae_base,
- NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
+ NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
(mdio_ld_cmd ~EXT_G_MDIO_CMD_LCD));
while(nlm_read_nae_reg(nae_base,
NAE_REG(block, intf_type,
@@ -197,16 +197,16 @@ nlm_gmac_mdio_read(uint64_t nae_base, in
(phyaddr EXT_G_MDIO_PHYADDR_POS) |
(regidx EXT_G_MDIO_REGADDR_POS);
if (nlm_is_xlp8xx_ax() || nlm_is_xlp8xx_b0() || nlm_is_xlp3xx_ax())
- ctrlval |= EXT_G_MDIO_DIV;
+ ctrlval |= EXT_G_MDIO_DIV;
else
ctrlval |= EXT_G_MDIO_DIV_WITH_HW_DIV64;
- nlm_write_nae_reg(nae_base,
- NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
ctrlval);
nlm_write_nae_reg(nae_base,
- NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
+ NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
ctrlval | (118));
DELAY(1000);
/* poll master busy bit until it is not busy */
@@ -215,7 +215,7 @@ nlm_gmac_mdio_read(uint64_t nae_base, in
EXT_G_MDIO_STAT_MBSY);
nlm_write_nae_reg(nae_base,
- NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
+ NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
ctrlval);
/* Read the data back */
@@ -246,7 +246,7 @@ nlm_gmac_mdio_write(uint64_t nae_base, i
(EXT_G0_MDIO_CTRL + bus * 4)));
if (mdio_ld_cmd EXT_G_MDIO_CMD_LCD) {
nlm_write_nae_reg(nae_base,
- NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
+
svn commit: r279384 - in head/sys/mips/nlm: . dev
Author: jchandra
Date: Fri Feb 27 23:33:53 2015
New Revision: 279384
URL: https://svnweb.freebsd.org/changeset/base/279384
Log:
Add subclass of simplebus for Broadcom XLP
This will override the resource allocation of simplebus, and also
merge the resource allocation code which was in xlp_pci.c.
With this change the SoC devices that does not have proper PCI
resources will be on the FDT simplebus. We can remove
sys/mips/nlm/dev/cfi_pci_xlp.c and sys/mips/nlm/dev/uart_pci_xlp.c
Added:
head/sys/mips/nlm/xlp_simplebus.c (contents, props changed)
Deleted:
head/sys/mips/nlm/dev/cfi_pci_xlp.c
head/sys/mips/nlm/dev/uart_pci_xlp.c
Modified:
head/sys/mips/nlm/files.xlp
head/sys/mips/nlm/xlp_pci.c
Modified: head/sys/mips/nlm/files.xlp
==
--- head/sys/mips/nlm/files.xlp Fri Feb 27 23:14:08 2015(r279383)
+++ head/sys/mips/nlm/files.xlp Fri Feb 27 23:33:53 2015(r279384)
@@ -11,14 +11,11 @@ mips/nlm/bus_space_rmi_pci.cstandard
mips/nlm/mpreset.S standard
mips/nlm/board_eeprom.cstandard
mips/nlm/board_cpld.c standard
+mips/nlm/xlp_simplebus.c optional fdt
mips/nlm/xlp_pci.c optional pci
mips/nlm/uart_cpu_xlp.coptional uart
mips/nlm/usb_init.coptional usb
#
-# Simple SoC devices
-mips/nlm/dev/uart_pci_xlp.coptional uart
-mips/nlm/dev/cfi_pci_xlp.c optional cfi
-#
# Network driver and micro-core code
mips/nlm/dev/net/nae.c optional xlpge
mips/nlm/dev/net/mdio.coptional xlpge
Modified: head/sys/mips/nlm/xlp_pci.c
==
--- head/sys/mips/nlm/xlp_pci.c Fri Feb 27 23:14:08 2015(r279383)
+++ head/sys/mips/nlm/xlp_pci.c Fri Feb 27 23:33:53 2015(r279384)
@@ -52,6 +52,7 @@ __FBSDID($FreeBSD$);
#include dev/uart/uart_bus.h
#include dev/uart/uart_cpu.h
+#include dev/ofw/openfirm.h
#include dev/ofw/ofw_bus.h
#include dev/ofw/ofw_bus_subr.h
@@ -74,169 +75,21 @@ __FBSDID($FreeBSD$);
#include pcib_if.h
#include pci_if.h
-#defineEMUL_MEM_START 0x1600UL
-#defineEMUL_MEM_END0x18ffUL
-
-/* Override PCI a bit for SoC devices */
-
-enum {
- INTERNAL_DEV= 0x1, /* internal device, skip on enumeration */
- MEM_RES_EMUL= 0x2, /* no MEM or IO bar, custom res alloc */
- SHARED_IRQ = 0x4,
- DEV_MMIO32 = 0x8, /* byte access not allowed to mmio */
-};
-
-struct xlp_devinfo {
- struct pci_devinfo pcidev;
- int irq;
- int flags;
- u_long mem_res_start;
-};
-
-static struct resource *
-xlp_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
-u_long start, u_long end, u_long count, u_int flags)
-{
- struct resource *r;
- struct xlp_devinfo *xlp_devinfo;
- int busno;
-
- /*
-* Do custom allocation for MEMORY resource for SoC device if
-* MEM_RES_EMUL flag is set
-*/
- busno = pci_get_bus(child);
- if ((type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) busno == 0) {
- xlp_devinfo = (struct xlp_devinfo *)device_get_ivars(child);
- if ((xlp_devinfo-flags MEM_RES_EMUL) != 0) {
- /* no emulation for IO ports */
- if (type == SYS_RES_IOPORT)
- return (NULL);
-
- start = xlp_devinfo-mem_res_start;
- count = XLP_PCIE_CFG_SIZE - XLP_IO_PCI_HDRSZ;
-
- /* MMC needs to 2 slots with rids 16 and 20 and a
-* fixup for size */
- if (pci_get_device(child) == PCI_DEVICE_ID_NLM_MMC) {
- count = 0x100;
- if (*rid == 16)
- ; /* first slot already setup */
- else if (*rid == 20)
- start += 0x100; /* second slot */
- else
- return (NULL);
- }
-
- end = start + count - 1;
- r = BUS_ALLOC_RESOURCE(device_get_parent(bus), child,
- type, rid, start, end, count, flags);
- if (r == NULL)
- return (NULL);
- if ((xlp_devinfo-flags DEV_MMIO32) != 0)
- rman_set_bustag(r, rmi_uart_bus_space);
- return (r);
- }
- }
-
- /* Not custom alloc, use PCI code */
- return
svn commit: r279341 - head/sys/mips/nlm
Author: jchandra
Date: Fri Feb 27 00:57:09 2015
New Revision: 279341
URL: https://svnweb.freebsd.org/changeset/base/279341
Log:
Improve additional interrupt ACK for Broadcom XLP
Handling some interrupts in XLP (like PCIe and SATA) involves writing to
vendor specific registers as part of interrupt acknowledgement.
This was earlier done with xlp_establish_intr(), but a better solution
is to provide a function xlp_set_bus_ack() that can be used with
cpu_establish_hardintr(). This will allow platform initialization code to
setup these ACKs without changing the standrard drivers.
Modified:
head/sys/mips/nlm/interrupt.h
head/sys/mips/nlm/intr_machdep.c
head/sys/mips/nlm/xlp_pci.c
Modified: head/sys/mips/nlm/interrupt.h
==
--- head/sys/mips/nlm/interrupt.h Fri Feb 27 00:54:53 2015
(r279340)
+++ head/sys/mips/nlm/interrupt.h Fri Feb 27 00:57:09 2015
(r279341)
@@ -68,9 +68,7 @@
* XLR needs custom pre and post handlers for PCI/PCI-e interrupts
* XXX: maybe follow i386 intsrc model
*/
-void xlp_establish_intr(const char *name, driver_filter_t filt,
-driver_intr_t handler, void *arg, int irq, int flags,
-void **cookiep, void (*busack)(int));
void xlp_enable_irq(int irq);
+void xlp_set_bus_ack(int irq, void (*ack)(int, void *), void *arg);
#endif /* _RMI_INTERRUPT_H_ */
Modified: head/sys/mips/nlm/intr_machdep.c
==
--- head/sys/mips/nlm/intr_machdep.cFri Feb 27 00:54:53 2015
(r279340)
+++ head/sys/mips/nlm/intr_machdep.cFri Feb 27 00:57:09 2015
(r279341)
@@ -58,7 +58,8 @@ __FBSDID($FreeBSD$);
#include mips/nlm/xlp.h
struct xlp_intrsrc {
- void (*busack)(int);/* Additional ack */
+ void (*bus_ack)(int, void *); /* Additional ack */
+ void *bus_ack_arg; /* arg for additional ack */
struct intr_event *ie; /* event corresponding to intr */
int irq;
int irt;
@@ -119,23 +120,13 @@ cpu_establish_softintr(const char *name,
panic(Soft interrupts unsupported!\n);
}
-void
-cpu_establish_hardintr(const char *name, driver_filter_t * filt,
-void (*handler) (void *), void *arg, int irq, int flags,
-void **cookiep)
-{
-
- xlp_establish_intr(name, filt, handler, arg, irq, flags,
- cookiep, NULL);
-}
-
static void
xlp_post_filter(void *source)
{
struct xlp_intrsrc *src = source;
- if (src-busack)
- src-busack(src-irq);
+ if (src-bus_ack)
+ src-bus_ack(src-irq, src-bus_ack_arg);
nlm_pic_ack(xlp_pic_base, src-irt);
}
@@ -144,8 +135,8 @@ xlp_pre_ithread(void *source)
{
struct xlp_intrsrc *src = source;
- if (src-busack)
- src-busack(src-irq);
+ if (src-bus_ack)
+ src-bus_ack(src-irq, src-bus_ack_arg);
}
static void
@@ -157,19 +148,35 @@ xlp_post_ithread(void *source)
}
void
-xlp_establish_intr(const char *name, driver_filter_t filt,
-driver_intr_t handler, void *arg, int irq, int flags,
-void **cookiep, void (*busack)(int))
+xlp_set_bus_ack(int irq, void (*ack)(int, void *), void *arg)
+{
+ struct xlp_intrsrc *src;
+
+ KASSERT(irq 0 irq = XLR_MAX_INTR,
+ (%s called for bad hard intr %d, __func__, irq));
+
+ /* no locking needed - this will called early in boot */
+ src = xlp_interrupts[irq];
+ KASSERT(src-ie != NULL,
+ (%s called after IRQ enable for %d., __func__, irq));
+ src-bus_ack_arg = arg;
+ src-bus_ack = ack;
+}
+
+void
+cpu_establish_hardintr(const char *name, driver_filter_t * filt,
+void (*handler) (void *), void *arg, int irq, int flags,
+void **cookiep)
{
struct intr_event *ie; /* descriptor for the IRQ */
struct xlp_intrsrc *src = NULL;
int errcode;
- if (irq 0 || irq XLR_MAX_INTR)
- panic(%s called for unknown hard intr %d, __func__, irq);
+ KASSERT(irq 0 irq = XLR_MAX_INTR ,
+ (%s called for bad hard intr %d, __func__, irq));
/*
-* FIXME locking - not needed now, because we do this only on
+* Locking - not needed now, because we do this only on
* startup from CPU0
*/
src = xlp_interrupts[irq];
@@ -194,7 +201,6 @@ xlp_establish_intr(const char *name, dri
return;
}
src-irq = irq;
- src-busack = busack;
src-ie = ie;
}
if (XLP_IRQ_IS_PICINTR(irq)) {
Modified: head/sys/mips/nlm/xlp_pci.c
==
--- head/sys/mips/nlm/xlp_pci.c Fri Feb 27 00:54:53 2015(r279340)
+++ head/sys/mips/nlm/xlp_pci.c Fri Feb 27 00:57:09 2015(r279341)
@@
svn commit: r279345 - in head/sys: boot/fdt/dts/mips mips/nlm
Author: jchandra
Date: Fri Feb 27 02:21:52 2015
New Revision: 279345
URL: https://svnweb.freebsd.org/changeset/base/279345
Log:
Move PCI bus below simplebus for Broadcom XLP
This will enable us to do common allocation code for memory and
interrupts for SoC devices as well as PCI devices.
Modified:
head/sys/boot/fdt/dts/mips/xlp-basic.dts
head/sys/mips/nlm/xlp_pci.c
Modified: head/sys/boot/fdt/dts/mips/xlp-basic.dts
==
--- head/sys/boot/fdt/dts/mips/xlp-basic.dtsFri Feb 27 01:59:29 2015
(r279344)
+++ head/sys/boot/fdt/dts/mips/xlp-basic.dtsFri Feb 27 02:21:52 2015
(r279345)
@@ -65,6 +65,10 @@
interrupts = 17;
};
+ pci0: pci@1800 {
+ compatible = netlogic,xlp-pci, pci;
+ reg = 0xd000 0x1000;
+ };
};
chosen {
Modified: head/sys/mips/nlm/xlp_pci.c
==
--- head/sys/mips/nlm/xlp_pci.c Fri Feb 27 01:59:29 2015(r279344)
+++ head/sys/mips/nlm/xlp_pci.c Fri Feb 27 02:21:52 2015(r279345)
@@ -52,6 +52,9 @@ __FBSDID($FreeBSD$);
#include dev/uart/uart_bus.h
#include dev/uart/uart_cpu.h
+#include dev/ofw/ofw_bus.h
+#include dev/ofw/ofw_bus_subr.h
+
#include machine/bus.h
#include machine/md_var.h
#include machine/intr_machdep.h
@@ -281,7 +284,6 @@ DEFINE_CLASS_1(pci, xlp_pci_driver, xlp_
pci_driver);
DRIVER_MODULE(xlp_pci, pcib, xlp_pci_driver, pci_devclass, 0, 0);
-static devclass_t pcib_devclass;
static struct rman irq_rman, port_rman, mem_rman, emul_rman;
static void
@@ -328,8 +330,11 @@ static int
xlp_pcib_probe(device_t dev)
{
- device_set_desc(dev, XLP PCI bus);
- return (BUS_PROBE_NOWILDCARD);
+ if (ofw_bus_is_compatible(dev, netlogic,xlp-pci)) {
+ device_set_desc(dev, XLP PCI bus);
+ return (BUS_PROBE_DEFAULT);
+ }
+ return (ENXIO);
}
static int
@@ -481,13 +486,6 @@ xlp_pcib_attach(device_t dev)
return (0);
}
-static void
-xlp_pcib_identify(driver_t * driver, device_t parent)
-{
-
- BUS_ADD_CHILD(parent, 0, pcib, 0);
-}
-
/*
* XLS PCIe can have upto 4 links, and each link has its on IRQ
* Find the link on which the device is on
@@ -780,7 +778,6 @@ mips_pcib_route_interrupt(device_t bus,
static device_method_t xlp_pcib_methods[] = {
/* Device interface */
- DEVMETHOD(device_identify, xlp_pcib_identify),
DEVMETHOD(device_probe, xlp_pcib_probe),
DEVMETHOD(device_attach, xlp_pcib_attach),
@@ -813,4 +810,5 @@ static driver_t xlp_pcib_driver = {
1, /* no softc */
};
-DRIVER_MODULE(pcib, nexus, xlp_pcib_driver, pcib_devclass, 0, 0);
+static devclass_t pcib_devclass;
+DRIVER_MODULE(xlp_pcib, simplebus, xlp_pcib_driver, pcib_devclass, 0, 0);
___
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svn commit: r279305 - in head/sys: boot/fdt/dts/mips mips/nlm
Author: jchandra
Date: Thu Feb 26 02:05:45 2015
New Revision: 279305
URL: https://svnweb.freebsd.org/changeset/base/279305
Log:
Add netlogic,xlp-pic as interrupt controller for XLP
Add an empty driver for netlogic,xlp-pic to ensure that the device tree
is correct and has an interrupt controller.
Modified:
head/sys/boot/fdt/dts/mips/xlp-basic.dts
head/sys/mips/nlm/intr_machdep.c
Modified: head/sys/boot/fdt/dts/mips/xlp-basic.dts
==
--- head/sys/boot/fdt/dts/mips/xlp-basic.dtsThu Feb 26 01:53:24 2015
(r279304)
+++ head/sys/boot/fdt/dts/mips/xlp-basic.dtsThu Feb 26 02:05:45 2015
(r279305)
@@ -47,12 +47,21 @@
ranges = 0x0 0x1800 0x0400;
bus-frequency = 0;
+ pic: pic@4000 {
+ compatible = netlogic,xlp-pic;
+ interrupt-controller;
+ #address-cells = 0;
+ #interrupt-cells = 1;
+ reg = 0x4000 0x200;
+ };
+
serial0: serial@30100 {
compatible = ns16550;
reg = 0x30100 0x200;
reg-shift = 2;
current-speed = 115200;
clock-frequency = 13300;
+ interrupt-parent = pic;
interrupts = 9;
};
Modified: head/sys/mips/nlm/intr_machdep.c
==
--- head/sys/mips/nlm/intr_machdep.cThu Feb 26 01:53:24 2015
(r279304)
+++ head/sys/mips/nlm/intr_machdep.cThu Feb 26 02:05:45 2015
(r279305)
@@ -35,6 +35,10 @@ __FBSDID($FreeBSD$);
#include sys/bus.h
#include sys/interrupt.h
#include sys/kernel.h
+#include sys/module.h
+
+#include dev/ofw/ofw_bus.h
+#include dev/ofw/ofw_bus_subr.h
#include machine/cpu.h
#include machine/cpufunc.h
@@ -251,3 +255,39 @@ cpu_init_interrupts()
mips_intr_counters[i] = mips_intrcnt_create(name);
}
}
+
+static int xlp_pic_probe(device_t);
+static int xlp_pic_attach(device_t);
+
+static int
+xlp_pic_probe(device_t dev)
+{
+
+ if (!ofw_bus_is_compatible(dev, netlogic,xlp-pic))
+ return (ENXIO);
+ device_set_desc(dev, XLP PIC);
+ return (0);
+}
+
+static int
+xlp_pic_attach(device_t dev)
+{
+
+ return (0);
+}
+
+static device_method_t xlp_pic_methods[] = {
+ DEVMETHOD(device_probe, xlp_pic_probe),
+ DEVMETHOD(device_attach,xlp_pic_attach),
+
+ DEVMETHOD_END
+};
+
+static driver_t xlp_pic_driver = {
+ xlp_pic,
+ xlp_pic_methods,
+ 1, /* no softc */
+};
+
+static devclass_t xlp_pic_devclass;
+DRIVER_MODULE(xlp_pic, simplebus, xlp_pic_driver, xlp_pic_devclass, 0, 0);
___
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svn commit: r279306 - in head/sys: boot/fdt/dts/mips mips/nlm
Author: jchandra
Date: Thu Feb 26 02:22:47 2015
New Revision: 279306
URL: https://svnweb.freebsd.org/changeset/base/279306
Log:
Remove run-time allocation of XLP IRQs
Follow the same static IRQ to Interrupt Table Entry mapping as the other
OS supported on XLP.
Modified:
head/sys/boot/fdt/dts/mips/xlp-basic.dts
head/sys/mips/nlm/interrupt.h
head/sys/mips/nlm/intr_machdep.c
head/sys/mips/nlm/xlp.h
head/sys/mips/nlm/xlp_pci.c
Modified: head/sys/boot/fdt/dts/mips/xlp-basic.dts
==
--- head/sys/boot/fdt/dts/mips/xlp-basic.dtsThu Feb 26 02:05:45 2015
(r279305)
+++ head/sys/boot/fdt/dts/mips/xlp-basic.dtsThu Feb 26 02:22:47 2015
(r279306)
@@ -62,7 +62,7 @@
current-speed = 115200;
clock-frequency = 13300;
interrupt-parent = pic;
- interrupts = 9;
+ interrupts = 17;
};
};
Modified: head/sys/mips/nlm/interrupt.h
==
--- head/sys/mips/nlm/interrupt.h Thu Feb 26 02:05:45 2015
(r279305)
+++ head/sys/mips/nlm/interrupt.h Thu Feb 26 02:22:47 2015
(r279306)
@@ -43,13 +43,26 @@
#defineXLP_IRQ_IS_PICINTR(irq) ((irq) = PIC_IRQ_BASE \
(irq) = PIC_IRT_LAST_IRQ)
-#definePIC_UART_0_IRQ 9
-#definePIC_PCIE_0_IRQ 11
-#definePIC_PCIE_1_IRQ 12
-#definePIC_PCIE_2_IRQ 13
-#definePIC_PCIE_3_IRQ 14
-#definePIC_EHCI_0_IRQ 16
-#definePIC_MMC_IRQ 21
+#definePIC_UART_0_IRQ 17
+#definePIC_UART_1_IRQ 18
+
+#definePIC_PCIE_0_IRQ 19
+#definePIC_PCIE_1_IRQ 20
+#definePIC_PCIE_2_IRQ 21
+#definePIC_PCIE_3_IRQ 22
+#definePIC_PCIE_IRQ(l) (PIC_PCIE_0_IRQ + (l))
+
+#definePIC_USB_0_IRQ 23
+#definePIC_USB_1_IRQ 24
+#definePIC_USB_2_IRQ 25
+#definePIC_USB_3_IRQ 26
+#definePIC_USB_4_IRQ 27
+#definePIC_USB_IRQ(n) (PIC_USB_0_IRQ + (n))
+
+#definePIC_MMC_IRQ 29
+#definePIC_I2C_0_IRQ 30
+#definePIC_I2C_1_IRQ 31
+#definePIC_I2C_IRQ(n) (PIC_I2C_0_IRQ + (n))
/*
* XLR needs custom pre and post handlers for PCI/PCI-e interrupts
Modified: head/sys/mips/nlm/intr_machdep.c
==
--- head/sys/mips/nlm/intr_machdep.cThu Feb 26 02:05:45 2015
(r279305)
+++ head/sys/mips/nlm/intr_machdep.cThu Feb 26 02:22:47 2015
(r279306)
@@ -61,12 +61,46 @@ struct xlp_intrsrc {
void (*busack)(int);/* Additional ack */
struct intr_event *ie; /* event corresponding to intr */
int irq;
+ int irt;
};
static struct xlp_intrsrc xlp_interrupts[XLR_MAX_INTR];
static mips_intrcnt_t mips_intr_counters[XLR_MAX_INTR];
static int intrcnt_index;
+int
+xlp_irq_to_irt(int irq)
+{
+ uint32_t offset;
+
+ switch (irq) {
+ case PIC_UART_0_IRQ:
+ case PIC_UART_1_IRQ:
+ offset = XLP_IO_UART_OFFSET(0, irq - PIC_UART_0_IRQ);
+ return (xlp_socdev_irt(offset));
+ case PIC_PCIE_0_IRQ:
+ case PIC_PCIE_1_IRQ:
+ case PIC_PCIE_2_IRQ:
+ case PIC_PCIE_3_IRQ:
+ offset = XLP_IO_PCIE_OFFSET(0, irq - PIC_PCIE_0_IRQ);
+ return (xlp_socdev_irt(offset));
+ case PIC_USB_0_IRQ:
+ case PIC_USB_1_IRQ:
+ case PIC_USB_2_IRQ:
+ case PIC_USB_3_IRQ:
+ case PIC_USB_4_IRQ:
+ offset = XLP_IO_USB_OFFSET(0, irq - PIC_USB_0_IRQ);
+ return (xlp_socdev_irt(offset));
+ case PIC_I2C_0_IRQ:
+ case PIC_I2C_1_IRQ:
+ offset = XLP_IO_I2C0_OFFSET(0);
+ return (xlp_socdev_irt(offset) + irq - PIC_I2C_0_IRQ);
+ default:
+ printf(ERROR: %s: unknown irq %d\n, __func__, irq);
+ return (-1);
+ }
+}
+
void
xlp_enable_irq(int irq)
{
@@ -102,7 +136,7 @@ xlp_post_filter(void *source)
if (src-busack)
src-busack(src-irq);
- nlm_pic_ack(xlp_pic_base, xlp_irq_to_irt(src-irq));
+ nlm_pic_ack(xlp_pic_base, src-irt);
}
static void
@@ -119,7 +153,7 @@ xlp_post_ithread(void *source)
{
struct xlp_intrsrc *src = source;
- nlm_pic_ack(xlp_pic_base, xlp_irq_to_irt(src-irq));
+ nlm_pic_ack(xlp_pic_base, src-irt);
}
void
@@ -163,6 +197,13 @@ xlp_establish_intr(const char *name, dri
src-busack = busack;
src-ie = ie;
}
+ if
svn commit: r279304 - in head/sys/mips/nlm: . hal
Author: jchandra Date: Thu Feb 26 01:53:24 2015 New Revision: 279304 URL: https://svnweb.freebsd.org/changeset/base/279304 Log: Fix up interrupt definitions for Broadcom XLP Gather all the IRQ definitions to interrupt.h. Earlier these were in xlp.h and pic.h. Update the definition of XLP_IRQ_IS_PICINTR to check for last irq as well. Modified: head/sys/mips/nlm/hal/pic.h head/sys/mips/nlm/interrupt.h head/sys/mips/nlm/xlp.h Modified: head/sys/mips/nlm/hal/pic.h == --- head/sys/mips/nlm/hal/pic.h Wed Feb 25 22:41:27 2015(r279303) +++ head/sys/mips/nlm/hal/pic.h Thu Feb 26 01:53:24 2015(r279304) @@ -168,14 +168,9 @@ #definePIC_IRT_TIMER_INDEX(num)((num) + PIC_IRT_TIMER_0_INDEX) #definePIC_CLOCK_TIMER 7 -#definePIC_IRQ_BASE8 #if !defined(LOCORE) !defined(__ASSEMBLY__) -#definePIC_IRT_FIRST_IRQ (PIC_IRQ_BASE) -#definePIC_IRT_LAST_IRQ63 -#defineXLP_IRQ_IS_PICINTR(irq) ((irq) = PIC_IRT_FIRST_IRQ) - /* * Misc */ Modified: head/sys/mips/nlm/interrupt.h == --- head/sys/mips/nlm/interrupt.h Wed Feb 25 22:41:27 2015 (r279303) +++ head/sys/mips/nlm/interrupt.h Thu Feb 26 01:53:24 2015 (r279304) @@ -34,9 +34,22 @@ /* Defines for the IRQ numbers */ -#define IRQ_IPI41 /* 8-39 are mapped by PIC intr 0-31 */ -#define IRQ_MSGRING 6 -#define IRQ_TIMER 7 +#defineIRQ_IPI 41 /* 8-39 are used by PIC interrupts */ +#defineIRQ_MSGRING 6 +#defineIRQ_TIMER 7 + +#definePIC_IRQ_BASE8 +#definePIC_IRT_LAST_IRQ39 +#defineXLP_IRQ_IS_PICINTR(irq) ((irq) = PIC_IRQ_BASE \ + (irq) = PIC_IRT_LAST_IRQ) + +#definePIC_UART_0_IRQ 9 +#definePIC_PCIE_0_IRQ 11 +#definePIC_PCIE_1_IRQ 12 +#definePIC_PCIE_2_IRQ 13 +#definePIC_PCIE_3_IRQ 14 +#definePIC_EHCI_0_IRQ 16 +#definePIC_MMC_IRQ 21 /* * XLR needs custom pre and post handlers for PCI/PCI-e interrupts Modified: head/sys/mips/nlm/xlp.h == --- head/sys/mips/nlm/xlp.h Wed Feb 25 22:41:27 2015(r279303) +++ head/sys/mips/nlm/xlp.h Thu Feb 26 01:53:24 2015(r279304) @@ -34,18 +34,6 @@ #include mips/nlm/hal/mips-extns.h #include mips/nlm/hal/iomap.h -#definePIC_UART_0_IRQ 9 - -#definePIC_PCIE_0_IRQ 11 -#definePIC_PCIE_1_IRQ 12 -#definePIC_PCIE_2_IRQ 13 -#definePIC_PCIE_3_IRQ 14 - -#definePIC_EHCI_0_IRQ 16 -#definePIC_MMC_IRQ 21 -/* 41 used by IRQ_SMP */ - - /* XLP 8xx/4xx A0, A1, A2 CPU COP0 PRIDs */ #defineCHIP_PROCESSOR_ID_XLP_8XX 0x10 #defineCHIP_PROCESSOR_ID_XLP_3XX 0x11 ___ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to svn-src-all-unsubscr...@freebsd.org
svn commit: r256045 - head/sys/mips/nlm/dev/sec
Author: jchandra
Date: Fri Oct 4 10:01:20 2013
New Revision: 256045
URL: http://svnweb.freebsd.org/changeset/base/256045
Log:
Style fixes for the Netlogic XLP RSA driver
Updates to the Netlogic XLP on-chp RSA block driver. The changes are
to follow style(9) guidelines, to improve readability and to remove
unnecessary initialization.
No changes to logic have been introduced by this commit.
Submitted by: Venkatesh J. V. venkatesh.vivekanan...@broadcom.com
Approved by: re (hrs)
Modified:
head/sys/mips/nlm/dev/sec/nlmrsa.c
head/sys/mips/nlm/dev/sec/nlmrsalib.h
Modified: head/sys/mips/nlm/dev/sec/nlmrsa.c
==
--- head/sys/mips/nlm/dev/sec/nlmrsa.c Fri Oct 4 09:02:02 2013
(r256044)
+++ head/sys/mips/nlm/dev/sec/nlmrsa.c Fri Oct 4 10:01:20 2013
(r256045)
@@ -62,14 +62,14 @@ __FBSDID($FreeBSD$);
#include mips/nlm/hal/sys.h
#include mips/nlm/hal/fmn.h
#include mips/nlm/hal/nlmsaelib.h
-#include mips/nlm/dev/sec/nlmrsalib.h
#include mips/nlm/dev/sec/rsa_ucode.h
#include mips/nlm/hal/cop2.h
#include mips/nlm/hal/mips-extns.h
#include mips/nlm/msgring.h
+#include mips/nlm/dev/sec/nlmrsalib.h
#ifdef NLM_RSA_DEBUG
-int print_krp_params(struct cryptkop *krp);
+static int print_krp_params(struct cryptkop *krp);
#endif
static int xlp_rsa_init(struct xlp_rsa_softc *sc, int node);
@@ -97,7 +97,7 @@ static device_method_t xlp_rsa_methods[]
/* crypto device methods */
DEVMETHOD(cryptodev_newsession, xlp_rsa_newsession),
- DEVMETHOD(cryptodev_freesession,xlp_rsa_freesession),
+ DEVMETHOD(cryptodev_freesession, xlp_rsa_freesession),
DEVMETHOD(cryptodev_kprocess, xlp_rsa_kprocess),
DEVMETHOD_END
@@ -113,29 +113,25 @@ static devclass_t xlp_rsa_devclass;
DRIVER_MODULE(nlmrsa, pci, xlp_rsa_driver, xlp_rsa_devclass, 0, 0);
MODULE_DEPEND(nlmrsa, crypto, 1, 1, 1);
-void
-nlm_xlprsaecc_msgring_handler(int vc, int size, int code, int src_id,
-struct nlm_fmn_msg *msg, void *data);
-
#ifdef NLM_RSA_DEBUG
-int
+static int
print_krp_params(struct cryptkop *krp)
{
int i;
- printf(krp-krp_op :%d\n,krp-krp_op);
- printf(krp-krp_status :%d\n,krp-krp_status);
- printf(krp-krp_iparams:%d\n,krp-krp_iparams);
- printf(krp-krp_oparams:%d\n,krp-krp_oparams);
- for (i=0;ikrp-krp_iparams+krp-krp_oparams;i++) {
- printf(krp-krp_param[%d].crp_p:0x%llx\n,i,
+ printf(krp-krp_op :%d\n, krp-krp_op);
+ printf(krp-krp_status :%d\n, krp-krp_status);
+ printf(krp-krp_iparams:%d\n, krp-krp_iparams);
+ printf(krp-krp_oparams:%d\n, krp-krp_oparams);
+ for (i = 0; i krp-krp_iparams + krp-krp_oparams; i++) {
+ printf(krp-krp_param[%d].crp_p:0x%llx\n, i,
(unsigned long long)krp-krp_param[i].crp_p);
- printf(krp-krp_param[%d].crp_nbits:%d\n,i,
+ printf(krp-krp_param[%d].crp_nbits:%d\n, i,
krp-krp_param[i].crp_nbits);
- printf(krp-krp_param[%d].crp_nbytes :%d\n,i,
- (krp-krp_param[i].crp_nbits+7)/8);
+ printf(krp-krp_param[%d].crp_nbytes :%d\n, i,
+ howmany(krp-krp_param[i].crp_nbits, 8));
}
- return 0;
+ return (0);
}
#endif
@@ -155,19 +151,20 @@ xlp_rsa_init(struct xlp_rsa_softc *sc, i
printf(Couldn't register rsa/ecc msgring handler\n);
goto errout;
}
- m.msg[0] = m.msg[1] = m.msg[2] = m.msg[3] = 0;
fbvc = nlm_cpuid() / CMS_MAX_VCPU_VC;
/* Do the CMS credit initialization */
/* Currently it is configured by default to 50 when kernel comes up */
- if ((cmd = malloc(sizeof(struct xlp_rsa_command), M_DEVBUF,
- M_NOWAIT | M_ZERO)) == NULL) {
+ cmd = malloc(sizeof(struct xlp_rsa_command), M_DEVBUF,
+ M_NOWAIT | M_ZERO);
+ if (cmd == NULL) {
err = ENOMEM;
printf(Failed to allocate mem for cmd\n);
goto errout;
}
size = sizeof(nlm_rsa_ucode_data);
- if ((cmd-rsasrc = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) {
+ cmd-rsasrc = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
+ if (cmd-rsasrc == NULL) {
err = ENOMEM;
printf(Failed to allocate mem for cmd-rsasrc\n);
goto errout;
@@ -184,6 +181,7 @@ xlp_rsa_init(struct xlp_rsa_softc *sc, i
vtophys(cmd-rsasrc));
/* Software scratch pad */
m.msg[2] = (uintptr_t)cmd;
+ m.msg[3] = 0;
for (dstvc = sc-rsaecc_vc_start; dstvc = sc-rsaecc_vc_end; dstvc++) {
ret = nlm_fmn_msgsend(dstvc, 3, FMN_SWCODE_RSA, m);
@@ -215,38 +213,38 @@ void
nlm_xlprsaecc_msgring_handler(int vc, int size, int code, int src_id,
struct nlm_fmn_msg *msg, void *data)
{
-
svn commit: r256046 - head/sys/mips/nlm/dev/sec
Author: jchandra
Date: Fri Oct 4 11:11:51 2013
New Revision: 256046
URL: http://svnweb.freebsd.org/changeset/base/256046
Log:
Fixes for the Netlogic XLP on-chip RSA block driver
The changes are to:
* Use contigmalloc/contigfree which handling microcode buffer
* Use a different buffer to send microcode to each engine
* Swap microcode in little-endian compilation
* Fix freeback message queue id field
* Simplify xlp_get_rsa_opsize() to remove unnecessary checks
* Fix NULL check after use in xlp_free_cmd_params()
* Do better error handling when the hardware returns error
* Fix error codes in few cases
Submitted by: Vekatesh J. V. venkatesh.vivekanan...@broadcom.com
Approved by: re (hrs)
Modified:
head/sys/mips/nlm/dev/sec/nlmrsa.c
Modified: head/sys/mips/nlm/dev/sec/nlmrsa.c
==
--- head/sys/mips/nlm/dev/sec/nlmrsa.c Fri Oct 4 10:01:20 2013
(r256045)
+++ head/sys/mips/nlm/dev/sec/nlmrsa.c Fri Oct 4 11:11:51 2013
(r256046)
@@ -34,6 +34,7 @@ __FBSDID($FreeBSD$);
#include sys/systm.h
#include sys/proc.h
#include sys/errno.h
+#include sys/endian.h
#include sys/malloc.h
#include sys/kernel.h
#include sys/module.h
@@ -69,7 +70,7 @@ __FBSDID($FreeBSD$);
#include mips/nlm/dev/sec/nlmrsalib.h
#ifdef NLM_RSA_DEBUG
-static int print_krp_params(struct cryptkop *krp);
+static void print_krp_params(struct cryptkop *krp);
#endif
static int xlp_rsa_init(struct xlp_rsa_softc *sc, int node);
@@ -114,7 +115,7 @@ DRIVER_MODULE(nlmrsa, pci, xlp_rsa_drive
MODULE_DEPEND(nlmrsa, crypto, 1, 1, 1);
#ifdef NLM_RSA_DEBUG
-static int
+static void
print_krp_params(struct cryptkop *krp)
{
int i;
@@ -131,7 +132,6 @@ print_krp_params(struct cryptkop *krp)
printf(krp-krp_param[%d].crp_nbytes :%d\n, i,
howmany(krp-krp_param[i].crp_nbits, 8));
}
- return (0);
}
#endif
@@ -139,7 +139,7 @@ static int
xlp_rsa_init(struct xlp_rsa_softc *sc, int node)
{
struct xlp_rsa_command *cmd = NULL;
- uint32_t size, fbvc, dstvc, endsel, regval;
+ uint32_t fbvc, dstvc, endsel, regval;
struct nlm_fmn_msg m;
int err, ret, i;
uint64_t base;
@@ -151,39 +151,36 @@ xlp_rsa_init(struct xlp_rsa_softc *sc, i
printf(Couldn't register rsa/ecc msgring handler\n);
goto errout;
}
- fbvc = nlm_cpuid() / CMS_MAX_VCPU_VC;
+ fbvc = nlm_cpuid() * 4 + XLPGE_FB_VC;
/* Do the CMS credit initialization */
/* Currently it is configured by default to 50 when kernel comes up */
- cmd = malloc(sizeof(struct xlp_rsa_command), M_DEVBUF,
- M_NOWAIT | M_ZERO);
- if (cmd == NULL) {
- err = ENOMEM;
- printf(Failed to allocate mem for cmd\n);
- goto errout;
- }
- size = sizeof(nlm_rsa_ucode_data);
- cmd-rsasrc = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
- if (cmd-rsasrc == NULL) {
- err = ENOMEM;
- printf(Failed to allocate mem for cmd-rsasrc\n);
- goto errout;
- }
- if (((uintptr_t)cmd-rsasrc (XLP_L2L3_CACHELINE_SIZE - 1))) {
- err = EINVAL;
- printf(cmd-rsasrc is not cacheline aligned\n);
- goto errout;
- }
- memcpy(cmd-rsasrc, (uint8_t *)nlm_rsa_ucode_data, size);
- m.msg[0] = nlm_crypto_form_rsa_ecc_fmn_entry0(1, 0x70, 0,
- vtophys(cmd-rsasrc));
- m.msg[1] = nlm_crypto_form_rsa_ecc_fmn_entry1(0, 1, fbvc,
- vtophys(cmd-rsasrc));
- /* Software scratch pad */
- m.msg[2] = (uintptr_t)cmd;
- m.msg[3] = 0;
-
+#if BYTE_ORDER == LITTLE_ENDIAN
+ for (i = 0; i nitems(nlm_rsa_ucode_data); i++)
+ nlm_rsa_ucode_data[i] = htobe64(nlm_rsa_ucode_data[i]);
+#endif
for (dstvc = sc-rsaecc_vc_start; dstvc = sc-rsaecc_vc_end; dstvc++) {
+ cmd = malloc(sizeof(struct xlp_rsa_command), M_DEVBUF,
+ M_NOWAIT | M_ZERO);
+ KASSERT(cmd != NULL, (%s:cmd is NULL\n, __func__));
+ cmd-rsasrc = contigmalloc(sizeof(nlm_rsa_ucode_data),
+ M_DEVBUF,
+ (M_WAITOK | M_ZERO),
+ 0UL /* low address */, -1UL /* high address */,
+ XLP_L2L3_CACHELINE_SIZE /* alignment */,
+ 0UL /* boundary */);
+ KASSERT(cmd-rsasrc != NULL,
+ (%s:cmd-rsasrc is NULL\n, __func__));
+ memcpy(cmd-rsasrc, nlm_rsa_ucode_data,
+ sizeof(nlm_rsa_ucode_data));
+ m.msg[0] = nlm_crypto_form_rsa_ecc_fmn_entry0(1, 0x70, 0,
+ vtophys(cmd-rsasrc));
+ m.msg[1] = nlm_crypto_form_rsa_ecc_fmn_entry1(0, 1, fbvc,
+ vtophys(cmd-rsasrc));
+ /* Software scratch pad */
+ m.msg[2]
svn commit: r255367 - in head/sys: conf mips/mips
Author: jchandra
Date: Sat Sep 7 16:31:30 2013
New Revision: 255367
URL: http://svnweb.freebsd.org/changeset/base/255367
Log:
Use a better version of memcpy/bcopy for mips kernel.
Use a variant of mips libc memcpy for kernel. This implementation uses
64-bit operations when compiled for 64-bit, and is significantly faster
in that case.
Submitted by: Tanmay Jagdale tanm...@broadcom.com
Added:
head/sys/mips/mips/bcopy.S (contents, props changed)
Modified:
head/sys/conf/files.mips
head/sys/mips/mips/support.S
Modified: head/sys/conf/files.mips
==
--- head/sys/conf/files.mipsSat Sep 7 16:16:57 2013(r255366)
+++ head/sys/conf/files.mipsSat Sep 7 16:31:30 2013(r255367)
@@ -38,6 +38,7 @@ mips/mips/stack_machdep.c optionalddb
mips/mips/stdatomic.c standard \
compile-with ${NORMAL_C:N-Wmissing-prototypes}
mips/mips/support.Sstandard
+mips/mips/bcopy.S standard
mips/mips/swtch.S standard
mips/mips/sys_machdep.cstandard
mips/mips/tlb.cstandard
Added: head/sys/mips/mips/bcopy.S
==
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/mips/mips/bcopy.S Sat Sep 7 16:31:30 2013(r255367)
@@ -0,0 +1,286 @@
+/* $NetBSD: bcopy.S,v 1.3 2009/12/14 00:39:00 matt Exp $ */
+
+/*
+ * Mach Operating System
+ * Copyright (c) 1993 Carnegie Mellon University
+ * All Rights Reserved.
+ *
+ * Permission to use, copy, modify and distribute this software and its
+ * documentation is hereby granted, provided that both the copyright
+ * notice and this permission notice appear in all copies of the
+ * software, derivative works or modified versions, and any portions
+ * thereof, and that both notices appear in supporting documentation.
+ *
+ * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS AS IS
+ * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
+ * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+ *
+ * Carnegie Mellon requests users of this software to return to
+ *
+ * Software Distribution Coordinator or software.distribut...@cs.cmu.edu
+ * School of Computer Science
+ * Carnegie Mellon University
+ * Pittsburgh PA 15213-3890
+ *
+ * any improvements or extensions that they make and grant Carnegie Mellon
+ * the rights to redistribute these changes.
+ */
+
+/*
+ * File: mips_bcopy.s
+ * Author: Chris Maeda
+ * Date: June 1993
+ *
+ * Fast copy routine. Derived from aligned_block_copy.
+ */
+
+
+#include machine/asm.h
+__FBSDID($FreeBSD$);
+
+#include machine/endian.h
+
+#if defined(LIBC_SCCS) !defined(lint)
+#if 0
+ ASMSTR(from: @(#)mips_bcopy.s 2.2 CMU 18/06/93)
+#else
+ ASMSTR($NetBSD: bcopy.S,v 1.3 2009/12/14 00:39:00 matt Exp $)
+#endif
+#endif /* LIBC_SCCS and not lint */
+
+#ifdef __ABICALLS__
+ .abicalls
+#endif
+
+/*
+ * bcopy(caddr_t src, caddr_t dst, unsigned int len)
+ *
+ * a0 src address
+ * a1 dst address
+ * a2 length
+ */
+
+#defineSRCREG a0
+#defineDSTREG a1
+#defineSIZEREG a2
+
+LEAF(memcpy)
+ .setnoat
+ .setnoreorder
+
+ movev0, a0
+ movea0, a1
+ movea1, v0
+
+ALEAF(bcopy)
+ALEAF(ovbcopy)
+ /*
+* Make sure we can copy forwards.
+*/
+ sltut0,SRCREG,DSTREG# t0 == SRCREG DSTREG
+ bne t0,zero,6f # copy backwards
+
+ /*
+* There are four alignment cases (with frequency)
+* (Based on measurements taken with a DECstation 5000/200
+* inside a Mach kernel.)
+*
+* aligned - aligned(mostly)
+* unaligned - aligned(sometimes)
+* aligned,unaligned - unaligned (almost never)
+*
+* Note that we could add another case that checks if
+* the destination and source are unaligned but the
+* copy is alignable. eg if src and dest are both
+* on a halfword boundary.
+*/
+ andit1,DSTREG,(SZREG-1) # get last bits of dest
+ bne t1,zero,3f # dest unaligned
+ andit0,SRCREG,(SZREG-1) # get last bits of src
+ bne t0,zero,5f
+
+ /*
+* Forward aligned-aligned copy, 8 words at a time.
+*/
+98:
+ li AT,-(SZREG*8)
+ and t0,SIZEREG,AT # count truncated to multiples
+ PTR_ADDUa3,SRCREG,t0# run fast loop up to this addr
+ sltuAT,SRCREG,a3# any work to do?
+ beq
svn commit: r255368 - in head/sys/mips/nlm: . dev/net hal
Author: jchandra
Date: Sat Sep 7 18:26:16 2013
New Revision: 255368
URL: http://svnweb.freebsd.org/changeset/base/255368
Log:
Netlogic XLP network driver update
Changes are to
- update board and network interface detection logic
- fix reading onboard CPLD in little-endian config
- print NAE frequency conrrectly for Bx chips
- update XAUI config to disable Rx/Tx until interface is up
Submitted by: Venkatesh J V venkatesh.vivekanan...@broadcom.com
Modified:
head/sys/mips/nlm/board.c
head/sys/mips/nlm/board.h
head/sys/mips/nlm/board_cpld.c
head/sys/mips/nlm/dev/net/nae.c
head/sys/mips/nlm/dev/net/xaui.c
head/sys/mips/nlm/dev/net/xlpge.c
head/sys/mips/nlm/dev/net/xlpge.h
head/sys/mips/nlm/hal/nae.h
head/sys/mips/nlm/hal/nlm_hal.c
head/sys/mips/nlm/hal/sys.h
Modified: head/sys/mips/nlm/board.c
==
--- head/sys/mips/nlm/board.c Sat Sep 7 16:31:30 2013(r255367)
+++ head/sys/mips/nlm/board.c Sat Sep 7 18:26:16 2013(r255368)
@@ -280,15 +280,8 @@ nlm_setup_port_defaults(struct xlp_port_
* 1 3 9 0
*/
static void
-nlm_board_get_phyaddr(int block, int port, int *mdio, int *phyaddr)
+nlm_board_get_phyaddr(int block, int port, int *phyaddr)
{
-
- /* XXXJC: this is a board feature, check for chip not proper */
- if (nlm_is_xlp3xx() || (nlm_is_xlp8xx() block == 4))
- *mdio = 0;
- else
- *mdio = 1;
-
switch (block) {
case 0: switch (port) {
case 0: *phyaddr = 4; break;
@@ -377,7 +370,7 @@ nlm_print_processor_info(void)
* at run-time goes here
*/
static int
-nlm_setup_xlp_board(void)
+nlm_setup_xlp_board(int node)
{
struct xlp_board_info *boardp;
struct xlp_node_info*nodep;
@@ -385,17 +378,18 @@ nlm_setup_xlp_board(void)
struct xlp_block_ivars *blockp;
struct xlp_port_ivars *portp;
uint64_t cpldbase, nae_pcibase;
- int node, block, port, rv, dbtype, usecpld;
+ int block, port, rv, dbtype, usecpld = 0, evp = 0, svp = 0;
uint8_t *b;
/* start with a clean slate */
boardp = xlp_board_info;
- memset(boardp, 0, sizeof(xlp_board_info));
- boardp-nodemask = 0x1; /* only node 0 */
+ if (boardp-nodemask == 0)
+ memset(boardp, 0, sizeof(xlp_board_info));
+ boardp-nodemask |= (1 node);
nlm_print_processor_info();
b = board_eeprom_buf;
- rv = nlm_board_eeprom_read(0, EEPROM_I2CBUS, EEPROM_I2CADDR, 0, b,
+ rv = nlm_board_eeprom_read(node, EEPROM_I2CBUS, EEPROM_I2CADDR, 0, b,
EEPROM_SIZE);
if (rv == 0) {
board_eeprom_set = 1;
@@ -409,80 +403,114 @@ nlm_setup_xlp_board(void)
printf(Board Info: Error on EEPROM read (i2c@%d %#X).\n,
EEPROM_I2CBUS, EEPROM_I2CADDR);
+ nae_pcibase = nlm_get_nae_pcibase(node);
+ nodep = boardp-nodes[node];
+ naep = nodep-nae_ivars;
+ naep-node = node;
+
+ /* frequency at which network block runs */
+ naep-freq = 500;
+
+ /* CRC16 polynomial used for flow table generation */
+ naep-flow_crc_poly = 0x;
+ naep-hw_parser_en = 1;
+ naep-prepad_en = 1;
+ naep-prepad_size = 3; /* size in 16 byte units */
+ naep-ieee_1588_en = 1;
+
+ naep-ilmask = 0x0; /* set this based on daughter card */
+ naep-xauimask = 0x0; /* set this based on daughter card */
+ naep-sgmiimask = 0x0; /* set this based on daughter card */
+ naep-nblocks = nae_num_complex(nae_pcibase);
+ if (strncmp(b[16], PCIE, 4) == 0) {
+ usecpld = 0; /* XLP PCIe card */
+ /* Broadcom's XLP PCIe card has the following
+* blocks fixed.
+* blk 0-XAUI, 1-XAUI, 4-SGMII(one port) */
+ naep-blockmask = 0x13;
+ } else if (strncmp(b[16], MB-EVP, 6) == 0) {
+ usecpld = 1; /* XLP non-PCIe card which has CPLD */
+ evp = 1;
+ naep-blockmask = (1 naep-nblocks) - 1;
+ } else if ((strncmp(b[16], MB-S, 4) == 0) ||
+ (strncmp(b[16], MB_S, 4) == 0)) {
+ usecpld = 1; /* XLP non-PCIe card which has CPLD */
+ svp = 1;
+ /* 3xx chip reports one block extra which is a bug */
+ naep-nblocks = naep-nblocks - 1;
+ naep-blockmask = (1 naep-nblocks) - 1;
+ } else {
+ printf(ERROR!!! Board type:%7s didn't match any board
+type we support\n, b[16]);
+ return (-1);
+ }
+ cpldbase = nlm_board_cpld_base(node, XLP_EVB_CPLD_CHIPSELECT);
- /* XXXJC: check for boards with right CPLD, for now
-*4xx PCI cards don't have CPLD with daughter
-*card info */
- usecpld = !nlm_is_xlp4xx();
+ /* pretty
svn commit: r249436 - head/sys/kern
Author: jchandra
Date: Sat Apr 13 07:23:37 2013
New Revision: 249436
URL: http://svnweb.freebsd.org/changeset/base/249436
Log:
Fix changes made in r249408.
In some cases, kern_envp is set by the architecture code and env_pos does
not contain the length of the static kernel environment. In these cases
r249408 causes the kernel to discard the environment.
Fix this by updating the check for empty static env to *kern_envp != '\0'
Reported by: np@
Modified:
head/sys/kern/kern_environment.c
Modified: head/sys/kern/kern_environment.c
==
--- head/sys/kern/kern_environment.cSat Apr 13 05:11:21 2013
(r249435)
+++ head/sys/kern/kern_environment.cSat Apr 13 07:23:37 2013
(r249436)
@@ -231,7 +231,7 @@ init_dynamic_kenv(void *data __unused)
kenvp = malloc((KENV_SIZE + 1) * sizeof(char *), M_KENV,
M_WAITOK | M_ZERO);
i = 0;
- if (env_pos 0) {
+ if (*kern_envp != '\0') {
for (cp = kern_envp; cp != NULL; cp = kernenv_next(cp)) {
len = strlen(cp) + 1;
if (len KENV_MNAMELEN + 1 + KENV_MVALLEN + 1) {
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svn commit: r249408 - head/sys/kern
Author: jchandra
Date: Fri Apr 12 15:58:53 2013
New Revision: 249408
URL: http://svnweb.freebsd.org/changeset/base/249408
Log:
Fix kenv behavior when there is no static environment
In case where there are no static kernel environment entries, the
function init_dynamic_kenv() adds an incorrect entry at position 0 of
the dynamic kernel environment. This in turn causes kenv(1) to print
and empty list even though there are dynamic entries added later.
Fix this by checking env_pos in init_dynamic_kenv() and adding dynamic
entries only if there are static entries.
Modified:
head/sys/kern/kern_environment.c
Modified: head/sys/kern/kern_environment.c
==
--- head/sys/kern/kern_environment.cFri Apr 12 15:19:35 2013
(r249407)
+++ head/sys/kern/kern_environment.cFri Apr 12 15:58:53 2013
(r249408)
@@ -231,20 +231,23 @@ init_dynamic_kenv(void *data __unused)
kenvp = malloc((KENV_SIZE + 1) * sizeof(char *), M_KENV,
M_WAITOK | M_ZERO);
i = 0;
- for (cp = kern_envp; cp != NULL; cp = kernenv_next(cp)) {
- len = strlen(cp) + 1;
- if (len KENV_MNAMELEN + 1 + KENV_MVALLEN + 1) {
- printf(WARNING: too long kenv string, ignoring %s\n,
- cp);
- continue;
+ if (env_pos 0) {
+ for (cp = kern_envp; cp != NULL; cp = kernenv_next(cp)) {
+ len = strlen(cp) + 1;
+ if (len KENV_MNAMELEN + 1 + KENV_MVALLEN + 1) {
+ printf(
+ WARNING: too long kenv string, ignoring %s\n,
+ cp);
+ continue;
+ }
+ if (i KENV_SIZE) {
+ kenvp[i] = malloc(len, M_KENV, M_WAITOK);
+ strcpy(kenvp[i++], cp);
+ } else
+ printf(
+ WARNING: too many kenv strings, ignoring %s\n,
+ cp);
}
- if (i KENV_SIZE) {
- kenvp[i] = malloc(len, M_KENV, M_WAITOK);
- strcpy(kenvp[i++], cp);
- } else
- printf(
- WARNING: too many kenv strings, ignoring %s\n,
- cp);
}
kenvp[i] = NULL;
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svn commit: r249409 - head/sys/mips/nlm/dev/net
Author: jchandra
Date: Fri Apr 12 16:03:22 2013
New Revision: 249409
URL: http://svnweb.freebsd.org/changeset/base/249409
Log:
Fix incorrect KASSERTs in xlpge
Fix for crash in Netlogic XLP network accelerator driver when invariants
are enabled - use correct the condition for KASSERT.
Modified:
head/sys/mips/nlm/dev/net/xlpge.c
Modified: head/sys/mips/nlm/dev/net/xlpge.c
==
--- head/sys/mips/nlm/dev/net/xlpge.c Fri Apr 12 15:58:53 2013
(r249408)
+++ head/sys/mips/nlm/dev/net/xlpge.c Fri Apr 12 16:03:22 2013
(r249409)
@@ -975,7 +975,7 @@ nlm_mii_pollstat(void *arg)
if (sc-mii_bus) {
mii = device_get_softc(sc-mii_bus);
- KASSERT(mii == NULL, (mii ptr is NULL));
+ KASSERT(mii != NULL, (mii ptr is NULL));
mii_pollstat(mii);
@@ -1143,7 +1143,7 @@ get_buf(void)
#ifdef INVARIANTS
temp1 = vtophys((vm_offset_t) m_new-m_data);
temp2 = vtophys((vm_offset_t) m_new-m_data + 1536);
- KASSERT((temp1 + 1536) != temp2,
+ KASSERT((temp1 + 1536) == temp2,
(Alloced buffer is not contiguous));
#endif
return ((void *)m_new-m_data);
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svn commit: r249415 - in head/sys/mips: include mips
Author: jchandra
Date: Fri Apr 12 17:22:12 2013
New Revision: 249415
URL: http://svnweb.freebsd.org/changeset/base/249415
Log:
Move MIPS_MAX_TLB_ENTRIES definition from cpuregs.h to tlb.c
Having MIPS_MAX_TLB_ENTRIES defined to 128 is misleading, since it used
to be 64 in older releases of MIPS architecture (where it could be read
from Config1) and can be much more than 128 for the newer processors.
For now, move the definition to the only file using it (mips/mips/tlb.c)
and define MIPS_MAX_TLB_ENTRIES depending on the MIPS cpu defined. Also
add few checks so that we do not write beyond the end of the tlb_state
array.
This fixes a kernel data corruption seen in Netlogic XLP, which was casued
by tlb_save() writing beyond the end of tlb_state array when breaking into
debugger.
Modified:
head/sys/mips/include/cpuregs.h
head/sys/mips/mips/tlb.c
Modified: head/sys/mips/include/cpuregs.h
==
--- head/sys/mips/include/cpuregs.h Fri Apr 12 17:15:47 2013
(r249414)
+++ head/sys/mips/include/cpuregs.h Fri Apr 12 17:22:12 2013
(r249415)
@@ -521,7 +521,6 @@
#define MIPS_CONFIG1_TLBSZ_MASK0x7E00 /* bits 30..25
# tlb entries minus one */
#define MIPS_CONFIG1_TLBSZ_SHIFT 25
-#defineMIPS_MAX_TLB_ENTRIES128
#define MIPS_CONFIG1_IS_MASK 0x01C0 /* bits 24..22 icache
sets per way */
#define MIPS_CONFIG1_IS_SHIFT 22
Modified: head/sys/mips/mips/tlb.c
==
--- head/sys/mips/mips/tlb.cFri Apr 12 17:15:47 2013(r249414)
+++ head/sys/mips/mips/tlb.cFri Apr 12 17:22:12 2013(r249415)
@@ -40,6 +40,14 @@
#include machine/pte.h
#include machine/tlb.h
+#if defined(CPU_CNMIPS)
+#defineMIPS_MAX_TLB_ENTRIES128
+#elif defined(CPU_NLM)
+#defineMIPS_MAX_TLB_ENTRIES(2048 + 128)
+#else
+#defineMIPS_MAX_TLB_ENTRIES64
+#endif
+
struct tlb_state {
unsigned wired;
struct tlb_entry {
@@ -264,12 +272,15 @@ tlb_invalidate_range(pmap_t pmap, vm_off
void
tlb_save(void)
{
- unsigned i, cpu;
+ unsigned ntlb, i, cpu;
cpu = PCPU_GET(cpuid);
-
+ if (num_tlbentries MIPS_MAX_TLB_ENTRIES)
+ ntlb = MIPS_MAX_TLB_ENTRIES;
+ else
+ ntlb = num_tlbentries;
tlb_state[cpu].wired = mips_rd_wired();
- for (i = 0; i num_tlbentries; i++) {
+ for (i = 0; i ntlb; i++) {
mips_wr_index(i);
tlb_read();
@@ -329,7 +340,7 @@ tlb_invalidate_one(unsigned i)
DB_SHOW_COMMAND(tlb, ddb_dump_tlb)
{
register_t ehi, elo0, elo1;
- unsigned i, cpu;
+ unsigned i, cpu, ntlb;
/*
* XXX
@@ -344,12 +355,18 @@ DB_SHOW_COMMAND(tlb, ddb_dump_tlb)
db_printf(Invalid CPU %u\n, cpu);
return;
}
+ if (num_tlbentries MIPS_MAX_TLB_ENTRIES) {
+ ntlb = MIPS_MAX_TLB_ENTRIES;
+ db_printf(Warning: Only %d of %d TLB entries saved!\n,
+ ntlb, num_tlbentries);
+ } else
+ ntlb = num_tlbentries;
if (cpu == PCPU_GET(cpuid))
tlb_save();
db_printf(Beginning TLB dump for CPU %u...\n, cpu);
- for (i = 0; i num_tlbentries; i++) {
+ for (i = 0; i ntlb; i++) {
if (i == tlb_state[cpu].wired) {
if (i != 0)
db_printf(^^^ WIRED ENTRIES ^^^\n);
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Re: svn commit: r249408 - head/sys/kern
On Sat, Apr 13, 2013 at 3:12 AM, Navdeep Parhar n...@freebsd.org wrote:
This prevents my system from booting up properly. Backing out this
change restores normal operation.
The symptoms are that the kernel doesn't find the root fs itself but
waits at the mountroot prompt instead. I'm able to specify the
filesystem to use and then the boot proceeds as normal. Once the
system has booted up I see only two entries in kenv, indicating that
something clobbered the environment.
# kenv
kern.devalias.ada0=ad4
kern.devalias.ada1=ad6
After looking at the changes again, I realized that most architectures do
not update the env_pos when they setup kern_envp.
If there are no objections, I will check-in the attached change, otherwise
I will revert this commit.
Thanks for reporting this, and sorry for the mess.
JC.
On Fri, Apr 12, 2013 at 8:58 AM, Jayachandran C. jchan...@freebsd.org
wrote:
Author: jchandra
Date: Fri Apr 12 15:58:53 2013
New Revision: 249408
URL: http://svnweb.freebsd.org/changeset/base/249408
Log:
Fix kenv behavior when there is no static environment
In case where there are no static kernel environment entries, the
function init_dynamic_kenv() adds an incorrect entry at position 0 of
the dynamic kernel environment. This in turn causes kenv(1) to print
and empty list even though there are dynamic entries added later.
Fix this by checking env_pos in init_dynamic_kenv() and adding dynamic
entries only if there are static entries.
Modified:
head/sys/kern/kern_environment.c
Modified: head/sys/kern/kern_environment.c
==
--- head/sys/kern/kern_environment.cFri Apr 12 15:19:35 2013
(r249407)
+++ head/sys/kern/kern_environment.cFri Apr 12 15:58:53 2013
(r249408)
@@ -231,20 +231,23 @@ init_dynamic_kenv(void *data __unused)
kenvp = malloc((KENV_SIZE + 1) * sizeof(char *), M_KENV,
M_WAITOK | M_ZERO);
i = 0;
- for (cp = kern_envp; cp != NULL; cp = kernenv_next(cp)) {
- len = strlen(cp) + 1;
- if (len KENV_MNAMELEN + 1 + KENV_MVALLEN + 1) {
- printf(WARNING: too long kenv string, ignoring
%s\n,
- cp);
- continue;
+ if (env_pos 0) {
+ for (cp = kern_envp; cp != NULL; cp = kernenv_next(cp)) {
+ len = strlen(cp) + 1;
+ if (len KENV_MNAMELEN + 1 + KENV_MVALLEN + 1) {
+ printf(
+ WARNING: too long kenv string, ignoring
%s\n,
+ cp);
+ continue;
+ }
+ if (i KENV_SIZE) {
+ kenvp[i] = malloc(len, M_KENV, M_WAITOK);
+ strcpy(kenvp[i++], cp);
+ } else
+ printf(
+ WARNING: too many kenv strings,
ignoring %s\n,
+ cp);
}
- if (i KENV_SIZE) {
- kenvp[i] = malloc(len, M_KENV, M_WAITOK);
- strcpy(kenvp[i++], cp);
- } else
- printf(
- WARNING: too many kenv strings, ignoring
%s\n,
- cp);
}
kenvp[i] = NULL;
kenv-fix.diff
Description: Binary data
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svn commit: r245877 - head/sys/mips/nlm
Author: jchandra
Date: Thu Jan 24 11:42:16 2013
New Revision: 245877
URL: http://svnweb.freebsd.org/changeset/base/245877
Log:
Little-endian fix for PCI on Broadcom XLP.
Update the function xlp_pcib_hardware_swap_enable() to do nothing
when BYTE_ORDER is not BIG_ENDIAN. PCIe hardware swap is not requred
in little-endian mode as the endianness matches that of CPU.
Modified:
head/sys/mips/nlm/xlp_pci.c
Modified: head/sys/mips/nlm/xlp_pci.c
==
--- head/sys/mips/nlm/xlp_pci.c Thu Jan 24 09:36:50 2013(r245876)
+++ head/sys/mips/nlm/xlp_pci.c Thu Jan 24 11:42:16 2013(r245877)
@@ -487,12 +487,14 @@ xlp_pcib_write_config(device_t dev, u_in
}
/*
- * Enable byte swap in hardware. Program a link's PCIe SWAP regions
- * from the link's IO and MEM address ranges.
+ * Enable byte swap in hardware when compiled big-endian.
+ * Programs a link's PCIe SWAP regions from the link's IO and MEM address
+ * ranges.
*/
static void
xlp_pcib_hardware_swap_enable(int node, int link)
{
+#if BYTE_ORDER == BIG_ENDIAN
uint64_t bbase, linkpcibase;
uint32_t bar;
int pcieoffset;
@@ -514,6 +516,7 @@ xlp_pcib_hardware_swap_enable(int node,
bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_LIMIT0 + link);
nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_LIM, bar | 0xFFF);
+#endif
}
static int
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svn commit: r245879 - in head/sys/mips/nlm: . hal
Author: jchandra
Date: Thu Jan 24 14:33:25 2013
New Revision: 245879
URL: http://svnweb.freebsd.org/changeset/base/245879
Log:
Broadcom XLP updates for the new firmware
Support few more versions of board firmware. In case the security
block is disabled, enable it at boot. Also increase the excluded
memory region to cover the area used by the firmware to initialize
devices.
Modified:
head/sys/mips/nlm/hal/sys.h
head/sys/mips/nlm/xlp_machdep.c
Modified: head/sys/mips/nlm/hal/sys.h
==
--- head/sys/mips/nlm/hal/sys.h Thu Jan 24 14:29:31 2013(r245878)
+++ head/sys/mips/nlm/hal/sys.h Thu Jan 24 14:33:25 2013(r245879)
@@ -140,5 +140,18 @@ enum {
INVALID_DFS_DEVICE = 0xFF
};
+static __inline
+void nlm_sys_enable_block(uint64_t sys_base, int block)
+{
+ uint32_t dfsdis, mask;
+
+ mask = 1 block;
+ dfsdis = nlm_read_sys_reg(sys_base, SYS_DFS_DIS_CTRL);
+ if ((dfsdis mask) == 0)
+ return; /* already enabled, nothing to do */
+ dfsdis = ~mask;
+ nlm_write_sys_reg(sys_base, SYS_DFS_DIS_CTRL, dfsdis);
+}
+
#endif
#endif
Modified: head/sys/mips/nlm/xlp_machdep.c
==
--- head/sys/mips/nlm/xlp_machdep.c Thu Jan 24 14:29:31 2013
(r245878)
+++ head/sys/mips/nlm/xlp_machdep.c Thu Jan 24 14:33:25 2013
(r245879)
@@ -157,6 +157,20 @@ xlp_setup_mmu(void)
}
static void
+xlp_enable_blocks(void)
+{
+ uint64_t sysbase;
+ int i;
+
+ for (i = 0; i XLP_MAX_NODES; i++) {
+ if (!nlm_dev_exists(XLP_IO_SYS_OFFSET(i)))
+ continue;
+ sysbase = nlm_get_sys_regbase(i);
+ nlm_sys_enable_block(sysbase, DFS_DEVICE_RSA);
+ }
+}
+
+static void
xlp_parse_mmu_options(void)
{
uint64_t sysbase;
@@ -420,9 +434,8 @@ xlp_pic_init(void)
#defineXLP_MEM_LIM 0xf000UL
#endif
static vm_paddr_t xlp_mem_excl[] = {
- 0, 0, /* entry for kernel image, set by xlp_mem_init*/
- 0x0c00, 0x0d00, /* uboot mess */
- 0x1000, 0x1400, /* cms queue and other stuff */
+ 0, 0, /* for kernel image region, see xlp_mem_init */
+ 0x0c00, 0x1400, /* uboot area, cms queue and other stuff */
0x1fc0, 0x1fd0, /* reset vec */
0x1e00, 0x1e20, /* poe buffers */
};
@@ -559,6 +572,8 @@ platform_start(__register_t a0 __unused,
/* setup for the startup core */
xlp_setup_mmu();
+ xlp_enable_blocks();
+
/* Read/Guess/setup board information */
nlm_board_info_setup();
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svn commit: r245880 - head/sys/mips/nlm/dev/net
Author: jchandra
Date: Thu Jan 24 14:42:58 2013
New Revision: 245880
URL: http://svnweb.freebsd.org/changeset/base/245880
Log:
Minor updates to the Broadcom XLP NAE driver
Remove unnecessary SGMII initialization code from nae.c. While there
clean up some prints and whitespace.
Modified:
head/sys/mips/nlm/dev/net/nae.c
head/sys/mips/nlm/dev/net/xlpge.c
Modified: head/sys/mips/nlm/dev/net/nae.c
==
--- head/sys/mips/nlm/dev/net/nae.c Thu Jan 24 14:33:25 2013
(r245879)
+++ head/sys/mips/nlm/dev/net/nae.c Thu Jan 24 14:42:58 2013
(r245880)
@@ -1427,9 +1427,8 @@ nlm_nae_open_if(uint64_t nae_base, int n
int port, uint32_t desc_size)
{
uint32_t netwk_inf;
- uint32_t mac_cfg1, mac_cfg2, netior_ctrl3;
- int iface, speed, duplex, ifmode;
- int iface_ctrl_reg, iface_ctrl3_reg, conf1_reg, conf2_reg;
+ uint32_t mac_cfg1, netior_ctrl3;
+ int iface, iface_ctrl_reg, iface_ctrl3_reg, conf1_reg, conf2_reg;
switch (port_type) {
case XAUIC:
@@ -1487,6 +1486,7 @@ nlm_nae_open_if(uint64_t nae_base, int n
/* clear gmac reset */
mac_cfg1 = nlm_read_nae_reg(nae_base, conf1_reg);
nlm_write_nae_reg(nae_base, conf1_reg, mac_cfg1 ~(1 31));
+
/* clear speed debug bit */
iface_ctrl3_reg = SGMII_NET_IFACE_CTRL3(nblock, iface);
netior_ctrl3 = nlm_read_nae_reg(nae_base, iface_ctrl3_reg);
@@ -1500,33 +1500,21 @@ nlm_nae_open_if(uint64_t nae_base, int n
nlm_write_nae_reg(nae_base, iface_ctrl_reg,
netwk_inf ~(0x1 2));
- /* setup defaults *//* XXXJC: take defaults from sc? */
- speed = 2;
- duplex = 1;
- ifmode = 0x2;
- netwk_inf = nlm_read_nae_reg(nae_base, iface_ctrl_reg);
- netwk_inf = ~(0x3);
- nlm_write_nae_reg(nae_base, iface_ctrl_reg,
- netwk_inf | (speed 0x3));
- mac_cfg2 = nlm_read_nae_reg(nae_base, conf2_reg);
- mac_cfg2 = ~(0x3 8);
- nlm_write_nae_reg(nae_base, conf2_reg,
- mac_cfg2|
- ((ifmode 0x3) 8) | /* interface mode */
- (duplex 0x1));
-
/* clear stats counters */
netwk_inf = nlm_read_nae_reg(nae_base, iface_ctrl_reg);
nlm_write_nae_reg(nae_base, iface_ctrl_reg,
netwk_inf | (1 15));
+
/* enable stats counters */
netwk_inf = nlm_read_nae_reg(nae_base, iface_ctrl_reg);
nlm_write_nae_reg(nae_base, iface_ctrl_reg,
(netwk_inf ~(1 15)) | (1 16));
+
+ /* flow control? */
mac_cfg1 = nlm_read_nae_reg(nae_base, conf1_reg);
nlm_write_nae_reg(nae_base, conf1_reg,
mac_cfg1 | (0x3 4));
- break;
+ break;
}
nlm_nae_init_ingress(nae_base, desc_size);
Modified: head/sys/mips/nlm/dev/net/xlpge.c
==
--- head/sys/mips/nlm/dev/net/xlpge.c Thu Jan 24 14:33:25 2013
(r245879)
+++ head/sys/mips/nlm/dev/net/xlpge.c Thu Jan 24 14:42:58 2013
(r245880)
@@ -1364,13 +1364,13 @@ nlm_xlpge_mii_statchg(device_t dev)
if (mii-mii_media_status IFM_ACTIVE) {
if (IFM_SUBTYPE(mii-mii_media_active) == IFM_10_T) {
sc-speed = NLM_SGMII_SPEED_10;
- speed = 10-Mbps;
+ speed = 10Mbps;
} else if (IFM_SUBTYPE(mii-mii_media_active) == IFM_100_TX) {
sc-speed = NLM_SGMII_SPEED_100;
- speed = 100-Mbps;
+ speed = 100Mbps;
} else { /* default to 1G */
sc-speed = NLM_SGMII_SPEED_1000;
- speed = 1-Gbps;
+ speed = 1Gbps;
}
if ((mii-mii_media_active IFM_GMASK) == IFM_FDX) {
@@ -1381,7 +1381,7 @@ nlm_xlpge_mii_statchg(device_t dev)
duplexity = half;
}
- printf(Setup [complex=%d, port=%d] with speed=%s duplex=%s\n,
+ printf(Port [%d, %d] setup with speed=%s duplex=%s\n,
sc-block, sc-port, speed, duplexity);
nlm_nae_setup_mac(sc-base_addr, sc-block, sc-port, 0, 1, 1,
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svn commit: r245881 - in head/sys/mips/nlm: dev/net hal
Author: jchandra
Date: Thu Jan 24 15:14:22 2013
New Revision: 245881
URL: http://svnweb.freebsd.org/changeset/base/245881
Log:
Broadcom XLP network driver update for XLP 8xx B1 rev
Update MDIO reset code to support Broadcom XLP B1 revisions.
Update nlm_xlpge_ioctl, nlm_xlpge_port_enable need not be
called after nlm_xlpge_init.
Obtained from:Venkatesh J V venkatesh.vivekanan...@broadcom.com
Modified:
head/sys/mips/nlm/dev/net/mdio.c
head/sys/mips/nlm/dev/net/sgmii.c
head/sys/mips/nlm/dev/net/xlpge.c
head/sys/mips/nlm/hal/mdio.h
Modified: head/sys/mips/nlm/dev/net/mdio.c
==
--- head/sys/mips/nlm/dev/net/mdio.cThu Jan 24 14:42:58 2013
(r245880)
+++ head/sys/mips/nlm/dev/net/mdio.cThu Jan 24 15:14:22 2013
(r245881)
@@ -149,7 +149,8 @@ nlm_int_gmac_mdio_reset(uint64_t nae_bas
uint32_t val;
val = (7 INT_MDIO_CTRL_XDIV_POS) |
- (1 INT_MDIO_CTRL_MCDIV_POS);
+ (1 INT_MDIO_CTRL_MCDIV_POS) |
+ (INT_MDIO_CTRL_SMP);
nlm_write_nae_reg(nae_base,
NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
@@ -302,10 +303,13 @@ nlm_gmac_mdio_reset(uint64_t nae_base, i
{
uint32_t ctrlval;
+ ctrlval = nlm_read_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)));
+
if (nlm_is_xlp8xx_ax() || nlm_is_xlp8xx_b0() || nlm_is_xlp3xx_ax())
- ctrlval = EXT_G_MDIO_DIV;
+ ctrlval |= EXT_G_MDIO_DIV;
else
- ctrlval = EXT_G_MDIO_DIV_WITH_HW_DIV64;
+ ctrlval |= EXT_G_MDIO_DIV_WITH_HW_DIV64;
nlm_write_nae_reg(nae_base,
NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL + bus * 4)),
@@ -314,3 +318,16 @@ nlm_gmac_mdio_reset(uint64_t nae_base, i
NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL + bus * 4)), ctrlval);
return (0);
}
+
+/*
+ * nlm_mdio_reset_all : reset all internal and external MDIO
+ */
+void
+nlm_mdio_reset_all(uint64_t nae_base)
+{
+ /* reset internal MDIO */
+ nlm_int_gmac_mdio_reset(nae_base, 0, BLOCK_7, LANE_CFG);
+ /* reset external MDIO */
+ nlm_gmac_mdio_reset(nae_base, 0, BLOCK_7, LANE_CFG);
+ nlm_gmac_mdio_reset(nae_base, 1, BLOCK_7, LANE_CFG);
+}
Modified: head/sys/mips/nlm/dev/net/sgmii.c
==
--- head/sys/mips/nlm/dev/net/sgmii.c Thu Jan 24 14:42:58 2013
(r245880)
+++ head/sys/mips/nlm/dev/net/sgmii.c Thu Jan 24 15:14:22 2013
(r245881)
@@ -69,13 +69,6 @@ nlm_configure_sgmii_interface(uint64_t n
void
nlm_sgmii_pcs_init(uint64_t nae_base, uint32_t cplx_mask)
{
- /* reset internal MDIO */
- nlm_int_gmac_mdio_reset(nae_base, 0, BLOCK_7, LANE_CFG);
-
- /* reset external MDIO */
- nlm_gmac_mdio_reset(nae_base, 0, BLOCK_7, LANE_CFG);
- nlm_gmac_mdio_reset(nae_base, 1, BLOCK_7, LANE_CFG);
-
xlp_nae_config_lane_gmac(nae_base, cplx_mask);
}
Modified: head/sys/mips/nlm/dev/net/xlpge.c
==
--- head/sys/mips/nlm/dev/net/xlpge.c Thu Jan 24 14:42:58 2013
(r245880)
+++ head/sys/mips/nlm/dev/net/xlpge.c Thu Jan 24 15:14:22 2013
(r245881)
@@ -444,6 +444,8 @@ nlm_xlpnae_init(int node, struct nlm_xlp
val = nlm_set_device_frequency(node, DFS_DEVICE_NAE, sc-freq);
printf(Setup NAE frequency to %dMHz\n, val);
+ nlm_mdio_reset_all(nae_base);
+
printf(Initialze SGMII PCS for blocks 0x%x\n, sc-sgmiimask);
nlm_sgmii_pcs_init(nae_base, sc-sgmiimask);
@@ -797,8 +799,9 @@ nlm_xlpge_ioctl(struct ifnet *ifp, u_lon
if (ifp-if_flags IFF_UP) {
if ((ifp-if_drv_flags IFF_DRV_RUNNING) == 0)
nlm_xlpge_init(sc);
- nlm_xlpge_mac_set_rx_mode(sc);
- nlm_xlpge_port_enable(sc);
+ else
+ nlm_xlpge_port_enable(sc);
+ nlm_xlpge_mac_set_rx_mode(sc);
sc-link = NLM_LINK_UP;
} else {
if (ifp-if_drv_flags IFF_DRV_RUNNING)
@@ -1288,6 +1291,7 @@ nlm_xlpge_attach(device_t dev)
nlm_xlpge_ifinit(sc);
ifp_ports[port].xlpge_sc = sc;
nlm_xlpge_mii_init(dev, sc);
+
nlm_xlpge_setup_stats_sysctl(dev, sc);
return (0);
@@ -1385,7 +1389,7 @@ nlm_xlpge_mii_statchg(device_t dev)
sc-block, sc-port, speed, duplexity);
nlm_nae_setup_mac(sc-base_addr, sc-block, sc-port, 0, 1, 1,
- sc-speed, sc-duplexity);
+ sc-speed, sc-duplexity);
}
}
Modified: head/sys/mips/nlm/hal/mdio.h
==
---
svn commit: r245883 - head/sys/mips/nlm/hal
Author: jchandra
Date: Thu Jan 24 15:23:01 2013
New Revision: 245883
URL: http://svnweb.freebsd.org/changeset/base/245883
Log:
Fix credit configuration on Broadcom XLP CMS
The CMS output queue credit configuration register is 64 bit, so use
a 64 bit variable while updating it.
Obtained from:Venkatesh J V venkatesh.vivekanan...@broadcom.com
Modified:
head/sys/mips/nlm/hal/fmn.c
Modified: head/sys/mips/nlm/hal/fmn.c
==
--- head/sys/mips/nlm/hal/fmn.c Thu Jan 24 15:18:41 2013(r245882)
+++ head/sys/mips/nlm/hal/fmn.c Thu Jan 24 15:23:01 2013(r245883)
@@ -138,9 +138,9 @@ uint32_t nlm_cms_total_stations = 18 * 4
void nlm_cms_setup_credits(uint64_t base, int destid, int srcid, int credit)
{
- uint32_t val;
+ uint64_t val;
- val = ((credit 24) | (destid 12) | (srcid 0));
+ val = (((uint64_t)credit 24) | (destid 12) | (srcid 0));
nlm_write_cms_reg(base, CMS_OUTPUTQ_CREDIT_CFG, val);
}
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svn commit: r245884 - in head/sys/mips/nlm: dev/net hal
Author: jchandra
Date: Thu Jan 24 15:49:47 2013
New Revision: 245884
URL: http://svnweb.freebsd.org/changeset/base/245884
Log:
Little-endian and other fixes for Broadcom XLP network driver
The changes are:
- the microcore code loaded into the NAE has to be byteswapped
in LE
- the descriptors in memory for a P2P NAE descriptor has to be
byteswapped in LE
- the m_data pointer is already cacheline aligned, so the
unnecessary m_adj to cacheline size can be removed
- fix mask used to obtain physical address from the Tx freeback
descriptor
- fix a compile error in code under #ifdef
Obtained from:Venkatesh J V venkatesh.vivekanan...@broadcom.com
Modified:
head/sys/mips/nlm/dev/net/xlpge.c
head/sys/mips/nlm/hal/ucore_loader.h
Modified: head/sys/mips/nlm/dev/net/xlpge.c
==
--- head/sys/mips/nlm/dev/net/xlpge.c Thu Jan 24 15:23:01 2013
(r245883)
+++ head/sys/mips/nlm/dev/net/xlpge.c Thu Jan 24 15:49:47 2013
(r245884)
@@ -869,6 +869,7 @@ xlpge_tx(struct ifnet *ifp, struct mbuf
vm_offset_t buf = (vm_offset_t) m-m_data;
int len = m-m_len;
int frag_sz;
+ uint64_t desc;
/*printf(m_data = %p len %d\n, m-m_data, len); */
while (len) {
@@ -883,8 +884,9 @@ xlpge_tx(struct ifnet *ifp, struct mbuf
frag_sz = PAGE_SIZE - (buf PAGE_MASK);
if (len frag_sz)
frag_sz = len;
- p2p-frag[pos] = nae_tx_desc(P2D_NEOP, 0, 127,
+ desc = nae_tx_desc(P2D_NEOP, 0, 127,
frag_sz, paddr);
+ p2p-frag[pos] = htobe64(desc);
pos++;
len -= frag_sz;
buf += frag_sz;
@@ -894,7 +896,7 @@ xlpge_tx(struct ifnet *ifp, struct mbuf
KASSERT(pos != 0, (Zero-length mbuf chain?\n));
/* Make the last one P2D EOP */
- p2p-frag[pos-1] |= (uint64_t)P2D_EOP 62;
+ p2p-frag[pos-1] |= htobe64((uint64_t)P2D_EOP 62);
/* stash useful pointers in the desc */
p2p-frag[XLP_NTXFRAGS-3] = 0xf00bad;
@@ -1131,7 +1133,8 @@ get_buf(void)
if ((m_new = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR)) == NULL)
return (NULL);
m_new-m_len = m_new-m_pkthdr.len = MCLBYTES;
- m_adj(m_new, NAE_CACHELINE_SIZE - ((uintptr_t)m_new-m_data 0x1f));
+ KASSERT(((uintptr_t)m_new-m_data (NAE_CACHELINE_SIZE - 1)) == 0,
+ (m_new-m_data is not cacheline aligned));
md = (uint64_t *)m_new-m_data;
md[0] = (intptr_t)m_new;/* Back Ptr */
md[1] = 0xf00bad;
@@ -1140,10 +1143,9 @@ get_buf(void)
#ifdef INVARIANTS
temp1 = vtophys((vm_offset_t) m_new-m_data);
temp2 = vtophys((vm_offset_t) m_new-m_data + 1536);
- KASSERT(temp1 + 1536) != temp2,
+ KASSERT((temp1 + 1536) != temp2,
(Alloced buffer is not contiguous));
#endif
-
return ((void *)m_new-m_data);
}
@@ -1552,7 +1554,7 @@ nlm_xlpge_msgring_handler(int vc, int si
ifp-if_opackets++;
} else if (size 1) { /* Recieve packet */
- phys_addr = msg-msg[1] 0xe0ULL;
+ phys_addr = msg-msg[1] 0xc0ULL;
length = (msg-msg[1] 40) 0x3fff;
length -= MAC_CRC_LEN;
Modified: head/sys/mips/nlm/hal/ucore_loader.h
==
--- head/sys/mips/nlm/hal/ucore_loader.hThu Jan 24 15:23:01 2013
(r245883)
+++ head/sys/mips/nlm/hal/ucore_loader.hThu Jan 24 15:49:47 2013
(r245884)
@@ -49,7 +49,7 @@ nlm_ucore_load_image(uint64_t nae_base,
size = sizeof(ucore_app_bin)/sizeof(uint32_t);
for (i = 0; i size; i++, addr += 4)
- nlm_store_word_daddr(addr, p[i]);
+ nlm_store_word_daddr(addr, htobe32(p[i]));
/* add a 'nop' if number of instructions are odd */
if (size 0x1)
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Re: svn commit: r243631 - in head/sys: kern sys
On Fri, Jan 11, 2013 at 11:16 PM, Alan Cox a...@rice.edu wrote: On 01/11/2013 05:38, Jayachandran C. wrote: [...] I see an issue with commit on MIPS XLP platform as well. With 16 GB physical memory, the ncallout is calculated to be 538881 (since it is based on maxfiles - which is now based on the physical memory). Due to this, the callwheel allocation per cpu is 16MB (callwheelsize is 1MB). And on a 32 CPU machine, the total allocation for callouts comes to 32*16MB = 512MB. I have worked around this issue for now by increasing VM_KMEM_SIZE_MAX (which is 200MB now) - but I think a better fix is needed for this. MIPS should use a definition for VM_KMEM_SIZE_MAX that scales with the kernel address space size, like amd64, i386, and sparc64, and not a fixed number. I think that the following should work for both 32- and 64-bit processors: Index: mips/include/vmparam.h === --- mips/include/vmparam.h (revision 245229) +++ mips/include/vmparam.h (working copy) @@ -130,10 +130,11 @@ #endif /* - * Ceiling on amount of kmem_map kva space. + * Ceiling on the amount of kmem_map KVA space: 40% of the entire KVA space. */ #ifndef VM_KMEM_SIZE_MAX -#defineVM_KMEM_SIZE_MAX(200 * 1024 * 1024) +#defineVM_KMEM_SIZE_MAX((VM_MAX_KERNEL_ADDRESS - \ +VM_MIN_KERNEL_ADDRESS + 1) * 2 / 5) #endif /* initial pagein size of beginning of executable file */ This fix is needed, can you please check it in? I have tested it for 32 and 64 bit. But the second part of the problem - allocating 512MB out of 16GB at boot-time for callouts - might need a fix as well. Thanks, JC. ___ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to svn-src-all-unsubscr...@freebsd.org
Re: svn commit: r243631 - in head/sys: kern sys
On Tue, Jan 8, 2013 at 3:12 AM, Andre Oppermann an...@freebsd.org wrote: On 07.01.2013 20:32, Alan Cox wrote: On 01/07/2013 12:47, Oleksandr Tymoshenko wrote: On 12/27/2012 6:46 PM, Oleksandr Tymoshenko wrote: On 12/18/2012 1:59 AM, Alan Cox wrote: On 12/17/2012 23:40, Oleksandr Tymoshenko wrote: On 2012-12-08, at 1:21 PM, Alan Cox a...@rice.edu wrote: On 12/08/2012 14:32, Andre Oppermann wrote: .. skipped .. The trouble seems to come from NSFBUFS which is (512 + maxusers * 16) resulting in a kernel map of (512 + 400 * 16) * PAGE_SIZE = 27MB. This seem to be pushing it with the smaller ARM kmap layout. Does it boot and run when you set the tunable kern.ipc.nsfbufs=3500? ARM does have a direct map mode as well which doesn't require the allocation of sfbufs. I'm not sure which other problems that approach has. Only a few (3?) platforms use it. It reduces the size of the user address space, and translation between physical addresses and direct map addresses is not computationally trivial as it is on other architectures, e.g., amd64, ia64. However, it does try to use large page mappings. Hopefully alc@ (added to cc) can answer that and also why the kmap of 27MB manages to wrench the ARM kernel. Arm does not define caps on either the buffer map size (param.h) or the kmem map size (vmparam.h). It would probably make sense to copy these definitions from i386. Adding caps didn't help. I did some digging and found out that although address range 0xc000 .. 0x is indeed valid for ARM in general actual KVA space varies for each specific hardware platform. This real KVA is defined by virtual_avail, virtual_end pair and ifI use them instead of VM_MIN_KERNEL_ADDRESS, VM_MAX_KERNEL_ADDRESS in init_param2 function my pandaboard successfully boots. Since former pair is used for defining kernel_map boundaries I believe it should be used for auto tuning as well. That makes sense. However, virtual_avail isn't the start of the kernel address space. The kernel map always starts at VM_MIN_KERNEL_ADDRESS. (See kmem_init().) virtual_avail represents the next unallocated virtual address in the kernel address space at an early point in initialization. virtual_avail and virtual_end aren't used after that, or outside the VM system. Please use vm_map_min(kernel_map) and vm_map_max(kernel_map) instead. I checked: kernel_map is not available (NULL) at this point. So we can't use it to determine real KVA size. Closest thing we can get is virtual_avail/virtual_end pair. Andre, could you approve attached patch for commit or suggest better solution? Any update on this one? Can I proceed with commit? Sorry, I've been away from my e-mail since the 30th, and I'm now in the process of getting caught up. Give me a day or so to look at this. I see an issue with commit on MIPS XLP platform as well. With 16 GB physical memory, the ncallout is calculated to be 538881 (since it is based on maxfiles - which is now based on the physical memory). Due to this, the callwheel allocation per cpu is 16MB (callwheelsize is 1MB). And on a 32 CPU machine, the total allocation for callouts comes to 32*16MB = 512MB. I have worked around this issue for now by increasing VM_KMEM_SIZE_MAX (which is 200MB now) - but I think a better fix is needed for this. JC. ___ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to svn-src-all-unsubscr...@freebsd.org
svn commit: r239487 - in head/sys: boot/fdt/dts mips/nlm
Author: jchandra
Date: Tue Aug 21 09:37:23 2012
New Revision: 239487
URL: http://svn.freebsd.org/changeset/base/239487
Log:
Add correct range parameter in XLP DTS
r239274 added support for ranges. Update XLP DTS to provide the correct
range parameter for the XLP SoC bus. Also fix bus_space_map method
for XLP bus space.
Submitted by: Sreekanth M. sreekanth.molagava...@broadcom.com
Modified:
head/sys/boot/fdt/dts/xlp-basic.dts
head/sys/mips/nlm/bus_space_rmi.c
Modified: head/sys/boot/fdt/dts/xlp-basic.dts
==
--- head/sys/boot/fdt/dts/xlp-basic.dts Tue Aug 21 09:18:28 2012
(r239486)
+++ head/sys/boot/fdt/dts/xlp-basic.dts Tue Aug 21 09:37:23 2012
(r239487)
@@ -44,7 +44,7 @@
#address-cells = 1;
#size-cells = 1;
compatible = simple-bus;
- ranges = 0x0;
+ ranges = 0x0 0x1800 0x0400;
bus-frequency = 0;
serial0: serial@30100 {
Modified: head/sys/mips/nlm/bus_space_rmi.c
==
--- head/sys/mips/nlm/bus_space_rmi.c Tue Aug 21 09:18:28 2012
(r239486)
+++ head/sys/mips/nlm/bus_space_rmi.c Tue Aug 21 09:37:23 2012
(r239487)
@@ -366,7 +366,7 @@ rmi_bus_space_map(void *t __unused, bus_
bus_space_handle_t *bshp)
{
- *bshp = addr;
+ *bshp = MIPS_PHYS_TO_DIRECT_UNCACHED(addr);
return (0);
}
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svn commit: r239413 - head/sys/mips/nlm
Author: jchandra
Date: Mon Aug 20 11:51:49 2012
New Revision: 239413
URL: http://svn.freebsd.org/changeset/base/239413
Log:
Define and exclude DRAM regions used by hardware/bootloder on XLP
Fix xlp_mem_init() - remove the ad-hoc code for excluding memory regions
and use an array of regions.
Modified:
head/sys/mips/nlm/xlp_machdep.c
Modified: head/sys/mips/nlm/xlp_machdep.c
==
--- head/sys/mips/nlm/xlp_machdep.c Mon Aug 20 11:34:49 2012
(r239412)
+++ head/sys/mips/nlm/xlp_machdep.c Mon Aug 20 11:51:49 2012
(r239413)
@@ -419,83 +419,91 @@ xlp_pic_init(void)
#else
#defineXLP_MEM_LIM 0xf000UL
#endif
+static vm_paddr_t xlp_mem_excl[] = {
+ 0, 0, /* entry for kernel image, set by xlp_mem_init*/
+ 0x0c00, 0x0d00, /* uboot mess */
+ 0x1000, 0x1400, /* cms queue and other stuff */
+ 0x1fc0, 0x1fd0, /* reset vec */
+ 0x1e00, 0x1e20, /* poe buffers */
+};
+
+static int
+mem_exclude_add(vm_paddr_t *avail, vm_paddr_t mstart, vm_paddr_t mend)
+{
+ int nreg = sizeof(xlp_mem_excl)/sizeof(xlp_mem_excl[0]);
+ int i, pos;
+
+ pos = 0;
+ for (i = 0; i nreg; i += 2) {
+ if (mstart xlp_mem_excl[i + 1])
+ continue;
+ if (mstart xlp_mem_excl[i]) {
+ avail[pos++] = mstart;
+ if (mend xlp_mem_excl[i])
+ avail[pos++] = mend;
+ else
+ avail[pos++] = xlp_mem_excl[i];
+ }
+ mstart = xlp_mem_excl[i + 1];
+ if (mend = mstart)
+ break;
+ }
+ if (mstart mend) {
+ avail[pos++] = mstart;
+ avail[pos++] = mend;
+ }
+ return (pos);
+}
+
static void
xlp_mem_init(void)
{
- uint64_t bridgebase = nlm_get_bridge_regbase(0); /* TOOD: Add other
nodes */
- vm_size_t physsz = 0;
-uint64_t base, lim, val;
- int i, j;
-
+ vm_paddr_t physsz, tmp;
+ uint64_t bridgebase, base, lim, val;
+ int i, j, k, n;
+
+ /* update kernel image area in exclude regions */
+ tmp = (vm_paddr_t)MIPS_KSEG0_TO_PHYS(_end);
+ tmp = round_page(tmp) + 0x2; /* round up */
+ xlp_mem_excl[1] = tmp;
+
+ printf(Memory (from DRAM BARs):\n);
+ bridgebase = nlm_get_bridge_regbase(0); /* TODO: Add other nodes */
+ physsz = 0;
for (i = 0, j = 0; i 8; i++) {
val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_BAR(i));
- base = ((val 12) 0xf) 20;
+val = (val 12) 0xf;
+ base = val 20;
val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_LIMIT(i));
-lim = ((val 12) 0xf) 20;
-
- /* BAR not enabled */
- if (lim == 0)
+val = (val 12) 0xf;
+ if (val == 0) /* BAR not enabled */
continue;
+lim = (val + 1) 20;
+ printf( BAR %d: %#jx - %#jx : , i, (intmax_t)base,
+ (intmax_t)lim);
- /* first bar, start a bit after end */
- if (base == 0) {
- base = (vm_paddr_t)MIPS_KSEG0_TO_PHYS(_end);
- base = round_page(base) + 0x2; /* round up */
- /* TODO : hack to avoid uboot packet mem, network
-* interface will write here if not reset correctly
-* by u-boot */
- lim = 0x0c00;
- }
- if (base = XLP_MEM_LIM) {
- printf(Mem [%d]: Ignore %#jx - %#jx\n, i,
- (intmax_t)base, (intmax_t)lim);
- continue;
- }
- if (lim XLP_MEM_LIM) {
- printf(Mem [%d]: Restrict %#jx - %#jx\n, i,
- (intmax_t)lim, (intmax_t)XLP_MEM_LIM);
- lim = XLP_MEM_LIM;
- }
if (lim = base) {
- printf(Mem[%d]: Malformed %#jx - %#jx\n, i,
+ printf(\tskipped - malformed %#jx - %#jx\n,
(intmax_t)base, (intmax_t)lim);
continue;
+ } else if (base = XLP_MEM_LIM) {
+ printf( skipped - outside usable limit %#jx.\n,
+ (intmax_t)XLP_MEM_LIM);
+ continue;
+ } else if (lim = XLP_MEM_LIM) {
+ lim = XLP_MEM_LIM;
+ printf( truncated to %#jx.\n, (intmax_t)XLP_MEM_LIM);
+ } else
+ printf( usable\n);
+
+ /* exclude
svn commit: r238289 - head/sys/mips/nlm
Author: jchandra Date: Mon Jul 9 10:17:06 2012 New Revision: 238289 URL: http://svn.freebsd.org/changeset/base/238289 Log: Fix PCIe hardware swap configuration for Netlogic XLP The last 12 bits of the limit registers have to be set to 1. These bits are not significant in bridge BARs and are 0 on read, but the bits are valid in the swap limit register and needs to be set. Modified: head/sys/mips/nlm/xlp_pci.c Modified: head/sys/mips/nlm/xlp_pci.c == --- head/sys/mips/nlm/xlp_pci.c Mon Jul 9 09:38:53 2012(r238288) +++ head/sys/mips/nlm/xlp_pci.c Mon Jul 9 10:17:06 2012(r238289) @@ -507,13 +507,13 @@ xlp_pcib_hardware_swap_enable(int node, nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_BASE, bar); bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_LIMIT0 + link); - nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_LIM, bar); + nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_LIM, bar | 0xFFF); bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_BASE0 + link); nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_BASE, bar); bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_LIMIT0 + link); - nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_LIM, bar); + nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_LIM, bar | 0xFFF); } static int ___ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to svn-src-all-unsubscr...@freebsd.org
svn commit: r238290 - head/sys/mips/nlm
Author: jchandra
Date: Mon Jul 9 10:24:45 2012
New Revision: 238290
URL: http://svn.freebsd.org/changeset/base/238290
Log:
Identify Netlogic XLP 8xx B1 chip revisions
Add functions to check for 8xx B0 and 3xx Ax revisions which will
be used in network block initialization.
Modified:
head/sys/mips/nlm/board.c
head/sys/mips/nlm/xlp.h
Modified: head/sys/mips/nlm/board.c
==
--- head/sys/mips/nlm/board.c Mon Jul 9 10:17:06 2012(r238289)
+++ head/sys/mips/nlm/board.c Mon Jul 9 10:24:45 2012(r238290)
@@ -362,6 +362,8 @@ nlm_print_processor_info(void)
revstr = A2; break;
case 3:
revstr = B0; break;
+ case 4:
+ revstr = B1; break;
default:
revstr = ??; break;
}
Modified: head/sys/mips/nlm/xlp.h
==
--- head/sys/mips/nlm/xlp.h Mon Jul 9 10:17:06 2012(r238289)
+++ head/sys/mips/nlm/xlp.h Mon Jul 9 10:24:45 2012(r238290)
@@ -57,6 +57,7 @@
#defineXLP_REVISION_A1 0x01
#defineXLP_REVISION_A2 0x02
#defineXLP_REVISION_B0 0x03
+#defineXLP_REVISION_B1 0x04
#ifndef LOCORE
/*
@@ -87,6 +88,16 @@ static __inline int nlm_is_xlp3xx(void)
return (nlm_processor_id() == CHIP_PROCESSOR_ID_XLP_3XX);
}
+static __inline int nlm_is_xlp3xx_ax(void)
+{
+ uint32_t procid = mips_rd_prid();
+ int prid = (procid 8) 0xff;
+ int rev = procid 0xff;
+
+ return (prid == CHIP_PROCESSOR_ID_XLP_3XX
+ rev XLP_REVISION_B0);
+}
+
static __inline int nlm_is_xlp4xx(void)
{
int prid = nlm_processor_id();
@@ -116,5 +127,17 @@ static __inline int nlm_is_xlp8xx_ax(voi
(rev XLP_REVISION_B0));
}
+static __inline int nlm_is_xlp8xx_b0(void)
+{
+ uint32_t procid = mips_rd_prid();
+ int prid = (procid 8) 0xff;
+ int rev = procid 0xff;
+
+ return ((prid == CHIP_PROCESSOR_ID_XLP_8XX ||
+ prid == CHIP_PROCESSOR_ID_XLP_432 ||
+ prid == CHIP_PROCESSOR_ID_XLP_416)
+ rev == XLP_REVISION_B0);
+}
+
#endif /* LOCORE */
#endif /* __NLM_XLP_H__ */
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svn commit: r238293 - in head/sys/mips/nlm: dev/net hal
Author: jchandra
Date: Mon Jul 9 10:39:57 2012
New Revision: 238293
URL: http://svn.freebsd.org/changeset/base/238293
Log:
Support Netlogic XLP 8xx B1 revisions in xlpge.
Updates to the MDIO access code for the new revision of the
XLP chip.
Modified:
head/sys/mips/nlm/dev/net/mdio.c
head/sys/mips/nlm/hal/mdio.h
Modified: head/sys/mips/nlm/dev/net/mdio.c
==
--- head/sys/mips/nlm/dev/net/mdio.cMon Jul 9 10:36:43 2012
(r238292)
+++ head/sys/mips/nlm/dev/net/mdio.cMon Jul 9 10:39:57 2012
(r238293)
@@ -38,6 +38,8 @@ __FBSDID($FreeBSD$);
#include mips/nlm/hal/nae.h
#include mips/nlm/hal/mdio.h
+#include mips/nlm/xlp.h
+
/* Internal MDIO READ/WRITE Routines */
int
nlm_int_gmac_mdio_read(uint64_t nae_base, int bus, int block,
@@ -176,12 +178,7 @@ nlm_gmac_mdio_read(uint64_t nae_base, in
int intf_type, int phyaddr, int regidx)
{
uint32_t mdio_ld_cmd;
- uint32_t val;
-
- val = EXT_G_MDIO_CMD_SP |
- (phyaddr EXT_G_MDIO_PHYADDR_POS) |
- (regidx EXT_G_MDIO_REGADDR_POS) |
- EXT_G_MDIO_DIV;
+ uint32_t ctrlval;
mdio_ld_cmd = nlm_read_nae_reg(nae_base, NAE_REG(block, intf_type,
(EXT_G0_MDIO_CTRL + bus * 4)));
@@ -195,14 +192,22 @@ nlm_gmac_mdio_read(uint64_t nae_base, in
EXT_G_MDIO_STAT_MBSY);
}
- nlm_write_nae_reg(nae_base,
+ ctrlval = EXT_G_MDIO_CMD_SP |
+ (phyaddr EXT_G_MDIO_PHYADDR_POS) |
+ (regidx EXT_G_MDIO_REGADDR_POS);
+ if (nlm_is_xlp8xx_ax() || nlm_is_xlp8xx_b0() || nlm_is_xlp3xx_ax())
+ ctrlval |= EXT_G_MDIO_DIV;
+ else
+ ctrlval |= EXT_G_MDIO_DIV_WITH_HW_DIV64;
+
+ nlm_write_nae_reg(nae_base,
NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
- val);
+ ctrlval);
nlm_write_nae_reg(nae_base,
NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
- val | (118));
-
+ ctrlval | (118));
+ DELAY(1000);
/* poll master busy bit until it is not busy */
while(nlm_read_nae_reg(nae_base,
NAE_REG(block, intf_type, (EXT_G0_MDIO_RD_STAT + bus * 4)))
@@ -210,7 +215,7 @@ nlm_gmac_mdio_read(uint64_t nae_base, in
nlm_write_nae_reg(nae_base,
NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
- val);
+ ctrlval);
/* Read the data back */
return nlm_read_nae_reg(nae_base,
@@ -236,11 +241,6 @@ nlm_gmac_mdio_write(uint64_t nae_base, i
uint32_t mdio_ld_cmd;
uint32_t ctrlval;
- ctrlval = EXT_G_MDIO_CMD_SP |
- (phyaddr EXT_G_MDIO_PHYADDR_POS) |
- (regidx EXT_G_MDIO_REGADDR_POS) |
- EXT_G_MDIO_DIV;
-
mdio_ld_cmd = nlm_read_nae_reg(nae_base, NAE_REG(block, intf_type,
(EXT_G0_MDIO_CTRL + bus * 4)));
if (mdio_ld_cmd EXT_G_MDIO_CMD_LCD) {
@@ -258,6 +258,14 @@ nlm_gmac_mdio_write(uint64_t nae_base, i
NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL_DATA+bus*4)),
val);
+ ctrlval = EXT_G_MDIO_CMD_SP |
+ (phyaddr EXT_G_MDIO_PHYADDR_POS) |
+ (regidx EXT_G_MDIO_REGADDR_POS);
+ if (nlm_is_xlp8xx_ax() || nlm_is_xlp8xx_b0() || nlm_is_xlp3xx_ax())
+ ctrlval |= EXT_G_MDIO_DIV;
+ else
+ ctrlval |= EXT_G_MDIO_DIV_WITH_HW_DIV64;
+
nlm_write_nae_reg(nae_base,
NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
ctrlval);
@@ -265,6 +273,7 @@ nlm_gmac_mdio_write(uint64_t nae_base, i
nlm_write_nae_reg(nae_base,
NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
ctrlval | EXT_G_MDIO_CMD_LCD);
+ DELAY(1000);
/* poll master busy bit until it is not busy */
while(nlm_read_nae_reg(nae_base,
@@ -291,11 +300,17 @@ int
nlm_gmac_mdio_reset(uint64_t nae_base, int bus, int block,
int intf_type)
{
+ uint32_t ctrlval;
+
+ if (nlm_is_xlp8xx_ax() || nlm_is_xlp8xx_b0() || nlm_is_xlp3xx_ax())
+ ctrlval = EXT_G_MDIO_DIV;
+ else
+ ctrlval = EXT_G_MDIO_DIV_WITH_HW_DIV64;
+
nlm_write_nae_reg(nae_base,
- NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
- EXT_G_MDIO_MMRST | EXT_G_MDIO_DIV);
+ NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL + bus * 4)),
+ EXT_G_MDIO_MMRST | ctrlval);
nlm_write_nae_reg(nae_base,
- NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
- EXT_G_MDIO_DIV);
+ NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL + bus * 4)), ctrlval);
return (0);
}
Modified: head/sys/mips/nlm/hal/mdio.h
==
--- head/sys/mips/nlm/hal/mdio.hMon Jul 9 10:36:43 2012
(r238292)
svn commit: r234646 - head/contrib/jemalloc/include/jemalloc
Author: jchandra Date: Tue Apr 24 11:42:48 2012 New Revision: 234646 URL: http://svn.freebsd.org/changeset/base/234646 Log: jemalloc: pointer size definition for 64-bit mips platforms LG_SIZEOF_PTR has to be defined as 3 when jemalloc is compiled for 64 bit platforms. Reviewed by: juli Approved by: jasone Modified: head/contrib/jemalloc/include/jemalloc/jemalloc_FreeBSD.h Modified: head/contrib/jemalloc/include/jemalloc/jemalloc_FreeBSD.h == --- head/contrib/jemalloc/include/jemalloc/jemalloc_FreeBSD.h Tue Apr 24 10:20:24 2012(r234645) +++ head/contrib/jemalloc/include/jemalloc/jemalloc_FreeBSD.h Tue Apr 24 11:42:48 2012(r234646) @@ -41,8 +41,12 @@ # define LG_SIZEOF_PTR2 #endif #ifdef __mips__ +#ifdef __mips_n64 +# define LG_SIZEOF_PTR3 +#else # define LG_SIZEOF_PTR2 #endif +#endif #ifdef __powerpc64__ # define LG_SIZEOF_PTR3 #elif defined(__powerpc__) ___ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to svn-src-all-unsubscr...@freebsd.org
svn commit: r233776 - head/sys/mips/mips
Author: jchandra Date: Mon Apr 2 11:41:33 2012 New Revision: 233776 URL: http://svn.freebsd.org/changeset/base/233776 Log: Reinstate the XTLB handler for CPU_NLM and CPU_RMI These platforms set the KX bit even when booted in 32 bit mode. So the XLTB handler is needed even when __mips_n64 is not defined. Modified: head/sys/mips/mips/machdep.c Modified: head/sys/mips/mips/machdep.c == --- head/sys/mips/mips/machdep.cMon Apr 2 11:27:20 2012 (r233775) +++ head/sys/mips/mips/machdep.cMon Apr 2 11:41:33 2012 (r233776) @@ -346,7 +346,7 @@ mips_vector_init(void) bcopy(MipsTLBMiss, (void *)MIPS_UTLB_MISS_EXC_VEC, MipsTLBMissEnd - MipsTLBMiss); -#ifdef __mips_n64 +#if defined(__mips_n64) || defined(CPU_RMI) || defined(CPU_NLM) bcopy(MipsTLBMiss, (void *)MIPS_XTLB_MISS_EXC_VEC, MipsTLBMissEnd - MipsTLBMiss); #endif ___ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to svn-src-all-unsubscr...@freebsd.org
svn commit: r233657 - head/sys/mips/nlm/dev/net/ucore
Author: jchandra
Date: Thu Mar 29 11:46:29 2012
New Revision: 233657
URL: http://svn.freebsd.org/changeset/base/233657
Log:
Remove unnecessary assembly code.
The compiler should generate lw/sw corresponding to register
operations.
Modified:
head/sys/mips/nlm/dev/net/ucore/ucore.h
head/sys/mips/nlm/dev/net/ucore/ucore_app.c
Modified: head/sys/mips/nlm/dev/net/ucore/ucore.h
==
--- head/sys/mips/nlm/dev/net/ucore/ucore.h Thu Mar 29 11:20:19 2012
(r233656)
+++ head/sys/mips/nlm/dev/net/ucore/ucore.h Thu Mar 29 11:46:29 2012
(r233657)
@@ -45,8 +45,8 @@
#defineUCORE_FR_FIFOEMPTY 0x802c
#defineUCORE_PKT_DISTR 0x8030
-#definePACKET_MEMORY (0xFFE00)
-#definePACKET_DATA_OFFSET (64)
+#definePACKET_MEMORY 0xFFE00
+#definePACKET_DATA_OFFSET 64
#defineSHARED_SCRATCH_MEM 0x18000
/* Distribution mode */
@@ -57,8 +57,8 @@
#defineVAL_PDL(x) (((x) 0xf) 4)
/*output buffer done*/
-#defineVAL_FSV(x) (x19)
-#defineVAL_FFS(x) (x14)
+#defineVAL_FSV(x) (x 19)
+#defineVAL_FFS(x) (x 14)
#defineFWD_DEST_ONLY 1
#defineFWD_ENQ_DIST_VEC2
@@ -69,37 +69,33 @@
#defineUSE_HASH_DST(1 20)
+static __inline unsigned int
+nlm_read_ucore_reg(int reg)
+{
+ volatile unsigned int *addr = (volatile void *)reg;
+
+ return (*addr);
+}
+
+static __inline void
+nlm_write_ucore_reg(int reg, unsigned int val)
+{
+ volatile unsigned int *addr = (volatile void *)reg;
+
+ *addr = val;
+}
#defineNLM_DEFINE_UCORE(name, reg) \
-static __inline__ unsigned int nlm_read_ucore_##name(void) \
+static __inline unsigned int \
+nlm_read_ucore_##name(void)\
{ \
- unsigned int __rv; \
- __asm__ __volatile__ ( \
- .set push\n \
- .set noreorder\n\
- .set mips32\n \
- li $8, %1\n \
- lw %0, ($8)\n \
- .set pop\n \
- : =r (__rv) \
- : i (reg) \
- : $8 \
- ); \
-return __rv; \
+ return nlm_read_ucore_reg(reg); \
} \
\
-static __inline__ void nlm_write_ucore_##name(unsigned int val)\
+static __inline void \
+nlm_write_ucore_##name(unsigned int v) \
{ \
- __asm__ __volatile__( \
- .set push\n \
- .set noreorder\n\
- .set mips32\n \
- li $8, %1\n \
- sw %0, ($8)\n \
- .set pop\n \
- :: r (val), i (reg) \
- : $8 \
- ); \
+ nlm_write_ucore_reg(reg, v);\
} struct __hack
Modified: head/sys/mips/nlm/dev/net/ucore/ucore_app.c
==
--- head/sys/mips/nlm/dev/net/ucore/ucore_app.c Thu Mar 29 11:20:19 2012
(r233656)
+++ head/sys/mips/nlm/dev/net/ucore/ucore_app.c Thu Mar 29 11:46:29 2012
(r233657)
@@ -38,7 +38,7 @@ int main(void)
int intf, hw_parser_error, context;
#endif
unsigned int pktrdy;
- int num_cachelines = 1518 6; /* pktsize / L3 cacheline size */
+ int num_cachelines = 1518 / 64 ; /* pktsize / L3 cacheline size */
/* Spray packets to using distribution vector */
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svn commit: r233532 - head/sys/mips/nlm
Author: jchandra
Date: Tue Mar 27 07:34:27 2012
New Revision: 233532
URL: http://svn.freebsd.org/changeset/base/233532
Log:
Fixes to the XLP startup code.
Changes are:
- Correct the order of calling init functions.
- Fix up checking excluding reset area.
Modified:
head/sys/mips/nlm/xlp_machdep.c
Modified: head/sys/mips/nlm/xlp_machdep.c
==
--- head/sys/mips/nlm/xlp_machdep.c Tue Mar 27 04:15:38 2012
(r233531)
+++ head/sys/mips/nlm/xlp_machdep.c Tue Mar 27 07:34:27 2012
(r233532)
@@ -358,14 +358,14 @@ mips_init(void)
mips_cpu_init();
cpuinfo.cache_coherent_dma = TRUE;
pmap_bootstrap();
+ mips_proc0_init();
+ mutex_init();
#ifdef DDB
kdb_init();
if (boothowto RB_KDB) {
kdb_enter(Boot flags requested debugger, NULL);
}
#endif
- mips_proc0_init();
- mutex_init();
}
unsigned int
@@ -433,8 +433,12 @@ xlp_mem_init(void)
/* first bar, start a bit after end */
if (base == 0) {
- base = (vm_paddr_t)MIPS_KSEG0_TO_PHYS(_end) + 0x2;
- lim = 0x0c00; /* TODO : hack to avoid uboot
packet mem */
+ base = (vm_paddr_t)MIPS_KSEG0_TO_PHYS(_end);
+ base = round_page(base) + 0x2; /* round up */
+ /* TODO : hack to avoid uboot packet mem, network
+* interface will write here if not reset correctly
+* by u-boot */
+ lim = 0x0c00;
}
if (base = XLP_MEM_LIM) {
printf(Mem [%d]: Ignore %#jx - %#jx\n, i,
@@ -456,7 +460,7 @@ xlp_mem_init(void)
* Exclude reset entry memory range 0x1fc0 - 0x2000
* from free memory
*/
- if (base = 0x1fc0 (base + lim) 0x1fc0) {
+ if (base 0x2000 lim 0x1fc0) {
uint64_t base0, lim0, base1, lim1;
base0 = base;
@@ -542,6 +546,9 @@ platform_start(__register_t a0 __unused,
/* setup for the startup core */
xlp_setup_mmu();
+ /* Read/Guess/setup board information */
+ nlm_board_info_setup();
+
/* MIPS generic init */
mips_init();
@@ -549,7 +556,6 @@ platform_start(__register_t a0 __unused,
* XLP specific post initialization
* initialize other on chip stuff
*/
- nlm_board_info_setup();
xlp_pic_init();
mips_timer_init_params(xlp_cpu_frequency, 0);
___
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svn commit: r233533 - in head/sys/mips/nlm: . hal
Author: jchandra
Date: Tue Mar 27 07:39:05 2012
New Revision: 233533
URL: http://svn.freebsd.org/changeset/base/233533
Log:
Support for XLP4xx and XLP 8xx B0 revision
- Add 4xx processor IDs, add workaround in CPU detection code.
- Update frequency detection code for XLP 8xx.
- Add setting device frequency code.
- Update processor ID checking code.
Modified:
head/sys/mips/nlm/hal/nlm_hal.c
head/sys/mips/nlm/hal/sys.h
head/sys/mips/nlm/xlp.h
head/sys/mips/nlm/xlp_machdep.c
Modified: head/sys/mips/nlm/hal/nlm_hal.c
==
--- head/sys/mips/nlm/hal/nlm_hal.c Tue Mar 27 07:34:27 2012
(r233532)
+++ head/sys/mips/nlm/hal/nlm_hal.c Tue Mar 27 07:39:05 2012
(r233533)
@@ -55,33 +55,81 @@ int pic_irt_pcie_lnk2;
int pic_irt_pcie_lnk3;
uint32_t
-xlp_get_cpu_frequency(int core)
+xlp_get_cpu_frequency(int node, int core)
{
- uint64_t sysbase = nlm_get_sys_regbase(nlm_nodeid());
- uint64_t num;
+ uint64_t sysbase = nlm_get_sys_regbase(node);
unsigned int pll_divf, pll_divr, dfs_div, ext_div;
- unsigned int rstval, dfsval, denom;
+ unsigned int rstval, dfsval;
rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG);
dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE);
pll_divf = ((rstval 10) 0x7f) + 1;
pll_divr = ((rstval 8) 0x3) + 1;
- ext_div = ((rstval 30) 0x3) + 1;
- dfs_div = ((dfsval (core * 4)) 0xf) + 1;
+ if (!nlm_is_xlp8xx_ax())
+ ext_div = ((rstval 30) 0x3) + 1;
+ else
+ ext_div = 1;
+ dfs_div = ((dfsval (core 2)) 0xf) + 1;
- num = 8ULL * pll_divf;
- denom = 3 * pll_divr * ext_div * dfs_div;
- num = num/denom;
- return (num);
+ return ((8ULL * pll_divf)/(3 * pll_divr * ext_div * dfs_div));
+}
+
+static u_int
+nlm_get_device_frequency(uint64_t sysbase, int devtype)
+{
+ uint32_t pllctrl, dfsdiv, spf, spr, div_val;
+ int extra_div;
+
+ pllctrl = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL);
+ if (devtype = 7)
+ div_val = nlm_read_sys_reg(sysbase, SYS_DFS_DIV_VALUE0);
+ else {
+ devtype -= 8;
+ div_val = nlm_read_sys_reg(sysbase, SYS_DFS_DIV_VALUE1);
+ }
+ dfsdiv = ((div_val (devtype 2)) 0xf) + 1;
+ spf = (pllctrl 3 0x7f) + 1;
+ spr = (pllctrl 1 0x03) + 1;
+ extra_div = nlm_is_xlp8xx_ax() ? 1 : 2;
+
+ return ((400 * spf) / (3 * extra_div * spr * dfsdiv));
+}
+
+int
+nlm_set_device_frequency(int node, int devtype, int frequency)
+{
+ uint64_t sysbase;
+ u_int cur_freq;
+ int dec_div;
+
+ sysbase = nlm_get_sys_regbase(node);
+ cur_freq = nlm_get_device_frequency(sysbase, devtype);
+ if (cur_freq (frequency - 5))
+ dec_div = 1;
+ else
+ dec_div = 0;
+
+ for(;;) {
+ if ((cur_freq = (frequency - 5)) (cur_freq = frequency))
+ break;
+ if (dec_div)
+ nlm_write_sys_reg(sysbase, SYS_DFS_DIV_DEC_CTRL,
+ (1 devtype));
+ else
+ nlm_write_sys_reg(sysbase, SYS_DFS_DIV_INC_CTRL,
+ (1 devtype));
+ cur_freq = nlm_get_device_frequency(sysbase, devtype);
+ }
+ return (nlm_get_device_frequency(sysbase, devtype));
}
void
-nlm_pic_irt_init(void)
+nlm_pic_irt_init(int node)
{
- pic_irt_ehci0 = nlm_irtstart(nlm_get_usb_pcibase(nlm_nodeid(), 0));
- pic_irt_ehci1 = nlm_irtstart(nlm_get_usb_pcibase(nlm_nodeid(), 3));
- pic_irt_uart0 = nlm_irtstart(nlm_get_uart_pcibase(nlm_nodeid(), 0));
- pic_irt_uart1 = nlm_irtstart(nlm_get_uart_pcibase(nlm_nodeid(), 1));
+ pic_irt_ehci0 = nlm_irtstart(nlm_get_usb_pcibase(node, 0));
+ pic_irt_ehci1 = nlm_irtstart(nlm_get_usb_pcibase(node, 3));
+ pic_irt_uart0 = nlm_irtstart(nlm_get_uart_pcibase(node, 0));
+ pic_irt_uart1 = nlm_irtstart(nlm_get_uart_pcibase(node, 1));
/* Hardcoding the PCIE IRT information as PIC doesn't
understand any value other than 78,79,80,81 for PCIE0/1/2/3 */
@@ -107,24 +155,25 @@ int
xlp_irt_to_irq(int irt)
{
if (irt == pic_irt_ehci0)
- return PIC_EHCI_0_IRQ;
+ return PIC_EHCI_0_IRQ;
else if (irt == pic_irt_ehci1)
- return PIC_EHCI_1_IRQ;
+ return PIC_EHCI_1_IRQ;
else if (irt == pic_irt_uart0)
- return PIC_UART_0_IRQ;
+ return PIC_UART_0_IRQ;
else if (irt == pic_irt_uart1)
- return PIC_UART_1_IRQ;
+ return PIC_UART_1_IRQ;
else if (irt == pic_irt_pcie_lnk0)
- return PIC_PCIE_0_IRQ;
+ return PIC_PCIE_0_IRQ;
else if (irt == pic_irt_pcie_lnk1)
-
svn commit: r233534 - head/sys/mips/nlm
Author: jchandra
Date: Tue Mar 27 07:47:13 2012
New Revision: 233534
URL: http://svn.freebsd.org/changeset/base/233534
Log:
Switch to interrupt based message handling for XLP 8xx B0.
Fixup some style issues in the file as well.
Modified:
head/sys/mips/nlm/cms.c
Modified: head/sys/mips/nlm/cms.c
==
--- head/sys/mips/nlm/cms.c Tue Mar 27 07:39:05 2012(r233533)
+++ head/sys/mips/nlm/cms.c Tue Mar 27 07:47:13 2012(r233534)
@@ -65,9 +65,8 @@ __FBSDID($FreeBSD$);
#include mips/nlm/msgring.h
#include mips/nlm/interrupt.h
#include mips/nlm/xlp.h
-#include mips/nlm/board.h
-#define MSGRNG_NSTATIONS 1024
+#defineMSGRNG_NSTATIONS1024
/*
* Keep track of our message ring handler threads, each core has a
* different message station. Ideally we will need to start a few
@@ -92,7 +91,7 @@ struct tx_stn_handler {
static struct tx_stn_handler msgmap[MSGRNG_NSTATIONS];
static struct mtx msgmap_lock;
uint32_t xlp_msg_thread_mask;
-static int xlp_msg_threads_per_core = 3;
+static int xlp_msg_threads_per_core = XLP_MAX_THREADS;
static void create_msgring_thread(int hwtid);
static int msgring_process_fast_intr(void *arg);
@@ -105,7 +104,7 @@ static int fmn_msgcount[XLP_MAX_CORES *
static int fmn_loops[XLP_MAX_CORES * XLP_MAX_THREADS];
/* Whether polled driver implementation */
-static int polled = 1;
+static int polled = 0;
/* We do only i/o device credit setup here. CPU credit setup is now
* moved to xlp_msgring_cpu_init() so that the credits get setup
@@ -125,7 +124,7 @@ xlp_cms_credit_setup(int credit)
for (i = 0; i XLP_MAX_NODES; i++) {
cmspcibase = nlm_get_cms_pcibase(i);
if (!nlm_dev_exists(XLP_IO_CMS_OFFSET(i)))
- continue;
+ continue;
cmsbase = nlm_get_cms_regbase(i);
maxqid = nlm_read_reg(cmspcibase, XLP_PCI_DEVINFO_REG0);
for (dev = 0; dev 8; dev++) {
@@ -136,7 +135,7 @@ xlp_cms_credit_setup(int credit)
pcibase = nlm_pcicfg_base(devoffset);
src = nlm_qidstart(pcibase);
if (src == 0)
- continue;
+ continue;
#if 0 /* Debug */
printf(Setup CMS credits for queues );
printf([%d to %d] from src %d\n, 0,
@@ -163,7 +162,7 @@ xlp_msgring_cpu_init(int node, int cpu,
if((cpu % 4) == 0) {
src = cpu 2; /* each thread has 4 vc's */
for (qid = 0; qid maxqid; qid++)
- nlm_cms_setup_credits(cmsbase, qid, src, credit);
+ nlm_cms_setup_credits(cmsbase, qid, src, credit);
}
}
@@ -181,7 +180,6 @@ xlp_handle_msg_vc(u_int vcmask, int max_
int n_msgs = 0, vc, m, hwtid;
u_int msgmask;
-
hwtid = nlm_cpuid();
for (;;) {
/* check if VC empty */
@@ -211,8 +209,9 @@ xlp_handle_msg_vc(u_int vcmask, int max_
}
he = msgmap[srcid];
if(he-action != NULL)
- (he-action)(vc, size, code, srcid, msg,
he-arg);
-#if 1 /* defined DEBUG */
+ (he-action)(vc, size, code, srcid, msg,
+ he-arg);
+#if 0
else
printf([%s]: No Handler for msg from stn %d,
vc=%d, size=%d, msg0=%jx, droppinge\n,
@@ -226,7 +225,7 @@ xlp_handle_msg_vc(u_int vcmask, int max_
break; /* nothing done in this iter */
n_msgs += m;
if (max_msgs 0 n_msgs = max_msgs)
- break;
+ break;
}
return (n_msgs);
@@ -248,7 +247,7 @@ xlp_discard_msg_vc(u_int vcmask)
/* break if there is no msg or error */
if (status != 0)
- break;
+ break;
}
}
}
@@ -382,9 +381,6 @@ create_msgring_thread(int hwtid)
sched_class(td, PRI_ITHD);
sched_add(td, SRQ_INTR);
thread_unlock(td);
- if (bootverbose)
- printf(Msgring handler create on cpu %d (%s)\n,
- hwtid, td-td_name);
}
int
@@ -393,7 +389,9 @@ register_msgring_handler(int startb, int
{
int i;
- printf(Register handler %d-%d %p(%p)\n, startb, endb, action, arg);
+ if (bootverbose)
+ printf(Register handler %d-%d %p(%p)\n,
+ startb, endb, action, arg);
KASSERT(startb = 0 startb = endb endb MSGRNG_NSTATIONS,
(Invalid value for bucket range %d,%d, startb, endb));
@@ -421,11
svn commit: r233535 - head/sys/mips/nlm
Author: jchandra Date: Tue Mar 27 07:51:42 2012 New Revision: 233535 URL: http://svn.freebsd.org/changeset/base/233535 Log: Update the L1D cache flush sequence when enabling threads. Added more comments to the code. Modified: head/sys/mips/nlm/mpreset.S Modified: head/sys/mips/nlm/mpreset.S == --- head/sys/mips/nlm/mpreset.S Tue Mar 27 07:47:13 2012(r233534) +++ head/sys/mips/nlm/mpreset.S Tue Mar 27 07:51:42 2012(r233535) @@ -55,24 +55,24 @@ .setnoreorder li $8, LSU_DEBUG_DATA0 /* use register number to handle */ li $9, LSU_DEBUG_ADDR /* different ABIs */ - li t2, 0 - li t3, 0x200 + li t2, 0 /* index */ + li t3, 0x1000 /* loop count, 512 sets * 8 whatever? */ 1: sll v0, t2, 5 MTCR(0, 8) - ori v1, v0, 0x3 + ori v1, v0, 0x3 /* way0 | write_enable | write_active */ MTCR(3, 9) 2: MFCR(3, 9) - andiv1, 0x1 + andiv1, 0x1 /* wait for write_active == 0 */ bnezv1, 2b nop MTCR(0, 8) - ori v1, v0, 0x7 + ori v1, v0, 0x7 /* way1 | write_enable | write_active */ MTCR(3, 9) 3: MFCR(3, 9) - andiv1, 0x1 + andiv1, 0x1 /* wait for write_active == 0 */ bnezv1, 3b nop addit2, 1 @@ -195,7 +195,7 @@ LEAF(xlp_enable_threads) mfc0t1, MIPS_COP_0_STATUS movesp, t0 /* Restore the real SP */ - jr ra + jr.hb ra nop END(xlp_enable_threads) #endif ___ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to svn-src-all-unsubscr...@freebsd.org
svn commit: r233536 - in head/sys/mips/nlm: . hal
Author: jchandra
Date: Tue Mar 27 07:57:41 2012
New Revision: 233536
URL: http://svn.freebsd.org/changeset/base/233536
Log:
XLP PCIe code update.
- XLP supports hardware swap for PCIe IO/MEM accesses. Since we
are in big-endian mode, enable hardware swap and use the normal
bus space.
- move some printfs to bootverbose, and remove others.
- fix SoC device resource allocation code
- Do not use '|' while updating PCIE_BRIDGE_MSI_ADDRL
- some style fixes
In collaboration with: Venkatesh J. V. (venkatesh at netlogicmicro com)
Modified:
head/sys/mips/nlm/hal/iomap.h
head/sys/mips/nlm/hal/pcibus.h
head/sys/mips/nlm/xlp_pci.c
Modified: head/sys/mips/nlm/hal/iomap.h
==
--- head/sys/mips/nlm/hal/iomap.h Tue Mar 27 07:51:42 2012
(r233535)
+++ head/sys/mips/nlm/hal/iomap.h Tue Mar 27 07:57:41 2012
(r233536)
@@ -190,6 +190,16 @@ nlm_uenginenum(uint64_t pcibase)
return nlm_read_reg(pcibase, XLP_PCI_UCODEINFO_REG);
}
+/*
+ * Find node on which a given Soc device is located.
+ * input is the pci device (slot) number.
+ */
+static __inline__ int
+nlm_get_device_node(int device)
+{
+ return (device / 8);
+}
+
#endif /* !LOCORE or !__ASSEMBLY */
#endif /* __NLM_HAL_IOMAP_H__ */
Modified: head/sys/mips/nlm/hal/pcibus.h
==
--- head/sys/mips/nlm/hal/pcibus.h Tue Mar 27 07:51:42 2012
(r233535)
+++ head/sys/mips/nlm/hal/pcibus.h Tue Mar 27 07:57:41 2012
(r233536)
@@ -57,16 +57,26 @@
#defineMSI_MIPS_DATA_INTVEC0x00ff
-#definePCIE_BRIDGE_CMD 0x1
-#definePCIE_BRIDGE_MSI_CAP 0x14
-#definePCIE_BRIDGE_MSI_ADDRL 0x15
-#definePCIE_BRIDGE_MSI_ADDRH 0x16
-#definePCIE_BRIDGE_MSI_DATA0x17
+/* PCIE Memory and IO regions */
+#definePCIE_MEM_BASE 0xd000ULL
+#definePCIE_MEM_LIMIT 0xdfffULL
+#definePCIE_IO_BASE0x1400ULL
+#definePCIE_IO_LIMIT 0x15ffULL
+
+#definePCIE_BRIDGE_CMD 0x1
+#definePCIE_BRIDGE_MSI_CAP 0x14
+#definePCIE_BRIDGE_MSI_ADDRL 0x15
+#definePCIE_BRIDGE_MSI_ADDRH 0x16
+#definePCIE_BRIDGE_MSI_DATA0x17
/* XLP Global PCIE configuration space registers */
-#definePCIE_MSI_STATUS 0x25A
-#definePCIE_MSI_EN 0x25B
-#definePCIE_INT_EN00x261
+#definePCIE_BYTE_SWAP_MEM_BASE 0x247
+#definePCIE_BYTE_SWAP_MEM_LIM 0x248
+#definePCIE_BYTE_SWAP_IO_BASE 0x249
+#definePCIE_BYTE_SWAP_IO_LIM 0x24A
+#definePCIE_MSI_STATUS 0x25A
+#definePCIE_MSI_EN 0x25B
+#definePCIE_INT_EN00x261
/* PCIE_MSI_EN */
#definePCIE_MSI_VECTOR_INT_EN 0x
Modified: head/sys/mips/nlm/xlp_pci.c
==
--- head/sys/mips/nlm/xlp_pci.c Tue Mar 27 07:51:42 2012(r233535)
+++ head/sys/mips/nlm/xlp_pci.c Tue Mar 27 07:57:41 2012(r233536)
@@ -61,6 +61,7 @@ __FBSDID($FreeBSD$);
#include mips/nlm/hal/iomap.h
#include mips/nlm/hal/mips-extns.h
#include mips/nlm/hal/pic.h
+#include mips/nlm/hal/bridge.h
#include mips/nlm/hal/pcibus.h
#include mips/nlm/hal/uart.h
#include mips/nlm/xlp.h
@@ -77,7 +78,6 @@ static struct rman irq_rman, port_rman,
static void
xlp_pci_init_resources(void)
{
-
irq_rman.rm_start = 0;
irq_rman.rm_end = 255;
irq_rman.rm_type = RMAN_ARRAY;
@@ -91,7 +91,7 @@ xlp_pci_init_resources(void)
port_rman.rm_type = RMAN_ARRAY;
port_rman.rm_descr = I/O ports;
if (rman_init(port_rman)
- || rman_manage_region(port_rman, 0x1400UL, 0x15ffUL))
+ || rman_manage_region(port_rman, PCIE_IO_BASE, PCIE_IO_LIMIT))
panic(pci_init_resources port_rman);
mem_rman.rm_start = 0;
@@ -99,15 +99,19 @@ xlp_pci_init_resources(void)
mem_rman.rm_type = RMAN_ARRAY;
mem_rman.rm_descr = I/O memory;
if (rman_init(mem_rman)
- || rman_manage_region(mem_rman, 0xd000ULL, 0xdfffULL))
+ || rman_manage_region(mem_rman, PCIE_MEM_BASE, PCIE_MEM_LIMIT))
panic(pci_init_resources mem_rman);
+ /*
+* This includes the GBU (nor flash) memory range and the PCIe
+* memory area.
+*/
emul_rman.rm_start = 0;
emul_rman.rm_end = ~0ul;
emul_rman.rm_type = RMAN_ARRAY;
emul_rman.rm_descr = Emulated MEMIO;
if (rman_init(emul_rman)
- || rman_manage_region(emul_rman, 0x1800ULL, 0x18ffULL))
svn commit: r233537 - in head/sys: conf dev/iicbus
Author: jchandra
Date: Tue Mar 27 09:48:18 2012
New Revision: 233537
URL: http://svn.freebsd.org/changeset/base/233537
Log:
Move driver for DS1374 RTC to sys/dev/iicbus
The earlier version of the driver is sys/mips/rmi/dev/iic/ds1374u.c
Convert all references to ds1374u to ds1374, and use DEVMETHOD_END.
Also update the license header as Netlogic is now Broadcom.
Added:
head/sys/dev/iicbus/ds1374.c (contents, props changed)
Modified:
head/sys/conf/NOTES
head/sys/conf/files
Modified: head/sys/conf/NOTES
==
--- head/sys/conf/NOTES Tue Mar 27 07:57:41 2012(r233536)
+++ head/sys/conf/NOTES Tue Mar 27 09:48:18 2012(r233537)
@@ -2547,9 +2547,11 @@ device iicsmb # smb over i2c bridge
# I2C peripheral devices
#
# ds133x Dallas Semiconductor DS1337, DS1338 and DS1339 RTC
+# ds1374 Dallas Semiconductor DS1374 RTC
# ds1672 Dallas Semiconductor DS1672 RTC
#
device ds133x
+device ds1374
device ds1672
# Parallel-Port Bus
Modified: head/sys/conf/files
==
--- head/sys/conf/files Tue Mar 27 07:57:41 2012(r233536)
+++ head/sys/conf/files Tue Mar 27 09:48:18 2012(r233537)
@@ -1149,6 +1149,7 @@ dev/ieee488/tnt4882.c optional tnt4882
dev/ieee488/upd7210.c optional pcii | tnt4882
dev/iicbus/ad7418.coptional ad7418
dev/iicbus/ds133x.coptional ds133x
+dev/iicbus/ds1374.coptional ds1374
dev/iicbus/ds1672.coptional ds1672
dev/iicbus/icee.c optional icee
dev/iicbus/if_ic.c optional ic
Added: head/sys/dev/iicbus/ds1374.c
==
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/dev/iicbus/ds1374.cTue Mar 27 09:48:18 2012
(r233537)
@@ -0,0 +1,143 @@
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in
+ *the documentation and/or other materials provided with the
+ *distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include sys/cdefs.h
+__FBSDID($FreeBSD$);
+
+#include sys/param.h
+#include sys/systm.h
+#include sys/kernel.h
+#include sys/module.h
+#include sys/bus.h
+#include sys/clock.h
+#include sys/time.h
+#include sys/resource.h
+#include sys/rman.h
+
+#include mips/include/bus.h
+#include mips/include/cpu.h
+#include mips/include/cpufunc.h
+#include mips/include/frame.h
+#include mips/include/resource.h
+
+#include dev/iicbus/iiconf.h
+#include dev/iicbus/iicbus.h
+
+#include iicbus_if.h
+#include clock_if.h
+
+#defineDS1374_RTC_COUNTER 0 /* counter (bytes 0-3) */
+
+struct ds1374_softc {
+ uint32_tsc_addr;
+ device_tsc_dev;
+};
+
+static int
+ds1374_probe(device_t dev)
+{
+ device_set_desc(dev, DS1374 RTC);
+ return (0);
+}
+
+static int
+ds1374_attach(device_t dev)
+{
+ struct ds1374_softc *sc = device_get_softc(dev);
+
+ if(sc==NULL) {
+ printf(ds1374_attach device_get_softc failed\n);
+ return (0);
+ }
+ sc-sc_dev = dev;
+ sc-sc_addr = iicbus_get_addr(dev);
+
+ clock_register(dev, 1000);
+ return (0);
+}
+
+static int
+ds1374_settime(device_t dev, struct timespec *ts)
+{
+ /* NB: register pointer precedes actual data */
+ uint8_t data[5] = { DS1374_RTC_COUNTER };
+ struct ds1374_softc *sc = device_get_softc(dev);
+ struct iic_msg msgs[1] = {
+{ sc-sc_addr, IIC_M_WR, 5, data },
+ };
+
+ data[1] = (ts-tv_sec 0) 0xff;
+ data[2] = (ts-tv_sec 8) 0xff;
+
svn commit: r233538 - head/sys/dev/iicbus
Author: jchandra Date: Tue Mar 27 10:00:33 2012 New Revision: 233538 URL: http://svn.freebsd.org/changeset/base/233538 Log: Fix property name, r233537 used mime-type instead of svn:mime-type Modified: Directory Properties: head/sys/dev/iicbus/ds1374.c (props changed) ___ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to svn-src-all-unsubscr...@freebsd.org
svn commit: r233539 - in head/sys: conf dev/iicbus
Author: jchandra
Date: Tue Mar 27 10:44:32 2012
New Revision: 233539
URL: http://svn.freebsd.org/changeset/base/233539
Log:
Driver for OpenCores I2C controller.
Add a Simple polled driver iicoc for the OpenCores I2C controller. This
is used in Netlogic XLP processors.
Submitted by: Sreekanth M. S. (kanthms at netlogicmicro com)
Added:
head/sys/dev/iicbus/iicoc.c (contents, props changed)
head/sys/dev/iicbus/iicoc.h (contents, props changed)
Modified:
head/sys/conf/NOTES
head/sys/conf/files
Modified: head/sys/conf/NOTES
==
--- head/sys/conf/NOTES Tue Mar 27 10:00:33 2012(r233538)
+++ head/sys/conf/NOTES Tue Mar 27 10:44:32 2012(r233539)
@@ -2530,6 +2530,7 @@ devicesmb
# ic i2c network interface
# iic i2c standard io
# iicsmb i2c to smb bridge. Allow i2c i/o with smb commands.
+# iicoc simple polling driver for OpenCores I2C controller
#
# Supported interfaces:
# bktr brooktree848 I2C software interface
@@ -2543,6 +2544,7 @@ deviceiicbb
device ic
device iic
device iicsmb # smb over i2c bridge
+device iicoc # OpenCores I2C controller support
# I2C peripheral devices
#
Modified: head/sys/conf/files
==
--- head/sys/conf/files Tue Mar 27 10:00:33 2012(r233538)
+++ head/sys/conf/files Tue Mar 27 10:44:32 2012(r233539)
@@ -1161,6 +1161,7 @@ dev/iicbus/iicbus_if.moptional iicbus
dev/iicbus/iiconf.coptional iicbus
dev/iicbus/iicsmb.coptional iicsmb \
dependency iicbus_if.h
+dev/iicbus/iicoc.c optional iicoc
dev/iir/iir.c optional iir
dev/iir/iir_ctrl.c optional iir
dev/iir/iir_pci.c optional iir pci
Added: head/sys/dev/iicbus/iicoc.c
==
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/dev/iicbus/iicoc.c Tue Mar 27 10:44:32 2012(r233539)
@@ -0,0 +1,390 @@
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in
+ *the documentation and/or other materials provided with the
+ *distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include sys/cdefs.h
+__FBSDID($FreeBSD$);
+
+#include sys/param.h
+#include sys/systm.h
+#include sys/kernel.h
+#include sys/lock.h
+#include sys/module.h
+#include sys/mutex.h
+#include sys/bus.h
+#include sys/rman.h
+
+#include machine/bus.h
+
+#include dev/iicbus/iiconf.h
+#include dev/iicbus/iicbus.h
+#include dev/iicbus/iicoc.h
+
+#include dev/pci/pcireg.h
+#include dev/pci/pcivar.h
+
+#include iicbus_if.h
+
+static devclass_t iicoc_devclass;
+
+/*
+ * Device methods
+ */
+static int iicoc_probe(device_t);
+static int iicoc_attach(device_t);
+static int iicoc_detach(device_t);
+
+static int iicoc_start(device_t dev, u_char slave, int timeout);
+static int iicoc_stop(device_t dev);
+static int iicoc_read(device_t dev, char *buf,
+int len, int *read, int last, int delay);
+static int iicoc_write(device_t dev, const char *buf,
+int len, int *sent, int timeout);
+static int iicoc_repeated_start(device_t dev, u_char slave, int timeout);
+
+struct iicoc_softc {
+ device_tdev;/* Self */
+ u_int reg_shift; /* Chip specific */
+ u_int clockfreq;
+ u_int i2cfreq;
+ struct resource *mem_res; /* Memory resource */
+ int mem_rid;
+ int sc_started;
+ uint8_t i2cdev_addr;
+ device_tiicbus;
+ struct mtx
svn commit: r233540 - in head/sys/mips: conf nlm
Author: jchandra Date: Tue Mar 27 11:17:04 2012 New Revision: 233540 URL: http://svn.freebsd.org/changeset/base/233540 Log: I2C support for XLP, add hints for I2C devices and update PCI resource allocation code. Added: head/sys/mips/conf/XLP.hints (contents, props changed) Modified: head/sys/mips/conf/std.XLP head/sys/mips/nlm/xlp_pci.c Added: head/sys/mips/conf/XLP.hints == --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/mips/conf/XLP.hintsTue Mar 27 11:17:04 2012 (r233540) @@ -0,0 +1,5 @@ +# $FreeBSD$ + +# RTC +hint.ds1374_rtc.0.at=iicbus1 +hint.ds1374_rtc.0.addr=0xd0 Modified: head/sys/mips/conf/std.XLP == --- head/sys/mips/conf/std.XLP Tue Mar 27 10:44:32 2012(r233539) +++ head/sys/mips/conf/std.XLP Tue Mar 27 11:17:04 2012(r233540) @@ -5,6 +5,8 @@ makeoptions MODULES_OVERRIDE= makeoptionsDEBUG=-g# Build kernel with gdb(1) debug symbols #profile 2 +hints XLP.hints + optionsSCHED_ULE # ULE scheduler #options VERBOSE_SYSINIT #options SCHED_4BSD # 4BSD scheduler @@ -55,6 +57,11 @@ options ALT_BREAK_TO_DEBUGGER optionsGEOM_UZIP +# Device tree +optionsFDT +optionsFDT_DTB_STATIC +makeoptionsFDT_DTS_FILE=xlp-basic.dts + # Pseudo device loop device random @@ -83,6 +90,8 @@ deviceehci# EHCI PCI-USB interface #deviceuhid# Human Interface Devices device umass # Requires scbus and da -optionsFDT -optionsFDT_DTB_STATIC -makeoptionsFDT_DTS_FILE=xlp-basic.dts +# i2c driver and devices +device iic +device iicbus +device iicoc +device ds1374 # RTC on XLP boards Modified: head/sys/mips/nlm/xlp_pci.c == --- head/sys/mips/nlm/xlp_pci.c Tue Mar 27 10:44:32 2012(r233539) +++ head/sys/mips/nlm/xlp_pci.c Tue Mar 27 11:17:04 2012(r233540) @@ -497,6 +497,15 @@ assign_soc_resource(device_t child, int *rm = emul_rman; *bst = uart_bus_space_mem; break; + + case PCI_DEVICE_ID_NLM_I2C: + *va = nlm_pcicfg_base(XLP_IO_I2C_OFFSET(node, unit)) + + XLP_IO_PCI_HDRSZ; + *startp = MIPS_KSEG1_TO_PHYS(*va); + *countp = 0x100; + *rm = emul_rman; + *bst = uart_bus_space_mem; + break; } /* calculate end if allocated */ if (*rm) ___ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to svn-src-all-unsubscr...@freebsd.org
svn commit: r233541 - in head/sys/mips: conf nlm nlm/dev nlm/dev/sec nlm/hal
Author: jchandra
Date: Tue Mar 27 11:43:46 2012
New Revision: 233541
URL: http://svn.freebsd.org/changeset/base/233541
Log:
Opencrypto driver for XLP Security and RSA/ECC blocks
Support for the Security and RSA blocks on XLP SoC. Even though
the XLP supports many more algorithms, only the ones supported
in OCF have been added.
Submitted by: Venkatesh J. V. (venkatesh at netlogicmicro com)
Added:
head/sys/mips/nlm/dev/
head/sys/mips/nlm/dev/sec/
head/sys/mips/nlm/dev/sec/nlmrsa.c (contents, props changed)
head/sys/mips/nlm/dev/sec/nlmrsalib.h (contents, props changed)
head/sys/mips/nlm/dev/sec/nlmsec.c (contents, props changed)
head/sys/mips/nlm/dev/sec/nlmseclib.c (contents, props changed)
head/sys/mips/nlm/dev/sec/nlmseclib.h (contents, props changed)
head/sys/mips/nlm/dev/sec/rsa_ucode.h (contents, props changed)
head/sys/mips/nlm/hal/nlmsaelib.h (contents, props changed)
Modified:
head/sys/mips/conf/std.XLP
head/sys/mips/nlm/files.xlp
head/sys/mips/nlm/hal/iomap.h
Modified: head/sys/mips/conf/std.XLP
==
--- head/sys/mips/conf/std.XLP Tue Mar 27 11:17:04 2012(r233540)
+++ head/sys/mips/conf/std.XLP Tue Mar 27 11:43:46 2012(r233541)
@@ -95,3 +95,13 @@ device iic
device iicbus
device iicoc
device ds1374 # RTC on XLP boards
+
+# Crypto
+device crypto
+device cryptodev
+device nlmsec
+device nlmrsa
+
+# Options that use crypto
+optionsIPSEC
+optionsGEOM_ELI
Added: head/sys/mips/nlm/dev/sec/nlmrsa.c
==
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/mips/nlm/dev/sec/nlmrsa.c Tue Mar 27 11:43:46 2012
(r233541)
@@ -0,0 +1,556 @@
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in
+ *the documentation and/or other materials provided with the
+ *distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include sys/cdefs.h
+__FBSDID($FreeBSD$);
+
+#include sys/cdefs.h
+#include sys/param.h
+#include sys/systm.h
+#include sys/proc.h
+#include sys/errno.h
+#include sys/malloc.h
+#include sys/kernel.h
+#include sys/module.h
+#include sys/mbuf.h
+#include sys/lock.h
+#include sys/mutex.h
+#include sys/sysctl.h
+#include sys/bus.h
+#include sys/random.h
+#include sys/rman.h
+#include sys/uio.h
+#include sys/kobj.h
+
+#include dev/pci/pcivar.h
+
+#include opencrypto/cryptodev.h
+
+#include cryptodev_if.h
+
+#include vm/vm.h
+#include vm/pmap.h
+
+#include mips/nlm/hal/haldefs.h
+#include mips/nlm/hal/iomap.h
+#include mips/nlm/xlp.h
+#include mips/nlm/hal/sys.h
+#include mips/nlm/hal/fmn.h
+#include mips/nlm/hal/nlmsaelib.h
+#include mips/nlm/dev/sec/nlmrsalib.h
+#include mips/nlm/dev/sec/rsa_ucode.h
+#include mips/nlm/hal/cop2.h
+#include mips/nlm/hal/mips-extns.h
+#include mips/nlm/msgring.h
+
+#ifdef NLM_RSA_DEBUG
+int print_krp_params(struct cryptkop *krp);
+#endif
+
+static int xlp_rsa_init(struct xlp_rsa_softc *sc, int node);
+static int xlp_rsa_newsession(device_t , uint32_t *, struct cryptoini *);
+static int xlp_rsa_freesession(device_t , uint64_t);
+static int xlp_rsa_kprocess(device_t , struct cryptkop *, int);
+static int xlp_get_rsa_opsize(struct xlp_rsa_command *cmd, unsigned int bits);
+static void xlp_free_cmd_params(struct xlp_rsa_command *cmd);
+static int xlp_rsa_inp2hwformat(uint8_t *src, uint8_t *dst,
+uint32_t paramsize, uint8_t result);
+
+static int xlp_rsa_probe(device_t);
+static int xlp_rsa_attach(device_t);
+static int xlp_rsa_detach(device_t);
+
+static device_method_t xlp_rsa_methods[] = {
+ /* device interface */
+
svn commit: r233545 - in head/sys/mips: conf nlm nlm/dev/net nlm/dev/net/ucore nlm/hal
Author: jchandra
Date: Tue Mar 27 14:05:12 2012
New Revision: 233545
URL: http://svn.freebsd.org/changeset/base/233545
Log:
xlpge : driver for XLP network accelerator
Features:
- network driver for the four 10G interfaces and two management ports
on XLP 8xx.
- Support 4xx and 3xx variants of the processor.
- Source code and firmware building for the 16 mips32r2 micro-code engines
in the Network Accelerator.
- Basic initialization code for Packet ordering Engine.
Submitted by: Prabhath Raman (prabhath at netlogicmicro com)
[refactored and fixed up for style by jchandra]
Added:
head/sys/mips/nlm/dev/net/
head/sys/mips/nlm/dev/net/mdio.c (contents, props changed)
head/sys/mips/nlm/dev/net/nae.c (contents, props changed)
head/sys/mips/nlm/dev/net/sgmii.c (contents, props changed)
head/sys/mips/nlm/dev/net/ucore/
head/sys/mips/nlm/dev/net/ucore/crt0_basic.S (contents, props changed)
head/sys/mips/nlm/dev/net/ucore/ld.ucore.S (contents, props changed)
head/sys/mips/nlm/dev/net/ucore/ucore.h (contents, props changed)
head/sys/mips/nlm/dev/net/ucore/ucore_app.c (contents, props changed)
head/sys/mips/nlm/dev/net/xaui.c (contents, props changed)
head/sys/mips/nlm/dev/net/xlpge.c (contents, props changed)
head/sys/mips/nlm/dev/net/xlpge.h (contents, props changed)
head/sys/mips/nlm/hal/interlaken.h (contents, props changed)
head/sys/mips/nlm/hal/mdio.h (contents, props changed)
head/sys/mips/nlm/hal/nae.h (contents, props changed)
head/sys/mips/nlm/hal/poe.h (contents, props changed)
head/sys/mips/nlm/hal/sgmii.h (contents, props changed)
head/sys/mips/nlm/hal/ucore_loader.h (contents, props changed)
head/sys/mips/nlm/hal/xaui.h (contents, props changed)
Modified:
head/sys/mips/conf/std.XLP
head/sys/mips/nlm/board.c
head/sys/mips/nlm/board.h
head/sys/mips/nlm/files.xlp
head/sys/mips/nlm/hal/iomap.h
head/sys/mips/nlm/msgring.h
Modified: head/sys/mips/conf/std.XLP
==
--- head/sys/mips/conf/std.XLP Tue Mar 27 14:02:22 2012(r233544)
+++ head/sys/mips/conf/std.XLP Tue Mar 27 14:05:12 2012(r233545)
@@ -71,6 +71,7 @@ devicebpf
# Network
device miibus
device ether
+device xlpge
#devicere
device msk
device em
Modified: head/sys/mips/nlm/board.c
==
--- head/sys/mips/nlm/board.c Tue Mar 27 14:02:22 2012(r233544)
+++ head/sys/mips/nlm/board.c Tue Mar 27 14:05:12 2012(r233545)
@@ -44,16 +44,289 @@ __FBSDID($FreeBSD$);
#include mips/nlm/hal/fmn.h
#include mips/nlm/hal/pic.h
#include mips/nlm/hal/sys.h
+#include mips/nlm/hal/nae.h
#include mips/nlm/hal/uart.h
+#include mips/nlm/hal/poe.h
#include mips/nlm/xlp.h
#include mips/nlm/board.h
+#include mips/nlm/msgring.h
static uint8_t board_eeprom_buf[EEPROM_SIZE];
static int board_eeprom_set;
struct xlp_board_info xlp_board_info;
+struct vfbid_tbl {
+ int vfbid;
+ int dest_vc;
+};
+
+/* XXXJC : this should be derived from msg thread mask */
+static struct vfbid_tbl nlm_vfbid[] = {
+ /* NULL FBID should map to cpu0 to detect NAE send msg errors */
+ {127, 0}, /* NAE - NAE mappings */
+ {51, 1019}, {50, 1018}, {49, 1017}, {48, 1016},
+ {47, 1015}, {46, 1014}, {45, 1013}, {44, 1012},
+ {43, 1011}, {42, 1010}, {41, 1009}, {40, 1008},
+ {39, 1007}, {38, 1006}, {37, 1005}, {36, 1004},
+ {35, 1003}, {34, 1002}, {33, 1001}, {32, 1000},
+ /* NAE - CPU mappings, freeback got to vc 3 of each thread */
+ {31, 127}, {30, 123}, {29, 119}, {28, 115},
+ {27, 111}, {26, 107}, {25, 103}, {24, 99},
+ {23, 95}, {22, 91}, {21, 87}, {20, 83},
+ {19, 79}, {18, 75}, {17, 71}, {16, 67},
+ {15, 63}, {14, 59}, {13, 55}, {12, 51},
+ {11, 47}, {10, 43}, { 9, 39}, { 8, 35},
+ { 7, 31}, { 6, 27}, { 5, 23}, { 4, 19},
+ { 3, 15}, { 2, 11}, { 1,7}, { 0,3},
+};
+
+static struct vfbid_tbl nlm3xx_vfbid[] = {
+ /* NULL FBID should map to cpu0 to detect NAE send msg errors */
+ {127, 0}, /* NAE - NAE mappings */
+ {39, 503}, {38, 502}, {37, 501}, {36, 500},
+ {35, 499}, {34, 498}, {33, 497}, {32, 496},
+ /* NAE - CPU mappings, freeback got to vc 3 of each thread */
+ {31, 127}, {30, 123}, {29, 119}, {28, 115},
+ {27, 111}, {26, 107}, {25, 103}, {24, 99},
+ {23, 95}, {22, 91}, {21, 87}, {20, 83},
+ {19, 79}, {18, 75}, {17, 71}, {16, 67},
+ {15, 63}, {14, 59}, {13, 55}, {12, 51},
+ {11, 47}, {10, 43}, { 9, 39}, { 8, 35},
+ { 7, 31}, { 6, 27}, { 5, 23}, { 4, 19},
+ { 3, 15}, { 2, 11}, { 1,7}, { 0,3},
svn commit: r233549 - in head/sys/mips/nlm: . dev
Author: jchandra
Date: Tue Mar 27 14:48:40 2012
New Revision: 233549
URL: http://svn.freebsd.org/changeset/base/233549
Log:
XLP UART code udpate.
Move XLP PCI UART device to sys/mips/nlm/dev/ directory. Other
drivers for the XLP SoC devices will be added here as well.
Update uart_cpu_xlp.c and uart_pci_xlp.c use macros for uart port,
speed and IO frequency.
Added:
head/sys/mips/nlm/dev/uart_pci_xlp.c
- copied, changed from r233508, head/sys/mips/nlm/uart_pci_xlp.c
Deleted:
head/sys/mips/nlm/uart_pci_xlp.c
Modified:
head/sys/mips/nlm/board.h
head/sys/mips/nlm/files.xlp
head/sys/mips/nlm/uart_cpu_xlp.c
Modified: head/sys/mips/nlm/board.h
==
--- head/sys/mips/nlm/board.h Tue Mar 27 14:24:46 2012(r233548)
+++ head/sys/mips/nlm/board.h Tue Mar 27 14:48:40 2012(r233549)
@@ -43,6 +43,10 @@
#defineEEPROM_SIZE 48
#defineEEPROM_MACADDR_OFFSET 2
+/* used if there is no FDT */
+#defineBOARD_CONSOLE_SPEED 115200
+#defineBOARD_CONSOLE_UART 0
+
/*
* EVP board CPLD chip select and daughter card info field
*/
Copied and modified: head/sys/mips/nlm/dev/uart_pci_xlp.c (from r233508,
head/sys/mips/nlm/uart_pci_xlp.c)
==
--- head/sys/mips/nlm/uart_pci_xlp.cMon Mar 26 13:02:31 2012
(r233508, copy source)
+++ head/sys/mips/nlm/dev/uart_pci_xlp.cTue Mar 27 14:48:40 2012
(r233549)
@@ -1,30 +1,29 @@
/*-
- * Copyright (c) 2011 Netlogic Microsystems Inc.
- *
- * (based on dev/uart/uart_bus_pci.c)
- * Copyright (c) 2006 Marcel Moolenaar
- * Copyright (c) 2001 M. Warner Losh
- * All rights reserved.
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
+ *
* 1. Redistributions of source code must retain the above copyright
*notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
- *notice, this list of conditions and the following disclaimer in the
- *documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *notice, this list of conditions and the following disclaimer in
+ *the documentation and/or other materials provided with the
+ *distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include sys/cdefs.h
@@ -56,7 +55,8 @@ static device_method_t uart_soc_methods[
DEVMETHOD(device_probe, uart_soc_probe),
DEVMETHOD(device_attach,uart_bus_attach),
DEVMETHOD(device_detach,uart_bus_detach),
- { 0, 0 }
+
+ DEVMETHOD_END
};
static driver_t uart_soc_driver = {
@@ -77,7 +77,7 @@ uart_soc_probe(device_t dev)
sc = device_get_softc(dev);
sc-sc_class = uart_ns8250_class;
device_set_desc(dev, Netlogic SoC UART);
- return (uart_bus_probe(dev, 2, 13300, 0, 0));
+ return (uart_bus_probe(dev, 2, XLP_IO_CLK, 0, 0));
}
DRIVER_MODULE(uart_soc, pci, uart_soc_driver, uart_devclass, 0, 0);
Modified: head/sys/mips/nlm/files.xlp
==
--- head/sys/mips/nlm/files.xlp Tue Mar 27 14:24:46 2012(r233548)
+++ head/sys/mips/nlm/files.xlp
svn commit: r233553 - head/sys/dev/cfi
Author: jchandra
Date: Tue Mar 27 15:13:12 2012
New Revision: 233553
URL: http://svn.freebsd.org/changeset/base/233553
Log:
CFI fixes for big endian archs.
The flash commands and responses are little-endian and have to be
byte swapped on big-endian systems. However the raw read of data
need not be swapped.
Make the cfi_read and cfi_write do the swapping, and provide a
cfi_read_raw which does not byte swap for reading data from
flash.
Modified:
head/sys/dev/cfi/cfi_core.c
head/sys/dev/cfi/cfi_dev.c
head/sys/dev/cfi/cfi_disk.c
head/sys/dev/cfi/cfi_var.h
Modified: head/sys/dev/cfi/cfi_core.c
==
--- head/sys/dev/cfi/cfi_core.c Tue Mar 27 15:07:43 2012(r233552)
+++ head/sys/dev/cfi/cfi_core.c Tue Mar 27 15:13:12 2012(r233553)
@@ -36,6 +36,7 @@ __FBSDID($FreeBSD$);
#include sys/systm.h
#include sys/bus.h
#include sys/conf.h
+#include sys/endian.h
#include sys/kernel.h
#include sys/malloc.h
#include sys/module.h
@@ -54,7 +55,7 @@ devclass_t cfi_devclass;
devclass_t cfi_diskclass;
uint32_t
-cfi_read(struct cfi_softc *sc, u_int ofs)
+cfi_read_raw(struct cfi_softc *sc, u_int ofs)
{
uint32_t val;
@@ -76,6 +77,32 @@ cfi_read(struct cfi_softc *sc, u_int ofs
return (val);
}
+uint32_t
+cfi_read(struct cfi_softc *sc, u_int ofs)
+{
+ uint32_t val;
+ uint16_t sval;
+
+ ofs = ~(sc-sc_width - 1);
+ switch (sc-sc_width) {
+ case 1:
+ val = bus_space_read_1(sc-sc_tag, sc-sc_handle, ofs);
+ break;
+ case 2:
+ sval = bus_space_read_2(sc-sc_tag, sc-sc_handle, ofs);
+ val = le16toh(sval);
+ break;
+ case 4:
+ val = bus_space_read_4(sc-sc_tag, sc-sc_handle, ofs);
+ val = le32toh(val);
+ break;
+ default:
+ val = ~0;
+ break;
+ }
+ return (val);
+}
+
static void
cfi_write(struct cfi_softc *sc, u_int ofs, u_int val)
{
@@ -86,10 +113,10 @@ cfi_write(struct cfi_softc *sc, u_int of
bus_space_write_1(sc-sc_tag, sc-sc_handle, ofs, val);
break;
case 2:
- bus_space_write_2(sc-sc_tag, sc-sc_handle, ofs, val);
+ bus_space_write_2(sc-sc_tag, sc-sc_handle, ofs, htole16(val));
break;
case 4:
- bus_space_write_4(sc-sc_tag, sc-sc_handle, ofs, val);
+ bus_space_write_4(sc-sc_tag, sc-sc_handle, ofs, htole32(val));
break;
}
}
Modified: head/sys/dev/cfi/cfi_dev.c
==
--- head/sys/dev/cfi/cfi_dev.c Tue Mar 27 15:07:43 2012(r233552)
+++ head/sys/dev/cfi/cfi_dev.c Tue Mar 27 15:13:12 2012(r233553)
@@ -103,7 +103,7 @@ cfi_block_start(struct cfi_softc *sc, u_
/* Read the block from flash for byte-serving. */
ptr.x8 = sc-sc_wrbuf;
for (r = 0; r sc-sc_wrbufsz; r += sc-sc_width) {
- val = cfi_read(sc, sc-sc_wrofs + r);
+ val = cfi_read_raw(sc, sc-sc_wrofs + r);
switch (sc-sc_width) {
case 1:
*(ptr.x8)++ = val;
@@ -189,7 +189,7 @@ cfi_devread(struct cdev *dev, struct uio
while (error == 0 uio-uio_resid 0
uio-uio_offset sc-sc_size) {
ofs = uio-uio_offset;
- val = cfi_read(sc, ofs);
+ val = cfi_read_raw(sc, ofs);
switch (sc-sc_width) {
case 1:
buf.x8[0] = val;
Modified: head/sys/dev/cfi/cfi_disk.c
==
--- head/sys/dev/cfi/cfi_disk.c Tue Mar 27 15:07:43 2012(r233552)
+++ head/sys/dev/cfi/cfi_disk.c Tue Mar 27 15:13:12 2012(r233553)
@@ -182,19 +182,19 @@ cfi_disk_read(struct cfi_softc *sc, stru
if (sc-sc_width == 1) {
uint8_t *dp = (uint8_t *)bp-bio_data;
while (resid 0 bp-bio_offset sc-sc_size) {
- *dp++ = cfi_read(sc, bp-bio_offset);
+ *dp++ = cfi_read_raw(sc, bp-bio_offset);
bp-bio_offset += 1, resid -= 1;
}
} else if (sc-sc_width == 2) {
uint16_t *dp = (uint16_t *)bp-bio_data;
while (resid 0 bp-bio_offset sc-sc_size) {
- *dp++ = cfi_read(sc, bp-bio_offset);
+ *dp++ = cfi_read_raw(sc, bp-bio_offset);
bp-bio_offset += 2, resid -= 2;
}
} else {
uint32_t *dp = (uint32_t *)bp-bio_data;
while (resid 0 bp-bio_offset sc-sc_size) {
- *dp++ = cfi_read(sc, bp-bio_offset);
+ *dp++ = cfi_read_raw(sc, bp-bio_offset);
svn commit: r233556 - in head/sys/mips: conf nlm nlm/dev
Author: jchandra
Date: Tue Mar 27 15:16:38 2012
New Revision: 233556
URL: http://svn.freebsd.org/changeset/base/233556
Log:
NOR flash driver for XLP.
The NOR interface on the SoC appears on the top level PCI bus. Add
a simple driver for this.
Added:
head/sys/mips/nlm/dev/cfi_pci_xlp.c (contents, props changed)
Modified:
head/sys/mips/conf/std.XLP
head/sys/mips/nlm/files.xlp
head/sys/mips/nlm/xlp_pci.c
Modified: head/sys/mips/conf/std.XLP
==
--- head/sys/mips/conf/std.XLP Tue Mar 27 15:15:30 2012(r233555)
+++ head/sys/mips/conf/std.XLP Tue Mar 27 15:16:38 2012(r233556)
@@ -106,3 +106,7 @@ device nlmrsa
# Options that use crypto
optionsIPSEC
optionsGEOM_ELI
+
+# NOR
+device cfi
+device cfid
Added: head/sys/mips/nlm/dev/cfi_pci_xlp.c
==
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/mips/nlm/dev/cfi_pci_xlp.c Tue Mar 27 15:16:38 2012
(r233556)
@@ -0,0 +1,77 @@
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in
+ *the documentation and/or other materials provided with the
+ *distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include sys/cdefs.h
+__FBSDID($FreeBSD$);
+
+#include sys/param.h
+#include sys/systm.h
+#include sys/bus.h
+#include sys/conf.h
+#include sys/kernel.h
+#include sys/module.h
+#include machine/bus.h
+#include sys/rman.h
+#include machine/resource.h
+
+#include dev/pci/pcivar.h
+
+#include dev/cfi/cfi_var.h
+
+#include mips/nlm/hal/haldefs.h
+#include mips/nlm/hal/iomap.h
+
+static int cfi_xlp_probe(device_t dev);
+
+static device_method_t cfi_xlp_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, cfi_xlp_probe),
+ DEVMETHOD(device_attach,cfi_attach),
+ DEVMETHOD(device_detach,cfi_detach),
+ DEVMETHOD_END
+};
+
+static driver_t cfi_xlp_driver = {
+ cfi_driver_name,
+ cfi_xlp_methods,
+ sizeof(struct cfi_softc),
+};
+
+static int
+cfi_xlp_probe(device_t dev)
+{
+
+ if (pci_get_vendor(dev) != PCI_VENDOR_NETLOGIC ||
+ pci_get_device(dev) != PCI_DEVICE_ID_NLM_NOR)
+ return (ENXIO);
+
+ device_set_desc(dev, Netlogic XLP NOR Bus);
+ return (cfi_probe(dev));
+}
+
+DRIVER_MODULE(cfi_xlp, pci, cfi_xlp_driver, cfi_devclass, 0, 0);
Modified: head/sys/mips/nlm/files.xlp
==
--- head/sys/mips/nlm/files.xlp Tue Mar 27 15:15:30 2012(r233555)
+++ head/sys/mips/nlm/files.xlp Tue Mar 27 15:16:38 2012(r233556)
@@ -18,6 +18,7 @@ mips/nlm/usb_init.c optional usb
#
# Simple SoC devices
mips/nlm/dev/uart_pci_xlp.coptional uart
+mips/nlm/dev/cfi_pci_xlp.c optional cfi
#
# Network driver and micro-core code
mips/nlm/dev/net/nae.c optional xlpge
Modified: head/sys/mips/nlm/xlp_pci.c
==
--- head/sys/mips/nlm/xlp_pci.c Tue Mar 27 15:15:30 2012(r233555)
+++ head/sys/mips/nlm/xlp_pci.c Tue Mar 27 15:16:38 2012(r233556)
@@ -62,6 +62,7 @@ __FBSDID($FreeBSD$);
#include mips/nlm/hal/mips-extns.h
#include mips/nlm/hal/pic.h
#include mips/nlm/hal/bridge.h
+#include mips/nlm/hal/gbu.h
#include mips/nlm/hal/pcibus.h
#include mips/nlm/hal/uart.h
#include mips/nlm/xlp.h
@@ -479,6 +480,7 @@ assign_soc_resource(device_t child, int
u_long *countp, struct rman **rm, bus_space_tag_t *bst, vm_offset_t *va)
{
int devid, inst, node, unit;
+
svn commit: r233563 - in head/sys/mips/nlm: . hal
Author: jchandra
Date: Tue Mar 27 15:39:55 2012
New Revision: 233563
URL: http://svn.freebsd.org/changeset/base/233563
Log:
Update memory and resource allocation code for SoC devices
The XLP on-chip devices have PCI configuration headers, but some of the
devices need custom resource allocation code.
- devices with no MEM/IO BARs with registers in PCIe extended reg
space have to be handled in memory resource allocation
- devices without INTPIN/INTLINE in PCI header can be supported
by having these faked with a shadow register.
- Some devices does not allow 8/16 bit access to the register space,
he default bus space cannot be used for these.
Subclass pci and override attach and resource allocation methods to
take care of this.
Remove earlier code which did this partially.
Deleted:
head/sys/mips/nlm/intern_dev.c
Modified:
head/sys/mips/nlm/files.xlp
head/sys/mips/nlm/hal/nlm_hal.c
head/sys/mips/nlm/hal/pcibus.h
head/sys/mips/nlm/hal/pic.h
head/sys/mips/nlm/intr_machdep.c
head/sys/mips/nlm/xlp.h
head/sys/mips/nlm/xlp_machdep.c
head/sys/mips/nlm/xlp_pci.c
Modified: head/sys/mips/nlm/files.xlp
==
--- head/sys/mips/nlm/files.xlp Tue Mar 27 15:33:38 2012(r233562)
+++ head/sys/mips/nlm/files.xlp Tue Mar 27 15:39:55 2012(r233563)
@@ -12,7 +12,6 @@ mips/nlm/mpreset.Sstandard
mips/nlm/board_eeprom.cstandard
mips/nlm/board_cpld.c standard
mips/nlm/xlp_pci.c optional pci
-mips/nlm/intern_dev.c optional pci
mips/nlm/uart_cpu_xlp.coptional uart
mips/nlm/usb_init.coptional usb
#
Modified: head/sys/mips/nlm/hal/nlm_hal.c
==
--- head/sys/mips/nlm/hal/nlm_hal.c Tue Mar 27 15:33:38 2012
(r233562)
+++ head/sys/mips/nlm/hal/nlm_hal.c Tue Mar 27 15:39:55 2012
(r233563)
@@ -37,23 +37,8 @@ __FBSDID($FreeBSD$);
#include mips/nlm/hal/haldefs.h
#include mips/nlm/hal/iomap.h
#include mips/nlm/hal/sys.h
-#include mips/nlm/hal/pic.h
#include mips/nlm/xlp.h
-#include mips/nlm/hal/uart.h
-#include mips/nlm/hal/mmu.h
-#include mips/nlm/hal/pcibus.h
-#include mips/nlm/hal/usb.h
-
-int pic_irt_ehci0;
-int pic_irt_ehci1;
-int pic_irt_uart0;
-int pic_irt_uart1;
-int pic_irt_pcie_lnk0;
-int pic_irt_pcie_lnk1;
-int pic_irt_pcie_lnk2;
-int pic_irt_pcie_lnk3;
-
uint32_t
xlp_get_cpu_frequency(int node, int core)
{
@@ -66,9 +51,9 @@ xlp_get_cpu_frequency(int node, int core
pll_divf = ((rstval 10) 0x7f) + 1;
pll_divr = ((rstval 8) 0x3) + 1;
if (!nlm_is_xlp8xx_ax())
- ext_div = ((rstval 30) 0x3) + 1;
+ ext_div = ((rstval 30) 0x3) + 1;
else
- ext_div = 1;
+ ext_div = 1;
dfs_div = ((dfsval (core 2)) 0xf) + 1;
return ((8ULL * pll_divf)/(3 * pll_divr * ext_div * dfs_div));
@@ -122,98 +107,3 @@ nlm_set_device_frequency(int node, int d
}
return (nlm_get_device_frequency(sysbase, devtype));
}
-
-void
-nlm_pic_irt_init(int node)
-{
- pic_irt_ehci0 = nlm_irtstart(nlm_get_usb_pcibase(node, 0));
- pic_irt_ehci1 = nlm_irtstart(nlm_get_usb_pcibase(node, 3));
- pic_irt_uart0 = nlm_irtstart(nlm_get_uart_pcibase(node, 0));
- pic_irt_uart1 = nlm_irtstart(nlm_get_uart_pcibase(node, 1));
-
- /* Hardcoding the PCIE IRT information as PIC doesn't
- understand any value other than 78,79,80,81 for PCIE0/1/2/3 */
- pic_irt_pcie_lnk0 = 78;
- pic_irt_pcie_lnk1 = 79;
- pic_irt_pcie_lnk2 = 80;
- pic_irt_pcie_lnk3 = 81;
-}
-/*
- * Find the IRQ for the link, each link has a different interrupt
- * at the XLP pic
- */
-int xlp_pcie_link_irt(int link)
-{
-
- if( (link 0) || (link 3))
- return (-1);
-
- return (pic_irt_pcie_lnk0 + link);
-}
-
-int
-xlp_irt_to_irq(int irt)
-{
- if (irt == pic_irt_ehci0)
- return PIC_EHCI_0_IRQ;
- else if (irt == pic_irt_ehci1)
- return PIC_EHCI_1_IRQ;
- else if (irt == pic_irt_uart0)
- return PIC_UART_0_IRQ;
- else if (irt == pic_irt_uart1)
- return PIC_UART_1_IRQ;
- else if (irt == pic_irt_pcie_lnk0)
- return PIC_PCIE_0_IRQ;
- else if (irt == pic_irt_pcie_lnk1)
- return PIC_PCIE_1_IRQ;
- else if (irt == pic_irt_pcie_lnk2)
- return PIC_PCIE_2_IRQ;
- else if (irt == pic_irt_pcie_lnk3)
- return PIC_PCIE_3_IRQ;
- else {
- if (bootverbose)
- printf(Cannot find irq for IRT %d\n, irt);
- return 0;
-}
-}
-
-int
-xlp_irq_to_irt(int irq)
-{
-
svn commit: r233564 - in head/sys/mips: conf nlm
Author: jchandra
Date: Tue Mar 27 15:43:32 2012
New Revision: 233564
URL: http://svn.freebsd.org/changeset/base/233564
Log:
Resource allocation for XLP SoC SDHCI slots
The on-chip SD slots do not have PCI BARs corresponding to them, so
this has to be handled in the custom SoC memory allocation.
Provide memory resource for rids corresponding to BAR 0 and 1 in
the custom allocation code.
Modified:
head/sys/mips/conf/std.XLP
head/sys/mips/nlm/xlp_pci.c
Modified: head/sys/mips/conf/std.XLP
==
--- head/sys/mips/conf/std.XLP Tue Mar 27 15:39:55 2012(r233563)
+++ head/sys/mips/conf/std.XLP Tue Mar 27 15:43:32 2012(r233564)
@@ -110,3 +110,8 @@ options GEOM_ELI
# NOR
device cfi
device cfid
+
+# MMC/SD
+device mmc # MMC/SD bus
+device mmcsd # MMC/SD memory card
+device sdhci # Generic PCI SD Host Controller
Modified: head/sys/mips/nlm/xlp_pci.c
==
--- head/sys/mips/nlm/xlp_pci.c Tue Mar 27 15:39:55 2012(r233563)
+++ head/sys/mips/nlm/xlp_pci.c Tue Mar 27 15:43:32 2012(r233564)
@@ -165,8 +165,22 @@ xlp_pci_alloc_resource(device_t bus, dev
/* no emulation for IO ports */
if (type == SYS_RES_IOPORT)
return (NULL);
+
start = xlp_devinfo-mem_res_start;
count = XLP_PCIE_CFG_SIZE - XLP_IO_PCI_HDRSZ;
+
+ /* MMC needs to 2 slots with rids 16 and 20 and a
+* fixup for size */
+ if (pci_get_device(child) == PCI_DEVICE_ID_NLM_MMC) {
+ count = 0x100;
+ if (*rid == 16)
+ ; /* first slot already setup */
+ else if (*rid == 20)
+ start += 0x100; /* second slot */
+ else
+ return (NULL);
+ }
+
end = start + count - 1;
r = BUS_ALLOC_RESOURCE(device_get_parent(bus), child,
type, rid, start, end, count, flags);
@@ -254,6 +268,8 @@ xlp_add_soc_child(device_t pcib, device_
xlp_dinfo = (struct xlp_devinfo *)dinfo;
xlp_dinfo-irq = irq;
xlp_dinfo-flags = flags;
+
+ /* memory resource from ecfg space, if MEM_RES_EMUL is set */
if ((flags MEM_RES_EMUL) != 0)
xlp_dinfo-mem_res_start = XLP_DEFAULT_IO_BASE + devoffset +
XLP_IO_PCI_HDRSZ;
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svn commit: r233570 - head/sys/mips/nlm
Author: jchandra Date: Tue Mar 27 18:26:35 2012 New Revision: 233570 URL: http://svn.freebsd.org/changeset/base/233570 Log: Fix size of PCI softc. Modified: head/sys/mips/nlm/xlp_pci.c Modified: head/sys/mips/nlm/xlp_pci.c == --- head/sys/mips/nlm/xlp_pci.c Tue Mar 27 18:22:14 2012(r233569) +++ head/sys/mips/nlm/xlp_pci.c Tue Mar 27 18:26:35 2012(r233570) @@ -331,7 +331,8 @@ static device_method_t xlp_pci_methods[] DEVMETHOD_END }; -DEFINE_CLASS_1(pci, xlp_pci_driver, xlp_pci_methods, 0, pci_driver); +DEFINE_CLASS_1(pci, xlp_pci_driver, xlp_pci_methods, sizeof(struct pci_softc), +pci_driver); DRIVER_MODULE(xlp_pci, pcib, xlp_pci_driver, pci_devclass, 0, 0); static devclass_t pcib_devclass; ___ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to svn-src-all-unsubscr...@freebsd.org
Re: svn commit: r233570 - head/sys/mips/nlm
On Wed, Mar 28, 2012 at 2:51 AM, John Baldwin j...@freebsd.org wrote: On Tuesday, March 27, 2012 2:26:35 pm Jayachandran C. wrote: Author: jchandra Date: Tue Mar 27 18:26:35 2012 New Revision: 233570 URL: http://svn.freebsd.org/changeset/base/233570 Log: Fix size of PCI softc. Modified: head/sys/mips/nlm/xlp_pci.c Modified: head/sys/mips/nlm/xlp_pci.c == --- head/sys/mips/nlm/xlp_pci.c Tue Mar 27 18:22:14 2012 (r233569) +++ head/sys/mips/nlm/xlp_pci.c Tue Mar 27 18:26:35 2012 (r233570) @@ -331,7 +331,8 @@ static device_method_t xlp_pci_methods[] DEVMETHOD_END }; -DEFINE_CLASS_1(pci, xlp_pci_driver, xlp_pci_methods, 0, pci_driver); +DEFINE_CLASS_1(pci, xlp_pci_driver, xlp_pci_methods, sizeof(struct pci_softc), + pci_driver); DRIVER_MODULE(xlp_pci, pcib, xlp_pci_driver, pci_devclass, 0, 0); static devclass_t pcib_devclass; Oops, not sure how I missed this one earlier. :( It is completely my fault :) I did not notice the PCI dma tag change when I moved this code from my user branch to HEAD today. JC. ___ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to svn-src-all-unsubscr...@freebsd.org
svn commit: r233308 - head/sys/mips/mips
Author: jchandra
Date: Thu Mar 22 15:14:10 2012
New Revision: 233308
URL: http://svn.freebsd.org/changeset/base/233308
Log:
Fix return type of mips pmap_kextract()
The return type should be vm_paddr_t, not vm_offset_t.
Modified:
head/sys/mips/mips/pmap.c
Modified: head/sys/mips/mips/pmap.c
==
--- head/sys/mips/mips/pmap.c Thu Mar 22 14:20:51 2012(r233307)
+++ head/sys/mips/mips/pmap.c Thu Mar 22 15:14:10 2012(r233308)
@@ -3209,7 +3209,7 @@ pmap_emulate_modified(pmap_t pmap, vm_of
* Extract the physical page address associated
* virtual address.
*/
- /* PMAP_INLINE */ vm_offset_t
+vm_paddr_t
pmap_kextract(vm_offset_t va)
{
int mapped;
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svn commit: r228271 - head/sys/mips/nlm/hal
Author: jchandra Date: Mon Dec 5 02:56:08 2011 New Revision: 228271 URL: http://svn.freebsd.org/changeset/base/228271 Log: Fix XLP compilation. Add definitions of LSU_DEBUG_ADDR and LSU_DEBUG_DATA0, the code that uses it was added in r227799 Reported by: gonzo Modified: head/sys/mips/nlm/hal/cpucontrol.h Modified: head/sys/mips/nlm/hal/cpucontrol.h == --- head/sys/mips/nlm/hal/cpucontrol.h Mon Dec 5 00:12:10 2011 (r228270) +++ head/sys/mips/nlm/hal/cpucontrol.h Mon Dec 5 02:56:08 2011 (r228271) @@ -44,6 +44,8 @@ #defineCPU_BLOCKID_MAP 10 #defineLSU_DEFEATURE 0x304 +#defineLSU_DEBUG_ADDR 0x305 +#defineLSU_DEBUG_DATA0 0x306 #defineLSU_CERRLOG_REGID 0x09 #defineSCHED_DEFEATURE 0x700 ___ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to svn-src-all-unsubscr...@freebsd.org
svn commit: r228272 - head/sys/mips/nlm
Author: jchandra Date: Mon Dec 5 03:10:01 2011 New Revision: 228272 URL: http://svn.freebsd.org/changeset/base/228272 Log: Fix N32 compilation again for XLP. Disable DDB/KDB related options for N32, and add back a cast that was lost during the last set of updates. Reported by: gonzo, bz Modified: head/sys/mips/nlm/xlp_machdep.c Modified: head/sys/mips/nlm/xlp_machdep.c == --- head/sys/mips/nlm/xlp_machdep.c Mon Dec 5 02:56:08 2011 (r228271) +++ head/sys/mips/nlm/xlp_machdep.c Mon Dec 5 03:10:01 2011 (r228272) @@ -278,7 +278,7 @@ xlp_bootargs_init(__register_t arg) phandle_t chosen; ihandle_t mask; - dtbp = (void *)arg; + dtbp = (void *)(intptr_t)arg; #if defined(FDT_DTB_STATIC) /* * In case the device tree blob was not passed as argument try ___ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to svn-src-all-unsubscr...@freebsd.org
