Author: raj
Date: Sun May 27 10:25:20 2012
New Revision: 236141
URL: http://svn.freebsd.org/changeset/base/236141
Log:
Let us manage differences of Book-E PowerPC variations i.e. vendor /
implementation specific vs. the common architecture definition.
Bring PPC4XX defines (PSL, SPR, TLB). Note the new definitions under
BOOKE_PPC4XX are not used in the code yet.
This change set is not supposed to affect existing E500 support, it's just
another reorg step before bringing support for E500mc, E5500 and PPC465.
Obtained from: AppliedMicro, Freescale, Semihalf
Modified:
head/sys/conf/files.powerpc
head/sys/conf/options.powerpc
head/sys/kern/sched_ule.c
head/sys/powerpc/booke/locore.S
head/sys/powerpc/booke/machdep.c
head/sys/powerpc/conf/MPC85XX
head/sys/powerpc/conf/NOTES
head/sys/powerpc/include/pcpu.h
head/sys/powerpc/include/profile.h
head/sys/powerpc/include/psl.h
head/sys/powerpc/include/pte.h
head/sys/powerpc/include/spr.h
head/sys/powerpc/include/tlb.h
head/sys/powerpc/include/trap.h
head/sys/powerpc/include/vmparam.h
head/sys/powerpc/powerpc/cpu.c
head/sys/powerpc/powerpc/db_trace.c
head/sys/powerpc/powerpc/gdb_machdep.c
head/sys/powerpc/powerpc/genassym.c
Modified: head/sys/conf/files.powerpc
==============================================================================
--- head/sys/conf/files.powerpc Sun May 27 09:34:47 2012 (r236140)
+++ head/sys/conf/files.powerpc Sun May 27 10:25:20 2012 (r236141)
@@ -97,17 +97,17 @@ powerpc/aim/swtch64.S optional aim powe
powerpc/aim/trap.c optional aim
powerpc/aim/uma_machdep.c optional aim
powerpc/aim/vm_machdep.c optional aim
-powerpc/booke/clock.c optional e500
-powerpc/booke/copyinout.c optional e500
-powerpc/booke/interrupt.c optional e500
-powerpc/booke/locore.S optional e500 no-obj
-powerpc/booke/machdep.c optional e500
-powerpc/booke/mp_cpudep.c optional e500 smp
+powerpc/booke/clock.c optional booke
+powerpc/booke/copyinout.c optional booke
+powerpc/booke/interrupt.c optional booke
+powerpc/booke/locore.S optional booke no-obj
+powerpc/booke/machdep.c optional booke
+powerpc/booke/mp_cpudep.c optional booke smp
powerpc/booke/platform_bare.c optional mpc85xx
-powerpc/booke/pmap.c optional e500
-powerpc/booke/swtch.S optional e500
-powerpc/booke/trap.c optional e500
-powerpc/booke/vm_machdep.c optional e500
+powerpc/booke/pmap.c optional booke
+powerpc/booke/swtch.S optional booke
+powerpc/booke/trap.c optional booke
+powerpc/booke/vm_machdep.c optional booke
powerpc/cpufreq/dfs.c optional cpufreq
powerpc/cpufreq/pcr.c optional cpufreq aim
powerpc/fpu/fpu_add.c optional fpu_emu powerpc
Modified: head/sys/conf/options.powerpc
==============================================================================
--- head/sys/conf/options.powerpc Sun May 27 09:34:47 2012
(r236140)
+++ head/sys/conf/options.powerpc Sun May 27 10:25:20 2012
(r236141)
@@ -2,7 +2,9 @@
# Options specific to the powerpc platform kernels
AIM opt_global.h
-E500 opt_global.h
+BOOKE opt_global.h
+BOOKE_E500 opt_global.h
+BOOKE_PPC4XX opt_global.h
CELL
POWERPC
Modified: head/sys/kern/sched_ule.c
==============================================================================
--- head/sys/kern/sched_ule.c Sun May 27 09:34:47 2012 (r236140)
+++ head/sys/kern/sched_ule.c Sun May 27 10:25:20 2012 (r236141)
@@ -77,7 +77,7 @@ dtrace_vtime_switch_func_t dtrace_vtime_
#include <machine/cpu.h>
#include <machine/smp.h>
-#if defined(__powerpc__) && defined(E500)
+#if defined(__powerpc__) && defined(BOOKE_E500)
#error "This architecture is not currently compatible with ULE"
#endif
Modified: head/sys/powerpc/booke/locore.S
==============================================================================
--- head/sys/powerpc/booke/locore.S Sun May 27 09:34:47 2012
(r236140)
+++ head/sys/powerpc/booke/locore.S Sun May 27 10:25:20 2012
(r236141)
@@ -218,7 +218,7 @@ done_mapping:
mr %r3, %r30
mr %r4, %r31
- /* Prepare e500 core */
+ /* Prepare core */
bl booke_init
/* Switch to thread0.td_kstack now */
Modified: head/sys/powerpc/booke/machdep.c
==============================================================================
--- head/sys/powerpc/booke/machdep.c Sun May 27 09:34:47 2012
(r236140)
+++ head/sys/powerpc/booke/machdep.c Sun May 27 10:25:20 2012
(r236141)
@@ -392,6 +392,7 @@ booke_init(uint32_t arg1, uint32_t arg2)
debugf(" boothowto = 0x%08x\n", boothowto);
debugf(" kernel ccsrbar = 0x%08x\n", CCSRBAR_VA);
debugf(" MSR = 0x%08x\n", mfmsr());
+#if defined(BOOKE_E500)
debugf(" HID0 = 0x%08x\n", mfspr(SPR_HID0));
debugf(" HID1 = 0x%08x\n", mfspr(SPR_HID1));
debugf(" BUCSR = 0x%08x\n", mfspr(SPR_BUCSR));
@@ -399,13 +400,16 @@ booke_init(uint32_t arg1, uint32_t arg2)
__asm __volatile("msync; isync");
csr = ccsr_read4(OCP85XX_L2CTL);
debugf(" L2CTL = 0x%08x\n", csr);
+#endif
debugf(" dtbp = 0x%08x\n", (uint32_t)dtbp);
print_kernel_section_addr();
print_kenv();
+#if defined(BOOKE_E500)
//tlb1_print_entries();
//tlb1_print_tlbentries();
+#endif
kdb_init();
@@ -421,8 +425,10 @@ booke_init(uint32_t arg1, uint32_t arg2)
pmap_mmu_install(MMU_TYPE_BOOKE, 0);
pmap_bootstrap((uintptr_t)kernel_text, end);
debugf("MSR = 0x%08x\n", mfmsr());
+#if defined(BOOKE_E500)
//tlb1_print_entries();
//tlb1_print_tlbentries();
+#endif
/* Initialize params/tunables that are derived from memsize. */
init_param2(physmem);
Modified: head/sys/powerpc/conf/MPC85XX
==============================================================================
--- head/sys/powerpc/conf/MPC85XX Sun May 27 09:34:47 2012
(r236140)
+++ head/sys/powerpc/conf/MPC85XX Sun May 27 10:25:20 2012
(r236141)
@@ -4,7 +4,8 @@
# $FreeBSD$
#
-cpu E500
+cpu BOOKE
+cpu BOOKE_E500
ident MPC85XX
machine powerpc powerpc
Modified: head/sys/powerpc/conf/NOTES
==============================================================================
--- head/sys/powerpc/conf/NOTES Sun May 27 09:34:47 2012 (r236140)
+++ head/sys/powerpc/conf/NOTES Sun May 27 10:25:20 2012 (r236141)
@@ -14,7 +14,8 @@
#
# You must specify at least one CPU (the one you intend to run on).
cpu AIM
-#cpu E500
+#cpu BOOKE_E500
+#cpu BOOKE_PPC440
options FPU_EMU
Modified: head/sys/powerpc/include/pcpu.h
==============================================================================
--- head/sys/powerpc/include/pcpu.h Sun May 27 09:34:47 2012
(r236140)
+++ head/sys/powerpc/include/pcpu.h Sun May 27 10:25:20 2012
(r236141)
@@ -115,7 +115,7 @@ struct pmap;
PCPU_MD_COMMON_FIELDS \
PCPU_MD_AIM_FIELDS
#endif
-#ifdef E500
+#if defined(BOOKE)
#define PCPU_MD_FIELDS \
PCPU_MD_COMMON_FIELDS \
PCPU_MD_BOOKE_FIELDS
Modified: head/sys/powerpc/include/profile.h
==============================================================================
--- head/sys/powerpc/include/profile.h Sun May 27 09:34:47 2012
(r236140)
+++ head/sys/powerpc/include/profile.h Sun May 27 10:25:20 2012
(r236141)
@@ -172,12 +172,13 @@ __asm( " .globl _mcount \n" \
#define __PROFILE_VECTOR_BASE EXC_RST
#define __PROFILE_VECTOR_TOP (EXC_LAST + 0x100)
#endif /* AIM */
-#ifdef E500
+#if defined(BOOKE)
extern char interrupt_vector_base[];
extern char interrupt_vector_top[];
#define __PROFILE_VECTOR_BASE (uintfptr_t)interrupt_vector_base
#define __PROFILE_VECTOR_TOP (uintfptr_t)interrupt_vector_top
-#endif /* E500 */
+#endif /* BOOKE_E500 || BOOKE_PPC4XX */
+
#endif /* !COMPILING_LINT */
#ifndef __PROFILE_VECTOR_BASE
Modified: head/sys/powerpc/include/psl.h
==============================================================================
--- head/sys/powerpc/include/psl.h Sun May 27 09:34:47 2012
(r236140)
+++ head/sys/powerpc/include/psl.h Sun May 27 10:25:20 2012
(r236141)
@@ -35,7 +35,7 @@
#ifndef _MACHINE_PSL_H_
#define _MACHINE_PSL_H_
-#if defined(E500)
+#if defined(BOOKE_E500)
/*
* Machine State Register (MSR) - e500 core
*
@@ -67,7 +67,29 @@
#define PSL_KERNSET (PSL_CE | PSL_ME | PSL_EE)
#define PSL_USERSET (PSL_KERNSET | PSL_PR)
-#else /* if defined(E500) */
+#elif defined(BOOKE_PPC4XX)
+/*
+ * Machine State Register (MSR) - PPC4xx core
+ */
+#define PSL_WE (0x80000000 >> 13) /* Wait State Enable */
+#define PSL_CE (0x80000000 >> 14) /* Critical Interrupt Enable */
+#define PSL_EE (0x80000000 >> 16) /* External Interrupt Enable */
+#define PSL_PR (0x80000000 >> 17) /* Problem State */
+#define PSL_FP (0x80000000 >> 18) /* Floating Point Available */
+#define PSL_ME (0x80000000 >> 19) /* Machine Check Enable */
+#define PSL_FE0 (0x80000000 >> 20) /* Floating-point exception
mode 0 */
+#define PSL_DWE (0x80000000 >> 21) /* Debug Wait Enable */
+#define PSL_DE (0x80000000 >> 22) /* Debug interrupt Enable */
+#define PSL_FE1 (0x80000000 >> 23) /* Floating-point exception
mode 1 */
+#define PSL_IS (0x80000000 >> 26) /* Instruction Address Space */
+#define PSL_DS (0x80000000 >> 27) /* Data Address Space */
+
+#define PSL_KERNSET (PSL_CE | PSL_ME | PSL_EE | PSL_FP)
+#define PSL_USERSET (PSL_KERNSET | PSL_PR)
+
+#define PSL_FE_DFLT 0x00000000UL /* default == none */
+
+#else /* if defined(BOOKE_*) */
/*
* Machine State Register (MSR)
*
@@ -127,5 +149,5 @@
#define PSL_USERSTATIC (PSL_USERSET | PSL_IP | 0x87c0008c)
-#endif /* if defined(E500) */
+#endif /* if defined(BOOKE_E500) */
#endif /* _MACHINE_PSL_H_ */
Modified: head/sys/powerpc/include/pte.h
==============================================================================
--- head/sys/powerpc/include/pte.h Sun May 27 09:34:47 2012
(r236140)
+++ head/sys/powerpc/include/pte.h Sun May 27 10:25:20 2012
(r236141)
@@ -163,7 +163,7 @@ extern u_int dsisr(void);
#endif /* _KERNEL */
#endif /* LOCORE */
-#else
+#else /* BOOKE */
#include <machine/tlb.h>
@@ -224,6 +224,8 @@ typedef struct pte pte_t;
/* RPN mask, TLB0 4K pages */
#define PTE_PA_MASK PAGE_MASK
+#if defined(BOOKE_E500)
+
/* PTE bits assigned to MAS2, MAS3 flags */
#define PTE_W MAS2_W
#define PTE_I MAS2_I
@@ -241,6 +243,26 @@ typedef struct pte pte_t;
#define PTE_MAS3_MASK ((MAS3_UX | MAS3_SX | MAS3_UW \
| MAS3_SW | MAS3_UR | MAS3_SR) << PTE_MAS3_SHIFT)
+#elif defined(BOOKE_PPC4XX)
+
+#define PTE_WL1 TLB_WL1
+#define PTE_IL2I TLB_IL2I
+#define PTE_IL2D TLB_IL2D
+
+#define PTE_W TLB_W
+#define PTE_I TLB_I
+#define PTE_M TLB_M
+#define PTE_G TLB_G
+
+#define PTE_UX TLB_UX
+#define PTE_SX TLB_SX
+#define PTE_UW TLB_UW
+#define PTE_SW TLB_SW
+#define PTE_UR TLB_UR
+#define PTE_SR TLB_SR
+
+#endif
+
/* Other PTE flags */
#define PTE_VALID 0x80000000 /* Valid */
#define PTE_MODIFIED 0x40000000 /* Modified */
@@ -256,6 +278,5 @@ typedef struct pte pte_t;
#define PTE_ISMODIFIED(pte) ((pte)->flags & PTE_MODIFIED)
#define PTE_ISREFERENCED(pte) ((pte)->flags & PTE_REFERENCED)
-#endif /* #elif defined(E500) */
-
+#endif /* BOOKE_PPC4XX */
#endif /* _MACHINE_PTE_H_ */
Modified: head/sys/powerpc/include/spr.h
==============================================================================
--- head/sys/powerpc/include/spr.h Sun May 27 09:34:47 2012
(r236140)
+++ head/sys/powerpc/include/spr.h Sun May 27 10:25:20 2012
(r236141)
@@ -455,7 +455,7 @@
#define SPR_DAC1 0x3f6 /* 4.. Data Address Compare 1 */
#define SPR_DAC2 0x3f7 /* 4.. Data Address Compare 2 */
#define SPR_PIR 0x3ff /* .6. Processor Identification
Register */
-#elif defined(E500)
+#elif defined(BOOKE)
#define SPR_PIR 0x11e /* ..8 Processor Identification
Register */
#define SPR_DBSR 0x130 /* ..8 Debug Status Register */
#define DBSR_IDE 0x80000000 /* Imprecise debug event.
*/
@@ -628,7 +628,7 @@
#define ESR_DIZ 0x00800000 /* Data/instruction
storage interrupt - zone fault */
#define ESR_U0F 0x00008000 /* Data storage interrupt
- U0 fault */
-#elif defined(E500)
+#elif defined(BOOKE)
#define SPR_MCSR 0x23c /* ..8 Machine Check Syndrome
register */
@@ -642,12 +642,20 @@
#define ESR_BO 0x00020000 /* Data/instruction
storage, byte ordering */
#define ESR_SPE 0x00000080 /* SPE exception bit */
-
#define SPR_CSRR0 0x03a /* ..8 58 Critical SRR0 */
#define SPR_CSRR1 0x03b /* ..8 59 Critical SRR1 */
#define SPR_MCSRR0 0x23a /* ..8 570 Machine check SRR0 */
#define SPR_MCSRR1 0x23b /* ..8 571 Machine check SRR1 */
+#define SPR_MMUCR 0x3b2 /* 4.. MMU Control Register */
+#define MMUCR_SWOA (0x80000000 >> 7)
+#define MMUCR_U1TE (0x80000000 >> 9)
+#define MMUCR_U2SWOAE (0x80000000 >> 10)
+#define MMUCR_DULXE (0x80000000 >> 12)
+#define MMUCR_IULXE (0x80000000 >> 13)
+#define MMUCR_STS (0x80000000 >> 15)
+#define MMUCR_STID_MASK (0xFF000000 >> 24)
+
#define SPR_MMUCSR0 0x3f4 /* ..8 1012 MMU Control and
Status Register 0 */
#define MMUCSR0_L2TLB0_FI 0x04 /* TLB0 flash invalidate */
#define MMUCSR0_L2TLB1_FI 0x02 /* TLB1 flash invalidate */
@@ -758,6 +766,5 @@
#define BUCSR_BPEN 0x00000001 /* Branch Prediction
Enable */
#define BUCSR_BBFI 0x00000200 /* Branch Buffer Flash
Invalidate */
-#endif /* #elif defined(E500) */
-
+#endif /* BOOKE */
#endif /* !_POWERPC_SPR_H_ */
Modified: head/sys/powerpc/include/tlb.h
==============================================================================
--- head/sys/powerpc/include/tlb.h Sun May 27 09:34:47 2012
(r236140)
+++ head/sys/powerpc/include/tlb.h Sun May 27 10:25:20 2012
(r236141)
@@ -1,5 +1,5 @@
/*-
- * Copyright (C) 2006 Semihalf, Marian Balakowicz <m...@semihalf.com>
+ * Copyright (C) 2006-2012 Semihalf.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,6 +30,8 @@
#ifndef _MACHINE_TLB_H_
#define _MACHINE_TLB_H_
+#if defined(BOOKE_E500)
+
/* PowerPC E500 MAS registers */
#define MAS0_TLBSEL(x) ((x << 28) & 0x10000000)
#define MAS0_ESEL(x) ((x << 16) & 0x000F0000)
@@ -122,15 +124,6 @@
#define _TLB_ENTRY_MEM (0)
#endif
-#define TID_KERNEL 0 /* TLB TID to use for kernel (shared)
translations */
-#define TID_KRESERVED 1 /* Number of TIDs reserved for kernel */
-#define TID_URESERVED 0 /* Number of TIDs reserved for user */
-#define TID_MIN (TID_KRESERVED + TID_URESERVED)
-#define TID_MAX 255
-#define TID_NONE -1
-
-#define TLB_UNLOCKED 0
-
#if !defined(LOCORE)
typedef struct tlb_entry {
uint32_t mas1;
@@ -138,15 +131,80 @@ typedef struct tlb_entry {
uint32_t mas3;
} tlb_entry_t;
-typedef int tlbtid_t;
-struct pmap;
-
void tlb0_print_tlbentries(void);
void tlb1_inval_entry(unsigned int);
void tlb1_init(vm_offset_t);
void tlb1_print_entries(void);
void tlb1_print_tlbentries(void);
+#endif /* !LOCORE */
+
+#elif defined(BOOKE_PPC4XX)
+
+/* TLB Words */
+#define TLB_PAGEID 0
+#define TLB_XLAT 1
+#define TLB_ATTRIB 2
+
+/* Page identification fields */
+#define TLB_EPN_MASK (0xFFFFFC00 >> 0)
+#define TLB_VALID (0x80000000 >> 22)
+#define TLB_TS (0x80000000 >> 23)
+#define TLB_SIZE_1K (0x00000000 >> 24)
+#define TLB_SIZE_MASK (0xF0000000 >> 24)
+
+/* Translation fields */
+#define TLB_RPN_MASK (0xFFFFFC00 >> 0)
+#define TLB_ERPN_MASK (0xF0000000 >> 28)
+
+/* Storage attribute and access control fields */
+#define TLB_WL1 (0x80000000 >> 11)
+#define TLB_IL1I (0x80000000 >> 12)
+#define TLB_IL1D (0x80000000 >> 13)
+#define TLB_IL2I (0x80000000 >> 14)
+#define TLB_IL2D (0x80000000 >> 15)
+#define TLB_U0 (0x80000000 >> 16)
+#define TLB_U1 (0x80000000 >> 17)
+#define TLB_U2 (0x80000000 >> 18)
+#define TLB_U3 (0x80000000 >> 19)
+#define TLB_W (0x80000000 >> 20)
+#define TLB_I (0x80000000 >> 21)
+#define TLB_M (0x80000000 >> 22)
+#define TLB_G (0x80000000 >> 23)
+#define TLB_E (0x80000000 >> 24)
+#define TLB_UX (0x80000000 >> 26)
+#define TLB_UW (0x80000000 >> 27)
+#define TLB_UR (0x80000000 >> 28)
+#define TLB_SX (0x80000000 >> 29)
+#define TLB_SW (0x80000000 >> 30)
+#define TLB_SR (0x80000000 >> 31)
+#define TLB_SIZE 64
+
+#define TLB_SIZE_4K (0x10000000 >> 24)
+#define TLB_SIZE_16K (0x20000000 >> 24)
+#define TLB_SIZE_64K (0x30000000 >> 24)
+#define TLB_SIZE_256K (0x40000000 >> 24)
+#define TLB_SIZE_1M (0x50000000 >> 24)
+#define TLB_SIZE_16M (0x70000000 >> 24)
+#define TLB_SIZE_256M (0x90000000 >> 24)
+#define TLB_SIZE_1G (0xA0000000 >> 24)
+
+#endif /* BOOKE_E500 */
+
+#define TID_KERNEL 0 /* TLB TID to use for kernel (shared)
translations */
+#define TID_KRESERVED 1 /* Number of TIDs reserved for kernel */
+#define TID_URESERVED 0 /* Number of TIDs reserved for user */
+#define TID_MIN (TID_KRESERVED + TID_URESERVED)
+#define TID_MAX 255
+#define TID_NONE -1
+
+#define TLB_UNLOCKED 0
+
+#if !defined(LOCORE)
+
+typedef int tlbtid_t;
+
+struct pmap;
void tlb_lock(uint32_t *);
void tlb_unlock(uint32_t *);
Modified: head/sys/powerpc/include/trap.h
==============================================================================
--- head/sys/powerpc/include/trap.h Sun May 27 09:34:47 2012
(r236140)
+++ head/sys/powerpc/include/trap.h Sun May 27 10:25:20 2012
(r236141)
@@ -2,7 +2,7 @@
#if defined(AIM)
#include <machine/trap_aim.h>
-#elif defined(E500)
+#elif defined(BOOKE)
#include <machine/trap_booke.h>
#endif
Modified: head/sys/powerpc/include/vmparam.h
==============================================================================
--- head/sys/powerpc/include/vmparam.h Sun May 27 09:34:47 2012
(r236140)
+++ head/sys/powerpc/include/vmparam.h Sun May 27 10:25:20 2012
(r236141)
@@ -78,7 +78,7 @@
#endif
#define SHAREDPAGE (VM_MAXUSER_ADDRESS - PAGE_SIZE)
#else /* LOCORE */
-#if !defined(__powerpc64__) && defined(E500)
+#if !defined(__powerpc64__) && defined(BOOKE)
#define VM_MIN_ADDRESS 0
#define VM_MAXUSER_ADDRESS 0x7ffff000
#endif
Modified: head/sys/powerpc/powerpc/cpu.c
==============================================================================
--- head/sys/powerpc/powerpc/cpu.c Sun May 27 09:34:47 2012
(r236140)
+++ head/sys/powerpc/powerpc/cpu.c Sun May 27 10:25:20 2012
(r236141)
@@ -446,6 +446,7 @@ cpu_6xx_print_cacheinfo(u_int cpuid, uin
static void
cpu_booke_setup(int cpuid, uint16_t vers)
{
+#ifdef BOOKE_E500
register_t hid0;
hid0 = mfspr(SPR_HID0);
@@ -457,6 +458,7 @@ cpu_booke_setup(int cpuid, uint16_t vers
mtspr(SPR_HID0, hid0);
printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, HID0_E500_BITMASK);
+#endif
if (cpu_idle_hook == NULL)
cpu_idle_hook = cpu_idle_booke;
Modified: head/sys/powerpc/powerpc/db_trace.c
==============================================================================
--- head/sys/powerpc/powerpc/db_trace.c Sun May 27 09:34:47 2012
(r236140)
+++ head/sys/powerpc/powerpc/db_trace.c Sun May 27 10:25:20 2012
(r236141)
@@ -102,7 +102,7 @@ struct db_variable db_regs[] = {
{ "dar", DB_OFFSET(cpu.aim.dar), db_frame },
{ "dsisr", DB_OFFSET(cpu.aim.dsisr), db_frame },
#endif
-#ifdef E500
+#if defined(BOOKE)
{ "dear", DB_OFFSET(cpu.booke.dear), db_frame },
{ "esr", DB_OFFSET(cpu.booke.esr), db_frame },
#endif
@@ -243,7 +243,7 @@ db_backtrace(struct thread *td, db_addr_
case EXC_SC: trapstr = "SC"; break;
case EXC_EXI: trapstr = "EXI"; break;
case EXC_MCHK: trapstr = "MCHK"; break;
-#ifndef E500
+#if !defined(BOOKE)
case EXC_VEC: trapstr = "VEC"; break;
case EXC_FPA: trapstr = "FPA"; break;
case EXC_BPT: trapstr = "BPT"; break;
Modified: head/sys/powerpc/powerpc/gdb_machdep.c
==============================================================================
--- head/sys/powerpc/powerpc/gdb_machdep.c Sun May 27 09:34:47 2012
(r236140)
+++ head/sys/powerpc/powerpc/gdb_machdep.c Sun May 27 10:25:20 2012
(r236141)
@@ -84,7 +84,7 @@ gdb_cpu_setreg(int regnum, void *val)
int
gdb_cpu_signal(int vector, int dummy __unused)
{
-#ifdef E500
+#if defined(BOOKE)
if (vector == EXC_DEBUG || vector == EXC_PGM)
return (SIGTRAP);
#else
Modified: head/sys/powerpc/powerpc/genassym.c
==============================================================================
--- head/sys/powerpc/powerpc/genassym.c Sun May 27 09:34:47 2012
(r236140)
+++ head/sys/powerpc/powerpc/genassym.c Sun May 27 10:25:20 2012
(r236141)
@@ -63,7 +63,7 @@ ASSYM(PC_TEMPSAVE, offsetof(struct pcpu,
ASSYM(PC_DISISAVE, offsetof(struct pcpu, pc_disisave));
ASSYM(PC_DBSAVE, offsetof(struct pcpu, pc_dbsave));
-#ifdef E500
+#if defined(BOOKE)
ASSYM(PC_BOOKE_CRITSAVE, offsetof(struct pcpu, pc_booke_critsave));
ASSYM(PC_BOOKE_MCHKSAVE, offsetof(struct pcpu, pc_booke_mchksave));
ASSYM(PC_BOOKE_TLBSAVE, offsetof(struct pcpu, pc_booke_tlbsave));
@@ -116,15 +116,14 @@ ASSYM(SEGMENT_MASK, SEGMENT_MASK);
ASSYM(PM_SR, offsetof(struct pmap, pm_sr));
ASSYM(USER_SR, USER_SR);
#endif
-#elif defined(E500)
+#elif defined(BOOKE)
ASSYM(PM_PDIR, offsetof(struct pmap, pm_pdir));
-#endif
-
-#if defined(E500)
ASSYM(PTE_RPN, offsetof(struct pte, rpn));
ASSYM(PTE_FLAGS, offsetof(struct pte, flags));
+#if defined(BOOKE_E500)
ASSYM(TLB0_ENTRY_SIZE, sizeof(struct tlb_entry));
#endif
+#endif
#ifdef __powerpc64__
ASSYM(FSP, 48);
@@ -215,18 +214,20 @@ ASSYM(SF_UC, offsetof(struct sigframe, s
ASSYM(KERNBASE, KERNBASE);
ASSYM(MAXCOMLEN, MAXCOMLEN);
-#ifdef E500
+#if defined(BOOKE)
+ASSYM(PSL_DE, PSL_DE);
+ASSYM(PSL_DS, PSL_DS);
+ASSYM(PSL_IS, PSL_IS);
+ASSYM(PSL_CE, PSL_CE);
+#endif
+#if defined(BOOKE_E500)
ASSYM(PSL_UCLE, PSL_UCLE);
ASSYM(PSL_SPE, PSL_SPE);
ASSYM(PSL_WE, PSL_WE);
-ASSYM(PSL_CE, PSL_CE);
ASSYM(PSL_UBLE, PSL_UBLE);
-ASSYM(PSL_DS, PSL_DS);
-ASSYM(PSL_IS, PSL_IS);
-ASSYM(PSL_DE, PSL_DE);
ASSYM(PSL_KERNSET_INIT, PSL_KERNSET_INIT);
-#else /* AIM */
+#elif defined(AIM)
#ifdef __powerpc64__
ASSYM(PSL_SF, PSL_SF);
ASSYM(PSL_HV, PSL_HV);
@@ -256,8 +257,9 @@ ASSYM(PSL_FE1, PSL_FE1);
ASSYM(PSL_FP, PSL_FP);
ASSYM(PSL_ME, PSL_ME);
ASSYM(PSL_PR, PSL_PR);
+#if defined(BOOKE_E500)
ASSYM(PSL_PMM, PSL_PMM);
-
+#endif
ASSYM(PSL_KERNSET, PSL_KERNSET);
ASSYM(PSL_USERSET, PSL_USERSET);
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