Author: kib
Date: Fri Nov 16 07:07:00 2012
New Revision: 243139
URL: http://svnweb.freebsd.org/changeset/base/243139
Log:
MFC r242432:
Provide the reading and display of the Standard Extended Features,
introduced with the IvyBridge CPUs. Provide the definitions for new
bits in CR3 and CR4 registers.
Modified:
stable/9/sys/amd64/amd64/identcpu.c
stable/9/sys/amd64/amd64/initcpu.c
stable/9/sys/amd64/include/md_var.h
stable/9/sys/amd64/include/specialreg.h
Directory Properties:
stable/9/sys/ (props changed)
Modified: stable/9/sys/amd64/amd64/identcpu.c
==============================================================================
--- stable/9/sys/amd64/amd64/identcpu.c Fri Nov 16 07:05:57 2012
(r243138)
+++ stable/9/sys/amd64/amd64/identcpu.c Fri Nov 16 07:07:00 2012
(r243139)
@@ -384,6 +384,18 @@ printcpuinfo(void)
);
}
+ if (cpu_stdext_feature != 0) {
+ printf("\n Standard Extended Features=0x%b",
+ cpu_stdext_feature,
+ "\020"
+ "\001GSFSBASE"
+ "\002TSCADJ"
+ "\010SMEP"
+ "\012ENHMOVSB"
+ "\013INVPCID"
+ );
+ }
+
if (via_feature_rng != 0 || via_feature_xcrypt != 0)
print_via_padlock_info();
@@ -501,6 +513,11 @@ identify_cpu(void)
}
}
+ if (cpu_high >= 7) {
+ cpuid_count(7, 0, regs);
+ cpu_stdext_feature = regs[1];
+ }
+
if (cpu_vendor_id == CPU_VENDOR_INTEL ||
cpu_vendor_id == CPU_VENDOR_AMD ||
cpu_vendor_id == CPU_VENDOR_CENTAUR) {
Modified: stable/9/sys/amd64/amd64/initcpu.c
==============================================================================
--- stable/9/sys/amd64/amd64/initcpu.c Fri Nov 16 07:05:57 2012
(r243138)
+++ stable/9/sys/amd64/amd64/initcpu.c Fri Nov 16 07:07:00 2012
(r243139)
@@ -72,6 +72,7 @@ u_int cpu_vendor_id; /* CPU vendor ID *
u_int cpu_fxsr; /* SSE enabled */
u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
u_int cpu_clflush_line_size = 32;
+u_int cpu_stdext_feature;
u_int cpu_max_ext_state_size;
SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
Modified: stable/9/sys/amd64/include/md_var.h
==============================================================================
--- stable/9/sys/amd64/include/md_var.h Fri Nov 16 07:05:57 2012
(r243138)
+++ stable/9/sys/amd64/include/md_var.h Fri Nov 16 07:07:00 2012
(r243139)
@@ -48,6 +48,7 @@ extern u_int amd_pminfo;
extern u_int via_feature_rng;
extern u_int via_feature_xcrypt;
extern u_int cpu_clflush_line_size;
+extern u_int cpu_stdext_feature;
extern u_int cpu_fxsr;
extern u_int cpu_high;
extern u_int cpu_id;
Modified: stable/9/sys/amd64/include/specialreg.h
==============================================================================
--- stable/9/sys/amd64/include/specialreg.h Fri Nov 16 07:05:57 2012
(r243138)
+++ stable/9/sys/amd64/include/specialreg.h Fri Nov 16 07:07:00 2012
(r243139)
@@ -52,6 +52,8 @@
#define CR0_NW 0x20000000 /* Not Write-through */
#define CR0_CD 0x40000000 /* Cache Disable */
+#define CR3_PCID_SAVE 0x8000000000000000
+
/*
* Bits in PPro special registers
*/
@@ -66,7 +68,10 @@
#define CR4_PCE 0x00000100 /* Performance monitoring counter
enable */
#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */
+#define CR4_FSGSBASE 0x00010000 /* Enable FS/GS BASE accessing
instructions */
+#define CR4_PCIDE 0x00020000 /* Enable Context ID */
#define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */
+#define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution Prevention
*/
/*
* Bits in AMD64 special registers. EFER is 64 bits wide.
@@ -261,6 +266,12 @@
#define AMDID_COREID_SIZE 0x0000f000
#define AMDID_COREID_SIZE_SHIFT 12
+#define CPUID_STDEXT_FSGSBASE 0x00000001
+#define CPUID_STDEXT_TSC_ADJUST 0x00000002
+#define CPUID_STDEXT_SMEP 0x00000080
+#define CPUID_STDEXT_ENH_MOVSB 0x00000200
+#define CPUID_STDEXT_INVPCID 0x00000400
+
/*
* CPUID manufacturers identifiers
*/
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