Author: kib
Date: Sat Apr 16 06:07:13 2016
New Revision: 298101
URL: https://svnweb.freebsd.org/changeset/base/298101
Log:
Add x86 CPU features definitions published in the Intel SDM rev. 58.
Sponsored by: The FreeBSD Foundation
MFC after: 1 week
Modified:
head/sys/x86/include/specialreg.h
head/sys/x86/x86/identcpu.c
Modified: head/sys/x86/include/specialreg.h
==============================================================================
--- head/sys/x86/include/specialreg.h Sat Apr 16 05:14:55 2016
(r298100)
+++ head/sys/x86/include/specialreg.h Sat Apr 16 06:07:13 2016
(r298101)
@@ -332,6 +332,7 @@
*/
#define CPUID_STDEXT_FSGSBASE 0x00000001
#define CPUID_STDEXT_TSC_ADJUST 0x00000002
+#define CPUID_STDEXT_SGX 0x00000004
#define CPUID_STDEXT_BMI1 0x00000008
#define CPUID_STDEXT_HLE 0x00000010
#define CPUID_STDEXT_AVX2 0x00000020
@@ -341,7 +342,10 @@
#define CPUID_STDEXT_ERMS 0x00000200
#define CPUID_STDEXT_INVPCID 0x00000400
#define CPUID_STDEXT_RTM 0x00000800
+#define CPUID_STDEXT_PQM 0x00001000
+#define CPUID_STDEXT_NFPUSG 0x00002000
#define CPUID_STDEXT_MPX 0x00004000
+#define CPUID_STDEXT_PQE 0x00008000
#define CPUID_STDEXT_AVX512F 0x00010000
#define CPUID_STDEXT_AVX512DQ 0x00020000
#define CPUID_STDEXT_RDSEED 0x00040000
@@ -359,6 +363,16 @@
#define CPUID_STDEXT_AVX512BW 0x40000000
/*
+ * CPUID instruction 7 Structured Extended Features, leaf 0 ecx info
+ */
+#define CPUID_STDEXT2_PREFETCHWT1 0x00000001
+#define CPUID_STDEXT2_UMIP 0x00000004
+#define CPUID_STDEXT2_PKU 0x00000008
+#define CPUID_STDEXT2_OSPKE 0x00000010
+#define CPUID_STDEXT2_RDPID 0x00400000
+#define CPUID_STDEXT2_SGXLC 0x40000000
+
+/*
* CPUID manufacturers identifiers
*/
#define AMD_VENDOR_ID "AuthenticAMD"
Modified: head/sys/x86/x86/identcpu.c
==============================================================================
--- head/sys/x86/x86/identcpu.c Sat Apr 16 05:14:55 2016 (r298100)
+++ head/sys/x86/x86/identcpu.c Sat Apr 16 06:07:13 2016 (r298101)
@@ -926,6 +926,7 @@ printcpuinfo(void)
/* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
"\001FSGSBASE"
"\002TSCADJ"
+ "\003SGX"
/* Bit Manipulation Instructions */
"\004BMI1"
/* Hardware Lock Elision */
@@ -945,9 +946,9 @@ printcpuinfo(void)
"\014RTM"
"\015PQM"
"\016NFPUSG"
- "\020PQE"
/* Intel Memory Protection Extensions */
"\017MPX"
+ "\020PQE"
/* AVX512 Foundation */
"\021AVX512F"
"\022AVX512DQ"
@@ -976,8 +977,11 @@ printcpuinfo(void)
"\020"
"\001PREFETCHWT1"
"\002AVX512VBMI"
+ "\003UMIP"
"\004PKU"
"\005OSPKE"
+ "\027RDPID"
+ "\037SGXLC"
);
}
@@ -1935,7 +1939,10 @@ print_INTEL_TLB(u_int data)
printf("Instruction TLB: 4 KByte pages, fully associative, 48
entries\n");
break;
case 0x63:
- printf("Data TLB: 1 GByte pages, 4-way set associative, 4
entries\n");
+ printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set
associative, 32 entries and a separate array with 1 GByte pages, 4-way set
associative, 4 entries\n");
+ break;
+ case 0x64:
+ printf("Data TLB: 4 KBytes pages, 4-way set associative, 512
entries\n");
break;
case 0x66:
printf("1st-level data cache: 8 KB, 4-way set associative,
sectored cache, 64 byte line size\n");
@@ -2051,6 +2058,9 @@ print_INTEL_TLB(u_int data)
case 0xc3:
printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way
associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
break;
+ case 0xc4:
+ printf("DTLB: 2M/4M Byte pages, 4-way associative, 32
entries\n");
+ break;
case 0xca:
printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative,
512 entries\n");
break;
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