Re: riscv64: switch to clockintr(9)
On Tue, Nov 08 2022, Mark Kettenis wrote: >> Date: Tue, 8 Nov 2022 13:06:51 + >> From: Scott Cheloha >> >> On Mon, Nov 07, 2022 at 09:23:26PM +0100, Jeremie Courreges-Anglas wrote: >> > On Sun, Nov 06 2022, Scott Cheloha wrote: >> > > This patch switches riscv64 to clockintr(9). >> > > >> > > jca@ has been testing it (on a SiFive board?). It has survived two >> > > parallel release builds and upgrades from the resulting bsd.rd. >> > >> > I still get the same results on my HiFive Unmatched (produced by >> > SiFive indeed). The diff LGTM. >> > >> > Looks like clock and stat evcounts get merged with this diff. Not a big >> > problem but probably not intended? >> >> Whoops, good eye, forgot to mention that. >> >> This change is intended. With this patch, we can't keep a distinct >> count of hardclock() and statclock() calls anymore because >> clockintr_dispatch(9) handles the dispatch on behalf of the riscv64 >> code. So the "stat" evcount goes away. >> >> The "clock" evcount now represents a count of clock interrupts. >> That's it. One per riscv64 clock_intr() call. ack. Still ok jca@ > And I think that is fine. Those are the actual interrupts. Fine with me too! -- jca | PGP : 0x1524E7EE / 5135 92C1 AD36 5293 2BDF DDCC 0DFA 74AE 1524 E7EE
Re: riscv64: switch to clockintr(9)
> Date: Tue, 8 Nov 2022 13:06:51 + > From: Scott Cheloha > > On Mon, Nov 07, 2022 at 09:23:26PM +0100, Jeremie Courreges-Anglas wrote: > > On Sun, Nov 06 2022, Scott Cheloha wrote: > > > This patch switches riscv64 to clockintr(9). > > > > > > jca@ has been testing it (on a SiFive board?). It has survived two > > > parallel release builds and upgrades from the resulting bsd.rd. > > > > I still get the same results on my HiFive Unmatched (produced by > > SiFive indeed). The diff LGTM. > > > > Looks like clock and stat evcounts get merged with this diff. Not a big > > problem but probably not intended? > > Whoops, good eye, forgot to mention that. > > This change is intended. With this patch, we can't keep a distinct > count of hardclock() and statclock() calls anymore because > clockintr_dispatch(9) handles the dispatch on behalf of the riscv64 > code. So the "stat" evcount goes away. > > The "clock" evcount now represents a count of clock interrupts. > That's it. One per riscv64 clock_intr() call. And I think that is fine. Those are the actual interrupts. > > > It could use testing on another machine. Are there other practical > > > machines aside from SiFive? > > > > There aren't that many vendors/machines that we do support: > > > > https://www.openbsd.org/riscv64.html > > Okay, noted. > >
Re: riscv64: switch to clockintr(9)
On Mon, Nov 07, 2022 at 09:23:26PM +0100, Jeremie Courreges-Anglas wrote: > On Sun, Nov 06 2022, Scott Cheloha wrote: > > This patch switches riscv64 to clockintr(9). > > > > jca@ has been testing it (on a SiFive board?). It has survived two > > parallel release builds and upgrades from the resulting bsd.rd. > > I still get the same results on my HiFive Unmatched (produced by > SiFive indeed). The diff LGTM. > > Looks like clock and stat evcounts get merged with this diff. Not a big > problem but probably not intended? Whoops, good eye, forgot to mention that. This change is intended. With this patch, we can't keep a distinct count of hardclock() and statclock() calls anymore because clockintr_dispatch(9) handles the dispatch on behalf of the riscv64 code. So the "stat" evcount goes away. The "clock" evcount now represents a count of clock interrupts. That's it. One per riscv64 clock_intr() call. > > It could use testing on another machine. Are there other practical > > machines aside from SiFive? > > There aren't that many vendors/machines that we do support: > > https://www.openbsd.org/riscv64.html Okay, noted.
Re: riscv64: switch to clockintr(9)
On Sun, Nov 06 2022, Scott Cheloha wrote: > This patch switches riscv64 to clockintr(9). > > jca@ has been testing it (on a SiFive board?). It has survived two > parallel release builds and upgrades from the resulting bsd.rd. I still get the same results on my HiFive Unmatched (produced by SiFive indeed). The diff LGTM. Looks like clock and stat evcounts get merged with this diff. Not a big problem but probably not intended? > It could use testing on another machine. Are there other practical > machines aside from SiFive? There aren't that many vendors/machines that we do support: https://www.openbsd.org/riscv64.html -- jca | PGP : 0x1524E7EE / 5135 92C1 AD36 5293 2BDF DDCC 0DFA 74AE 1524 E7EE
