Re: arm64 gic-v3 driver

2017-04-29 Thread Patrick Wildt 
On Sat, Apr 29, 2017 at 06:45:15PM +0200, Mark Kettenis wrote:
> The firefly rk3399 board has a gic-v3, so I'd like to get Dale's
> driver into the tree.  I did some further cleanup, renamed the driver
> to agintc(4) (as jsg@ felt the "new" in angintc(4) did't make sense)
> and fixed two bugs:
> 
> * prival in setipl() was used uninitialized
> 
> * apparently a dsb instruction is needed after reading the ICC_IAR1
>   register
> 
> I deliberately tried to keep the differences to ampintc(4) as small as
> possible such that it easier to compare the code.  I have a small
> followup diff that will tweak ampintc(4) in the cases where the code
> in agintc(4) was cleaner to start with.
> 
> There may be more bugs lurking in this code as I'm still seeing plenty
> of weird behaviour.  But at least this will get me going.
> 
> ok?

Yes, please.  I have seen some whitespace issues which I commented
inline, feel free to fix those before committing.  Need to do another
read later, but please just go ahead.

> 
> 
> Index: arch/arm64/dev/agintc.c
> ===
> RCS file: arch/arm64/dev/agintc.c
> diff -N arch/arm64/dev/agintc.c
> --- /dev/null 1 Jan 1970 00:00:00 -
> +++ arch/arm64/dev/agintc.c   29 Apr 2017 16:33:50 -
> @@ -0,0 +1,785 @@
> +/* $OpenBSD$ */
> +/*
> + * Copyright (c) 2007, 2009, 2011, 2017 Dale Rahn 
> + *
> + * Permission to use, copy, modify, and distribute this software for any
> + * purpose with or without fee is hereby granted, provided that the above
> + * copyright notice and this permission notice appear in all copies.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
> + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
> + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
> + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
> + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
> + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
> + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
> + */
> +
> +/*
> + * This is a device driver for the GICv3/GICv4 IP from ARM as specified
> + * in IHI0069C, an example of this hardware is the GIC 500.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +
> +#define ICC_PMR  s3_0_c4_c6_0
> +#define ICC_IAR0 s3_0_c12_c8_0
> +#define ICC_EOIR0s3_0_c12_c8_1
> +#define ICC_HPPIR0   s3_0_c12_c8_2
> +#define ICC_BPR0 s3_0_c12_c8_3
> +
> +#define ICC_DIR  s3_0_c12_c11_1
> +#define ICC_SGI1Rs3_0_c12_c11_5
> +#define ICC_SGI0Rs3_0_c12_c11_7
> +
> +#define ICC_IAR1 s3_0_c12_c12_0
> +#define ICC_EOIR1s3_0_c12_c12_1
> +#define ICC_HPPIR1   s3_0_c12_c12_2
> +#define ICC_BPR1 s3_0_c12_c12_3
> +#define ICC_CTLR s3_0_c12_c12_4
> +#define ICC_SRE_EL1  s3_0_c12_c12_5
> +#define  ICC_SRE_EL1_EN  0x7
> +#define ICC_IGRPEN0  s3_0_c12_c12_6
> +#define ICC_IGRPEN1  s3_0_c12_c12_7
> +
> +#define _STR(x) #x
> +#define STR(x) _STR(x)
> +
> +/* distributor registers */
> +#define  GICD_CTLR   0x
> +// non-secure
> +#define  GICD_CTLR_RWP   (1U << 31)

Replace the first space with a tab.

> +#define   GICD_CTRL_EnableGrp1   (1 << 0)
> +#define   GICD_CTRL_EnableGrp1A  (1 << 1)
> +#define   GICD_CTRL_ARE_NS   (1 << 4)
> +#define  GICD_TYPER  0x0004
> +#define   GICD_TYPER_ITLINE_M0xf
> +#define  GICD_IIDR   0x0008
> +#define  GICD_ISENABLER(i)   (0x0100 + (IRQ_TO_REG32(i) * 4))
> +#define  GICD_ICENABLER(i)   (0x0180 + (IRQ_TO_REG32(i) * 4))
> +#define  GICD_ISPENDR(i) (0x0200 + (IRQ_TO_REG32(i) * 4))
> +#define  GICD_ICPENDR(i) (0x0280 + (IRQ_TO_REG32(i) * 4))
> +#define  GICD_ISACTIVER(i)   (0x0300 + (IRQ_TO_REG32(i) * 4))
> +#define  GICD_ICACTIVER(i)   (0x0380 + (IRQ_TO_REG32(i) * 4))
> +#define  GICD_IPRIORITYR(i)  (0x0400 + (i))
> +#define  GICD_ICFGR(i)   (0x0c00 + (IRQ_TO_REG16(i) * 4))
> +#define  GICD_IROUTER(i) (0x6000 + ((i) * 8))
> +
> +/* redistributor registers */
> +#define GICR_CTLR0x0
> +#define  GICR_CTLR_RWP   ((1U << 31) | (1 << 3))
> +#define GICR_IIDR0x4
> +#define GICR_TYPER   0x8
> +#define  GICR_TYPER_LAST (1 << 4)
> +#define  GICR_TYPER_VLPIS(1 << 1)
> +#define GICR_WAKER   0x00014
> +#define  GICR_WAKER_X31  (1U << 31)
> +#define  GICR_WAKER_CHILDRENASLEEP   (1 << 2)
> +#define  GICR_WAKER_PROCESSORSLEEP   (1 << 1)
> +#define  GICR_WAKER_X0   (1 << 0)
> +#define GICR_ISENABLE0   0x10100
> +#define

arm64 gic-v3 driver

2017-04-29 Thread Mark Kettenis 
The firefly rk3399 board has a gic-v3, so I'd like to get Dale's
driver into the tree.  I did some further cleanup, renamed the driver
to agintc(4) (as jsg@ felt the "new" in angintc(4) did't make sense)
and fixed two bugs:

* prival in setipl() was used uninitialized

* apparently a dsb instruction is needed after reading the ICC_IAR1
  register

I deliberately tried to keep the differences to ampintc(4) as small as
possible such that it easier to compare the code.  I have a small
followup diff that will tweak ampintc(4) in the cases where the code
in agintc(4) was cleaner to start with.

There may be more bugs lurking in this code as I'm still seeing plenty
of weird behaviour.  But at least this will get me going.

ok?


Index: arch/arm64/dev/agintc.c
===
RCS file: arch/arm64/dev/agintc.c
diff -N arch/arm64/dev/agintc.c
--- /dev/null   1 Jan 1970 00:00:00 -
+++ arch/arm64/dev/agintc.c 29 Apr 2017 16:33:50 -
@@ -0,0 +1,785 @@
+/* $OpenBSD$ */
+/*
+ * Copyright (c) 2007, 2009, 2011, 2017 Dale Rahn 
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * This is a device driver for the GICv3/GICv4 IP from ARM as specified
+ * in IHI0069C, an example of this hardware is the GIC 500.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include 
+#include 
+
+#define ICC_PMRs3_0_c4_c6_0
+#define ICC_IAR0   s3_0_c12_c8_0
+#define ICC_EOIR0  s3_0_c12_c8_1
+#define ICC_HPPIR0 s3_0_c12_c8_2
+#define ICC_BPR0   s3_0_c12_c8_3
+
+#define ICC_DIRs3_0_c12_c11_1
+#define ICC_SGI1R  s3_0_c12_c11_5
+#define ICC_SGI0R  s3_0_c12_c11_7
+
+#define ICC_IAR1   s3_0_c12_c12_0
+#define ICC_EOIR1  s3_0_c12_c12_1
+#define ICC_HPPIR1 s3_0_c12_c12_2
+#define ICC_BPR1   s3_0_c12_c12_3
+#define ICC_CTLR   s3_0_c12_c12_4
+#define ICC_SRE_EL1s3_0_c12_c12_5
+#define  ICC_SRE_EL1_EN0x7
+#define ICC_IGRPEN0s3_0_c12_c12_6
+#define ICC_IGRPEN1s3_0_c12_c12_7
+
+#define _STR(x) #x
+#define STR(x) _STR(x)
+
+/* distributor registers */
+#defineGICD_CTLR   0x
+// non-secure
+#define  GICD_CTLR_RWP (1U << 31)
+#define GICD_CTRL_EnableGrp1   (1 << 0)
+#define GICD_CTRL_EnableGrp1A  (1 << 1)
+#define GICD_CTRL_ARE_NS   (1 << 4)
+#defineGICD_TYPER  0x0004
+#define GICD_TYPER_ITLINE_M0xf
+#defineGICD_IIDR   0x0008
+#defineGICD_ISENABLER(i)   (0x0100 + (IRQ_TO_REG32(i) * 4))
+#defineGICD_ICENABLER(i)   (0x0180 + (IRQ_TO_REG32(i) * 4))
+#defineGICD_ISPENDR(i) (0x0200 + (IRQ_TO_REG32(i) * 4))
+#defineGICD_ICPENDR(i) (0x0280 + (IRQ_TO_REG32(i) * 4))
+#defineGICD_ISACTIVER(i)   (0x0300 + (IRQ_TO_REG32(i) * 4))
+#defineGICD_ICACTIVER(i)   (0x0380 + (IRQ_TO_REG32(i) * 4))
+#defineGICD_IPRIORITYR(i)  (0x0400 + (i))
+#defineGICD_ICFGR(i)   (0x0c00 + (IRQ_TO_REG16(i) * 4))
+#defineGICD_IROUTER(i) (0x6000 + ((i) * 8))
+
+/* redistributor registers */
+#define GICR_CTLR  0x0
+#define  GICR_CTLR_RWP ((1U << 31) | (1 << 3))
+#define GICR_IIDR  0x4
+#define GICR_TYPER 0x8
+#define  GICR_TYPER_LAST   (1 << 4)
+#define  GICR_TYPER_VLPIS  (1 << 1)
+#define GICR_WAKER 0x00014
+#define  GICR_WAKER_X31(1U << 31)
+#define  GICR_WAKER_CHILDRENASLEEP (1 << 2)
+#define  GICR_WAKER_PROCESSORSLEEP (1 << 1)
+#define  GICR_WAKER_X0 (1 << 0)
+#define GICR_ISENABLE0 0x10100
+#define GICR_ICENABLE0 0x10180
+#define GICR_ISPENDR0  0x10200
+#define GICR_ICPENDR0  0x10280
+#define GICR_ISACTIVE0 0x10300
+#define GICR_ICACTIVE0 0x10380
+#define GICR_IPRIORITYR(i) (0x10400 + (i))
+#define GICR_ICFGR00x10c00
+#define GICR_ICFGR10x10c04
+
+#define IRQ_TO_REG32(i)(((i) >> 5) & 0x7)
+#define IRQ_TO_REG32BIT(i) ((i) & 0x1f)
+
+#define IRQ_TO_REG16(i)