subject:"fix dpms issues on ivy bridge"

Re: fix dpms issues on ivy bridge

2013-02-01 Thread Martin Pieuchot

On 29/01/13(Tue) 13:34, Jonathan Gray wrote:
 The following changes mostly based on what has happened in
 the upstream drm code seems to resolve problems with screen corruption
 on power saving/dpms on ivy bridge with ums here.  Testing on ironlake/
 sandy bridge/ivy bridge (aka Core i*) to make sure this doesn't break
 anything appreciated.
 
 - remove a workaround which was in itself causing issues
 - switch the order of disabling fdi rx  tx
 - disable DPLL_SEL when disabling the crtc
 - add a few extra delays

I don't have hardware to test this on, but it looks ok to me. However I
think that now would be the right time to commit it, if you think you
received enough test reports, as we are approaching the release.

 
 Index: i830_display.c
 ===
 RCS file: /cvs/xenocara/driver/xf86-video-intel/src/i830_display.c,v
 retrieving revision 1.16
 diff -u -p -r1.16 i830_display.c
 --- i830_display.c15 Jan 2013 06:31:43 -  1.16
 +++ i830_display.c29 Jan 2013 02:24:21 -
 @@ -1535,16 +1535,6 @@ static void ivb_manual_fdi_link_train(xf
   INREG(fdi_rx_reg);
  
   usleep(150);
 -
 - if (HAS_PCH_CPT(intel)) {
 - temp = INREG(SOUTH_CHICKEN1);
 - temp |= FDI_PHASE_SYNC_OVR(pipe);
 - OUTREG(SOUTH_CHICKEN1, temp); /* once to unlock... */
 - temp |= FDI_PHASE_SYNC_EN(pipe);
 - OUTREG(SOUTH_CHICKEN1, temp); /* then again to enable */
 - INREG(SOUTH_CHICKEN1);
 - usleep(150);
 - }
   
   for (i = 0; i  4; i++) {
   temp = INREG(fdi_tx_reg);
 @@ -1862,11 +1852,6 @@ ironlake_crtc_disable(xf86CrtcPtr crtc)
   OUTREG(pf_win_size, 0);
   INREG(pf_win_size);
  
 - ErrorF(FDI TX disable\n);
 - temp = INREG(fdi_tx_reg);
 - OUTREG(fdi_tx_reg, temp  ~FDI_TX_ENABLE);
 - INREG(fdi_tx_reg);
 -
   ErrorF(FDI RX disable\n);
   temp = INREG(fdi_rx_reg);
   temp = ~(0x07  16);
 @@ -1876,14 +1861,13 @@ ironlake_crtc_disable(xf86CrtcPtr crtc)
  
   usleep(100);
  
 - ErrorF(FDI TX train 1 preload\n);
 - /* still set train pattern 1 */
 + ErrorF(FDI TX disable\n);
   temp = INREG(fdi_tx_reg);
 - temp = ~FDI_LINK_TRAIN_NONE;
 - temp |= FDI_LINK_TRAIN_PATTERN_1;
 - OUTREG(fdi_tx_reg, temp);
 + OUTREG(fdi_tx_reg, temp  ~FDI_TX_ENABLE);
   INREG(fdi_tx_reg);
  
 + usleep(100);
 +
   ErrorF(FDI RX train 1 preload\n);
   temp = INREG(fdi_rx_reg);
   if (HAS_PCH_CPT(intel)) {
 @@ -1898,6 +1882,16 @@ ironlake_crtc_disable(xf86CrtcPtr crtc)
  
   usleep(100);
  
 + ErrorF(FDI TX train 1 preload\n);
 + /* still set train pattern 1 */
 + temp = INREG(fdi_tx_reg);
 + temp = ~FDI_LINK_TRAIN_NONE;
 + temp |= FDI_LINK_TRAIN_PATTERN_1;
 + OUTREG(fdi_tx_reg, temp);
 + INREG(fdi_tx_reg);
 +
 + usleep(100);
 +
   if (i830PipeHasType(crtc, I830_OUTPUT_LVDS)) {
   ErrorF(LVDS port force off\n);
   while ((temp = INREG(PCH_LVDS))  PORT_ENABLE) {
 @@ -1933,6 +1927,25 @@ ironlake_crtc_disable(xf86CrtcPtr crtc)
   OUTREG(transconf_reg, temp);
   INREG(transconf_reg);
   usleep(100);
 +
 + if (HAS_PCH_CPT(intel)) {
 + /* disable DPLL_SEL */
 + temp = INREG(PCH_DPLL_SEL);
 + switch (pipe) {
 + case 0:
 + temp = ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
 + break;
 + case 1:
 + temp = ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
 + break;
 + case 2:
 + /* C shares PLL A or B */
 + temp = ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
 + break;
 + }
 + OUTREG(PCH_DPLL_SEL, temp);
 + INREG(PCH_DPLL_SEL);
 + }
  
   ErrorF(PCH DPLL disable\n);
   /* disable PCH DPLL */

Re: fix dpms issues on ivy bridge

2013-01-29 Thread Dawe

On Jan 29, 2013 13:34, Jonathan Gray wrote:
 The following changes mostly based on what has happened in
 the upstream drm code seems to resolve problems with screen corruption
 on power saving/dpms on ivy bridge with ums here.  Testing on ironlake/
 sandy bridge/ivy bridge (aka Core i*) to make sure this doesn't break
 anything appreciated.
 
 - remove a workaround which was in itself causing issues
 - switch the order of disabling fdi rx  tx
 - disable DPLL_SEL when disabling the crtc
 - add a few extra delays
 

So far, everything still works on my amd65 ironlake.
Suspend/resume, dpms, switching between consoles, no corruption to be seen.

OpenBSD 5.2-current (GENERIC.MP) #20: Mon Jan 21 17:23:23 MST 2013
t...@amd64.openbsd.org:/usr/src/sys/arch/amd64/compile/GENERIC.MP
real mem = 6225903616 (5937MB)
avail mem = 6037680128 (5757MB)
mainbus0 at root
bios0 at mainbus0: SMBIOS rev. 2.6 @ 0xe0010 (78 entries)
bios0: vendor LENOVO version 6IET68WW (1.28 ) date 07/12/2010
bios0: LENOVO 25184QG
acpi0 at bios0: rev 2
acpi0: sleep states S0 S3 S4 S5
acpi0: tables DSDT FACP SSDT ECDT APIC MCFG HPET ASF! SLIC BOOT SSDT TCPA SSDT
SSDT SSDT
acpi0: wakeup devices LID_(S3) SLPB(S3) UART(S3) IGBE(S4) EXP1(S4) EXP2(S4)
EXP3(S4) EXP4(S4) EXP5(S4) EHC1(S3) EHC2(S3) HDEF(S4)
acpitimer0 at acpi0: 3579545 Hz, 24 bits
acpiec0 at acpi0
acpimadt0 at acpi0 addr 0xfee0: PC-AT compat
cpu0 at mainbus0: apid 0 (boot processor)
cpu0: Intel(R) Core(TM) i5 CPU M 430 @ 2.27GHz, 2527.50 MHz
cpu0:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,SSE4.1,SSE4.2,POPCNT,NXE,LONG,LAHF,PERF,ITSC
cpu0: 256KB 64b/line 8-way L2 cache
cpu0: apic clock running at 133MHz
cpu1 at mainbus0: apid 1 (application processor)
cpu1: Intel(R) Core(TM) i5 CPU M 430 @ 2.27GHz, 2527.00 MHz
cpu1:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,SSE4.1,SSE4.2,POPCNT,NXE,LONG,LAHF,PERF,ITSC
cpu1: 256KB 64b/line 8-way L2 cache
cpu2 at mainbus0: apid 4 (application processor)
cpu2: Intel(R) Core(TM) i5 CPU M 430 @ 2.27GHz, 2527.00 MHz
cpu2:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,SSE4.1,SSE4.2,POPCNT,NXE,LONG,LAHF,PERF,ITSC
cpu2: 256KB 64b/line 8-way L2 cache
cpu3 at mainbus0: apid 5 (application processor)
cpu3: Intel(R) Core(TM) i5 CPU M 430 @ 2.27GHz, 2527.00 MHz
cpu3:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,SSE4.1,SSE4.2,POPCNT,NXE,LONG,LAHF,PERF,ITSC
cpu3: 256KB 64b/line 8-way L2 cache
ioapic0 at mainbus0: apid 1 pa 0xfec0, version 20, 24 pins
ioapic0: misconfigured as apic 2, remapped to apid 1
acpimcfg0 at acpi0 addr 0xe000, bus 0-255
acpihpet0 at acpi0: 14318179 Hz
acpiprt0 at acpi0: bus 0 (PCI0)
acpiprt1 at acpi0: bus -1 (PEG_)
acpiprt2 at acpi0: bus 2 (EXP1)
acpiprt3 at acpi0: bus 3 (EXP2)
acpiprt4 at acpi0: bus -1 (EXP3)
acpiprt5 at acpi0: bus -1 (EXP4)
acpiprt6 at acpi0: bus 13 (EXP5)
acpicpu0 at acpi0: C3, C1, PSS
acpicpu1 at acpi0: C3, C1, PSS
acpicpu2 at acpi0: C3, C1, PSS
acpicpu3 at acpi0: C3, C1, PSS
acpipwrres0 at acpi0: PUBS
acpitz0 at acpi0: critical temperature is 100 degC
acpibtn0 at acpi0: LID_
acpibtn1 at acpi0: SLPB
acpibat0 at acpi0: BAT0 not present
acpibat1 at acpi0: BAT1 not present
acpiac0 at acpi0: AC unit online
acpithinkpad0 at acpi0
cpu0: Enhanced SpeedStep 2527 MHz: speeds: 2267, 2266, 2133, 1999, 1866, 1733,
1599, 1466, 1333, 1199 MHz
pci0 at mainbus0 bus 0
pchb0 at pci0 dev 0 function 0 Intel Core Host rev 0x02
vga1 at pci0 dev 2 function 0 Intel HD Graphics rev 0x02
wsdisplay0 at vga1 mux 1: console (80x25, vt100 emulation)
wsdisplay0: screen 1-5 added (80x25, vt100 emulation)
intagp0 at vga1
agp0 at intagp0: aperture at 0xd000, size 0x1000
inteldrm0 at vga1: apic 1 int 16
drm0 at inteldrm0
Intel 3400 MEI rev 0x06 at pci0 dev 22 function 0 not configured
em0 at pci0 dev 25 function 0 Intel 82577LM rev 0x06: msi, address
00:26:2d:fb:c7:02
ehci0 at pci0 dev 26 function 0 Intel 3400 USB rev 0x06: apic 1 int 23
usb0 at ehci0: USB revision 2.0
uhub0 at usb0 Intel EHCI root hub rev 2.00/1.00 addr 1
azalia0 at pci0 dev 27 function 0 Intel 3400 HD Audio rev 0x06: msi
azalia0: codecs: Conexant/0x5069, Intel/0x2804, using Conexant/0x5069
audio0 at azalia0
ppb0 at pci0 dev 28 function 0 Intel 3400 PCIE rev 0x06: msi
pci1 at ppb0 bus 2
ppb1 at pci0 dev 28 function 1 Intel 3400 PCIE rev 0x06: msi
pci2 at ppb1 bus 3
iwn0 at pci2 dev 0 function 0 Intel WiFi Link 1000 rev 0x00: msi, MIMO 1T2R,
BGS, address 00:26:c7:31:15:06
ppb2 at pci0 dev 28 function 4 Intel 3400 PCIE rev 0x06: msi
pci3 at ppb2 bus

Re: fix dpms issues on ivy bridge

2013-01-29 Thread Brad Smith

On Tue, Jan 29, 2013 at 03:13:17PM +0100, Dawe wrote:
 On Jan 29, 2013 13:34, Jonathan Gray wrote:
  The following changes mostly based on what has happened in
  the upstream drm code seems to resolve problems with screen corruption
  on power saving/dpms on ivy bridge with ums here.  Testing on ironlake/
  sandy bridge/ivy bridge (aka Core i*) to make sure this doesn't break
  anything appreciated.
  
  - remove a workaround which was in itself causing issues
  - switch the order of disabling fdi rx  tx
  - disable DPLL_SEL when disabling the crtc
  - add a few extra delays
  
 
 So far, everything still works on my amd65 ironlake.

You have an amd65 system? :) *jealous*

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fix dpms issues on ivy bridge

2013-01-28 Thread Jonathan Gray

The following changes mostly based on what has happened in
the upstream drm code seems to resolve problems with screen corruption
on power saving/dpms on ivy bridge with ums here.  Testing on ironlake/
sandy bridge/ivy bridge (aka Core i*) to make sure this doesn't break
anything appreciated.

- remove a workaround which was in itself causing issues
- switch the order of disabling fdi rx  tx
- disable DPLL_SEL when disabling the crtc
- add a few extra delays

Index: i830_display.c
===
RCS file: /cvs/xenocara/driver/xf86-video-intel/src/i830_display.c,v
retrieving revision 1.16
diff -u -p -r1.16 i830_display.c
--- i830_display.c  15 Jan 2013 06:31:43 -  1.16
+++ i830_display.c  29 Jan 2013 02:24:21 -
@@ -1535,16 +1535,6 @@ static void ivb_manual_fdi_link_train(xf
INREG(fdi_rx_reg);
 
usleep(150);
-
-   if (HAS_PCH_CPT(intel)) {
-   temp = INREG(SOUTH_CHICKEN1);
-   temp |= FDI_PHASE_SYNC_OVR(pipe);
-   OUTREG(SOUTH_CHICKEN1, temp); /* once to unlock... */
-   temp |= FDI_PHASE_SYNC_EN(pipe);
-   OUTREG(SOUTH_CHICKEN1, temp); /* then again to enable */
-   INREG(SOUTH_CHICKEN1);
-   usleep(150);
-   }

for (i = 0; i  4; i++) {
temp = INREG(fdi_tx_reg);
@@ -1862,11 +1852,6 @@ ironlake_crtc_disable(xf86CrtcPtr crtc)
OUTREG(pf_win_size, 0);
INREG(pf_win_size);
 
-   ErrorF(FDI TX disable\n);
-   temp = INREG(fdi_tx_reg);
-   OUTREG(fdi_tx_reg, temp  ~FDI_TX_ENABLE);
-   INREG(fdi_tx_reg);
-
ErrorF(FDI RX disable\n);
temp = INREG(fdi_rx_reg);
temp = ~(0x07  16);
@@ -1876,14 +1861,13 @@ ironlake_crtc_disable(xf86CrtcPtr crtc)
 
usleep(100);
 
-   ErrorF(FDI TX train 1 preload\n);
-   /* still set train pattern 1 */
+   ErrorF(FDI TX disable\n);
temp = INREG(fdi_tx_reg);
-   temp = ~FDI_LINK_TRAIN_NONE;
-   temp |= FDI_LINK_TRAIN_PATTERN_1;
-   OUTREG(fdi_tx_reg, temp);
+   OUTREG(fdi_tx_reg, temp  ~FDI_TX_ENABLE);
INREG(fdi_tx_reg);
 
+   usleep(100);
+
ErrorF(FDI RX train 1 preload\n);
temp = INREG(fdi_rx_reg);
if (HAS_PCH_CPT(intel)) {
@@ -1898,6 +1882,16 @@ ironlake_crtc_disable(xf86CrtcPtr crtc)
 
usleep(100);
 
+   ErrorF(FDI TX train 1 preload\n);
+   /* still set train pattern 1 */
+   temp = INREG(fdi_tx_reg);
+   temp = ~FDI_LINK_TRAIN_NONE;
+   temp |= FDI_LINK_TRAIN_PATTERN_1;
+   OUTREG(fdi_tx_reg, temp);
+   INREG(fdi_tx_reg);
+
+   usleep(100);
+
if (i830PipeHasType(crtc, I830_OUTPUT_LVDS)) {
ErrorF(LVDS port force off\n);
while ((temp = INREG(PCH_LVDS))  PORT_ENABLE) {
@@ -1933,6 +1927,25 @@ ironlake_crtc_disable(xf86CrtcPtr crtc)
OUTREG(transconf_reg, temp);
INREG(transconf_reg);
usleep(100);
+
+   if (HAS_PCH_CPT(intel)) {
+   /* disable DPLL_SEL */
+   temp = INREG(PCH_DPLL_SEL);
+   switch (pipe) {
+   case 0:
+   temp = ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
+   break;
+   case 1:
+   temp = ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
+   break;
+   case 2:
+   /* C shares PLL A or B */
+   temp = ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
+   break;
+   }
+   OUTREG(PCH_DPLL_SEL, temp);
+   INREG(PCH_DPLL_SEL);
+   }
 
ErrorF(PCH DPLL disable\n);
/* disable PCH DPLL */

Re: fix dpms issues on ivy bridge

Re: fix dpms issues on ivy bridge

Re: fix dpms issues on ivy bridge

fix dpms issues on ivy bridge

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