[time-nuts] Trimble Thunderbolt - Power connector
I wonder if anyone on the list has any power connectors available for the Trimble Thunderbolt that they can spare? I am looking for four of these connectors. They are the 6 way header Molex Part No. 50-57-9406 plus the crimp terminals I have been trying to source these in the UK but the distributors have minimum order levels of 50 and surcharges of $20 for small orders! Many thanks Tracey Lincolnshire UK ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Trimble Thunderbolt - Power connector
I wonder if anyone on the list has any power connectors available for the Trimble Thunderbolt that they can spare? Yes, send me email off-line. /tvb ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] Locking 100 MHz to 10 MHz
I am designing a system where I lock a 100 MHz VCXO to a 10 MHz reference using an AD9510 clock PLL chip. I have two questions to which I don't know the answer: - First, given the specs of both oscillators, I know how to choose the right loop bandwidth. The problem is that I have no idea what kind of 10 MHz oscillators people are going to connect. The 100 MHz osc typical specs for phase noise are: 10Hz -65dBc 100Hz-68dBc 1k -98 10k-140 100k to 100MHz -145 I was thinking of just going with a 1kHz bandwidth, for lack of any better ideas. - Second, for when there is no 10 MHz reference connected, the system needs to be brought to a reasonable frequency. The PLL charge pump outputs are tri-stated. On the end of the loop filter, right before the control voltage input to the VCXO, I have a resistor divider to center the voltage between 3.3V and ground. I use 100K resistors in the hope that they will not affect things when the loop is active, but I can't really tell, since all the phase noises involved are well below the ability of my equipment to measure. Is this a safe technique, or am I messing up the performance while the loop is locked? Thanks, Matt ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] BOULDER SCIENTIFIC 106D DUAL MIXER TIME DIFFERENCE SYSTEM
Bruce, Thanks! The info helps a lot. This unit appears to be an improved later version (1985 or so) of the unit in the PDF. It has two isolation amps that can be cabled in as well as a switch selectable delay line and a coarse and fine vernier phase adjust. The mixers are mini circuits vice vari-L and the filtering at the mixer output is somewhat different. The rest of the electronics conforms with the schematics in the PDF. I powered it up with some inputs and it's outputs are good. Just need to hook it up to my counter and see what happens! Thanks again for the info! Corby Dawson ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] HP 5370B question
Hi, Could a few of the 5370B owners connect the counters reference output to its counting input jack and with a 1 second gate let me know what the last 2 digits are doing? An earlier post implied that the last couple digits will wander around due to the way its designed. I'd like to know what a couple different counters show to see if that is indeed true! Thanks, Corby Dawson ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Locking 100 MHz to 10 MHz
In a message dated 12/19/2007 10:38:54 Pacific Standard Time, [EMAIL PROTECTED] writes: I can't really tell, since all the phase noises involved are well below the ability of my equipment to measure. Is this a safe technique, or am I messing up the performance while the loop is locked? Thanks, Matt Hi Matt, in my opinion, you would probably introduce some thermal noise through this 50KOhm equivalent resistor while the PLL is not operating. Noise could maybe be reduced if there is a cap to ground on this divider (this cap being part of the loop filter). The PLL bandwidth depends solely on the phase noise of your 10MHz source versus your 100MHz oscillator. If the 10MHz source is better at say 100Hz offset (better by more than 20dB) then the loop bandwidth should be more than 100Hz, so that the PLL can actually reduce the phase noise of your 100MHz oscillator. At 100Hz offset, you say you have -68dBc/Hz at 100MHz. This calculates to -88dBc/Hz at 100Hz offset for the 10MHz source (excluding the PLL chip and loop-filter noise). You may want to check the noise performance of the PLL on the ADI website's PLL simulator. So if you have much better than -88dBc/Hz at 100Hz on your 10MHz oscillator (not hard to achieve, many oscillators have -140dBc/Hz at 100Hz already) then you would be wasting performance with a 100Hz loop filter, and you may want to do a 1KHz or even wider loop filter or so. But if you don't know the 10MHz source's performance, it is probably best to be safe and use 10Hz, or 100Hz loop filter BW. A good spectrum analyzer (such as HP 8560B/E etc with the phase-noise software option) should allow you to measure -68dBc/Hz noise at 100Hz offset at 100MHz, so you can check what BW results in the overall lowest noise. In short, if you want to maximize your systems performance, then loop bandwidth depends on the performance of the 10MHz versus the 100MHz oscillator for close-in phase noise. To do the math, subtract 20log(100/10) = -20dB from the noise of the 100MHz oscillator to get the equivalent noise energy for the 10MHz oscillator (at the same frequency offset). Hope this makes sense, bye, Said **See AOL's top rated recipes (http://food.aol.com/top-rated-recipes?NCID=aoltop000304) ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] HP 5370B question
In message [EMAIL PROTECTED], corby d dawson writes: Hi, Could a few of the 5370B owners connect the counters reference output to its counting input jack and with a 1 second gate let me know what the last 2 digits are doing? An earlier post implied that the last couple digits will wander around due to the way its designed. I'd like to know what a couple different counters show to see if that is indeed true! The last couple of digits are not free to assume any possible value since they are the low end of a binary to decimal conversion from the (N/256) vernier counter. -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 [EMAIL PROTECTED] | TCP/IP since RFC 956 FreeBSD committer | BSD since 4.3-tahoe Never attribute to malice what can adequately be explained by incompetence. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.