Re: [time-nuts] REQ: Manuals and Schematics for the Austron 2110
Hello, I have a manual for the 2110 at work, including several fold-out schematics as I recall. I will have time to scan it in a couple of days. Christmas greetings from Norway! - Harald P.S. I have been a long time lurker on the time-nuts list, but I believe this is my first useful contribution :-) -Opprinnelig melding- Fra: John C. Westmoreland, P.E. [mailto:j...@westmorelandengineering.com] Sendt: 29. desember 2013 04:01 Til: Discussion of precise time and frequency measurement Emne: [time-nuts] REQ: Manuals and Schematics for the Austron 2110 Hello All, Does someone in the group have the manuals and schematics for the Austron 2110 - microprocessor controlled disciplined frequency standard? A lot of the Austron manuals are on the 'net - but I cannot find the one for the 2110 (yet). Thanks In Advance! John W. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] REQ: Manuals and Schematics for the Austron 2110
Hello Harald, Appreciate this very much. I hope to return the favor some day. Happy Holidays and 73's, John W. AJ6BC On Mon, Dec 30, 2013 at 12:12 AM, Harald Hauglin h...@justervesenet.nowrote: Hello, I have a manual for the 2110 at work, including several fold-out schematics as I recall. I will have time to scan it in a couple of days. Christmas greetings from Norway! - Harald P.S. I have been a long time lurker on the time-nuts list, but I believe this is my first useful contribution :-) -Opprinnelig melding- Fra: John C. Westmoreland, P.E. [mailto:j...@westmorelandengineering.com] Sendt: 29. desember 2013 04:01 Til: Discussion of precise time and frequency measurement Emne: [time-nuts] REQ: Manuals and Schematics for the Austron 2110 Hello All, Does someone in the group have the manuals and schematics for the Austron 2110 - microprocessor controlled disciplined frequency standard? A lot of the Austron manuals are on the 'net - but I cannot find the one for the 2110 (yet). Thanks In Advance! John W. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] sysclock source for AD9912 DDS?
I've tested the AD9912 evaluation board: http://www.anderswallin.net/wp-content/uploads/2013/12/dds_test_2013-12-30.png I want to use it with a 10MHz external input clock, but it looks like the on-board PLL that generates a 1200MHz sample clock from my input isn't that great, since I get strong side-bands on the output that are only 18-20 dB down from the fundamental. So it looks like I need to supply a clean 800-1000MHz clock to the DDS to get a clean output. Any ideas/suggestions for generating this from a 10 MHz sine? Driving the DDS system clock from an expensive RF generator (e.g. HP 8648A) would be possible but I'd prefer a PLL from 10MHz if it's doable simply/cheaply. Anders ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] sysclock source for AD9912 DDS?
On 12/30/13 7:56 AM, Anders Wallin wrote: I've tested the AD9912 evaluation board: http://www.anderswallin.net/wp-content/uploads/2013/12/dds_test_2013-12-30.png I want to use it with a 10MHz external input clock, but it looks like the on-board PLL that generates a 1200MHz sample clock from my input isn't that great, since I get strong side-bands on the output that are only 18-20 dB down from the fundamental. So it looks like I need to supply a clean 800-1000MHz clock to the DDS to get a clean output. Any ideas/suggestions for generating this from a 10 MHz sine? Driving the DDS system clock from an expensive RF generator (e.g. HP 8648A) would be possible but I'd prefer a PLL from 10MHz if it's doable simply/cheaply. Most of the time, they're expecting you to filter the output of the DDS to remove the spurs. Probably not a PLL, at least not one of the generic PLL chips, because you'll get spurs and sidebands from the comparison frequency in the loop, and they'll be fairly close in. You have two basic alternatives.. a PLL using a divider from your 1 GHz and using the 10 MHz as the comparison frequency, and then good filtering to get rid of the 10 MHz spurs. A bit challenging since that's a 1% bandwidth filter. (maybe you could do that with the onchip reference generator, and feed it back in) Or, You want a straight out multiplier chain with appropriate filtering in between stages. Maybe a x7, followed by 70MHz BPF (which should be readily available), then another x7 to 490 MHz, then a x2 or x3. Or end with a x5 (to 350 MHz) and a x3 to 1050. A sort of hybrid approach might also work.. take your 10 and make 100MHz(x5 x2) with it, then feed that into your DDS. That will put the spurs 100 MHz away, which is a lot easier to filter than spurs that are 10 MHz away. I'm pretty sure Wenzel has some application notes on this. When you say clean, how clean do you need it? What sort of tuning range are you going to run the DDS over? (maybe some of the spurs will wind up in places you don't care about and can filter out) ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] sysclock source for AD9912 DDS?
My lab has had good luck with the ADF4350 eval boards as clock generators. The snippet description on the analog devices website of them is incorrect though, they can accept a 10 MHz clock ref. The datasheet is definitely more accurate than the description. -Ben On Mon, Dec 30, 2013 at 9:36 AM, Jim Lux jim...@earthlink.net wrote: On 12/30/13 7:56 AM, Anders Wallin wrote: I've tested the AD9912 evaluation board: http://www.anderswallin.net/wp-content/uploads/2013/12/ dds_test_2013-12-30.png I want to use it with a 10MHz external input clock, but it looks like the on-board PLL that generates a 1200MHz sample clock from my input isn't that great, since I get strong side-bands on the output that are only 18-20 dB down from the fundamental. So it looks like I need to supply a clean 800-1000MHz clock to the DDS to get a clean output. Any ideas/suggestions for generating this from a 10 MHz sine? Driving the DDS system clock from an expensive RF generator (e.g. HP 8648A) would be possible but I'd prefer a PLL from 10MHz if it's doable simply/cheaply. Most of the time, they're expecting you to filter the output of the DDS to remove the spurs. Probably not a PLL, at least not one of the generic PLL chips, because you'll get spurs and sidebands from the comparison frequency in the loop, and they'll be fairly close in. You have two basic alternatives.. a PLL using a divider from your 1 GHz and using the 10 MHz as the comparison frequency, and then good filtering to get rid of the 10 MHz spurs. A bit challenging since that's a 1% bandwidth filter. (maybe you could do that with the onchip reference generator, and feed it back in) Or, You want a straight out multiplier chain with appropriate filtering in between stages. Maybe a x7, followed by 70MHz BPF (which should be readily available), then another x7 to 490 MHz, then a x2 or x3. Or end with a x5 (to 350 MHz) and a x3 to 1050. A sort of hybrid approach might also work.. take your 10 and make 100MHz(x5 x2) with it, then feed that into your DDS. That will put the spurs 100 MHz away, which is a lot easier to filter than spurs that are 10 MHz away. I'm pretty sure Wenzel has some application notes on this. When you say clean, how clean do you need it? What sort of tuning range are you going to run the DDS over? (maybe some of the spurs will wind up in places you don't care about and can filter out) ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/ mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] sysclock source for AD9912 DDS?
Anders, I used an AD9858 years ago in our FireFox synthesizer product clocked at 1GHz locked to the on-board 10MHz GPSDO. I used an ADF4002 or 4000 (can't remember) pll with integer division driving a UMC (now Sirenza) VCO. It worked very well and there where no 10MHz spurs measurable. Its very easy to get rid of reference feedthrough by using a good low pass filter on the EFC input and proper layout technique. I used a 5KHz bandwidth or so. The Analog Devices PLL simulator tool makes it a breeze to design the loop filter and predict output performance. Choosing a VCO with limited modulation BW also helps keep the reference away from the output. You can even select VCOs from a list of programmed parts in the AD software. Today I would not use a simple (cheap) 1GHz VCO anymore because of the relatively high phase noise, and some if them require up to 20V drive voltage. I would use a Crystal based product such as our ULN-1G 1GHz crystal oscillator. That part may be overkill since it has DC-DC regulators, filters, mil-temp range, and a +22dBm temp-stabilized output amplifier, but its a drop-in replacement for a VCO. With that part, the loop filter bandwidth can be reduced to a couple 100Hz to take advantage of the very low PN of the oscillator. If price is an issue, and you just need a one-off then you can build your own 1GHz crystal VCXO: Use a third harmonic crystal to run a single transistor oscillator at 125MHz (or buy a 125MHz low-noise oscillator). A third harmonic crystal will allow a wider frequency control range than a fifth harmonic, which may be needed to compensate aging and temp effects on the crystal.Then multiply by four using a simple RC resonant circuit in a common emitter driver. Follow this by another driver to get +10dBm or so. Then use a diode doubler (Mini Circuits etc) to get 1GHz output, and buffer that output with an RF transistor, or an LVDS driver chip etc. you may want to follow that with a mini circuits 1200MHz low pass filter to get rid of any residual 1500MHz f3 spurs. But depending on your needs a passive, five or six component LP filter driven by an ADF400x and a standard 1GHz VCO may just do the trick. You should be able to get an ADF400x eval board cheaply and swap out the VCO to a 1GHz unit from Ebay and program the board using a PC or micro-controller. Caveat Emptor: I tried other PLL vendors, and they were not as good as Analog. Also stay away from fractional-n PLLs for phase noise and spurs. Voila. Bye, Said Sent From iPhone On Dec 30, 2013, at 9:56, Anders Wallin anders.e.e.wal...@gmail.com wrote: I've tested the AD9912 evaluation board: http://www.anderswallin.net/wp-content/uploads/2013/12/dds_test_2013-12-30.png I want to use it with a 10MHz external input clock, but it looks like the on-board PLL that generates a 1200MHz sample clock from my input isn't that great, since I get strong side-bands on the output that are only 18-20 dB down from the fundamental. So it looks like I need to supply a clean 800-1000MHz clock to the DDS to get a clean output. Any ideas/suggestions for generating this from a 10 MHz sine? Driving the DDS system clock from an expensive RF generator (e.g. HP 8648A) would be possible but I'd prefer a PLL from 10MHz if it's doable simply/cheaply. Anders ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] sysclock source for AD9912 DDS?
Am 30.12.2013 16:56, schrieb Anders Wallin: I've tested the AD9912 evaluation board: http://www.anderswallin.net/wp-content/uploads/2013/12/dds_test_2013-12-30.png I want to use it with a 10MHz external input clock, but it looks like the on-board PLL that generates a 1200MHz sample clock from my input isn't that great, since I get strong side-bands on the output that are only 18-20 dB down from the fundamental. So it looks like I need to supply a clean 800-1000MHz clock to the DDS to get a clean output. Any ideas/suggestions for generating this from a 10 MHz sine? Driving the DDS system clock from an expensive RF generator (e.g. HP 8648A) would be possible but I'd prefer a PLL from 10MHz if it's doable simply/cheaply. I'm planning to do something similar as a ADC sample clock. (and an offset generator) Over Xmas, I got as far as locking a MTI-260 to my house reference, giving clean 10 MHz + distrib amp . Next step will be locking a 100 MHz VCXO to the 10 MHz, it's less ado than multiplying and filtering. This will be a Pascall in the long run or sth. homebrew. For now, I'll try a Crystek CVHD-950. Close-in noise will be governed by the MTI-260 anyway. 2 doublers with absolutely minimum filtering on 200 MHz and then 2 SAW-Filters on 400 MHz against 100, 200, 300, 500, 600, 700... MHz http://www.digikey.de/product-search/de?pv7=2k=495-3923-1-ndmnonly=0newproducts=0ColumnSort=0page=1quantity=0ptm=0fid=0pageSize=25 http://media.digikey.com/pdf/Data%20Sheets/Epcos%20PDFs/B3742.pdf They are €1,90 @ 1. Finally, a doubler or tripler to 800 or 1200 MHz. Sub/harmonics are now far away and easily removed. The SAW filters would also do most of the filtering work when I multiplied directly *2 *5 from 10 to 100 MHz. Finally, a few days to build sth. interesting!!! :-) regards, Gerhard ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] sysclock source for AD9912 DDS?
Try to look on these designs made by me http://rudius.net/oz2m/ngnb/vcopll.htm Michael -Oprindelig meddelelse- Fra: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] På vegne af Anders Wallin Sendt: 30. december 2013 16:56 Til: Discussion of precise time and frequency measurement Emne: [time-nuts] sysclock source for AD9912 DDS? I've tested the AD9912 evaluation board: http://www.anderswallin.net/wp-content/uploads/2013/12/dds_test_2013-12-30.p ng I want to use it with a 10MHz external input clock, but it looks like the on-board PLL that generates a 1200MHz sample clock from my input isn't that great, since I get strong side-bands on the output that are only 18-20 dB down from the fundamental. So it looks like I need to supply a clean 800-1000MHz clock to the DDS to get a clean output. Any ideas/suggestions for generating this from a 10 MHz sine? Driving the DDS system clock from an expensive RF generator (e.g. HP 8648A) would be possible but I'd prefer a PLL from 10MHz if it's doable simply/cheaply. Anders ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] Fwd: sysclock source for AD9912 DDS?
Look up PA3AKE, he built a 1 GHz source clock, Martein also provides a substantial amount of research data. Good luck for the new year. Gerald VK3GJM Sent while out and about Begin forwarded message: From: Anders Wallin anders.e.e.wal...@gmail.commailto:anders.e.e.wal...@gmail.com Date: 31 December 2013 2:56:03 AEDT To: Discussion of precise time and frequency measurement time-nuts@febo.commailto:time-nuts@febo.com Subject: [time-nuts] sysclock source for AD9912 DDS? Reply-To: Discussion of precise time and frequency measurement time-nuts@febo.commailto:time-nuts@febo.com I've tested the AD9912 evaluation board: http://www.anderswallin.net/wp-content/uploads/2013/12/dds_test_2013-12-30.png I want to use it with a 10MHz external input clock, but it looks like the on-board PLL that generates a 1200MHz sample clock from my input isn't that great, since I get strong side-bands on the output that are only 18-20 dB down from the fundamental. So it looks like I need to supply a clean 800-1000MHz clock to the DDS to get a clean output. Any ideas/suggestions for generating this from a 10 MHz sine? Driving the DDS system clock from an expensive RF generator (e.g. HP 8648A) would be possible but I'd prefer a PLL from 10MHz if it's doable simply/cheaply. Anders ___ time-nuts mailing list -- time-nuts@febo.commailto:time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. -- Message protected by MailGuard: e-mail anti-virus, anti-spam and content filtering.http://www.mailguard.com.au/mg ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] sysclock source for AD9912 DDS?
Anders I've used the AD9912 Eval board with great success - spurs with the on-chip clock multiplier were -60dBc, IIRC, maybe better. My guess is that you are pushing the on-chip VCO too high - do you really need a 1200MHz system clock? The AD9912 is only specified for a sys. clock of 1000MHz, and the on-chip VCO is also only specified to 1000MHz - yes, I know that the Eval software allows other values, but the VCO actually has quite a narrow frequency range (10%) in order to improve phase noise, and uses switchable on-chip inductors to select the correct output frequency range, the highest being 900-1000MHz. I'd be surprised if it locks at 1200MHz. First thing is to try a 1000MHz clock. regards Grant Hodgson From: Anders Wallin anders.e.e.wal...@gmail.com To: Discussion of precise time and frequency measurement time-nuts@febo.com Subject: [time-nuts] sysclock source for AD9912 DDS? I've tested the AD9912 evaluation board: http://www.anderswallin.net/wp-content/uploads/2013/12/dds_test_2013-12-30.png I want to use it with a 10MHz external input clock, but it looks like the on-board PLL that generates a 1200MHz sample clock from my input isn't that great, since I get strong side-bands on the output that are only 18-20 dB down from the fundamental. So it looks like I need to supply a clean 800-1000MHz clock to the DDS to get a clean output. Any ideas/suggestions for generating this from a 10 MHz sine? Driving the DDS system clock from an expensive RF generator (e.g. HP 8648A) would be possible but I'd prefer a PLL from 10MHz if it's doable simply/cheaply. Anders ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] sysclock source for AD9912 DDS?
From: Said Jackson Today I would not use a simple (cheap) 1GHz VCO anymore because of the relatively high phase noise, and some if them require up to 20V drive voltage. I would use a Crystal based product such as our ULN-1G 1GHz crystal oscillator. That part may be overkill since it has DC-DC regulators, filters, mil-temp range, and a +22dBm temp-stabilized output amplifier, but its a drop-in replacement for a VCO. With that part, the loop filter bandwidth can be reduced to a couple 100Hz to take advantage of the very low PN of the oscillator. Said, can you give the url for your ULN-1G 1GHz crystal oscillator? I'm interested in price and phase noise and how it compares to the Wenzel products. Thanks, Mike ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] REQ: Manuals and Schematics for the Austron 2010B
Hello time-nuts, Another request - does someone in the group have the manuals and schematics for the Austron 2010B - disciplined frequency standard? Thanks and Happy New Year! John Westmoreland ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] sysclock source for AD9912 DDS?
Hi Anders, Have a look at my AD9910 quadrature DDS http://members.wideband.net.au/gzimmer/QuadDDS/default.html I used a Crystek 1GHz SAW oscillator regards Zim ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] From Burt - K6OQK...
Gang, Best wishes to all for good health and much contentment in the New Year. Burt Margaret Burt I. Weiner Associates Broadcast Technical Services Glendale, California U.S.A. b...@att.net www.biwa.cc K6OQK ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] sysclock source for AD9912 DDS?
Thanks for all replies so far! It looks like I will play around with the evaluation board some more, and see if I can get the on-chip PLL to behave better. The settings with 2x edge-detector and 60x PLL were the only ones I could find where the output frequency setting in the software corresponded to the actual output frequency - hence I tested only with 10MHz x120 = 1200 MHz sysclock. I have asked about this on the AD forum, but no replies yet. If that doesn't work the suggested ADF4351 (or similar) evaluation board looks like the most straightforward option. thanks, Anders ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
