Re: [time-nuts] WWV/WWVH audio simulator?

[Hal Murray]

> No, that's not it. It's a design-by-committee thing. As I recall it, the
> Europeans wanted a 32 byte payload, as then you throw in a 32-byte E1 into
> it, but this was judged to small for datacom which the North American side
> wanted, that wanted a 64 byte payload. 

Thanks.  I hadn't heard the E1 idea before.

The story that I remember was that 32 bytes was small enough so that they 
wouldn't need echo canceling.  The Wiki page on ATM says "With 32 bytes, 
France would have been able to implement an ATM-based voice network with 
calls from one end of France to the other requiring no echo cancellation."

--

> That is only the start of the trouble. The real troubles was that they
> designed really stupid leaky-bucket algorithms amongst other things.

I think the real problem was much bigger than that.  There was a mind-set 
collision between the phone company people and the networking people.  
Phone/voice people assume traffic uses a constant bit rate.  (They do play 
statistical games like taking advantage of silence on expensive 
trans-Atlantiic links.)  Networking traffic is bursty.  Not only does a 
packet turn into a burst of cells, but packets often come in clusters.  The 
voice market didn't need much buffering.  Back in those days, buffering was 
expensive, or at least though to be expensive.  So the phone companies bought 
switches without much buffering and then expected the networking guys to act 
like voice circuits.  Basically, networking over ATM was a disaster as soon 
as they tried it.



This is probably getting off topic for time-nuts.


-- 
These are my opinions.  I hate spam.



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[time-nuts] WWV/WWVH audio simulator

[Brian Garrett]

Jayson Smith wrote:

Anyway, I'd love to find a program for Windows that simulates the audio 
from WWV as closely as possible. I know someone on this list talked 
about having written such a beast, although I don't know if it'd run on 
Windows, back in 2010. I also wish WWV streamed on the net. Don't get me 
wrong, I know why they don't, but I still think a crisp, clear, direct 
from the sound source feed would be cool. Any thoughts?
Jayson
If audio rather than accuracy s what your looking fore, what about Skype or 
something similar?  Not sure how good the sound quality is to the discerning 
ear, but you would at least save on long-distance charges to Colorado, plus you 
could dial time services internationally for no more than the cost of the 
subscription charge.  I used to dial France’s 3699 service quite oftentill 
Orange Telecom took it over & made it unavailable outside France & its 
territories. (Amazing lack of latency, by the way.  You could try recording WWV 
together with the overseas signal and checking the delays.  I found them to be 
better than time.gov, most days. Brian Garrett   
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Re: [time-nuts] Motorola GPS antenna type GCNT20A3A

[Graeme Zimmer]

>On 12/12/2013 10:57 AM, Russ Ramirez wrote:
> FYI, in case anyone should be interested. $20

> http://www.goldmine-elec-products.com/prodinfo.asp?number=G19738
> Motorola GCNT20A3A +25db Antenna.

For what it's worth, I purchased one of these and it eventually arrived 
after a rather round-about trip.


I hooked it up just now and it does seem to work, but signals are 
definitely not as strong as my Nokia 470290a-101 +20db Antenna,

however it is sited in a poorer location and with a longer piece of coax.

So although they are an "Engineering Sample", they do seem to work.
Eventually I'm mount it higher up and give it a fairer test.

later  Zim



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[time-nuts] Defective High Performance Crystal Oscillators

[Mike M]

I'm interested  in  obtaining your defective  high  performance crystal
oscillators. By defective, I mean

01. no oscillation
02. wrong frequency
03. parastic or spurious oscillations
04. low output
05. distorted output
06. frequency jumps
07. poor or no temperature control
08. unstable frequency
09. frequency drift
10. frequency trim out of range
11. intermittent
12. poor or excessive phase noise
13. rattles when shaken

or any  other  problem  not listed above. I  plan  to  do  a failure
analysis and  try  to  understand what caused  the  problem  and how
frequent it is. I plan to post the results for everyone to review.

I'll be  happy  to pay shipping cost and  some  nominal  fee. Please
contact me offline and let me know the make and model,  what's wrong
with the device(s), and the estimated shipping cost. Least expensive
method is preferred.

This is  a long-term project. I plan to build a  history  of failure
modes across  a  broad range of products so  we  can  understand the
reliability issues better.

Thanks,

Mike Monett
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Re: [time-nuts] WWV/WWVH audio simulator?

[Magnus Danielson]

On 07/01/14 05:53, Tom Minnis wrote:

I believe the Western Electric D1 channel bank was the first and the
European standard came along later.  Then came the D2, the D3 and
finally the D4 when integrated codecs finally came to be and it was
practical to get rid of the common codec and do it channel by channel. I
have tried to look at the spectrum of AM broadcast radio when they are
taking phone calls and you can defiantly see the low frequency roll off
starting around 300Hz for the guy on the phone and when the guy at the
station talks, there are strong components below 100Hz.


First came the TDM replacements of FDM trunks, first system I know of is 
from 1953 and predates the Western Electric D1 channel bank by 9 years. 
It was only when TDM switching was introduced that things started 
coordination and standardisation, as the TDM trunks could be 
incompatible as the interconnect was done in analog signals.


Cheers,
Magnus

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Re: [time-nuts] WWV/WWVH audio simulator?

[Magnus Danielson]

Jim,

On 07/01/14 05:43, Jim Lux wrote:

On 1/6/14 8:36 PM, Magnus Danielson wrote:

Bob,

It works the other way around. The standard Bell handset (103A I believe
the designation was) has the 300-3400 Hz response, and with not so fancy
analogue filtering, you can handle 4 kHz and thus 8 kHz sampling rate.
The ITU-T G.711 A-law (where naturally the americans wanted their own,
so u-law appeared) does non-linear pseudo-dynamic compression into 8
bits. T1s cram 24 channels into one frame, and adding 1 bit for framing,
giving 24*8+1=193 bits per frame, giving the 1544 kb/s rate. 193 being a
prime have caused a bit of headache over the years. In Europe, cramming
30 channels into a bundle was preferred, and allowing 2 bytes for
framing and signalling. In T1, you do signalling by bit-stealing every
6th LSB on a channel. Caused some grey hairs for modem designers back in
the day, and followed along over into the ISDN, as the primary rates was
over E1 and T1. T1 also had three different line-encodings, of which
only one was really transparent to all binary combinations.

Oh the joy of early digital telephony. Many lessons where hard to learn.
Synchronization was only one of them.


Don't forget the length of ATM cells.. 53 bytes.. because of how big
France is.


No, that's not it. It's a design-by-committee thing. As I recall it, the 
Europeans wanted a 32 byte payload, as then you throw in a 32-byte E1 
into it, but this was judged to small for datacom which the North 
American side wanted, that wanted a 64 byte payload. Since no agreement 
could be done, they went half-way and made it 48 bytes payload, so both 
would be equally annoyed. Toss a 5 byte header that people where 
agreeing on and we have the lovely 53 byte (prime number again!) ATM 
cell size.


That is only the start of the trouble. The real troubles was that they 
designed really stupid leaky-bucket algorithms amongst other things. The 
leaky bucket algorithms I saw didn't have a very smooth rate behaviour 
at higher speeds. When I set up a channel over the pan-European ATM 
pilot using G3-signaling (Group 3 fax signalling that is, first 
signalling protocol of ATM), I also discovered that each operator had 
their own definition of what made up 1 Mb/s of ATM stream, so I got the 
lowest rate along the line... we had ordered 24 Mb/s, so it was more an 
interesting experience than failure.


They also ended up being forced to do the synchronization as in the 
PDH/SDH, so they just used the same to get the traffic shaping decent. 
Magic how the history re-occurs as we see the same occurring again with 
MPLS (being viewed as the ATM again but let's not call it that and lets 
make the cells... eh... packets longer, I keep referring to it as 
tag-switching).


Synchronous Ethernet and Telecom profile PTP continues the PDH/SDH 
synchronization tradition.


Cheers,
Magnus
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Re: [time-nuts] sand9 TCMO

[Magnus Danielson]

On 06/01/14 20:13, Attila Kinali wrote:

On Mon, 06 Jan 2014 06:24:18 -0800
Jim Lux  wrote:


MEMS might be good for certain tasks, but for closer in noise I've only
seen some progress recently, but not measured it myself. Close-in noise
seems to have been pretty bad for all MEMS so far.



I think that's probably related to the physically small size. It's hard
to get a high Q in something that's smaller than a gnat's eyelash.


It's not only the Q (although i have not seen any Q values yet), but
also that (almost?) all of those MEMS oscillators have a fixed frequency
oscillator structure and use a fractional-N PLL together with a standard
CMOS VCO. The spurs of the PLL are clearly visible if you go down to 1kHz
(i haven't seen any spectrums going further down than 1kHz for MEMS 
oscillators).


Well, you want to make sure you do not have multiple resonant modes 
oscillating at the same time. The Q of each of those modes will 
naturally be of interest. In quartz oscillators you kill of nearby modes 
to avoid oscillating in modes with unwanted behaviour, such as high TC 
dependence. You can modify the oscillator circuit of 10811A in order to 
have it oscillate in a more temperature dependent mode, as it helps to 
identify the stability of the oven. MEMS is just another acoustical 
resonator, but implemented in silicon rather than silicon dioxide.


Q values of 75000 mentioned in this little article, which is early in 
the MEMS oscillator industrialization:

http://www.memsjournal.com/2006/02/timing_with_mem.html

This is a good read:
http://www.ifcs-eftf2011.org/sites/ifcs-eftf2011.org/files/editor-files/Slides_Piazza.pdf
Notice that on page 46 there is a phase-noise plot with close-in noise 
down to 10 Hz shown.



The big promise of MEMS oscillators of having very low power consumption
is not fullfiled yet. About half a year ago i checked all the 32kHz
MEMS oscillators i could find and got numbers for power consumption that
were about the same as an MSP430 would use, with its 32kHz crystal
oscillator running.


I think their main advantage is size rather than power-consumption. 
Turns out that low power-consumption comes at a performance reduction, 
that have never happen before :)
I've noticed that there now seems to be a split, depending on what needs 
there is.


For good performance, I still want a good crystal, for many auxillary 
oscillators MEMS can be useful, or locked to a good crystal.


Cheers,
Magnus
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Re: [time-nuts] WWV/WWVH audio simulator?

[Tom Minnis]

I believe the Western Electric D1 channel bank was the first and the 
European standard came along later.  Then came the D2, the D3 and 
finally the D4 when integrated codecs finally came to be and it was 
practical to get rid of the common codec and do it channel by channel.  
I have tried to look at the spectrum of AM broadcast radio when they are 
taking phone calls and you can defiantly see the low frequency roll off 
starting around 300Hz for the guy on the phone and when the guy at the 
station talks, there are strong components below 100Hz.


On 1/6/2014 8:36 PM, Magnus Danielson wrote:

Bob,

It works the other way around. The standard Bell handset (103A I 
believe the designation was) has the 300-3400 Hz response, and with 
not so fancy analogue filtering, you can handle 4 kHz and thus 8 kHz 
sampling rate. The ITU-T G.711 A-law (where naturally the americans 
wanted their own, so u-law appeared) does non-linear pseudo-dynamic 
compression into 8 bits. T1s cram 24 channels into one frame, and 
adding 1 bit for framing, giving 24*8+1=193 bits per frame, giving the 
1544 kb/s rate. 193 being a prime have caused a bit of headache over 
the years. In Europe, cramming 30 channels into a bundle was 
preferred, and allowing 2 bytes for framing and signalling. In T1, you 
do signalling by bit-stealing every 6th LSB on a channel. Caused some 
grey hairs for modem designers back in the day, and followed along 
over into the ISDN, as the primary rates was over E1 and T1. T1 also 
had three different line-encodings, of which only one was really 
transparent to all binary combinations.


Oh the joy of early digital telephony. Many lessons where hard to learn.
Synchronization was only one of them.

Cheers,
Magnus

On 05/01/14 20:33, Robert LaJeunesse wrote:
The US POTS is digitized at 8KHz sample rate, so Nyquist says the 
highest frequency you can accurately digitize is 4KHz. Allow some for 
a (fancy digital) filter and 3400Hz is about the best you can expect. 
As for T1, almost right. The 8K samples per second are u-law 
processed to 8 bits each for transmission down the line, at 1.544 
Mb/s a T1 line handles 24 streams, plus 8K bits per second of 
supervisory data. Yes, a nice round 193 bits per frame.


Bob LaJeunesse





From: DaveH 
To: 'Discussion of precise time and frequency measurement' 


Sent: Sunday, January 5, 2014 1:53 PM
Subject: Re: [time-nuts] WWV/WWVH audio simulator?


This is by design

The POTS (Plain Old Telephone System) specifies a bandwidth of 300Hz to
3,400Hz.

http://en.wikipedia.org/wiki/Plain_old_telephone_service

They are trying to cram as many channels into as little bandwidth as
possible and the greater the frequency response they provide, the more
bandwidth it takkes and the fewer channels they can provide.

T1 lines were originally developed to bring 16 voice channels into a
building that didn't have enough copper circuits.

Dave


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Re: [time-nuts] WWV/WWVH audio simulator?

[Jim Lux]

On 1/6/14 8:36 PM, Magnus Danielson wrote:

Bob,

It works the other way around. The standard Bell handset (103A I believe
the designation was) has the 300-3400 Hz response, and with not so fancy
analogue filtering, you can handle 4 kHz and thus 8 kHz sampling rate.
The ITU-T G.711 A-law (where naturally the americans wanted their own,
so u-law appeared) does non-linear pseudo-dynamic compression into 8
bits. T1s cram 24 channels into one frame, and adding 1 bit for framing,
giving 24*8+1=193 bits per frame, giving the 1544 kb/s rate. 193 being a
prime have caused a bit of headache over the years. In Europe, cramming
30 channels into a bundle was preferred, and allowing 2 bytes for
framing and signalling. In T1, you do signalling by bit-stealing every
6th LSB on a channel. Caused some grey hairs for modem designers back in
the day, and followed along over into the ISDN, as the primary rates was
over E1 and T1. T1 also had three different line-encodings, of which
only one was really transparent to all binary combinations.

Oh the joy of early digital telephony. Many lessons where hard to learn.
Synchronization was only one of them.


Don't forget the length of ATM cells.. 53 bytes.. because of how big 
France is.



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Re: [time-nuts] WWV/WWVH audio simulator?

[Magnus Danielson]

Bob,

It works the other way around. The standard Bell handset (103A I believe 
the designation was) has the 300-3400 Hz response, and with not so fancy 
analogue filtering, you can handle 4 kHz and thus 8 kHz sampling rate. 
The ITU-T G.711 A-law (where naturally the americans wanted their own, 
so u-law appeared) does non-linear pseudo-dynamic compression into 8 
bits. T1s cram 24 channels into one frame, and adding 1 bit for framing, 
giving 24*8+1=193 bits per frame, giving the 1544 kb/s rate. 193 being a 
prime have caused a bit of headache over the years. In Europe, cramming 
30 channels into a bundle was preferred, and allowing 2 bytes for 
framing and signalling. In T1, you do signalling by bit-stealing every 
6th LSB on a channel. Caused some grey hairs for modem designers back in 
the day, and followed along over into the ISDN, as the primary rates was 
over E1 and T1. T1 also had three different line-encodings, of which 
only one was really transparent to all binary combinations.


Oh the joy of early digital telephony. Many lessons where hard to learn.
Synchronization was only one of them.

Cheers,
Magnus

On 05/01/14 20:33, Robert LaJeunesse wrote:

The US POTS is digitized at 8KHz sample rate, so Nyquist says the highest 
frequency you can accurately digitize is 4KHz. Allow some for a (fancy digital) 
filter and 3400Hz is about the best you can expect. As for T1, almost right. 
The 8K samples per second are u-law processed to 8 bits each for transmission 
down the line, at 1.544 Mb/s a T1 line handles 24 streams, plus 8K bits per 
second of supervisory data. Yes, a nice round 193 bits per frame.

Bob LaJeunesse





From: DaveH 
To: 'Discussion of precise time and frequency measurement' 
Sent: Sunday, January 5, 2014 1:53 PM
Subject: Re: [time-nuts] WWV/WWVH audio simulator?


This is by design

The POTS (Plain Old Telephone System) specifies a bandwidth of 300Hz to
3,400Hz.

http://en.wikipedia.org/wiki/Plain_old_telephone_service

They are trying to cram as many channels into as little bandwidth as
possible and the greater the frequency response they provide, the more
bandwidth it takkes and the fewer channels they can provide.

T1 lines were originally developed to bring 16 voice channels into a
building that didn't have enough copper circuits.

Dave


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Re: [time-nuts] 'CPLDs for clock dividers' Thread

[Bob Camp]

Hi

The other reasonable question that may be asked is - at what offset from 
carrier?

I’d expect the floor to cut in by 10 KHz offset. The numbers at 1KHz might be 6 
db worse than the floor. Past that depends a *lot* on how fast the edges are on 
your drive signal. If all goes well, you could be at -145 dbc at 100 Hz offset. 
You could be 10 or 20 db worse. 

Bob
 
On Jan 6, 2014, at 6:07 PM, Bob Camp  wrote:

> Hi
> 
> You can get into the -154.9 dbc / square root hertz to -164.9 dbc / square 
> root hertz 
> 
> Since we’re talking about phase noise I assumed the units were the ones 
> normally used. Typing all the square root hertz stuff takes a while. 
> 
> It’s been a while since I’ve seen phase noise dimensioned in eggs ….
> 
> Bob
> 
> On Jan 6, 2014, at 12:45 PM, Ulrich Bangert  wrote:
> 
>> Bob,
>> 
>> I appreciate your postings a lot but can you please explain what property
>> you are referring to with a sentence like
>> 
>>> you can get into the high 150’s to low 160’s on a 10 MHz
>> 
>> Using numbers without units (maybe: quail eggs per sqare inch ?) makes it
>> difficult to understand what you are going to say even for experienced time
>> nutters.
>> 
>> Brent,
>> 
>>> Precious little to add to this, just to confirm that 
>>> back in another life at Watkins Johnson (early 90's), 
>>> we used CPLD's for low phase noise dividers all the time.  
>>> My work at the time was focused on everything but the divider.
>> 
>> Ok, but how much different input signals did you have for one CPLD? If your
>> answer is "1" then you have given youself the explanation why they worked
>> ok.
>> 
>> Best regards
>> Ulrich
>> 
>>> -Ursprüngliche Nachricht-
>>> Von: time-nuts-boun...@febo.com 
>>> [mailto:time-nuts-boun...@febo.com] Im Auftrag von Bob Camp
>>> Gesendet: Montag, 6. Januar 2014 13:28
>>> An: Discussion of precise time and frequency measurement
>>> Betreff: Re: [time-nuts] 'CPLDs for clock dividers' Thread
>>> 
>>> 
>>> Hi
>>> 
>>> If you disable all the internal clocks (normally fairly easy) 
>>> and your supply is clean and it’s a modern high speed part, 
>>> you can get into the high 150’s to low 160’s on a 10 MHz 
>>> output with a CPLD. 
>>> 
>>> If you have one of those wonderful old designs where the 
>>> charge pump clocks (or what ever) stay on all the time, you 
>>> will be in the 120’s to 130’s. 
>>> 
>>> Bob
>>> 
>>> On Jan 5, 2014, at 9:11 PM, John C. Westmoreland, P.E. 
>>>  wrote:
>>> 
 Hello All,
 
 I was looking at the archives - what was the outcome of this:
 
 Thanks to everyone for their advice.  I bought a CoolRunner II 
 development board (only $39!) and will let you know how it goes.
 
 Matt
 
 On Wed, Feb 3, 2010 at 10:59 AM, Matt Ettus >>> > wrote:
> * Does anyone have any experience using CPLDs for very low phase 
> noise
 *>* dividers?  You can get an XC9536XL from Xilinx for 
>>> around $1, and 
 I
 *>* thought it would make a good divide by 2 through 10 device.
 *>>* Matt*
 
 A lot of the discussion focused on the difficulties of 
>>> downloading the 
 tools for Altera or Xilinx - the Max II family from Altera was 
 recommended - but there was no apparent outcome or 
>>> resolution to this 
 thread - seemingly.
 
 Does anyone have that CPLD recommendation?
 
 Thanks,
 John Westmoreland ___
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 To unsubscribe, go to 
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>>> 
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>> 
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Re: [time-nuts] OT - Old Hatfield 2105 Step attenuator specs

[Alan Melia]

Hi agn Giuseppi that may indicate your units date from later, after the 
company were acquired by Pascall

Alan
- Original Message - 
From: "Giuseppe Marullo" 
To: "Discussion of precise time and frequency measurement" 


Sent: Monday, January 06, 2014 4:05 PM
Subject: Re: [time-nuts] OT - Old Hatfield 2105 Step attenuator specs



Alan,
thank you for your answer.
>. If you are refering to the units in blue crackle diecast case with
miniature toggle
Sort of, but "mine" is orange:
http://thumbs3.ebaystatic.com/d/l225/m/mkbCnoRgl8RNnxvJdy9phAw.jpg
Seems pretty close, I was hoping for some better figure but I plan to use 
it for HF bands, so no big deal if the Fmax is 150MHz.


Thank you again.

Giuseppe Marullo
IW2JWW
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Re: [time-nuts] 'CPLDs for clock dividers' Thread

[Bob Camp]

Hi

There are also parts from other vendors that have the same sort of issues. 
Altera certainly has (had) some. 

Bob

On Jan 6, 2014, at 2:20 PM, Bruce Griffiths  wrote:

> Another issue is whether the clock of the internal  state machine used in 
> some CPLDs to load internal RAM cells from slower EEPROM cells is turned off 
> after power up initialisation.
> Some Xilinx parts for example do not turn of this clock. This clock is a 
> potential source of spurs.
> 
> Bruce
> 
> Bob Camp wrote:
>> Hi
>> 
>> If you disable all the internal clocks (normally fairly easy) and your 
>> supply is clean and it’s a modern high speed part, you can get into the high 
>> 150’s to low 160’s on a 10 MHz output with a CPLD.
>> 
>> If you have one of those wonderful old designs where the charge pump clocks 
>> (or what ever) stay on all the time, you will be in the 120’s to 130’s.
>> 
>> Bob
>> 
>> On Jan 5, 2014, at 9:11 PM, John C. Westmoreland, 
>> P.E.  wrote:
>> 
>>   
>>> Hello All,
>>> 
>>> I was looking at the archives - what was the outcome of this:
>>> 
>>> Thanks to everyone for their advice.  I bought a CoolRunner II
>>> development board (only $39!) and will let you know how it goes.
>>> 
>>> Matt
>>> 
>>> On Wed, Feb 3, 2010 at 10:59 AM, Matt Ettus>> >  wrote:
>>> 
 * Does anyone have any experience using CPLDs for very low phase noise
   
>>> *>* dividers?  You can get an XC9536XL from Xilinx for around $1, and I
>>> *>* thought it would make a good divide by 2 through 10 device.
>>> *>>* Matt*
>>> 
>>> A lot of the discussion focused on the difficulties of downloading the 
>>> tools for
>>> Altera or Xilinx - the Max II family from Altera was recommended - but 
>>> there was
>>> no apparent outcome or resolution to this thread - seemingly.
>>> 
>>> Does anyone have that CPLD recommendation?
>>> 
>>> Thanks,
>>> John Westmoreland
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>>> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
>>> and follow the instructions there.
>>> 
>> ___
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>> and follow the instructions there.
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>>   
> 
> ___
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Re: [time-nuts] 'CPLDs for clock dividers' Thread

[Bob Camp]

Hi

You can get into the -154.9 dbc / square root hertz to -164.9 dbc / square root 
hertz 

Since we’re talking about phase noise I assumed the units were the ones 
normally used. Typing all the square root hertz stuff takes a while. 

It’s been a while since I’ve seen phase noise dimensioned in eggs ….

Bob

On Jan 6, 2014, at 12:45 PM, Ulrich Bangert  wrote:

> Bob,
> 
> I appreciate your postings a lot but can you please explain what property
> you are referring to with a sentence like
> 
>> you can get into the high 150’s to low 160’s on a 10 MHz
> 
> Using numbers without units (maybe: quail eggs per sqare inch ?) makes it
> difficult to understand what you are going to say even for experienced time
> nutters.
> 
> Brent,
> 
>> Precious little to add to this, just to confirm that 
>> back in another life at Watkins Johnson (early 90's), 
>> we used CPLD's for low phase noise dividers all the time.  
>> My work at the time was focused on everything but the divider.
> 
> Ok, but how much different input signals did you have for one CPLD? If your
> answer is "1" then you have given youself the explanation why they worked
> ok.
> 
> Best regards
> Ulrich
> 
>> -Ursprüngliche Nachricht-
>> Von: time-nuts-boun...@febo.com 
>> [mailto:time-nuts-boun...@febo.com] Im Auftrag von Bob Camp
>> Gesendet: Montag, 6. Januar 2014 13:28
>> An: Discussion of precise time and frequency measurement
>> Betreff: Re: [time-nuts] 'CPLDs for clock dividers' Thread
>> 
>> 
>> Hi
>> 
>> If you disable all the internal clocks (normally fairly easy) 
>> and your supply is clean and it’s a modern high speed part, 
>> you can get into the high 150’s to low 160’s on a 10 MHz 
>> output with a CPLD. 
>> 
>> If you have one of those wonderful old designs where the 
>> charge pump clocks (or what ever) stay on all the time, you 
>> will be in the 120’s to 130’s. 
>> 
>> Bob
>> 
>> On Jan 5, 2014, at 9:11 PM, John C. Westmoreland, P.E. 
>>  wrote:
>> 
>>> Hello All,
>>> 
>>> I was looking at the archives - what was the outcome of this:
>>> 
>>> Thanks to everyone for their advice.  I bought a CoolRunner II 
>>> development board (only $39!) and will let you know how it goes.
>>> 
>>> Matt
>>> 
>>> On Wed, Feb 3, 2010 at 10:59 AM, Matt Ettus >> > wrote:
 * Does anyone have any experience using CPLDs for very low phase 
 noise
>>> *>* dividers?  You can get an XC9536XL from Xilinx for 
>> around $1, and 
>>> I
>>> *>* thought it would make a good divide by 2 through 10 device.
>>> *>>* Matt*
>>> 
>>> A lot of the discussion focused on the difficulties of 
>> downloading the 
>>> tools for Altera or Xilinx - the Max II family from Altera was 
>>> recommended - but there was no apparent outcome or 
>> resolution to this 
>>> thread - seemingly.
>>> 
>>> Does anyone have that CPLD recommendation?
>>> 
>>> Thanks,
>>> John Westmoreland ___
>>> time-nuts mailing list -- time-nuts@febo.com
>>> To unsubscribe, go to 
>> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
>>> and follow the instructions there.
>> 
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> 
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[time-nuts] WWVB "repeater" (was: WWV Simulator Programs)

[M. Simon]

May I suggest United Chemi-Con EKZM series capacitors. They are very long life 
electrolytics.  

Data sheet: 
http://www.chemi-con.com/components/com_lcatalog/uploaded/8/4/4/79794946651719ba91258a.pdf


They are rated 6,000, 8,000, and 10,000 hours at load (max ripple current) 
depending on case size. The actual life is longer at lower temperature (below 
105C) and lower current. The relationship with current and temperature is 
non-linear. Mouser carries them: 
http://www.mouser.com/Search/Refine.aspx?N=1323043&Keyword=ekzm


Reliability

http://www.chemi-con.com/index.php?option=com_content&view=article&id=11&Itemid=17
  

Capacitor life
http://www.chemi-con.com/index.php?option=com_content&view=article&id=12&Itemid=19

General page including the above links
Understanding The Aluminum Electrolytic Capacitor

http://www.chemi-con.com/index.php?option=com_content&view=article&id=13&Itemid=5


Simon





Date: Fri, 03 Jan 2014 13:25:10 -0700
From: Clint Turner 
To: time-nuts@febo.com
Subject: [time-nuts] WWVB "repeater" (was:  WWV Simulator Programs)
Message-ID: <52c71ca6.10...@ussc.com>
Content-Type: text/plain; charset=ISO-8859-1; format=flowed

Sometime in the late 1990s, a friend of mine who works for a local city 
government asked me if there was something that I could do about some 
WWVB clocks located in a conference room, downtown, on a middle floor of 
an office building amongst computers and fluorescent lights that never 
managed to get the correct time.

Together, we built this:

http://ka7oei.blogspot.com/2013/03/getting-atomic-wwvb-clocks-to-work.html

It's been in operation since it was installed, except for two occasions:

- After a few weeks it quit working so my friend opened the cover of the 
outdoor unit to take a look.  Once the water drained out, it started 
operating again.  (He then drilled a drain hole and sealed everything 
else a bit better.)

- Last year - after somewhat more than a decade of operation - it quit 
working when the electrolytics in the transformer-type "wall wart" that 
powered it dried out and there was several volts of AC riding atop the 
DC output.  A new wall wart was procured and I added a large capacitor 
in the indoor amplifier's box as well.


==




Engineering is the art of making what you want from what you can get at a 
profit.
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Re: [time-nuts] 'CPLDs for clock dividers' Thread

[Bruce Griffiths]

Another issue is whether the clock of the internal  state machine used 
in some CPLDs to load internal RAM cells from slower EEPROM cells is 
turned off after power up initialisation.
Some Xilinx parts for example do not turn of this clock. This clock is a 
potential source of spurs.


Bruce

Bob Camp wrote:

Hi

If you disable all the internal clocks (normally fairly easy) and your supply 
is clean and it’s a modern high speed part, you can get into the high 150’s to 
low 160’s on a 10 MHz output with a CPLD.

If you have one of those wonderful old designs where the charge pump clocks (or 
what ever) stay on all the time, you will be in the 120’s to 130’s.

Bob

On Jan 5, 2014, at 9:11 PM, John C. Westmoreland, 
P.E.  wrote:

   

Hello All,

I was looking at the archives - what was the outcome of this:

Thanks to everyone for their advice.  I bought a CoolRunner II
development board (only $39!) and will let you know how it goes.

Matt

On Wed, Feb 3, 2010 at 10:59 AM, Matt Ettushttps://www.febo.com/cgi-bin/mailman/listinfo/time-nuts>>  wrote:
 

* Does anyone have any experience using CPLDs for very low phase noise
   

*>* dividers?  You can get an XC9536XL from Xilinx for around $1, and I
*>* thought it would make a good divide by 2 through 10 device.
*>>* Matt*

A lot of the discussion focused on the difficulties of downloading the tools for
Altera or Xilinx - the Max II family from Altera was recommended - but there was
no apparent outcome or resolution to this thread - seemingly.

Does anyone have that CPLD recommendation?

Thanks,
John Westmoreland
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[time-nuts] Symmetricom down conversion antenna needed...

[Dave Wright]

Hi All,

Was lucky(?) enough to acquire an early Symmetricom unit, what I believe to be 
a predecessor of the XL-DC line. Model number is 151-652-387-1. This is a 
Rubidium unit, and appears to be in good health running open loop.

This particular model requires a down conversion antenna, which I am 
discovering is a rare item these days. My research so far has revealed that the 
following Symmetricom model numbers are suitable:

142-401
142-602
142-603
142-610

These antennas expect 12VDC and a 16.368 MHz reference for the LO, and send 
down a  4.092MHz IF to the receiver card.

I'm hoping that someone on the list might have one or be able to connect me 
with a seller..!

Also have a Hughes Network System Time Code (HNSTC) card, Symmetricom model 
86-3799-30 that I would be happy to trade if anyone is interested.


_Dave  KC6UPS

502-489-4527




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Re: [time-nuts] sand9 TCMO

[Attila Kinali]

On Mon, 06 Jan 2014 06:24:18 -0800
Jim Lux  wrote:

> > MEMS might be good for certain tasks, but for closer in noise I've only
> > seen some progress recently, but not measured it myself. Close-in noise
> > seems to have been pretty bad for all MEMS so far.
> >
> 
> I think that's probably related to the physically small size. It's hard 
> to get a high Q in something that's smaller than a gnat's eyelash.

It's not only the Q (although i have not seen any Q values yet), but
also that (almost?) all of those MEMS oscillators have a fixed frequency
oscillator structure and use a fractional-N PLL together with a standard
CMOS VCO. The spurs of the PLL are clearly visible if you go down to 1kHz
(i haven't seen any spectrums going further down than 1kHz for MEMS 
oscillators).

But advanced oscillator structures make it possible to have oscillators
which show very low temperature dependence (IIRC <5ppm over -30°C to +80°C)
without any electronic temperature compensation applied (yet).
(done by SiTime. Sorry, don't have any exact reference)

The big promise of MEMS oscillators of having very low power consumption
is not fullfiled yet. About half a year ago i checked all the 32kHz
MEMS oscillators i could find and got numbers for power consumption that
were about the same as an MSP430 would use, with its 32kHz crystal 
oscillator running.

Attila Kinali

-- 
I pity people who can't find laughter or at least some bit of amusement in
the little doings of the day. I believe I could find something ridiculous
even in the saddest moment, if necessary. It has nothing to do with being
superficial. It's a matter of joy in life.
-- Sophie Scholl
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Re: [time-nuts] 'CPLDs for clock dividers' Thread

[Hal Murray]

vesoa...@deea.isel.ipl.pt said:
> With respect to jitter does anyone compared the solutions using a PLL or DCM
>  on FPGAs for clock dividing? For instance, from 10 MHz to 44.1 kHz which
> would be the best option? Does a CPLD supersedes those FPGA functionalities
> for that kind of operation? 

If you read the fine print in the Xilinx data sheets for their FPGAs with 
DCMs you will see that they will be horrible for things like good phase 
noise.  They are using digital DLLs, delay locked loops, rather than analog 
PLLs.  It's a long string of buffers.  They tap off at the right place and 
jiggle the tap back and forth as needed.  That "jiggle" covers two things.  
One is the fractional tap to get the right frequency.  I'd expect the output 
to have spurs like a DDS.  The jiggle also gets adjusted to cover things like 
temperature shifts, so the spurs you see now may be different if you wait a 
few minutes.

If you don't use the DCM, I'd expect them to work reasonably well.  They 
probably have more logic than you need for a simple clock divider and you 
have to reload them at power up.


-- 
These are my opinions.  I hate spam.



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Re: [time-nuts] 'CPLDs for clock dividers' Thread

[brent evers]

Wow -

Now you're really taxing my memory.  Radios tuned from 2Mhz to 2Ghz.  LO
was high side mix and I think ran from roughly 3-5Ghz, comprised of 4
switched VCO's.  I think the IF was always 70Mhz.  I'd have to revisit
quite a bit to come up with more info than that.  Sorry I can't remember
more - that was 20 years ago this year, first job out of school.  Yikes,
I'm getting old.

Brent


On Mon, Jan 6, 2014 at 12:45 PM, Ulrich Bangert wrote:

> Bob,
>
> I appreciate your postings a lot but can you please explain what property
> you are referring to with a sentence like
>
> > you can get into the high 150’s to low 160’s on a 10 MHz
>
> Using numbers without units (maybe: quail eggs per sqare inch ?) makes it
> difficult to understand what you are going to say even for experienced time
> nutters.
>
> Brent,
>
> > Precious little to add to this, just to confirm that
> > back in another life at Watkins Johnson (early 90's),
> > we used CPLD's for low phase noise dividers all the time.
> > My work at the time was focused on everything but the divider.
>
> Ok, but how much different input signals did you have for one CPLD? If your
> answer is "1" then you have given youself the explanation why they worked
> ok.
>
> Best regards
> Ulrich
>
> > -Ursprüngliche Nachricht-
> > Von: time-nuts-boun...@febo.com
> > [mailto:time-nuts-boun...@febo.com] Im Auftrag von Bob Camp
> > Gesendet: Montag, 6. Januar 2014 13:28
> > An: Discussion of precise time and frequency measurement
> > Betreff: Re: [time-nuts] 'CPLDs for clock dividers' Thread
> >
> >
> > Hi
> >
> > If you disable all the internal clocks (normally fairly easy)
> > and your supply is clean and it’s a modern high speed part,
> > you can get into the high 150’s to low 160’s on a 10 MHz
> > output with a CPLD.
> >
> > If you have one of those wonderful old designs where the
> > charge pump clocks (or what ever) stay on all the time, you
> > will be in the 120’s to 130’s.
> >
> > Bob
> >
> > On Jan 5, 2014, at 9:11 PM, John C. Westmoreland, P.E.
> >  wrote:
> >
> > > Hello All,
> > >
> > > I was looking at the archives - what was the outcome of this:
> > >
> > > Thanks to everyone for their advice.  I bought a CoolRunner II
> > > development board (only $39!) and will let you know how it goes.
> > >
> > > Matt
> > >
> > > On Wed, Feb 3, 2010 at 10:59 AM, Matt Ettus  > > > wrote:
> > >> * Does anyone have any experience using CPLDs for very low phase
> > >> noise
> > > *>* dividers?  You can get an XC9536XL from Xilinx for
> > around $1, and
> > > I
> > > *>* thought it would make a good divide by 2 through 10 device.
> > > *>>* Matt*
> > >
> > > A lot of the discussion focused on the difficulties of
> > downloading the
> > > tools for Altera or Xilinx - the Max II family from Altera was
> > > recommended - but there was no apparent outcome or
> > resolution to this
> > > thread - seemingly.
> > >
> > > Does anyone have that CPLD recommendation?
> > >
> > > Thanks,
> > > John Westmoreland ___
> > > time-nuts mailing list -- time-nuts@febo.com
> > > To unsubscribe, go to
> > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> > > and follow the instructions there.
> >
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> > To unsubscribe, go to
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> > and follow the instructions there.
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Re: [time-nuts] 'CPLDs for clock dividers' Thread

[Ulrich Bangert]

Bob,

I appreciate your postings a lot but can you please explain what property
you are referring to with a sentence like

> you can get into the high 150’s to low 160’s on a 10 MHz

Using numbers without units (maybe: quail eggs per sqare inch ?) makes it
difficult to understand what you are going to say even for experienced time
nutters.

Brent,

> Precious little to add to this, just to confirm that 
> back in another life at Watkins Johnson (early 90's), 
> we used CPLD's for low phase noise dividers all the time.  
> My work at the time was focused on everything but the divider.

Ok, but how much different input signals did you have for one CPLD? If your
answer is "1" then you have given youself the explanation why they worked
ok.

Best regards
Ulrich

> -Ursprüngliche Nachricht-
> Von: time-nuts-boun...@febo.com 
> [mailto:time-nuts-boun...@febo.com] Im Auftrag von Bob Camp
> Gesendet: Montag, 6. Januar 2014 13:28
> An: Discussion of precise time and frequency measurement
> Betreff: Re: [time-nuts] 'CPLDs for clock dividers' Thread
> 
> 
> Hi
> 
> If you disable all the internal clocks (normally fairly easy) 
> and your supply is clean and it’s a modern high speed part, 
> you can get into the high 150’s to low 160’s on a 10 MHz 
> output with a CPLD. 
> 
> If you have one of those wonderful old designs where the 
> charge pump clocks (or what ever) stay on all the time, you 
> will be in the 120’s to 130’s. 
> 
> Bob
> 
> On Jan 5, 2014, at 9:11 PM, John C. Westmoreland, P.E. 
>  wrote:
> 
> > Hello All,
> > 
> > I was looking at the archives - what was the outcome of this:
> > 
> > Thanks to everyone for their advice.  I bought a CoolRunner II 
> > development board (only $39!) and will let you know how it goes.
> > 
> > Matt
> > 
> > On Wed, Feb 3, 2010 at 10:59 AM, Matt Ettus  > > wrote:
> >> * Does anyone have any experience using CPLDs for very low phase 
> >> noise
> > *>* dividers?  You can get an XC9536XL from Xilinx for 
> around $1, and 
> > I
> > *>* thought it would make a good divide by 2 through 10 device.
> > *>>* Matt*
> > 
> > A lot of the discussion focused on the difficulties of 
> downloading the 
> > tools for Altera or Xilinx - the Max II family from Altera was 
> > recommended - but there was no apparent outcome or 
> resolution to this 
> > thread - seemingly.
> > 
> > Does anyone have that CPLD recommendation?
> > 
> > Thanks,
> > John Westmoreland ___
> > time-nuts mailing list -- time-nuts@febo.com
> > To unsubscribe, go to 
> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> > and follow the instructions there.
> 
> ___
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Re: [time-nuts] Hp 5060A C-field

[paul swed]

OK seems no matter what I do compared to the Tbolt and Z3801the 5061/5060
still drifts right on the scope. Granted a big shift in the cfield seems to
get the unit to advance, but then after some hours it returns back to the
same slow rate. But I did learn about the magical A1 synthesizer and built
an excel calculator to see what the jumper settings do. If anyone wants it
I will forward it.
Putting the A! synth on the bench and feeding a 5 Mhz source in I could see
how it behaved. It tends to run a little high in frequency. I mean
fractions of a hertz.
As far as the jumpers go one change really does move the synth quite a ways
from the atomic frequency. So what I learned is that changing the jumpers
really would make a heck of a jump either fast or slow, not some fine grain
shift.
Regards
Paul
WB8TSL


On Fri, Jan 3, 2014 at 9:04 PM, paul swed  wrote:

> Tom and Corby
> Thanks for the help. I suspect that the 5060/5061 is perhaps as good as it
> can get.
> My other references such as the 3801 and Tbolt have it down now in the
> 1X10-11 region. Close to 1 but goes above and below. I did find the magical
> cfield R to be 70 ohms and will have to calculate the current.
> When I do measurements for 10 ns displacement it takes some 13-18 minutes.
> I also use a 5370b counter much easier to measure the ns drift than the
> scope.
> Regards
> Paul
> WB8TSL
>
>
>
> On Fri, Jan 3, 2014 at 1:13 PM, Tom Van Baak (lab) wrote:
>
>> Hi Paul,
>>
>> About cesium clocks: hp 5060A and early versions of the hp 5061A needed
>> to be able to keep *either* atomic time (true, accurate, stable, SI
>> seconds) or astronomical time (inaccurate, unstable, slow, and gradually
>> slowing, earth rotation time).
>>
>> The larger C-field range allowed this user choice of time-scales. I have
>> many examples of both clocks here.
>>
>> It appears most time & frequency labs converted to "atomic time" in the
>> late 60's and 70's which is why all later 5061A, all 5061B, every 5071A,
>> and all modern atomic/ion/optical clocks tick "atomic" seconds instead of
>> the slightly larger and monthly / seasonally / climatically / geologically
>> / gravitationally variable "earth" seconds. And why we have leap seconds.
>>
>> In the past 50 years even die-hard astronomers have thrown in the towel
>> and conceded that atomic time is a more stable time reference than earth
>> rotation rate. In order to point modern, super-accurate telescopes they use
>> a high-precision (sub-millisecond!) "DUT1" correction to convert
>> physics-stable atomic time into engineering-accurate astronomical time;
>> "close enough for government pointing work" as they say.
>>
>> Now that we're well into the post-astronomical time age, the narrow
>> C-field range is adequate. If you have a 5060 or older 5061 there is no
>> harm in using resistors to restrict the C-field range.
>>
>> /tvb (i5s)
>>
>> > On Jan 3, 2014, at 7:51 AM, paul swed  wrote:
>> >
>> > Corby
>> > Having a good time tinkering with the 5061. Did change the resistors for
>> > the cfield regulator so that its much close to the schematic and am
>> > experimenting with that.
>> > The system does seems to be able to be tuned through a stable position
>> that
>> > reduces the drift to 2 min/10ns drift and the CS is slow compared to the
>> > 5065 RB set to loran C when its on the air.
>> > I do have a older synth div board. No thumbwheel switches. It appears
>> to me
>> > to be jumpered at 8634. I think that may be wrong. The book says 2095
>> for
>> > atomic time.
>> > Appreciate your thoughts.
>> > Regards
>> > Paul
>> >
>> >
>> >> On Thu, Jan 2, 2014 at 4:52 PM, paul swed  wrote:
>> >>
>> >> Corby
>> >> I pulled the a15 board and there are no resistors, just a short across
>> >> what would have been r19 and 21. So I suspect that there is to much
>> current
>> >> actually. Further speculation is that when the pot is toward ground
>> more
>> >> current flows from what I see in the schematic.
>> >> I may guess that more current equals lower frequency?
>> >> Regards
>> >> Paul.
>> >>
>> >>
>> >>> On Thu, Jan 2, 2014 at 4:22 PM,  wrote:
>> >>>
>> >>> Paul the C-field current is the same for the 5061A and 5060A.
>> >>>
>> >>> The 5060A C-field pot has LOTS more range than the later 5061A where
>> they
>> >>> installed resistors on each side of the pot to reduce the range.
>> >>>
>> >>> Corby
>> >>>
>> >>> ___
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>> >>> and follow the instructions there.
>> >>>
>> >>
>> >>
>> > ___
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>> > and follow the instructions there.
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Re: [time-nuts] OT - Old Hatfield 2105 Step attenuator specs

[Giuseppe Marullo]

Alan,
thank you for your answer.
>. If you are refering to the units in blue crackle diecast case with 
miniature toggle

Sort of, but "mine" is orange:
http://thumbs3.ebaystatic.com/d/l225/m/mkbCnoRgl8RNnxvJdy9phAw.jpg
Seems pretty close, I was hoping for some better figure but I plan to 
use it for HF bands, so no big deal if the Fmax is 150MHz.


Thank you again.

Giuseppe Marullo
IW2JWW
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Re: [time-nuts] 'CPLDs for clock dividers' Thread

[Vasco Soares]

Hi All,

With respect to jitter does anyone compared the solutions using a PLL or DCM 
on FPGAs for clock dividing? For instance, from 10 MHz to 44.1 kHz which 
would be the best option? Does a CPLD supersedes those FPGA functionalities 
for that kind of operation?


Best regards,
Vasco Soares


- Original Message - 
From: "brent evers" 
To: "Discussion of precise time and frequency measurement" 


Sent: Monday, January 06, 2014 1:30 PM
Subject: Re: [time-nuts] 'CPLDs for clock dividers' Thread


Precious little to add to this, just to confirm that back in another life
at Watkins Johnson (early 90's), we used CPLD's for low phase noise
dividers all the time.  My work at the time was focused on everything but
the divider.

Brent


On Mon, Jan 6, 2014 at 7:27 AM, Bob Camp  wrote:


Hi

If you disable all the internal clocks (normally fairly easy) and your
supply is clean and it’s a modern high speed part, you can get into the
high 150’s to low 160’s on a 10 MHz output with a CPLD.

If you have one of those wonderful old designs where the charge pump
clocks (or what ever) stay on all the time, you will be in the 120’s to
130’s.

Bob

On Jan 5, 2014, at 9:11 PM, John C. Westmoreland, P.E. <
j...@westmorelandengineering.com> wrote:

> Hello All,
>
> I was looking at the archives - what was the outcome of this:
>
> Thanks to everyone for their advice.  I bought a CoolRunner II
> development board (only $39!) and will let you know how it goes.
>
> Matt
>
> On Wed, Feb 3, 2010 at 10:59 AM, Matt Ettus  > wrote:
>> * Does anyone have any experience using CPLDs for very low phase noise
> *>* dividers?  You can get an XC9536XL from Xilinx for around $1, and I
> *>* thought it would make a good divide by 2 through 10 device.
> *>>* Matt*
>
> A lot of the discussion focused on the difficulties of downloading the
tools for
> Altera or Xilinx - the Max II family from Altera was recommended - but
there was
> no apparent outcome or resolution to this thread - seemingly.
>
> Does anyone have that CPLD recommendation?
>
> Thanks,
> John Westmoreland
> ___
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Re: [time-nuts] OT - Old Hatfield 2105 Step attenuator specs

[Alan Melia]

Hi Guiseppi I think I have some papers on them somewhere.I cant remember the 
model numbers. If you are refering to the units in blue crackle diecast case 
with miniature toggle switches the spec max frequency is 150MHz from memory. 
I did plot one some time ago on my Spectrum Analyser and TG, They are usable 
to 200MHz with reduced accuracy.


Alan
G3NYK.
- Original Message - 
From: "Giuseppe Marullo" 
To: "Discussion of precise time and frequency measurement" 


Sent: Monday, January 06, 2014 1:13 PM
Subject: [time-nuts] OT - Old Hatfield 2105 Step attenuator specs



Hello to all,
and Happy New Year.

I would like to know the specs for this attenuator, especially the maximum 
frequency, if any good folk has a ballpark idea...

I was not able to locate any info about it.

Thanks in advance.

Giuseppe Marullo
IW2JWW
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Re: [time-nuts] sand9 TCMO

[Jim Lux]

On 1/6/14 6:05 AM, Magnus Danielson wrote:


MEMS might be good for certain tasks, but for closer in noise I've only
seen some progress recently, but not measured it myself. Close-in noise
seems to have been pretty bad for all MEMS so far.



I think that's probably related to the physically small size. It's hard 
to get a high Q in something that's smaller than a gnat's eyelash.


I wonder if someone has done some sort of fundamental analysis, like 
there is for antennas that establishes a "laws of physics" limit on how 
good it can possibly be for a given size or mass.  For antennas, there's 
the Chu or Chu-Harrington limit that says there's a tradeoff between 
directivity, stored energy and physical size.  A high directivity, small 
antenna will have a lot of stored energy, which in practice means low 
efficiency.


For instance, at some point, the resonator is so small that the amount 
of energy in it is comparable to the thermal noise, so if it's uncooled, 
that sets a floor on best performance.



 It's a quick way to stop those entrepreneurs who know just enough to 
be dangerous when they say that they're going to make 1 degree wide 
beams with something the size of a cellphone.  You know, the companies 
that have one or two folks in engineering and 35 in investor relations. 
 They often combine their "not realizable in real world" antenna with a 
"new form of modulation and coding that provides 10x performance over 
best methods today".


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Re: [time-nuts] sand9 TCMO

[Magnus Danielson]

John,

On 06/01/14 08:40, John C. Westmoreland, P.E. wrote:

Hello All,

I thought this may be of interest to the group - a start-up company - Sand9
- has developed a temperature controlled MEMS oscillator (TCMO):

http://www.sand9.com/product/tcmo/ .


I see nothing very special about this MEMS compared to others I've seen. 
Phase-noise measure stops at 12 kHz, which is not too hard, as the 
cut-over to CMOS oscillator is below that in the step-up PLL.


MEMS might be good for certain tasks, but for closer in noise I've only 
seen some progress recently, but not measured it myself. Close-in noise 
seems to have been pretty bad for all MEMS so far.


Cheers,
Magnus
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Re: [time-nuts] 'CPLDs for clock dividers' Thread

[brent evers]

Precious little to add to this, just to confirm that back in another life
at Watkins Johnson (early 90's), we used CPLD's for low phase noise
dividers all the time.  My work at the time was focused on everything but
the divider.

Brent


On Mon, Jan 6, 2014 at 7:27 AM, Bob Camp  wrote:

> Hi
>
> If you disable all the internal clocks (normally fairly easy) and your
> supply is clean and it’s a modern high speed part, you can get into the
> high 150’s to low 160’s on a 10 MHz output with a CPLD.
>
> If you have one of those wonderful old designs where the charge pump
> clocks (or what ever) stay on all the time, you will be in the 120’s to
> 130’s.
>
> Bob
>
> On Jan 5, 2014, at 9:11 PM, John C. Westmoreland, P.E. <
> j...@westmorelandengineering.com> wrote:
>
> > Hello All,
> >
> > I was looking at the archives - what was the outcome of this:
> >
> > Thanks to everyone for their advice.  I bought a CoolRunner II
> > development board (only $39!) and will let you know how it goes.
> >
> > Matt
> >
> > On Wed, Feb 3, 2010 at 10:59 AM, Matt Ettus  > > wrote:
> >> * Does anyone have any experience using CPLDs for very low phase noise
> > *>* dividers?  You can get an XC9536XL from Xilinx for around $1, and I
> > *>* thought it would make a good divide by 2 through 10 device.
> > *>>* Matt*
> >
> > A lot of the discussion focused on the difficulties of downloading the
> tools for
> > Altera or Xilinx - the Max II family from Altera was recommended - but
> there was
> > no apparent outcome or resolution to this thread - seemingly.
> >
> > Does anyone have that CPLD recommendation?
> >
> > Thanks,
> > John Westmoreland
> > ___
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> > To unsubscribe, go to
> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> > and follow the instructions there.
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[time-nuts] OT - Old Hatfield 2105 Step attenuator specs

[Giuseppe Marullo]

Hello to all,
and Happy New Year.

I would like to know the specs for this attenuator, especially the 
maximum frequency, if any good folk has a ballpark idea...

I was not able to locate any info about it.

Thanks in advance.

Giuseppe Marullo
IW2JWW
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Re: [time-nuts] 'CPLDs for clock dividers' Thread

[Bob Camp]

Hi

If you disable all the internal clocks (normally fairly easy) and your supply 
is clean and it’s a modern high speed part, you can get into the high 150’s to 
low 160’s on a 10 MHz output with a CPLD. 

If you have one of those wonderful old designs where the charge pump clocks (or 
what ever) stay on all the time, you will be in the 120’s to 130’s. 

Bob

On Jan 5, 2014, at 9:11 PM, John C. Westmoreland, P.E. 
 wrote:

> Hello All,
> 
> I was looking at the archives - what was the outcome of this:
> 
> Thanks to everyone for their advice.  I bought a CoolRunner II
> development board (only $39!) and will let you know how it goes.
> 
> Matt
> 
> On Wed, Feb 3, 2010 at 10:59 AM, Matt Ettus  > wrote:
>> * Does anyone have any experience using CPLDs for very low phase noise
> *>* dividers?  You can get an XC9536XL from Xilinx for around $1, and I
> *>* thought it would make a good divide by 2 through 10 device.
> *>>* Matt*
> 
> A lot of the discussion focused on the difficulties of downloading the tools 
> for
> Altera or Xilinx - the Max II family from Altera was recommended - but there 
> was
> no apparent outcome or resolution to this thread - seemingly.
> 
> Does anyone have that CPLD recommendation?
> 
> Thanks,
> John Westmoreland
> ___
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