Re: [time-nuts] low noise multiplication to 100 MHz
We have looked at the LMK devices but with my 74 years would not try to solder it. There are other neat parts out there but again who is able to solder them. Bert Kehren In a message dated 1/25/2016 8:11:14 P.M. Eastern Standard Time, b...@hsmicrowave.com writes: Aaah - but then you need a microprocessor (and its noise if you're not careful) to control it. IMHO - too complicated an approach. Hard to beat a "careful" straight multiplier approach for simple or a phased locked 100 MHz VCXO for the best phase noise. Bill - N6GHz On 1/25/2016 9:20 AM, Graham / KE9H wrote: > There are clock distribution parts designed to do this low noise frequency > conversion and distribution. > > Consider TI LMK04100 > > Ignore PLL1 > Put your 10 MHz as the reference input to PLL2. > Set Internal VCO to ~1200 MHz > Set the internal dividers to get 100 MHz out, and 10 MHz back to the PLL2 > phase detector. > > Get reasonable noise and 100 MHz output with your choice of 2VPECL, LVDS, > LVCMOS output levels. > > If you have a dirty input clock/reference, or multiple sources, you can use > PLL1 and an external crystal in a VCO to clean it up before you multiply it > to 1200 MHz. > > And you can get up to four other frequencies out of the part at the same > time. > > 150 fs class jitter. > > $13 cost, quantity one. > > --- Graham > > == > > > > > > On Mon, Jan 25, 2016 at 9:22 AM, Bert Kehren via time-nuts < > time-nuts@febo.com> wrote: > >> If not good enough an XOR with filter and one of the Crystek VCXO's >> previously mentioned may do it. >> Bert Kehren >> >> >> In a message dated 1/25/2016 10:01:33 A.M. Eastern Standard Time, >> mag...@rubidium.dyndns.org writes: >> >> Also, it will be systematic, with idle tones. Because of the delay >> elements used, they will not be long-term static but move around. >> >> I agree, this is quite noisy. If the noise is tolerable, it is indeed a >> small solution. 100 ps 1-sigma for 5 MHz in 100 MHz out isn't what I >> would consider low. >> >> https://www.idt.com/document/dst/570-datasheet >> >> Cheers, >> Magnus >> >> On 01/24/2016 11:12 PM, Bruce Griffiths wrote: >>> Unfortunately the ICS570 (like all zero delay buffers) has an output >> jitter approaching about 1000 times the likely RF ADC internal sampling >> jitter. The resultant SNR degradation may be a little excessive for this >> application.. >>>Bruce >>> >>> >>> On Monday, 25 January 2016 11:00 AM, Bert Kehren via time-nuts >>wrote: >>> >>>With all the discussions in a small 100 MHz source I asked my project >>> partner Juerg in Switzerland to run some data on the ICS 570 that we use >> on the >>> majority of our projects with excellent results. Using the HP53132A we >> see >> >>> + - 1 count at E10-11 ignore the large jumps those come from the Tbolt >>> frequency change to correct the 1 pps. Depending on the application >> this is an >>> excellent device. >>> Bert Kehren >>> >>> >>> In a message dated 1/23/2016 6:02:23 P.M. Eastern Standard Time, >>> dk...@arcor.de writes: >>> >>> Am22.01.2016 um 22:40 schrieb jimlux: the oscillator is a HCMOS output, so figure swinging about 3.5V Output.. I'm feeding differential clock inputs on ADCs. I'll bet a +/- 300mV swing would work. > 4)Title said "Low Noise" needs better definition as to what kind of > noise and how far down. Are we to be concerned about harmonic and >> spur > content as compared to real random white noise? This is time-nuts.. it has to beperfect.. But realistically, my source is probably going to be about -90dBc/Hz at 1 Hz, -125 at 10Hz, -145 at 100 Hz. I'm going up by a factor of 10, so I'd expect 20 dB worse plus a little..(nothing is perfect, >> eh?) Call it maybe -100 to -95 at 10 Hz, -125 to -120 at 100 Hz and so >> forth. harmonics areinteresting: it's the sample clock into an ADC. So harmonics of the 100 aren't a big deal. harmonics of the 10 or 20 are. If you have significant 90 or 110 contaminating the 100, then you get weird spurs.. (I had this problem on a software radio where the 50 MHz sample clock was contaminated with some 66 MHz from the >> CPU) Spurs cause the same issues. ON the other hand... spurs that are pretty low don't make much difference if you're digitizing a signal that is close to the noise floor: the spur multiplied by the desired signal is usually lower and down in the noise. Strong CW in band signals, though, are a real >> pain. >>> < >>> >> https://picasaweb.google.com/103357048842463945642/Tronix#607927018804883377 >>>8 >>> I think that top left board would not be far away: >>> >>> in : 10 MHz LVDS or CMOS >>> in: 3V3 >>> out: 100 MHz CMOS 3V3 >>> >>> just a few hours wall clock time from layout to wor
Re: [time-nuts] low noise multiplication to 100 MHz
Am 25.01.2016 um 18:20 schrieb Graham / KE9H: There are clock distribution parts designed to do this low noise frequency conversion and distribution. Consider TI LMK04100 150 fs class jitter. But only if you integrate the noise only from 12 kHz offset to 20 MHz. It is a telecom spec. regards, Gerhard ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] low noise multiplication to 100 MHz
b...@hsmicrowave.com said: > Aaah - but then you need a microprocessor (and its noise if you're not > careful) to control it. IMHO - too complicated an approach. Yes, but you don't need many smarts to send a few bits to configure a PLL chip. You can get low end microprocessors in 8 pin packages. They don't even need an external clock or crystal, just a bypass cap. If you are concerned about noise, they can go into deep sleep mode. Most of them have really low power modes designed so that the battery for a chip can run close to shelf life. -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] Z3801 misbehaving
After running continuously for about 3 years at work, I stored my Z3801 for a little over a year. I recently took it out of storage and when I hooked it up, all I get is a power on light. The front panel LEDs light in sequence and the 6 inside blink red once and then the last one blinks continuously as always. Thing is, it never locks on GPS. I even left it on over night. When run on 27 volts, it starts out at about 1.1 amps, then after about 10 minutes, goes up to 1.26 amps. Then, after about 30 more minutes, it settles down to .88 amps and stays there. The OCXO gets warm. I haven't checked for 10 MHz out, but I am pretty sure it is there. I hooked it up to my netbook but I get no response from it at all. I am using one of those USB to serial devices and it used to work. I am looking for a PC with a real serial port to try. I know the antenna is good. It works with one of those Symmetricom GPSDO cards. Having heard about the evils of tantalum capacitors for years, I replaced them all except for those on the GPS receiver board itself. All the test points that call out a voltage read correctly. I'm thinking of trying a new GPS board next. I have had this thing a long time and it has always just worked. Any ideas what the problem is? ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Generating a solid PPS from 10Mhz source - finetuned start
Hi > On Jan 25, 2016, at 8:55 AM, Xavier Bestel wrote: > > Hi Guys, > > Le mercredi 13 janvier 2016 à 09:22 +, Jerome Blaha a écrit : >> Hey Guys, >> >> Is there an easy circuit to build that can consistently deliver a 1 >> PPS from a 10MHz source with excellent resolution and >> repeatability? My first application is to test different 10MHz >> oscillators without a TIC always attached and then compare the PPS >> output change over time against a master GPSDO PPS with an HP53132A. >> >> The circuit used for PPS generation would have to deliver consistent >> PPS output with preferably not more than 100ps noise or jitter, >> assuming a perfect source. I'm totally guessing that for this >> resolution, the PPS would have to be generated and accurate to within >> 0.001Hz every second. If this is too difficult, maybe the >> integration time can be increased to generate one pulse every >> 10second or every 100,000,000.00 cycles? >> >> Finally, is a square 10Mhz reference any better in this case than a >> sinusoidal input for generating the PPS? > > What would it take to make that PPS adjustable with a step <= 1ns ? > I see that the PIC solution has a mean of "arming" the 1PPS to let it > start at the desired time, but the granularity would be of course > 10MHz. For example are there easy-to-use programmable delays to reach > the missing precision ? The question is (as always) why? If you are trying to get to low temperature coef and low jitter and good long term stability …. No, they really aren’t good enough. Bob > > Xav > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] low noise multiplication to 100 MHz
Aaah - but then you need a microprocessor (and its noise if you're not careful) to control it. IMHO - too complicated an approach. Hard to beat a "careful" straight multiplier approach for simple or a phased locked 100 MHz VCXO for the best phase noise. Bill - N6GHz On 1/25/2016 9:20 AM, Graham / KE9H wrote: There are clock distribution parts designed to do this low noise frequency conversion and distribution. Consider TI LMK04100 Ignore PLL1 Put your 10 MHz as the reference input to PLL2. Set Internal VCO to ~1200 MHz Set the internal dividers to get 100 MHz out, and 10 MHz back to the PLL2 phase detector. Get reasonable noise and 100 MHz output with your choice of 2VPECL, LVDS, LVCMOS output levels. If you have a dirty input clock/reference, or multiple sources, you can use PLL1 and an external crystal in a VCO to clean it up before you multiply it to 1200 MHz. And you can get up to four other frequencies out of the part at the same time. 150 fs class jitter. $13 cost, quantity one. --- Graham == On Mon, Jan 25, 2016 at 9:22 AM, Bert Kehren via time-nuts < time-nuts@febo.com> wrote: If not good enough an XOR with filter and one of the Crystek VCXO's previously mentioned may do it. Bert Kehren In a message dated 1/25/2016 10:01:33 A.M. Eastern Standard Time, mag...@rubidium.dyndns.org writes: Also, it will be systematic, with idle tones. Because of the delay elements used, they will not be long-term static but move around. I agree, this is quite noisy. If the noise is tolerable, it is indeed a small solution. 100 ps 1-sigma for 5 MHz in 100 MHz out isn't what I would consider low. https://www.idt.com/document/dst/570-datasheet Cheers, Magnus On 01/24/2016 11:12 PM, Bruce Griffiths wrote: Unfortunately the ICS570 (like all zero delay buffers) has an output jitter approaching about 1000 times the likely RF ADC internal sampling jitter. The resultant SNR degradation may be a little excessive for this application.. Bruce On Monday, 25 January 2016 11:00 AM, Bert Kehren via time-nuts wrote: With all the discussions in a small 100 MHz source I asked my project partner Juerg in Switzerland to run some data on the ICS 570 that we use on the majority of our projects with excellent results. Using the HP53132A we see + - 1 count at E10-11 ignore the large jumps those come from the Tbolt frequency change to correct the 1 pps. Depending on the application this is an excellent device. Bert Kehren In a message dated 1/23/2016 6:02:23 P.M. Eastern Standard Time, dk...@arcor.de writes: Am 22.01.2016 um 22:40 schrieb jimlux: the oscillator is a HCMOS output, so figure swinging about 3.5V Output.. I'm feeding differential clock inputs on ADCs. I'll bet a +/- 300mV swing would work. 4)Title said "Low Noise" needs better definition as to what kind of noise and how far down. Are we to be concerned about harmonic and spur content as compared to real random white noise? This is time-nuts.. it has to be perfect.. But realistically, my source is probably going to be about -90dBc/Hz at 1 Hz, -125 at 10Hz, -145 at 100 Hz. I'm going up by a factor of 10, so I'd expect 20 dB worse plus a little..(nothing is perfect, eh?) Call it maybe -100 to -95 at 10 Hz, -125 to -120 at 100 Hz and so forth. harmonics are interesting: it's the sample clock into an ADC. So harmonics of the 100 aren't a big deal. harmonics of the 10 or 20 are. If you have significant 90 or 110 contaminating the 100, then you get weird spurs.. (I had this problem on a software radio where the 50 MHz sample clock was contaminated with some 66 MHz from the CPU) Spurs cause the same issues. ON the other hand... spurs that are pretty low don't make much difference if you're digitizing a signal that is close to the noise floor: the spur multiplied by the desired signal is usually lower and down in the noise. Strong CW in band signals, though, are a real pain. < https://picasaweb.google.com/103357048842463945642/Tronix#607927018804883377 8 I think that top left board would not be far away: in : 10 MHz LVDS or CMOS in: 3V3 out: 100 MHz CMOS 3V3 just a few hours wall clock time from layout to working as a ham radio weekender, so please excuse my diy home board production process. Ok, the use of a 4046 descendant may not be the last word from a timenut perspective, but I'll redo it with an osc of my own anyway. Divider 100/10 is a LVC163 (161?) + lvc04. < http://www.crystek.com/crystal/spec-sheets/vcxo/CVHD-950.pdf > Digi-Key has 153 of them on a tape and 441 of a similar one , even cheaper that seems to point to the same data sheet. < http://www.digikey.de/product-detail/de/CVHD-950-100.000/744-1213-ND/1644128 You can get the few dB missing close-in by transfer from your reference. In the picture: The bottom row of boards is a doubler 100->200 MHz using 2*BF862, slight gain,
Re: [time-nuts] low noise multiplication to 100 MHz
There are clock distribution parts designed to do this low noise frequency conversion and distribution. Consider TI LMK04100 Ignore PLL1 Put your 10 MHz as the reference input to PLL2. Set Internal VCO to ~1200 MHz Set the internal dividers to get 100 MHz out, and 10 MHz back to the PLL2 phase detector. Get reasonable noise and 100 MHz output with your choice of 2VPECL, LVDS, LVCMOS output levels. If you have a dirty input clock/reference, or multiple sources, you can use PLL1 and an external crystal in a VCO to clean it up before you multiply it to 1200 MHz. And you can get up to four other frequencies out of the part at the same time. 150 fs class jitter. $13 cost, quantity one. --- Graham == On Mon, Jan 25, 2016 at 9:22 AM, Bert Kehren via time-nuts < time-nuts@febo.com> wrote: > If not good enough an XOR with filter and one of the Crystek VCXO's > previously mentioned may do it. > Bert Kehren > > > In a message dated 1/25/2016 10:01:33 A.M. Eastern Standard Time, > mag...@rubidium.dyndns.org writes: > > Also, it will be systematic, with idle tones. Because of the delay > elements used, they will not be long-term static but move around. > > I agree, this is quite noisy. If the noise is tolerable, it is indeed a > small solution. 100 ps 1-sigma for 5 MHz in 100 MHz out isn't what I > would consider low. > > https://www.idt.com/document/dst/570-datasheet > > Cheers, > Magnus > > On 01/24/2016 11:12 PM, Bruce Griffiths wrote: > > Unfortunately the ICS570 (like all zero delay buffers) has an output > jitter approaching about 1000 times the likely RF ADC internal sampling > jitter. The resultant SNR degradation may be a little excessive for this > application.. > > Bruce > > > > > > On Monday, 25 January 2016 11:00 AM, Bert Kehren via time-nuts > wrote: > > > > > > With all the discussions in a small 100 MHz source I asked my project > > partner Juerg in Switzerland to run some data on the ICS 570 that we use > on the > > majority of our projects with excellent results. Using the HP53132A we > see > > > + - 1 count at E10-11 ignore the large jumps those come from the Tbolt > > frequency change to correct the 1 pps. Depending on the application > this is an > > excellent device. > > Bert Kehren > > > > > > In a message dated 1/23/2016 6:02:23 P.M. Eastern Standard Time, > > dk...@arcor.de writes: > > > > Am 22.01.2016 um 22:40 schrieb jimlux: > >> the oscillator is a HCMOS output, so figure swinging about 3.5V > >> Output.. I'm feeding differential clock inputs on ADCs. I'll bet a > >> +/- 300mV swing would work. > >> > >>> 4)Title said "Low Noise" needs better definition as to what kind of > >>> noise and how far down. Are we to be concerned about harmonic and > spur > >>> content as compared to real random white noise? > >> > >> This is time-nuts.. it has to be perfect.. > >> > >> But realistically, my source is probably going to be about -90dBc/Hz > >> at 1 Hz, -125 at 10Hz, -145 at 100 Hz. I'm going up by a factor of > >> 10, so I'd expect 20 dB worse plus a little..(nothing is perfect, > eh?) > >> > >> Call it maybe -100 to -95 at 10 Hz, -125 to -120 at 100 Hz and so > forth. > >> > >> harmonics are interesting: it's the sample clock into an ADC. So > >> harmonics of the 100 aren't a big deal. harmonics of the 10 or 20 > >> are. If you have significant 90 or 110 contaminating the 100, then > >> you get weird spurs.. (I had this problem on a software radio where > >> the 50 MHz sample clock was contaminated with some 66 MHz from the > CPU) > >> > >> Spurs cause the same issues. > >> > >> ON the other hand... spurs that are pretty low don't make much > >> difference if you're digitizing a signal that is close to the noise > >> floor: the spur multiplied by the desired signal is usually lower and > >> down in the noise. Strong CW in band signals, though, are a real > pain. > >> > >> > > < > > > > https://picasaweb.google.com/103357048842463945642/Tronix#607927018804883377 > > 8 > >> > > > > I think that top left board would not be far away: > > > > in : 10 MHz LVDS or CMOS > > in: 3V3 > > out: 100 MHz CMOS 3V3 > > > > just a few hours wall clock time from layout to working as a > > ham radio weekender, so please excuse my diy home board > > production process. > > > > Ok, the use of a 4046 descendant may not be the last word > > from a timenut perspective, but I'll redo it with an osc of > > my own anyway. Divider 100/10 is a LVC163 (161?) + lvc04. > > > > > > < http://www.crystek.com/crystal/spec-sheets/vcxo/CVHD-950.pdf > > > > > Digi-Key has 153 of them on a tape and 441 of a similar one , even > > cheaper that seems to point to the same data sheet. > > > > < > > > > http://www.digikey.de/product-detail/de/CVHD-950-100.000/744-1213-ND/1644128 > > > >> > > You can get the few dB missing close-in by transfer from your > reference. > > > > In the picture: > > The bottom row of boards
[time-nuts] LEDs as non-linear photo-detectors
Moin, Just to spice up the discussion of LEDs and their photo-sensitivity, I would like to point you at the bachelor thess of Aljunid[1] where he used LEDs as replacement for photodiodes in a michelson interferometer style pulsewidth autocorellation setup to measure femtosecond pulses. Attila Kinali [1] "Optical Autocorrelation using Non-Linearity in a Simple Photodiode", by Syed Abdullah Aljunid, 2007 http://qolah.org/thesis/thesis-syed.pdf -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] HP5370B & HP5345B Front-End IC Redesign Effort
I would imagine it was much less expensive for HP to gut second hand equipment and re-qualify it than restart a fab or qualify a new design front end. On 25 Jan 2016 16:01, "Bert Kehren via time-nuts" wrote: > Getting back to the original question, years ago I was told but could not > confirm that HP was buying up 5345's because of a Government commitment to > replace front ends. If they had to go to such matters I doubt we will be > able to find a solution. > In my home counter work I tried but ended up using boards out of 5345's > Bert Kehren > > > In a message dated 1/25/2016 10:01:18 A.M. Eastern Standard Time, > bruce.griffi...@xtra.co.nz writes: > > I've been considering this for some time.The key is the replacement for > the triggered phase locked oscillator based interpolators. > FPGA based TDCs aren't yet quite good enough. > Off the shelf TDC chips are a little better but still fall a little short > in performance. > > Whilst a TAC approach can achieve around 4ps or so (eg various Wavecrest > instruments) a lot of discrete parts are likely to be required. > > My crude testing of a triggered damped sinewave generator sampled by an RF > ADC indicates that an event time stamp noise of 5ps or better appears > feasible. > > The technique of exciting a high Q saw bandpass filter with an impulse and > digitising the output is probably more expensive and complex than > desirable. > > Bruce > > > On Monday, 25 January 2016 6:04 PM, Bob Camp wrote: > > > Hi > > Since the front end chips are mixed signal ASIC’s, it will take more than > a bit of time to > replace them directly. Re-doing the entire front panel board is the most > likely way to “fix” > the problem. The question is - why do that at all? Just do a PC instrument > that does the same > thing as the counter with way less effort….. > > Bob > > > > On Jan 24, 2016, at 6:02 PM, Dimitri.p wrote: > > > > Someday , someone will get bored with everything else and give it a try, > you know, in their spare time. > > The time when these counter were new was a long while ago. > > Back then an amplifier chip with 500MHZ BW was a much bigger deal than > it is in 2016. > > ...but spare time is permanently on backorder :) > > > > Dimitri > > > > At 06:15 AM 1/24/2016, Bob Camp wrote: > >> Hi > >> > >> Back when these counters (5345, 5370, 5335) all were new, the inputs > were > >> the weak link on all of them. There were known âdonât do thatâ things > on the line > >> that would blow out each of them. Regardless of the level of care and > yelling, inputs > >> blew on a fairly regular basis. Probably 10% of the counters went back > >> for repair over a 5 year period. It was always a âswap out the entire > boardâ sort > >> of repair and never was under $1K. We regularly spent the price of a > new counter > >> each year on repairs. If there had been an easy way to fix them, (or > even to just > >> pay $500 for the chip) we would have done it. > >> > >> Bob > >> > >> > On Jan 24, 2016, at 8:34 AM, Dale Cannon > wrote: > >> > > >> > Funny, > >> > > >> > A friend asked me if I could replicate the front end for a 5370A, a > many > >> > years back. I related to him that replicating the input chip was not > a > >> > trivial task. His 5370A had been used (by someone else) for direct > testing > >> > of controlled-motion DC motors and the front end had obviously been > >> > overstressed by voltage spiking. At the time, I had considered > replicating > >> > the front-end probe circuit of a K100D logic analyzer: FET diff. pair > >> > followed by an ECL 10216 line driver. Obviously most daughterboard or > dead > >> > bug modification approaches have downsides; in the end I just > couldn't cut > >> > up the HP front end and told him to search for a more qualified > repair > >> > facility. > >> > > >> > BAMA boat anchors has the K100D manual and probe schematic. > >> > > >> > Dale Cannon KS4FA > >> > > >> > > >> > -Original Message- > >> > From: time-nuts [mailto:time-nuts-boun...@febo.com] On Behalf Of > Mathew > >> > Breton > >> > Sent: Friday, January 22, 2016 5:15 PM > >> > To: time-nuts@febo.com > >> > Subject: [time-nuts] HP5370B & HP5345B Front-End IC Redesign Effort > >> > > >> > I was gifted an HP 5370B with the usual problem: front-end problems, > >> > probably due to overstress. It is currently up and running again with > a set > >> > of 5345A series A3/A4 boards as I wasn't able to get a cheap pair of > >> > 5088-706x hybrid ICs. > >> > This sounds like a common problem. As a result, I'm designing an > open-source > >> > drop-in (hopefully) replacement. My hat is off to the original IC > designer, > >> > as it is not a trivial effort due to the wide input signal > common-mode > >> > range, and very tight trigger timing requirements. Other items (like > the > >> > E-ECL) output) are also adding a bit of extra effort. > >> > I'm hoping that someone(s) might be interested
Re: [time-nuts] HP5370B & HP5345B Front-End IC Redesign Effort
Hello to the group. Lots to learn. eecl? :-) Heck happy to get ecl working. That said I did pull the manuals on the 5370 and 5345. They are the same front end. And really 1 magical chip. OK now I am going to super over simplify the issue. Forgetting the nice features, why wouldn't the first step be to simply create a sine to square wave converter? But a dead frontend makes the counter useless. So getting a signal past it is useful even if its not the exact quality of what existed. Does that simplify at least the first possible answer. Regards Paul WB8TSL. On Mon, Jan 25, 2016 at 10:32 AM, Bert Kehren via time-nuts < time-nuts@febo.com> wrote: > Getting back to the original question, years ago I was told but could not > confirm that HP was buying up 5345's because of a Government commitment to > replace front ends. If they had to go to such matters I doubt we will be > able to find a solution. > In my home counter work I tried but ended up using boards out of 5345's > Bert Kehren > > > In a message dated 1/25/2016 10:01:18 A.M. Eastern Standard Time, > bruce.griffi...@xtra.co.nz writes: > > I've been considering this for some time.The key is the replacement for > the triggered phase locked oscillator based interpolators. > FPGA based TDCs aren't yet quite good enough. > Off the shelf TDC chips are a little better but still fall a little short > in performance. > > Whilst a TAC approach can achieve around 4ps or so (eg various Wavecrest > instruments) a lot of discrete parts are likely to be required. > > My crude testing of a triggered damped sinewave generator sampled by an RF > ADC indicates that an event time stamp noise of 5ps or better appears > feasible. > > The technique of exciting a high Q saw bandpass filter with an impulse and > digitising the output is probably more expensive and complex than > desirable. > > Bruce > > > On Monday, 25 January 2016 6:04 PM, Bob Camp wrote: > > > Hi > > Since the front end chips are mixed signal ASIC’s, it will take more than > a bit of time to > replace them directly. Re-doing the entire front panel board is the most > likely way to “fix” > the problem. The question is - why do that at all? Just do a PC instrument > that does the same > thing as the counter with way less effort….. > > Bob > > > > On Jan 24, 2016, at 6:02 PM, Dimitri.p wrote: > > > > Someday , someone will get bored with everything else and give it a try, > you know, in their spare time. > > The time when these counter were new was a long while ago. > > Back then an amplifier chip with 500MHZ BW was a much bigger deal than > it is in 2016. > > ...but spare time is permanently on backorder :) > > > > Dimitri > > > > At 06:15 AM 1/24/2016, Bob Camp wrote: > >> Hi > >> > >> Back when these counters (5345, 5370, 5335) all were new, the inputs > were > >> the weak link on all of them. There were known âdonât do thatâ things > on the line > >> that would blow out each of them. Regardless of the level of care and > yelling, inputs > >> blew on a fairly regular basis. Probably 10% of the counters went back > >> for repair over a 5 year period. It was always a âswap out the entire > boardâ sort > >> of repair and never was under $1K. We regularly spent the price of a > new counter > >> each year on repairs. If there had been an easy way to fix them, (or > even to just > >> pay $500 for the chip) we would have done it. > >> > >> Bob > >> > >> > On Jan 24, 2016, at 8:34 AM, Dale Cannon > wrote: > >> > > >> > Funny, > >> > > >> > A friend asked me if I could replicate the front end for a 5370A, a > many > >> > years back. I related to him that replicating the input chip was not > a > >> > trivial task. His 5370A had been used (by someone else) for direct > testing > >> > of controlled-motion DC motors and the front end had obviously been > >> > overstressed by voltage spiking. At the time, I had considered > replicating > >> > the front-end probe circuit of a K100D logic analyzer: FET diff. pair > >> > followed by an ECL 10216 line driver. Obviously most daughterboard or > dead > >> > bug modification approaches have downsides; in the end I just > couldn't cut > >> > up the HP front end and told him to search for a more qualified > repair > >> > facility. > >> > > >> > BAMA boat anchors has the K100D manual and probe schematic. > >> > > >> > Dale Cannon KS4FA > >> > > >> > > >> > -Original Message- > >> > From: time-nuts [mailto:time-nuts-boun...@febo.com] On Behalf Of > Mathew > >> > Breton > >> > Sent: Friday, January 22, 2016 5:15 PM > >> > To: time-nuts@febo.com > >> > Subject: [time-nuts] HP5370B & HP5345B Front-End IC Redesign Effort > >> > > >> > I was gifted an HP 5370B with the usual problem: front-end problems, > >> > probably due to overstress. It is currently up and running again with > a set > >> > of 5345A series A3/A4 boards as I wasn't able to get a cheap pair of > >> > 5088-706x hybrid ICs. > >> > T
Re: [time-nuts] HP5370B & HP5345B Front-End IC Redesign Effort
Getting back to the original question, years ago I was told but could not confirm that HP was buying up 5345's because of a Government commitment to replace front ends. If they had to go to such matters I doubt we will be able to find a solution. In my home counter work I tried but ended up using boards out of 5345's Bert Kehren In a message dated 1/25/2016 10:01:18 A.M. Eastern Standard Time, bruce.griffi...@xtra.co.nz writes: I've been considering this for some time.The key is the replacement for the triggered phase locked oscillator based interpolators. FPGA based TDCs aren't yet quite good enough. Off the shelf TDC chips are a little better but still fall a little short in performance. Whilst a TAC approach can achieve around 4ps or so (eg various Wavecrest instruments) a lot of discrete parts are likely to be required. My crude testing of a triggered damped sinewave generator sampled by an RF ADC indicates that an event time stamp noise of 5ps or better appears feasible. The technique of exciting a high Q saw bandpass filter with an impulse and digitising the output is probably more expensive and complex than desirable. Bruce On Monday, 25 January 2016 6:04 PM, Bob Camp wrote: Hi Since the front end chips are mixed signal ASIC’s, it will take more than a bit of time to replace them directly. Re-doing the entire front panel board is the most likely way to “fix” the problem. The question is - why do that at all? Just do a PC instrument that does the same thing as the counter with way less effort….. Bob > On Jan 24, 2016, at 6:02 PM, Dimitri.p wrote: > > Someday , someone will get bored with everything else and give it a try, you know, in their spare time. > The time when these counter were new was a long while ago. > Back then an amplifier chip with 500MHZ BW was a much bigger deal than it is in 2016. > ...but spare time is permanently on backorder :) > > Dimitri > > At 06:15 AM 1/24/2016, Bob Camp wrote: >> Hi >> >> Back when these counters (5345, 5370, 5335) all were new, the inputs were >> the weak link on all of them. There were known âdonât do thatâ things on the line >> that would blow out each of them. Regardless of the level of care and yelling, inputs >> blew on a fairly regular basis. Probably 10% of the counters went back >> for repair over a 5 year period. It was always a âswap out the entire boardâ sort >> of repair and never was under $1K. We regularly spent the price of a new counter >> each year on repairs. If there had been an easy way to fix them, (or even to just >> pay $500 for the chip) we would have done it. >> >> Bob >> >> > On Jan 24, 2016, at 8:34 AM, Dale Cannon wrote: >> > >> > Funny, >> > >> > A friend asked me if I could replicate the front end for a 5370A, a many >> > years back. I related to him that replicating the input chip was not a >> > trivial task. His 5370A had been used (by someone else) for direct testing >> > of controlled-motion DC motors and the front end had obviously been >> > overstressed by voltage spiking. At the time, I had considered replicating >> > the front-end probe circuit of a K100D logic analyzer: FET diff. pair >> > followed by an ECL 10216 line driver. Obviously most daughterboard or dead >> > bug modification approaches have downsides; in the end I just couldn't cut >> > up the HP front end and told him to search for a more qualified repair >> > facility. >> > >> > BAMA boat anchors has the K100D manual and probe schematic. >> > >> > Dale Cannon KS4FA >> > >> > >> > -Original Message- >> > From: time-nuts [mailto:time-nuts-boun...@febo.com] On Behalf Of Mathew >> > Breton >> > Sent: Friday, January 22, 2016 5:15 PM >> > To: time-nuts@febo.com >> > Subject: [time-nuts] HP5370B & HP5345B Front-End IC Redesign Effort >> > >> > I was gifted an HP 5370B with the usual problem: front-end problems, >> > probably due to overstress. It is currently up and running again with a set >> > of 5345A series A3/A4 boards as I wasn't able to get a cheap pair of >> > 5088-706x hybrid ICs. >> > This sounds like a common problem. As a result, I'm designing an open-source >> > drop-in (hopefully) replacement. My hat is off to the original IC designer, >> > as it is not a trivial effort due to the wide input signal common-mode >> > range, and very tight trigger timing requirements. Other items (like the >> > E-ECL) output) are also adding a bit of extra effort. >> > I'm hoping that someone(s) might be interested in working with me on it. I >> > would like to have my assumptions and math checked before I start the >> > detailed design phase, and perhaps contribute some better ideas. >> > In addition, it would be really helpful if someone could run a few rise-time >> > dispersion tests on an instrument with a working "B"-series A3/A4 PCB set >> > (my unit obviously doesn't qualify). >> > Regards, >>
Re: [time-nuts] low noise multiplication to 100 MHz
If not good enough an XOR with filter and one of the Crystek VCXO's previously mentioned may do it. Bert Kehren In a message dated 1/25/2016 10:01:33 A.M. Eastern Standard Time, mag...@rubidium.dyndns.org writes: Also, it will be systematic, with idle tones. Because of the delay elements used, they will not be long-term static but move around. I agree, this is quite noisy. If the noise is tolerable, it is indeed a small solution. 100 ps 1-sigma for 5 MHz in 100 MHz out isn't what I would consider low. https://www.idt.com/document/dst/570-datasheet Cheers, Magnus On 01/24/2016 11:12 PM, Bruce Griffiths wrote: > Unfortunately the ICS570 (like all zero delay buffers) has an output jitter approaching about 1000 times the likely RF ADC internal sampling jitter. The resultant SNR degradation may be a little excessive for this application.. > Bruce > > > On Monday, 25 January 2016 11:00 AM, Bert Kehren via time-nuts wrote: > > > With all the discussions in a small 100 MHz source I asked my project > partner Juerg in Switzerland to run some data on the ICS 570 that we use on the > majority of our projects with excellent results. Using the HP53132A we see > + - 1 count at E10-11 ignore the large jumps those come from the Tbolt > frequency change to correct the 1 pps. Depending on the application this is an > excellent device. > Bert Kehren > > > In a message dated 1/23/2016 6:02:23 P.M. Eastern Standard Time, > dk...@arcor.de writes: > > Am 22.01.2016 um 22:40 schrieb jimlux: >> the oscillator is a HCMOS output, so figure swinging about 3.5V >> Output.. I'm feeding differential clock inputs on ADCs. I'll bet a >> +/- 300mV swing would work. >> >>> 4)Title said "Low Noise" needs better definition as to what kind of >>> noise and how far down. Are we to be concerned about harmonic and spur >>> content as compared to real random white noise? >> >> This is time-nuts.. it has to be perfect.. >> >> But realistically, my source is probably going to be about -90dBc/Hz >> at 1 Hz, -125 at 10Hz, -145 at 100 Hz. I'm going up by a factor of >> 10, so I'd expect 20 dB worse plus a little..(nothing is perfect, eh?) >> >> Call it maybe -100 to -95 at 10 Hz, -125 to -120 at 100 Hz and so forth. >> >> harmonics are interesting: it's the sample clock into an ADC. So >> harmonics of the 100 aren't a big deal. harmonics of the 10 or 20 >> are. If you have significant 90 or 110 contaminating the 100, then >> you get weird spurs.. (I had this problem on a software radio where >> the 50 MHz sample clock was contaminated with some 66 MHz from the CPU) >> >> Spurs cause the same issues. >> >> ON the other hand... spurs that are pretty low don't make much >> difference if you're digitizing a signal that is close to the noise >> floor: the spur multiplied by the desired signal is usually lower and >> down in the noise. Strong CW in band signals, though, are a real pain. >> >> > < > https://picasaweb.google.com/103357048842463945642/Tronix#607927018804883377 > 8 >> > > I think that top left board would not be far away: > > in : 10 MHz LVDS or CMOS > in: 3V3 > out: 100 MHz CMOS 3V3 > > just a few hours wall clock time from layout to working as a > ham radio weekender, so please excuse my diy home board > production process. > > Ok, the use of a 4046 descendant may not be the last word > from a timenut perspective, but I'll redo it with an osc of > my own anyway. Divider 100/10 is a LVC163 (161?) + lvc04. > > > < http://www.crystek.com/crystal/spec-sheets/vcxo/CVHD-950.pdf > > > Digi-Key has 153 of them on a tape and 441 of a similar one , even > cheaper that seems to point to the same data sheet. > > < > http://www.digikey.de/product-detail/de/CVHD-950-100.000/744-1213-ND/1644128 > >> > You can get the few dB missing close-in by transfer from your reference. > > In the picture: > The bottom row of boards is a doubler 100->200 MHz using 2*BF862, slight > gain, > and diode doubler 200 -> 400 MHz, SAW filter to get rid of > 100/200/300/500/600 +/-10 etc, > post amp to get a usable level again. > > Still missing 400-> 800, 800->1600 to feed _my_ ADC clock input.. > > regards, Gerhard > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > ___
[time-nuts] Generating a solid PPS from 10Mhz source - finetuned start
Hi Guys, Le mercredi 13 janvier 2016 à 09:22 +, Jerome Blaha a écrit : > Hey Guys, > > Is there an easy circuit to build that can consistently deliver a 1 > PPS from a 10MHz source with excellent resolution and > repeatability? My first application is to test different 10MHz > oscillators without a TIC always attached and then compare the PPS > output change over time against a master GPSDO PPS with an HP53132A. > > The circuit used for PPS generation would have to deliver consistent > PPS output with preferably not more than 100ps noise or jitter, > assuming a perfect source. I'm totally guessing that for this > resolution, the PPS would have to be generated and accurate to within > 0.001Hz every second. If this is too difficult, maybe the > integration time can be increased to generate one pulse every > 10second or every 100,000,000.00 cycles? > > Finally, is a square 10Mhz reference any better in this case than a > sinusoidal input for generating the PPS? What would it take to make that PPS adjustable with a step <= 1ns ? I see that the PIC solution has a mean of "arming" the 1PPS to let it start at the desired time, but the granularity would be of course 10MHz. For example are there easy-to-use programmable delays to reach the missing precision ? Xav ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] low noise multiplication to 100 MHz
Also, it will be systematic, with idle tones. Because of the delay elements used, they will not be long-term static but move around. I agree, this is quite noisy. If the noise is tolerable, it is indeed a small solution. 100 ps 1-sigma for 5 MHz in 100 MHz out isn't what I would consider low. https://www.idt.com/document/dst/570-datasheet Cheers, Magnus On 01/24/2016 11:12 PM, Bruce Griffiths wrote: Unfortunately the ICS570 (like all zero delay buffers) has an output jitter approaching about 1000 times the likely RF ADC internal sampling jitter. The resultant SNR degradation may be a little excessive for this application.. Bruce On Monday, 25 January 2016 11:00 AM, Bert Kehren via time-nuts wrote: With all the discussions in a small 100 MHz source I asked my project partner Juerg in Switzerland to run some data on the ICS 570 that we use on the majority of our projects with excellent results. Using the HP53132A we see + - 1 count at E10-11 ignore the large jumps those come from the Tbolt frequency change to correct the 1 pps. Depending on the application this is an excellent device. Bert Kehren In a message dated 1/23/2016 6:02:23 P.M. Eastern Standard Time, dk...@arcor.de writes: Am 22.01.2016 um 22:40 schrieb jimlux: the oscillator is a HCMOS output, so figure swinging about 3.5V Output.. I'm feeding differential clock inputs on ADCs. I'll bet a +/- 300mV swing would work. 4)Title said "Low Noise" needs better definition as to what kind of noise and how far down. Are we to be concerned about harmonic and spur content as compared to real random white noise? This is time-nuts.. it has to be perfect.. But realistically, my source is probably going to be about -90dBc/Hz at 1 Hz, -125 at 10Hz, -145 at 100 Hz. I'm going up by a factor of 10, so I'd expect 20 dB worse plus a little..(nothing is perfect, eh?) Call it maybe -100 to -95 at 10 Hz, -125 to -120 at 100 Hz and so forth. harmonics are interesting: it's the sample clock into an ADC. So harmonics of the 100 aren't a big deal. harmonics of the 10 or 20 are. If you have significant 90 or 110 contaminating the 100, then you get weird spurs.. (I had this problem on a software radio where the 50 MHz sample clock was contaminated with some 66 MHz from the CPU) Spurs cause the same issues. ON the other hand... spurs that are pretty low don't make much difference if you're digitizing a signal that is close to the noise floor: the spur multiplied by the desired signal is usually lower and down in the noise. Strong CW in band signals, though, are a real pain. < https://picasaweb.google.com/103357048842463945642/Tronix#607927018804883377 8 I think that top left board would not be far away: in : 10 MHz LVDS or CMOS in: 3V3 out: 100 MHz CMOS 3V3 just a few hours wall clock time from layout to working as a ham radio weekender, so please excuse my diy home board production process. Ok, the use of a 4046 descendant may not be the last word from a timenut perspective, but I'll redo it with an osc of my own anyway. Divider 100/10 is a LVC163 (161?) + lvc04. < http://www.crystek.com/crystal/spec-sheets/vcxo/CVHD-950.pdf > Digi-Key has 153 of them on a tape and 441 of a similar one , even cheaper that seems to point to the same data sheet. < http://www.digikey.de/product-detail/de/CVHD-950-100.000/744-1213-ND/1644128 You can get the few dB missing close-in by transfer from your reference. In the picture: The bottom row of boards is a doubler 100->200 MHz using 2*BF862, slight gain, and diode doubler 200 -> 400 MHz, SAW filter to get rid of 100/200/300/500/600 +/-10 etc, post amp to get a usable level again. Still missing 400-> 800, 800->1600 to feed _my_ ADC clock input.. regards, Gerhard ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] Schlumberger FA2527 ocxo
Hi group, Does anyone know something about the Schlumberger type FA2527 5MHz OCXO? It seems to be a good unit, with mumetal shield, coarse and fine frequency adj multiturn pots, fine temperature trimmer, good voltage regulator, good assembly and internal cylindrical thermal chamber surronded by a wire resistence (double oven?). It was used in Schlumberger electronic counters in the seventies or eighties as a high stability option. I'm trying to understand pin out and supply voltage, but I wish to know some more information about functions of pins, and specifications. Nothing found on the net. Thank you in advance! Luca iw2lje Milano ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] HP5370B & HP5345B Front-End IC Redesign Effort
I've been considering this for some time.The key is the replacement for the triggered phase locked oscillator based interpolators. FPGA based TDCs aren't yet quite good enough. Off the shelf TDC chips are a little better but still fall a little short in performance. Whilst a TAC approach can achieve around 4ps or so (eg various Wavecrest instruments) a lot of discrete parts are likely to be required. My crude testing of a triggered damped sinewave generator sampled by an RF ADC indicates that an event time stamp noise of 5ps or better appears feasible. The technique of exciting a high Q saw bandpass filter with an impulse and digitising the output is probably more expensive and complex than desirable. Bruce On Monday, 25 January 2016 6:04 PM, Bob Camp wrote: Hi Since the front end chips are mixed signal ASIC’s, it will take more than a bit of time to replace them directly. Re-doing the entire front panel board is the most likely way to “fix” the problem. The question is - why do that at all? Just do a PC instrument that does the same thing as the counter with way less effort….. Bob > On Jan 24, 2016, at 6:02 PM, Dimitri.p wrote: > > Someday , someone will get bored with everything else and give it a try, you > know, in their spare time. > The time when these counter were new was a long while ago. > Back then an amplifier chip with 500MHZ BW was a much bigger deal than it is > in 2016. > ...but spare time is permanently on backorder :) > > Dimitri > > At 06:15 AM 1/24/2016, Bob Camp wrote: >> Hi >> >> Back when these counters (5345, 5370, 5335) all were new, the inputs were >> the weak link on all of them. There were known âdonât do thatâ things on the >> line >> that would blow out each of them. Regardless of the level of care and >> yelling, inputs >> blew on a fairly regular basis. Probably 10% of the counters went back >> for repair over a 5 year period. It was always a âswap out the entire boardâ >> sort >> of repair and never was under $1K. We regularly spent the price of a new >> counter >> each year on repairs. If there had been an easy way to fix them, (or even >> to just >> pay $500 for the chip) we would have done it. >> >> Bob >> >> > On Jan 24, 2016, at 8:34 AM, Dale Cannon wrote: >> > >> > Funny, >> > >> > A friend asked me if I could replicate the front end for a 5370A, a many >> > years back. I related to him that replicating the input chip was not a >> > trivial task. His 5370A had been used (by someone else) for direct testing >> > of controlled-motion DC motors and the front end had obviously been >> > overstressed by voltage spiking. At the time, I had considered replicating >> > the front-end probe circuit of a K100D logic analyzer: FET diff. pair >> > followed by an ECL 10216 line driver. Obviously most daughterboard or dead >> > bug modification approaches have downsides; in the end I just couldn't cut >> > up the HP front end and told him to search for a more qualified repair >> > facility. >> > >> > BAMA boat anchors has the K100D manual and probe schematic. >> > >> > Dale Cannon KS4FA >> > >> > >> > -Original Message- >> > From: time-nuts [mailto:time-nuts-boun...@febo.com] On Behalf Of Mathew >> > Breton >> > Sent: Friday, January 22, 2016 5:15 PM >> > To: time-nuts@febo.com >> > Subject: [time-nuts] HP5370B & HP5345B Front-End IC Redesign Effort >> > >> > I was gifted an HP 5370B with the usual problem: front-end problems, >> > probably due to overstress. It is currently up and running again with a set >> > of 5345A series A3/A4 boards as I wasn't able to get a cheap pair of >> > 5088-706x hybrid ICs. >> > This sounds like a common problem. As a result, I'm designing an >> > open-source >> > drop-in (hopefully) replacement. My hat is off to the original IC designer, >> > as it is not a trivial effort due to the wide input signal common-mode >> > range, and very tight trigger timing requirements. Other items (like the >> > E-ECL) output) are also adding a bit of extra effort. >> > I'm hoping that someone(s) might be interested in working with me on it. I >> > would like to have my assumptions and math checked before I start the >> > detailed design phase, and perhaps contribute some better ideas. >> > In addition, it would be really helpful if someone could run a few >> > rise-time >> > dispersion tests on an instrument with a working "B"-series A3/A4 PCB set >> > (my unit obviously doesn't qualify). >> > Regards, >> > Mat Breton >> > ___ >> > time-nuts mailing list -- time-nuts@febo.com >> > To unsubscribe, go to >> > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts >> > and follow the instructions there. >> > - >> > No virus found in this message. >> > Checked by AVG - www.avg.com >> > Version: 2016.0.7294 / Virus Database: 4492/11420 - Release Date: 01/17/16 >> > >> > ___ >> > time-nuts mailing list -- ti
