Re: [time-nuts] eLoran is up and operating. Looking good

2017-02-07 Thread Gary E. Miller
Yo Bob!

On Tue, 7 Feb 2017 21:38:52 -0500
Bob Camp  wrote:

> Teaching
> the NTP drivers when not to use the data and how to compare data is a
> do-able thing.  It’s just that nobody has ever bothered to do it.

The NTPsec team would love to work with anyone that has a device
that could use an improved NTP driver.

> Coming up with some simple to use tools to estimate the errors and
> config them in is likely the only practical way to do it.

NTPsec has done a lot of recent work on tools.  We are open to any
suggestions or requests that people may make.

RGDS
GARY
---
Gary E. Miller Rellim 109 NW Wilmington Ave., Suite E, Bend, OR 97703
g...@rellim.com  Tel:+1 541 382 8588

Veritas liberabit vos. -- Quid est veritas?
"If you can’t measure it, you can’t improve it." - Lord Kelvin
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Re: [time-nuts] eLoran is up and operating. Looking good

2017-02-07 Thread Bob Camp
Hi

A very practical contribution one *could* make would be to enhance the drivers 
for the radio based systems. Propagation is a big deal with any of the radio 
setups. Loran is no exception to that. Teaching the NTP drivers when not to
use the data and how to compare data is a do-able thing. It’s just that nobody
has ever bothered to do it. Coming up with some simple to use tools to estimate
the errors and config them in is likely the only practical way to do it.

Bob


> On Feb 7, 2017, at 12:10 AM, Ruslan Nabioullin  wrote:
> 
> On 02/06/2017 09:06 PM, Bob Camp wrote:
>>> On Feb 6, 2017, at 7:38 PM, Ruslan Nabioullin

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Re: [time-nuts] Sub-ps delay line

2017-02-07 Thread Magnus Danielson

Hi,

My first thought would be to use a pair of couplers before and after the 
delay line and bring it into a mixer to serve as a phase detector such 
that you can create a control loop to stabilize delay. This way you get 
a handle on the temperature variations.


There is trombone delays that can be used. They seem to reach that level 
of resolution.


There is microstepper boxes, but usually they operate on 5 or 10 MHz.

There is multiple ways to design delays for CW signals, microsteppers 
uses various forms of gear-boxes and programmable generators. Chips 
either use gate delays or programmable comparator vs. ramp of some form.

Ensuring temperature stability and drift limits is however always an issue.

Delay loop oscillator for calibration can be done, but biases can be 
problematic, so a number of different setups needs to be done to build 
confidence. It's a combinatorial exercise which is quite interesting.


Cheers,
Magnus

On 02/07/2017 05:13 PM, Mattia Rizzi wrote:

Hello,
I'm looking/designing a sub-ps delay line with very high stability.
Basically it has microwave requirements on phase matching.
The main features that such delay line should have are:
- sub-ps resolution and about 1 ns range
- High stability, must not drift more than 2ps/year, preferably 1ps/year
- Temperature coefficient (tempco) below 1 ps/celsius
- Low phase noise floor, target random jitter below 100 fs RSM from 100Hz
to 1MHz.
- flicker noise below -90dBc at 1Hz (100MHz carrier)
- cheap (below 50 euros) and PCB integrable
- optional: autocalibration or a way to check calibration health over time
(checking the oscillation frequency of the delay line connected as loop?)

Operating conditions: The delay line will be used for RF distribution,
where the clock signals (100-200MHz) must stay in +/- 10 ps error window.
Since timing jitter (wander) is 1.6ps RMS, the delay line must be very
accurate, with maximum of +/- 3ps of delay uncertainty. The delay line is
used to phase-match the  clock outputs at factory, hence will not be
anymore modified (or for only fine corrections, tens of picoseconds). The
factory calibration compensates for the delay line and PCB
process/production variations. The boards will operate at almost same
temperature and humidity levels over years of continuous running.

Circuit constrains: The delay line is fed with an AC-coupled LVPECL clock
output (only P output used) and should provides a single-ended AC clock
output signal.

Indeed, no commercial chip fits into these requirements.

My idea is to use an RC filter to delay the input clock signal and then to
restore the clock edges with a LTC6957-1 (LVPECL outputs).
The RC filter would be realized using a varactor (Skyworks SMVA1470-004LF)
and a 16-bit DAC to control the voltage bias (+ stable voltage reference).
I already checked the values, and sub-ps resolution seems easily
achievable. The solution requires a factory calibration due to the
non-linear behavior of the varactor, but since I only need small
adjustments, this is not a problem.

The problem is to guarantee the calibration over years of operation.
Since a femtofarad parasitic capacitance can change the delay, I already
thought about protecting the delay line with some kind of resin (Epoxy?)
and/or a RF cage to protect it from dirt and moisture.
One of the issue is aging. I derived a typical varactor aging from VCTCXO
oscillators (no varactor manufacturer knows the effects of aging on its
products, apparently) and it's still good. But the aging of LTC6957 is not
known.
Is the PCB fabrication using microwave requirements on the dielectric fine?

Based on your experience, do you think that such delay line can respect the
requirements listed above, especially stability?
Am I missing something?
Thank you!

cheers,
Mattia Rizzi
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Re: [time-nuts] Sub-ps delay line

2017-02-07 Thread David
I did something similar a couple years ago to make an adjustable 75
nanosecond pretrigger for my sampling oscilloscope so I will just pass
along some things I learned.

Power supply noise will create jitter in single ended logic because of
lack of power supply rejection.  Temperature will be a problem with
single ended logic also although I did not care about that.  The delay
section certainly needs to be differential which the LTC6957-1 neatly
covers; I was planning to use a comparator or line receiver next time
but the LTC6957-1 looks ideal.

With the above in mind, I would use a separate reference quality
regulator for the supply voltages and any reference levels.  I only
needed 10s of picosecond stability and picosecond level jitter but I
suspect at the level of precision you desire, ground loops need to be
avoided even through a solid ground plane.

How were you planning on testing the performance?

I need to give this further thought but if you only need 1ns worth of
control and feed one input of the LTC6957-1 with a 100 MHz sine wave,
wouldn't adjusting the level of the other input work to adjust the
delay at the output?
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Re: [time-nuts] Lucent KS-24361 REF 0 standalone

2017-02-07 Thread Thomas Petig
Hi,
Thank you for your reply.
As always, the solution appears after sending the mail on the list. I
send a wrong character for terminating the message and therefore the REF
0 was confused when the message ends (it expected 0x0D 0x0A, but got
0x0D 0xA0 from me).

It seems that in pForth, pr_gps_debug will count this as frame error.

Regarding my setup, I am sending the Oncore messages from Python via a
USB cable. I just trigger the Python script on the PPS, I don't read the
actual what the skytraq sends. It seems the REF 0 is happy with the
timing of my Oncore messages.

Regards,
   Thomas
   DK6KD
   SA6CID

On Mon, Feb 06, 2017 at 03:40:23PM -0500, Bob Camp wrote:
> Hi
>
> The only serial dialog between the two units is a repeat of the output of the
> GPS module. My guess is that there is some subtle difference between
> the Oncore data and they skytraq….
>
> Bob
>
> > On Feb 6, 2017, at 1:23 PM, Thomas Petig  wrote:
> >
> > Hi everyone,
> > I am currently trying to repeat previous work of members of this list in
> > convincing the REF 0, to run standalone with a given 1PPS signal from a
> > gps. Similar to:
> > https://syncchannel.blogspot.se/2015/08/standalone-operation-of-lucent-ks-24361.html
> >
> > I am using a skytraq gps with 100ms, 74AC04 for inverting and level
> > shifting and I added the jumper wires on J5. I simulate the Oncore
> > messages with a python script using a usb->uart cable and triggering on
> > the 1PPS pulse on the CTS line. I am sending @@Ea, @@En, @@Bb, @@Ap,
> > @@Aw, @@Ag, @@At, @@Az, @@Bj, @@Bo with a delay of 75 ms, as suggested
> > in the blog above:
> > https://github.com/thpe/oncore/blob/master/oncore_emu.py
> >
> > Surprisingly, I have a constant delay of 0.8 ms, and only a jitter of
> > +/-0.1 ms for the oncore messages compared to the pulse on the CTS line.
> >
> > Short everything is working and if I force external 1PPS usage it locks
> > to it (NO GPS light goes off). Using pForth:
> > 1 force_ext_1pps
> > 1 force_gps_1pps
> >
> > But, it does not do it on its own, since it ignores the tracking mode
> > for the satellites and, I guess after reading the Z3801A manual,
> > therefore it claims the GPS 1PPS signal as invalid. E.g., for the entry
> > with @@Ea:
> > 0x02, 0x08, 0xFF, 0x82
> > meaning satellite 2 in mode 8 (used for positioning) it assumes mode 0.
> > The other values, like signal strength 0xFF and channel status 0x82 are
> > taken, even if I change them to something else. The mode value is
> > ignored no matter what it says.
> >
> > In the attached files on sees that "GPS 1PPS Invalid: not tracking", and
> > the mode of the is 0. I forced it to use the external 1PPS signal.
> >
> > So, the question what tiny detail did I miss while reading the mailing
> > list archive and those blogs on how to set the REF 0 up for standalone
> > operation just using the Oncore messages?
> >
> > Does someone has dump of the communication between REF 1 and
> > REF 0, until the REF 0 is happy (I don't have a REF 1)?
> >
> > Regards,
> >   Thomas
> >   DK6KD
> >   SA6CID
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Re: [time-nuts] information about the Austron Synchronous Filter 2090A

2017-02-07 Thread Tom Van Baak
> Hi, any ideas on what the Austron Synchronous Filter 2090A is for?  I 
> couldn't find it in the '88 catalog.  I recall seeing some hits for it 
> in old unclassified DoD R&D publications in the past, wherein it was 
> used as part of an experimental LORAN reception setup.

>From the data sheet:


The AUSTRON Model 2090A Synchronous Filter is a Loran-C waveform averaging 
system that extends the range and versatility of the AUSTRON Model 2000C 
Loran-C Receiver in a variety of time/frequency and propagation applications.

Basically, the Model 2090A obtains a pulse waveform average that is taken over 
a number of pulse group repetition periods and processed for scope display or 
stripchart recording.

Loran-C waveform averaging accomplishes two important results:

  First, most types of coherent CW interference (communication signals, etc.) 
may be cancelled to zero in less than a second. This type of interference can 
be particularly troublesome when recording Loran-C waveforms in conventional 
ways.

  Second, averaging improves the waveform signal-to-random-noise ratio in 
proportion to the effective averaging time. Thus, it is possible to retrieve 
and analyze Loran-C signal waveforms that are obscured by atmospheric and 
manmade noise in the normal 20 KHz or 50 KHz receiver RF bandwidth.


For more details, including photo, specs and principles of operation, see:
http://leapsecond.com/museum/au2090a/

/tvb

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Re: [time-nuts] Sub-ps delay line

2017-02-07 Thread Bob Stewart
Since you need a set-and-forget type of solution, could you use a wide trace on 
your board and laser etch/mill it to set your delay, similar to the way film 
resistors are trimmed?  IOW, add length by turning the wide trace into a 
zig-zag.

Bob -AE6RV.com

GFS GPSDO list:
groups.yahoo.com/neo/groups/GFS-GPSDOs/info

  From: Mattia Rizzi 
 To: Discussion of precise time and frequency measurement  
 Sent: Tuesday, February 7, 2017 10:13 AM
 Subject: [time-nuts] Sub-ps delay line
   
Hello,
I'm looking/designing a sub-ps delay line with very high stability.
Basically it has microwave requirements on phase matching.
The main features that such delay line should have are:
- sub-ps resolution and about 1 ns range
- High stability, must not drift more than 2ps/year, preferably 1ps/year
- Temperature coefficient (tempco) below 1 ps/celsius
- Low phase noise floor, target random jitter below 100 fs RSM from 100Hz
to 1MHz.
- flicker noise below -90dBc at 1Hz (100MHz carrier)
- cheap (below 50 euros) and PCB integrable
- optional: autocalibration or a way to check calibration health over time
(checking the oscillation frequency of the delay line connected as loop?)

Operating conditions: The delay line will be used for RF distribution,
where the clock signals (100-200MHz) must stay in +/- 10 ps error window.
Since timing jitter (wander) is 1.6ps RMS, the delay line must be very
accurate, with maximum of +/- 3ps of delay uncertainty. The delay line is
used to phase-match the  clock outputs at factory, hence will not be
anymore modified (or for only fine corrections, tens of picoseconds). The
factory calibration compensates for the delay line and PCB
process/production variations. The boards will operate at almost same
temperature and humidity levels over years of continuous running.

Circuit constrains: The delay line is fed with an AC-coupled LVPECL clock
output (only P output used) and should provides a single-ended AC clock
output signal.

Indeed, no commercial chip fits into these requirements.

My idea is to use an RC filter to delay the input clock signal and then to
restore the clock edges with a LTC6957-1 (LVPECL outputs).
The RC filter would be realized using a varactor (Skyworks SMVA1470-004LF)
and a 16-bit DAC to control the voltage bias (+ stable voltage reference).
I already checked the values, and sub-ps resolution seems easily
achievable. The solution requires a factory calibration due to the
non-linear behavior of the varactor, but since I only need small
adjustments, this is not a problem.

The problem is to guarantee the calibration over years of operation.
Since a femtofarad parasitic capacitance can change the delay, I already
thought about protecting the delay line with some kind of resin (Epoxy?)
and/or a RF cage to protect it from dirt and moisture.
One of the issue is aging. I derived a typical varactor aging from VCTCXO
oscillators (no varactor manufacturer knows the effects of aging on its
products, apparently) and it's still good. But the aging of LTC6957 is not
known.
Is the PCB fabrication using microwave requirements on the dielectric fine?

Based on your experience, do you think that such delay line can respect the
requirements listed above, especially stability?
Am I missing something?
Thank you!

cheers,
Mattia Rizzi
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Re: [time-nuts] Sub-ps delay line

2017-02-07 Thread Mattia Rizzi
Hello,

>Put a length of coax in an adjustable oven ?

Using the numbers provided by [1], RG58 has about  -0.152 ps/m/deg. I need
1 ns range, cable length is prohibitive.

cheers,
Mattia

[1] http://www.hepl.hiroshima-u.ac.jp/phx/notes/cable/cable.html

2017-02-07 18:04 GMT+01:00 Poul-Henning Kamp :

> 
> In message  gmail.com>
> , Mattia Rizzi writes:
>
> >I'm looking/designing a sub-ps delay line with very high stability.
> >Basically it has microwave requirements on phase matching.
> >The main features that such delay line should have are:
> >- sub-ps resolution and about 1 ns range
>
> Put a length of coax in an adjustable oven ?
>
> --
> Poul-Henning Kamp   | UNIX since Zilog Zeus 3.20
> p...@freebsd.org | TCP/IP since RFC 956
> FreeBSD committer   | BSD since 4.3-tahoe
> Never attribute to malice what can adequately be explained by incompetence.
>
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Re: [time-nuts] Sub-ps delay line

2017-02-07 Thread Poul-Henning Kamp

In message 
, Mattia Rizzi writes:

>I'm looking/designing a sub-ps delay line with very high stability.
>Basically it has microwave requirements on phase matching.
>The main features that such delay line should have are:
>- sub-ps resolution and about 1 ns range

Put a length of coax in an adjustable oven ?

-- 
Poul-Henning Kamp   | UNIX since Zilog Zeus 3.20
p...@freebsd.org | TCP/IP since RFC 956
FreeBSD committer   | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.
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Re: [time-nuts] Sub-ps delay line

2017-02-07 Thread Scott Stobbe
I would also advise you take a look at how well you can maintain your
system impedance, say 50 Ohms. For example, I have seen about 100's ps
phase difference on a 10 MHz reference, using one BNC female-female coupler
versus another, a small part is due to TOF, but most of that is due to
subtle differences in the impedance of each coupler, thus by causing
reflections. The same is true for one cable versus another.

On Tue, Feb 7, 2017 at 11:13 AM, Mattia Rizzi 
wrote:

> Hello,
> I'm looking/designing a sub-ps delay line with very high stability.
> Basically it has microwave requirements on phase matching.
> The main features that such delay line should have are:
> - sub-ps resolution and about 1 ns range
> - High stability, must not drift more than 2ps/year, preferably 1ps/year
> - Temperature coefficient (tempco) below 1 ps/celsius
> - Low phase noise floor, target random jitter below 100 fs RSM from 100Hz
> to 1MHz.
> - flicker noise below -90dBc at 1Hz (100MHz carrier)
> - cheap (below 50 euros) and PCB integrable
> - optional: autocalibration or a way to check calibration health over time
> (checking the oscillation frequency of the delay line connected as loop?)
>
> Operating conditions: The delay line will be used for RF distribution,
> where the clock signals (100-200MHz) must stay in +/- 10 ps error window.
> Since timing jitter (wander) is 1.6ps RMS, the delay line must be very
> accurate, with maximum of +/- 3ps of delay uncertainty. The delay line is
> used to phase-match the  clock outputs at factory, hence will not be
> anymore modified (or for only fine corrections, tens of picoseconds). The
> factory calibration compensates for the delay line and PCB
> process/production variations. The boards will operate at almost same
> temperature and humidity levels over years of continuous running.
>
> Circuit constrains: The delay line is fed with an AC-coupled LVPECL clock
> output (only P output used) and should provides a single-ended AC clock
> output signal.
>
> Indeed, no commercial chip fits into these requirements.
>
> My idea is to use an RC filter to delay the input clock signal and then to
> restore the clock edges with a LTC6957-1 (LVPECL outputs).
> The RC filter would be realized using a varactor (Skyworks SMVA1470-004LF)
> and a 16-bit DAC to control the voltage bias (+ stable voltage reference).
> I already checked the values, and sub-ps resolution seems easily
> achievable. The solution requires a factory calibration due to the
> non-linear behavior of the varactor, but since I only need small
> adjustments, this is not a problem.
>
> The problem is to guarantee the calibration over years of operation.
> Since a femtofarad parasitic capacitance can change the delay, I already
> thought about protecting the delay line with some kind of resin (Epoxy?)
> and/or a RF cage to protect it from dirt and moisture.
> One of the issue is aging. I derived a typical varactor aging from VCTCXO
> oscillators (no varactor manufacturer knows the effects of aging on its
> products, apparently) and it's still good. But the aging of LTC6957 is not
> known.
> Is the PCB fabrication using microwave requirements on the dielectric fine?
>
> Based on your experience, do you think that such delay line can respect the
> requirements listed above, especially stability?
> Am I missing something?
> Thank you!
>
> cheers,
> Mattia Rizzi
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> mailman/listinfo/time-nuts
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>
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Re: [time-nuts] WWV Receivers

2017-02-07 Thread Chris Albertson
On Mon, Feb 6, 2017 at 11:27 PM, Hal Murray  wrote:

>
> > esp. if one uses a Chinese $6.50 incl. shipping HF  receiver off eBay;
>
> Could somebody give me a lesson in receivers appropriate for extracting
> time
> from WWV?
>
> Is $10 a realistic price?
>

Yes, this would not need to be tunable as WWV is at a fixed frequency.  I
have seen a receiver that uses a 10MHz crystal in the front end and then
mixes the signal to baseband then samples it with a PC "sound card".   $10
in parts easy

You extract the time in the PC software.   I say "PC" but a really low-end
computer like a Rasperry Pi would be perfect for this, maybe over kill but
you'd want the features of the OS to send the time some place
-- 

Chris Albertson
Redondo Beach, California
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[time-nuts] Sub-ps delay line

2017-02-07 Thread Mattia Rizzi
Hello,
I'm looking/designing a sub-ps delay line with very high stability.
Basically it has microwave requirements on phase matching.
The main features that such delay line should have are:
- sub-ps resolution and about 1 ns range
- High stability, must not drift more than 2ps/year, preferably 1ps/year
- Temperature coefficient (tempco) below 1 ps/celsius
- Low phase noise floor, target random jitter below 100 fs RSM from 100Hz
to 1MHz.
- flicker noise below -90dBc at 1Hz (100MHz carrier)
- cheap (below 50 euros) and PCB integrable
- optional: autocalibration or a way to check calibration health over time
(checking the oscillation frequency of the delay line connected as loop?)

Operating conditions: The delay line will be used for RF distribution,
where the clock signals (100-200MHz) must stay in +/- 10 ps error window.
Since timing jitter (wander) is 1.6ps RMS, the delay line must be very
accurate, with maximum of +/- 3ps of delay uncertainty. The delay line is
used to phase-match the  clock outputs at factory, hence will not be
anymore modified (or for only fine corrections, tens of picoseconds). The
factory calibration compensates for the delay line and PCB
process/production variations. The boards will operate at almost same
temperature and humidity levels over years of continuous running.

Circuit constrains: The delay line is fed with an AC-coupled LVPECL clock
output (only P output used) and should provides a single-ended AC clock
output signal.

Indeed, no commercial chip fits into these requirements.

My idea is to use an RC filter to delay the input clock signal and then to
restore the clock edges with a LTC6957-1 (LVPECL outputs).
The RC filter would be realized using a varactor (Skyworks SMVA1470-004LF)
and a 16-bit DAC to control the voltage bias (+ stable voltage reference).
I already checked the values, and sub-ps resolution seems easily
achievable. The solution requires a factory calibration due to the
non-linear behavior of the varactor, but since I only need small
adjustments, this is not a problem.

The problem is to guarantee the calibration over years of operation.
Since a femtofarad parasitic capacitance can change the delay, I already
thought about protecting the delay line with some kind of resin (Epoxy?)
and/or a RF cage to protect it from dirt and moisture.
One of the issue is aging. I derived a typical varactor aging from VCTCXO
oscillators (no varactor manufacturer knows the effects of aging on its
products, apparently) and it's still good. But the aging of LTC6957 is not
known.
Is the PCB fabrication using microwave requirements on the dielectric fine?

Based on your experience, do you think that such delay line can respect the
requirements listed above, especially stability?
Am I missing something?
Thank you!

cheers,
Mattia Rizzi
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Re: [time-nuts] WWV Receivers

2017-02-07 Thread Poul-Henning Kamp

In message <20170207072741.b084f406...@ip-64-139-1-69.sjc.megapath.net>, Hal 
Murray writes:
>
>> esp. if one uses a Chinese $6.50 incl. shipping HF  receiver off eBay;
>
>Could somebody give me a lesson in receivers appropriate for extracting time 
>from WWV?

Somebody should do an SDR project for this.

Modern microcontrollers have ADC's which are capable of sampling fast
enough and plenty of processing power to demodulate all the parts,
including the phase modulation.

Clock the microcontroller of your house-standard and you have a pretty
good sanity-check on your GPS receivers.

-- 
Poul-Henning Kamp   | UNIX since Zilog Zeus 3.20
p...@freebsd.org | TCP/IP since RFC 956
FreeBSD committer   | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.
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[time-nuts] WWV Receivers

2017-02-07 Thread Hal Murray

> esp. if one uses a Chinese $6.50 incl. shipping HF  receiver off eBay;

Could somebody give me a lesson in receivers appropriate for extracting time 
from WWV?

Is $10 a realistic price?


-- 
These are my opinions.  I hate spam.



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