Re: [time-nuts] new tdc from Texas
379998 379...@qq.com writes: Hi The spec is similar with TDC-GP22. In double-res mode, the resolution is 45ps, the stdev is 35ps. This unit is 55ps and 35ps. Not sure when the sample chip is ready. The TSSOP package is much more friendly to homebrew guys. Indeed this looks like quite an interesting device. I'm not sure I understand how it is able to approach timing resolution comparable to that of the THS788 yet at a fraction of the power. The sample rate is evidently quite limited. Is this just a function of the ring oscillator duty cycle being much smaller? Also, does anyone understand the reason behind the 12ns minimum measurement time? Cheers, - Ben pgpks0OEnyQ82.pgp Description: PGP signature ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] GPS SDR
I thought this[1] might be of interest to time nuts. It seems that some folks have been working on one obvious application to the new tool presented to us by the rts-sdr project: GPS reception. In addition to some discussion of software implementation, the post has some references to some open source FPGA receivers that might be of use to time nuts. Cheers, - Ben [1] http://michelebavaro.blogspot.it/2012/04/spring-news-in-gnss-and-sdr-domain.html ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Experience with THS788 from TI?
Thank you very much for your response. This is amazingly helpful. Attila Kinali att...@kinali.ch writes: On Wed, 21 Mar 2012 12:18:21 -0400 Ben Gamari bgam...@physics.umass.edu wrote: On Wed, 21 Mar 2012 09:44:14 -0500, David davidwh...@gmail.com wrote: I am surprised it is not more accurate and precise. Even old discrete designs can get down to 10ps or better. I wonder what market it is for where space is at that much of a premium. Out of curiosity, would you happen to have an example of discrete TDC design? Recently I've been exploring the TDC design space as these devices are a critical part of our experiments (I do spectroscopy of biological molecules). I'm currently (slowly) working on a FPGA TDC design (based on the PandaDAQ[1] and CERN's Spartan 6 TDC design) but it seems it will be non-trivial to get down to the 12 ns the commercial offerings provide (although at great cost). What would a discrete TDC design look like? Are there any designs in the open? There are multiple designs out there, some of which have been documented openly (in manuals, like the SR620 which is available from Didiers site) others are only known from papers. In general, i'd say if you need more documentation for a design done by a research group, you should be able to get help from them directly. Most people i know that work in research are more than happy to share their tools with others. Really, this is more of a personal project than anything else. While I can't say I'm quite at the time-nut level of fanaticism, I am always looking for an interesting project where I might learn a thing or two. If the result may one day help in a research setting, all the better. If you are really going to build your own design, then i suggest you read these papers: Thank you very much for this list. While I have already stumbled upon a few of the FPGA papers, I'm largely ignorant of the other possible approaches. Given the limitations of FPGA TDCs, it will be nice to see what is possible by other means. That being said, I'm quite keen on bringing up something on the FPGA. I just got the power supplies on the PandaDAQ running last night (QFN is a pain without my shiny new hot air rework station), so it seems that soon enough I'll have a Spartan 6 at my disposal. Time Interval Measurement Literature Review by... uh.. dont know www.rrsg.ee.uct.ac.za/members/jon/activities/timcs.pdf Gives you an easy overview of different methods of time interval measurement and how they work. Review of methods for time interval measurements with picosecond resolution by Jozef Kalisz, 2003, http://ztc.wel.wat.edu.pl/kalisz/met4_1_004.pdf A very detailed, but broad overview of the methods that are used in todays TIM/TDC applications. Time-to-digital Converters by Stephan Henzler, 2010 DOI: 10.1007/978-90-481-8628-0 A more theoretic overview of TDCs. Nice if you need more math. But if your library doesn't have access to the books from Springer, i wouldn't buy it (you probably do not need all that much of math). Error analysis and design of the Nutt time-interval digitiser with picosecond resoulution, by Kalisz, Pawlovski, Pelka, 1987 give you a much better treatment of how errors occur in TDCs and how to mathematically treat them. An FPGA Wave Union TDC for Time-of-Flight Applications, by Jinyuan Wu, 2009 The 10ps Wavelet TDC: Improving FPGA TDC Resolution beyond its Cell Delay, by Wu and Shi, http://www-ppd.fnal.gov/EEDOffice-W/Projects/ckm/comadc/WaveletTDC_abs08.pdf A 20ps Resolution Wave Union FPGA TDC with On-Chip Real Time Correction, by Qi, Deng, Gong and Liu, 2010 The wave union TDC is a quite interesting design that allows to get a quite high resolution with an FPGA only implementation. But this design depends highly on good placement, stable enviorment conditions (temperature, supply voltage) and permanent re-calibration (which in turn needs uncorrelated time events) As I said earlier, I have seen these earlier. Given that the CERN core has achieved 50ps resolution without wave union, it would be interesting to see what one could accomplish with a full wave union implementation. Time-Interval Measurements Based on SAW Filter Excitation, by Petr Panek, 2007 Time interval measurement device based on surface acoustic wave filter excitation, providing 1ps precision and stability, by Panek and Prochazka, 2007 Random Erros in Time Interval Measurement Based on SAW Filter Excitation, by Petr Panek, 2008 A very nice idea on how to use a high frequency startable oscillator with an ADC as phase detector. Panek claims to get below 1ps with a 200MHz clock and a 525MHz filter/oscillator. His calculations indicate that the ultimate limit of resolution is given by the sampling jitter of the ADC and the frequency and bandwidth (ie the Q of the oscillator). There This looks quite nice. I must say that I haven't If you search the IEEE archvies, you will find many more
Re: [time-nuts] Experience with THS788 from TI?
Attila Kinali att...@kinali.ch writes: On Thu, 22 Mar 2012 11:12:40 -0400 Ben Gamari bgam...@physics.umass.edu wrote: If you are really going to build your own design, then i suggest you read these papers: Thank you very much for this list. While I have already stumbled upon a few of the FPGA papers, I'm largely ignorant of the other possible approaches. Given the limitations of FPGA TDCs, it will be nice to see what is possible by other means. I'm quite sure there is much more around. I only dug a little bit a weekend or so and got a couple of intersting papers. It is also a good idea, to dig trough old circuit descriptions, form the 70s and older. You will find there many forgotten gems, that get increasingly relevant when you leave the digital domain, especially when going high speed. If only there weren't so much to read. That being said, I'm quite keen on bringing up something on the FPGA. I just got the power supplies on the PandaDAQ running last night (QFN is a pain without my shiny new hot air rework station), so it seems that soon enough I'll have a Spartan 6 at my disposal. *g* If you do QFN or any serious SMD stuff, get a Leiter HOT JET S with fine nozzles (3mm and 5mm), or anything similar. Normal hot air guns don't really work and a complete rework station is way too expensive for anything a mere mortal does. On the other hand, with such a Hot Jet S (or similar) you can even solder BGAs, reliably. After my first attempt at the QFN with an iron, I broke down and picked up a rework station for $100. It's not difficult to find them in the $75 range on eBay if you want to go lower. May not be the best station, but it will serve it's purpose. Time-Interval Measurements Based on SAW Filter Excitation, by Petr Panek, 2007 Time interval measurement device based on surface acoustic wave filter excitation, providing 1ps precision and stability, by Panek and Prochazka, 2007 Random Erros in Time Interval Measurement Based on SAW Filter Excitation, by Petr Panek, 2008 A very nice idea on how to use a high frequency startable oscillator with an ADC as phase detector. Panek claims to get below 1ps with a 200MHz clock and a 525MHz filter/oscillator. His calculations indicate that the ultimate limit of resolution is given by the sampling jitter of the ADC and the frequency and bandwidth (ie the Q of the oscillator). There Oops.. There is a sentence missing... Interrupts are bad for emails. There is even a report of a similar design, using an LC tank as resonant circuit that got into the 10ps RMS region. See High frequency, high time time resolution time-to-digital converter emplying passive resonant circuits, by Ripamonti, Abba and Geracy, 2010 http://risorse.dei.polimi.it/digital/products/2010/High%20frequency,%20high%20time%20resolution%20time-to-digital%20converter%20employing%20passive%20resonating%20circuits.pdf After looking at the SAW filter technique a little bit more carefully I may consider implementing it in the past. It has a nice elegance to it. That being said, the path of least resistance at this point is to use the board I have, which lacks the 100MHz ADC. A project for a later date... But getting to below that will not be easy. Mainly due to all those side effect, non-idealities and other stuff you have to deal with. And be aware, that you are dealing with an high frequncy/high speed circuit. Crudly said, you are in the ballpark of a 1/10ps = 100GHz system. Everything has to be right to get you there. Sure. This is the real issue. I am a physicist by training, so the basics of high-speed design are largely a mystery to me. From application notes (in particular Jim Williams' old but very readable work) I've gleaned the following, 1) Keep traces short and well impedence matched 2) Ample bypassing 3) Ground plane is essential 4) Know where thy return path is! Duly noted. I recommend getting the Tietze-Schenk Halbleiter Schaltungstechnik (resp Electronic Circuits in englisch). It's like Horowitz, just with more theoretical background and more explenation how to design stuff. Ie you get the formulas to calculate what you need if you want to go to the limit. It's still very much practical (only as much theory as needed) but covers enough of the theory if you want to have more than just cookbook examples. Thanks! I'll look into this. I'm still looking for a good high speed / high frequency book. I've asked for literature in that area a few weeks ago on this list, but have not gotten the time yet to read all those books. You might want to check the answers too. But beyond these rough guidelines my intuition isn't so well honed. Do you have anything to add? Unfortunatley not. I'm too young for much experience and don't have a big lab to test things. Not to mention the constant lack of time. The only thing i have at my disposal are tons of papers i've read on train rides
[time-nuts] Experience with THS788 from TI?
On Wed, 21 Mar 2012 09:44:14 -0500, David davidwh...@gmail.com wrote: I am surprised it is not more accurate and precise. Even old discrete designs can get down to 10ps or better. I wonder what market it is for where space is at that much of a premium. Out of curiosity, would you happen to have an example of discrete TDC design? Recently I've been exploring the TDC design space as these devices are a critical part of our experiments (I do spectroscopy of biological molecules). I'm currently (slowly) working on a FPGA TDC design (based on the PandaDAQ[1] and CERN's Spartan 6 TDC design) but it seems it will be non-trivial to get down to the 12 ns the commercial offerings provide (although at great cost). What would a discrete TDC design look like? Are there any designs in the open? Cheers, - Ben [1] http://www.keteu.org/~haunma/proj/pandadaq/ [2] http://www.ohwr.org/projects/tdc-core/wiki ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] WWVB BPSK Receiver Project?
Looks like this bounced as I sent from the wrong address. Better late than never. On Wed, 14 Mar 2012 15:46:48 -0700, Chuck Forsberg WA7KGX N2469R c...@omen.com wrote: Asus has a $30 Xonar PCI soundcard that should do the job. I have two of the the more expensive pci-e versions. Some motherboards can do a/d at 192 but not as well as the Xonar. Even better: a USB DVB card [1]. For $30 you have a few million 8-bit I/Q samples per second and an interface to Gnu Radio. The possibilities are nearly endless. Cheers, - Ben [1] http://sdr.osmocom.org/trac/wiki/rtl-sdr ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Experience with THS788 from TI?
Bob Camp li...@rtty.us writes: Hi Are you after 12 ns or 12 ps? Bah, yes, my bad: picoseconds is the relevant timescale here. Cheers, - Ben ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Experience with THS788 from TI?
Bob Camp li...@rtty.us writes: Hi Ok, for a legit 12 ps with 0.1 ps drift and 200 mega samples per second - not to many alternatives. The FPGA stuff will get you to 50 to 100 ps on the same basis this gets you to 12 ps. They will get you to 20 to 40 ps on a good day - sort of the way this chip gets 8 ps. The FPGA will do it at a much lower data rate. In our experiments, we are typically observing very low count rates (100kHz at absolute most). I've occassionally stumbled upon a paper which claims to get 10ps on a standard FPGA, but naturally they never show the code. Given that I'm a relative novice at high-speed electronics and FPGAing in general, I'll consider myself lucky if I get the 50ps advertised by the CERN core. In particular, one issue I've been struggling with is the discriminator. Our fast detectors produce a NIM negative-current pulse which will ultimately need to become suitable input for the FPGA. Of course, the most precise time measurement in the world is useless if the discriminator front-end has a nanosecond jitter. Unfortunately, I have yet to find any open, high precision discriminator designs. In principle a constant fraction discriminator doesn't seem to difficult to implement, but when it comes to preserving the high-speed signal integrity, it seems like it could get pretty hairy. Comments? If you average over many samples, all of these will get you a better estimate. How much better depends on a bunch of things. The TI part *could* do very well if you have a 200 MHz signal to look at. For time-correlated single photon counting (our primary use for precision timing), having high temporal resolution is quite important. That being said, all of those arrival times all get combined into a correlation function so shot-per-shot jitter will be in large part averaged out. Cheers, - Ben ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
