Re: [time-nuts] ADF4002 phase noise - in FireFly-IIA-100MHz
Hi If you are running a synthesizer with a 1 KHz reference frequency and trying to use a 900 MHz VCO for the output, reference spurs are going to be a major issue. If you are going straight from 10 MHz to 100 MHz with a crystal oscillator at 100 MHz, reference spurs should not be a significant problem. Different issues in different designs. Bob On Mar 11, 2010, at 4:56 PM, Bruce Griffiths wrote: > Thats only true when the current source noise dominates. > When switching jitter on the pulse eges dominates the pulse width has no > effect (to first order) on the noise. > > Since the supply rails are relatively noisy in an FPGA the current source > noise will usually dominate in a CMOS XOR implemented in an FPGA. > > If the XOR supply noise can be made very low then its possible that the > switching jitter noise contribution dominates. > One example being the classical diode ring mixer with both IF and LO ports > saturated. > > Bruce > > Henk wrote: >> Hi, >> >> In order to avoid a dead zone in a phase detector there is a current pulse >> in both the up and the down source. The net result when locked is zero but >> the noise is still there. Therefor the moved charge in lock should be as low >> as possible. The up and down currents must be as short as possible. Therefor >> a well designed PFD will out perform a EXOR. I allways designed for the >> shortest pulses. For the nmos current source I used 100ps but the pmos >> dictated to go to 300ps. >> >> Henk >> >> Op 10 mrt 2010, om 19:36 heeft saidj...@aol.com het volgende geschreven: >> >>> Hi Ulrich, >>> >>> I think in our design the spec is limited by the ~-100dBc noise at 100Hz >>> offset of the 100MHz VCXO. >>> >>> Please note that the ADF4002 actually improves that noise by about 15dB >>> from the datasheet spec (or the unit we tested was that much better than the >>> one shown in the datasheet). >>> >>> Also, the ADF4002 allows different Current settings for the PFD, this >>> affects phase noise as well. Fine-tuning of these settings and the loop >>> filter >>> reduced the noise further. We use a 10MHz PFD output, so that should be >>> optimal for phase noise. >>> >>> So in short, we improve the inherent close-in PN performance of the VCXO >>> significantly. Would an Exor gate have resulted in better performance? >>> Maybe. >>> But the 10MHz spur on the VCXO EFC pin from the EXOR output may cause much >>> higher spur levels at 10, 20, 30MHz etc on the VCXO output. And you would >>> have to contend with counter noise (10:1 divider), and there would not have >>> been flexibility in frequency, as well as a PLL Lock indicator.. >>> >>> bye, >>> Said >>> >>> >>> In a message dated 3/10/2010 07:19:14 Pacific Standard Time, >>> df...@ulrich-bangert.de writes: >>> >>> Let me put forward the question in another way: Had you to lock a 100 MHz >>> VCXO to a 10 MHz reference, what other chip had you used that you believe >>> is >>> the better performer? Please no injection locking or even stranger, just >>> plain PLL. >>> ___ >>> time-nuts mailing list -- time-nuts@febo.com >>> To unsubscribe, go to >>> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts >>> and follow the instructions there. >> >> >> ___ >> time-nuts mailing list -- time-nuts@febo.com >> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts >> and follow the instructions there. >> > > > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] ADF4002 phase noise - in FireFly-IIA-100MHz
Thats only true when the current source noise dominates. When switching jitter on the pulse eges dominates the pulse width has no effect (to first order) on the noise. Since the supply rails are relatively noisy in an FPGA the current source noise will usually dominate in a CMOS XOR implemented in an FPGA. If the XOR supply noise can be made very low then its possible that the switching jitter noise contribution dominates. One example being the classical diode ring mixer with both IF and LO ports saturated. Bruce Henk wrote: Hi, In order to avoid a dead zone in a phase detector there is a current pulse in both the up and the down source. The net result when locked is zero but the noise is still there. Therefor the moved charge in lock should be as low as possible. The up and down currents must be as short as possible. Therefor a well designed PFD will out perform a EXOR. I allways designed for the shortest pulses. For the nmos current source I used 100ps but the pmos dictated to go to 300ps. Henk Op 10 mrt 2010, om 19:36 heeft saidj...@aol.com het volgende geschreven: Hi Ulrich, I think in our design the spec is limited by the ~-100dBc noise at 100Hz offset of the 100MHz VCXO. Please note that the ADF4002 actually improves that noise by about 15dB from the datasheet spec (or the unit we tested was that much better than the one shown in the datasheet). Also, the ADF4002 allows different Current settings for the PFD, this affects phase noise as well. Fine-tuning of these settings and the loop filter reduced the noise further. We use a 10MHz PFD output, so that should be optimal for phase noise. So in short, we improve the inherent close-in PN performance of the VCXO significantly. Would an Exor gate have resulted in better performance? Maybe. But the 10MHz spur on the VCXO EFC pin from the EXOR output may cause much higher spur levels at 10, 20, 30MHz etc on the VCXO output. And you would have to contend with counter noise (10:1 divider), and there would not have been flexibility in frequency, as well as a PLL Lock indicator.. bye, Said In a message dated 3/10/2010 07:19:14 Pacific Standard Time, df...@ulrich-bangert.de writes: Let me put forward the question in another way: Had you to lock a 100 MHz VCXO to a 10 MHz reference, what other chip had you used that you believe is the better performer? Please no injection locking or even stranger, just plain PLL. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] ADF4002 phase noise - in FireFly-IIA-100MHz
Hi, In order to avoid a dead zone in a phase detector there is a current pulse in both the up and the down source. The net result when locked is zero but the noise is still there. Therefor the moved charge in lock should be as low as possible. The up and down currents must be as short as possible. Therefor a well designed PFD will out perform a EXOR. I allways designed for the shortest pulses. For the nmos current source I used 100ps but the pmos dictated to go to 300ps. Henk Op 10 mrt 2010, om 19:36 heeft saidj...@aol.com het volgende geschreven: Hi Ulrich, I think in our design the spec is limited by the ~-100dBc noise at 100Hz offset of the 100MHz VCXO. Please note that the ADF4002 actually improves that noise by about 15dB from the datasheet spec (or the unit we tested was that much better than the one shown in the datasheet). Also, the ADF4002 allows different Current settings for the PFD, this affects phase noise as well. Fine-tuning of these settings and the loop filter reduced the noise further. We use a 10MHz PFD output, so that should be optimal for phase noise. So in short, we improve the inherent close-in PN performance of the VCXO significantly. Would an Exor gate have resulted in better performance? Maybe. But the 10MHz spur on the VCXO EFC pin from the EXOR output may cause much higher spur levels at 10, 20, 30MHz etc on the VCXO output. And you would have to contend with counter noise (10:1 divider), and there would not have been flexibility in frequency, as well as a PLL Lock indicator.. bye, Said In a message dated 3/10/2010 07:19:14 Pacific Standard Time, df...@ulrich-bangert.de writes: Let me put forward the question in another way: Had you to lock a 100 MHz VCXO to a 10 MHz reference, what other chip had you used that you believe is the better performer? Please no injection locking or even stranger, just plain PLL. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] ADF4002 phase noise - in FireFly-IIA-100MHz
> from my limited understanding of things I would have guessed that the > ADF4001/2 PFD's ability to produce very short pulses in the > locked condition > puts a lot of energy into higher harmonics of the PFD's output, making it > more easy for the loop filter to remove them. In contrast to that > the simple > rectangle from an XOR has most of its energy in the lower > harmonics. That is > why I have believed AD's claims to have a real low noise PFD in these > devices. > > Is the theory all that wrong or do you expect other factors to be > responsible for the not superiour performance? My guess is that the ratio of the loop bandwidth to the comparison frequency is so dramatic in these cases -- on the order of 100,000:1 -- and the VC(X)O has such low tuning sensitivity, that there are unlikely to be any observable effects related to the PD output waveform. These typically show up as comparison-frequency sidebands rather than as broadband noise, in any event. I have actually never built a loop with an XOR gate; I've always used PFDs of one stripe or another. > Let me put forward the question in another way: Had you to lock a 100 MHz > VCXO to a 10 MHz reference, what other chip had you used that you > believe is > the better performer? Please no injection locking or even stranger, just > plain PLL. I don't think there are any magic chips that will deliver state-of-the-art performance in this application, unfortunately. If I really wanted to tweak a multiplier like that to the max, I'd be tempted to multiply the 10 MHz signal to 100 MHz with a tuned multiplier chain, and then use the OCXO to 'filter' it, using a mixer as the phase detector and no digital dividers at all. By the same token, a regenerative divider to bring the OCXO down to 10 MHz would also work well. Careful construction and a lot of tweaking would be needed, either way. In practice I'm OK with an inband noise floor of around -115 dBc/Hz as delivered by the ADF4002, as long as it falls off steeply beyond the loop BW (which it does, reaching ~-150 dBc/Hz by 1 kHz and well under -160 dBc/Hz by 10 kHz). Most DDS or ADC chips that I'm likely to drive with such a source will see little if any degradation beyond their residual specs. > I am in the state of constructiong a 10 to 100 MHz multiplier and your > advice is highly appreciated, until now I have been thinking the ADF4002 > could be an improvement against my usual AD9901 cover design in an FPGA or > CPLD. More experiments need to be done, certainly. There have been a number of FPGA/CPLD reflock modules designed by various people over the years, but I haven't seen any really good measurements of what they can do. With the ADF chips, the last few dBc/Hz of inband performance always seem to come down to the amount of care you take with the input signal conditioning, and I don't think the FPGA/CPLD phase detector would be very different in that regard. -- john, KE5FX ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] ADF4002 phase noise - in FireFly-IIA-100MHz
Hi Ulrich, I think in our design the spec is limited by the ~-100dBc noise at 100Hz offset of the 100MHz VCXO. Please note that the ADF4002 actually improves that noise by about 15dB from the datasheet spec (or the unit we tested was that much better than the one shown in the datasheet). Also, the ADF4002 allows different Current settings for the PFD, this affects phase noise as well. Fine-tuning of these settings and the loop filter reduced the noise further. We use a 10MHz PFD output, so that should be optimal for phase noise. So in short, we improve the inherent close-in PN performance of the VCXO significantly. Would an Exor gate have resulted in better performance? Maybe. But the 10MHz spur on the VCXO EFC pin from the EXOR output may cause much higher spur levels at 10, 20, 30MHz etc on the VCXO output. And you would have to contend with counter noise (10:1 divider), and there would not have been flexibility in frequency, as well as a PLL Lock indicator.. bye, Said In a message dated 3/10/2010 07:19:14 Pacific Standard Time, df...@ulrich-bangert.de writes: Let me put forward the question in another way: Had you to lock a 100 MHz VCXO to a 10 MHz reference, what other chip had you used that you believe is the better performer? Please no injection locking or even stranger, just plain PLL. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] ADF4002 phase noise - in FireFly-IIA-100MHz
John and Said, from my limited understanding of things I would have guessed that the ADF4001/2 PFD's ability to produce very short pulses in the locked condition puts a lot of energy into higher harmonics of the PFD's output, making it more easy for the loop filter to remove them. In contrast to that the simple rectangle from an XOR has most of its energy in the lower harmonics. That is why I have believed AD's claims to have a real low noise PFD in these devices. Is the theory all that wrong or do you expect other factors to be responsible for the not superiour performance? Let me put forward the question in another way: Had you to lock a 100 MHz VCXO to a 10 MHz reference, what other chip had you used that you believe is the better performer? Please no injection locking or even stranger, just plain PLL. I am in the state of constructiong a 10 to 100 MHz multiplier and your advice is highly appreciated, until now I have been thinking the ADF4002 could be an improvement against my usual AD9901 cover design in an FPGA or CPLD. Best regards Ulrich > -Ursprungliche Nachricht- > Von: time-nuts-boun...@febo.com > [mailto:time-nuts-boun...@febo.com] Im Auftrag von saidj...@aol.com > Gesendet: Mittwoch, 10. Marz 2010 00:28 > An: time-nuts@febo.com > Betreff: [time-nuts] ADF4002 phase noise - in FireFly-IIA-100MHz > > > Hi John, > > we have a new 100MHz board (FireFly-IIA-100MHz) that uses an > ADF4002 to > generate 100MHz from the 10MHz internal OCXO. > > The VCXO we use is rated at better than 100dBc at 100Hz. > > The 10MHz reference achieves typ. -148 dBc at 100Hz. > > We measured -115dBc/Hz at 100MHz at 100Hz offset in a couple > of sample > units using the TSC5125A. > > This is in-line with your measurement at 80MHz. > > Loop BW is ~30Hz, so the 100Hz offset is slightly outside of > the ADF4002 > loop BW. > > Note that we get ~15dB better performance at 100Hz offset > than the VCXO > datasheet would let us expect. > > bye, > Said > > > In a message dated 3/9/2010 14:00:16 Pacific Standard Time, > jmi...@pop.net > writes: > > I haven't exhaustively tested the ADF4107 but I have played > with the > ADF4002 > recently. I haven't been able to come within several dBc/Hz > of its rated noise level. In one test, at 100 Hz from an 80 > MHz carrier, I've seen about -118 dBc/Hz from the ADF4002 > when fed by 10 MHz with -145 dBc/Hz at 100 Hz (which would > become about -127 dBc/Hz in an ideal 80 MHz > multiplier.) > The figure-of-merit equation suggests that -222 + 20*log(8) > + 10*log(10 > MHz) > = -134 dBc/Hz would be achievable, well below the -127 > dBc/Hz limit imposed by the reference. > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] ADF4002 phase noise - in FireFly-IIA-100MHz
Hi John, we have a new 100MHz board (FireFly-IIA-100MHz) that uses an ADF4002 to generate 100MHz from the 10MHz internal OCXO. The VCXO we use is rated at better than 100dBc at 100Hz. The 10MHz reference achieves typ. -148 dBc at 100Hz. We measured -115dBc/Hz at 100MHz at 100Hz offset in a couple of sample units using the TSC5125A. This is in-line with your measurement at 80MHz. Loop BW is ~30Hz, so the 100Hz offset is slightly outside of the ADF4002 loop BW. Note that we get ~15dB better performance at 100Hz offset than the VCXO datasheet would let us expect. bye, Said In a message dated 3/9/2010 14:00:16 Pacific Standard Time, jmi...@pop.net writes: I haven't exhaustively tested the ADF4107 but I have played with the ADF4002 recently. I haven't been able to come within several dBc/Hz of its rated noise level. In one test, at 100 Hz from an 80 MHz carrier, I've seen about -118 dBc/Hz from the ADF4002 when fed by 10 MHz with -145 dBc/Hz at 100 Hz (which would become about -127 dBc/Hz in an ideal 80 MHz multiplier.) The figure-of-merit equation suggests that -222 + 20*log(8) + 10*log(10 MHz) = -134 dBc/Hz would be achievable, well below the -127 dBc/Hz limit imposed by the reference. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
