Re: [time-nuts] Divide by 3

[Charles Steinmetz]

Nick wrote:

>> Charles wrote:
>>
>> What specific chips did you use?
>
> Nick wrote:
>
> MC74VHC1G86
> 74HC74D

Good to know, thanks.  Just FYI, you may want to look into the NC7SZ86 
(and other NC7SZ "TinyLogic" series parts).  The NC7SZ86 is 
pin-compatible with the 74VHC1G part, with several added advantages:


1).  Output drive current is +/- 24mA rather than only 8mA.  (This 
doesn't matter for the divide-by-three circuit, but in my book sturdy 
outputs are always preferred.)


2).  It is a bit faster.

3).  Speed doesn't drop off as much on lower-voltage supplies.

4).  The NC7SZ series incorporates ground-bounce reduction for lower EMI 
and noise.


Best regards,

Charles


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Re: [time-nuts] Divide by 3

[Nick Sayer via time-nuts]

https://www.digikey.com/product-detail/en/on-semiconductor/MC74VHC1G86DTT1G/MC74VHC1G86DTT1GOSCT-ND/2705092
https://www.digikey.com/product-detail/en/nxp-semiconductors/74HC74D,653/568-1490-1-ND/763395


> On Jul 6, 2016, at 8:39 PM, Charles Steinmetz  wrote:
> 
> Nick wrote:
> 
>> I got the boards back, and Charles’ version with just two D FFs and a single 
>> XOR works perfectly. It works even without the delay line he indicated
> 
> I have never needed the delay in practice, either (I use mostly NC7SZ, 74AC, 
> and 74HC logic).  Modern logic is vastly more forgiving WRT setup and hold 
> times compared to the bad old days.  I showed the delay just in case someone 
> built it without and it didn't work.
> 
> What specific chips did you use?
> 
> Best regards,
> 
> Charles
> 
> 
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Re: [time-nuts] Divide by 3

[Charles Steinmetz]

Nick wrote:


I got the boards back, and Charles’ version with just two D FFs and a single 
XOR works perfectly. It works even without the delay line he indicated


I have never needed the delay in practice, either (I use mostly NC7SZ, 
74AC, and 74HC logic).  Modern logic is vastly more forgiving WRT setup 
and hold times compared to the bad old days.  I showed the delay just in 
case someone built it without and it didn't work.


What specific chips did you use?

Best regards,

Charles


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Re: [time-nuts] Divide by 3

[Nick Sayer via time-nuts]

> On Jun 8, 2016, at 9:59 AM, Charles Steinmetz  wrote:
> 
> Nick wrote:
> 
>> I’m contemplating trying my GPS board with an FE-405B. That’s a different 
>> kettle of fish, but at the end of that, if I’m successful, one of the goals 
>> would be to be able to use it for the external reference of my 53220A. 
>> Unfortunately, 15 MHz isn’t one of the options - only 1, 5 and 10.
>> 
>> So I did some googling and found a divide-by-3 circuit using flip-flops, and 
>> then designed a board for it
> 
> You can achieve substantially lower jitter (phase noise) with a regenerative 
> divider, which also allows you to divide by 3/2 for a 10MHz output.  I've 
> built several like that, and they work extremely well.
> 
> There are simpler divide-by-three logic circuits (generally, the simpler the 
> circuit the closer to an exact 50% duty cycle and the lower the jitter).  See 
> the attached image for one approach.
> 

I got the boards back, and Charles’ version with just two D FFs and a single 
XOR works perfectly. It works even without the delay line he indicated (sample 
size 1, FWIW). The version with the three D FFs and 3 NORs works just fine too, 
but of course it’s not as small as Charles’.


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[time-nuts] Divide by 3

[Mark Sims]

When I was working on the temperature control feature of Lady Heather,  I 
noticed that I could detect when ever I opened the refrigerator door (in the 
next room) or when I was in the same room as the Tbolt by looking at the EFC or 
temperature sensor plots...  the Thunderbolt oscillator makes a nice 
thermometer.  People are basically a 100 watt space heater.

Another time I was working on a precision temperature recorder (based upon an 
Analog Devices V/F chip).  It could easily detect when a person walked into or 
left a (rather large) lab.  You could even quantify the number of people in the 
lab (one particularly large guy counted as two people).

-
>  People would say "nice thermometer, guys :-( 
>   
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Re: [time-nuts] Divide by 3

[Richard (Rick) Karlquist]

I remember when we first got a prototype 10816
Mini-Rubidium standard working.  We put in on
of those old paper strip chart recorders (this
was circa 1981).  We were pretty cocky about
how it went straight down the page.  You
couldn't do that with quartz.  When we
came back the next day, you could clearly
see frequency steps when the air conditioning
went off at night and came on in the daytime.
People would say "nice thermometer, guys :-(

Rick

On 6/8/2016 2:21 PM, Hal Murray wrote:


att...@kinali.ch said:

Temperature, in an office or lab, does not change that much to cause large
differences.


Maybe in your lab.

I'd expect that will change as people get more sensitive to energy costs.
Things like turning down/off the heat/cooling at night can lead to large
swings.


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Re: [time-nuts] Divide by 3

[Richard (Rick) Karlquist]

On 6/8/2016 9:59 AM, Charles Steinmetz wrote:


You can achieve substantially lower jitter (phase noise) with a
regenerative divider, which also allows you to divide by 3/2 for a 10MHz
output.  I've built several like that, and they work extremely well.



When I was at Agilent, they developed a very low noise regenerative 
divide by 3/2 chain to use in high performance instruments.  The gurus 
who know about this stuff said it was the lowest phase noise

architecture.

Rick
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Re: [time-nuts] Divide by 3

[Nick Sayer via time-nuts]

> On Jun 8, 2016, at 9:59 AM, Charles Steinmetz  wrote:
> 
> You can achieve substantially lower jitter (phase noise) with a regenerative 
> divider, which also allows you to divide by 3/2 for a 10MHz output.  I've 
> built several like that, and they work extremely well.
> 
> There are simpler divide-by-three logic circuits (generally, the simpler the 
> circuit the closer to an exact 50% duty cycle and the lower the jitter).  See 
> the attached image for one approach.
> 

Very nice! That one also simulates properly on CircuitLab without the delay 
gates in the output feedback. I tried adding the delay gates back in, and it 
didn’t change, but I can imagine that’s just because it’s a simulator.


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Re: [time-nuts] Divide by 3

[Nick Sayer via time-nuts]

There’s a link to the blog posting (not mine) that has the schematic on the 
OSHPark shared project.

The schematic there isn’t *totally* obvious - the square boxes that are 
otherwise unlabeled are D flip-flops with D on the left and Q on the right. 
I’ve simulated the circuit at CircuitLab and gotten the correct behavior, for 
what that’s worth.

You’re correct that multiple instances of this circuit fed from the same source 
would not be in phase. That’s ok with me. I’m just going to build one.

I don’t know if I’ll actually put it into service or not. I have lots of 
different references at my disposal for the 53220A, and at this point my 
thinking is that all of them are going to be a tie given this TIA’s specs.

Someone else mentioned sine vs square for the 53220A reference input. I’ve fed 
square waves into this TIA with no indication that it hasn’t worked just as 
well as sine, but I don’t have any assurance beyond that.

> On Jun 8, 2016, at 9:47 AM, Richard (Rick) Karlquist  
> wrote:
> 
> The URL you cited doesn't have the schematic in any obvious
> place.  However, using both edges of the clock to supposedly
> result in 50% duty cycle output depends on having 50%
> duty cycle at the input.  If you have differential logic
> like ECL, this can be realistic.  Single ended logic,
> questionable.
> 
> The other issue is that the divider can start up in any
> one of 3 phases with respect to any other frequency
> dividers in your system, unless you do something to
> synchronize the various dividers.
> 
> This is probably old hat to most readers of time-nuts, but
> I just wanted to mention it in case some were unaware
> of it.
> 
> Rick
> 
> On 6/8/2016 6:55 AM, Nick Sayer via time-nuts wrote:
>> I’m contemplating trying my GPS board with an FE-405B. That’s a different 
>> kettle of fish, but at the end of that, if I’m successful, one of the goals 
>> would be to be able to use it for the external reference of my 53220A. 
>> Unfortunately, 15 MHz isn’t one of the options - only 1, 5 and 10.
>> 
>> So I did some googling and found a divide-by-3 circuit using flip-flops, and 
>> then designed a board for it:
>> 
>> https://oshpark.com/shared_projects/jxXp7wYM
>> 
>> The circuit uses 3 D flip-flops and 3 NOR gates and has a 50% duty cycle 
>> output that’s 1/3 the frequency of the input. The OSHPark project has a 
>> pointer to the original blog post that has a schematic. The only difference 
>> between their schematic and mine is that in theirs, the third flip-flop has 
>> an inverted clock input. The third NOR gate inverts the clock to achieve 
>> that in mine (also one flip-flop and one NOR gate are unused and have the 
>> inputs tied high).
>> 
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Re: [time-nuts] Divide by 3

[Nick Sayer via time-nuts]

In this case, the FE-405B outputs a sine wave, which is converted to square 
with a self-biased inverter. That’s fed into an NB3N551 clock buffer. Two of 
the outputs go off to the discipline system and the other two are user outputs, 
one of which would be fed into the circuit in question.

On the scope, the 10 MHz I have from the FE-5680As look 50% to me, but of 
course that doesn’t mean a lot. The controller is clocked from it too, and it 
really wants “close” to 50% duty cycles, but again, their tolerances aren’t 
Time Nuts(tm) grade.

All that said, I’m feeding this stuff into a 53220A, so I’m not sure there 
aren’t bigger fish to fry...


> On Jun 8, 2016, at 11:48 AM, Alex Pummer  wrote:
> 
> utilizing rising and falling edges makes the circuit output signal duty cycle 
> sensitive to the input signal's duty cycle, and therefore the harmonic 
> content will vary with the input duty cycle variation.
> 73
> KJ6UHN
> Alex
> 
> On 6/8/2016 9:47 AM, Richard (Rick) Karlquist wrote:
>> The URL you cited doesn't have the schematic in any obvious
>> place.  However, using both edges of the clock to supposedly
>> result in 50% duty cycle output depends on having 50%
>> duty cycle at the input.  If you have differential logic
>> like ECL, this can be realistic.  Single ended logic,
>> questionable.
>> 
>> The other issue is that the divider can start up in any
>> one of 3 phases with respect to any other frequency
>> dividers in your system, unless you do something to
>> synchronize the various dividers.
>> 
>> This is probably old hat to most readers of time-nuts, but
>> I just wanted to mention it in case some were unaware
>> of it.
>> 
>> Rick
>> 
>> On 6/8/2016 6:55 AM, Nick Sayer via time-nuts wrote:
>>> I’m contemplating trying my GPS board with an FE-405B. That’s a different 
>>> kettle of fish, but at the end of that, if I’m successful, one of the goals 
>>> would be to be able to use it for the external reference of my 53220A. 
>>> Unfortunately, 15 MHz isn’t one of the options - only 1, 5 and 10.
>>> 
>>> So I did some googling and found a divide-by-3 circuit using flip-flops, 
>>> and then designed a board for it:
>>> 
>>> https://oshpark.com/shared_projects/jxXp7wYM
>>> 
>>> The circuit uses 3 D flip-flops and 3 NOR gates and has a 50% duty cycle 
>>> output that’s 1/3 the frequency of the input. The OSHPark project has a 
>>> pointer to the original blog post that has a schematic. The only difference 
>>> between their schematic and mine is that in theirs, the third flip-flop has 
>>> an inverted clock input. The third NOR gate inverts the clock to achieve 
>>> that in mine (also one flip-flop and one NOR gate are unused and have the 
>>> inputs tied high).
>>> 
>>> ___
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>>> 
>>> 
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>> 
>> -
>> No virus found in this message.
>> Checked by AVG - www.avg.com
>> Version: 2016.0.7639 / Virus Database: 4598/12384 - Release Date: 06/08/16
> 
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Re: [time-nuts] Divide by 3

[Hal Murray]

att...@kinali.ch said:
> Temperature, in an office or lab, does not change that much to cause large
> differences. 

Maybe in your lab.

I'd expect that will change as people get more sensitive to energy costs.  
Things like turning down/off the heat/cooling at night can lead to large 
swings.

-- 
These are my opinions.  I hate spam.



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Re: [time-nuts] Divide by 3

[Alex Pummer]

utilizing rising and falling edges makes the circuit output signal duty 
cycle sensitive to the input signal's duty cycle, and therefore the 
harmonic content will vary with the input duty cycle variation.

73
KJ6UHN
Alex

On 6/8/2016 9:47 AM, Richard (Rick) Karlquist wrote:

The URL you cited doesn't have the schematic in any obvious
place.  However, using both edges of the clock to supposedly
result in 50% duty cycle output depends on having 50%
duty cycle at the input.  If you have differential logic
like ECL, this can be realistic.  Single ended logic,
questionable.

The other issue is that the divider can start up in any
one of 3 phases with respect to any other frequency
dividers in your system, unless you do something to
synchronize the various dividers.

This is probably old hat to most readers of time-nuts, but
I just wanted to mention it in case some were unaware
of it.

Rick

On 6/8/2016 6:55 AM, Nick Sayer via time-nuts wrote:
I’m contemplating trying my GPS board with an FE-405B. That’s a 
different kettle of fish, but at the end of that, if I’m successful, 
one of the goals would be to be able to use it for the external 
reference of my 53220A. Unfortunately, 15 MHz isn’t one of the 
options - only 1, 5 and 10.


So I did some googling and found a divide-by-3 circuit using 
flip-flops, and then designed a board for it:


https://oshpark.com/shared_projects/jxXp7wYM

The circuit uses 3 D flip-flops and 3 NOR gates and has a 50% duty 
cycle output that’s 1/3 the frequency of the input. The OSHPark 
project has a pointer to the original blog post that has a schematic. 
The only difference between their schematic and mine is that in 
theirs, the third flip-flop has an inverted clock input. The third 
NOR gate inverts the clock to achieve that in mine (also one 
flip-flop and one NOR gate are unused and have the inputs tied high).


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-
No virus found in this message.
Checked by AVG - www.avg.com
Version: 2016.0.7639 / Virus Database: 4598/12384 - Release Date: 
06/08/16


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[time-nuts] Divide by 3

[cdelect]

The FE405B AD plot I recently posted used a simple (non 50% duty cycle)
divide by 3 using a 74ls74 and 74ls02 (if I remember correctly). 
I used the HP board from the pair used in the 5065A or 5061A/B.
The existing 74ls74 was piggy backed with the 74ls02 and connections made
with tiny wire. The non-symmetrical 5Mhz output of the divider went into
the existing 5Mhz filter amp resulting in a nice clean Sine wave.
As the plot shows the AD does not suffer using this simple scheme.

Cheers,

Corby

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Re: [time-nuts] Divide by 3

[Charles Steinmetz]

Nick wrote:


I’m contemplating trying my GPS board with an FE-405B. That’s a different 
kettle of fish, but at the end of that, if I’m successful, one of the goals 
would be to be able to use it for the external reference of my 53220A. 
Unfortunately, 15 MHz isn’t one of the options - only 1, 5 and 10.

So I did some googling and found a divide-by-3 circuit using flip-flops, and 
then designed a board for it


You can achieve substantially lower jitter (phase noise) with a 
regenerative divider, which also allows you to divide by 3/2 for a 10MHz 
output.  I've built several like that, and they work extremely well.


There are simpler divide-by-three logic circuits (generally, the simpler 
the circuit the closer to an exact 50% duty cycle and the lower the 
jitter).  See the attached image for one approach.


Best regards,

Charles


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Re: [time-nuts] Divide by 3

[Attila Kinali]

On Wed, 8 Jun 2016 18:35:43 +0200
Mike Cook  wrote:

> It is a no brainer to get a sine from a square wave, BUT , I seriously
> doubt that the excellent ADEV can be maintained with all that flipping
> and flopping going on. I even doubt that it could be kept in a pure sine
> implementation. 

I would not worry too much about ADEV degradation. The two most influencial
parameters for delay changes are temperature and supply voltage. Given that
the power supply is of decent quality (<<1% change per °C), then the supply
variations have little influence. Temperature, in an office or lab, does
not change that much to cause large differences.

I attached a TDEV plot (TDEV_all_pairs.png) of our clock sync system, which
uses Cyclone4 FPGAs (on an undmodified DE0-nano board) as TDCs to measure and
correct the skew between otherwise independent nodes. The measurements were
done using pulse outputs of the nodes feeding an DTS-2075, hence depict the
skew between pairs of nodes[1]. As you can see the curves go down nicely down
(with white phase noise) to <2ps in the 10-100s range. The blue curve looks
worse, due to hysteresis effects in the control system.

The second plot (TDEV_N4_N5_long.png) is an 9d19h run of the blue node
pair from the other plot. As you can see, the TDEV stays below 10ps up to 1e5s.
Most of the instability at taus >10 comes from the above mentioned hysteresis.

All measurements were done in late April, early May this year in Vienna,
with changing weather conditions. I.e. the temperature was anything but stable.
Unfortunately, we didn't record the temperature in the room.

If you take this data as indication, you can guess that any modern CMOS system
in an office environment will add less than 10ps timing uncertainty long term.
More likely it will be less than 1ps, as the plots depict measurements of a
complex system that does a lot of detection and non-trivial processing. 
For a frequency reference that is fed by GPS this level of stability should
be good enough.

Short term effects (aka phase noise) are a totally different story, though.


Attila Kinali

[1] I am leaving the details of the system out for the moment, as they are
not really important for the discussion at hand. As soon as I have time to
prepare the arxiv version of the paper I will post it on this list.

-- 
It is upon moral qualities that a society is ultimately founded. All 
the prosperity and technological sophistication in the world is of no 
use without that foundation.
 -- Miss Matheson, The Diamond Age, Neil Stephenson
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Re: [time-nuts] Divide by 3

[Mike Cook]

> Le 8 juin 2016 à 15:55, Nick Sayer via time-nuts  a écrit 
> :
> 
> I’m contemplating trying my GPS board with an FE-405B. That’s a different 
> kettle of fish, but at the end of that, if I’m successful, one of the goals 
> would be to be able to use it for the external reference of my 53220A. 
> Unfortunately, 15 MHz isn’t one of the options - only 1, 5 and 10.

I saw the same, which put me off trying to do the same. However I am not sure 
that your approach will work as the specs for the external clock indicate:

 - EXTernal  selects an external reference signal applied to the rear panel
Ext Ref In  connector. The signal must be:
•  1 MHz , 5 MHz, or 10 MHz
•  100 mVrms to 2.5 Vrms
•  sine wave

Your output is digital, no? It may function but I wouldn’t trust it.

It is a no brainer to get a sine from a square wave, BUT , I seriously doubt 
that the excellent ADEV can be maintained with all that flipping and flopping 
going on. I even doubt that it could be kept in a pure sine implementation. 

Mike


> 
> So I did some googling and found a divide-by-3 circuit using flip-flops, and 
> then designed a board for it:
> 
> https://oshpark.com/shared_projects/jxXp7wYM
> 
> The circuit uses 3 D flip-flops and 3 NOR gates and has a 50% duty cycle 
> output that’s 1/3 the frequency of the input. The OSHPark project has a 
> pointer to the original blog post that has a schematic. The only difference 
> between their schematic and mine is that in theirs, the third flip-flop has 
> an inverted clock input. The third NOR gate inverts the clock to achieve that 
> in mine (also one flip-flop and one NOR gate are unused and have the inputs 
> tied high).
> 
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have not got it. »
George Bernard Shaw

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[time-nuts] Divide by 3

[Nick Sayer via time-nuts]

I’m contemplating trying my GPS board with an FE-405B. That’s a different 
kettle of fish, but at the end of that, if I’m successful, one of the goals 
would be to be able to use it for the external reference of my 53220A. 
Unfortunately, 15 MHz isn’t one of the options - only 1, 5 and 10.

So I did some googling and found a divide-by-3 circuit using flip-flops, and 
then designed a board for it:

https://oshpark.com/shared_projects/jxXp7wYM

The circuit uses 3 D flip-flops and 3 NOR gates and has a 50% duty cycle output 
that’s 1/3 the frequency of the input. The OSHPark project has a pointer to the 
original blog post that has a schematic. The only difference between their 
schematic and mine is that in theirs, the third flip-flop has an inverted clock 
input. The third NOR gate inverts the clock to achieve that in mine (also one 
flip-flop and one NOR gate are unused and have the inputs tied high).

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