Re: [time-nuts] Looking for ECL divide by 3 with symmetry
symmetry is better to look with spectrum analyzer, at good symmetry you should not see second harmonic 73 KJ6UHN Alex On 10/6/2015 12:28 AM, ed breya wrote: Problem solved - one missing connection was fixed, and it now runs just fine. Symmetry looks good on a scope, and the toggle rate is plenty enough. It runs OK to beyond 120 MHz input. Ed ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Looking for ECL divide by 3 with symmetry
Problem solved - one missing connection was fixed, and it now runs just fine. Symmetry looks good on a scope, and the toggle rate is plenty enough. It runs OK to beyond 120 MHz input. Ed ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Looking for ECL divide by 3 with symmetry
After studying the various divide by 3 circuits, I decided to try designing one that would be simpler in terms of package count, using available ECL DIPs on-hand. Instead of the JK-FF version followed by duty cycle-fixing circuitry, I opted for two 10131 dual D-FFs to provide the state machine, with 50 percent duty cycle. A 10116 line receiver provides the input interface and two-phase clock. So, a circuit of three DIP packages does the whole works. A quick paper analysis showed that it should work. I gathered up the parts and I built it onto a small vector circuit board, but it did not work. I did it relatively quickly, so probably have a wiring error to figure out. To make sure I didn't miss something, I ran a check with a simple logic simulator that I found, and it proved out OK, design-wise, so I think it should be good to go once I figure out the proper wiring. A summary of the circuit and operational simulation is attached. It should be fully synchronous and glitchless up to the toggle limit. Also, starting it from the one disallowed state seems to be no problem - it quickly cycles to the proper sequence. Using D-FF decoding within the counter section has a little more prop delay than the gated versions. I didn't check the timing limitations yet, but I'm pretty sure it will be OK at the required 50 MHz toggle rate. Ed div3 sim1.rtf Description: MS-Word document ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Looking for ECL divide by 3 with symmetry
I found I have some 10135 dual JK FFs on hand, so will try a version based on JK, that needs no extra gates, with a 10116 triple line receiver for I/O. If it turns out that symmetry is needed, I'll add a 10131 D FF, and the 10116 already provides both clock edges. Either way, it should be reasonable in simplicity and power. Ed ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Looking for ECL divide by 3 with symmetry
Thanks guys - good info. Some of these circuits must be the ones I've seen before, and some are new to me, so I'll keep them too (until I lose them again). I'm not sure if I will need symmetry in the output, but it seems better to have it for cleaning up if necessary. The resulting signal will be the reference frequency for a phase-locked microwave oscillator - the old brick style. So, it ultimately drives a class-C 2N5109 stage that drives the SRD for the sampler, with plenty of harmonic content anyway. I just have to make sure the harmonic I need doesn't somehow get canceled out or land in a null. Ed ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] Looking for ECL divide by 3 with symmetry
I need to build an ECL divide by 3 circuit to run at about 50 MHz input. I know there are lots of examples out there, but I vaguely recall years ago I stumbled upon one or more that also provided more of a symmetrical output nearly 50 percent duty factor, by using both input edges, or reclocking with another FF. I saved the info, but of course can't find it now that I need it - in my computers, papers, or online. Does anyone know of these tricks, and any example circuits - this would save me some rediscovery and design time. Ed ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Looking for ECL divide by 3 with symmetry
IIRC one would use a divide by 4 circuit with the final output feeding back to an exclusive-or gate through which the (square wave) source clock passes. The ex-or effectively adds a clock edge to the divide by four, making it divide by three. It also changes the effective clock edge, so the final output is basically a square wave. http://www.theremin.us/Circuit_Library/symmetrical_digital_dividers.html Bob LaJeunesse > Sent: Sunday, September 27, 2015 at 12:36 PM > From: "ed breya"> To: time-nuts@febo.com > Subject: [time-nuts] Looking for ECL divide by 3 with symmetry > > I need to build an ECL divide by 3 circuit to run at about 50 MHz input. > I know there are lots of examples out there, but I vaguely recall years > ago I stumbled upon one or more that also provided more of a symmetrical > output nearly 50 percent duty factor, by using both input edges, or > reclocking with another FF. I saved the info, but of course can't find > it now that I need it - in my computers, papers, or online. Does anyone > know of these tricks, and any example circuits - this would save me some > rediscovery and design time. > > Ed > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Looking for ECL divide by 3 with symmetry
I have rediscovered what I need, so no problem anymore. Ed ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Looking for ECL divide by 3 with symmetry
Division by an odd factor requires clocking off both edges of the incoming clock if you wish to achieve a 50% duty cycle output. So the output duty cycle is affected by the duty cycle and response to the possibly different risetime and falltime of the incoming clock. I would think that for the best immunity from these effects you would need to use a differential amplifier to get clean rising edges from both incoming edges. But this may be too much detail ... see the following link for some examples of how to divide by odd numbers: http://www.onsemi.com/pub_link/Collateral/AND8001-D.PDF -- Bill Byrom N5BB On Sun, Sep 27, 2015, at 11:36 AM, ed breya wrote: > I need to build an ECL divide by 3 circuit to run at about 50 MHz input. > I know there are lots of examples out there, but I vaguely recall years > ago I stumbled upon one or more that also provided more of a symmetrical > output nearly 50 percent duty factor, by using both input edges, or > reclocking with another FF. I saved the info, but of course can't find > it now that I need it - in my computers, papers, or online. Does anyone > know of these tricks, and any example circuits - this would save me some > rediscovery and design time. > > Ed > _ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Looking for ECL divide by 3 with symmetry
e...@telight.com said: > I need to build an ECL divide by 3 circuit to run at about 50 MHz input. I > know there are lots of examples out there, but I vaguely recall years ago I > stumbled upon one or more that also provided more of a symmetrical output > nearly 50 percent duty factor, by using both input edges, or reclocking > with another FF. If you you have a square wave input, you can build a clock doubler with an XOR and FF. That gives short pulses, but they are wide enough to clock FFs using that technology. You can add a delay line to make the pulse wider. (PCB traces are 6 inches per ns so you can get short delays that way.) If you are working with ECL, many parts use differential clocking so you can cleanly clock on the other edge by swapping pins. So you could make a 50-50 divide by 3 from 3 FFs: 2 for a count-to-3 FSM, and 1 clocked on the other edge, and a small cloud of gates. The FSM has 3 states. FF 1 is on for cycle 1. FF 2 is on for cycle 2. Both are off for cycle 3. FF 3 is FF 1 delayed by a 1/2 cycle. The output is FF 1 ORed with FF 3. I think the input to FF 1 is not (FF 1 or FF 2) The input to FF 2 is FF 1. The input to FF 3 is FF 1. -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.