Re: [time-nuts] Low phase noise digital divider (in 600MHz to10MHz area)
There was a thread some time ago just about that. It was probably 2007, so if you look in the archives, you should find it. I will look for it too, as I want to index it for future reference, and if I find it first, I'll post it again. Didier -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Anders Time Sent: Friday, January 25, 2008 7:02 AM To: time-nuts@febo.com Subject: [time-nuts] Low phase noise digital divider (in 600MHz to10MHz area) Have been locking around for a good article on how to design a good Low phase noise digital divider(in 600MHz to 10MHz area), but the have not found any good literature. Today most people talk about regenerative dividers, but are a rather complex subject. Does anyone have experience in what logic family that have the lowest noise TTL, AC, HC, F etc? What is the upper limit for ECL diviers? My first idea was to use ECL to divide down to 100MHz area and then to use lower noise TTL to go down to 10MHz. What about edge-conditioning circuit at divider input? Have seen people talk about it, but no info what it does? Thanks Anders No virus found in this outgoing message. Checked by AVG Free Edition. Version: 7.5.516 / Virus Database: 269.19.11/1242 - Release Date: 1/24/2008 8:32 PM ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Low phase noise digital divider (in 600MHz to10MHz area)
Anders Time wrote: Have been locking around for a good article on how to design a good Low phase noise digital divider(in 600MHz to 10MHz area), but the have not found any good literature. Today most people talk about regenerative dividers, but are a rather complex subject. Does anyone have experience in what logic family that have the lowest noise TTL, AC, HC, F etc? What is the upper limit for ECL diviers? My first idea was to use ECL to divide down to 100MHz area and then to use lower noise TTL to go down to 10MHz. What about edge-conditioning circuit at divider input? Have seen people talk about it, but no info what it does? Thanks Anders Anders The upper limit for current ECL dividers is well over 1 GHz. Theres nothing terribly fancy about the edge conditioning circuit at a divider input, its just a limiting amplifier or comparator used to amplify the input signal and reduce the input transition times seen by the divider. If you are serious about low noise division dont forget to bandpass filter the input to the divider and bandpass filter the output of each divide by 16 followed by another clock shaper. This process minimises the aliased noise at the divider output. If you want to use a programmable divider this cascaded divide and filter technique can become somewhat unwieldy. F dividers are supposed to be quieter but I havent seen any definitive measurements comparing like with like. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Low phase noise digital divider (in 600MHz to10MHz area)
Anders One option is to use just the programmable divider part of a PLL IC, such as those from National Semiconductors or Analog Devices. Or, use a Hittite HMC394 programmable counter preceded by a fast /2 flip flop. The PLLs will need serial programming via a micro-controller or other logic device; the HMC394 uses parallel programming so is easier to implement. Neither the PLLs nor the HMC394 counter need external edge conditioning - they will work with sine wave inputs. These solutions won't give you as good a phase noise performance as a regenerative divider, but if you want something that you can just plug together then they will work for relatively little effort. And you don't need to worry about -ve supply voltages which some ECL devices need. regards Grant From: Anders Time [EMAIL PROTECTED] Subject: [time-nuts] Low phase noise digital divider (in 600MHz to10MHz area) To: time-nuts@febo.com Message-ID: [EMAIL PROTECTED] Content-Type: text/plain; charset=ISO-8859-1 Have been locking around for a good article on how to design a good Low phase noise digital divider(in 600MHz to 10MHz area), but the have not found any good literature. Today most people talk about regenerative dividers, but are a rather complex subject. Does anyone have experience in what logic family that have the lowest noise TTL, AC, HC, F etc? What is the upper limit for ECL diviers? My first idea was to use ECL to divide down to 100MHz area and then to use lower noise TTL to go down to 10MHz. What about edge-conditioning circuit at divider input? Have seen people talk about it, but no info what it does? Thanks Anders ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
