Re: [time-nuts] Phase Noise/Jitter/SNR/N to Slope ratio etc
> So to summarise : To make a synthesiser`s phase noise low : > > - Apply the KIS principle [Keep It Simple] > - Use high speed [non-saturating?] logic rather than low CMOS is actually among the cleanest logic families for digital PLLs these days. ECL has always been among the worst. It was used for years because loop designers had no other choice if they needed high speed. > - The VCO resonant circuit should be of the highest > "Q" possible - Why? Higher Q means narrower bandwidth. Losses in the tank circuit lower the Q and raise the oscillator's noise floor. Another way of putting it: in any low-noise circuit you don't want more gain than necessary. That includes oscillators. Lower Q, higher loss... more gain available to amplify any noise present. Wikipedia probably has an entry for the "Leeson equation," which is worth looking at. > - Use a YIG in preference to Varicaps, and use back-to- > back matched varicaps if possible. There is nothing magical about YIG oscillators except for their linearity and the possibility of multi-octave coverage. They are difficult and expensive parts to design with; you don't use them unless you have no other choice. > - Use great care with PSU, and earth returns between the > digital [phase detector] circuits, and analogue > circuits [ VCO]. > -The VCO supply Voltage needs to be very clean, and > stable. > - Minimise the tuning range of the VCO where possible > to minimise the effect of any jitter that *does* > reach the VCO through the loop filter. The core reason for this has to do with the fact that varactor diodes have relatively-bad Q, compared to fixed capacitors and low-loss inductors. The less influence the varactor has over the overall tank capacitance, the lower the tuning range... and the higher the overall Q. It's true that oscillators with narrow tuning ranges are less susceptible to external noise from opamps, logic gates, resistors, and the like, but that's really a second-order effect if the rest of the oscillator is of quality design. -- john, KE5FX ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] Phase Noise/Jitter/SNR/N to Slope ratio etc
So to summarise : To make a synthesiser`s phase noise low :
- Apply the KIS principle [Keep It Simple]
- Use high speed [non-saturating?] logic rather than low
- The logic supplies should be well regulated, distributed
and decoupled.
- Make the PRF to the P/F detector as high as possible.
- The loop filter should have a sharp rolloff
and maintain loop stability ;-)
- The loop BW should be as low as possible.
[ ie loop filter should rolloff at the lowest frequency
tolerable]
- The reference frequency should have the highest slope to
noise ratio possible Since slope is proportional to
amplitude if frequency is constant, then this ratio
equates to a high SNR - and we all might as well
go shoot ourselves if the reference frequency
changes - eh guys ;-).
- Use quality, low noise, components in the VCO including
the active device.
- Employ great craftiness in the choice of circuit
configuration for the VCO.
- The VCO resonant circuit should be of the highest
"Q" possible - Why?
- Use a YIG in preference to Varicaps, and use back-to-
back matched varicaps if possible.
- Use great care with PSU, and earth returns between the
digital [phase detector] circuits, and analogue
circuits [ VCO].
-The VCO supply Voltage needs to be very clean, and
stable.
- Minimise the tuning range of the VCO where possible
to minimise the effect of any jitter that *does*
reach the VCO through the loop filter.
- Keep the RF Voltage across the varicaps small
[class "A" oscillator?/crafty design]
- Maximise the VCO output voltage to maximise SNR
or output amplitude to phase noise amplitude.
Some of these are at odds with each other, but can anyone
constructively criticise or refute these points, or add more, or expand on any
of them, please?
Again, thankyou for your thoughts,...Don C.
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