Re: [time-nuts] Time tagging fpga
Anders, The counter runs on a Pipistrello. I looked at the information on the web about time taggers before starting. I decided to try an oversampling scheme described by a group of Italian? physicists for a multichannel time tagging instrument. They used 4x oversampling. My version is crude; it uses the 50 MHz on-board clock but of course could use an external clock source. The clock is multiplied to 1 GHz and then divided into four 125 Hz clocks phased 45 degrees apart. There is a fifth 125 MHz clock at 0 phase for the main counter and external interface. There are four channels, each with 3 bits for value and a forth bit indicating an event. The sixteen bits are followed by a 48 bit counter value. what, if any, signal conditioning do you have between the DMTD output and the FPGA? I was thinking about copying the CERN DIO design which looks like this: http://ibin.co/1iEwLuAUQYJ4 it has a fuse, a resistor to set the input impedance, protection diodes, and an ADCMP604 that outputs an LVDS pair to the FPGA. The CERN design is for a 125 MHz clock. What would be the preferred way to generate this for the Pipistrello, with an optional 10MHz reference input? OCXO at 10MHz and a ADF4351 PLL+VCO up to 125MHz? Does someone have a tested circuit that autodetects the external 10MHz and can switch between the OCXO and ext-ref? This yields 1 ns resolution (bin size) but the bins sizes are certainly not all equal. I have few means to check the accuracy but for my purposes (logging 100 Hz to 1 Hz zero crossings of a DMTD) it is certainly more accurate than I need. I have experimented with .5 ns bin sizes, also using the 8x oversampling with a 250 MHz clock. To keep the backend 125 MHz structure I used a two phase multiplexer to combine two successive samples. This runs but is not reliable and needs further work before it's useful. Did you post the schematic for your DMTD? Many of the time-to-digital papers calibrate the bin-width by collecting time-stamps from an asynchronous pulse-source. If the bins are equal you should get a flat histogram. Some use a ring-oscillator on the fpga for generating the asynchronous hits. Anders ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Time tagging fpga
I was about to comment on this. As you interpolate among the 8 phases, time errors in the routing might need to compensated for in order to represent a flat stepping of time-compensation. It will not be perfect naturally. Cheers, Magnus On 11/23/2014 03:57 PM, Anders Wallin wrote: Anders, The counter runs on a Pipistrello. I looked at the information on the web about time taggers before starting. I decided to try an oversampling scheme described by a group of Italian? physicists for a multichannel time tagging instrument. They used 4x oversampling. My version is crude; it uses the 50 MHz on-board clock but of course could use an external clock source. The clock is multiplied to 1 GHz and then divided into four 125 Hz clocks phased 45 degrees apart. There is a fifth 125 MHz clock at 0 phase for the main counter and external interface. There are four channels, each with 3 bits for value and a forth bit indicating an event. The sixteen bits are followed by a 48 bit counter value. what, if any, signal conditioning do you have between the DMTD output and the FPGA? I was thinking about copying the CERN DIO design which looks like this: http://ibin.co/1iEwLuAUQYJ4 it has a fuse, a resistor to set the input impedance, protection diodes, and an ADCMP604 that outputs an LVDS pair to the FPGA. The CERN design is for a 125 MHz clock. What would be the preferred way to generate this for the Pipistrello, with an optional 10MHz reference input? OCXO at 10MHz and a ADF4351 PLL+VCO up to 125MHz? Does someone have a tested circuit that autodetects the external 10MHz and can switch between the OCXO and ext-ref? This yields 1 ns resolution (bin size) but the bins sizes are certainly not all equal. I have few means to check the accuracy but for my purposes (logging 100 Hz to 1 Hz zero crossings of a DMTD) it is certainly more accurate than I need. I have experimented with .5 ns bin sizes, also using the 8x oversampling with a 250 MHz clock. To keep the backend 125 MHz structure I used a two phase multiplexer to combine two successive samples. This runs but is not reliable and needs further work before it's useful. Did you post the schematic for your DMTD? Many of the time-to-digital papers calibrate the bin-width by collecting time-stamps from an asynchronous pulse-source. If the bins are equal you should get a flat histogram. Some use a ring-oscillator on the fpga for generating the asynchronous hits. Anders ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Time tagging fpga
Hi I believe the DMTD mentioned is the one done by Bill Riley. It’s at: http://www.wriley.com/A%20Small%20DMTD%20System.pdf That paper has way more info on the device and it’s signal processing than is worth going into on the list. There has been some discussion about the limiters used here on the list. I’d offer the quick summary of: they are adequate for the task. The active filtering ahead of the limiters is specific to a pre-defined range of offset frequencies / beat notes. It covers the ones most people use. The performance data shown on the site pretty well demonstrates that the box is up to any task a normal Time Nut would use it for. Those with multiple optical ion trap standards in the basement may need to tweak it a little :) Bob On Nov 23, 2014, at 9:57 AM, Anders Wallin anders.e.e.wal...@gmail.com wrote: Anders, The counter runs on a Pipistrello. I looked at the information on the web about time taggers before starting. I decided to try an oversampling scheme described by a group of Italian? physicists for a multichannel time tagging instrument. They used 4x oversampling. My version is crude; it uses the 50 MHz on-board clock but of course could use an external clock source. The clock is multiplied to 1 GHz and then divided into four 125 Hz clocks phased 45 degrees apart. There is a fifth 125 MHz clock at 0 phase for the main counter and external interface. There are four channels, each with 3 bits for value and a forth bit indicating an event. The sixteen bits are followed by a 48 bit counter value. what, if any, signal conditioning do you have between the DMTD output and the FPGA? I was thinking about copying the CERN DIO design which looks like this: http://ibin.co/1iEwLuAUQYJ4 it has a fuse, a resistor to set the input impedance, protection diodes, and an ADCMP604 that outputs an LVDS pair to the FPGA. The CERN design is for a 125 MHz clock. What would be the preferred way to generate this for the Pipistrello, with an optional 10MHz reference input? OCXO at 10MHz and a ADF4351 PLL+VCO up to 125MHz? Does someone have a tested circuit that autodetects the external 10MHz and can switch between the OCXO and ext-ref? This yields 1 ns resolution (bin size) but the bins sizes are certainly not all equal. I have few means to check the accuracy but for my purposes (logging 100 Hz to 1 Hz zero crossings of a DMTD) it is certainly more accurate than I need. I have experimented with .5 ns bin sizes, also using the 8x oversampling with a 250 MHz clock. To keep the backend 125 MHz structure I used a two phase multiplexer to combine two successive samples. This runs but is not reliable and needs further work before it's useful. Did you post the schematic for your DMTD? Many of the time-to-digital papers calibrate the bin-width by collecting time-stamps from an asynchronous pulse-source. If the bins are equal you should get a flat histogram. Some use a ring-oscillator on the fpga for generating the asynchronous hits. Anders ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Time tagging fpga
Hi If you want to go sub-nanosecond there are other ways to do the TDC in an FPGA. Numbers in the 60 to 140 ps range are fairly easy to hit with 2010 era FPGA’s. The results need to be corrected for temperature and voltage if either one moves very much. The routing delays drop out as part of the normal “random pulse” calibration process. Bob On Nov 23, 2014, at 10:55 AM, Magnus Danielson mag...@rubidium.dyndns.org wrote: I was about to comment on this. As you interpolate among the 8 phases, time errors in the routing might need to compensated for in order to represent a flat stepping of time-compensation. It will not be perfect naturally. Cheers, Magnus On 11/23/2014 03:57 PM, Anders Wallin wrote: Anders, The counter runs on a Pipistrello. I looked at the information on the web about time taggers before starting. I decided to try an oversampling scheme described by a group of Italian? physicists for a multichannel time tagging instrument. They used 4x oversampling. My version is crude; it uses the 50 MHz on-board clock but of course could use an external clock source. The clock is multiplied to 1 GHz and then divided into four 125 Hz clocks phased 45 degrees apart. There is a fifth 125 MHz clock at 0 phase for the main counter and external interface. There are four channels, each with 3 bits for value and a forth bit indicating an event. The sixteen bits are followed by a 48 bit counter value. what, if any, signal conditioning do you have between the DMTD output and the FPGA? I was thinking about copying the CERN DIO design which looks like this: http://ibin.co/1iEwLuAUQYJ4 it has a fuse, a resistor to set the input impedance, protection diodes, and an ADCMP604 that outputs an LVDS pair to the FPGA. The CERN design is for a 125 MHz clock. What would be the preferred way to generate this for the Pipistrello, with an optional 10MHz reference input? OCXO at 10MHz and a ADF4351 PLL+VCO up to 125MHz? Does someone have a tested circuit that autodetects the external 10MHz and can switch between the OCXO and ext-ref? This yields 1 ns resolution (bin size) but the bins sizes are certainly not all equal. I have few means to check the accuracy but for my purposes (logging 100 Hz to 1 Hz zero crossings of a DMTD) it is certainly more accurate than I need. I have experimented with .5 ns bin sizes, also using the 8x oversampling with a 250 MHz clock. To keep the backend 125 MHz structure I used a two phase multiplexer to combine two successive samples. This runs but is not reliable and needs further work before it's useful. Did you post the schematic for your DMTD? Many of the time-to-digital papers calibrate the bin-width by collecting time-stamps from an asynchronous pulse-source. If the bins are equal you should get a flat histogram. Some use a ring-oscillator on the fpga for generating the asynchronous hits. Anders ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Time tagging fpga
On Sat, Nov 22, 2014 at 5:37 AM, Robert Darby bobda...@triad.rr.com wrote: I finally got the time tagging fpga I was playing with to a semi-usable state. I mentioned in an earlier post that I was unable to compile or link the FTDI library but Magnus Karlsson very kindly rewrote a program of his to provide me with a utility to set up the USB asynchronous parallel interface characteristics on the PC. Only bad thing is you're running blind so it pays to do a short run to make sure all's well before committing to a long capture. Interesting! How do you generate a clock (what frequency) for the FPGA? Are you using a coarse-counter + interpolator (delay-line?) approach? I'm planning to explore this with a Pipistrello (sparta6 LX45) board, which has the same fpga used in this work: http://arxiv.org/abs/1303.6840 the VHDL is available on ohwr: http://www.ohwr.org/projects/tdc-core/wiki Anders ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Time tagging fpga
Hi The key point - it’s a counter after a mixer. You don’t need the fancy delay line / multiple delay line / strange pulse down the delay line stuff in this case. You also don’t wind up with odd algorithms to count bits and determine when a gap really is a gap. In the mix down case, a system running with a 10 MHz clock is normally adequate. A clock rate of 50 or 100 MHz on a simple counter would be overkill in most cases. You get a major error expansion when you down convert the signals. Some Math: Device under test frequency; 5 MHz Offset oscillator frequency: 5 MHz + 5 Hz Beat note 5 Hz Error expansion due to down conversion 1x10^6 If you can resolve edges at 1 second to 1x10^-7 (10 MHz clock) the net resolution would be 1x10^-13. That’s good enough for the sources being used. It improves directly by tau (1x10^-14 at 10 sec) so even if it is marginal at 1 second, it will catch up with any set of real sources somewhere inside 100 seconds In a real system, the limiters on the beat notes are more likely to be the resolution determining factor than a 10 MHz based counter. That’s all based on Bill Riley’s DMTD manual and his description of how the box works. It’s also based on the assumption that this one works the same way except the PIC is replaced by the FPGA. Bob On Nov 22, 2014, at 3:12 AM, Anders Wallin anders.e.e.wal...@gmail.com wrote: On Sat, Nov 22, 2014 at 5:37 AM, Robert Darby bobda...@triad.rr.com wrote: I finally got the time tagging fpga I was playing with to a semi-usable state. I mentioned in an earlier post that I was unable to compile or link the FTDI library but Magnus Karlsson very kindly rewrote a program of his to provide me with a utility to set up the USB asynchronous parallel interface characteristics on the PC. Only bad thing is you're running blind so it pays to do a short run to make sure all's well before committing to a long capture. Interesting! How do you generate a clock (what frequency) for the FPGA? Are you using a coarse-counter + interpolator (delay-line?) approach? I'm planning to explore this with a Pipistrello (sparta6 LX45) board, which has the same fpga used in this work: http://arxiv.org/abs/1303.6840 the VHDL is available on ohwr: http://www.ohwr.org/projects/tdc-core/wiki Anders ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Time tagging fpga
Hi Does the FPGA directly put out something that Time Lab understands? On Nov 21, 2014, at 10:37 PM, Robert Darby bobda...@triad.rr.com wrote: I finally got the time tagging fpga I was playing with to a semi-usable state. I mentioned in an earlier post That post seems to have gone astray before it got here that I was unable to compile or link the FTDI library but Magnus Karlsson very kindly rewrote a program of his to provide me with a utility to set up the USB asynchronous parallel interface characteristics on the PC. Only bad thing is you're running blind so it pays to do a short run to make sure all's well before committing to a long capture. Which suggests that you are running some sort of shim program on the PC (thus the first question). Bob I just finished a trial run using the Riley DMTD with three devices. I have a rather shaky 5065A, an Austron 1250 and an FTS 1050. The attached trace shows the 5065 misbehaving about half way through the run, the FTS displaying a periodic oscillation and the Austron just doing it's thing. It's nothing earth shattering but it sure is nice having the third clock to sort out who's being naughty or nice. I kinda suspect the FTS oscillation is related to the battery charging cycle; back in 2013 TVB mentioned he'd had problems with the FTS battery charging affecting the outputs. Anything specific to look at aside from replacing all the usual capacitor suspects? Regards, Bob Darby Capture.PNG___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Time tagging fpga
Anders, The counter runs on a Pipistrello. I looked at the information on the web about time taggers before starting. I decided to try an oversampling scheme described by a group of Italian? physicists for a multichannel time tagging instrument. They used 4x oversampling. My version is crude; it uses the 50 MHz on-board clock but of course could use an external clock source. The clock is multiplied to 1 GHz and then divided into four 125 Hz clocks phased 45 degrees apart. There is a fifth 125 MHz clock at 0 phase for the main counter and external interface. There are four channels, each with 3 bits for value and a forth bit indicating an event. The sixteen bits are followed by a 48 bit counter value. The incoming signal is sampled eight times on the positive and inverted phased clocks. The eight bits are brought back to phase 0 in an eight stage pipeline. They are decoded based on priority and added to the front of a 48 bit counter value. The output is through a 64 bit in, 8 bit out fifo fed to an asynchronous USB interface. This yields 1 ns resolution (bin size) but the bins sizes are certainly not all equal. I have few means to check the accuracy but for my purposes (logging 100 Hz to 1 Hz zero crossings of a DMTD) it is certainly more accurate than I need. I have experimented with .5 ns bin sizes, also using the 8x oversampling with a 250 MHz clock. To keep the backend 125 MHz structure I used a two phase multiplexer to combine two successive samples. This runs but is not reliable and needs further work before it's useful. Now that I can almost comprehend VHDL I'll take a look at the CERN project. Certainly the notion of a ± 92 ps tag is interesting. Bob Camp You are of course correct that nothing fancy is needed. My purpose was to replace the three PicTic counters in the Riley box with something that I felt was more reliable. Some time back I posted a question asking if variable dead time has an effect on ADEV readings. I noticed very strange variations in the slope of the phase difference as the counts got close to rollover. I wondered if, as the counter went from lets say 5 sample/s to 2.5 samples/s and then back, this was a problem. Based on my first trials, the results appear to be better because there is no dead time and effectively no phase rollover. I also wanted to learn about VHDL, VDL, and programmable logic. Know virtually nothing about the subject, a simple time tagging device that I could put to some use seemed like a good starting point. But again, for my purposes the 20 ns resolution of the Pic-Tics was more than adequate. However, I did think that it might also be useful to compare GPS 1 pps signals and therefore somewhat better resolution would be useful. As noted in my post last night, the results feed a binary file. I use several filter programs to extract the channels and the time difference between the channels. Any competent programmer (which I am not) could read the stream in real time and write the differences to an ascii file for each difference.Assuming three clocks you would then need to open three instances of Timelab. Thanks for everyone's help and Jon Mile's Timelab. Bob Darby On 11/22/2014 3:12 AM, Anders Wallin wrote: On Sat, Nov 22, 2014 at 5:37 AM, Robert Darby bobda...@triad.rr.com wrote: I finally got the time tagging fpga I was playing with to a semi-usable state. I mentioned in an earlier post that I was unable to compile or link the FTDI library but Magnus Karlsson very kindly rewrote a program of his to provide me with a utility to set up the USB asynchronous parallel interface characteristics on the PC. Only bad thing is you're running blind so it pays to do a short run to make sure all's well before committing to a long capture. Interesting! How do you generate a clock (what frequency) for the FPGA? Are you using a coarse-counter + interpolator (delay-line?) approach? I'm planning to explore this with a Pipistrello (sparta6 LX45) board, which has the same fpga used in this work: http://arxiv.org/abs/1303.6840 the VHDL is available on ohwr: http://www.ohwr.org/projects/tdc-core/wiki Anders ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Time tagging fpga
Anders, I believe the CERN carry chain idea was described in a 2006 paper A High-Resolution Time to Digital Converter Implemented in Field Programmable Gate Arrays, Jian Song, Qi An, and Shubin Liu. Might be interesting to compare the two implementations. Bob Darby On 11/22/2014 3:12 AM, Anders Wallin wrote: On Sat, Nov 22, 2014 at 5:37 AM, Robert Darby bobda...@triad.rr.com wrote: I finally got the time tagging fpga I was playing with to a semi-usable state. I mentioned in an earlier post that I was unable to compile or link the FTDI library but Magnus Karlsson very kindly rewrote a program of his to provide me with a utility to set up the USB asynchronous parallel interface characteristics on the PC. Only bad thing is you're running blind so it pays to do a short run to make sure all's well before committing to a long capture. Interesting! How do you generate a clock (what frequency) for the FPGA? Are you using a coarse-counter + interpolator (delay-line?) approach? I'm planning to explore this with a Pipistrello (sparta6 LX45) board, which has the same fpga used in this work: http://arxiv.org/abs/1303.6840 the VHDL is available on ohwr: http://www.ohwr.org/projects/tdc-core/wiki Anders ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] Time tagging fpga
I finally got the time tagging fpga I was playing with to a semi-usable state. I mentioned in an earlier post that I was unable to compile or link the FTDI library but Magnus Karlsson very kindly rewrote a program of his to provide me with a utility to set up the USB asynchronous parallel interface characteristics on the PC. Only bad thing is you're running blind so it pays to do a short run to make sure all's well before committing to a long capture. I just finished a trial run using the Riley DMTD with three devices. I have a rather shaky 5065A, an Austron 1250 and an FTS 1050. The attached trace shows the 5065 misbehaving about half way through the run, the FTS displaying a periodic oscillation and the Austron just doing it's thing. It's nothing earth shattering but it sure is nice having the third clock to sort out who's being naughty or nice. I kinda suspect the FTS oscillation is related to the battery charging cycle; back in 2013 TVB mentioned he'd had problems with the FTS battery charging affecting the outputs. Anything specific to look at aside from replacing all the usual capacitor suspects? Regards, Bob Darby ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
