Re: [time-nuts] Understanding Oliver Collins Paper Design of Low Jitter Hard Limiters
Hello Bruce and others, Thanks for the clarifications. Thanks to your e-mail, the light went on about the difference between slope gain g and voltage gain G. I'm continuing to struggle with equation 3b. We are all on the same page regarding this idea that when the clipper is at its negative or positive limits, the noise can no longer reach the filter. So by the time t = T/G, the input waveform has not yet hit its maximum at V, assuming G 1. Without any RC filter, the output waveform has hit its maximum at t = T/G. With an RC filter, the noise could be integrated over a longer period, and yet bandlimit the noise, reducing its variance. So I suppose that's the trade-off. - Too sluggish of an RC filter, and the clipping doesn't happen for a long time. - Too quick of an RC filter, and we allow more noise bandwidth to add to the jitter. Did I get that right? In the construction of equation 3b, where th T/G, could you shed some light on how this was set up? Yours Raj -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On Behalf Of Bruce Griffiths Sent: Wednesday, August 22, 2012 11:41 AM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] Understanding Oliver Collins Paper Design of Low Jitter Hard Limiters Once the gain stages enter saturation their noise contribution decreases significantly in a well designed limiter stage. The noise contribution is assumed to be zero in this state by the Collins paper. In practice, at least for low frequency limiters, power supply noise may be an issue if the limiter output isnt diode clamped. The slope gain g isnt equal to the voltage gain G due to the effect of the low pass filter on the amplifier stage output slew rate. Bruce raj_so...@agilent.com wrote: Hello Everyone, Thanks to Azelio, Bob and David for their comments. Special thanks to Magnus for clarifying the intent of this paper. I think I begin to understand the 'k' term. When I look at jitter, I actually look at residual phase noise using the E5500 phase noise measurement system. One could use a sampling oscilloscope with a clean trigger to do something similar, but for what we do here, customers want to know phase noise spectral density versus frequency. I have found the region between 1 Hz and 100 Hz offsets to be particularly challenging. Jason Breitbarth, CEO of Holtzworth, wrote a nice paper for microwave Journal on residual phase noise. http://www.holzworth.com/Aux_docs/PhaseNoise_Article_MWJ_Jun08.pdf I have thought more critically about my block diagram, and fortunately, I'm not trying to square up sine waves from 1 MHz to 100 MHz. These are generated using ECL counters and re-clocking. Just yesterday, I proved to myself that this was working correctly. But there is a situation where I submit a 100 MHz sine wave to this limiter, which then serves as the reference for a phase lock loop. The residual noise of the loop is much higher when the LO is a sine wave as compared to when driven by a square wave. This is straightforward to visualize. A zero crossing detector will be much more sensitive to noise when the input is a shallow sloped sine wave as compared to a sharp edged square wave. Perhaps I just need to tinker with the limiter, checking supply noise suppression, thermal noise, etc. Magnus makes a very good point that the paper only considers a simplified model using white noise as the input. Perhaps once the mathematics have been understood, one could extend the analysis to include 1/f noise at 10 Hz and 100 Hz. But even with white noise input, the mathematics seem crazy hard. I asked around a couple of folks around here, and the typical response was has been too many years since I looked at this type of math. So this could be a good way for me to refresh. In figures 2 and 3, Collins presents the basic model. An input signal rises from 0 V to V V between times 0 and T. The input slope 'rho_in' is V/T. Going through an amplifier of gain G, the output waveform is sharper, transitioning from 0 V to V V between times 0 and T/G. The output slope during the transition period could be related as rho_out (output slope) = g (slope gain) * rho_in (input slope). Dividing the basic voltage gain equation Vout = G * Vin by time, can we reasonably say that voltage gain G is the same as slope gain g? Assuming white noise at the input of variance No, the autocorrelation function is Rxx(tau) = No*delta(tau). Submitting the amplified random signal through a simple RC low pass filter, we obtain the result of equation 2. In the development of equation 3, the author states that the noise input is not applied for all time. Rather, it is turned on at time 0 and turned off at time T/G. So equation 3a is a reasonable modification of equation 2; rather than integrate from zero to infinity, integrate from zero to 'th
Re: [time-nuts] Understanding Oliver Collins Paper Design of Low Jitter Hard Limiters
On Wed, 22 Aug 2012 19:00:10 -0700, Hal Murray hmur...@megapathdsl.net wrote: jmulc...@cox.net said: The amount of jitter verses logic family is all over the place as well. Take a look at an LS verses an HCT vs an S family and you will see what I mean. Some of them are very nasty, and are not all created equally. Is there any collection of hard data? How much does it depend upon manufacturer or test setup? How much couples through from power supply? I have not seen any. The jitter varies not only between logic families but also between manufacturers and IC processes. It is usually unimportant for logic intended for synchronous applications. The circuit design itself can be critical. If you want to avoid testing and qualifying parts, then some of the faster logic families have guaranteed jitter specifications. They also tend to include switching threshold control or compensation to increase power supply rejection. Does the jitter scale with prop-time? Usually but not always. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Understanding Oliver Collins Paper Design of Low Jitter Hard Limiters
Hi In general, saturated logic (TTL / CMOS) will do better than non-saturated (ECL / LVDS). Faster with saturated generally = better, provided it's silicon. Once you go to high mobility semiconductors the 1/f noise picks up. Yes, you need a quiet supply. How quiet is going to depend on your edge rates, input frequencies, phase noise offsets, the coupling circuit, and the logic used. Put another way - you need to test your circuit. There are bits and pieces of that very limited summary scattered across several hundred papers and data sheets. Bob On Aug 22, 2012, at 10:00 PM, Hal Murray hmur...@megapathdsl.net wrote: jmulc...@cox.net said: The amount of jitter verses logic family is all over the place as well. Take a look at an LS verses an HCT vs an S family and you will see what I mean. Some of them are very nasty, and are not all created equally. Is there any collection of hard data? How much does it depend upon manufacturer or test setup? How much couples through from power supply? Does the jitter scale with prop-time? -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Understanding Oliver Collins Paper Design of Low Jitter Hard Limiters
On 08/24/2012 12:07 AM, Bob Camp wrote: Hi In general, saturated logic (TTL / CMOS) will do better than non-saturated (ECL / LVDS). Faster with saturated generally = better, provided it's silicon. Once you go to high mobility semiconductors the 1/f noise picks up. Yes, you need a quiet supply. How quiet is going to depend on your edge rates, input frequencies, phase noise offsets, the coupling circuit, and the logic used. Put another way - you need to test your circuit. There are bits and pieces of that very limited summary scattered across several hundred papers and data sheets. NIST has only made a few papers on it, and to some degree it is inconclusive. Also, it doesn't give good hints on more current logic as it was made ages ago. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Understanding Oliver Collins Paper Design of Low Jitter Hard Limiters
In your opinion, if I build a 7404 ZCD and a hard limiter one, can I see the jitter difference on a simple 'scope (Tek TDS220 or TDS3012) or do I need the Wavecrest SIA3000? On Wed, Aug 22, 2012 at 1:37 AM, Bob Camp li...@rtty.us wrote: Hi Since the Collins approach tunes the system for a single frequency input (more or less), the approach is probably not the best for a many decades sort of frequency range. There are a number of things that he alludes to in the paper, but does not directly address. The most obvious is the temperature dependance of the stuff the system is made of. Another is the simple fact that a non-clipping linear amplifier is likely the best choice for a first stage, provide the input is not already near clipping. Bob On Aug 21, 2012, at 12:50 PM, raj_so...@agilent.com wrote: Hello everyone, I am new to this forum. It looks like a lively discussion on various topics. A colleague of mine here at Agilent pointed me to this paper entitled The Design of Low Jitter Hard Limiters by Oliver Collins. In Bruce Griffiths' precision time in frequency webpage, this paper is described as seminal. (http://www.ko4bb.com/~bruce/ZeroCrossingDetectors.html) Since I'm trying to create a limiter that will accept frequencies ranging from 1 MHz to 100 MHz, I thought it would be good to understand the conclusions of this paper (if not the mathematics as well). The mathematics turned out to be quite challenging to decode. Has someone on this forum unraveled the equations? It appears Collins has recommendations on the bandwidth and gain of a jitter minimizing limiter, and then extends this analysis to provide the bandwidth and gain of a cascade of limiters. But the application is still fuzzy. In figure 5, he shows a graph showing the dependence of jitter on crossing time. Is the crossing time (implied by equations 7) considered a design parameter one can vary? Also, on figure 4, the k parameter has been varied to show the rising waveform as a function of k. The threshold is always assumed to be 0.5. So could k be related to tau, the time constant of the RC filter? Thanks in advance for all your help. Yours Raj ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Understanding Oliver Collins Paper Design of Low Jitter Hard Limiters
Do you mean with a 7404 hex inverter? I actually did something like this recently while adding a 75ns pre-trigger pulse to an existing fast rise pulse generator. The pre-trigger pulse ended up having significant pattern dependant jitter caused by the adjacent TTL divider chain modulating the supply voltage and the poor power supply rejection of the 7404. I was easily able to see the jitter on my 7T11 sampling oscilloscope but on my 2440 (20 GS/sec equivalent time sampling), it was barely perceptible if that despite ideal conditions. The peak to peak jitter was about 100ps. As far as I could tell from the available online documentation, the TDS220 and TDS3012 have relatively low sample rates and do not support equivalent time sampling so I would expect them to show even less than my 2440. On Wed, 22 Aug 2012 11:55:11 +0200, Azelio Boriani azelio.bori...@screen.it wrote: In your opinion, if I build a 7404 ZCD and a hard limiter one, can I see the jitter difference on a simple 'scope (Tek TDS220 or TDS3012) or do I need the Wavecrest SIA3000? On Wed, Aug 22, 2012 at 1:37 AM, Bob Camp li...@rtty.us wrote: Hi Since the Collins approach tunes the system for a single frequency input (more or less), the approach is probably not the best for a many decades sort of frequency range. There are a number of things that he alludes to in the paper, but does not directly address. The most obvious is the temperature dependance of the stuff the system is made of. Another is the simple fact that a non-clipping linear amplifier is likely the best choice for a first stage, provide the input is not already near clipping. Bob On Aug 21, 2012, at 12:50 PM, raj_so...@agilent.com wrote: Hello everyone, I am new to this forum. It looks like a lively discussion on various topics. A colleague of mine here at Agilent pointed me to this paper entitled The Design of Low Jitter Hard Limiters by Oliver Collins. In Bruce Griffiths' precision time in frequency webpage, this paper is described as seminal. (http://www.ko4bb.com/~bruce/ZeroCrossingDetectors.html) Since I'm trying to create a limiter that will accept frequencies ranging from 1 MHz to 100 MHz, I thought it would be good to understand the conclusions of this paper (if not the mathematics as well). The mathematics turned out to be quite challenging to decode. Has someone on this forum unraveled the equations? It appears Collins has recommendations on the bandwidth and gain of a jitter minimizing limiter, and then extends this analysis to provide the bandwidth and gain of a cascade of limiters. But the application is still fuzzy. In figure 5, he shows a graph showing the dependence of jitter on crossing time. Is the crossing time (implied by equations 7) considered a design parameter one can vary? Also, on figure 4, the k parameter has been varied to show the rising waveform as a function of k. The threshold is always assumed to be 0.5. So could k be related to tau, the time constant of the RC filter? Thanks in advance for all your help. Yours Raj ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Understanding Oliver Collins Paper Design of Low Jitter Hard Limiters
According to http://cp.literature.agilent.com/litweb/pdf/5989-8794EN.pdf the real time sampling scope (like the TDS220 or TDS3012) can measure cycle to cycle jitter directly, whereas the equivalent time sampling has only one sample each trigger and a little delay on the sampling point for the next trigger. The displayed waveform is a sort of sum of more than one cycle and now I can't figure out what type of picture this can give. The TDS3012 has also the advantage of the Digital Phosphor behavior that can be useful for the jitter analysis. Maybe a stable timebase and low jitter external trigger input are essential. Unfortunately the TDS3012 has a 200ppm timebase... On Wed, Aug 22, 2012 at 2:54 PM, David davidwh...@gmail.com wrote: Do you mean with a 7404 hex inverter? I actually did something like this recently while adding a 75ns pre-trigger pulse to an existing fast rise pulse generator. The pre-trigger pulse ended up having significant pattern dependant jitter caused by the adjacent TTL divider chain modulating the supply voltage and the poor power supply rejection of the 7404. I was easily able to see the jitter on my 7T11 sampling oscilloscope but on my 2440 (20 GS/sec equivalent time sampling), it was barely perceptible if that despite ideal conditions. The peak to peak jitter was about 100ps. As far as I could tell from the available online documentation, the TDS220 and TDS3012 have relatively low sample rates and do not support equivalent time sampling so I would expect them to show even less than my 2440. On Wed, 22 Aug 2012 11:55:11 +0200, Azelio Boriani azelio.bori...@screen.it wrote: In your opinion, if I build a 7404 ZCD and a hard limiter one, can I see the jitter difference on a simple 'scope (Tek TDS220 or TDS3012) or do I need the Wavecrest SIA3000? On Wed, Aug 22, 2012 at 1:37 AM, Bob Camp li...@rtty.us wrote: Hi Since the Collins approach tunes the system for a single frequency input (more or less), the approach is probably not the best for a many decades sort of frequency range. There are a number of things that he alludes to in the paper, but does not directly address. The most obvious is the temperature dependance of the stuff the system is made of. Another is the simple fact that a non-clipping linear amplifier is likely the best choice for a first stage, provide the input is not already near clipping. Bob On Aug 21, 2012, at 12:50 PM, raj_so...@agilent.com wrote: Hello everyone, I am new to this forum. It looks like a lively discussion on various topics. A colleague of mine here at Agilent pointed me to this paper entitled The Design of Low Jitter Hard Limiters by Oliver Collins. In Bruce Griffiths' precision time in frequency webpage, this paper is described as seminal. (http://www.ko4bb.com/~bruce/ZeroCrossingDetectors.html) Since I'm trying to create a limiter that will accept frequencies ranging from 1 MHz to 100 MHz, I thought it would be good to understand the conclusions of this paper (if not the mathematics as well). The mathematics turned out to be quite challenging to decode. Has someone on this forum unraveled the equations? It appears Collins has recommendations on the bandwidth and gain of a jitter minimizing limiter, and then extends this analysis to provide the bandwidth and gain of a cascade of limiters. But the application is still fuzzy. In figure 5, he shows a graph showing the dependence of jitter on crossing time. Is the crossing time (implied by equations 7) considered a design parameter one can vary? Also, on figure 4, the k parameter has been varied to show the rising waveform as a function of k. The threshold is always assumed to be 0.5. So could k be related to tau, the time constant of the RC filter? Thanks in advance for all your help. Yours Raj ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions
Re: [time-nuts] Understanding Oliver Collins Paper Design of Low Jitter Hard Limiters
Hi It depends very much on just how low a frequency sine wave you put into the limiter. If you run low enough, then indeed you will be able to see the difference. If the scope can display 1 ns jitter, then a 1 Hz sine wave is likely to be low enough. Bob -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On Behalf Of Azelio Boriani Sent: Wednesday, August 22, 2012 5:55 AM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] Understanding Oliver Collins Paper Design of Low Jitter Hard Limiters In your opinion, if I build a 7404 ZCD and a hard limiter one, can I see the jitter difference on a simple 'scope (Tek TDS220 or TDS3012) or do I need the Wavecrest SIA3000? On Wed, Aug 22, 2012 at 1:37 AM, Bob Camp li...@rtty.us wrote: Hi Since the Collins approach tunes the system for a single frequency input (more or less), the approach is probably not the best for a many decades sort of frequency range. There are a number of things that he alludes to in the paper, but does not directly address. The most obvious is the temperature dependance of the stuff the system is made of. Another is the simple fact that a non-clipping linear amplifier is likely the best choice for a first stage, provide the input is not already near clipping. Bob On Aug 21, 2012, at 12:50 PM, raj_so...@agilent.com wrote: Hello everyone, I am new to this forum. It looks like a lively discussion on various topics. A colleague of mine here at Agilent pointed me to this paper entitled The Design of Low Jitter Hard Limiters by Oliver Collins. In Bruce Griffiths' precision time in frequency webpage, this paper is described as seminal. (http://www.ko4bb.com/~bruce/ZeroCrossingDetectors.html) Since I'm trying to create a limiter that will accept frequencies ranging from 1 MHz to 100 MHz, I thought it would be good to understand the conclusions of this paper (if not the mathematics as well). The mathematics turned out to be quite challenging to decode. Has someone on this forum unraveled the equations? It appears Collins has recommendations on the bandwidth and gain of a jitter minimizing limiter, and then extends this analysis to provide the bandwidth and gain of a cascade of limiters. But the application is still fuzzy. In figure 5, he shows a graph showing the dependence of jitter on crossing time. Is the crossing time (implied by equations 7) considered a design parameter one can vary? Also, on figure 4, the k parameter has been varied to show the rising waveform as a function of k. The threshold is always assumed to be 0.5. So could k be related to tau, the time constant of the RC filter? Thanks in advance for all your help. Yours Raj ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Understanding Oliver Collins Paper Design of Low Jitter Hard Limiters
Hello Everyone, Thanks to Azelio, Bob and David for their comments. Special thanks to Magnus for clarifying the intent of this paper. I think I begin to understand the 'k' term. When I look at jitter, I actually look at residual phase noise using the E5500 phase noise measurement system. One could use a sampling oscilloscope with a clean trigger to do something similar, but for what we do here, customers want to know phase noise spectral density versus frequency. I have found the region between 1 Hz and 100 Hz offsets to be particularly challenging. Jason Breitbarth, CEO of Holtzworth, wrote a nice paper for microwave Journal on residual phase noise. http://www.holzworth.com/Aux_docs/PhaseNoise_Article_MWJ_Jun08.pdf I have thought more critically about my block diagram, and fortunately, I'm not trying to square up sine waves from 1 MHz to 100 MHz. These are generated using ECL counters and re-clocking. Just yesterday, I proved to myself that this was working correctly. But there is a situation where I submit a 100 MHz sine wave to this limiter, which then serves as the reference for a phase lock loop. The residual noise of the loop is much higher when the LO is a sine wave as compared to when driven by a square wave. This is straightforward to visualize. A zero crossing detector will be much more sensitive to noise when the input is a shallow sloped sine wave as compared to a sharp edged square wave. Perhaps I just need to tinker with the limiter, checking supply noise suppression, thermal noise, etc. Magnus makes a very good point that the paper only considers a simplified model using white noise as the input. Perhaps once the mathematics have been understood, one could extend the analysis to include 1/f noise at 10 Hz and 100 Hz. But even with white noise input, the mathematics seem crazy hard. I asked around a couple of folks around here, and the typical response was has been too many years since I looked at this type of math. So this could be a good way for me to refresh. In figures 2 and 3, Collins presents the basic model. An input signal rises from 0 V to V V between times 0 and T. The input slope 'rho_in' is V/T. Going through an amplifier of gain G, the output waveform is sharper, transitioning from 0 V to V V between times 0 and T/G. The output slope during the transition period could be related as rho_out (output slope) = g (slope gain) * rho_in (input slope). Dividing the basic voltage gain equation Vout = G * Vin by time, can we reasonably say that voltage gain G is the same as slope gain g? Assuming white noise at the input of variance No, the autocorrelation function is Rxx(tau) = No*delta(tau). Submitting the amplified random signal through a simple RC low pass filter, we obtain the result of equation 2. In the development of equation 3, the author states that the noise input is not applied for all time. Rather, it is turned on at time 0 and turned off at time T/G. So equation 3a is a reasonable modification of equation 2; rather than integrate from zero to infinity, integrate from zero to 'th', the threshold crossing time. But equation 3b has me spinning my wheels. For th T/G, noise deposited to the capacitor in the filter is now dissipating? But we do not consider noise added once the limiter has saturated, or do we? Yours Raj -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On Behalf Of Azelio Boriani Sent: Wednesday, August 22, 2012 6:44 AM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] Understanding Oliver Collins Paper Design of Low Jitter Hard Limiters According to http://cp.literature.agilent.com/litweb/pdf/5989-8794EN.pdf the real time sampling scope (like the TDS220 or TDS3012) can measure cycle to cycle jitter directly, whereas the equivalent time sampling has only one sample each trigger and a little delay on the sampling point for the next trigger. The displayed waveform is a sort of sum of more than one cycle and now I can't figure out what type of picture this can give. The TDS3012 has also the advantage of the Digital Phosphor behavior that can be useful for the jitter analysis. Maybe a stable timebase and low jitter external trigger input are essential. Unfortunately the TDS3012 has a 200ppm timebase... On Wed, Aug 22, 2012 at 2:54 PM, David davidwh...@gmail.com wrote: Do you mean with a 7404 hex inverter? I actually did something like this recently while adding a 75ns pre-trigger pulse to an existing fast rise pulse generator. The pre-trigger pulse ended up having significant pattern dependant jitter caused by the adjacent TTL divider chain modulating the supply voltage and the poor power supply rejection of the 7404. I was easily able to see the jitter on my 7T11 sampling oscilloscope but on my 2440 (20 GS/sec equivalent time sampling), it was barely perceptible if that despite ideal conditions
Re: [time-nuts] Understanding Oliver Collins Paper Design of Low Jitter Hard Limiters
I was not measuring cycle to cycle jitter but the input to output jitter of a TTL gate itself when used as part of a delay circuit. The input circuit and input waveform to the gate are very similar to what would be expected in a sine wave zero crossing detector. Using a 7S11/7T11 in sequential sampling mode, I could see the jitter fine on any analog 7000 series oscilloscope but to get a nicer photo, I used a 7834 in variable persistence mode. The trigger occurs about 80ns before the displayed fast rise pulse. Most of the jitter is a product of the low power supply rejection of the TTL gate and input circuit. http://www.banishedsouls.org/c2df3757f1/PG506/PDJ%20Test%201b%20-%201.jpg Using hard limiting before the zero crossing detector will relax the design of the later significantly. Differential signal paths would help considerably as well. From going through the manuals and specifications, I am just not sure the TDS220 or TDS3012 has the time base resolution necessary to compare the jitter from the two different designs. On my 2440, it was very difficult to see any difference between no jitter and the jitter in the example I linked above. On Wed, 22 Aug 2012 15:44:10 +0200, Azelio Boriani azelio.bori...@screen.it wrote: According to http://cp.literature.agilent.com/litweb/pdf/5989-8794EN.pdf the real time sampling scope (like the TDS220 or TDS3012) can measure cycle to cycle jitter directly, whereas the equivalent time sampling has only one sample each trigger and a little delay on the sampling point for the next trigger. The displayed waveform is a sort of sum of more than one cycle and now I can't figure out what type of picture this can give. The TDS3012 has also the advantage of the Digital Phosphor behavior that can be useful for the jitter analysis. Maybe a stable timebase and low jitter external trigger input are essential. Unfortunately the TDS3012 has a 200ppm timebase... On Wed, Aug 22, 2012 at 2:54 PM, David davidwh...@gmail.com wrote: Do you mean with a 7404 hex inverter? I actually did something like this recently while adding a 75ns pre-trigger pulse to an existing fast rise pulse generator. The pre-trigger pulse ended up having significant pattern dependant jitter caused by the adjacent TTL divider chain modulating the supply voltage and the poor power supply rejection of the 7404. I was easily able to see the jitter on my 7T11 sampling oscilloscope but on my 2440 (20 GS/sec equivalent time sampling), it was barely perceptible if that despite ideal conditions. The peak to peak jitter was about 100ps. As far as I could tell from the available online documentation, the TDS220 and TDS3012 have relatively low sample rates and do not support equivalent time sampling so I would expect them to show even less than my 2440. On Wed, 22 Aug 2012 11:55:11 +0200, Azelio Boriani azelio.bori...@screen.it wrote: In your opinion, if I build a 7404 ZCD and a hard limiter one, can I see the jitter difference on a simple 'scope (Tek TDS220 or TDS3012) or do I need the Wavecrest SIA3000? On Wed, Aug 22, 2012 at 1:37 AM, Bob Camp li...@rtty.us wrote: Hi Since the Collins approach tunes the system for a single frequency input (more or less), the approach is probably not the best for a many decades sort of frequency range. There are a number of things that he alludes to in the paper, but does not directly address. The most obvious is the temperature dependance of the stuff the system is made of. Another is the simple fact that a non-clipping linear amplifier is likely the best choice for a first stage, provide the input is not already near clipping. Bob On Aug 21, 2012, at 12:50 PM, raj_so...@agilent.com wrote: Hello everyone, I am new to this forum. It looks like a lively discussion on various topics. A colleague of mine here at Agilent pointed me to this paper entitled The Design of Low Jitter Hard Limiters by Oliver Collins. In Bruce Griffiths' precision time in frequency webpage, this paper is described as seminal. (http://www.ko4bb.com/~bruce/ZeroCrossingDetectors.html) Since I'm trying to create a limiter that will accept frequencies ranging from 1 MHz to 100 MHz, I thought it would be good to understand the conclusions of this paper (if not the mathematics as well). The mathematics turned out to be quite challenging to decode. Has someone on this forum unraveled the equations? It appears Collins has recommendations on the bandwidth and gain of a jitter minimizing limiter, and then extends this analysis to provide the bandwidth and gain of a cascade of limiters. But the application is still fuzzy. In figure 5, he shows a graph showing the dependence of jitter on crossing time. Is the crossing time (implied by equations 7) considered a design parameter one can vary? Also, on figure 4, the k parameter has been varied to show the rising waveform as a function of k.
Re: [time-nuts] Understanding Oliver Collins Paper Design of Low Jitter Hard Limiters
Once the gain stages enter saturation their noise contribution decreases significantly in a well designed limiter stage. The noise contribution is assumed to be zero in this state by the Collins paper. In practice, at least for low frequency limiters, power supply noise may be an issue if the limiter output isnt diode clamped. The slope gain g isnt equal to the voltage gain G due to the effect of the low pass filter on the amplifier stage output slew rate. Bruce raj_so...@agilent.com wrote: Hello Everyone, Thanks to Azelio, Bob and David for their comments. Special thanks to Magnus for clarifying the intent of this paper. I think I begin to understand the 'k' term. When I look at jitter, I actually look at residual phase noise using the E5500 phase noise measurement system. One could use a sampling oscilloscope with a clean trigger to do something similar, but for what we do here, customers want to know phase noise spectral density versus frequency. I have found the region between 1 Hz and 100 Hz offsets to be particularly challenging. Jason Breitbarth, CEO of Holtzworth, wrote a nice paper for microwave Journal on residual phase noise. http://www.holzworth.com/Aux_docs/PhaseNoise_Article_MWJ_Jun08.pdf I have thought more critically about my block diagram, and fortunately, I'm not trying to square up sine waves from 1 MHz to 100 MHz. These are generated using ECL counters and re-clocking. Just yesterday, I proved to myself that this was working correctly. But there is a situation where I submit a 100 MHz sine wave to this limiter, which then serves as the reference for a phase lock loop. The residual noise of the loop is much higher when the LO is a sine wave as compared to when driven by a square wave. This is straightforward to visualize. A zero crossing detector will be much more sensitive to noise when the input is a shallow sloped sine wave as compared to a sharp edged square wave. Perhaps I just need to tinker with the limiter, checking supply noise suppression, thermal noise, etc. Magnus makes a very good point that the paper only considers a simplified model using white noise as the input. Perhaps once the mathematics have been understood, one could extend the analysis to include 1/f noise at 10 Hz and 100 Hz. But even with white noise input, the mathematics seem crazy hard. I asked around a couple of folks around here, and the typical response was has been too many years since I looked at this type of math. So this could be a good way for me to refresh. In figures 2 and 3, Collins presents the basic model. An input signal rises from 0 V to V V between times 0 and T. The input slope 'rho_in' is V/T. Going through an amplifier of gain G, the output waveform is sharper, transitioning from 0 V to V V between times 0 and T/G. The output slope during the transition period could be related as rho_out (output slope) = g (slope gain) * rho_in (input slope). Dividing the basic voltage gain equation Vout = G * Vin by time, can we reasonably say that voltage gain G is the same as slope gain g? Assuming white noise at the input of variance No, the autocorrelation function is Rxx(tau) = No*delta(tau). Submitting the amplified random signal through a simple RC low pass filter, we obtain the result of equation 2. In the development of equation 3, the author states that the noise input is not applied for all time. Rather, it is turned on at time 0 and turned off at time T/G. So equation 3a is a reasonable modification of equation 2; rather than integrate from zero to infinity, integrate from zero to 'th', the threshold crossing time. But equation 3b has me spinning my wheels. For th T/G, noise deposited to the capacitor in the filter is now dissipating? But we do not consider noise added once the limiter has saturated, or do we? Yours Raj -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On Behalf Of Azelio Boriani Sent: Wednesday, August 22, 2012 6:44 AM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] Understanding Oliver Collins Paper Design of Low Jitter Hard Limiters According to http://cp.literature.agilent.com/litweb/pdf/5989-8794EN.pdf the real time sampling scope (like the TDS220 or TDS3012) can measure cycle to cycle jitter directly, whereas the equivalent time sampling has only one sample each trigger and a little delay on the sampling point for the next trigger. The displayed waveform is a sort of sum of more than one cycle and now I can't figure out what type of picture this can give. The TDS3012 has also the advantage of the Digital Phosphor behavior that can be useful for the jitter analysis. Maybe a stable timebase and low jitter external trigger input are essential. Unfortunately the TDS3012 has a 200ppm timebase... On Wed, Aug 22, 2012 at 2:54 PM, Daviddavidwh...@gmail.com wrote: Do you mean with a 7404 hex inverter? I actually
Re: [time-nuts] Understanding Oliver Collins Paper Design of Low Jitter Hard Limiters
The amount of jitter verses logic family is all over the place as well. Take a look at an LS verses an HCT vs an S family and you will see what I mean. Some of them are very nasty, and are not all created equally. Jerry At 09:58 AM 8/22/2012, you wrote: I was not measuring cycle to cycle jitter but the input to output jitter of a TTL gate itself when used as part of a delay circuit. The input circuit and input waveform to the gate are very similar to what would be expected in a sine wave zero crossing detector. Using a 7S11/7T11 in sequential sampling mode, I could see the jitter fine on any analog 7000 series oscilloscope but to get a nicer photo, I used a 7834 in variable persistence mode. The trigger occurs about 80ns before the displayed fast rise pulse. Most of the jitter is a product of the low power supply rejection of the TTL gate and input circuit. http://www.banishedsouls.org/c2df3757f1/PG506/PDJ%20Test%201b%20-%201.jpg Using hard limiting before the zero crossing detector will relax the design of the later significantly. Differential signal paths would help considerably as well. From going through the manuals and specifications, I am just not sure the TDS220 or TDS3012 has the time base resolution necessary to compare the jitter from the two different designs. On my 2440, it was very difficult to see any difference between no jitter and the jitter in the example I linked above. On Wed, 22 Aug 2012 15:44:10 +0200, Azelio Boriani azelio.bori...@screen.it wrote: According to http://cp.literature.agilent.com/litweb/pdf/5989-8794EN.pdf the real time sampling scope (like the TDS220 or TDS3012) can measure cycle to cycle jitter directly, whereas the equivalent time sampling has only one sample each trigger and a little delay on the sampling point for the next trigger. The displayed waveform is a sort of sum of more than one cycle and now I can't figure out what type of picture this can give. The TDS3012 has also the advantage of the Digital Phosphor behavior that can be useful for the jitter analysis. Maybe a stable timebase and low jitter external trigger input are essential. Unfortunately the TDS3012 has a 200ppm timebase... On Wed, Aug 22, 2012 at 2:54 PM, David davidwh...@gmail.com wrote: Do you mean with a 7404 hex inverter? I actually did something like this recently while adding a 75ns pre-trigger pulse to an existing fast rise pulse generator. The pre-trigger pulse ended up having significant pattern dependant jitter caused by the adjacent TTL divider chain modulating the supply voltage and the poor power supply rejection of the 7404. I was easily able to see the jitter on my 7T11 sampling oscilloscope but on my 2440 (20 GS/sec equivalent time sampling), it was barely perceptible if that despite ideal conditions. The peak to peak jitter was about 100ps. As far as I could tell from the available online documentation, the TDS220 and TDS3012 have relatively low sample rates and do not support equivalent time sampling so I would expect them to show even less than my 2440. On Wed, 22 Aug 2012 11:55:11 +0200, Azelio Boriani azelio.bori...@screen.it wrote: In your opinion, if I build a 7404 ZCD and a hard limiter one, can I see the jitter difference on a simple 'scope (Tek TDS220 or TDS3012) or do I need the Wavecrest SIA3000? On Wed, Aug 22, 2012 at 1:37 AM, Bob Camp li...@rtty.us wrote: Hi Since the Collins approach tunes the system for a single frequency input (more or less), the approach is probably not the best for a many decades sort of frequency range. There are a number of things that he alludes to in the paper, but does not directly address. The most obvious is the temperature dependance of the stuff the system is made of. Another is the simple fact that a non-clipping linear amplifier is likely the best choice for a first stage, provide the input is not already near clipping. Bob On Aug 21, 2012, at 12:50 PM, raj_so...@agilent.com wrote: Hello everyone, I am new to this forum. It looks like a lively discussion on various topics. A colleague of mine here at Agilent pointed me to this paper entitled The Design of Low Jitter Hard Limiters by Oliver Collins. In Bruce Griffiths' precision time in frequency webpage, this paper is described as seminal. (http://www.ko4bb.com/~bruce/ZeroCrossingDetectors.html) Since I'm trying to create a limiter that will accept frequencies ranging from 1 MHz to 100 MHz, I thought it would be good to understand the conclusions of this paper (if not the mathematics as well). The mathematics turned out to be quite challenging to decode. Has someone on this forum unraveled the equations? It appears Collins has recommendations on the bandwidth and gain of a jitter minimizing limiter, and then extends this analysis to provide the bandwidth and gain of a cascade of limiters. But the application is still fuzzy. In figure 5, he shows a
Re: [time-nuts] Understanding Oliver Collins Paper Design of Low Jitter Hard Limiters
jmulc...@cox.net said: The amount of jitter verses logic family is all over the place as well. Take a look at an LS verses an HCT vs an S family and you will see what I mean. Some of them are very nasty, and are not all created equally. Is there any collection of hard data? How much does it depend upon manufacturer or test setup? How much couples through from power supply? Does the jitter scale with prop-time? -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] Understanding Oliver Collins Paper Design of Low Jitter Hard Limiters
Hello everyone, I am new to this forum. It looks like a lively discussion on various topics. A colleague of mine here at Agilent pointed me to this paper entitled The Design of Low Jitter Hard Limiters by Oliver Collins. In Bruce Griffiths' precision time in frequency webpage, this paper is described as seminal. (http://www.ko4bb.com/~bruce/ZeroCrossingDetectors.html) Since I'm trying to create a limiter that will accept frequencies ranging from 1 MHz to 100 MHz, I thought it would be good to understand the conclusions of this paper (if not the mathematics as well). The mathematics turned out to be quite challenging to decode. Has someone on this forum unraveled the equations? It appears Collins has recommendations on the bandwidth and gain of a jitter minimizing limiter, and then extends this analysis to provide the bandwidth and gain of a cascade of limiters. But the application is still fuzzy. In figure 5, he shows a graph showing the dependence of jitter on crossing time. Is the crossing time (implied by equations 7) considered a design parameter one can vary? Also, on figure 4, the k parameter has been varied to show the rising waveform as a function of k. The threshold is always assumed to be 0.5. So could k be related to tau, the time constant of the RC filter? Thanks in advance for all your help. Yours Raj ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Understanding Oliver Collins Paper Design of Low Jitter Hard Limiters
On Tue, 21 Aug 2012 10:50:43 -0600, raj_so...@agilent.com wrote: Hello everyone, I am new to this forum. It looks like a lively discussion on various topics. A colleague of mine here at Agilent pointed me to this paper entitled The Design of Low Jitter Hard Limiters by Oliver Collins. In Bruce Griffiths' precision time in frequency webpage, this paper is described as seminal. (http://www.ko4bb.com/~bruce/ZeroCrossingDetectors.html) Since I'm trying to create a limiter that will accept frequencies ranging from 1 MHz to 100 MHz, I thought it would be good to understand the conclusions of this paper (if not the mathematics as well). The mathematics turned out to be quite challenging to decode. Has someone on this forum unraveled the equations? It appears Collins has recommendations on the bandwidth and gain of a jitter minimizing limiter, and then extends this analysis to provide the bandwidth and gain of a cascade of limiters. But the application is still fuzzy. In figure 5, he shows a graph showing the dependence of jitter on crossing time. Is the crossing time (implied by equations 7) considered a design parameter one can vary? Also, on figure 4, the k parameter has been varied to show the rising waveform as a function of k. The threshold is always assumed to be 0.5. So could k be related to tau, the time constant of the RC filter? Thanks in advance for all your help. Yours Raj I would love to take a look at this but the links to the paper at the IEEE are dead. My Google search just turned up others looking for the same paper. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Understanding Oliver Collins Paper Design of Low Jitter Hard Limiters
On 8/21/2012 1:22 PM, David wrote: On Tue, 21 Aug 2012 10:50:43 -0600,raj_so...@agilent.com wrote: Hello everyone, I am new to this forum. It looks like a lively discussion on various topics. A colleague of mine here at Agilent pointed me to this paper entitled The Design of Low Jitter Hard Limiters by Oliver Collins. In Bruce Griffiths' precision time in frequency webpage, this paper is described as seminal. (http://www.ko4bb.com/~bruce/ZeroCrossingDetectors.html) Since I'm trying to create a limiter that will accept frequencies ranging from 1 MHz to 100 MHz, I thought it would be good to understand the conclusions of this paper (if not the mathematics as well). The mathematics turned out to be quite challenging to decode. Has someone on this forum unraveled the equations? It appears Collins has recommendations on the bandwidth and gain of a jitter minimizing limiter, and then extends this analysis to provide the bandwidth and gain of a cascade of limiters. But the application is still fuzzy. In figure 5, he shows a graph showing the dependence of jitter on crossing time. Is the crossing time (implied by equations 7) considered a design parameter one can vary? Also, on figure 4, the k parameter has been varied to show the rising waveform as a function of k. The threshold is always assumed to be 0.5. So could k be related to tau, the time constant of the RC filter? Thanks in advance for all your help. Yours Raj I would love to take a look at this but the links to the paper at the IEEE are dead. My Google search just turned up others looking for the same paper. Just search for the title on IEEE - http://ieeexplore.ieee.org/search/searchresult.jsp?newsearch=truequeryText=The+Design+of+Low+Jitter+Hard+Limitersx=29y=18 Of course then you need to figure out how to pay IEEE for the privilege of reading the 672 kb paper. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Understanding Oliver Collins Paper Design of Low Jitter Hard Limiters
Hi Everyone, I uploaded the paper to my music website. http://www.rajsodhi.com/images/The%20Design%20of%20Low%20Jitter%20Hard%20Limiters,%20Oliver%20Collins%20May%201996.pdf Yours, Raj -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On Behalf Of Rex Sent: Tuesday, August 21, 2012 1:39 PM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] Understanding Oliver Collins Paper Design of Low Jitter Hard Limiters On 8/21/2012 1:22 PM, David wrote: On Tue, 21 Aug 2012 10:50:43 -0600,raj_so...@agilent.com wrote: Hello everyone, I am new to this forum. It looks like a lively discussion on various topics. A colleague of mine here at Agilent pointed me to this paper entitled The Design of Low Jitter Hard Limiters by Oliver Collins. In Bruce Griffiths' precision time in frequency webpage, this paper is described as seminal. (http://www.ko4bb.com/~bruce/ZeroCrossingDetectors.html) Since I'm trying to create a limiter that will accept frequencies ranging from 1 MHz to 100 MHz, I thought it would be good to understand the conclusions of this paper (if not the mathematics as well). The mathematics turned out to be quite challenging to decode. Has someone on this forum unraveled the equations? It appears Collins has recommendations on the bandwidth and gain of a jitter minimizing limiter, and then extends this analysis to provide the bandwidth and gain of a cascade of limiters. But the application is still fuzzy. In figure 5, he shows a graph showing the dependence of jitter on crossing time. Is the crossing time (implied by equations 7) considered a design parameter one can vary? Also, on figure 4, the k parameter has been varied to show the rising waveform as a function of k. The threshold is always assumed to be 0.5. So could k be related to tau, the time constant of the RC filter? Thanks in advance for all your help. Yours Raj I would love to take a look at this but the links to the paper at the IEEE are dead. My Google search just turned up others looking for the same paper. Just search for the title on IEEE - http://ieeexplore.ieee.org/search/searchresult.jsp?newsearch=truequeryText=The+Design+of+Low+Jitter+Hard+Limitersx=29y=18 Of course then you need to figure out how to pay IEEE for the privilege of reading the 672 kb paper. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Understanding Oliver Collins Paper Design of Low Jitter Hard Limiters
Hi Raj, On 08/21/2012 06:50 PM, raj_so...@agilent.com wrote: Hello everyone, I am new to this forum. It looks like a lively discussion on various topics. A colleague of mine here at Agilent pointed me to this paper entitled The Design of Low Jitter Hard Limiters by Oliver Collins. In Bruce Griffiths' precision time in frequency webpage, this paper is described as seminal. (http://www.ko4bb.com/~bruce/ZeroCrossingDetectors.html) This is indeed a good paper to read. Since I'm trying to create a limiter that will accept frequencies ranging from 1 MHz to 100 MHz, I thought it would be good to understand the conclusions of this paper (if not the mathematics as well). I agree that it could be very good to understand the paper for such a design. The mathematics turned out to be quite challenging to decode. Has someone on this forum unraveled the equations? Both Bruce and me have been looking deeply into this paper (even if it where some time ago, so I re-read it quickly). Bruce deeper than me, but I think I can guide you into it. It appears Collins has recommendations on the bandwidth and gain of a jitter minimizing limiter, and then extends this analysis to provide the bandwidth and gain of a cascade of limiters. But the application is still fuzzy. You obviously have not paid attention to Chapter 1 where the application is very clear and obvious. In particular Dual Mixer Time Difference (DMTD) systems (of which one side is seen in Figure 1) is being discussed, but I think it is equally valid in your application, as it relates to the overall basic issue Given a sine of a particular frequency, which limiter will provide me with minimum trigger jitter? In figure 5, he shows a graph showing the dependence of jitter on crossing time. Is the crossing time (implied by equations 7) considered a design parameter one can vary? Yes, k is the design parameter as the normalized crossing time. Also, on figure 4, the k parameter has been varied to show the rising waveform as a function of k. It essentially shows you how the filter bandwidth (as tau shifts with k) will affect the output signal as a function of the design parameter k. The threshold is always assumed to be 0.5. So could k be related to tau, the time constant of the RC filter? That is formula 10. Actually, you can pick one of many different parameters as the one for the one degree of freedom parameter, and he has chosen the normalized crossing time k. Just about any other normalized parameter could have worked as well. Bruce observed that the same amount of contributed noise was assumed in the Collins paper, so you would like to read his notes of: http://www.ko4bb.com/~bruce/GeneralisedCollinsHardLimiterPaperV3B.pdf Oh, an interesting note is that the Collins paper considers what happens on a single transition, so that's why it is relatively clean from input frequency issues. What will change is the input slew-rate. The Collins paper does not very clearly advice you how to deal with 1:100 input frequency design-range, even if it occurs as an example of variation, just scalled down a million times from your design problem. Another possible critique on the Collins paper is that it only consider white noise, and not flicker noise. For low frequencies, flicker would be noticeable if not dominant, where as for higher frequencies the white noise assumption works pretty well. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Understanding Oliver Collins Paper Design of Low Jitter Hard Limiters
Hi Raj, welcome. Thank you for joining the group and thanks to Magnus for his comment about the Collins' paper. On Tue, Aug 21, 2012 at 11:51 PM, Magnus Danielson mag...@rubidium.dyndns.org wrote: Hi Raj, On 08/21/2012 06:50 PM, raj_so...@agilent.com wrote: Hello everyone, I am new to this forum. It looks like a lively discussion on various topics. A colleague of mine here at Agilent pointed me to this paper entitled The Design of Low Jitter Hard Limiters by Oliver Collins. In Bruce Griffiths' precision time in frequency webpage, this paper is described as seminal. (http://www.ko4bb.com/~bruce/ZeroCrossingDetectors.html) This is indeed a good paper to read. Since I'm trying to create a limiter that will accept frequencies ranging from 1 MHz to 100 MHz, I thought it would be good to understand the conclusions of this paper (if not the mathematics as well). I agree that it could be very good to understand the paper for such a design. The mathematics turned out to be quite challenging to decode. Has someone on this forum unraveled the equations? Both Bruce and me have been looking deeply into this paper (even if it where some time ago, so I re-read it quickly). Bruce deeper than me, but I think I can guide you into it. It appears Collins has recommendations on the bandwidth and gain of a jitter minimizing limiter, and then extends this analysis to provide the bandwidth and gain of a cascade of limiters. But the application is still fuzzy. You obviously have not paid attention to Chapter 1 where the application is very clear and obvious. In particular Dual Mixer Time Difference (DMTD) systems (of which one side is seen in Figure 1) is being discussed, but I think it is equally valid in your application, as it relates to the overall basic issue Given a sine of a particular frequency, which limiter will provide me with minimum trigger jitter? In figure 5, he shows a graph showing the dependence of jitter on crossing time. Is the crossing time (implied by equations 7) considered a design parameter one can vary? Yes, k is the design parameter as the normalized crossing time. Also, on figure 4, the k parameter has been varied to show the rising waveform as a function of k. It essentially shows you how the filter bandwidth (as tau shifts with k) will affect the output signal as a function of the design parameter k. The threshold is always assumed to be 0.5. So could k be related to tau, the time constant of the RC filter? That is formula 10. Actually, you can pick one of many different parameters as the one for the one degree of freedom parameter, and he has chosen the normalized crossing time k. Just about any other normalized parameter could have worked as well. Bruce observed that the same amount of contributed noise was assumed in the Collins paper, so you would like to read his notes of: http://www.ko4bb.com/~bruce/GeneralisedCollinsHardLimiterPaperV3B.pdf Oh, an interesting note is that the Collins paper considers what happens on a single transition, so that's why it is relatively clean from input frequency issues. What will change is the input slew-rate. The Collins paper does not very clearly advice you how to deal with 1:100 input frequency design-range, even if it occurs as an example of variation, just scalled down a million times from your design problem. Another possible critique on the Collins paper is that it only consider white noise, and not flicker noise. For low frequencies, flicker would be noticeable if not dominant, where as for higher frequencies the white noise assumption works pretty well. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Understanding Oliver Collins Paper Design of Low Jitter Hard Limiters
Hi Since the Collins approach tunes the system for a single frequency input (more or less), the approach is probably not the best for a many decades sort of frequency range. There are a number of things that he alludes to in the paper, but does not directly address. The most obvious is the temperature dependance of the stuff the system is made of. Another is the simple fact that a non-clipping linear amplifier is likely the best choice for a first stage, provide the input is not already near clipping. Bob On Aug 21, 2012, at 12:50 PM, raj_so...@agilent.com wrote: Hello everyone, I am new to this forum. It looks like a lively discussion on various topics. A colleague of mine here at Agilent pointed me to this paper entitled The Design of Low Jitter Hard Limiters by Oliver Collins. In Bruce Griffiths' precision time in frequency webpage, this paper is described as seminal. (http://www.ko4bb.com/~bruce/ZeroCrossingDetectors.html) Since I'm trying to create a limiter that will accept frequencies ranging from 1 MHz to 100 MHz, I thought it would be good to understand the conclusions of this paper (if not the mathematics as well). The mathematics turned out to be quite challenging to decode. Has someone on this forum unraveled the equations? It appears Collins has recommendations on the bandwidth and gain of a jitter minimizing limiter, and then extends this analysis to provide the bandwidth and gain of a cascade of limiters. But the application is still fuzzy. In figure 5, he shows a graph showing the dependence of jitter on crossing time. Is the crossing time (implied by equations 7) considered a design parameter one can vary? Also, on figure 4, the k parameter has been varied to show the rising waveform as a function of k. The threshold is always assumed to be 0.5. So could k be related to tau, the time constant of the RC filter? Thanks in advance for all your help. Yours Raj ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
