Re: [time-nuts] DPLL for 10MHz

2012-05-07 Thread Poul-Henning Kamp
In message 063ae10c-af96-4f39-9caf-9e5ecc96b...@gmail.com, Bill Dailey writes
:
Does anyone have any knowledge of a simple (just soldering a few
connections and maybe programming a hz/volt rate) PCB for synchronizing
a precision OCXO to a GPSDO?  I am trying to improve short term
stability with a high stability OCXO and dont want to cut into
my fury and replace the OCXO.

The Vectron TRU-50 is pretty good for that.


-- 
Poul-Henning Kamp   | UNIX since Zilog Zeus 3.20
p...@freebsd.org | TCP/IP since RFC 956
FreeBSD committer   | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.

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Re: [time-nuts] DPLL for 10MHz

2012-05-07 Thread EWKehren
Doc contact me off list
Bert Kehren
 
 
In a message dated 5/7/2012 11:40:04 A.M. Eastern Daylight Time,  
docdai...@gmail.com writes:

Does  anyone have any knowledge of a simple (just soldering a few 
connections and  maybe programming a hz/volt rate) PCB for synchronizing a 
precision 
OCXO to a  GPSDO?  I am trying to improve short term stability with a high 
stability  OCXO and dont want to cut into my fury and replace the OCXO.  I 
cando  it manually but this seems like it would be nice and desirable for 
many yet I  can't find anything.  I presume it would have to be digital 
because of  the long time constant.

Doc
KX0O

Sent from my  iPhone
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Re: [time-nuts] DPLL for 10MHz

2012-05-07 Thread Eric Garner
This is something I would also like to know. I'm sure many others
would be interested as well. Bert would it be possible for you to
share your thoughts on the matter with the group at large?

-Eric

On Mon, May 7, 2012 at 8:43 AM,  ewkeh...@aol.com wrote:
 Doc contact me off list
 Bert Kehren


 In a message dated 5/7/2012 11:40:04 A.M. Eastern Daylight Time,
 docdai...@gmail.com writes:

 Does  anyone have any knowledge of a simple (just soldering a few
 connections and  maybe programming a hz/volt rate) PCB for synchronizing a 
 precision
 OCXO to a  GPSDO?  I am trying to improve short term stability with a high
 stability  OCXO and dont want to cut into my fury and replace the OCXO.  I
 cando  it manually but this seems like it would be nice and desirable for
 many yet I  can't find anything.  I presume it would have to be digital
 because of  the long time constant.

 Doc
 KX0O

 Sent from my  iPhone
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Re: [time-nuts] DPLL for 10MHz

2012-05-07 Thread David
On Mon, 07 May 2012 15:34:21 +, Poul-Henning Kamp
p...@phk.freebsd.dk wrote:

In message 063ae10c-af96-4f39-9caf-9e5ecc96b...@gmail.com, Bill Dailey writes
:
Does anyone have any knowledge of a simple (just soldering a few
connections and maybe programming a hz/volt rate) PCB for synchronizing
a precision OCXO to a GPSDO?  I am trying to improve short term
stability with a high stability OCXO and dont want to cut into
my fury and replace the OCXO.

The Vectron TRU-50 is pretty good for that.

That is an interesting part but what is the price and availability? It
looks suspiciously like if you have to ask, then you can not afford
it.

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Re: [time-nuts] DPLL for 10MHz

2012-05-07 Thread EWKehren
Tried, no interest, some one has offered to in the future do a gate array  
version, you may want to wait for that I am in the mean time using am analog 
 loop for less than 100 seconds between Rb and OCXO and a very modified 
Shera for  GPS/Rb. Works for me.
Contact me off list and we can talk.
Bert
 
 
 
In a message dated 5/7/2012 12:05:54 P.M. Eastern Daylight Time,  
garn...@gmail.com writes:

This is  something I would also like to know. I'm sure many others
would be  interested as well. Bert would it be possible for you to
share your  thoughts on the matter with the group at large?

-Eric

On Mon,  May 7, 2012 at 8:43 AM,  ewkeh...@aol.com wrote:
 Doc  contact me off list
 Bert Kehren


 In a message  dated 5/7/2012 11:40:04 A.M. Eastern Daylight Time,
  docdai...@gmail.com writes:

 Does  anyone have any  knowledge of a simple (just soldering a few
 connections and  maybe programming a hz/volt rate) PCB for synchronizing 
a  precision
 OCXO to a  GPSDO?  I am trying to improve short  term stability with a 
high
 stability  OCXO and dont want to cut  into my fury and replace the 
OCXO.  I
 cando  it manually  but this seems like it would be nice and desirable for
 many yet I  can't find anything.  I presume it would have to be digital
  because of  the long time constant.

 Doc
  KX0O

 Sent from my  iPhone
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_
Eric  Garner

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Re: [time-nuts] DPLL for 10MHz

2012-05-07 Thread Azelio Boriani
Using the PPS as a sync source?

On Mon, May 7, 2012 at 6:24 PM, ewkeh...@aol.com wrote:

 Tried, no interest, some one has offered to in the future do a gate array
 version, you may want to wait for that I am in the mean time using am
 analog
  loop for less than 100 seconds between Rb and OCXO and a very modified
 Shera for  GPS/Rb. Works for me.
 Contact me off list and we can talk.
 Bert



 In a message dated 5/7/2012 12:05:54 P.M. Eastern Daylight Time,
 garn...@gmail.com writes:

 This is  something I would also like to know. I'm sure many others
 would be  interested as well. Bert would it be possible for you to
 share your  thoughts on the matter with the group at large?

 -Eric

 On Mon,  May 7, 2012 at 8:43 AM,  ewkeh...@aol.com wrote:
  Doc  contact me off list
  Bert Kehren
 
 
  In a message  dated 5/7/2012 11:40:04 A.M. Eastern Daylight Time,
   docdai...@gmail.com writes:
 
  Does  anyone have any  knowledge of a simple (just soldering a few
  connections and  maybe programming a hz/volt rate) PCB for synchronizing
 a  precision
  OCXO to a  GPSDO?  I am trying to improve short  term stability with a
 high
  stability  OCXO and dont want to cut  into my fury and replace the
 OCXO.  I
  cando  it manually  but this seems like it would be nice and desirable
 for
  many yet I  can't find anything.  I presume it would have to be digital
   because of  the long time constant.
 
  Doc
   KX0O
 
  Sent from my  iPhone
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 --Eric
 _
 Eric  Garner

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Re: [time-nuts] DPLL for 10MHz

2012-05-07 Thread Azelio Boriani
The Vectron TRU-050 is a PLL with an integrated VCXO. You can sync a 10MHz
OCXO but not from a GPS receiver with the PPS only.

On Mon, May 7, 2012 at 6:29 PM, Azelio Boriani azelio.bori...@screen.itwrote:

 Using the PPS as a sync source?


 On Mon, May 7, 2012 at 6:24 PM, ewkeh...@aol.com wrote:

 Tried, no interest, some one has offered to in the future do a gate array
 version, you may want to wait for that I am in the mean time using am
 analog
  loop for less than 100 seconds between Rb and OCXO and a very modified
 Shera for  GPS/Rb. Works for me.
 Contact me off list and we can talk.
 Bert



 In a message dated 5/7/2012 12:05:54 P.M. Eastern Daylight Time,
 garn...@gmail.com writes:

 This is  something I would also like to know. I'm sure many others
 would be  interested as well. Bert would it be possible for you to
 share your  thoughts on the matter with the group at large?

 -Eric

 On Mon,  May 7, 2012 at 8:43 AM,  ewkeh...@aol.com wrote:
  Doc  contact me off list
  Bert Kehren
 
 
  In a message  dated 5/7/2012 11:40:04 A.M. Eastern Daylight Time,
   docdai...@gmail.com writes:
 
  Does  anyone have any  knowledge of a simple (just soldering a few
  connections and  maybe programming a hz/volt rate) PCB for synchronizing
 a  precision
  OCXO to a  GPSDO?  I am trying to improve short  term stability with a
 high
  stability  OCXO and dont want to cut  into my fury and replace the
 OCXO.  I
  cando  it manually  but this seems like it would be nice and desirable
 for
  many yet I  can't find anything.  I presume it would have to be digital
   because of  the long time constant.
 
  Doc
   KX0O
 
  Sent from my  iPhone
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 _
 Eric  Garner

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Re: [time-nuts] DPLL for 10MHz

2012-05-07 Thread Attila Kinali
On Mon, 7 May 2012 10:30:56 -0500
Bill Dailey docdai...@gmail.com wrote:

 Does anyone have any knowledge of a simple (just soldering a
 few connections and maybe programming a hz/volt rate) PCB for
 synchronizing a precision OCXO to a GPSDO?  I am trying to improve
 short term stability with a high stability OCXO and dont want to
 cut into my fury and replace the OCXO.  I cando it manually but
 this seems like it would be nice and desirable for many yet I can't
 find anything.  I presume it would have to be digital because of the
 long time constant.

What speaks against a simple design as used in the GPSDO by James Miller[1]?
Or if you want a better PLL than just an XOR gate, use a 74x4046.
They are still available in DIL, so building a complete PLL is possible
on a veroboard. This should be enough if you want to improve the short
term stability below 0.1s, where the fury rises above it's long term humb.

If you want to flatten down the humb the fury has (the one between a tau
of 1s and x*1000s), then you need a very stable OXCO to begin with.
Also, then i think the best approach would be to scale down both
signals to 1kHz and use a PICTIC II to measure the phase difference
between them. Then you can implement the control loop in the PIC of
the PICTIC II and drive an _external_ DAC with it.

Attila Kinali


[1] http://www.jrmiller.demon.co.uk/projects/ministd/manual.pdf
-- 
Why does it take years to find the answers to
the questions one should have asked long ago?

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Re: [time-nuts] DPLL for 10MHz

2012-05-07 Thread Chris Albertson
On Mon, May 7, 2012 at 9:54 AM, Attila Kinali att...@kinali.ch wrote:

 What speaks against a simple design as used in the GPSDO by James Miller[1]?
 Or if you want a better PLL than just an XOR gate, use a 74x4046.
 They are still available in DIL, so building a complete PLL is possible
 on a veroboard. This should be enough if you want to improve the short
 term stability below 0.1s, where the fury rises above it's long term humb.

That is my solution.  The 74x4046 come in a version that will do
10MHz.   I use it to let a 10MHz reference that has poor short term
noise drive an OCXO.It's all analog and not many parts.

Chris Albertson
Redondo Beach, California

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Re: [time-nuts] DPLL for 10MHz

2012-05-07 Thread EWKehren
I am patiently waiting for the code to drive the DAC.
Bert Kehren
 
 
In a message dated 5/7/2012 12:54:54 P.M. Eastern Daylight Time,  
att...@kinali.ch writes:

On Mon,  7 May 2012 10:30:56 -0500
Bill Dailey docdai...@gmail.com  wrote:

 Does anyone have any knowledge of a simple (just soldering  a
 few connections and maybe programming a hz/volt rate) PCB  for
 synchronizing a precision OCXO to a GPSDO?  I am trying to  improve
 short term stability with a high stability OCXO and dont want  to
 cut into my fury and replace the OCXO.  I cando it manually  but
 this seems like it would be nice and desirable for many yet I  can't
 find anything.  I presume it would have to be digital  because of the
 long time constant.

What speaks against a simple  design as used in the GPSDO by James 
Miller[1]?
Or if you want a better PLL  than just an XOR gate, use a 74x4046.
They are still available in DIL, so  building a complete PLL is possible
on a veroboard. This should be enough  if you want to improve the short
term stability below 0.1s, where the fury  rises above it's long term humb.

If you want to flatten down the humb  the fury has (the one between a tau
of 1s and x*1000s), then you need a  very stable OXCO to begin with.
Also, then i think the best approach would  be to scale down both
signals to 1kHz and use a PICTIC II to measure the  phase difference
between them. Then you can implement the control loop in  the PIC of
the PICTIC II and drive an _external_ DAC with it.

Attila Kinali


[1]  http://www.jrmiller.demon.co.uk/projects/ministd/manual.pdf
-- 
Why does  it take years to find the answers to
the questions one should have asked  long ago?

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Re: [time-nuts] DPLL for 10MHz

2012-05-07 Thread Attila Kinali
On Mon, 7 May 2012 12:17:02 -0500
Bill Dailey docdai...@gmail.com wrote:

 Regarding the vectron tru-050 looks nice but requires me to come up with
 a board and resistors and capacitors etc which is above my ability.  

Uhmm... how far does your abilities go?

 
 I looked at the miller thing but what I want to do is only correct the
 oscillator like every 500-1000 seconds.  I want to do more than smooth out
 the hump. I am playing with short term stability of mid 10-13 sub 1s to
 10-12 at between 500 and 1000s.  Yes, it is a good oscillator but not BVA
 good.

Read the recent Don't GPS' your Rb threat, it explains why you want
to update/correct your oscillator more often than every 500 seconds.

Also, if you want to go down to that level, a lot more is important
than just the right GPS receiver and the right PLL. You want to think
how you want to supply power to your system with very little noise on it.
How you want to connect the components without picking up too much noise,
neither E nor H field. etc pp.

It is easiest, if you do a PCB, then you can control a lot of the stuff
without too much effort. Building it on a veroboard is not recomended.
Instead use a solid ground plane (ie copper plate) to mount your stuff on,
if you want to do it prototype style.


Atila Kinali
-- 
Why does it take years to find the answers to
the questions one should have asked long ago?

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Re: [time-nuts] DPLL for 10MHz

2012-05-07 Thread Azelio Boriani
OK, so 1 PPS GPS to Rb - need a TIC; 10MHz Rb to OCXO - need a PLL. Are
you interested in an all digital 10nS single shot TIC that gives you a 2's
complement number (negative at the left of the GPS PPS and positive at the
right)? Here it is. This is my TIC, I use it on all my GPSDOs.


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY PPSPSI IS
PORT (PPSTIEOut: OUT std_logic_vector (23 downto 0);
PPSInA, PPSInB, Clock100, Clock20: IN std_logic);
END ENTITY PPSPSI;

ARCHITECTURE RippleCounter OF PPSPSI IS
SIGNAL PPSPhaseCntAB, PPSPhaseCntBA: std_logic_vector (22 downto 0);
SIGNAL PPSPhaseLtc: std_logic_vector (23 downto 0);
SIGNAL PPSADlyed, PPSBDlyed: std_logic_vector (4 downto 0);
SIGNAL PPSGateAB, PPSGateBA, PPSLtcA, PPSRstA, PPSLtcB, PPSRstB, StopCntAB,
StopCntBA: std_logic;
SIGNAL RstGateAB, RstGateBA, OvrLtcAB, OvrLtcBA, PPSLtcA1, PPSLtcB1,
PPSA2BSign: std_logic;

BEGIN
PPSAtoBSign: PROCESS --Sign will be 1 when A leads B (that is the TIE is
negative)
BEGIN
WAIT UNTIL PPSInB'EVENT AND PPSInB='1';
PPSA2BSign= PPSInA;
END PROCESS PPSAtoBSign;
PPSAtoBGate: PROCESS (PPSInA, RstGateAB)
BEGIN
IF RstGateAB='1' THEN
PPSGateAB= '0';
ELSIF PPSInA'EVENT AND PPSInA='1' THEN
PPSGateAB= '1';
END IF;
END PROCESS PPSAtoBGate;
PPSBtoAGate: PROCESS (PPSInB, RstGateBA)
BEGIN
IF RstGateBA='1' THEN
PPSGateBA= '0';
ELSIF PPSInB'EVENT AND PPSInB='1' THEN
PPSGateBA= '1';
END IF;
END PROCESS PPSBtoAGate;
PPSADelay: PROCESS
BEGIN
WAIT UNTIL Clock20'EVENT AND Clock20='1';
PPSADlyed= PPSADlyed (3 downto 0)PPSInA;
END PROCESS PPSADelay;
PPSBDelay: PROCESS
BEGIN
WAIT UNTIL Clock20'EVENT AND Clock20='1';
PPSBDlyed= PPSBDlyed (3 downto 0)PPSInB;
END PROCESS PPSBDelay;
PPSPhaseErrAB0: PROCESS (Clock100, PPSRstB) --Phase error counter bit 0
clocked by the gated 100MHz
BEGIN
IF PPSRstB='1' THEN
PPSPhaseCntAB (0)= '1';
ELSIF Clock100'EVENT AND Clock100='1' THEN
IF PPSGateAB='1' AND StopCntAB='0' THEN
PPSPhaseCntAB (0)= NOT PPSPhaseCntAB (0);
END IF;
END IF;
END PROCESS PPSPhaseErrAB0;
PPSPhaseErrAB: FOR I IN 1 TO 22 GENERATE
PPSPhaseErrABi: PROCESS (PPSPhaseCntAB (I-1), PPSRstB) --Phase error
counter bit 1
BEGIN
IF PPSRstB='1' THEN
PPSPhaseCntAB (I)= '1';
ELSIF PPSPhaseCntAB (I-1)'EVENT AND PPSPhaseCntAB (I-1)='1' THEN
PPSPhaseCntAB (I)= NOT PPSPhaseCntAB (I);
END IF;
END PROCESS PPSPhaseErrABi;
END GENERATE PPSPhaseErrAB;
PPSPhaseErrBA0: PROCESS (Clock100, PPSRstA) --Phase error counter bit 0
clocked by the gated 100MHz
BEGIN
IF PPSRstA='1' THEN
PPSPhaseCntBA (0)= '0';
ELSIF Clock100'EVENT AND Clock100='1' THEN
IF PPSGateBA='1' AND StopCntBA='0' THEN
PPSPhaseCntBA (0)= NOT PPSPhaseCntBA (0);
END IF;
END IF;
END PROCESS PPSPhaseErrBA0;
PPSPhaseErrBA: FOR I IN 1 TO 22 GENERATE
PPSPhaseErrBAi: PROCESS (PPSPhaseCntBA (I-1), PPSRstA) --Phase error down
counter
BEGIN
IF PPSRstA='1' THEN
PPSPhaseCntBA (I)= '0';
ELSIF PPSPhaseCntBA (I-1)'EVENT AND PPSPhaseCntBA (I-1)='0' THEN
PPSPhaseCntBA (I)= NOT PPSPhaseCntBA (I);
END IF;
END PROCESS PPSPhaseErrBAi;
END GENERATE PPSPhaseErrBA;
StopCntAB= '1' WHEN PPSPhaseCntAB (22 downto 1)=00
ELSE '0';
StopCntBA= '1' WHEN PPSPhaseCntBA (22 downto 1)=11
ELSE '0';
PPSPhaseLtc= '0'PPSPhaseCntBA WHEN PPSLtcA='1' AND PPSA2BSign='0' AND
StopCntBA='0' ELSE
'1'PPSPhaseCntAB WHEN PPSLtcB='1' AND PPSA2BSign='1' AND StopCntAB='0' ELSE
PPSPhaseLtc;
OvrLtcAB= StopCntAB WHEN PPSLtcB1='1' ELSE OvrLtcAB;
OvrLtcBA= StopCntBA WHEN PPSLtcA1='1' ELSE OvrLtcBA;
RstGateAB= '1' WHEN PPSInB='1' AND PPSBDlyed (1)='0' ELSE '0';
RstGateBA= '1' WHEN PPSInA='1' AND PPSADlyed (1)='0' ELSE '0';
PPSLtcA= '1' WHEN PPSADlyed=00011 ELSE '0';
PPSLtcA1= '1' WHEN PPSADlyed=1 ELSE '0'; --To be used by the
terminal count value
PPSRstA= '1' WHEN PPSADlyed=0 ELSE '0';
PPSLtcB= '1' WHEN PPSBDlyed=00011 ELSE '0';
PPSLtcB1= '1' WHEN PPSBDlyed=1 ELSE '0'; --To be used by the
terminal count value
PPSRstB= '1' WHEN PPSBDlyed=0 ELSE '0';
PPSTIEOut= 0111 WHEN OvrLtcAB='1' AND OvrLtcBA='1'
AND PPSPhaseLtc (23)='0' ELSE
1000 WHEN OvrLtcAB='1' AND OvrLtcBA='1' AND
PPSPhaseLtc (23)='1' ELSE
PPSPhaseLtc;
END ARCHITECTURE RippleCounter;



On Mon, May 7, 2012 at 7:58 PM, ewkeh...@aol.com wrote:

 10 MHz between Rb and OCXO 1 pps between GPS and Rb.  Always a Rb with
  GPS.
 Bert Kehren


 In a message dated 5/7/2012 1:30:57 P.M. Eastern Daylight Time,  azelio.
 bori...@screen.it writes:

 Using  the PPS as a sync source?

 On Mon, May 7, 2012 at 6:24 PM,  ewkeh...@aol.com wrote:

  Tried, no interest, some one has  offered to in the future do a gate
 array
  version, you may want to wait  for that I am in the mean time using am
  analog
   loop for  less than 100 seconds between Rb and OCXO and a very modified
  Shera  for  GPS/Rb. Works for me.
  Contact me off list and we can  talk.
  Bert
 
 
 
  In a message dated 5/7/2012  12:05:54 P.M. Eastern Daylight Time,
  garn...@gmail.com  writes:
 
  This is  something I would also like 

Re: [time-nuts] DPLL for 10MHz

2012-05-07 Thread Bill Dailey
Regarding my abilities.. regarding electronics... poor soldering is about
my limit... through hole only.   That is why I was hoping there was some
off the shelf method that I could wire up with 10 MHz in from the gspdo and
from the oscillator then wire up the EFC volatge and set the required
parameters and it would adjust my oscillator to the same frequency as the
GPSDO.  Sounds simple enough to me.  but apparently not.  I guess I need to
figure out how to do this electronics stuff...incidentally avoidance of 1)
foreign languages, 2) drafting and 3) electronics is why I chose to become
a chemical engineer.. hi hi.  I once accidentally signed up for a physics
lab that involved electronics... made it through the first lab period.. was
like a fish out of water... walked immediately to administration and
dropped it.  Oscilla-what I said as I skipped out of there.  It was all
electrical engineers.


-- 
Doc

Bill Dailey
KXØO
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Re: [time-nuts] DPLL for 10MHz

2012-05-07 Thread Azelio Boriani
I'm running (although running isn't quite correct for VHDL) this on a
50Kgates Xilinx XC3S50 FPGA. Of course this can be compiled on whatever
brand of logic you prefer, I've not used any proprietary/strange (other
than local clocks, which are usually discouraged) property. Of course this
is only a piece of the whole thing but it is the starting point. I combine
4 of these to get a 2.5nS single shot resolution, driven by 4 phases of the
100MHz clock derived from the XC3S50 clock manager. The 144pin XC3S50 can
be soldered by hand, not so easy but can be done. Better get an FPGA
evaluation board.

On Mon, May 7, 2012 at 11:27 PM, Thomas S. Knutsen la3...@gmail.com wrote:

 Hello.
 Thanks for publishing the VHDL code.
 What kind of device do you suggest for incorporating this? perhaps one
 that can be soldered by humans (no BGA).
 My only experience with FPGA is the Altera DE2 board we use at school.

 73 de Thomas LA3PNA.

 2012/5/7 Azelio Boriani azelio.bori...@screen.it

 OK, so 1 PPS GPS to Rb - need a TIC; 10MHz Rb to OCXO - need a PLL. Are
 you interested in an all digital 10nS single shot TIC that gives you a 2's
 complement number (negative at the left of the GPS PPS and positive at the
 right)? Here it is. This is my TIC, I use it on all my GPSDOs.


 LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.STD_LOGIC_UNSIGNED.ALL;

 ENTITY PPSPSI IS
 PORT (PPSTIEOut: OUT std_logic_vector (23 downto 0);
 PPSInA, PPSInB, Clock100, Clock20: IN std_logic);
 END ENTITY PPSPSI;

 ARCHITECTURE RippleCounter OF PPSPSI IS
 SIGNAL PPSPhaseCntAB, PPSPhaseCntBA: std_logic_vector (22 downto 0);
 SIGNAL PPSPhaseLtc: std_logic_vector (23 downto 0);
 SIGNAL PPSADlyed, PPSBDlyed: std_logic_vector (4 downto 0);
 SIGNAL PPSGateAB, PPSGateBA, PPSLtcA, PPSRstA, PPSLtcB, PPSRstB,
 StopCntAB,
 StopCntBA: std_logic;
 SIGNAL RstGateAB, RstGateBA, OvrLtcAB, OvrLtcBA, PPSLtcA1, PPSLtcB1,
 PPSA2BSign: std_logic;

 BEGIN
 PPSAtoBSign: PROCESS --Sign will be 1 when A leads B (that is the TIE is
 negative)
 BEGIN
 WAIT UNTIL PPSInB'EVENT AND PPSInB='1';
 PPSA2BSign= PPSInA;
 END PROCESS PPSAtoBSign;
 PPSAtoBGate: PROCESS (PPSInA, RstGateAB)
 BEGIN
 IF RstGateAB='1' THEN
 PPSGateAB= '0';
 ELSIF PPSInA'EVENT AND PPSInA='1' THEN
 PPSGateAB= '1';
 END IF;
 END PROCESS PPSAtoBGate;
 PPSBtoAGate: PROCESS (PPSInB, RstGateBA)
 BEGIN
 IF RstGateBA='1' THEN
 PPSGateBA= '0';
 ELSIF PPSInB'EVENT AND PPSInB='1' THEN
 PPSGateBA= '1';
 END IF;
 END PROCESS PPSBtoAGate;
 PPSADelay: PROCESS
 BEGIN
 WAIT UNTIL Clock20'EVENT AND Clock20='1';
 PPSADlyed= PPSADlyed (3 downto 0)PPSInA;
 END PROCESS PPSADelay;
 PPSBDelay: PROCESS
 BEGIN
 WAIT UNTIL Clock20'EVENT AND Clock20='1';
 PPSBDlyed= PPSBDlyed (3 downto 0)PPSInB;
 END PROCESS PPSBDelay;
 PPSPhaseErrAB0: PROCESS (Clock100, PPSRstB) --Phase error counter bit 0
 clocked by the gated 100MHz
 BEGIN
 IF PPSRstB='1' THEN
 PPSPhaseCntAB (0)= '1';
 ELSIF Clock100'EVENT AND Clock100='1' THEN
 IF PPSGateAB='1' AND StopCntAB='0' THEN
 PPSPhaseCntAB (0)= NOT PPSPhaseCntAB (0);
 END IF;
 END IF;
 END PROCESS PPSPhaseErrAB0;
 PPSPhaseErrAB: FOR I IN 1 TO 22 GENERATE
 PPSPhaseErrABi: PROCESS (PPSPhaseCntAB (I-1), PPSRstB) --Phase error
 counter bit 1
 BEGIN
 IF PPSRstB='1' THEN
 PPSPhaseCntAB (I)= '1';
 ELSIF PPSPhaseCntAB (I-1)'EVENT AND PPSPhaseCntAB (I-1)='1' THEN
 PPSPhaseCntAB (I)= NOT PPSPhaseCntAB (I);
 END IF;
 END PROCESS PPSPhaseErrABi;
 END GENERATE PPSPhaseErrAB;
 PPSPhaseErrBA0: PROCESS (Clock100, PPSRstA) --Phase error counter bit 0
 clocked by the gated 100MHz
 BEGIN
 IF PPSRstA='1' THEN
 PPSPhaseCntBA (0)= '0';
 ELSIF Clock100'EVENT AND Clock100='1' THEN
 IF PPSGateBA='1' AND StopCntBA='0' THEN
 PPSPhaseCntBA (0)= NOT PPSPhaseCntBA (0);
 END IF;
 END IF;
 END PROCESS PPSPhaseErrBA0;
 PPSPhaseErrBA: FOR I IN 1 TO 22 GENERATE
 PPSPhaseErrBAi: PROCESS (PPSPhaseCntBA (I-1), PPSRstA) --Phase error down
 counter
 BEGIN
 IF PPSRstA='1' THEN
 PPSPhaseCntBA (I)= '0';
 ELSIF PPSPhaseCntBA (I-1)'EVENT AND PPSPhaseCntBA (I-1)='0' THEN
 PPSPhaseCntBA (I)= NOT PPSPhaseCntBA (I);
 END IF;
 END PROCESS PPSPhaseErrBAi;
 END GENERATE PPSPhaseErrBA;
 StopCntAB= '1' WHEN PPSPhaseCntAB (22 downto 1)=00
 ELSE '0';
 StopCntBA= '1' WHEN PPSPhaseCntBA (22 downto 1)=11
 ELSE '0';
 PPSPhaseLtc= '0'PPSPhaseCntBA WHEN PPSLtcA='1' AND PPSA2BSign='0' AND
 StopCntBA='0' ELSE
 '1'PPSPhaseCntAB WHEN PPSLtcB='1' AND PPSA2BSign='1' AND StopCntAB='0'
 ELSE
 PPSPhaseLtc;
 OvrLtcAB= StopCntAB WHEN PPSLtcB1='1' ELSE OvrLtcAB;
 OvrLtcBA= StopCntBA WHEN PPSLtcA1='1' ELSE OvrLtcBA;
 RstGateAB= '1' WHEN PPSInB='1' AND PPSBDlyed (1)='0' ELSE '0';
 RstGateBA= '1' WHEN PPSInA='1' AND PPSADlyed (1)='0' ELSE '0';
 PPSLtcA= '1' WHEN PPSADlyed=00011 ELSE '0';
 PPSLtcA1= '1' WHEN PPSADlyed=1 ELSE '0'; --To be used by the
 terminal count value
 PPSRstA= '1' WHEN PPSADlyed=0 ELSE '0';
 PPSLtcB= '1' WHEN PPSBDlyed=00011 ELSE '0';
 PPSLtcB1= '1' WHEN PPSBDlyed=1 ELSE '0'; --To be used by the
 terminal 

Re: [time-nuts] DPLL for 10MHz

2012-05-07 Thread Tom Knox

I do not know if this is the type of solution you were looking for but Wenzel 
builds a fantastic LNPLL.

Thomas Knox



 Date: Mon, 7 May 2012 16:11:13 -0500
 From: docdai...@gmail.com
 To: time-nuts@febo.com
 Subject: Re: [time-nuts] DPLL for 10MHz
 
 Regarding my abilities.. regarding electronics... poor soldering is about
 my limit... through hole only.   That is why I was hoping there was some
 off the shelf method that I could wire up with 10 MHz in from the gspdo and
 from the oscillator then wire up the EFC volatge and set the required
 parameters and it would adjust my oscillator to the same frequency as the
 GPSDO.  Sounds simple enough to me.  but apparently not.  I guess I need to
 figure out how to do this electronics stuff...incidentally avoidance of 1)
 foreign languages, 2) drafting and 3) electronics is why I chose to become
 a chemical engineer.. hi hi.  I once accidentally signed up for a physics
 lab that involved electronics... made it through the first lab period.. was
 like a fish out of water... walked immediately to administration and
 dropped it.  Oscilla-what I said as I skipped out of there.  It was all
 electrical engineers.
 
 
 -- 
 Doc
 
 Bill Dailey
 KXØO
 ___
 time-nuts mailing list -- time-nuts@febo.com
 To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
 and follow the instructions there.
  
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