Re: [time-nuts] Frequency division by 81

[Bob kb8tq]

Hi

A lot depends on the output frequency of your OCXO. If it puts out 900 MHz, 
that’s a bit different than if it puts out 9 MHz. For “normal” OCXO’s in the sub
30 MHz region, CMOS logic will do the division just fine. If a PICDIV is a 
candidate,
I’m guessing the OCXO is in this range. 

You will be in the vicinity of 100 KHz with the output dividing from a 5 or 10 
MHz
OCXO. That means the noise floor of the logic is the main issue. The modern LVC
(and similar) logic families seem to have pretty good noise floors.

All this is just a guess without much to base it on …..

Bob

> On Jun 18, 2020, at 7:58 AM, Gilles Clement  wrote:
> 
> Hi 
> I need to divide the output of an OCXO by a factor D=81 for testing purposes. 
> So with minimum added phase noise.
> PICDIV-like approches would not work (D needs to be divisible by 8 or at 
> least be even) 
> I went through the archives and it seems that an Injection Locked Frequency 
> Divider with resynchronization flip-flop could be a simple and acceptable 
> solution. 
> As described in the following Wenzel paper: Unusual Frequency 
> Dividerswww.wenzel.com › uploads › dividers 
> 
> Does this make sense? 
> Gilles. 
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Re: [time-nuts] Frequency division by 81

[Dana Whitlow]

I've read that the so-called regenerative frequency divider has
exceptionally low
phase noise.  You could cascade four of them, each dividing by 3.  It's not
the
simplest thing in the world, but might yield really good phase noise
performance.
Back when I worked at TEK on the 2710 (low-cost SA) project, late 1980's,
one
of the engineers used one of these to divide a signal of around 2 GHz by 2;
these
were the days when IC dividers that would work that fast were either
unobtainium or
unaffordable.

See:
http://www.ke5fx.com/regen/1208.pdf
and note the reference to the IEEE paper.

Dana



On Thu, Jun 18, 2020 at 11:38 AM Mike Ingle  wrote:

> Hi Gilles,  I didn't peruse the linked paper, but I usually use a re-sync
> FF MC100ep51 or 52  with the clock at the pre-divider rate, and the "D"
> coming from in my case an FPGA.  thai eliminates the phase noise
> contributed by the FPGA.  The nice thing with an FPGA, is you can use the
> LVDS outputs into the differential ECL D pretty easily.  And  ECL is
> clean.  --mike
>
> On Thu, Jun 18, 2020 at 5:42 PM Gilles Clement  wrote:
>
> > Hi
> > I need to divide the output of an OCXO by a factor D=81 for testing
> > purposes. So with minimum added phase noise.
> > PICDIV-like approches would not work (D needs to be divisible by 8 or at
> > least be even)
> > I went through the archives and it seems that an Injection Locked
> > Frequency Divider with resynchronization flip-flop could be a simple and
> > acceptable solution.
> > As described in the following Wenzel paper: Unusual Frequency
> > Dividerswww.wenzel.com › uploads › dividers <
> >
> https://www.google.com/url?sa=t=j==s=web==rja=8=2ahUKEwik49qGpIvqAhURahQKHTBVClAQFjABegQIARAB=http%3A%2F%2Fwww.wenzel.com%2Fwp-content%2Fuploads%2Fdividers.pdf=AOvVaw2m-9lURROiSbG9XykiDNDU
> > >
> > Does this make sense?
> > Gilles.
> > ___
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> > http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
> > and follow the instructions there.
> >
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Re: [time-nuts] Frequency division by 81

[ed breya]

For a 10 MHz clock, 74HC would be fine. For small numbers like 81, a 
couple of 74HC163s would do it, and be good to go since they're 
synchronous anyway.


For large numbers, my go-to divider is the 74HC4040 12-bit ripple 
counter. It can be rigged for any fixed integer divide ratio from 3 to 
4095 with a simple diode gating arrangement for feedback to the reset 
input. For divide by 81, three diodes (64+16+1) and a resistor comprise 
the feedback circuit. The bigger and more numerically complicated the 
divide ratio, the more diodes are needed. The straight binary 2^n ones 
are of course trivial. The output edge may be re-synchronized with DFFs, 
as Gerhard mentioned. This is advisable especially for precision time 
and frequency work. Also, if you use a dual FF anyway, one can be used 
for re-synchronizing, and the other can be used in the feedback, to 
improve the reset action. The reset is asynchronous, so there is a risk 
of race around from the outputs to the reset, but the prop delays tend 
to eliminate it, and I've never had a problem with it.


The 74HC4020 may also be used, depending on the divide range needed - 
some of its binary stage outputs aren't available, while the 4040 has 
all of them. The 74HC393 also can work this way, for up to 255. I've 
used these counters many times this way, but can't remember the exact 
hookup, without going back to notes on some of my projects, or figuring 
it out again from the datasheets. It's quite simple, but if anyone 
needs, I can revisit and explain it.


Ed

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Re: [time-nuts] Frequency division by 81

[Hal Murray]

> I need to divide the output of an OCXO by a factor D=81 for testing purposes.
> So with minimum added phase noise. PICDIV-like approches would not work (D
> needs to be divisible by 8 or at least be even)  I went through the archives
> and it seems that an Injection Locked Frequency Divider with resynchronization
>  flip-flop could be a simple and acceptable solution.  

If a resynchronization FF gets you good enough signal quality, then you can do 
the divide in digital logic.

What is the input frequency?


-- 
These are my opinions.  I hate spam.




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Re: [time-nuts] Frequency division by 81

[Gerhard Hoffmann]

Why don't you simply divide by 81 with a normal CMOS divider and 
synchronize its output with a 7474-like flipflop to the original clock? 
The phase noise would be determined only by this last flipflop.


regards, Gerhard


Am 18.06.20 um 13:58 schrieb Gilles Clement:

Hi
I need to divide the output of an OCXO by a factor D=81 for testing purposes. 
So with minimum added phase noise.


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Re: [time-nuts] Frequency division by 81

[Mike Ingle]

Hi Gilles,  I didn't peruse the linked paper, but I usually use a re-sync
FF MC100ep51 or 52  with the clock at the pre-divider rate, and the "D"
coming from in my case an FPGA.  thai eliminates the phase noise
contributed by the FPGA.  The nice thing with an FPGA, is you can use the
LVDS outputs into the differential ECL D pretty easily.  And  ECL is
clean.  --mike

On Thu, Jun 18, 2020 at 5:42 PM Gilles Clement  wrote:

> Hi
> I need to divide the output of an OCXO by a factor D=81 for testing
> purposes. So with minimum added phase noise.
> PICDIV-like approches would not work (D needs to be divisible by 8 or at
> least be even)
> I went through the archives and it seems that an Injection Locked
> Frequency Divider with resynchronization flip-flop could be a simple and
> acceptable solution.
> As described in the following Wenzel paper: Unusual Frequency
> Dividerswww.wenzel.com › uploads › dividers <
> https://www.google.com/url?sa=t=j==s=web==rja=8=2ahUKEwik49qGpIvqAhURahQKHTBVClAQFjABegQIARAB=http%3A%2F%2Fwww.wenzel.com%2Fwp-content%2Fuploads%2Fdividers.pdf=AOvVaw2m-9lURROiSbG9XykiDNDU
> >
> Does this make sense?
> Gilles.
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> http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
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Re: [time-nuts] Frequency division by 81

[Tim Shoppa]

Depending on your needs there are many off-the-shelf programmable
frequency divider IC's.

Most of the modern ones are not programmed by strapping pins but by serial
connection to a microcontroller so this may not be your cup of tea.

If so, look at the math and note that 81 = 9*9 or 3*3*3*3.

Two divide-by-nines in series is very straightforward with something as old
fashioned as a couple 7490's with some AND gates.

And four divide-by-threes in series is done with bare flip flops. You can
even google to find divide-by-three with a square wave output if that's
what you need.

Tim N3QE

On Thu, Jun 18, 2020 at 11:42 AM Gilles Clement  wrote:

> Hi
> I need to divide the output of an OCXO by a factor D=81 for testing
> purposes. So with minimum added phase noise.
> PICDIV-like approches would not work (D needs to be divisible by 8 or at
> least be even)
> I went through the archives and it seems that an Injection Locked
> Frequency Divider with resynchronization flip-flop could be a simple and
> acceptable solution.
> As described in the following Wenzel paper: Unusual Frequency
> Dividerswww.wenzel.com › uploads › dividers <
> https://www.google.com/url?sa=t=j==s=web==rja=8=2ahUKEwik49qGpIvqAhURahQKHTBVClAQFjABegQIARAB=http%3A%2F%2Fwww.wenzel.com%2Fwp-content%2Fuploads%2Fdividers.pdf=AOvVaw2m-9lURROiSbG9XykiDNDU
> >
> Does this make sense?
> Gilles.
> ___
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> http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
> and follow the instructions there.
>
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[time-nuts] Frequency division by 81

[Gilles Clement]

Hi 
I need to divide the output of an OCXO by a factor D=81 for testing purposes. 
So with minimum added phase noise.
PICDIV-like approches would not work (D needs to be divisible by 8 or at least 
be even) 
I went through the archives and it seems that an Injection Locked Frequency 
Divider with resynchronization flip-flop could be a simple and acceptable 
solution. 
As described in the following Wenzel paper: Unusual Frequency 
Dividerswww.wenzel.com › uploads › dividers 

Does this make sense? 
Gilles. 
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