Re: [time-nuts] Frequency division by 81

[Bob kb8tq]

Hi

The biggest issue is that there are so many variables. They never seem
to get nailed down. What you are seeing is the answer to 20 or more 
“niche” requirements.

For instance:

Is the “phase noise” requirement close in or broadband? ECL is in general 
horrible for broadband phase noise. 

Is the source at UHF or below 10 MHz? A CMOS solution isn’t going to make
much sense at 500 MHz. 

Is a square wave ( to drive logic ) part of the system requirement? Since 
in some cases these are corporate sponsored designs (as opposed to
basement projects) even getting into something that simple is “revealing 
too much of our IP”. 

If the destination is an FPGA, they generally have horrible noise performance. 
That’s true both close in and broadband. What’s “good” there is likely pretty
awful in another context. 

What *is* “good phase noise? To one person, it’s -150 dbc/Hz at 100 KHz offset
 on a 10 MHZ source. To the next person it’s 40 db better than that.

As long as none of the details are available, the answers are going to be
very difficult to parse. It’s also why people who do this sort of thing spend 
years learning how to do it. 

Bob



> On Jun 19, 2020, at 7:23 PM, Mark Haun  wrote:
> 
> On Fri, 19 Jun 2020 14:49:01 +
> "Poul-Henning Kamp"  wrote:
>> Gilles Clement writes:
>>> Could you point me to a practical design example of a Pi divider ?  
>> 
>> Look at Fig 2 in Enrico's paper:
>> 
>>> http://rubiola.org/pdf-articles/conference/2013-ifcs-Frequency-dividers.pdf
> 
> I saw this a while ago and found it interesting, but not being a proper
> time nut myself, I am wondering: are the advantages of this divider
> architecture maintained if you need a square wave output?  Wouldn't the
> triangle->square conversion introduce its own noise, possibly swamping
> the gains of the lambda divider?
> 
> As an aside, I have noticed that every time this question comes up,
> there are a variety of answers, ranging from "use a PICDIV" to "use this
> fancy low-noise architecture" to "use ECL / HC / modern fast logic
> gates."  I read through the replies but never seem to leave the
> discussion knowing any more than I did at its start.  It would be great
> if someone could provide the context to understand the relative merits
> of each suggestion---how they are likely to stack up against one
> another and how you would choose one over the others.  I.e. please
> spend more time explaining why you are right and everyone else is wrong
> ;)  Otherwise, it's just chaff.
> 
> Mark
> 
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Re: [time-nuts] Frequency division by 81

[Bob kb8tq]

Hi

What are we trying to do here?

What is the input frequency?

What is the phase noise of the OCXO?

What is the phase noise requirement on the output?

Are there other system based requirements on the output?
(ADEV maybe ….)

=

Symmetry (by it’s self) going from 50/50 to 45/55 (or whatever) has zero impact 
on 
the phase noise of the output. 

If your logic implementation that *uses* the clock depends on 50/50 duty cycle, 
that 
is a very different “specific to your design” constraint. 

Bob

> On Jun 19, 2020, at 3:06 PM, Gilles Clement  wrote:
> 
> Current PICDIV concept generates exactly 50% output duty cycles, so only even 
> dividing factors are possible.
> If we accept a slightly unbalanced duty cycles (ex: one more instruction on 
> the down side loop than for the up side loop), one could generalize to odd 
> factors.
> (An idea suggested by Didier Juges)
> What would be the down sides for a Clock signal ? 
> Gilles. 
> 
>> Le 18 juin 2020 à 13:58, Gilles Clement  a écrit :
>> 
>> Hi 
>> I need to divide the output of an OCXO by a factor D=81 for testing 
>> purposes. So with minimum added phase noise.
>> PICDIV-like approches would not work (D needs to be divisible by 8 or at 
>> least be even) 
>> I went through the archives and it seems that an Injection Locked Frequency 
>> Divider with resynchronization flip-flop could be a simple and acceptable 
>> solution. 
>> As described in the following Wenzel paper: Unusual Frequency 
>> Dividerswww.wenzel.com › uploads › dividers 
>> 
>> Does this make sense? 
>> Gilles. 
> 
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Re: [time-nuts] Frequency division by 81

[Mark Haun]

On Fri, 19 Jun 2020 14:49:01 +
"Poul-Henning Kamp"  wrote:
> Gilles Clement writes:
> > Could you point me to a practical design example of a Pi divider ?  
> 
> Look at Fig 2 in Enrico's paper:
> 
> > http://rubiola.org/pdf-articles/conference/2013-ifcs-Frequency-dividers.pdf

I saw this a while ago and found it interesting, but not being a proper
time nut myself, I am wondering: are the advantages of this divider
architecture maintained if you need a square wave output?  Wouldn't the
triangle->square conversion introduce its own noise, possibly swamping
the gains of the lambda divider?

As an aside, I have noticed that every time this question comes up,
there are a variety of answers, ranging from "use a PICDIV" to "use this
fancy low-noise architecture" to "use ECL / HC / modern fast logic
gates."  I read through the replies but never seem to leave the
discussion knowing any more than I did at its start.  It would be great
if someone could provide the context to understand the relative merits
of each suggestion---how they are likely to stack up against one
another and how you would choose one over the others.  I.e. please
spend more time explaining why you are right and everyone else is wrong
;)  Otherwise, it's just chaff.

Mark

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Re: [time-nuts] Frequency division by 81

[Gerhard Hoffmann]

Am 19.06.20 um 11:42 schrieb Clint Jay:
12F675 is specified for clock input of 20MHz and (without digging too 
deep into the way the code works) I think the PICDiv code works with 
clock input rather than input to a timer or counter peripheral so 
20MHz would be fine. While I'd not recommend it for use I have seen 
them run (experimentally) at 27MHz and I've seen anecdotal reports of 
over 30MHz. 

Burn the attachment into something like this:

< 
https://www.ebay.de/itm/Coolrunner-rev-C-fur-Jasper-Trinity-Corona-Phat-Slim-Kabelpuls-IC-Xbox-36-tp/353110312086?_trkparms=aid%3D1110006%26algo%3DHOMESPLICE.SIM%26ao%3D1%26asc%3D20200520130048%26meid%3D477f5b9f172e4c9b92d885140d5a8df0%26pid%3D15%26rk%3D1%26rkt%3D2%26mehot%3Dco%26sd%3D402298757019%26itm%3D353110312086%26pmt%3D1%26noa%3D0%26pg%3D2047675%26algv%3DSimplAMLv5PairwiseWebWithBBEV2bDemotion%26brand%3DMarkenlos&_trksid=p2047675.c15.m1851 
 >


and you're done.

Add sine/square converter in front if neededand output precision 
flipflop if standard CMOS is not good enough.


I have my own stamp-sized Coolrunner II board, never tested this one. 
One could also program a phase comparator and/or 1pps generation from 
100 MHz into it. BTDT. I might provide the Gerbers for JLCPCB.


regards, Gerhard

-

library IEEE;
use     IEEE.STD_LOGIC_1164.ALL;
use     ieee.numeric_std.all;

entity div81 is
    Port(
        clk:  in   std_logic;   -- CMOS clock to > 200 MHz in
        q:    out  std_logic    -- divided output
    )
end div81;

architecture beehive of div81 is

    signal tctr:  integer range 0 to 80;

    attribute LOC: string;
    attribute IOSTANDARD: string;
    attribute LOC of clk: signal is "P1";  -- in put is pad 1
    attribute IOSTANDARD of clk:  signal is "LVCMOS33";
    attribute LOC of q:   signal is "p31"; -- output is pad 31
    attribute IOSTANDARD of q:    signal is "LVCMOS33";

    -- (function boolean_to_standard_logic no more needed in more 
modern VHDL)

    function bool2sl(b : boolean) return std_logic is
    begin
        if b then
            return '1';
        else
            return '0';
        end if;
    end function bool2sl;

begin

u_div : process(clk) is   -- this block wakes up if something happens on 
clock pin

    begin
        if rising_edge(clk) then

            if (tctr = 80)
            then
                tctr <= 0;  -- reset if maximum count reached
            else
                tctr <= tctr + 1;   -- else just increment
            end if;

            q <= bool2sl(tctr < 40); -- set output high/low time to taste
        end if;   -- rising_edge()
    end process u_div;

end beehive;







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Re: [time-nuts] Frequency division by 81

[Poul-Henning Kamp]

Gilles Clement writes:

> Could you point me to a practical design example of a Pi divider ?

Look at Fig 2 in Enrico's paper:

> http://rubiola.org/pdf-articles/conference/2013-ifcs-Frequency-dividers.pdf

I would implement it so that the shiftregister is also the divider,
by making it twice the length and feed it back to itself.

In your case it would be a 18 stage shiftregister, where the first
9 stages initialize to zero, and the last 9 stages initialize to
one, with the output connected back to the input that will give you
a rotating pattern of 0101...

Only 9 of the stages should be driving resistors to the output.

-- 
Poul-Henning Kamp   | UNIX since Zilog Zeus 3.20
p...@freebsd.org | TCP/IP since RFC 956
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Never attribute to malice what can adequately be explained by incompetence.

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Re: [time-nuts] Frequency division by 81

[Gilles Clement]

Hi, 
Could you point me to a practical design example of a Pi divider ?


Envoyé de mon iPad

> Le 19 juin 2020 à 08:56, Poul-Henning Kamp  a écrit :
> 
> 
> 
>> I need to divide the output of an OCXO by a factor D=81 for testing 
>> purposes. So with minimum added phase noise.
> 
> Two stages of divide by 9 PI-dividers ?
> 
>   http://rubiola.org/pdf-articles/conference/2013-ifcs-Frequency-dividers.pdf
> 
> -- 
> Poul-Henning Kamp   | UNIX since Zilog Zeus 3.20
> p...@freebsd.org | TCP/IP since RFC 956
> FreeBSD committer   | BSD since 4.3-tahoe
> Never attribute to malice what can adequately be explained by incompetence.

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Re: [time-nuts] Frequency division by 81

[Gilles Clement]

Current PICDIV concept generates exactly 50% output duty cycles, so only even 
dividing factors are possible.
If we accept a slightly unbalanced duty cycles (ex: one more instruction on the 
down side loop than for the up side loop), one could generalize to odd factors.
(An idea suggested by Didier Juges)
What would be the down sides for a Clock signal ? 
Gilles. 

> Le 18 juin 2020 à 13:58, Gilles Clement  a écrit :
> 
> Hi 
> I need to divide the output of an OCXO by a factor D=81 for testing purposes. 
> So with minimum added phase noise.
> PICDIV-like approches would not work (D needs to be divisible by 8 or at 
> least be even) 
> I went through the archives and it seems that an Injection Locked Frequency 
> Divider with resynchronization flip-flop could be a simple and acceptable 
> solution. 
> As described in the following Wenzel paper: Unusual Frequency 
> Dividerswww.wenzel.com › uploads › dividers 
> 
> Does this make sense? 
> Gilles. 

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Re: [time-nuts] Frequency division by 81

[Gilles Clement]

Thanks for all your replies. 
Very interesting, A lot to digest.
Best, 
GIlles.



Envoyé de mon iPad

> Le 19 juin 2020 à 01:12, Richard (Rick) Karlquist  a 
> écrit :
> 
> 
> 
>> On 6/18/2020 4:58 AM, Gilles Clement wrote:
>> Hi
>> I need to divide the output of an OCXO by a factor D=81 for testing 
>> purposes. So with minimum added phase noise.
> 
> If you are using any kind of digital divider, let me
> recommend that you first condition the signal to be
> divided by using an ADI LTC6957-1 to convert a sine
> wave into a high slew rate square wave without a lot
> of added noise.  If it is already a square wave, you
> still might want to pass it through a narrow bandpass
> filter to remove phase noise, and then turn it back
> into a square wave.  All of this is almost more
> important than what you use to actually do the
> division itself.
> 
> Rick N6RK

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Re: [time-nuts] Frequency division by 81

[Clint Jay]

12F675 is specified for clock input of 20MHz and (without digging too deep
into the way the code works) I think the PICDiv code works with clock input
rather than input to a timer or counter peripheral so 20MHz would be fine.

While I'd not recommend it for use I have seen them run (experimentally) at
27MHz and I've seen anecdotal reports of over 30MHz.

It would be trivial to port the PICDiv code to a newer 12F chip, some of
which will do 48MHz, but there'd need to be validation of the results with
regard to phase noise etc.

On Fri, 19 Jun 2020 at 09:14, Bryan _  wrote:

> I don't believe a picdiv can be used for frequencies above 20MHz. I
> believe even that is pushing the max frequency input capability of the pic
>
>
> -=Bryan=-
>
> 
> From: time-nuts  on behalf of Bob kb8tq
> 
> Sent: June 18, 2020 10:05 AM
> To: Discussion of precise time and frequency measurement <
> time-nuts@lists.febo.com>
> Subject: Re: [time-nuts] Frequency division by 81
>
> Hi
>
> A lot depends on the output frequency of your OCXO. If it puts out 900 MHz,
> that’s a bit different than if it puts out 9 MHz. For “normal” OCXO’s in
> the sub
> 30 MHz region, CMOS logic will do the division just fine. If a PICDIV is a
> candidate,
> I’m guessing the OCXO is in this range.
>
> You will be in the vicinity of 100 KHz with the output dividing from a 5
> or 10 MHz
> OCXO. That means the noise floor of the logic is the main issue. The
> modern LVC
> (and similar) logic families seem to have pretty good noise floors.
>
> All this is just a guess without much to base it on …..
>
> Bob
>
> > On Jun 18, 2020, at 7:58 AM, Gilles Clement  wrote:
> >
> > Hi
> > I need to divide the output of an OCXO by a factor D=81 for testing
> purposes. So with minimum added phase noise.
> > PICDIV-like approches would not work (D needs to be divisible by 8 or at
> least be even)
> > I went through the archives and it seems that an Injection Locked
> Frequency Divider with resynchronization flip-flop could be a simple and
> acceptable solution.
> > As described in the following Wenzel paper: Unusual Frequency
> Dividerswww.wenzel.com › uploads › dividers <
> https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&cad=rja&uact=8&ved=2ahUKEwik49qGpIvqAhURahQKHTBVClAQFjABegQIARAB&url=http%3A%2F%2Fwww.wenzel.com%2Fwp-content%2Fuploads%2Fdividers.pdf&usg=AOvVaw2m-9lURROiSbG9XykiDNDU
> >
> > Does this make sense?
> > Gilles.
> > ___
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>
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-- 
Clint. M0UAW IO83

*No trees were harmed in the sending of this mail. However, a large number
of electrons were greatly inconvenienced.*
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[time-nuts] inside photo of SA.22c-LN

[Tom Knox]

Hi All;
By chance could anyone send me a close-up photo of the inside of a SA.22c-LN?
Either way thanks.
Good Health;
Tom Knox

303-554-0307

act...@hotmail.com

"Peace is not the absence of violence, but the presence of Justice" Both MLK 
and Albert Einstein
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Re: [time-nuts] Frequency division by 81

[Didier Juges]

You can use one of the Silabs 8051 microcontrollers. They run one clock per
instruction (for the 1 byte instructions like NOP) so dividing by 81 should
not be a problem.
I use them extensively to make programmable dividers. My favorite small
package is a SO-14. They have much smaller devices but they are in "no pin"
packages. They do not have DIP.
If you are interested, I can probably jury rig one for you this weekend, I
have a bunch of them on hand.
The small devices run at up to 25 MHz and run at 3.3V.

Didier KO4BB.

On Thu, Jun 18, 2020, 10:42 AM Gilles Clement  wrote:

> Hi
> I need to divide the output of an OCXO by a factor D=81 for testing
> purposes. So with minimum added phase noise.
> PICDIV-like approches would not work (D needs to be divisible by 8 or at
> least be even)
> I went through the archives and it seems that an Injection Locked
> Frequency Divider with resynchronization flip-flop could be a simple and
> acceptable solution.
> As described in the following Wenzel paper: Unusual Frequency
> Dividerswww.wenzel.com › uploads › dividers <
> https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&cad=rja&uact=8&ved=2ahUKEwik49qGpIvqAhURahQKHTBVClAQFjABegQIARAB&url=http%3A%2F%2Fwww.wenzel.com%2Fwp-content%2Fuploads%2Fdividers.pdf&usg=AOvVaw2m-9lURROiSbG9XykiDNDU
> >
> Does this make sense?
> Gilles.
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Re: [time-nuts] Frequency division by 81

[Richard (Rick) Karlquist]

On 6/18/2020 4:58 AM, Gilles Clement wrote:

Hi
I need to divide the output of an OCXO by a factor D=81 for testing purposes. 
So with minimum added phase noise.


If you are using any kind of digital divider, let me
recommend that you first condition the signal to be
divided by using an ADI LTC6957-1 to convert a sine
wave into a high slew rate square wave without a lot
of added noise.  If it is already a square wave, you
still might want to pass it through a narrow bandpass
filter to remove phase noise, and then turn it back
into a square wave.  All of this is almost more
important than what you use to actually do the
division itself.

Rick N6RK

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Re: [time-nuts] Frequency division by 81

[Poul-Henning Kamp]

> I need to divide the output of an OCXO by a factor D=81 for testing purposes. 
> So with minimum added phase noise.

Two stages of divide by 9 PI-dividers ?


http://rubiola.org/pdf-articles/conference/2013-ifcs-Frequency-dividers.pdf

-- 
Poul-Henning Kamp   | UNIX since Zilog Zeus 3.20
p...@freebsd.org | TCP/IP since RFC 956
FreeBSD committer   | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.

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Re: [time-nuts] Frequency division by 81

[Bryan _]

I don't believe a picdiv can be used for frequencies above 20MHz. I believe 
even that is pushing the max frequency input capability of the pic


-=Bryan=-


From: time-nuts  on behalf of Bob kb8tq 

Sent: June 18, 2020 10:05 AM
To: Discussion of precise time and frequency measurement 

Subject: Re: [time-nuts] Frequency division by 81

Hi

A lot depends on the output frequency of your OCXO. If it puts out 900 MHz,
that’s a bit different than if it puts out 9 MHz. For “normal” OCXO’s in the sub
30 MHz region, CMOS logic will do the division just fine. If a PICDIV is a 
candidate,
I’m guessing the OCXO is in this range.

You will be in the vicinity of 100 KHz with the output dividing from a 5 or 10 
MHz
OCXO. That means the noise floor of the logic is the main issue. The modern LVC
(and similar) logic families seem to have pretty good noise floors.

All this is just a guess without much to base it on …..

Bob

> On Jun 18, 2020, at 7:58 AM, Gilles Clement  wrote:
>
> Hi
> I need to divide the output of an OCXO by a factor D=81 for testing purposes. 
> So with minimum added phase noise.
> PICDIV-like approches would not work (D needs to be divisible by 8 or at 
> least be even)
> I went through the archives and it seems that an Injection Locked Frequency 
> Divider with resynchronization flip-flop could be a simple and acceptable 
> solution.
> As described in the following Wenzel paper: Unusual Frequency 
> Dividerswww.wenzel.com › uploads › dividers 
> 
> Does this make sense?
> Gilles.
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Re: [time-nuts] Frequency division by 81

[Bob kb8tq]

Hi

The gotcha is that the “HC” logic families have pretty high broadband noise 
floors compared to newer parts. 
At 20 log (N), divide by 81 gets you about 38 db of phase noise improvement. If 
you started off at -130 dbc/Hz, 
you come out at -168 dbc / Hz. That (of course) assumes you don’t hit this or 
that floor first. 

Agin, with limited information from the OP, it’s tough to work out just what 
the limits would actually be. ( what is the
starting frequency?, what phase noise offsets mater? …..)

Bob

> On Jun 18, 2020, at 3:36 PM, ed breya  wrote:
> 
> For a 10 MHz clock, 74HC would be fine. For small numbers like 81, a couple 
> of 74HC163s would do it, and be good to go since they're synchronous anyway.
> 
> For large numbers, my go-to divider is the 74HC4040 12-bit ripple counter. It 
> can be rigged for any fixed integer divide ratio from 3 to 4095 with a simple 
> diode gating arrangement for feedback to the reset input. For divide by 81, 
> three diodes (64+16+1) and a resistor comprise the feedback circuit. The 
> bigger and more numerically complicated the divide ratio, the more diodes are 
> needed. The straight binary 2^n ones are of course trivial. The output edge 
> may be re-synchronized with DFFs, as Gerhard mentioned. This is advisable 
> especially for precision time and frequency work. Also, if you use a dual FF 
> anyway, one can be used for re-synchronizing, and the other can be used in 
> the feedback, to improve the reset action. The reset is asynchronous, so 
> there is a risk of race around from the outputs to the reset, but the prop 
> delays tend to eliminate it, and I've never had a problem with it.
> 
> The 74HC4020 may also be used, depending on the divide range needed - some of 
> its binary stage outputs aren't available, while the 4040 has all of them. 
> The 74HC393 also can work this way, for up to 255. I've used these counters 
> many times this way, but can't remember the exact hookup, without going back 
> to notes on some of my projects, or figuring it out again from the 
> datasheets. It's quite simple, but if anyone needs, I can revisit and explain 
> it.
> 
> Ed
> 
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