[time-nuts] Best Leo Bodnar configuration for 10MHz

2021-09-14 Thread Marek Dorsic
Hi Community,

   I received my Leo Bodnar Mini GPS Reference Clock.
The same 10MHz output frequency can be achieved by varios configuration 
settings.
Are some of these combinations better than others?

 .marek
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[time-nuts] PicoDIV, the RPi Pico frequency divider

2021-05-13 Thread Marek Dorsic
Hello Time-Nuts,

   first time a read about the PIOs of the Raspberry Pi Pico 
 and saw the few PIO assembler 
instructions  I immediately 
thought about the PicDIV frequency divider of Tom van Baak.
As you may know, programming PIC is not a piece of cake when not completely 
impossible (e.g. for those with an MacOS or without proper PIC programmer). But 
every kid can plug in a USB cable and drag & drop a file. That is how RPi Pico 
is programmed. 

Hence I reinvented the wheel and created PicoDIV project - basic 10M : 1 
frequency divider implemented within the PIO of the RPi Pico. The code 
configures the system clock to be driven by the impulses on GPIO20 (note that 
only GPIO20 and GPIO22 pins can be used for this purpose) which then clocks the 
PIO assembler instructions counting pulses and controlling output pins.
You can find the code at https://github.com/dorsic/PicoDIV 


Sadly I am not able to measure the jitter of outputting signal and cannot 
compare it with the original PicDIV. I would greatly appreciate if some of you 
will have the time and interest to do so. If any code modifications will be 
required, just write me a note.

For those who do not have the toolchain installed to compile own code I provide 
built sample. Download the picoDIV.uf2 
 file and drag & 
drop it to your Pico.
Connect 10MHz, 0-3.3V square wave signal to GPIO20 (pin 26) and you will see 1 
PPS 10ms pulses on pin GPIO0 (pin 1), the onboard blinking and also 1 MHz and 
100 kHz signals on GPIO21 and GPIO15 respectively.

Just be careful, all RPi Pico GPIOs are 3.3V. The Pico GPIO cannot be used at 
5V.



.md



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[time-nuts] ADEV interpretation

2021-04-04 Thread Marek Dorsic
Hello,

I would like to ask your knowledge to help me interpret this basic ADEV result.
Assume following measurement setup:
PPS output of Ublox RCB-F9T connected to channel 1 of a HP53131A counter.
10MHz output of the counter's internal oscillator (opt. 010, medium stability 
oven) divided with PICDIV to 1 PPS connected to channel 2 of the counter.
Counter set to measure time interval from channel 1 to channel 2.
After processing the readings, the floor of ADEV is 5x10^-10 at about 30-100 
seconds interval.
Which of the following is true?
a) ADEV shows the real performance of the internal oscillator,
b) ADEV floor is 5x10^-10 because of the restricted counter time interval 
resolution (500ps),
c) ADEV floor is 5x10^-10 because of the ZED-F9T PPS jitter (after saw 
correction) of the gate start input channel.



Thanks in advance
 .marek


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Re: [time-nuts] VFD Idea for HP Equipment

2021-02-08 Thread Marek Dorsic
Hi,

when operating in remote mode, you can use the ":DISP:ENABLE OFF“ command 
through GP-IB to turn the display off 
before starting the measurement loop.

 .marek

> On 8 Feb 2021, at 18:38, Chris Hastreiter  wrote:
> 
> Hi,
> 
> Here's a simple idea in case anyone else is doing long duration testing
> with HP equipment from the Vacuum Fluorescent generation before they began
> including a display-off hotkey.
> 
> This particular example is a 53131A counter which is also before they began
> putting a separate microcontroller in the front panel assembly for display
> operation.  Pin 21 in the ribbon cable is the +38V anode voltage for the
> display, and pins 22 and 24 are the filament circuit.  An auxiliary switch
> interrupts pins 21 and 24 to turn off the VFD and allow the device to
> continue to operate in remote mode.
> 
> Chris
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Re: [time-nuts] x86 CPU Timekeeping and clock generation

2021-01-06 Thread Marek Dorsic
NTP has a drift file (usually /var/lib/ntp/ntp.drift or /var/lib/ntp/drift on 
Linux) where it stores and periodically updates the computers clock drift 
measured by ntpd in ppm.
In your scenario I assume it should contain only one number - 0. If it’s not 0, 
does it correspond to the drift you are observing?
 
   .md

> On 6 Jan 2021, at 08:28, Hal Murray  wrote:
> 
> 
>> My question is: what i'm missing? 
> 
> Two ideas come to mind.
> 
> Most PCs (and servers) smear the CPU clock frequency slightly to dance around 
> the FCC rules.  The chip that does that will have slight temperature 
> influence 
> so even if everything else is working right there will be tiny changes if you 
> look closely enough.
> 
> On Linux, you will see something like this at boot time.  (look in dmesg)
> [0.00] tsc: Detected 3292.448 MHz processor
> 
> Even if the hardware does the right thing, the software may screwup.  If your 
> system is using the TSC for timekeeping, that number above is used to setup 
> the conversion from TSC ticks to ns.  A year or 6 ago, there was a bug in 
> that 
> routine.  If you patched the boot code to call that routine a half dozen 
> times 
> you would get a half dozen different answers.  The kernel guys didn't notice 
> because they were all close enough that ntpd could compensate.  But any geek 
> looking at ntpd graphs of drift would notice big jumps when the system was 
> rebooted.
> 
> 
> -- 
> These are my opinions.  I hate spam.
> 
> 
> 
> 
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