Re: [time-nuts] Phase Noise and ADCs
On 9/26/20 9:33 PM, John Miles wrote: One consequence of charge retention is that when the input signal is in the first Nyquist zone, meaning below fLO/2, no net frequency translation occurs in a sampler. There is no mixing going on, hence no reciprocal mixing either. The sampler's zero-order hold characteristic passes the captured input signal straight through to the output. Because your ADC's front end is a sampler, this is the condition that applies when you digitize a 10 MHz input signal with a 122.88 MHz clock. About 13 times per input cycle, a sample of the 10 MHz signal is captured and transferred to the hold capacitance for eventual readout on the data bus. Any jitter that's present on the 122.88 MHz clock will be transferred as well, but it will be attenuated by 20*log10(12.288) dB because each clock cycle is responsible for capturing only about 1/13 of each input cycle. That actually makes a lot of sense. Thanks very much! John ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Phase Noise and ADCs
> To a first order, the ADC is like an ideal multiplier/mixer - phase noise on > the > clock contributes to phase noise on the sampled data by reciprocal mixing, > just > like a mixer. The ADC-as-mixer metaphor is a useful abstraction, but a leaky one. Here's the way I think of it: while all mixers are multipliers, they fall into two distinct categories, 'stateful' and 'stateless.' Conventional mixers are switches with no internal state of their own. At any given moment they are either on or off based on the LO input state, or they exhibit forward or reverse conduction in the case of a diode ring or similar balanced structure. So their ideal response is dictated solely by the usual Fourier expansion of the square-wave LO harmonics including the first. A harmonic mixer is another stateless mixer, but through topology and component selection it is designed to respond best to input signals near even, odd, or (if driven by a comb generator) both multiples of the LO frequency. Still subject to Fourier at the end of the day, but with specific workarounds where needed. Now, while a sampler is still a multiplier at heart, some 'state' in the form of charge on the sample/hold capacitor is retained from one LO cycle to the next. As a result, unlike a conventional mixer, a sampler's theoretical response at higher input frequencies has nothing to do with the Fourier content of the LO drive signal, but is instead limited by the hold capacitance and external source impedance. It ends up looking like a sin(x)/x function, falling off slowly in general with input frequency but with periodic zeroes near LO harmonics >1. One consequence of charge retention is that when the input signal is in the first Nyquist zone, meaning below fLO/2, no net frequency translation occurs in a sampler. There is no mixing going on, hence no reciprocal mixing either. The sampler's zero-order hold characteristic passes the captured input signal straight through to the output. Because your ADC's front end is a sampler, this is the condition that applies when you digitize a 10 MHz input signal with a 122.88 MHz clock. About 13 times per input cycle, a sample of the 10 MHz signal is captured and transferred to the hold capacitance for eventual readout on the data bus. Any jitter that's present on the 122.88 MHz clock will be transferred as well, but it will be attenuated by 20*log10(12.288) dB because each clock cycle is responsible for capturing only about 1/13 of each input cycle. Make sense? -- john, KE5FX Miles Design LLC ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Phase Noise and ADCs
Hi > On Sep 26, 2020, at 7:22 PM, Magnus Danielson wrote: > > Hi John, > > On 2020-09-26 17:10, John Ackermann N8UR wrote: >> We know that phase noise scales with frequency, so if you multiply >> frequency by 10 you get a 20 dB increase in noise. >> >> What I don't fully understand is how that relationship works with >> other than simple multiplication/division. >> >> For example (and my real life concern), if I have an analog to digital >> converter that is clocked at 122.88 MHz and know the phase noise of >> that clock signal, what do I know about the effective phase noise when >> the ADC is receiving a signal at, e.g., 12.288 MHz? >> >> In other words, if I were to measure the phase noise at the output of >> the ADC when fed a high-enough quality 12.288 MHz signal, would I see >> something like the 122.88 MHz phase noise, or something better due to >> the scaling by 10? > > In this case, your 12.288 MHz phase-noise will be augmented with the > scaled-down version of the 122,88 MHz phase-noise. The trick being used > is to actually let the sampling clock of the ADC be a transfer clock > such that it samples a reference also, at which time one subtracts the > phase-data from the reference, most of the transfer clocks noise cancels > out, and it does so fairly well as it have common integration time > between the channels, so you avoid the decorrelation that DMTD normally > suffers from. The second trick being used is to use a second pair of > ADCs to make ADC deficiensies cancel out too, as the DUT and REF is > common mode and the individual ADC noise contributors can be averaged out. > If you are going to do the “cancel out” process, a dual ADC with a common clock interface is a really good idea. Not all dual ADC devices have that feature…… Bob > Now, as you decimate data etc. you still have the issue of ADC > resolution, as that has a tendency to loose weak side-bands. The > non-linearity is kind of peculiar actually. > > I recommend you to dig up Sam Stein's papers on his phase noise > development. I think you will find them a good read and help you with > your understanding. > > Cheers, > Magnus > > > > ___ > time-nuts mailing list -- time-nuts@lists.febo.com > To unsubscribe, go to > http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com > and follow the instructions there. ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Phase Noise and ADCs
Hi John, On 2020-09-26 17:10, John Ackermann N8UR wrote: > We know that phase noise scales with frequency, so if you multiply > frequency by 10 you get a 20 dB increase in noise. > > What I don't fully understand is how that relationship works with > other than simple multiplication/division. > > For example (and my real life concern), if I have an analog to digital > converter that is clocked at 122.88 MHz and know the phase noise of > that clock signal, what do I know about the effective phase noise when > the ADC is receiving a signal at, e.g., 12.288 MHz? > > In other words, if I were to measure the phase noise at the output of > the ADC when fed a high-enough quality 12.288 MHz signal, would I see > something like the 122.88 MHz phase noise, or something better due to > the scaling by 10? In this case, your 12.288 MHz phase-noise will be augmented with the scaled-down version of the 122,88 MHz phase-noise. The trick being used is to actually let the sampling clock of the ADC be a transfer clock such that it samples a reference also, at which time one subtracts the phase-data from the reference, most of the transfer clocks noise cancels out, and it does so fairly well as it have common integration time between the channels, so you avoid the decorrelation that DMTD normally suffers from. The second trick being used is to use a second pair of ADCs to make ADC deficiensies cancel out too, as the DUT and REF is common mode and the individual ADC noise contributors can be averaged out. Now, as you decimate data etc. you still have the issue of ADC resolution, as that has a tendency to loose weak side-bands. The non-linearity is kind of peculiar actually. I recommend you to dig up Sam Stein's papers on his phase noise development. I think you will find them a good read and help you with your understanding. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Phase Noise and ADCs
On 9/26/20 9:56 AM, Bob kb8tq wrote: Hi In addition, the input to the ADC has it’s own noise issues. If you have a really clean clock (or a poor ADC), the noise floor of the input may dominate the noise floor. Bob Yes - and typically, this spec is not given in a useful fashion for time-nuttery. You have to test it and see what it is. for instance, the AD9650 has a specified aperture uncertainty specified as jitter of, say, 0.08 picosecond, rms. And they don't specify what the clock input bandwidth is. On Sep 26, 2020, at 12:28 PM, jimlux wrote: On 9/26/20 8:10 AM, John Ackermann N8UR wrote: We know that phase noise scales with frequency, so if you multiply frequency by 10 you get a 20 dB increase in noise. What I don't fully understand is how that relationship works with other than simple multiplication/division. For example (and my real life concern), if I have an analog to digital converter that is clocked at 122.88 MHz and know the phase noise of that clock signal, what do I know about the effective phase noise when the ADC is receiving a signal at, e.g., 12.288 MHz? To a first order, the ADC is like an ideal multiplier/mixer - phase noise on the clock contributes to phase noise on the sampled data by reciprocal mixing, just like a mixer. In other words, if I were to measure the phase noise at the output of the ADC when fed a high-enough quality 12.288 MHz signal, would I see something like the 122.88 MHz phase noise, or something better due to the scaling by 10? Thanks! John ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there. ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there. ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there. ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Phase Noise and ADCs
Hi In addition, the input to the ADC has it’s own noise issues. If you have a really clean clock (or a poor ADC), the noise floor of the input may dominate the noise floor. Bob > On Sep 26, 2020, at 12:28 PM, jimlux wrote: > > On 9/26/20 8:10 AM, John Ackermann N8UR wrote: >> We know that phase noise scales with frequency, so if you multiply frequency >> by 10 you get a 20 dB increase in noise. >> What I don't fully understand is how that relationship works with other than >> simple multiplication/division. >> For example (and my real life concern), if I have an analog to digital >> converter that is clocked at 122.88 MHz and know the phase noise of that >> clock signal, what do I know about the effective phase noise when the ADC is >> receiving a signal at, e.g., 12.288 MHz? > > To a first order, the ADC is like an ideal multiplier/mixer - phase noise on > the clock contributes to phase noise on the sampled data by reciprocal > mixing, just like a mixer. > > > >> In other words, if I were to measure the phase noise at the output of the >> ADC when fed a high-enough quality 12.288 MHz signal, would I see something >> like the 122.88 MHz phase noise, or something better due to the scaling by >> 10? >> Thanks! >> John >> ___ >> time-nuts mailing list -- time-nuts@lists.febo.com >> To unsubscribe, go to >> http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com >> and follow the instructions there. > > > ___ > time-nuts mailing list -- time-nuts@lists.febo.com > To unsubscribe, go to > http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com > and follow the instructions there. ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Phase Noise and ADCs
On 9/26/20 8:10 AM, John Ackermann N8UR wrote: We know that phase noise scales with frequency, so if you multiply frequency by 10 you get a 20 dB increase in noise. What I don't fully understand is how that relationship works with other than simple multiplication/division. For example (and my real life concern), if I have an analog to digital converter that is clocked at 122.88 MHz and know the phase noise of that clock signal, what do I know about the effective phase noise when the ADC is receiving a signal at, e.g., 12.288 MHz? To a first order, the ADC is like an ideal multiplier/mixer - phase noise on the clock contributes to phase noise on the sampled data by reciprocal mixing, just like a mixer. In other words, if I were to measure the phase noise at the output of the ADC when fed a high-enough quality 12.288 MHz signal, would I see something like the 122.88 MHz phase noise, or something better due to the scaling by 10? Thanks! John ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there. ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
[time-nuts] Phase Noise and ADCs
We know that phase noise scales with frequency, so if you multiply frequency by 10 you get a 20 dB increase in noise. What I don't fully understand is how that relationship works with other than simple multiplication/division. For example (and my real life concern), if I have an analog to digital converter that is clocked at 122.88 MHz and know the phase noise of that clock signal, what do I know about the effective phase noise when the ADC is receiving a signal at, e.g., 12.288 MHz? In other words, if I were to measure the phase noise at the output of the ADC when fed a high-enough quality 12.288 MHz signal, would I see something like the 122.88 MHz phase noise, or something better due to the scaling by 10? Thanks! John ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
