[U-Boot] 83xx, uec: split enet_interface in two variables, was: 83xx, uec: adjust enet_interface settings on the fly.
There's no sensible reason to unite speed and interface type into
one variable. So split this variable enet_interface into two
vars: enet_interface_type, which hold the interface type and speed.
Also: add the possibility for switching between 10 and 100 MBit
interfaces on the fly, when running in FAST_ETH mode.
Signed-off-by: Heiko Schocher h...@denx.de
---
board/freescale/mpc8360emds/mpc8360emds.c |3 +-
drivers/qe/uec.c | 122 -
drivers/qe/uec.h | 34
drivers/qe/uec_phy.c | 84 +++-
include/configs/MPC8323ERDB.h |6 +-
include/configs/MPC832XEMDS.h |6 +-
include/configs/MPC8360EMDS.h |6 +-
include/configs/MPC8360ERDK.h |6 +-
include/configs/MPC8568MDS.h |6 +-
include/configs/MPC8569MDS.h | 30 +---
include/configs/kmeter1.h |3 +-
11 files changed, 175 insertions(+), 131 deletions(-)
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c
b/board/freescale/mpc8360emds/mpc8360emds.c
index d4ba043..4f55732 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -159,7 +159,8 @@ int board_eth_init(bd_t *bd)
int i;
for (i = 0; i ARRAY_SIZE(uec_info); i++)
- uec_info[i].enet_interface = ENET_1000_RGMII_RXID;
+ uec_info[i].enet_interface_type = RGMII_RXID;
+ uec_info[i].speed = 1000;
}
return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info));
}
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index db95ada..881632d 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -323,9 +323,10 @@ static int uec_set_mac_duplex(uec_private_t *uec, int
duplex)
return 0;
}
-static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode)
+static int uec_set_mac_if_mode(uec_private_t *uec,
+ enet_interface_type_e if_mode, int speed)
{
- enet_interface_eenet_if_mode;
+ enet_interface_type_e enet_if_mode;
uec_info_t *uec_info;
uec_t *uec_regs;
u32 upsmr;
@@ -346,52 +347,68 @@ static int uec_set_mac_if_mode(uec_private_t *uec,
enet_interface_e if_mode)
upsmr = in_be32(uec-uccf-uf_regs-upsmr);
upsmr = ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
- switch (enet_if_mode) {
- case ENET_100_MII:
- case ENET_10_MII:
+ switch (speed) {
+ case 10:
maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
+ switch (enet_if_mode) {
+ case MII:
+ break;
+ case RGMII:
+ upsmr |= (UPSMR_RPM | UPSMR_R10M);
+ break;
+ case RMII:
+ upsmr |= (UPSMR_R10M | UPSMR_RMM);
+ break;
+ default:
+ return -EINVAL;
+ break;
+ }
break;
- case ENET_1000_GMII:
- maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
- break;
- case ENET_1000_TBI:
- maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
- upsmr |= UPSMR_TBIM;
- break;
- case ENET_1000_RTBI:
- maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
- upsmr |= (UPSMR_RPM | UPSMR_TBIM);
- break;
- case ENET_1000_RGMII_RXID:
- case ENET_1000_RGMII_ID:
- case ENET_1000_RGMII:
- maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
- upsmr |= UPSMR_RPM;
- break;
- case ENET_100_RGMII:
- maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
- upsmr |= UPSMR_RPM;
- break;
- case ENET_10_RGMII:
- maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
- upsmr |= (UPSMR_RPM | UPSMR_R10M);
- break;
- case ENET_100_RMII:
- maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
- upsmr |= UPSMR_RMM;
- break;
- case ENET_10_RMII:
+ case 100:
maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
- upsmr |= (UPSMR_R10M | UPSMR_RMM);
+ switch (enet_if_mode) {
+
[U-Boot] 83xx, kmeter1: fix compile error
- delete double MTDIDS_DEFAULT and MTDPARTS_DEFAULT defines in board config file. - add mising CONFIG_KM_UBI_PARTITION_NAME define Signed-off-by: Heiko Schocher h...@denx.de --- include/configs/kmeter1.h |7 ++- 1 files changed, 2 insertions(+), 5 deletions(-) diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index e812eda..d27b75b 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -33,6 +33,8 @@ /* include common defines/options for all Keymile boards */ #include keymile-common.h +#define CONFIG_KM_UBI_PARTITION_NAME ubi0 + #define MTDIDS_DEFAULT nor0=boot #define MTDPARTS_DEFAULT \ mtdparts=boot:768k(u-boot),128k(env),128k(envred),\ @@ -450,11 +452,6 @@ #define CONFIG_PRAM512 /* protected RAM [KBytes] */ -#define MTDIDS_DEFAULT nor2=app -#define MTDPARTS_DEFAULT \ - mtdparts=app:256k(u-boot),128k(env),128k(envred), \ - 1536k(esw0),8704k(rootfs0),1536k(esw1),2432k(rootfs1),640k(var),768k(cfg) - /* * Environment Configuration */ -- 1.6.2.5 -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ColdFire I2C implementing I2C idle [PATCH]
Hello Michael, Michael Durrant wrote: Signed-off-by: David Wu davi...@arcturusnetworks.com Signed-off-by: Michael Durrant mdurr...@arcturusnetworks.com Can you please use git-format-patch for creating this patch, and post it here again not attached, just as plain text? (Same for your other 3 patches) Thanks. bye Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] u-boot fails to read from nand flash in omap3
Thanks for your quick replies, I could finally solve it yesterday, the problem was that I was writing the nand with nandecc set to HW, so if I read it just after writing it would work, but as soon as I reseted it, it would go back to ecc SW and stop working... I was just forgetting to add a nandecc hw before reading the nand... thanks for the ideas, :) best regards -- View this message in context: http://old.nabble.com/u-boot-fails-to-read-from-nand-flash-in-omap3-tp27222315p27238600.html Sent from the Uboot - Users mailing list archive at Nabble.com. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Add bootcount to AT91
Hi all,
As the merge window has closed, I'd just like to bump my old mail
below and ask for comments. Currently the actual register to use is
hard-coded. I'm unsure of what the current status is when it comes to
include new architecture specific CONFIG_*-options.
The bootcount-feature is supported in u-boot for some PPC-boards. The
patch below is basically a rip-off of one of these features, adapted
for the AT91SAM9-architecture. It is tested on an olimex board with an
at91sam9260.
I'd be very happy if we could get this feature mainlined. (I've also
got some replies off-list, from people wanting to use this feature.)
Thanks in advance!
Best regards,
Anders
On Thu, Jan 14, 2010 at 15:00, Anders Darander
anders.daran...@gmail.com wrote:
From: Anders Darander a...@datarespons.se
Use AT91_GPBR 3 as a bootcount register.
Signed-off-by: Anders Darander a...@datarespons.se
---
cpu/arm926ejs/at91/cpu.c | 28
1 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/cpu/arm926ejs/at91/cpu.c b/cpu/arm926ejs/at91/cpu.c
index f2f7b62..09c1376 100644
--- a/cpu/arm926ejs/at91/cpu.c
+++ b/cpu/arm926ejs/at91/cpu.c
@@ -31,6 +31,11 @@
#define AT91_MAIN_CLOCK 0
#endif
+/* The at91sam9260 has 4 GPBR (0-3), we'll use the last one, nr 3,
+ * to keep track of the bootcount. */
+#define AT91_GPBR_BOOTCOUNT_REGISTER 3
+#define AT91_BOOTCOUNT_ADDRESS (AT91_GPBR + 4*AT91_GPBR_BOOTCOUNT_REGISTER)
+
int arch_cpu_init(void)
{
return at91_clock_init(AT91_MAIN_CLOCK);
@@ -52,3 +57,26 @@ int print_cpuinfo(void)
return 0;
}
#endif
+
+#ifdef CONFIG_BOOTCOUNT_LIMIT
+
+void bootcount_store (ulong a)
+{
+ volatile ulong *save_addr =
+ (volatile ulong *)(AT91_BASE_SYS + AT91_BOOTCOUNT_ADDRESS);
+
+ *save_addr = (BOOTCOUNT_MAGIC 0x) | a;
+}
+
+ulong bootcount_load (void)
+{
+ volatile ulong *save_addr =
+ (volatile ulong *)(AT91_BASE_SYS + AT91_BOOTCOUNT_ADDRESS);
+
+ if ((*save_addr 0x) != (BOOTCOUNT_MAGIC 0x))
+ return 0;
+ else
+ return (*save_addr 0x);
+}
+
+#endif /* CONFIG_BOOTCOUNT_LIMIT */
--
1.6.6
--
Anders Darander
EPO guidelines 1978: If the contribution to the known art resides
solely in a computer program then the subject matter is not
patentable in whatever manner it may be presented in the claims.
___
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Re: [U-Boot] [PATCH V2 7/9] fsl_esdhc: add support for mx51 processor
Andy Fleming wrote: Wolfgang has already covered most of this, but I have a few other comments (plus a couple of redundant ones) Hi Andy, I know why you did this, but I really think it's a bad idea to trick the driver into doing the right thing. I agree, I wanted only to point out why I need to do this ;) It's more painful, but we need to change all of the out_be32/in_be32 commands into something generic, and then add support for big and little endian accesses. This is just a hack. :( Ok, let's see if I have really understood and I can proceed with the modifications. I start to change the driver replacing all _be32 functions with a more neutral name (write_register/read_register or something like that). I will define these functions then in asm-ppc/io.h and asm-arm/io.h, setting them to the desired function. Let's try to use #ifdefs sparingly, and definitely have them trigger on constants that are directly related to the difference. This isn't a PPC/ARM problem. I see you've already agreed to use gd-sdhc_clk, though, so that's good. I agree, using global data is a good idea. You have two choices, here. Either create a new CONFIG_SYS option that declares the existence of this register for platforms that have it, In this case we will probably get a lot of CONFIG_SYS options when Freescale changes version or uses this controller on other processors. There are some different registers, not only for snooping. In most cases, some further bits are added. At least I need to know if the SDCLK_EN bit is present in the control register (present in the MX.51 implementation, absent in PowerQuick). OR (my preference) design a configuration mechanism which allows board/cpu code to declare such things. I agree with you. I have already changed the initialization procedure and I can pass (as you suggest later) a configuration structure that describe the feature of the controller. The board can set this structure in board_mmc_init(). If it is not set, the driver should work as now (powerpc), so the structure must be filled only by arm boards. Ideally, the driver could detect this based on a version register, but I'm well aware that FSL's hardware designers frequently forget to increment their version numbers for such small changes. I know, the version register is not reliable enough... What is certain is that CONFIG_PPC is wrong. Absolutely agree, I get rid of it. const char *compat = fsl,esdhc; @@ -365,3 +414,4 @@ out: do_fixup_by_compat(blob, compat, status, status, strlen(status) + 1, 1); } +#endif Use the OF config option, here. Ok, thanks. +#define clrbits_be32(addr, clear) clrbits(l, addr, clear) +#define setbits_be32(addr, set) setbits(l, addr, set) +#define clrsetbits_be32(addr, clear, set) clrsetbits(l, addr, clear, set) + + This should be part of a completely different patch. Also, I'm positive that it's completely wrong. setbits_be32 is big endian, writel is little endian. Agree. I will set a separate patch to setup the newer functions to access the registers. #ifdef CONFIG_FSL_ESDHC int fsl_esdhc_mmc_init(bd_t *bis); +int fsl_esdhc_initialize(bd_t *bis, uint32_t esdhc_addr, + int (*getcd)(struct mmc *mmc)); Hmmmthis doesn't scale well. Rather than pass in an address and a function pointer, create a structure with that information, and then pass *that* in. That way, when we discover we want some other information/functions, we can add them without having to modify the API. You are right. I will create a structure that I can use to describe the feature of the controller, as you already suggested. I think getcd needs more discussion, but even if it doesn't, this clearly belongs in a separate patch. You are modifying the U-Boot MMC API, here, not just the fsl_esdhc driver. Probably I do not need anymore. I can implement as you suggest a weakly defined function, something like: int board_mmc_getcd(u8 *cd, struct mmc *mmc)__attribute__((weak, alias(__board_mmc_getcd))) If this failed, I can use the internal bits of the controller to check the presence of the card. Stefano -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: off...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] U-boot running on DDR fails to detect the CFI compliant flash
Hi Albert and Stefan, I have used the proper commands. i.e. mw.b 0xfc00 0xf0 mw.b 0xfc55 0x98 md.b 0xfc10 But still no positive results. Last time I forgot to tell here, that I have commneted the for(;;) loop in hang function after flash_init result testing in lib_ppc/board.c and then I am able to run the above commands on uboot prompt. 1) You're writing 32-bit words to the chip. At most it should be 16-bit words, possibly even 8-bits. Try mw.w and mw.b. Prakash - I tried both but no success. How to crosscheck the chipwidth? Can someone tell what is chipwidth and portwidth? I believe I am using chipwidth - 16 and portwidth - 8. How to validate this against chipwidth and portwidth? 2) Your writes actually appear where you did them, as if the flash was already in write mode, which is highly unlikely, or if you had some cache enabled for this area of your address space. Prakash - Albert, I didn't understand above message clearly. Please explain what you want to say. If anyhow my flash is in write mode then also I should be able to see the CFI query command response. PCIMW. Hi Baren, Please reply to my earlier mail addressed to you if possible. Thanks Regards, Prakash Bedge On Tue, Jan 19, 2010 at 10:14 PM, Albert ARIBAUD albert.arib...@free.frwrote: prakash bedge a écrit : Hi Baren and Stefan What I find is *VERY* helpful when trying to understand flash control issues is to *manually* do the QRY write sequence (see your flash data sheet) by using memory write/read commands from the u-boot command prompt I tested the same using mw and md commands from uboot prompt for read CFI query command. But test failed. Log details: mw 0xfc00 0xf0 mw 0xfc55 0x98 md 0xfc10 fc10: fc20: fc30: fc40: fc50: ff00 98ff . fc60: fc70: fc80: fc90: fca0: fcb0: fcc0: fcd0: fce0: fcf0: fc000100: mw 0xfc00 0xf0 mw 0xfcAA 0x98 ... This is the actual mapping. md 0xfc20 fc20: fc30: fc40: fc50: ff00 98ff . fc60: fc70: fc80: fc90: fca0: 0098.. ... fcb0: fcc0: fcd0: fce0: fcf0: fc000100: fc000110: I believe that I am executing correct commands. If wrong please guide me. M29W128Gh details: chip is 16 bit (is this chipwidth?) bus is 8 bit (is this portwidth?) Algorithm -AMD Banks- 1 sectors - 128 Which u-boot version you used where you do not need to change the uboot code for ST make M29W128GH? What other configuration or code I need to check in order to identify the root cause? Two things strike me as weird: 1) You're writing 32-bit words to the chip. At most it should be 16-bit words, possibly even 8-bits. Try mw.w and mw.b. 2) Your writes actually appear where you did them, as if the flash was already in write mode, which is highly unlikely, or if you had some cache enabled for this area of your address space. Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Linux Kernel without Ethernet (missed MAC)
Hi Arno, But maybe you did not even read the FAQ, for example http://www.denx.de/wiki/view/DULG/EthernetDoesNotWorkInLinux ? In my first mail (http://lists.denx.de/pipermail/u-boot/2010-January/066703.html) I wrote that I have checked this and wrote down what I found out. Probably it is due to my limited experience in this, that's why I asked for help. A ifconfig after boot will not help, as I don't have an eth-device. I will not comment yet another time on this infamous topic of passing MAC addresses to the Linux kernel in the ARM world - we tried several times to fix this. Usually we were informed that this can be easily (really that's what they tell you on the ARM mailing list) done with an initial ramdisk - even if you want to use an NFS rootfilesystem. So for your information - you should still have an ethernet interface in Linux, you simply have to assign a mac. Use something like ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx. Then the interface should work. Cheers Detlev -- I've never understood the tendency to pick up tastes because they are popular. In fact, I think it is foolish to do that. I mean, don't you know what you like? People who are so weak that they will take their tastes from people around them in the desperate desire to be accepted, I think of them as cowards. -- Richard M. Stallman -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: d...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [GIT PULL] MIPS updates
Hi, please pull the following unaligned.h patch required by zlib.c. Thanks in advance, Shinya --- The following changes since commit 50ef25ef24eccd8e69d2c1ccc97b3f7e30109f51: Michal Simek (1): microblaze: zlib needs asm/unaligned.h are available in the git repository at: git://git.denx.de/u-boot-mips.git master Shinya Kuribayashi (1): MIPS: qemu_mips: Import asm/unaligned.h from the Linux kernel include/asm-mips/unaligned.h | 26 ++ 1 files changed, 26 insertions(+), 0 deletions(-) create mode 100644 include/asm-mips/unaligned.h ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [STATUS] Merge Window closed, waiting for pull requests
Dear Mike Frysinger, In message 201001191826.17864.vap...@gentoo.org you wrote: did you see my pull request for kgdb patches from the Blackfin tree ? I did. Do you think anything is missing in current mainline? also, should i collect my misc smallish patches that saw no feedback in a tree for you ? That would be really nice - but then, I don't think there are any patches outstanding that are not architecture-specific and therefore have to go through the respective custodians? Please post a list of patches you think missing. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de It is easier to write an incorrect program than understand a correct one. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] U-boot running on DDR fails to detect the CFI compliant flash
Hi Prakash Please quote properly and don't top post. Your emails are very hard to understand. prakash bedge wrote: Hi Albert and Stefan, I have used the proper commands. i.e. mw.b 0xfc00 0xf0 mw.b 0xfc55 0x98 md.b 0xfc10 But still no positive results. Last time I forgot to tell here, that I have commneted the for(;;) loop in hang function after flash_init result testing in lib_ppc/board.c and then I am able to run the above commands on uboot prompt. 1) You're writing 32-bit words to the chip. At most it should be 16-bit words, possibly even 8-bits. Try mw.w and mw.b. Prakash - I tried both but no success. How to crosscheck the chipwidth? Can someone tell what is chipwidth and portwidth? I believe I am using chipwidth - 16 and portwidth - 8. How to validate this against chipwidth and portwidth? Number one thing you *MUST* do is read the flash data sheets, especially the command interface. Repeat until you understand. Then try the QRY command sequence by hand in all the various possibilities (see thread links below). * In your hardware, the 55 and AA addresses may be shifted by one or two bits: http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/31501/focus=31735 * In your hardware, the command byte lane may be one byte wide, two bytes wide, or four bytes wide. This changes the 55/AA addresses and which byte lane(s) are used for the command. * Do you have 1, 2, or 4 chips on your board? * Is your memory bus 1, 2, or 4 bytes wide? The thread links below will help explain. Note that Robert is using the BDI, and thus using the BDI memory read/write commands. You want to use u-boot's memory read/write commands instead. Pay special attention to these posts: http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/31501/focus=31588 http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/31501/focus=31723 http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/31501/focus=31724 http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/31501/focus=31730 http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/31501/focus=31735 http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/31501/focus=31787 http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/31501/focus=31738 Good luck, gvb [snip] ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] mpc5xxx: Support CPU internal watchdog.
Signed-off-by: Detlev Zundel d...@denx.de
---
cpu/mpc5xxx/cpu.c | 20 +++-
cpu/mpc5xxx/cpu_init.c | 14 +-
include/watchdog.h |5 +
3 files changed, 37 insertions(+), 2 deletions(-)
diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c
index 2a28df4..edfb828 100644
--- a/cpu/mpc5xxx/cpu.c
+++ b/cpu/mpc5xxx/cpu.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2000-2003
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, w...@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -192,3 +192,21 @@ int cpu_eth_init(bd_t *bis)
return mpc5xxx_fec_initialize(bis);
}
#endif
+
+#if defined(CONFIG_WATCHDOG)
+void watchdog_reset(void)
+{
+ int re_enable = disable_interrupts();
+ reset_5xxx_watchdog();
+ if (re_enable) enable_interrupts();
+}
+
+void reset_5xxx_watchdog(void)
+{
+ volatile struct mpc5xxx_gpt *gpt0 =
+ (struct mpc5xxx_gpt *) MPC5XXX_GPT;
+
+ /* Trigger TIMER_0 by writing A5 to OCPW */
+ clrsetbits_be32(gpt0-emsr, 0xff00, 0xa500);
+}
+#endif /* CONFIG_WATCHDOG */
diff --git a/cpu/mpc5xxx/cpu_init.c b/cpu/mpc5xxx/cpu_init.c
index acff5f5..b151464 100644
--- a/cpu/mpc5xxx/cpu_init.c
+++ b/cpu/mpc5xxx/cpu_init.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2000-2009
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, w...@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -24,6 +24,7 @@
#include common.h
#include mpc5xxx.h
#include asm/io.h
+#include watchdog.h
DECLARE_GLOBAL_DATA_PTR;
@@ -45,6 +46,8 @@ void cpu_init_f (void)
(struct mpc5xxx_gpio *) MPC5XXX_GPIO;
volatile struct mpc5xxx_xlb *xlb =
(struct mpc5xxx_xlb *) MPC5XXX_XLBARB;
+ volatile struct mpc5xxx_gpt *gpt0 =
+ (struct mpc5xxx_gpt *) MPC5XXX_GPT;
unsigned long addecr = (1 25); /* Boot_CS */
#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_MGT5100)
addecr |= (1 22); /* SDRAM enable */
@@ -206,6 +209,15 @@ void cpu_init_f (void)
/* Enable piplining */
clrbits_be32(xlb-config, (1 31));
# endif
+
+#if defined(CONFIG_WATCHDOG)
+ /* Charge the watchdog timer - prescaler = 64k, count = 64k*/
+ out_be32(gpt0-cir, 0x);
+ out_be32(gpt0-emsr, 0x9004); /* wden|ce|timer_ms */
+
+ reset_5xxx_watchdog();
+#endif /* CONFIG_WATCHDOG */
+
#endif /* CONFIG_MPC5200 */
}
diff --git a/include/watchdog.h b/include/watchdog.h
index 9265be9..ef2f5aa 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -84,6 +84,11 @@
void reset_5xx_watchdog(volatile immap_t *immr);
#endif
+/* MPC 5xxx */
+#if defined(CONFIG_MPC5xxx) !defined(__ASSEMBLY__)
+ void reset_5xxx_watchdog(void);
+#endif
+
/* AMCC 4xx */
#if defined(CONFIG_4xx) !defined(__ASSEMBLY__)
void reset_4xx_watchdog(void);
--
1.6.2.5
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Re: [U-Boot] Linux Kernel without Ethernet (missed MAC)
I did a small mod in uboot now. After each ethernet-access the interface chip seems to get a soft reset, which deletes the mac address in its registers. So in smc911x.h () in function smc911x_reset I commented the line // smc911x_reg_write(dev, HW_CFG, HW_CFG_SRST); It is somehow pitty that kernel (even latest) and uboot doesn't match anymore. As I coudn't find out how does the kernel usually know the mac from, I don't know what part is responsible. Thanks all of you for your help. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] da830evm: Use table driven pin mux configuration
Tidyup the pin muxer configuration using the Davinci table driven pinmux configuration function and data tables. Signed-off-by: Nick Thompson nick.thomp...@ge.com --- Applies to master Changes: Rebased after USB patch board/davinci/da830evm/da830evm.c | 35 +--- --- Pushed to u-boot-ti Thanks, Sandeep ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Profiling uboot
On Wed, Jan 20, 2010 at 09:51:57AM +0530, Basavaraj Dengi wrote:
Hi,
I am trying to measure the time taken by uboot, from its init till
it jumps to zImage[kernel].
Any suggestions as to which API's to be used for that?
Thanks in advance.
I've used the attached ptx_ts script to measure U-Boot. It probably came
from this mailing list at some point.
Ira
#! /usr/bin/perl
#
# ptx_ts - Pengutronix' Add A Time Stamp Filter V1
# written by Wolfram Sang, Copyright 2009 Pengutronix
# free software - no warranty - WTFPL V2, see http://sam.zoy.org/wtfpl/
use warnings;
use strict;
use Time::HiRes qw(gettimeofday tv_interval);
my $arg = defined($ARGV[0]) ? $ARGV[0] : '(?=foo)bar'; # false-branch is a
regexp that never matches
if ($arg eq '--help') {
print ptx_ts [regexp] - a filter which prepends a timestamp to every
line of STDOUT; time will be reset if [regexp] matches\n;
print Example: microcom microcom_options | ptx_ts 'U-Boot 2.0'\n;
exit 0;
}
my $old;
my $base;
$| = 1; # Flush output immediately
sub reset_time {
$old = 0;
$base = [gettimeofday()];
}
reset_time;
while (STDIN) {
reset_time if (/$arg/o);
my $new = tv_interval($base);
my $diff = $new - $old;
printf([%10.6f] %10.6f $_, $new, $diff);
$old = $new;
}
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[U-Boot] [PATCH V3 01/11] mkimage: Add Freescale imx Boot Image support (imximage)
This patch adds support for imximage (MX Boot Image)
to the mkimage utility. The imximage is used on the Freescales's
MX.25, MX.35 and MX.51 processors.
Further details under doc/README.imximage.
This patch was tested on a Freescale mx51evk board.
Signed-off-by: Stefano Babic sba...@denx.de
---
Makefile|4 +
common/image.c |1 +
doc/README.imximage | 188 +
include/image.h |1 +
tools/Makefile |2 +
tools/imximage.c| 324 +++
tools/imximage.h| 105 +
tools/mkimage.c |2 +
tools/mkimage.h |1 +
9 files changed, 628 insertions(+), 0 deletions(-)
create mode 100644 doc/README.imximage
create mode 100644 tools/imximage.c
create mode 100644 tools/imximage.h
diff --git a/Makefile b/Makefile
index ed6156f..365f87f 100644
--- a/Makefile
+++ b/Makefile
@@ -324,6 +324,10 @@ $(obj)u-boot.img: $(obj)u-boot.bin
sed -e 's/[ ]*$$/ for $(BOARD) board/') \
-d $ $@
+$(obj)u-boot.imx: $(obj)u-boot.bin
+ $(obj)tools/mkimage -n $(IMX_CONFIG) -T imximage \
+ -e $(TEXT_BASE) -d $ $@
+
$(obj)u-boot.kwb: $(obj)u-boot.bin
$(obj)tools/mkimage -n $(KWD_CONFIG) -T kwbimage \
-a $(TEXT_BASE) -e $(TEXT_BASE) -d $ $@
diff --git a/common/image.c b/common/image.c
index 82e7aa4..9e49713 100644
--- a/common/image.c
+++ b/common/image.c
@@ -140,6 +140,7 @@ static table_entry_t uimage_type[] = {
{ IH_TYPE_STANDALONE, standalone, Standalone Program, },
{ IH_TYPE_FLATDT, flat_dt,Flat Device Tree, },
{ IH_TYPE_KWBIMAGE, kwbimage, Kirkwood Boot Image,},
+ { IH_TYPE_IMXIMAGE, imximage, Freescale i.MX Boot Image,},
{ -1, , , },
};
diff --git a/doc/README.imximage b/doc/README.imximage
new file mode 100644
index 000..9048ef6
--- /dev/null
+++ b/doc/README.imximage
@@ -0,0 +1,188 @@
+-
+Imximage Boot Image generation using mkimage
+-
+
+This document describes how to set up a U-Boot image
+that can be booted by Freescale MX25, MX35 and MX51
+processors via internal boot mode.
+
+These processors can boot directly from NAND, SPI flash and SD card flash
+using its internal boot ROM support. They can boot from an internal
+UART, if booting from device media fails.
+Booting from NOR flash does not require to use this image type.
+
+For more details refer Chapter 2 - System Boot and section 2.14
+(flash header description) of the processor's manual.
+
+This implementation does not use at the moment the secure boot feature
+of the processor. The image is generated disabling all security fields.
+
+Command syntax:
+--
+./tools/mkimage -l mx u-boot_file
+ to list the imx image file details
+
+./tools/mkimage -T imximage \
+ -n board specific configuration file \
+ -e execution address -d u-boot binary output image file
+
+For example, for the mx51evk board:
+./tools/mkimage -n ./board/freescale/mx51evk/imximage.cfg \
+ -T imximage -e 0x9780 \
+ -d u-boot.bin u-boot.imx
+
+You can generate directly the image when you compile u-boot with:
+
+$ make u-boot.imx
+
+The output image can be flashed on the board SPI flash or on a SD card.
+In both cases, you have to copy the image at the offset required for the
+chosen media devices (0x400 for both SPI flash or SD card).
+
+Please check Freescale documentation for further details.
+
+Board specific configuration file specifications:
+-
+1. This file must present in the $(BOARDDIR) and the name should be
+ imximage.cfg (since this is used in Makefile).
+2. This file can have empty lines and lines starting with # as first
+ character to put comments.
+3. This file can have configuration command lines as mentioned below,
+ any other information in this file is treated as invalid.
+
+Configuration command line syntax:
+-
+1. Each command line is must have two strings, first one command or address
+ and second one data string
+2. Following are the valid command strings and associated data strings:-
+ Command string data string
+ -- ---
+ BOOT_FROM nand/spi/sd/onenand
+ Example:
+ BOOT_FROM spi
+ DATAtype address value
+
+ type: word=4, halfword=2, byte=1
+ address: physycal register address
+ value: value to be set in register
+ All values are in in
[U-Boot] [PATCH V3 02/11] MX51: Add initial support for the Freescale MX51
The patch add initial support for the Freescale i.MX51 processor
(family arm cortex_a8).
Signed-off-by: Stefano Babic sba...@denx.de
Signed-off-by: Fred Fan fanyef...@gmail.com
---
cpu/arm_cortexa8/mx51/Makefile| 48 ++
cpu/arm_cortexa8/mx51/clock.c | 293 +
cpu/arm_cortexa8/mx51/iomux.c | 165 ++
cpu/arm_cortexa8/mx51/lowlevel_init.S | 289
cpu/arm_cortexa8/mx51/soc.c | 109
cpu/arm_cortexa8/mx51/timer.c | 119 +
cpu/arm_cortexa8/mx51/u-boot.lds | 61 +++
include/asm-arm/arch-mx51/clock.h | 31
8 files changed, 1115 insertions(+), 0 deletions(-)
create mode 100644 cpu/arm_cortexa8/mx51/Makefile
create mode 100644 cpu/arm_cortexa8/mx51/clock.c
create mode 100644 cpu/arm_cortexa8/mx51/iomux.c
create mode 100644 cpu/arm_cortexa8/mx51/lowlevel_init.S
create mode 100644 cpu/arm_cortexa8/mx51/soc.c
create mode 100644 cpu/arm_cortexa8/mx51/timer.c
create mode 100644 cpu/arm_cortexa8/mx51/u-boot.lds
create mode 100644 include/asm-arm/arch-mx51/clock.h
diff --git a/cpu/arm_cortexa8/mx51/Makefile b/cpu/arm_cortexa8/mx51/Makefile
new file mode 100644
index 000..4d82293
--- /dev/null
+++ b/cpu/arm_cortexa8/mx51/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# (C) Copyright 2009 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(SOC).a
+
+COBJS = soc.o clock.o iomux.o timer.o
+SOBJS = lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB):$(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/cpu/arm_cortexa8/mx51/clock.c b/cpu/arm_cortexa8/mx51/clock.c
new file mode 100644
index 000..3c6f0c0
--- /dev/null
+++ b/cpu/arm_cortexa8/mx51/clock.c
@@ -0,0 +1,293 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/errno.h
+#include asm/arch/imx-regs.h
+#include asm/arch/crm_regs.h
+
+enum pll_clocks {
+ PLL1_CLOCK = 0,
+ PLL2_CLOCK,
+ PLL3_CLOCK,
+ PLL_CLOCKS,
+};
+
+struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
+ [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
+ [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
+ [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
+};
+
+struct mxc_ccm_reg *mxc_ccm = MXC_CCM_BASE;
+
+/*
+ * Calculate the frequency of this pll.
+ */
+static u32 decode_pll(struct mxc_pll_reg *pll, u32 infreq)
+{
+ u32 mfi, mfn, mfd, pd;
+
+ mfn = __raw_readl(pll-mfn);
+ mfd = __raw_readl(pll-mfd) + 1;
+ mfi = __raw_readl(pll-op);
+ pd = (mfi 0xF) + 1;
+ mfi = (mfi 4) 0xF;
+ mfi = (mfi = 5) ? mfi : 5;
+
+ return ((4 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
+}
+
+/*
+ * Get mcu main rate
+ */
+u32 get_mcu_main_clk(void)
+{
+ u32 reg, freq;
+
+
[U-Boot] [PATCH V3 03/11] MX51: Add register definitions
The patch add header files to support the Freescale i.MX51
processor, setting definitions for internal registers.
Signed-off-by: Stefano Babic sba...@denx.de
Signed-off-by: Fred Fan fanyef...@gmail.com
---
include/asm-arm/arch-mx51/asm-offsets.h | 50 ++
include/asm-arm/arch-mx51/crm_regs.h| 192 +
include/asm-arm/arch-mx51/imx-regs.h| 282 +++
3 files changed, 524 insertions(+), 0 deletions(-)
create mode 100644 include/asm-arm/arch-mx51/asm-offsets.h
create mode 100644 include/asm-arm/arch-mx51/crm_regs.h
create mode 100644 include/asm-arm/arch-mx51/imx-regs.h
diff --git a/include/asm-arm/arch-mx51/asm-offsets.h
b/include/asm-arm/arch-mx51/asm-offsets.h
new file mode 100644
index 000..3a83fa0
--- /dev/null
+++ b/include/asm-arm/arch-mx51/asm-offsets.h
@@ -0,0 +1,50 @@
+/*
+ * needed for cpu/arm_cortexa8/mx51/lowlevel_init.S
+ *
+ * These should be auto-generated
+ */
+/* CCM */
+#define CLKCTL_CCR 0x00
+#define CLKCTL_CCDR 0x04
+#define CLKCTL_CSR 0x08
+#define CLKCTL_CCSR 0x0C
+#define CLKCTL_CACRR0x10
+#define CLKCTL_CBCDR0x14
+#define CLKCTL_CBCMR0x18
+#define CLKCTL_CSCMR1 0x1C
+#define CLKCTL_CSCMR2 0x20
+#define CLKCTL_CSCDR1 0x24
+#define CLKCTL_CS1CDR 0x28
+#define CLKCTL_CS2CDR 0x2C
+#define CLKCTL_CDCDR0x30
+#define CLKCTL_CHSCCDR 0x34
+#define CLKCTL_CSCDR2 0x38
+#define CLKCTL_CSCDR3 0x3C
+#define CLKCTL_CSCDR4 0x40
+#define CLKCTL_CWDR 0x44
+#define CLKCTL_CDHIPR 0x48
+#define CLKCTL_CDCR 0x4C
+#define CLKCTL_CTOR 0x50
+#define CLKCTL_CLPCR0x54
+#define CLKCTL_CISR 0x58
+#define CLKCTL_CIMR 0x5C
+#define CLKCTL_CCOSR0x60
+#define CLKCTL_CGPR 0x64
+#define CLKCTL_CCGR00x68
+#define CLKCTL_CCGR10x6C
+#define CLKCTL_CCGR20x70
+#define CLKCTL_CCGR30x74
+#define CLKCTL_CCGR40x78
+#define CLKCTL_CCGR50x7C
+#define CLKCTL_CCGR60x80
+#define CLKCTL_CMEOR0x84
+
+/* DPLL */
+#define PLL_DP_CTL 0x00
+#define PLL_DP_CONFIG 0x04
+#define PLL_DP_OP 0x08
+#define PLL_DP_MFD 0x0C
+#define PLL_DP_MFN 0x10
+#define PLL_DP_HFS_OP 0x1C
+#define PLL_DP_HFS_MFD 0x20
+#define PLL_DP_HFS_MFN 0x24
diff --git a/include/asm-arm/arch-mx51/crm_regs.h
b/include/asm-arm/arch-mx51/crm_regs.h
new file mode 100644
index 000..14aa231
--- /dev/null
+++ b/include/asm-arm/arch-mx51/crm_regs.h
@@ -0,0 +1,192 @@
+/*
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
+#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
+
+#define MXC_CCM_BASE CCM_BASE_ADDR
+
+/* DPLL register mapping structure */
+struct mxc_pll_reg {
+ u32 ctrl;
+ u32 config;
+ u32 op;
+ u32 mfd;
+ u32 mfn;
+ u32 mfn_minus;
+ u32 mfn_plus;
+ u32 hfs_op;
+ u32 hfs_mfd;
+ u32 hfs_mfn;
+ u32 mfn_togc;
+ u32 destat;
+};
+
+/* Register maping of CCM*/
+struct mxc_ccm_reg {
+ u32 ccr;/* 0x */
+ u32 ccdr;
+ u32 csr;
+ u32 ccsr;
+ u32 cacrr; /* 0x0010*/
+ u32 cbcdr;
+ u32 cbcmr;
+ u32 cscmr1;
+ u32 cscmr2; /* 0x0020 */
+ u32 cscdr1;
+ u32 cs1cdr;
+ u32 cs2cdr;
+ u32 cdcdr; /* 0x0030 */
+ u32 chscdr;
+ u32 cscdr2;
+ u32 cscdr3;
+ u32 cscdr4; /* 0x0040 */
+ u32 cwdr;
+ u32 cdhipr;
+ u32 cdcr;
+ u32 ctor; /* 0x0050 */
+ u32 clpcr;
+ u32 cisr;
+ u32 cimr;
+ u32 ccosr; /* 0x0060 */
+ u32 cgpr;
+ u32 CCGR0;
+ u32 CCGR1;
+ u32 CCGR2; /* 0x0070 */
+ u32 CCGR3;
+ u32 CCGR4;
+ u32 CCGR5;
+ u32 CCGR6; /* 0x0080 */
+ u32 cmeor;
+};
+
+/* Define the bits in register CACRR */
+#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
+#define
[U-Boot] [PATCH V3 04/11] MX51: Add pin and multiplexer definitions.
The patch add header files to support the pin multiplexer
of the the Freescale i.MX51 processor.
Signed-off-by: Stefano Babic sba...@denx.de
Signed-off-by: Fred Fan fanyef...@gmail.com
---
include/asm-arm/arch-mx51/iomux.h | 193 +
include/asm-arm/arch-mx51/mx51_pins.h | 374 +
2 files changed, 567 insertions(+), 0 deletions(-)
create mode 100644 include/asm-arm/arch-mx51/iomux.h
create mode 100644 include/asm-arm/arch-mx51/mx51_pins.h
diff --git a/include/asm-arm/arch-mx51/iomux.h
b/include/asm-arm/arch-mx51/iomux.h
new file mode 100644
index 000..a41c387
--- /dev/null
+++ b/include/asm-arm/arch-mx51/iomux.h
@@ -0,0 +1,193 @@
+/*
+ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MACH_MX51_IOMUX_H__
+#define __MACH_MX51_IOMUX_H__
+
+#include common.h
+#include asm/io.h
+#include asm/arch/imx-regs.h
+#include asm/arch/mx51_pins.h
+
+typedef unsigned int iomux_pin_name_t;
+
+/* various IOMUX output functions */
+typedef enum iomux_config {
+ IOMUX_CONFIG_ALT0, /*! used as alternate function 0 */
+ IOMUX_CONFIG_ALT1, /*! used as alternate function 1 */
+ IOMUX_CONFIG_ALT2, /*! used as alternate function 2 */
+ IOMUX_CONFIG_ALT3, /*! used as alternate function 3 */
+ IOMUX_CONFIG_ALT4, /*! used as alternate function 4 */
+ IOMUX_CONFIG_ALT5, /*! used as alternate function 5 */
+ IOMUX_CONFIG_ALT6, /*! used as alternate function 6 */
+ IOMUX_CONFIG_ALT7, /*! used as alternate function 7 */
+ IOMUX_CONFIG_GPIO, /*! added to help user use GPIO mode */
+ IOMUX_CONFIG_SION = 0x1 4, /*! used as LOOPBACK:MUX SION bit */
+} iomux_pin_cfg_t;
+
+/* various IOMUX pad functions */
+typedef enum iomux_pad_config {
+ PAD_CTL_SRE_SLOW = 0x0 0,/* Slow slew rate */
+ PAD_CTL_SRE_FAST = 0x1 0,/* Fast slew rate */
+ PAD_CTL_DRV_LOW = 0x0 1, /* Low drive strength */
+ PAD_CTL_DRV_MEDIUM = 0x1 1, /* Medium drive strength */
+ PAD_CTL_DRV_HIGH = 0x2 1,/* High drive strength */
+ PAD_CTL_DRV_MAX = 0x3 1, /* Max drive strength */
+ PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 3, /* Opendrain disable */
+ PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 3,/* Opendrain enable */
+ PAD_CTL_100K_PD = 0x0 4, /* 100Kohm pulldown */
+ PAD_CTL_47K_PU = 0x1 4, /* 47Kohm pullup */
+ PAD_CTL_100K_PU = 0x2 4, /* 100Kohm pullup */
+ PAD_CTL_22K_PU = 0x3 4, /* 22Kohm pullup */
+ PAD_CTL_PUE_KEEPER = 0x0 6, /* enable pulldown */
+ PAD_CTL_PUE_PULL = 0x1 6,/* enable pullup */
+ PAD_CTL_PKE_NONE = 0x0 7,/* Disable pullup/pulldown */
+ PAD_CTL_PKE_ENABLE = 0x1 7, /* Enable pullup/pulldown */
+ PAD_CTL_HYS_NONE = 0x0 8,/* Hysteresis disabled */
+ PAD_CTL_HYS_ENABLE = 0x1 8, /* Hysteresis enabled */
+ PAD_CTL_DDR_INPUT_CMOS = 0x0 9,/* DDR input CMOS */
+ PAD_CTL_DDR_INPUT_DDR = 0x1 9,/* DDR input DDR */
+ PAD_CTL_DRV_VOT_LOW = 0x0 13, /* Low voltage mode */
+ PAD_CTL_DRV_VOT_HIGH = 0x1 13,/* High voltage mode */
+} iomux_pad_config_t;
+
+/* various IOMUX input select register index */
+typedef enum iomux_input_select {
+ MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
+ MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
+ MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT,
+ MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT,
+
[U-Boot] [PATCH V3 05/11] serial_mxc: add support for MX51 processor
The patch adds support for the Freescale mx51 processor.
Signed-off-by: Stefano Babic sba...@denx.de
Signed-off-by: Fred Fan fanyef...@gmail.com
---
drivers/serial/serial_mxc.c | 18 --
1 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index acc5b7d..b21c9c3 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -49,8 +49,18 @@
#define UART_PHYS 0x1001b000
#elif defined(CONFIG_SYS_MX27_UART6)
#define UART_PHYS 0x1001c000
+#elif defined(CONFIG_SYS_MX51_UART1)
+#define UART_PHYS UART1_BASE_ADDR
+#elif defined(CONFIG_SYS_MX51_UART2)
+#define UART_PHYS UART2_BASE_ADDR
+#elif defined(CONFIG_SYS_MX51_UART3)
+#define UART_PHYS UART3_BASE_ADDR
#else
-#error define CONFIG_SYS_MX31_UARTx to use the mx31 UART driver
+#error define CONFIG_SYS_MXxx_UARTx to use the MXC UART driver
+#endif
+
+#ifdef CONFIG_SERIAL_MULTI
+#warning MXC driver does not support MULTI serials.
#endif
/* Register definitions */
@@ -166,11 +176,7 @@ DECLARE_GLOBAL_DATA_PTR;
void serial_setbrg (void)
{
-#ifdef CONFIG_MX31
- u32 clk = mx31_get_ipg_clk();
-#else
- u32 clk = imx_get_perclk1();
-#endif
+ u32 clk = imx_get_uartclk();
if (!gd-baudrate)
gd-baudrate = CONFIG_BAUDRATE;
--
1.6.3.3
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[U-Boot] [PATCH V3 06/11] mmc: check correctness of the voltage mask in ocr
Most cards do not answer if some reserved bits in the ocr are set. However, some controllers can set bit 7 (reserved for low voltages), but how to manage low voltages SD card is not yet specified. Signed-off-by: Stefano Babic sba...@denx.de --- drivers/mmc/mmc.c | 10 +- 1 files changed, 9 insertions(+), 1 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index b69ce15..d91b9b7 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -273,7 +273,15 @@ sd_send_op_cond(struct mmc *mmc) cmd.cmdidx = SD_CMD_APP_SEND_OP_COND; cmd.resp_type = MMC_RSP_R3; - cmd.cmdarg = mmc-voltages; + + /* +* Most cards do not answer if some reserved bits +* in the ocr are set. However, Some controller +* can set bit 7 (reserved for low voltages), but +* how to manage low voltages SD card is not yet +* specified. +*/ + cmd.cmdarg = mmc-voltages 0xff8000; if (mmc-version == SD_VERSION_2) cmd.cmdarg |= OCR_HCS; -- 1.6.3.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V3 08/11] MMC: add weak function to detect MMC/SD card
Most controllers can check if there is a card in the slot.
However, they require pins that could be not available because
required by other functions and the detection of a card must
be performed in another way. This patch adds a weak function
that a board can implement to add its internal custom way
to check the presence of a MMC/SD card.
Signed-off-by: Stefano Babic sba...@denx.de
---
drivers/mmc/mmc.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index d91b9b7..3679225 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -36,6 +36,13 @@
static struct list_head mmc_devices;
static int cur_dev_num = -1;
+int __board_mmc_getcd(u8 *cd, struct mmc *mmc) {
+ return -1;
+}
+
+int board_mmc_getcd(u8 *cd, struct mmc *mmc)__attribute__((weak,
+ alias(__board_mmc_getcd)));
+
int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
return mmc-send_cmd(mmc, cmd, data);
--
1.6.3.3
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[U-Boot] [PATCH V3 09/11] ARM/PPC: add a common way to access registers
Some Freescale's processors of different architecture have the same peripheral (eSDHC controller in PowerPC and i.MX51). This patch adds neutral functions to access to the internal registers of the SOCs that can be used by both architectures. Signed-off-by: Stefano Babic sba...@denx.de --- include/asm-arm/io.h | 39 +++ include/asm-ppc/io.h | 21 + 2 files changed, 60 insertions(+), 0 deletions(-) diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h index fec3a7e..d7d6f41 100644 --- a/include/asm-arm/io.h +++ b/include/asm-arm/io.h @@ -112,6 +112,45 @@ extern void __raw_readsl(unsigned int addr, void *data, int longlen); #define __raw_base_readw(base,off) __arch_base_getw(base,off) #define __raw_base_readl(base,off) __arch_base_getl(base,off) +/* Clear and set bits in one shot. These macros can be used to clear and + * set multiple bits in a register using a single call. These macros can + * also be used to set a multiple-bit bit pattern using a mask, by + * specifying the mask in the 'clear' parameter and the new bit pattern + * in the 'set' parameter. + */ + +#define clrbits(type, addr, clear) \ + write##type(__raw_read##type(addr) ~(clear), (addr)) + +#define setbits(type, addr, set) \ + write##type(__raw_read##type(addr) | (set), (addr)) + +#define clrsetbits(type, addr, clear, set) \ + write##type((__raw_read##type(addr) ~(clear)) | (set), (addr)) + +#define write_reg(type,a,v)write##type(v,a) +#define read_reg(type,a) __raw_read##type(a) + +#define write_reg32(a,v) write_reg(l,a,v) +#define write_reg16(a,v) write_reg(w,a,v) +#define write_reg8(a,v)write_reg(b,a,v) + +#define read_reg32(a) read_reg(l,a) +#define read_reg16(a) read_reg(w,a) +#define read_reg8(a) read_reg(b,a) + +#define clrbits_reg32(addr, clear) clrbits(l, addr, clear) +#define setbits_reg32(addr, set) setbits(l, addr, set) +#define clrsetbits_reg32(addr, clear, set) clrsetbits(l, addr, clear, set) + +#define clrbits_reg16(addr, clear) clrbits(w, addr, clear) +#define setbits_reg16(addr, set) setbits(w, addr, set) +#define clrsetbits_reg16(addr, clear, set) clrsetbits(w, addr, clear, set) + +#define clrbits_reg8(addr, clear) clrbits(b, addr, clear) +#define setbits_reg8(addr, set) setbits(b, addr, set) +#define clrsetbits_reg8(addr, clear, set) clrsetbits(b, addr, clear, set) + /* * Now, pick up the machine-defined IO definitions */ diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h index 4ddad26..d8f7cd7 100644 --- a/include/asm-ppc/io.h +++ b/include/asm-ppc/io.h @@ -242,6 +242,15 @@ extern inline void out_be32(volatile unsigned __iomem *addr, int val) __asm__ __volatile__(sync; stw%U0%X0 %1,%0 : =m (*addr) : r (val)); } +/* Define cross-platform function to access to registers */ + +#define write_reg32(a,v) out_be32(a,v) +#define write_reg16(a,v) out_be16(a,v) +#define write_reg8(a,v)out_be8(a,v) +#define read_reg32(a) in_be32(a) +#define read_reg16(a) in_be16(a) +#define read_reg8(a) in_be8(a) + /* Clear and set bits in one shot. These macros can be used to clear and * set multiple bits in a register using a single call. These macros can * also be used to set a multiple-bit bit pattern using a mask, by @@ -278,6 +287,18 @@ extern inline void out_be32(volatile unsigned __iomem *addr, int val) #define setbits_8(addr, set) setbits(8, addr, set) #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) +#define clrbits_reg32(addr, clear) clrbits(be32, addr, clear) +#define setbits_reg32(addr, set) setbits(be32, addr, set) +#define clrsetbits_reg32(addr, clear, set) clrsetbits(be32, addr, clear, set) + +#define clrbits_reg16(addr, clear) clrbits(be16, addr, clear) +#define setbits_reg16(addr, set) setbits(be16, addr, set) +#define clrsetbits_reg16(addr, clear, set) clrsetbits(be16, addr, clear, set) + +#define clrbits_reg8(addr, clear) clrbits(be8, addr, clear) +#define setbits_reg8(addr, set) setbits(be8, addr, set) +#define clrsetbits_reg8(addr, clear, set) clrsetbits(be8, addr, clear, set) + /* * Given a physical address and a length, return a virtual address * that can be used to access the memory range with the caching -- 1.6.3.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V3 10/11] fsl_esdhc: add support for mx51 processor
The esdhc controller in the mx51 processor is quite
the same as the one in some powerpc processors
(MPC83xx, MPC85xx). This patches adapts the driver
to support the arm mx51.
Signed-off-by: Stefano Babic sba...@denx.de
---
cpu/arm_cortexa8/mx51/Makefile |2 +-
cpu/arm_cortexa8/mx51/speed.c | 38 ++
drivers/mmc/fsl_esdhc.c| 147 ++-
include/asm-arm/global_data.h |3 +
include/fsl_esdhc.h| 11 +++-
lib_arm/board.c|3 +
6 files changed, 153 insertions(+), 51 deletions(-)
create mode 100644 cpu/arm_cortexa8/mx51/speed.c
diff --git a/cpu/arm_cortexa8/mx51/Makefile b/cpu/arm_cortexa8/mx51/Makefile
index 4d82293..7cfaa2c 100644
--- a/cpu/arm_cortexa8/mx51/Makefile
+++ b/cpu/arm_cortexa8/mx51/Makefile
@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).a
-COBJS = soc.o clock.o iomux.o timer.o
+COBJS = soc.o clock.o iomux.o timer.o speed.o
SOBJS = lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/cpu/arm_cortexa8/mx51/speed.c b/cpu/arm_cortexa8/mx51/speed.c
new file mode 100644
index 000..10acbbf
--- /dev/null
+++ b/cpu/arm_cortexa8/mx51/speed.c
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (tsi-chung.l...@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/arch/imx-regs.h
+
+int get_clocks(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_FSL_ESDHC
+ gd-sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK);
+#endif
+ return 0;
+}
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index c6e9e6e..112beb6 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -37,7 +37,6 @@
#include fdt_support.h
#include asm/io.h
-
DECLARE_GLOBAL_DATA_PTR;
struct fsl_esdhc {
@@ -102,7 +101,8 @@ static int esdhc_setup_data(struct mmc *mmc, struct
mmc_data *data)
{
uint wml_value;
int timeout;
- struct fsl_esdhc *regs = mmc-priv;
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc-priv;
+ struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg-esdhc_base;
wml_value = data-blocksize/4;
@@ -112,24 +112,24 @@ static int esdhc_setup_data(struct mmc *mmc, struct
mmc_data *data)
wml_value = 0x10 | wml_value;
- out_be32(regs-dsaddr, (u32)data-dest);
+ write_reg32(regs-dsaddr, (u32)data-dest);
} else {
if (wml_value 0x80)
wml_value = 0x80;
- if ((in_be32(regs-prsstat) PRSSTAT_WPSPL) == 0) {
+ if ((read_reg32(regs-prsstat) PRSSTAT_WPSPL) == 0) {
printf(\nThe SD card is locked. Can not write to a
locked card.\n\n);
return TIMEOUT;
}
wml_value = wml_value 16 | 0x10;
- out_be32(regs-dsaddr, (u32)data-src);
+ write_reg32(regs-dsaddr, (u32)data-src);
}
- out_be32(regs-wml, wml_value);
+ write_reg32(regs-wml, wml_value);
- out_be32(regs-blkattr, data-blocks 16 | data-blocksize);
+ write_reg32(regs-blkattr, data-blocks 16 | data-blocksize);
/* Calculate the timeout period for data transactions */
- timeout = __ilog2(mmc-tran_speed/10);
+ timeout = fls(mmc-tran_speed/10) - 1;
timeout -= 13;
if (timeout 14)
@@ -138,7 +138,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct
mmc_data *data)
if (timeout 0)
timeout = 0;
- clrsetbits_be32(regs-sysctl, SYSCTL_TIMEOUT_MASK, timeout 16);
+ clrsetbits_reg32(regs-sysctl, SYSCTL_TIMEOUT_MASK, timeout 16);
return 0;
}
@@ -153,17 +153,20 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
uintxfertyp;
uintirqstat;
- volatile struct fsl_esdhc *regs = mmc-priv;
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc-priv;
+ volatile struct fsl_esdhc *regs = (struct fsl_esdhc
[U-Boot] [PATCH V3 11/11] Add initial support for Freescale mx51evk board
The patch adds initial support for the Freescale mx51evk board.
Network (FEC) and SD controller (fsl_esdhc) are supported.
Signed-off-by: Stefano Babic sba...@denx.de
Signed-off-by: Fred Fan fanyef...@gmail.com
---
MAINTAINERS |4 +
MAKEALL |1 +
Makefile |4 +
board/freescale/mx51evk/Makefile | 48
board/freescale/mx51evk/config.mk| 25 ++
board/freescale/mx51evk/imximage.cfg | 119 ++
board/freescale/mx51evk/mx51evk.c| 418 ++
board/freescale/mx51evk/mx51evk.h| 51
include/configs/mx51evk.h| 173 ++
9 files changed, 843 insertions(+), 0 deletions(-)
create mode 100644 board/freescale/mx51evk/Makefile
create mode 100644 board/freescale/mx51evk/config.mk
create mode 100644 board/freescale/mx51evk/imximage.cfg
create mode 100644 board/freescale/mx51evk/mx51evk.c
create mode 100644 board/freescale/mx51evk/mx51evk.h
create mode 100644 include/configs/mx51evk.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 9734b1d..8637550 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -151,6 +151,10 @@ Dave Ellis d...@sixnetio.com
SXNI855TMPC8xx
+Fred Fan fanyef...@gmail.com
+
+ mx51evk i.MX51
+
Thomas Frieden thom...@hyperion-entertainment.com
AmigaOneG3SEMPC7xx
diff --git a/MAKEALL b/MAKEALL
index ab1bb6f..485107a 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -617,6 +617,7 @@ LIST_ARM11=\
#
LIST_ARM_CORTEX_A8= \
devkit8000 \
+ mx51evk \
omap3_beagle\
omap3_overo \
omap3_evm \
diff --git a/Makefile b/Makefile
index 365f87f..01bf9a2 100644
--- a/Makefile
+++ b/Makefile
@@ -3267,6 +3267,9 @@ mx31pdk_nand_config : unconfig
fi
@$(MKCONFIG) -a mx31pdk arm arm1136 mx31pdk freescale mx31
+mx51evk_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx51evk freescale mx51
+
omap2420h4_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 ti omap24xx
@@ -3733,6 +3736,7 @@ clobber: clean
$(obj)cscope.* $(obj)*.*~
@rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL)
@rm -f $(obj)u-boot.kwb
+ @rm -f $(obj)u-boot.imx
@rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes}
@rm -f $(obj)cpu/mpc824x/bedbug_603e.c
@rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
diff --git a/board/freescale/mx51evk/Makefile b/board/freescale/mx51evk/Makefile
new file mode 100644
index 000..eb12fc5
--- /dev/null
+++ b/board/freescale/mx51evk/Makefile
@@ -0,0 +1,48 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski l...@denx.de
+#
+# (C) Copyright 2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).a
+
+COBJS := mx51evk.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/freescale/mx51evk/config.mk
b/board/freescale/mx51evk/config.mk
new file mode 100644
index 000..c8279ec
--- /dev/null
+++ b/board/freescale/mx51evk/config.mk
@@ -0,0 +1,25 @@
+#
+# Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in
Re: [U-Boot] [STATUS] Merge Window closed, waiting for pull requests
On 19.01.2010 23:30, Wolfgang Denk wrote: Hi as you probably have noticed, the merge window closed about 24 hours ago. Checking my list, I still see s _long_ list of ARM related patches that have not been processed yet. For many of them I haven't seen any review comments, nor have architecture maintainer picked these up and sent pull requests to Tom. Can you please try and work on this now, so that we can have the outstanding patches integrated into mainline in the next few days? I'd like to see the Beagle rev C4 patches applied: http://lists.denx.de/pipermail/u-boot/2010-January/066629.html http://lists.denx.de/pipermail/u-boot/2010-January/066632.html http://lists.denx.de/pipermail/u-boot/2010-January/066634.html http://lists.denx.de/pipermail/u-boot/2010-January/066636.html http://lists.denx.de/pipermail/u-boot/2010-January/066638.html http://lists.denx.de/pipermail/u-boot/2010-January/066640.html http://lists.denx.de/pipermail/u-boot/2010-January/066642.html (The ml archive seems to have some issues with these patches. In my inbox they seem to be fine, though) Thanks and best regards Dirk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] turning off interactive mode...
Hi list. I did a search and I must be completely missing the point. I want to build a released version of u-boot on my system. If I set the bootdely=0 and set a bootcmd does this prevent someone from hitting a key really quick and disrupting the boot? By reading the documentation, I'm pretty sure that's how one does it but can I get some confirmation. Thanks. -stv -- /* * Steve Iribarne * Software Engineer * (aka Grunt) */ ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [STATUS] Merge Window closed, waiting for pull requests
Subject: Re: [U-Boot] [STATUS] Merge Window closed, waiting for pull requests On 19.01.2010 23:30, Wolfgang Denk wrote: Hi as you probably have noticed, the merge window closed about 24 hours ago. Checking my list, I still see s _long_ list of ARM related patches that have not been processed yet. For many of them I haven't seen any review comments, nor have architecture maintainer picked these up and sent pull requests to Tom. Can you please try and work on this now, so that we can have the outstanding patches integrated into mainline in the next few days? I'd like to see the Beagle rev C4 patches applied: http://lists.denx.de/pipermail/u-boot/2010-January/066629.html http://lists.denx.de/pipermail/u-boot/2010-January/066632.html http://lists.denx.de/pipermail/u-boot/2010-January/066634.html http://lists.denx.de/pipermail/u-boot/2010-January/066636.html http://lists.denx.de/pipermail/u-boot/2010-January/066638.html http://lists.denx.de/pipermail/u-boot/2010-January/066640.html http://lists.denx.de/pipermail/u-boot/2010-January/066642.html (The ml archive seems to have some issues with these patches. In my inbox they seem to be fine, though) Same with me but when I discussed offline with Tom, it appears as if this set never made it to his Inbox. We need just a little more time. Thanks and best regards Dirk Sandeep ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Adding EP2500 MCF5282 board [PATCH] -- resent in git format
Mercury-EP2500.patch - added Mercury's EP2500 board uses the mcf5282 processor CREDITS.patch Signed-off-by: David Wu davi...@arcturusnetworks.com Signed-off-by: Michael Durrant mdurr...@arcturusnetworks.com --- CREDITS|5 + Makefile |3 +++ cpu/mcf52x2/cpu_init.c | 11 +++ 3 files changed, 19 insertions(+), 0 deletions(-) diff --git a/CREDITS b/CREDITS index 2471029..043ba6e 100644 --- a/CREDITS +++ b/CREDITS @@ -511,6 +511,11 @@ N: Martin Winistoerfer E: martinwinistoer...@gmx.ch D: Port to MPC555/556 microcontrollers and support for cmi board +N: David Wu +E: supp...@arcturusnetworks.com +D: Mercury Security EP2500 +W: http://www.arcturusnetworks.com + N: Ming-Len Wu E: minglen...@techware.com.tw D: Motorola MX1ADS board support diff --git a/Makefile b/Makefile index 1ab197b..9de721b 100644 --- a/Makefile +++ b/Makefile @@ -2062,6 +2062,9 @@ EB+MCF-EV123_internal_config :unconfig @echo TEXT_BASE = 0xF000|tee $(obj)board/BuS/EB+MCF-EV123/textbase.mk @$(MKCONFIG) EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS +EP2500_config:unconfig +@$(MKCONFIG) $(@:_config=) m68k mcf52x2 ep2500 Mercury + idmr_config :unconfig @$(MKCONFIG) $(@:_config=) m68k mcf52x2 idmr diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c index 7cea655..5b06930 100644 --- a/cpu/mcf52x2/cpu_init.c +++ b/cpu/mcf52x2/cpu_init.c @@ -5,6 +5,8 @@ * MCF5282 additionals * (C) Copyright 2005 * BuS Elektronik GmbH Co. KG e...@bus-elektronik.de + * (c) Copyright 2010 + * Arcturus Networks Inc. www.arcturusnetworks.com * * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. * TsiChung Liew (tsi-chung.l...@freescale.com) @@ -582,6 +584,12 @@ void cpu_init_f(void) #ifdef CONFIG_SYS_PTCPAR MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR; #endif +#if defined(CONFIG_SYS_PORTTC) +MCFGPIO_PORTTC = CONFIG_SYS_PORTTC; +#endif +#if defined(CONFIG_SYS_DDRTC) +MCFGPIO_DDRTC = CONFIG_SYS_DDRTC; +#endif #ifdef CONFIG_SYS_PTDPAR MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR; #endif @@ -589,6 +597,9 @@ void cpu_init_f(void) MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR; #endif +#if defined(CONFIG_SYS_DDRD) +MCFGPIO_DDRD = CONFIG_SYS_DDRD; +#endif #ifdef CONFIG_SYS_DDRUA MCFGPIO_DDRUA = CONFIG_SYS_DDRUA; #endif -- 1.4.3.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ColdFire I2C implementing I2C idle [PATCH] -- resent in git format
drivers_i2c_fsl_i2c.patch
- need to set I2C to be idle according to the MCF5282 user's manual
If I2SR[IBB] is set when the I2C bus module is enabled,
execute the following code sequence before proceeding with
normal initialization code. This issues a STOP command to the
slave device, placing it in idle state as if it were just
power-cycled on.
I2CR = 0x0
I2CR = 0xA
dummy read of I2DR
I2SR = 0x0
I2CR = 0x0
Signed-off-by: David Wu davi...@arcturusnetworks.com
Signed-off-by: Michael Durrant mdurr...@arcturusnetworks.com
---
drivers/i2c/fsl_i2c.c | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index 2241990..bce750c 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -251,12 +251,25 @@ i2c_init(int speed, int slaveadd)
#endif
}
+static __inline__ int i2c_set_idle(void)
+{
+writeb(0, i2c_dev[i2c_bus_num]-cr);
+writeb(I2C_CR_MEN | I2C_CR_MSTA, i2c_dev[i2c_bus_num]-cr);
+readb(i2c_dev[i2c_bus_num]-dr);
+writeb(0, i2c_dev[i2c_bus_num]-sr);
+writeb(0, i2c_dev[i2c_bus_num]-cr);
+writeb(I2C_CR_MEN, i2c_dev[i2c_bus_num]-cr);
+}
+
static int
i2c_wait4bus(void)
{
unsigned long long timeval = get_ticks();
const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
+if (readb(i2c_dev[i2c_bus_num]-sr) I2C_SR_MBB)
+i2c_set_idle();
+
while (readb(i2c_dev[i2c_bus_num]-sr) I2C_SR_MBB) {
if ((get_ticks() - timeval) timeout)
return -1;
-- 1.4.3.4
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Re: [U-Boot] ColdFire/M68K board.c initialization / order matters [PATCH] -- resent in git format
lib_m68k_board.patch - eth_init() requires eth_current which is initialized in eth_initialize() so eth_initialize (bd) should be called first then eth_init(bd) Signed-off-by: David Wu davi...@arcturusnetworks.com Signed-off-by: Michael Durrant mdurr...@arcturusnetworks.com --- lib_m68k/board.c |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/lib_m68k/board.c b/lib_m68k/board.c index 732023d..c17394b 100644 --- a/lib_m68k/board.c +++ b/lib_m68k/board.c @@ -639,13 +639,13 @@ void board_init_r (gd_t *id, ulong dest_ #endif #if defined(CONFIG_CMD_NET) WATCHDOG_RESET(); -#if defined(FEC_ENET) -eth_init(bd); -#endif #if defined(CONFIG_NET_MULTI) puts (Net: ); eth_initialize (bd); #endif +#if defined(FEC_ENET) +eth_init(bd); +#endif #endif #ifdef CONFIG_POST -- 1.4.3.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] MCF528x cache errata / fix [PATCH] -- resent in git format
cpu_mcf52x2_cache.patch - Setup CACR, bit 5 set to 0 per Freescale chip errata (MCF5282DE, Rev. 6, 5/2009) Signed-off-by: David Wu davi...@arcturusnetworks.com Signed-off-by: Michael Durrant mdurr...@arcturusnetworks.com --- cpu/mcf52x2/cpu_init.c |6 -- cpu/mcf52x2/start.S|5 - 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c index 5b06930..60b55ce 100644 --- a/cpu/mcf52x2/cpu_init.c +++ b/cpu/mcf52x2/cpu_init.c @@ -609,8 +609,10 @@ void cpu_init_f(void) #endif/* CONFIG_MONITOR_IS_IN_RAM */ -/* defer enabling cache until boot (see do_go) */ -/* icache_enable(); */ +#if defined(CONFIG_SYS_ENABLE_ICACHE) +/* enable instruction cache now */ +icache_enable(); +#endif } /* diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S index 0dd4de5..5540c95 100644 --- a/cpu/mcf52x2/start.S +++ b/cpu/mcf52x2/start.S @@ -417,7 +417,10 @@ icache_enable: movec%d0, %ACR0/* Enable cache */ move.l#0xff00c000, %d0/* Setup cache mask */ movec%d0, %ACR1/* Enable cache */ -move.l#0x80400100, %d0/* Setup cache mask, data cache disabel*/ +move.l#0x8040, %d0/* Setup cache mask, data cache disabled, + bit 5 set to 0 per chip errata + (MCF5282DE, Rev. 6, 5/2009) + */ movec%d0, %CACR/* Enable cache */ moveq#1, %d0 icache_state_access_1: -- 1.4.3.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [STATUS] Merge Window closed, waiting for pull requests
On 20.01.2010 18:58, Paulraj, Sandeep wrote: Subject: Re: [U-Boot] [STATUS] Merge Window closed, waiting for pull requests On 19.01.2010 23:30, Wolfgang Denk wrote: Hi as you probably have noticed, the merge window closed about 24 hours ago. Checking my list, I still see s _long_ list of ARM related patches that have not been processed yet. For many of them I haven't seen any review comments, nor have architecture maintainer picked these up and sent pull requests to Tom. Can you please try and work on this now, so that we can have the outstanding patches integrated into mainline in the next few days? I'd like to see the Beagle rev C4 patches applied: http://lists.denx.de/pipermail/u-boot/2010-January/066629.html http://lists.denx.de/pipermail/u-boot/2010-January/066632.html http://lists.denx.de/pipermail/u-boot/2010-January/066634.html http://lists.denx.de/pipermail/u-boot/2010-January/066636.html http://lists.denx.de/pipermail/u-boot/2010-January/066638.html http://lists.denx.de/pipermail/u-boot/2010-January/066640.html http://lists.denx.de/pipermail/u-boot/2010-January/066642.html (The ml archive seems to have some issues with these patches. In my inbox they seem to be fine, though) Same with me but when I discussed offline with Tom, it appears as if this set never made it to his Inbox. We need just a little more time. Time for what? Let us know if we can help with something! Best regards Dirk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH-V2 4/9] Nand mxc_nand add v1.1 controller support
Scott, Scott Wood skrev: On Sat, Jan 16, 2010 at 09:50:22PM -0700, John Rigby wrote: Add support for version 1.1 of the nfc nand flash controller which is on the i.mx25 soc. Use CONFIG_NAND_MXC_V1 and CONFIG_NAND_MXC_V1_1 to differentiate between the two supported versions. Add a define CONFIG_NAND_MXC_V1 to imx27lite board config. Also factor out some soc specific nand geometry config into a new inline routine and a couple of defines: mxc_get_nfc_info IMX_NFC_IS_16BIT IMX_NFC_IS_2KPAGE Added to imx-regs.h. Signed-off-by: John Rigby jcri...@gmail.com Earlier-version-signed-off-by: Wolfgang Denk w...@denx.de CC: Scott Wood scottw...@freescale.com CC: Fred Fan fanyef...@gmail.com --- The 16-bit detection conflicts with http://lists.denx.de/pipermail/u-boot/2009-November/064139.html Which way should I resolve the conflict? Or does one of you want to respin? I don't see 16BIT/2KPAGE/get_nfc_info defined for MX31... and does MX25 share MX27's imx-regs.h? Magnus, can you test this patch on MX31? I've now tested the patch and after adding an imx-regs.h for MX31 with the needed information the patch seems to work on i.MX31. Tested on the Litekit board with a small page NAND mounted. A comment for John Rigby on the patch though: Is it really necessary to specify the version of the NAND controller in the board configuration file? As far as I know, once you select which i.MX-device to use U-boot already has the necessary information to derive the version of the NAND FC automatically. Regards, Magnus ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Profiling uboot
Dear Ira W. Snyder, In message 20100120162647.gb4...@ovro.caltech.edu you wrote: I've used the attached ptx_ts script to measure U-Boot. It probably came from this mailing list at some point. Yeah, that's the perl version modeled after our good old expect script. Functionally equivalent. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de It became apparent that one reason why the Ice Giants were known as the Ice Giants was because they were, well, giants. The other was that they were made of ice. -Terry Pratchett, _Sourcery_ ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] turning off interactive mode...
Dear Steve Iribarne (GMail), In message b4b98b691001200957k7563b6a4x5f3b973cb80cc...@mail.gmail.com you wrote: I did a search and I must be completely missing the point. I want to build a released version of u-boot on my system. If I set the bootdely=0 and set a bootcmd does this prevent someone from hitting a key really quick and disrupting the boot? bootdelay = -1 By reading the documentation, I'm pretty sure that's how one does it but can I get some confirmation. Behaviour also depends on hardware and configuration - see for example CONFIG_ZERO_BOOTDELAY_CHECK Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de If I ever needed a brain transplant, I'd choose a teenager's because I'd want a brain that had never been used. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH-V2 4/9] Nand mxc_nand add v1.1 controller support
A comment for John Rigby on the patch though: Is it really necessary to specify the version of the NAND controller in the board configuration file? As far as I know, once you select which i.MX-device to use U-boot already has the necessary information to derive the version of the NAND FC automatically. We can determing nfc version for mxc version so I guess if we are going to leave mxc version ifdefs in the driver then the nfc versioning in the board configs makes no sense. Regards, Magnus ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ColdFire/M68K board.c initialization / order matters [PATCH] -- resent in git format
Hi Michael, Michael Durrant wrote: lib_m68k_board.patch - eth_init() requires eth_current which is initialized in eth_initialize() so eth_initialize (bd) should be called first then eth_init(bd) Actually, eth_init() shouldn't be called in board.c at all. regards, Ben ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ColdFire/M68K board.c initialization / order matters [PATCH] -- resent in git format
Ben Warren wrote: Hi Michael, Michael Durrant wrote: lib_m68k_board.patch - eth_init() requires eth_current which is initialized in eth_initialize() so eth_initialize (bd) should be called first then eth_init(bd) Actually, eth_init() shouldn't be called in board.c at all. Ok. I am open to suggestions here. Here is our rational for the change. We moved the eth_init() previously before eth_initialize (bd) to after as the eth_initialize over writes the current pointer. Our usage case is to ensure the Ethernet MAC address is retrieved from the eeprom and is used to initialized into the FEC registers in the MCF5282 before executing the customers application code. Since MAC initialization normally only happens when u-boot makes use of the Ethernet for network services such as ping or tftp we saw using eth_init() in board.c as an easy way to ensure the FEC registers are set up. Regards, Michael Durrant regards, Ben ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ColdFire/M68K board.c initialization / order matters [PATCH] -- resent in git format
Michael Durrant wrote: Ben Warren wrote: Hi Michael, Michael Durrant wrote: lib_m68k_board.patch - eth_init() requires eth_current which is initialized in eth_initialize() so eth_initialize (bd) should be called first then eth_init(bd) Actually, eth_init() shouldn't be called in board.c at all. Ok. I am open to suggestions here. Here is our rational for the change. We moved the eth_init() previously before eth_initialize (bd) to after as the eth_initialize over writes the current pointer. Our usage case is to ensure the Ethernet MAC address is retrieved from the eeprom and is used to initialized into the FEC registers in the MCF5282 before executing the customers application code. Since MAC initialization normally only happens when u-boot makes use of the Ethernet for network services such as ping or tftp we saw using eth_init() in board.c as an easy way to ensure the FEC registers are set up. U-boot policy is that unused hardware is also un-initialized. In your instance, if you're not going to use the network controller in U-boot, you don't get to program its MAC address. You'll find this has been discussed ad nauseum on this mailing list. Your options are to either use the FEC or read the EEPROM in the customer application. Regards, Michael Durrant regards, Ben ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] 85xx/eSDHC: fix eSDHC clock frequency mask
The default value of the prescaler of eSDHC clock frequency is 0x80, so we need to mask the MSB to set a different clock, or else it maybe make the behavior of this prescaler undefined. Signed-off-by: Mingkai Hu mingkai...@freescale.com --- include/fsl_esdhc.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 89b8304..eac6a2b 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -32,7 +32,7 @@ #define SYSCTL 0x0002e02c #define SYSCTL_INITA 0x0800 #define SYSCTL_TIMEOUT_MASK0x000f -#define SYSCTL_CLOCK_MASK 0x0fff +#define SYSCTL_CLOCK_MASK 0xfff0 #define SYSCTL_PEREN 0x0004 #define SYSCTL_HCKEN 0x0002 #define SYSCTL_IPGEN 0x0001 -- 1.6.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] 85xx/eSDHC: fix eSDHC clock frequency mask
The default value of the prescaler of eSDHC clock frequency is 0x80, so we need to mask the MSB to set a different clock, or else it maybe make the behavior of this prescaler undefined. Signed-off-by: Mingkai Hu mingkai...@freescale.com --- include/fsl_esdhc.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 89b8304..eac6a2b 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -32,7 +32,7 @@ #define SYSCTL 0x0002e02c #define SYSCTL_INITA 0x0800 #define SYSCTL_TIMEOUT_MASK 0x000f -#define SYSCTL_CLOCK_MASK0x0fff +#define SYSCTL_CLOCK_MASK0xfff0 #define SYSCTL_PEREN 0x0004 #define SYSCTL_HCKEN 0x0002 #define SYSCTL_IPGEN 0x0001 The patch is duplicated one from Leo. http://lists.denx.de/pipermail/u-boot/2010-January/066024.html Thanks, Dave ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [STATUS] Merge Window closed, waiting for pull requests
On Wednesday 20 January 2010 07:58:17 Wolfgang Denk wrote: Mike Frysinger wrote: did you see my pull request for kgdb patches from the Blackfin tree ? I did. Do you think anything is missing in current mainline? the latest master in your tree doesnt contain the two Blackfin kgdb patches which is why i asked also, should i collect my misc smallish patches that saw no feedback in a tree for you ? That would be really nice - but then, I don't think there are any patches outstanding that are not architecture-specific and therefore have to go through the respective custodians? Please post a list of patches you think missing. flash.h: pull in common.h for types bootm: allow people to disable this command Blackfin: disable NetBSD bootm support by default sha1: add dedicated config option gzip/zlib: make features optional lmb: only force on arches that use it -mike signature.asc Description: This is a digitally signed message part. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ColdFire I2C implementing I2C idle [PATCH] -- resent in git format
Hello Michael,
Thanks for posting your patches in plain text.
Michael Durrant wrote:
drivers_i2c_fsl_i2c.patch
- need to set I2C to be idle according to the MCF5282 user's manual
If I2SR[IBB] is set when the I2C bus module is enabled,
execute the following code sequence before proceeding with
normal initialization code. This issues a STOP command to the
slave device, placing it in idle state as if it were just
power-cycled on.
I2CR = 0x0
I2CR = 0xA
dummy read of I2DR
I2SR = 0x0
I2CR = 0x0
Signed-off-by: David Wu davi...@arcturusnetworks.com
Signed-off-by: Michael Durrant mdurr...@arcturusnetworks.com
---
drivers/i2c/fsl_i2c.c | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index 2241990..bce750c 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -251,12 +251,25 @@ i2c_init(int speed, int slaveadd)
#endif
}
+static __inline__ int i2c_set_idle(void)
+{
+writeb(0, i2c_dev[i2c_bus_num]-cr);
+writeb(I2C_CR_MEN | I2C_CR_MSTA, i2c_dev[i2c_bus_num]-cr);
+readb(i2c_dev[i2c_bus_num]-dr);
+writeb(0, i2c_dev[i2c_bus_num]-sr);
+writeb(0, i2c_dev[i2c_bus_num]-cr);
+writeb(I2C_CR_MEN, i2c_dev[i2c_bus_num]-cr);
+}
+
static int
i2c_wait4bus(void)
{
unsigned long long timeval = get_ticks();
const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
+if (readb(i2c_dev[i2c_bus_num]-sr) I2C_SR_MBB)
+i2c_set_idle();
+
while (readb(i2c_dev[i2c_bus_num]-sr) I2C_SR_MBB) {
if ((get_ticks() - timeval) timeout)
return -1;
Hmm.. I can;t find this for example in the MPC8360ERM.pdf, which
uses also this driver ... So I vote for activating this only,
if this driver is used for __M68K__ ...
Also, you write, that this sequence is necessary before normal
initialization code, but i2c_wait4bus() is called from i2c_read()
and i2c_write(), so the I2C bus is long ago initialized ...
or what do you mean with normal initialization code ?
Also, whats with multimaster systems? Your code maybe cuts a running
data transmission. The MPC8360ERM.pdf manual says check the MBB bit,
if the bus is free, before switching to master mode, thats what
actual code did ... so, I want this only activated, if __M68K__
is defined ...
bye
Heiko
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Re: [U-Boot] [PATCH] ppc4xx: Fix reporting of bootstrap options G and F on 460EX/GT
On Tuesday 19 January 2010 16:37:13 Felix Radensky wrote: Bootstrap options G and F are reported incorrectly (G instead of F and vice versa). This patch fixes this. Applied to u-boot-ppc4xx/master. Thanks. Cheers, Stefan -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: off...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ppc4xx: Allow setting a single SPD EEPROM address for DDR2 DIMMs
On Tuesday 19 January 2010 20:19:06 Felix Radensky wrote: On platforms where SPD EEPROM and another EEPROM have adjacent I2C addresses SPD_EEPROM_ADDRESS should be defined as a single element array, otherwise DDR2 setup code would fail with the following error: ERROR: Unknown DIMM detected in slot 1 However, fixing SPD_EEPROM_ADDRESS would result in another error: ERROR: DIMM's DDR1 and DDR2 type can not be mixed. This happens because initdram() routine does not explicitly initialize dimm_populated array. This patch fixes the problem. Applied to u-boot-ppc4xx/master. Thanks. Cheers, Stefan -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: off...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ColdFire I2C implementing I2C idle [PATCH] -- resent in git format
Hello Michael,
Thanks for posting your patches in plain text.
Michael Durrant wrote:
drivers_i2c_fsl_i2c.patch
- need to set I2C to be idle according to the MCF5282 user's manual
If I2SR[IBB] is set when the I2C bus module is enabled,
execute the following code sequence before proceeding with
normal initialization code. This issues a STOP command to the
slave device, placing it in idle state as if it were just
power-cycled on.
I2CR = 0x0
I2CR = 0xA
dummy read of I2DR
I2SR = 0x0
I2CR = 0x0
Signed-off-by: David Wu davi...@arcturusnetworks.com
Signed-off-by: Michael Durrant mdurr...@arcturusnetworks.com
---
drivers/i2c/fsl_i2c.c | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index 2241990..bce750c 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -251,12 +251,25 @@ i2c_init(int speed, int slaveadd)
#endif
}
+static __inline__ int i2c_set_idle(void)
+{
+writeb(0, i2c_dev[i2c_bus_num]-cr);
+writeb(I2C_CR_MEN | I2C_CR_MSTA, i2c_dev[i2c_bus_num]-cr);
+readb(i2c_dev[i2c_bus_num]-dr);
+writeb(0, i2c_dev[i2c_bus_num]-sr);
+writeb(0, i2c_dev[i2c_bus_num]-cr);
+writeb(I2C_CR_MEN, i2c_dev[i2c_bus_num]-cr);
+}
+
static int
i2c_wait4bus(void)
{
unsigned long long timeval = get_ticks();
const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
+if (readb(i2c_dev[i2c_bus_num]-sr) I2C_SR_MBB)
+i2c_set_idle();
+
while (readb(i2c_dev[i2c_bus_num]-sr) I2C_SR_MBB) {
if ((get_ticks() - timeval) timeout)
return -1;
Hmm.. I can;t find this for example in the MPC8360ERM.pdf, which
uses also this driver ... So I vote for activating this only,
if this driver is used for __M68K__ ...
Also, you write, that this sequence is necessary before normal
initialization code, but i2c_wait4bus() is called from i2c_read()
and i2c_write(), so the I2C bus is long ago initialized ...
or what do you mean with normal initialization code ?
Also, whats with multimaster systems? Your code maybe cuts a running
data transmission. The MPC8360ERM.pdf manual says check the MBB bit,
if the bus is free, before switching to master mode, thats what
actual code did ... so, I want this only activated, if __M68K__
is defined ...
All true. This cannot go in as is. What you need is a I2C reset sequence
as the above isn't enough in the general case. Michael, have a look at the
kernel driver, it has some fixup code you could borrow.
Jocke
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[U-Boot] Please pull u-boot-ppc4xx/master
The following changes since commit 50ef25ef24eccd8e69d2c1ccc97b3f7e30109f51: Michal Simek (1): microblaze: zlib needs asm/unaligned.h are available in the git repository at: git://www.denx.de/git/u-boot-ppc4xx.git master Felix Radensky (2): ppc4xx: Fix reporting of bootstrap options G and F on 460EX/GT ppc4xx: Allow setting a single SPD EEPROM address for DDR2 DIMMs cpu/ppc4xx/44x_spd_ddr2.c |2 +- cpu/ppc4xx/cpu.c |2 +- 2 files changed, 2 insertions(+), 2 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
