Re: [U-Boot] [PATCH] fsl-ddr: Fix the turnaround timing for TIMING_CFG_4
> Read-to-read/Write-to-write turnaround for same chip select > of DDR3 memory, BL/2+2 cycles is enough for these turnarounds. > Cutting down the turnaround from BL/2+4 to BL/2+2 will improve > the memory performance. Please ignore this patch, I will provide one better solution to address this performance issue. Thanks, Dave ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1 1/2] fsl-ddr: Fix the turnaround timing for TIMING_CFG_4
Read-to-read/Write-to-write turnaround for same chip select
of DDR3 memory, BL/2+2 cycles is enough for them at BC4 and
OTF case, BL/2 cycles is enough for fixed BL8.
Cutting down the turnaround from BL/2+4 to BL/2+2 or BL/2
will improve the memory performance.
Signed-off-by: Dave Liu
---
cpu/mpc8xxx/ddr/ctrl_regs.c | 17 -
1 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index 73f349f..aeb54c3 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -939,7 +939,8 @@ static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
}
/* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
-static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr)
+static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts)
{
unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
@@ -948,9 +949,15 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr)
unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
#if defined(CONFIG_FSL_DDR3)
- /* We need set BL/2 + 4 for BC4 or OTF */
- rrt = 4;/* BL/2 + 4 clocks */
- wwt = 4;/* BL/2 + 4 clocks */
+ if (popts->burst_length == DDR_BL8) {
+ /* We set BL/2 for fixed BL8 */
+ rrt = 0;/* BL/2 clocks */
+ wwt = 0;/* BL/2 clocks */
+ } else {
+ /* We need to set BL/2 + 2 to BC4 and OTF */
+ rrt = 2;/* BL/2 + 2 clocks */
+ wwt = 2;/* BL/2 + 2 clocks */
+ }
dll_lock = 1; /* tDLLK = 512 clocks from spec */
#endif
ddr->timing_cfg_4 = (0
@@ -1348,7 +1355,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t
*popts,
set_ddr_sdram_clk_cntl(ddr, popts);
set_ddr_init_addr(ddr);
set_ddr_init_ext_addr(ddr);
- set_timing_cfg_4(ddr);
+ set_timing_cfg_4(ddr, popts);
set_timing_cfg_5(ddr);
set_ddr_zq_cntl(ddr, zq_en);
--
1.6.4
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[U-Boot] [PATCH v1 2/2] fsl-ddr: change the default burst mode for DDR3
For 64B cacheline SoC, set the fixed 8-beat burst len, for 32B cacheline SoC, set the On-The-Fly as default. Signed-off-by: Dave Liu --- should go to B2.0.3 release. cpu/mpc8xxx/ddr/options.c |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c index 105e758..0a6169a 100644 --- a/cpu/mpc8xxx/ddr/options.c +++ b/cpu/mpc8xxx/ddr/options.c @@ -110,8 +110,13 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, /* Choose burst length. */ #if defined(CONFIG_FSL_DDR3) +#if defined(CONFIG_E500MC) + popts->OTF_burst_chop_en = 0; /* on-the-fly burst chop disable */ + popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */ +#else popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */ popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */ +#endif #else popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */ #endif -- 1.6.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V4 09/11] ARM/PPC: add a common way to access registers
Wolfgang Denk wrote: > I like this approach better than the precious one. > > However, I had hoped that we could do without such manual configu- > ration like CONFIG_FSL_ESDHC_*_ENDIAN. I mean, we already know the > target byte order, and you know in which byte order you want to > access the data, or is this board dependent? It should be enough to include asm/byteorder.h. Based on __BYTE_ORDER, I can select the correct accessors in the driver. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: off...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V4 09/11] ARM/PPC: add a common way to access registers
Dear Stefano Babic, In message <4b6a96b3.4060...@denx.de> you wrote: > Wolfgang Denk wrote: > > > I like this approach better than the precious one. > > > > However, I had hoped that we could do without such manual configu- > > ration like CONFIG_FSL_ESDHC_*_ENDIAN. I mean, we already know the > > target byte order, and you know in which byte order you want to > > access the data, or is this board dependent? > > It should be enough to include asm/byteorder.h. Based on __BYTE_ORDER, I > can select the correct accessors in the driver. Excellent. Then let's do it this way. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de A Perl script is correct if it's halfway readable and gets the job done before your boss fires you. - L. Wall & R. L. Schwartz, _Programming Perl_ ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] We give Secure Loan and Unsecured
The Direct Finance UK, is a private financial institution in the United Kingdom. Giving out loan to ease the Global Financial Crisis (Recession) with a little interest of 3%. We give Secure Loan and Unsecured Loans to individual and Corporate film. Interested Applicants should contact The application desk at this email: direct-of...@discuz.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv2] OMAP3: Avoid re-write to PRM_CLKSRC_CTRL
Premi, Sanjeev wrote:
>> -Original Message-
>> From: Premi, Sanjeev
>> Sent: Friday, January 29, 2010 6:44 PM
>> To: u-boot@lists.denx.de
>> Cc: Premi, Sanjeev; Hiremath, Vaibhav
>> Subject: [PATCHv2] OMAP3: Avoid re-write to PRM_CLKSRC_CTRL
>>
>> The function get_osc_clk_speed() is used to determine the master
>> clock. If SYS_CLK is being divided by 2, the divider is changed
>> to 1 - without following any sequence.
>>
>> Before reaching this function, some of the clocks have already
>> been set (by x-loader or equiv) OR power-on defaults are in use.
>> This change is too sudden, leading to instability beyond certain
>> tolerance zone.
>>
>> The problem was observed with DM3730 (silimar to OMAP3630), on
>> the OMAP3EVM.
>>
>> This patch removes the step to change clock divider. Instead,
>> uses a multiplication factor (if needed). Mathematically, the
>> formula is unchanged.
>>
>> Tested on OMAP3EVM with OMAP3530 and DM3730.
>>
>> Signed-off-by: Sanjeev Premi
>> Signed-off-by: Hiremath Vaibhav
>> ---
>> cpu/arm_cortexa8/omap3/clock.c | 15 +++
>> 1 files changed, 11 insertions(+), 4 deletions(-)
>>
>> diff --git a/cpu/arm_cortexa8/omap3/clock.c
>> b/cpu/arm_cortexa8/omap3/clock.c
>> index 174c453..e8189b4 100644
>> --- a/cpu/arm_cortexa8/omap3/clock.c
>> +++ b/cpu/arm_cortexa8/omap3/clock.c
>> @@ -40,7 +40,7 @@
>>
>> **
>> ***/
>> u32 get_osc_clk_speed(void)
>> {
>> -u32 start, cstart, cend, cdiff, val;
>> +u32 start, cstart, cend, cdiff, cdiv, val;
>> struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
>> struct prm *prm_base = (struct prm *)PRM_BASE;
>> struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1;
>> @@ -48,9 +48,13 @@ u32 get_osc_clk_speed(void)
>>
>> val = readl(&prm_base->clksrc_ctrl);
>>
>> -/* If SYS_CLK is being divided by 2, remove for now */
>> -val = (val & (~SYSCLKDIV_2)) | SYSCLKDIV_1;
>> -writel(val, &prm_base->clksrc_ctrl);
>> +if (val & SYSCLKDIV_2)
>> +cdiv = 2;
>> +else if (val & SYSCLKDIV_1)
>> +cdiv = 1;
>> +else
>> +/*Should never reach here! (Assume divider as 1) */
>> +cdiv = 1;
>>
>> /* enable timer2 */
>> val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1;
>> @@ -83,6 +87,9 @@ u32 get_osc_clk_speed(void)
>> cend = readl(&gpt1_base->tcrr); /* get end
>> sys_clk count */
>> cdiff = cend - cstart; /* get elapsed ticks */
>>
>> +if (cdiv == 2)
>> +cdiff *= 2;
>> +
>> /* based on number of ticks assign speed */
>> if (cdiff > 19000)
>> return S38_4M;
>> --
>> 1.6.2.2
>>
>>
>
> Tom, Sandeep,
>
> Just wanted to check the status of this patch.
>
I need to review and test it..
This will happen over the weekend.
> Best regards,
> Sanjeev
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[U-Boot] I2C Register
Hi, I am trying to read SPD data from dimm though I2c. as the board that i am using it has different I2c register so it is difficult to match with the register used in u-boot. Can i get the information about /*- | IIC Register Offsets '*/ #define IICMDBUF 0x00 #define IICSDBUF 0x02 #define IICLMADR 0x04 #define IICHMADR 0x05 #define IICCNTL 0x06 #define IICMDCNTL 0x07 #define IICSTS 0x08 #define IICEXTSTS 0x09 #define IICLSADR 0x0A #define IICHSADR 0x0B #define IICCLKDIV 0x0C #define IICINTRMSK 0x0D #define IICXFRCNT 0x0E #define IICXTCNTLSS 0x0F #define IICDIRECTCNTL 0x10 these register to that it will be easy for me to match with the register that i am using. Regards, Ronny The INTERNET now has a personality. YOURS! See your Yahoo! Homepage. http://in.yahoo.com/___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Add bootcount to AT91
Hi, On Thu, Jan 14, 2010 at 15:00, Anders Darander wrote: > From: Anders Darander > > Use AT91_GPBR 3 as a bootcount register. > As a followup to Werners list of patches not incorporated (from some time ago), I'd just like to get a comment on the status of this patch. Should it get reworked somehow, or could it be integrated? Regards, Anders Darander ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] I2C Register
Hi Ronny,
On Thursday 04 February 2010 15:30:35 Ronny D wrote:
> I am trying to read SPD data from dimm though I2c.
> as the board that i am using it has different I2c register so it is
> difficult to match with the register used in u-boot.
Which platform are you using? PPC4xx? Or something else?
> Can i get the
> information about
> /*-
>
>
> | IIC Register Offsets
>
> '--
> --*/ #define IICMDBUF 0x00
> #define IICSDBUF 0x02
> #define IICLMADR 0x04
> #define IICHMADR 0x05
> #define IICCNTL 0x06
> #define IICMDCNTL 0x07
> #define IICSTS 0x08
> #define IICEXTSTS 0x09
> #define IICLSADR 0x0A
> #define IICHSADR 0x0B
> #define IICCLKDIV 0x0C
> #define IICINTRMSK 0x0D
> #define IICXFRCNT 0x0E
> #define IICXTCNTLSS 0x0F
> #define IICDIRECTCNTL 0x10
>
> these register to that it will be easy for me to match with the register
> that i am using.
These defines above are not available in U-Boot any more. I switched to using
a struct s while ago:
struct ppc4xx_i2c {
u8 mdbuf;
u8 res1;
u8 sdbuf;
...
You are using PPC4xx, right?
Cheers,
Stefan
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: off...@denx.de
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Re: [U-Boot] [PATCH V4 09/11] ARM/PPC: add a common way to access registers
Stefano Babic wrote: > Wolfgang Denk wrote: > >> I like this approach better than the precious one. >> >> However, I had hoped that we could do without such manual configu- >> ration like CONFIG_FSL_ESDHC_*_ENDIAN. I mean, we already know the >> target byte order, and you know in which byte order you want to >> access the data, or is this board dependent? > > It should be enough to include asm/byteorder.h. Based on __BYTE_ORDER, I > can select the correct accessors in the driver. How about adding additional I/O accessors that do native endian accesses instead of specified endian? -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Add support for Indefia Nimbus Cloud Board
Dear Wolfgang, The problem with AVR32 and the CFI flash driver has a few possible solutions as noted by Haavard Skinnemoen in the email [1]. The only thing I can do is to go with the first alternative and set the flash address as the virtual address which is cache-disabled and works flawless with the CFI driver. That solution can also be used by other AVR32 boards, and I _think_ it also solves the JFFS2 scanning problem which was mentioned in [2]. The only ugly thing (for me) is when using the CFI commands, the flash addresses has to be shifted by 0xa000. (e.g. copy to flash at 0x1000 must be written as cp.b 0xa0001000 ). Please find the revised patch in a separate email, which also includes a new header file per your comments in the other email. Best Regards, Semih Hazar [1] http://www.mail-archive.com/u-boot@lists.denx.de/msg20911.html [2] http://lists.avr32linux.org/pipermail/u-boot/2009-August/000457.html ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Add support for Indefia Nimbus Cloud Board
Nimbus Cloud is an AVR32 based single board computer with 256MiB NAND, 64MiB SDRAM, battery backed RTC, LCD/touch screen support, VGA Output, Ethernet and offers seamless integration with Indefia's Zigbee transceivers. --- CREDITS |4 + MAINTAINERS |4 + MAKEALL |1 + Makefile|3 + board/indefia/nimbuscloud/Makefile | 40 +++ board/indefia/nimbuscloud/config.mk |3 + board/indefia/nimbuscloud/nimbuscloud.c | 165 +++ board/indefia/nimbuscloud/nimbuscloud.h |8 ++ board/indefia/nimbuscloud/u-boot.lds| 72 include/configs/nimbuscloud.h | 184 +++ 10 files changed, 484 insertions(+), 0 deletions(-) diff --git a/CREDITS b/CREDITS index 2471029..69a9dde 100644 --- a/CREDITS +++ b/CREDITS @@ -196,6 +196,10 @@ N: Anne-Sophie Harnois E: anne-sophie.harn...@nextream.fr D: Port to Walnut405 board +N: Semih Hazar +E: semih.ha...@indefia.com +D: Nimbus Cloud board support + N: Andreas Heppel E: ahep...@sysgo.de D: CPU Support for MPC 75x; board support for Eltec BAB750 [obsolete!] diff --git a/MAINTAINERS b/MAINTAINERS index e8ba4bc..9202137 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -881,6 +881,10 @@ Hans-Christian Egtvedt FAVR-32-EZKIT AT32AP7000 +Semih Hazar + + NIMBUSCLOUD AT32AP7000 + Mark Jackson MIMC200 AT32AP7000 diff --git a/MAKEALL b/MAKEALL index 15e93cf..6ee30ec 100755 --- a/MAKEALL +++ b/MAKEALL @@ -866,6 +866,7 @@ LIST_avr32="\ favr-32-ezkit \ hammerhead \ mimc200 \ + nimbuscloud \ " # diff --git a/Makefile b/Makefile index 69b963f..8c4e453 100644 --- a/Makefile +++ b/Makefile @@ -3593,6 +3593,9 @@ hammerhead_config : unconfig mimc200_config : unconfig @$(MKCONFIG) $(@:_config=) avr32 at32ap mimc200 mimc at32ap700x +nimbuscloud_config : unconfig +@$(MKCONFIG) $(@:_config=) avr32 at32ap nimbuscloud indefia at32ap700x + # # SH3 (SuperH) # diff --git a/board/indefia/nimbuscloud/Makefile b/board/indefia/nimbuscloud/Makefile new file mode 100644 index 000..43a9c68 --- /dev/null +++ b/board/indefia/nimbuscloud/Makefile @@ -0,0 +1,40 @@ +# +# Copyright (C) 2008-2009 Indefia +# +# See file CREDITS for list of people who contributed to this project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB:= $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/indefia/nimbuscloud/config.mk b/board/indefia/nimbuscloud/config.mk new file mode 100644 index 000..9a794e5 --- /dev/null +++ b/board/indefia/nimbuscloud/config.mk @@ -0,0 +1,3 @@ +TEXT_BASE = 0x +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections +PLATFORM_LDFLAGS += --gc-sections diff --git a/board/indefia/nimbuscloud/nimbuscloud.c b/board/indefia/nimbuscloud/nimbuscloud.c new file mode 100644 index 000..e869a97 --- /dev/null +++ b/board/indefia/nimbuscloud/nimbuscloud.c @@ -0,0 +1,165 @@ +/* + * Copyright (C) 2008-2009 Indefia + * + * Based on atngw100.c (c) Atmel Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that
Re: [U-Boot] [STATUS] Merge Window closed, waiting for pull requests
On 20.01.2010 18:58, Paulraj, Sandeep wrote: > > >> Subject: Re: [U-Boot] [STATUS] Merge Window closed, waiting for pull >> requests >> >> On 19.01.2010 23:30, Wolfgang Denk wrote: >>> Hi >>> >>> as you probably have noticed, the merge window closed about 24 hours >>> ago. Checking my list, I still see s _long_ list of ARM related >>> patches that have not been processed yet. For many of them I haven't >>> seen any review comments, nor have architecture maintainer picked >>> these up and sent pull requests to Tom. >>> >>> Can you please try and work on this now, so that we can have the >>> outstanding patches integrated into mainline in the next few days? >> >> I'd like to see the Beagle rev C4 patches applied: >> >> http://lists.denx.de/pipermail/u-boot/2010-January/066629.html >> http://lists.denx.de/pipermail/u-boot/2010-January/066632.html >> http://lists.denx.de/pipermail/u-boot/2010-January/066634.html >> http://lists.denx.de/pipermail/u-boot/2010-January/066636.html >> http://lists.denx.de/pipermail/u-boot/2010-January/066638.html >> http://lists.denx.de/pipermail/u-boot/2010-January/066640.html >> http://lists.denx.de/pipermail/u-boot/2010-January/066642.html >> >> (The ml archive seems to have some issues with these patches. In my >> inbox they seem to be fine, though) > Same with me but when I discussed offline with Tom, it appears as if this set > never made it to his Inbox. > > We need just a little more time. What's the recent status of this? Thanks Dirk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [STATUS] Merge Window closed, waiting for pull requests
> > On 20.01.2010 18:58, Paulraj, Sandeep wrote: > > > > > >> Subject: Re: [U-Boot] [STATUS] Merge Window closed, waiting for pull > >> requests > >> > >> On 19.01.2010 23:30, Wolfgang Denk wrote: > >>> Hi > >>> > >>> as you probably have noticed, the merge window closed about 24 hours > >>> ago. Checking my list, I still see s _long_ list of ARM related > >>> patches that have not been processed yet. For many of them I haven't > >>> seen any review comments, nor have architecture maintainer picked > >>> these up and sent pull requests to Tom. > >>> > >>> Can you please try and work on this now, so that we can have the > >>> outstanding patches integrated into mainline in the next few days? > >> > >> I'd like to see the Beagle rev C4 patches applied: > >> > >> http://lists.denx.de/pipermail/u-boot/2010-January/066629.html > >> http://lists.denx.de/pipermail/u-boot/2010-January/066632.html > >> http://lists.denx.de/pipermail/u-boot/2010-January/066634.html > >> http://lists.denx.de/pipermail/u-boot/2010-January/066636.html > >> http://lists.denx.de/pipermail/u-boot/2010-January/066638.html > >> http://lists.denx.de/pipermail/u-boot/2010-January/066640.html > >> http://lists.denx.de/pipermail/u-boot/2010-January/066642.html > >> > >> (The ml archive seems to have some issues with these patches. In my > >> inbox they seem to be fine, though) > > Same with me but when I discussed offline with Tom, it appears as if > this set never made it to his Inbox. > > > > We need just a little more time. > > What's the recent status of this? Tom had comments. Thanks, Sandeep ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [STATUS]
Hi, I would like to have all new stuff in the master branch by mid of next week or so (Feb 10). To all custodians: please try and pick up any remaining patches quickly now, and send me pull requests. To all ARM custodians (and especially Tom): I still see a long list of unprocessed patches queued up. Do you think we cn get at least most of this in during this week? Thanks in advance. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de "The number of Unix installations has grown to 10, with more expected."- The Unix Programmer's Manual, 2nd Edition, June, 1972 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] TI Davinci and MUSB
I've been trying to get usbtty working on a DM355 (still isn't
working...) and ran into a bug(?).
In drivers/usb/musb/davinci.h:
struct davinci_usb_regs {
u32 version;
u32 ctrlr;
u32 reserved[0x20];
u32 intclrr;
u32 intmskr;
u32 intmsksetr;
};
Shouldn't this be reserved[0x20/4] ?
--
Neal Tew
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Re: [U-Boot] TI Davinci and MUSB
> -Original Message-
> From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de]
> On Behalf Of Neal Tew
> Sent: Friday, February 05, 2010 3:33 AM
> To: u-boot@lists.denx.de
> Subject: [U-Boot] TI Davinci and MUSB
>
> I've been trying to get usbtty working on a DM355 (still isn't
> working...) and ran into a bug(?).
>
> In drivers/usb/musb/davinci.h:
>
> struct davinci_usb_regs {
> u32 version;
> u32 ctrlr;
> u32 reserved[0x20];
> u32 intclrr;
> u32 intmskr;
> u32 intmsksetr;
> };
>
> Shouldn't this be reserved[0x20/4] ?
Yes, this is a bug. Though the correct fix is,
- u32 reserved[0x20];
+ u32 reserved[5];
Please refer musb Davinci (DM6446) document (page-74) at,
http://focus.ti.com/lit/ug/sprue35f/sprue35f.pdf
-->4h CTRLR Control Register Section 4.1
8h STATR Status Register Section 4.2
10h RNDISR RNDIS Register Section 4.3
14h AUTOREQ Autorequest Register Section 4.4
20h INTSRCR USB Interrupt Source Register Section 4.5
24h INTSETR USB Interrupt Source Set Register Section 4.6
-->28h INTCLRR USB Interrupt Source Clear Register
-Ajay
>
> --
> Neal Tew
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Re: [U-Boot] I2C Register
Hi Stefan,
I am using ppc440 for customized board.
U-boot version that i am using is u-boot-2009.11.
Here i am searching for the ppc4xx_i2c structure but not able to get it. on the
other hand i have seen the i2c register macros used in i2c_transfer call.
~Ronny
--- On Thu, 4/2/10, Stefan Roese wrote:
From: Stefan Roese
Subject: Re: I2C Register
To: "Ronny D"
Cc: u-boot@lists.denx.de
Date: Thursday, 4 February, 2010, 2:53 PM
Hi Ronny,
On Thursday 04 February 2010 15:30:35 Ronny D wrote:
> I am trying to read SPD data from dimm though I2c.
> as the board that i am using it has different I2c register so it is
> difficult to match with the register used in u-boot.
Which platform are you using? PPC4xx? Or something else?
> Can i get the
> information about
> /*-
>
>
> | IIC Register Offsets
>
> '--
> --*/ #define IICMDBUF 0x00
> #define IICSDBUF 0x02
> #define IICLMADR 0x04
> #define IICHMADR 0x05
> #define IICCNTL 0x06
> #define IICMDCNTL 0x07
> #define IICSTS 0x08
> #define IICEXTSTS 0x09
> #define IICLSADR 0x0A
> #define IICHSADR 0x0B
> #define IICCLKDIV 0x0C
> #define IICINTRMSK 0x0D
> #define IICXFRCNT 0x0E
> #define IICXTCNTLSS 0x0F
> #define IICDIRECTCNTL 0x10
>
> these register to that it will be easy for me to match with the register
> that i am using.
These defines above are not available in U-Boot any more. I switched to using
a struct s while ago:
struct ppc4xx_i2c {
u8 mdbuf;
u8 res1;
u8 sdbuf;
...
You are using PPC4xx, right?
Cheers,
Stefan
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: off...@denx.de
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Re: [U-Boot] TI Davinci and MUSB
[5]? I don't think that's right. Look at the offsets.
-Neal
> I've been trying to get usbtty working on a DM355 (still isn't
> working...) and ran into a bug(?).
>
> In drivers/usb/musb/davinci.h:
>
> struct davinci_usb_regs {
> u32 version;
> u32 ctrlr;
> u32 reserved[0x20];
> u32 intclrr;
> u32 intmskr;
> u32 intmsksetr;
> };
>
> Shouldn't this be reserved[0x20/4] ?
Yes, this is a bug. Though the correct fix is,
- u32 reserved[0x20];
+ u32 reserved[5];
Please refer musb Davinci (DM6446) document (page-74) at,
http://focus.ti.com/lit/ug/sprue35f/sprue35f.pdf
-->4h CTRLR Control Register Section 4.1
8h STATR Status Register Section 4.2
10h RNDISR RNDIS Register Section 4.3
14h AUTOREQ Autorequest Register Section 4.4
20h INTSRCR USB Interrupt Source Register Section 4.5
24h INTSETR USB Interrupt Source Set Register Section 4.6
-->28h INTCLRR USB Interrupt Source Clear Register
-Ajay
>
> --
> Neal Tew
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Re: [U-Boot] TI Davinci and MUSB
> -Original Message-
> From: Neal Tew [mailto:lo...@mm.st]
> Sent: Friday, February 05, 2010 11:20 AM
> To: u-boot@lists.denx.de
> Cc: Gupta, Ajay Kumar
> Subject: Re: [U-Boot] TI Davinci and MUSB
>
> [5]? I don't think that's right. Look at the offsets.
>
> -Neal
>
> > I've been trying to get usbtty working on a DM355 (still isn't
> > working...) and ran into a bug(?).
> >
> > In drivers/usb/musb/davinci.h:
> >
> > struct davinci_usb_regs {
> > u32 version;
> > u32 ctrlr;
> > u32 reserved[0x20];
> > u32 intclrr;
> > u32 intmskr;
> > u32 intmsksetr;
> > };
> >
> > Shouldn't this be reserved[0x20/4] ?
>
> Yes, this is a bug. Though the correct fix is,
> - u32 reserved[0x20];
> + u32 reserved[5];
Opps, there are actually 32 intermediate register each of 32 bits.
So the correct one is as Neal suggested.
- u32 reserved[0x20];
+ u32 reserved[020/4];
-Ajay
>
> Please refer musb Davinci (DM6446) document (page-74) at,
> http://focus.ti.com/lit/ug/sprue35f/sprue35f.pdf
>
> -->4h CTRLR Control Register Section 4.1
> 8h STATR Status Register Section 4.2
> 10h RNDISR RNDIS Register Section 4.3
> 14h AUTOREQ Autorequest Register Section 4.4
> 20h INTSRCR USB Interrupt Source Register Section 4.5
> 24h INTSETR USB Interrupt Source Set Register Section 4.6
> -->28h INTCLRR USB Interrupt Source Clear Register
>
> -Ajay
> >
> > --
> > Neal Tew
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Re: [U-Boot] I2C Register
Hi Ronny, On Friday 05 February 2010 06:43:20 Ronny D wrote: > I am using ppc440 for customized board. So is this a "normal" AMCC PPC4xx (e.g. 440GX...) or a custom PPC4xx chip? If it's a common 4xx, then the normal PPC4xx I2C code should just work for you as well. > U-boot version that i am using is u-boot-2009.11. That is before the restructuring. For new work please use the latest version from the git repository. > Here i am searching for the ppc4xx_i2c structure but not able to get it. on > the other hand i have seen the i2c register macros used in i2c_transfer > call. Again, 2009-11 is already outdated. I reworked the I2C stuff in the meantime. Try the latest version and take a look at: cpu/ppc4xx/i2c.c include/4xx_i2c.h Cheers, Stefan -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: off...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] TI Davinci and MUSB
Dear "Gupta, Ajay Kumar", In message <19f8576c6e063c45be387c64729e7394044a775...@dbde02.ent.ti.com> you wrote: > > > u32 reserved[0x20]; > > u32 intclrr; > > u32 intmskr; > > u32 intmsksetr; > > }; > > > > Shouldn't this be reserved[0x20/4] ? > > Yes, this is a bug. Though the correct fix is, > - u32 reserved[0x20]; > + u32 reserved[5]; Umm... > Please refer musb Davinci (DM6446) document (page-74) at, > http://focus.ti.com/lit/ug/sprue35f/sprue35f.pdf > > -->4h CTRLR Control Register Section 4.1 > 8h STATR Status Register Section 4.2 > 10h RNDISR RNDIS Register Section 4.3 > 14h AUTOREQ Autorequest Register Section 4.4 > 20h INTSRCR USB Interrupt Source Register Section 4.5 > 24h INTSETR USB Interrupt Source Set Register Section 4.6 > -->28h INTCLRR USB Interrupt Source Clear Register Why don't we add these fields to he struct above if they are not actually reserved, but have a documented use? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de panic: kernel trap (ignored) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] I2C Register
It is not a normal AMCC PPC4xx, its a customized PPC4xx chip. so I2C code wont work for me as it is. i will have to map my register with i2c register used by u-boot. Now i have downloaded latest u-boot version(Jan 25 2010 12:37 Link u-boot-latest.tar.bz2 -> u-boot-2009.11.1.tar.bz2) from ftp. still ppc4xx_i2c structure i could not found. ~Ronny. --- On Thu, 4/2/10, Stefan Roese wrote: Hi Ronny, On Friday 05 February 2010 06:43:20 Ronny D wrote: > I am using ppc440 for customized board. So is this a "normal" AMCC PPC4xx (e.g. 440GX...) or a custom PPC4xx chip? If it's a common 4xx, then the normal PPC4xx I2C code should just work for you as well. > U-boot version that i am using is u-boot-2009.11. That is before the restructuring. For new work please use the latest version from the git repository. > Here i am searching for the ppc4xx_i2c structure but not able to get it. on > the other hand i have seen the i2c register macros used in i2c_transfer > call. Again, 2009-11 is already outdated. I reworked the I2C stuff in the meantime. Try the latest version and take a look at: cpu/ppc4xx/i2c.c include/4xx_i2c.h Cheers, Stefan -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: off...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot The INTERNET now has a personality. YOURS! See your Yahoo! Homepage. http://in.yahoo.com/___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] TI Davinci and MUSB
Dear "Gupta, Ajay Kumar", In message <19f8576c6e063c45be387c64729e7394044a776...@dbde02.ent.ti.com> you wrote: > > Opps, there are actually 32 intermediate register each of 32 bits. > > So the correct one is as Neal suggested. > > - u32 reserved[0x20]; > + u32 reserved[020/4]; 0x20 / 4 = 8 020 / 4 = 4 Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de One difference between a man and a machine is that a machine is quiet when well oiled. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] TI Davinci and MUSB
> -Original Message- > From: Wolfgang Denk [mailto:w...@denx.de] > Sent: Friday, February 05, 2010 12:12 PM > To: Gupta, Ajay Kumar > Cc: Neal Tew; u-boot@lists.denx.de > Subject: Re: [U-Boot] TI Davinci and MUSB > > Dear "Gupta, Ajay Kumar", > > In message <19f8576c6e063c45be387c64729e7394044a776...@dbde02.ent.ti.com> > you wrote: > > > > Opps, there are actually 32 intermediate register each of 32 bits. > > > > So the correct one is as Neal suggested. > > > > - u32 reserved[0x20]; > > + u32 reserved[020/4]; > > 0x20 / 4 = 8 > > 020 / 4 = 4 It was typing mistake... Thanks, Ajay > > Best regards, > > Wolfgang Denk > > -- > DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de > One difference between a man and a machine is that a machine is quiet > when well oiled. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] I2C Register
On Friday 05 February 2010 07:41:27 Ronny D wrote: > It is not a normal AMCC PPC4xx, its a customized PPC4xx chip. so I2C code > wont work for me as it is. I see. So you should probably not base your I2C driver code on the PPC4xx code. Perhaps you could use the soft_i2c code, where you only need some GPIO's to control the I2C signals. > i will have to map my register with i2c register used by u-boot. > > Now i have downloaded latest u-boot version(Jan 25 2010 12:37 Link > u-boot-latest.tar.bz2 -> u-boot-2009.11.1.tar.bz2) from ftp. > > still ppc4xx_i2c structure i could not found. That's because the source code on the FTP server is reflecting the last release version. Please use the latest version from the git repository instead: http://git.denx.de/?p=u-boot.git;a=summary There is also the possibility to download a snapshort in this web page, if you can't use git for some reason. Cheers, Stefan -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: off...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
