Re: [U-Boot] [PATCH 3/3] TI: TNETV107X EVM initial support
Dear Cyril Chemparathy, In message 1269893792-15248-4-git-send-email-cy...@ti.com you wrote: TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a bunch on on-chip integrated peripherals. This patch adds support for the TNETV107X EVM board. Signed-off-by: Cyril Chemparathy cy...@ti.com --- MAKEALL |1 + Makefile |3 + board/ti/tnetv107xevm/Makefile| 49 board/ti/tnetv107xevm/config.mk | 20 board/ti/tnetv107xevm/sdb_board.c | 66 +++ board/ti/tnetv107xevm/u-boot.lds | 48 include/configs/tnetv107x_evm.h | 225 + 7 files changed, 412 insertions(+), 0 deletions(-) create mode 100644 board/ti/tnetv107xevm/Makefile create mode 100644 board/ti/tnetv107xevm/config.mk create mode 100644 board/ti/tnetv107xevm/sdb_board.c create mode 100644 board/ti/tnetv107xevm/u-boot.lds create mode 100644 include/configs/tnetv107x_evm.h Entry to MAINTAINERS missing. diff --git a/Makefile b/Makefile index c0e73de..e723e7c 100644 --- a/Makefile +++ b/Makefile @@ -2936,6 +2936,9 @@ davinci_dm365evm_config : unconfig davinci_dm6467evm_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs dm6467evm davinci davinci +tnetv107x_evm_config: unconfig + @$(MKCONFIG) $(@:_config=) arm arm1176 tnetv107xevm ti tnetv107x + imx27lite_config:unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs imx27lite logicpd mx27 Please keep lists sorted - board names, and architectures. arm1176 has no place among arm926ejs systems. diff --git a/board/ti/tnetv107xevm/u-boot.lds b/board/ti/tnetv107xevm/u-boot.lds new file mode 100644 index 000..3afa17f --- /dev/null +++ b/board/ti/tnetv107xevm/u-boot.lds Do you really need board specific linker scripts? Or would one common linker script for all (or at least for most of the) boards be sufficient? diff --git a/include/configs/tnetv107x_evm.h b/include/configs/tnetv107x_evm.h new file mode 100644 index 000..795e3f1 --- /dev/null +++ b/include/configs/tnetv107x_evm.h ... +// +/* Architecture, CPU, etc. */ +// Incorrect multiline comment styile. Please fix globally. +#define MTDIDS_DEFAULT nand0=davinci_nand.0 +#define MTDPARTS_DEFAULT mtdparts=davinci_nand.0: \ + 1536k(uboot)ro, \ + 128k(params)ro, \ + 4m(kernel), \ + -(filesystem) Is davinci correct here? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de I have a theory that it's impossible to prove anything, but I can't prove it. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/4] s5p6442: Add support SMDK6442 board
Dear Joonyoung Shim, In message 4bb016eb.9010...@samsung.com you wrote: This patch adds the new board SMDK6442 that uses s5p6442 SoC. Cc: Minkyu Kang mk7.k...@samsung.com Cc: Kyungmin Park kyungmin.p...@samsung.com Signed-off-by: Joonyoung Shim jy0922.s...@samsung.com --- MAKEALL|1 + Makefile |3 + board/samsung/smdk6442/Makefile| 55 +++ board/samsung/smdk6442/config.mk |6 + board/samsung/smdk6442/lowlevel_init.S | 202 ++ board/samsung/smdk6442/mem_setup.S | 175 +++ board/samsung/smdk6442/onenand.c | 41 ++ board/samsung/smdk6442/smdk6442.c | 54 +++ include/configs/smdk6442.h | 242 9 files changed, 779 insertions(+), 0 deletions(-) create mode 100644 board/samsung/smdk6442/Makefile create mode 100644 board/samsung/smdk6442/config.mk create mode 100644 board/samsung/smdk6442/lowlevel_init.S create mode 100644 board/samsung/smdk6442/mem_setup.S create mode 100644 board/samsung/smdk6442/onenand.c create mode 100644 board/samsung/smdk6442/smdk6442.c create mode 100644 include/configs/smdk6442.h Entry to MAINTAINERS missing. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Military secrets are the most fleeting of all. -- Spock, The Enterprise Incident, stardate 5027.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] ARM1176: TI: TNETV107X soc initial support
Hi Wolfgang,
You might want to define a macro to reduce the amount of repeated
code here.
Will do in v2.
+void lpsc_control(unsigned int id, int state)
+{
+ __lpsc_control(1, -1, id, state);
+}
+
+int lpsc_status(unsigned int id)
+{
+ return psc_reg_read(PSC_MDSTAT(id)) 0x1f;
+}
+
+void clk_enable(unsigned int id)
+{
+ lpsc_control(id, PSC_MDCTL_NEXT_ENABLE);
+}
+
+void clk_disable(unsigned int id)
+{
+ lpsc_control(id, PSC_MDCTL_NEXT_DISABLE);
+}
These should probably be inlined ?
Are you referring to lpsc_control(), or to clk_enable/clk_disable?
The former can be eliminated, I think.
The latter are used elsewhere. Are you recommending that I inline and move to
a header?
Regards
Cyril.
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Re: [U-Boot] [PATCH 1/4] s5p6442: Support Samsung s5p6442 SoC
Dear Joonyoung Shim, In message 4bb016dc.5000...@samsung.com you wrote: This patch adds support s5p6442 SoC. The s5p6442 SoC is ARM1176 processor. Cc: Minkyu Kang mk7.k...@samsung.com Cc: Kyungmin Park kyungmin.p...@samsung.com Signed-off-by: Joonyoung Shim jy0922.s...@samsung.com ... +#define S5P6442_PWR_CFG 0xE010C000 ... +#define S5P6442_EINT_WAKEUP_MASK 0xE010C004 +#define S5P6442_WAKEUP_MASK 0xE010C008 +#define S5P6442_PWR_MODE 0xE010C00C +#define S5P6442_PWR_MODE_SLEEP (1 2) +#define S5P6442_NORMAL_CFG 0xE010C010 +#define S5P6442_IDLE_CFG 0xE010C020 +#define S5P6442_STOP_CFG 0xE010C030 +#define S5P6442_STOP_MEM_CFG 0xE010C034 +#define S5P6442_SLEEP_CFG0xE010C040 +#define S5P6442_OSC_FREQ 0xE010C100 +#define S5P6442_OSC_STABLE 0xE010C104 +#define S5P6442_PWR_STABLE 0xE010C108 +#define S5P6442_MTC_STABLE 0xE010C110 +#define S5P6442_CLAMP_STABLE 0xE010C114 +#define S5P6442_WAKEUP_STAT 0xE010C200 +#define S5P6442_OTHERS 0xE010E000 +#define S5P6442_OTHERS_SYSCON_INT_DISABLE(1 0) +#define S5P6442_MIE_CONTROL 0xE010E800 +#define S5P6442_HDMI_CONTROL 0xE010E804 +#define S5P6442_USB_PHY_CON 0xE010E80C +#define S5P6442_DAC_CONTROL 0xE010E810 +#define S5P6442_MIPI_DPHY_CONTROL0xE010E814 +#define S5P6442_ADC_CONTROL 0xE010E818 +#define S5P6442_PS_HOLD_CONTROL 0xE010E81C +#define S5P6442_PS_HOLD_DIR_OUTPUT (1 9) +#define S5P6442_PS_HOLD_DIR_INPUT(0 9) +#define S5P6442_PS_HOLD_DATA_HIGH(1 8) +#define S5P6442_PS_HOLD_DATA_LOW (0 8) +#define S5P6442_PS_HOLD_OUT_EN (1 0) +#define S5P6442_INFORM0 0xE010F000 +#define S5P6442_INFORM1 0xE010F004 +#define S5P6442_INFORM2 0xE010F008 +#define S5P6442_INFORM3 0xE010F00C +#define S5P6442_INFORM4 0xE010F010 +#define S5P6442_INFORM5 0xE010F014 +#define S5P6442_INFORM6 0xE010F018 +#define S5P6442_INFORM7 0xE010F01C Please use C structs to describe these registers. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Hiring experienced unix people is like a built-in filter against idiots. Hiring experienced NT people provides no such guarantee. -- Miguel Cruz in wgl96.349$cc.122...@typhoon2.ba-dsg.net ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] TI: TNETV107X EVM initial support
Hi Wolfgang, Thanks. Will send out a v2 with these changed. [...] +#define MTDPARTS_DEFAULT mtdparts=davinci_nand.0: \ + 1536k(uboot)ro, \ + 128k(params)ro, \ + 4m(kernel), \ + -(filesystem) Is davinci correct here? Yes, this SOC has the exact same controller as on Davinci, and therefore the NAND driver is reused. Regards Cyril. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] add support of arm/pxa270 board made by voipac
Dear Mikhail Kshevetskiy, In message 20100329162420.40f54...@laska.campus-ws.pu.ru you wrote: This patch is based on custom u-boot-1.1.2 version produced by voipac (http://www.voipac.com) and board/trizepsiv files from current u-boot. Up to now only PXA270 DIMM module with NOR flash is tested. Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com --- Makefile |3 + board/vpac270/Makefile| 51 +++ board/vpac270/config.mk |3 + board/vpac270/lowlevel_init.S | 740 + board/vpac270/vpac270.c | 101 ++ include/configs/vpac270.h | 329 ++ 6 files changed, 1227 insertions(+), 0 deletions(-) create mode 100644 board/vpac270/Makefile create mode 100644 board/vpac270/config.mk create mode 100644 board/vpac270/lowlevel_init.S create mode 100644 board/vpac270/vpac270.c create mode 100644 include/configs/vpac270.h Entries to MAKEALL and MAINTAINERS missing. diff --git a/board/vpac270/config.mk b/board/vpac270/config.mk new file mode 100644 index 000..4486f6b --- /dev/null +++ b/board/vpac270/config.mk @@ -0,0 +1,3 @@ +TEXT_BASE =0xa1f0 +# 0xa170 +#TEXT_BASE = 0 Please do not add dead code. Remove it. diff --git a/board/vpac270/lowlevel_init.S b/board/vpac270/lowlevel_init.S new file mode 100644 index 000..1df381c ... +/* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm Indentation and vertial alignment by TAB only. Please fix globally. + /* Set up GPIO pins first - */ + + ldr r0, =GPSR0 + ldr r1, =CONFIG_SYS_GPSR0_VAL + str r1, [r0] One TAB between instruction and arguments should be sufficient. + /* */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps*/ + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ + /* Chapter 10. */ + /* */ Incorrect multiline comment style. Please fix globally. ... + /* MECR: Memory Expansion Card Register */ + ldr r2, =CONFIG_SYS_MECR_VAL + str r2, [r1, #MECR_OFFSET] + ldr r2, [r1, #MECR_OFFSET] Inconsistent indentation - please fix globally. + /* MCMEM0: Card Interface slot 0 timing */ + ldr r2, =CONFIG_SYS_MCMEM0_VAL + str r2, [r1, #MCMEM0_OFFSET] + ldr r2, [r1, #MCMEM0_OFFSET] + + /* MCMEM1: Card Interface slot 1 timing */ + ldr r2, =CONFIG_SYS_MCMEM1_VAL + str r2, [r1, #MCMEM1_OFFSET] + ldr r2, [r1, #MCMEM1_OFFSET] + + /* MCATT0: Card Interface Attribute Space Timing, slot 0*/ + ldr r2, =CONFIG_SYS_MCATT0_VAL + str r2, [r1, #MCATT0_OFFSET] + ldr r2, [r1, #MCATT0_OFFSET] + + /* MCATT1: Card Interface Attribute Space Timing, slot 1*/ + ldr r2, =CONFIG_SYS_MCATT1_VAL + str r2, [r1, #MCATT1_OFFSET] + ldr r2, [r1, #MCATT1_OFFSET] + + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + ldr r2, =CONFIG_SYS_MCIO0_VAL + str r2, [r1, #MCIO0_OFFSET] + ldr r2, [r1, #MCIO0_OFFSET] + + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + ldr r2, =CONFIG_SYS_MCIO1_VAL + str r2, [r1, #MCIO1_OFFSET] + ldr r2, [r1, #MCIO1_OFFSET] + + /* */ + /* Step 2c: Write FLYCNFG FIXME: what's that???*/ + /* */ +@ldr r2, =CONFIG_SYS_FLYCNFG_VAL +@str r2, [r1, #FLYCNFG_OFFSET] +@str r2, [r1, #FLYCNFG_OFFSET] + + /* */ + /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ + /* */ + + /* Before accessing MDREFR we need a valid DRI field, so we set */ + /* this to power on defaults + DRI field. */ + + ldr r4, [r1, #MDREFR_OFFSET] + ldr r2, =0xFFF + bic r4, r4, r2 + + ldr r3, =CONFIG_SYS_MDREFR_VAL + and r3, r3, r2 + + orr r4,
Re: [U-Boot] [PATCH v2] mpc86xx: set the DDR BATs after calculating true DDR size
On Tue, Mar 30, 2010 at 12:02 PM, Becky Bruce bec...@kernel.crashing.org wrote: Can you test a board with a strange amount of RAM (1.5GB, or something), and see what happens with this patch? I really don't like leaving things this way. I put three 512MB sticks into bullwinkle, and got this: U-Boot 2010.03-rc1-6-g249f62d (Mar 30 2010 - 16:08:44) CPU: 8641D, Version: 2.0, (0x80900120) Core: E600 Core 0, Version: 2.2, (0x80040202) Clock Configuration: CPU:1500 MHz, MPX:500 MHz DDR:250 MHz (500 MT/s data rate), LBC:31.250 MHz L1:D-cache 32 KB enabled I-cache 32 KB enabled L2:512 KB enabled Board: MPC8641HPCN, Sys ID: 0x10, Sys Ver: 0x10, FPGA Ver: 0x22, vBank: 1 I2C: ready DRAM: 512 MB left unmapped DDR: 1.1 GB (DDR2, 64-bit, CL=4, ECC off) and here it hangs. So not only does it hang, but it appears there's a bug in print_size(). -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] jffs2, suen3: Fix compiler warning
Dear Heiko Schocher, In message 4baa041a.3000...@invitel.hu you wrote: $ ./MAKEALL suen3 jffs2_1pass.c: In function 'get_fl_mem': jffs2_1pass.c:399: warning: unused variable 'id' jffs2_1pass.c: In function 'get_node_mem': jffs2_1pass.c:423: warning: unused variable 'id' Signed-off-by: Heiko Schocher h...@denx.de --- - changes since v1: added comment from Wolfgang Denk fixed output fs/jffs2/jffs2_1pass.c | 37 ++--- 1 files changed, 22 insertions(+), 15 deletions(-) Applied. Sorry I missed this so long. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Who is the oldest inhabitant of this village? We haven't got one; we had one, but he died three weeks ago. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] Added serial loopback tests accessible via CLI and POST
Dear Michael Zaidman, In message 660c0f821003230641s5716a04cn2b15becf7c457...@mail.gmail.com you wrote: Then what is the uart[t]est command needed for? For two reasons: 1) It gets parameters such internal/external loopback and COM number while diag run uart performs only local loopback through all COMs. Thus, it can be used at production to perform external loopback tests. This does not fit into the POST framework then, it seems. 2) This test will be available even when compiled without POST for reasons of POST tests unavailability for particular cpu/board or specific board memory layout constrains. I don't like such chimera code. I don't get this. Where is the weak part needed? Either I have only one type of UART (then the weak is not needed as only onedriver is enabled), or I have both CPU specific and generic (16550 based) UARTs, in which case I eventually might ant to test _both_ of them (then the weak will not work). Currently, we have only CONFIG_SYS_POST_UART which will cause both files to be compiled in the case of mpc8xx or ppc4xx CPUs. Which will lead to the linker failure if no weak definition will be used. Do you mean we should do it at the makefile level by adding CONFIG_ specifing which file should be compiled and linked? I think this is a consequence of trying to squeeze soemthing into a framework which doesn't fit. POST and production test code should be kept separate. If they share common code, fine. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de You have the capacity to learn from mistakes. You'll learn a lot today. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] doc: Fix ramdisk examples in doc/uImage.FIT/multi.its
Dear Felix Radensky, In message 1269950533-898-1-git-send-email-fe...@embedded-sol.com you wrote: The ramdisk sections in doc/uImage.FIT/multi.its lack load address and entry point properties. Using examples from this file will result in unbootable image, u-boot will issue the following error messages: Can't get ramdisk subimage load address! Ramdisk image is corrupt or invalid This patch adds missing properties to ramdisk sections. Signed-off-by: Felix Radensky fe...@embedded-sol.com --- doc/uImage.FIT/multi.its |4 1 files changed, 4 insertions(+), 0 deletions(-) Applied, thanks. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de I used to be indecisive, now I'm not sure. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] ARM1176: TI: TNETV107X soc initial support
Dear Chemparathy, Cyril,
In message 8ffaa0bfc4e5374b8f85f65fe1f2bfa58ba44...@dlee02.ent.ti.com you
wrote:
+void lpsc_control(unsigned int id, int state)
+{
+ __lpsc_control(1, -1, id, state);
+}
+
+int lpsc_status(unsigned int id)
+{
+ return psc_reg_read(PSC_MDSTAT(id)) 0x1f;
+}
+
+void clk_enable(unsigned int id)
+{
+ lpsc_control(id, PSC_MDCTL_NEXT_ENABLE);
+}
+
+void clk_disable(unsigned int id)
+{
+ lpsc_control(id, PSC_MDCTL_NEXT_DISABLE);
+}
These should probably be inlined ?
Are you referring to lpsc_control(), or to clk_enable/clk_disable?
Both of them.
The former can be eliminated, I think.
The latter are used elsewhere. Are you recommending that I inline and move
to a header?
Yes. Assuming we really need sone one-line wrapper functions.
Best regards,
Wolfgang Denk
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Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
Real computer scientists despise the idea of actual hardware. Hard-
ware has limitations, software doesn't. It's a real shame that Turing
machines are so poor at I/O.
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Re: [U-Boot] [PATCH 3/3] TI: TNETV107X EVM initial support
Dear Chemparathy, Cyril, In message 8ffaa0bfc4e5374b8f85f65fe1f2bfa58babc...@dlee02.ent.ti.com you wrote: [...] +#define MTDPARTS_DEFAULT mtdparts=davinci_nand.0: \ + 1536k(uboot)ro, \ + 128k(params)ro, \ + 4m(kernel), \ + -(filesystem) Is davinci correct here? Yes, this SOC has the exact same controller as on Davinci, and therefore the NAND driver is reused. But you don't call this a Davinci-Board, or do you? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de There are three ways to get something done: (1) Do it yourself. (2) Hire someone to do it for you. (3) Forbid your kids to do it. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] Add initial support for Matrix Vision mvSMR board based on MPC5200B.
Dear Andre Schwarz,
In message 1269547381-16390-1-git-send-email-andre.schw...@matrix-vision.de
you wrote:
Add initial support for Matrix Vision mvSMR board based on MPC5200B.
Signed-off-by: Andre Schwarz andre.schw...@matrix-vision.de
...
diff --git a/board/matrix_vision/mvsmr/autoscript
b/board/matrix_vision/mvsmr/autoscript
new file mode 100644
index 000..abc082b
--- /dev/null
+++ b/board/matrix_vision/mvsmr/autoscript
The autoscr command has long been deprecated, so it makes little
sense to call a file autoscript.
+setenv boot24 bootm \${kernel_boot} \${mv_initrd_addr_ram}
+setenv ramkernel setenv kernel_boot \${loadaddr}
+setenv flashkernel setenv kernel_boot \${mv_kernel_addr}
+setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram}
\${mv_initrd_length}
You could write this like this:
setenv cpird 'cp ${mv_initrd_addr} ${mv_initrd_addr_ram} ${mv_initrd_length}'
which looks much cleaner to me.
+int mvsmr_get_mac(void)
+{
...
+ i2c_read(0x50, 0, 1, (unsigned char *)data, 6);
+
+ sprintf(mac, %02x:%02x:%02x:%02x:%02x:%02x,
+ data[0], data[1], data[2], data[3], data[4], data[5]);
+ setenv(ethaddr, mac);
Please use eth_setenv_enetaddr() instead.
+/*
+ * Supported commands
+ */
+#include config_cmd_default.h
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_I2C
You might want to keep the list sorted.
+#undef CONFIG_WATCHDOG
Don't undefine what is not defined anyway.
Best regards,
Wolfgang Denk
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
There's no sense in being precise when you don't even know what
you're talking about. -- John von Neumann
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[U-Boot] [PATCH] fix print_size printing fractional gigabyte numbers on 32-bit platforms
In print_size(), the math that calculates the fractional remainder of a number
used the same integer size as a physical address. However, the 10 * factor
of the algorithm means that a large number (e.g. 1.5GB) can overflow the
integer if we're running on a 32-bit system. Therefore, we need to
disassociate this function from the size of a physical address.
Signed-off-by: Timur Tabi ti...@freescale.com
---
include/common.h |2 +-
lib_generic/display_options.c |5 ++---
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/include/common.h b/include/common.h
index a133e34..4e77727 100644
--- a/include/common.h
+++ b/include/common.h
@@ -218,7 +218,7 @@ voidhang(void) __attribute__
((noreturn));
/* */
phys_size_t initdram (int);
intdisplay_options (void);
-void print_size (phys_size_t, const char *);
+void print_size(unsigned long long, const char *);
intprint_buffer (ulong addr, void* data, uint width, uint count, uint
linelen);
/* common/main.c */
diff --git a/lib_generic/display_options.c b/lib_generic/display_options.c
index 2dc2567..cafb603 100644
--- a/lib_generic/display_options.c
+++ b/lib_generic/display_options.c
@@ -43,10 +43,9 @@ int display_options (void)
* xxx GB, or xxx.y GB as needed; allow for optional trailing string
* (like \n)
*/
-void print_size (phys_size_t size, const char *s)
+void print_size(unsigned long long size, const char *s)
{
- ulong m = 0, n;
- phys_size_t d = 1 30;/* 1 GB */
+ unsigned long m = 0, n, d = 1 30 /* 1 GB */;
char c = 'G';
if (size d) { /* try MB */
--
1.6.5
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Re: [U-Boot] [PATCH 1/2 v2] net, fec_mxc: only setup the device enetaddr with eeprom value, if ethaddr is not setup
Hi Wolfgang, On 3/30/2010 1:34 PM, Wolfgang Denk wrote: Dear Heiko Schocher, In message4bb238e9.7060...@denx.de you wrote: if ethaddr is not setup in the environment, fill the device enetaddr with the contents of the eeprom, and only the device enetaddr, not the mac address registers! Tested on the magnesium board. Signed-off-by: Heiko Schocherh...@denx.de --- - changes since v1 posted here: http://lists.denx.de/pipermail/u-boot/2010-March/069192.html - splitted in two patches as Wolfgang suggested Thanks. Note that it would also have been an excellent idea to put the responsible custodian on Cc: drivers/net/fec_mxc.c |9 + 1 files changed, 5 insertions(+), 4 deletions(-) Applied, thanks. Ben, this is (as far as I see it) an undisputed bug fix, so I'm pulling this patch (and only this one from this series of 4) directly. Hope this is ok with you. Sorry for not wading into this conversation earlier. I have issues with this driver, in particular that it isn't truly a 'MULTI' driver. This came to my attention when I noticed that Heiko's changes reference the 'ethaddr' environment variable. Hopefully somebody will fix it properly. In any case, as you say, this fixes a real bug and doesn't make things worse. Good enough, I guess. Best regards, Wolfgang Denk thanks, Ben ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2 v2] net, fec_mxc: only setup the device enetaddr with eeprom value, if ethaddr is not setup
On Tuesday 30 March 2010 16:34:00 Wolfgang Denk wrote: Ben, this is (as far as I see it) an undisputed bug fix, so I'm pulling this patch (and only this one from this series of 4) directly. Hope this is ok with you. are people just ignoring my e-mails ? ive already pointed out multiple times why this is wrong and not what the current net standard is doing. -mike signature.asc Description: This is a digitally signed message part. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] fix print_size printing fractional gigabyte numbers on 32-bit platforms
Timur Tabi wrote:
In print_size(), the math that calculates the fractional remainder of a number
used the same integer size as a physical address. However, the 10 * factor
of the algorithm means that a large number (e.g. 1.5GB) can overflow the
integer if we're running on a 32-bit system. Therefore, we need to
disassociate this function from the size of a physical address.
Signed-off-by: Timur Tabi ti...@freescale.com
---
include/common.h |2 +-
lib_generic/display_options.c |5 ++---
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/include/common.h b/include/common.h
index a133e34..4e77727 100644
--- a/include/common.h
+++ b/include/common.h
@@ -218,7 +218,7 @@ void hang(void) __attribute__
((noreturn));
/* */
phys_size_t initdram (int);
int display_options (void);
-void print_size (phys_size_t, const char *);
+void print_size(unsigned long long, const char *);
int print_buffer (ulong addr, void* data, uint width, uint count, uint
linelen);
/* common/main.c */
diff --git a/lib_generic/display_options.c b/lib_generic/display_options.c
index 2dc2567..cafb603 100644
--- a/lib_generic/display_options.c
+++ b/lib_generic/display_options.c
@@ -43,10 +43,9 @@ int display_options (void)
* xxx GB, or xxx.y GB as needed; allow for optional trailing string
* (like \n)
*/
-void print_size (phys_size_t size, const char *s)
+void print_size(unsigned long long size, const char *s)
{
- ulong m = 0, n;
- phys_size_t d = 1 30;/* 1 GB */
+ unsigned long m = 0, n, d = 1 30 /* 1 GB */;
char c = 'G';
In changing d from phys_size_t to unsigned long, I think you're
introducing overflow in n * d (consider 5.5G rather than 1.5G).
Wouldn't a more straightforward fix, that doesn't affect the function
signature, be to just change 10 * to 10ULL *?
-Scott
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Re: [U-Boot] [PATCH] fix print_size printing fractional gigabyte numbers on 32-bit platforms
Scott Wood wrote: In changing d from phys_size_t to unsigned long, I think you're introducing overflow in n * d (consider 5.5G rather than 1.5G). Wouldn't a more straightforward fix, that doesn't affect the function signature, be to just change 10 * to 10ULL *? I don't see how that suggestion would make the code any different. Here's the expression: (10 * (size - (n * d)) + (d / 2) ) / d; I made 'size' into a u64, and I assume that the compiler will evaluate every other subexpression as a u64. That may be wrong. However, changing 10 to 10ULL makes the same assumption. I'll test 5.5GB and see what it does. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] fsl: improve the PIXIS code and fix a few bugs
On Wed, Mar 17, 2010 at 5:39 PM, Timur Tabi ti...@freescale.com wrote: Refactor and document the Freescale PIXIS code, used on most 85xx and 86xx boards. This makes the code easier to read and more flexible. This patch breaks all 5121, because I forgot to modify diu.c. I'll post a new version soon. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2 v2] net, fec_mxc: only setup the device enetaddr with eeprom value, if ethaddr is not setup
Wolfgang, On 3/30/2010 1:34 PM, Wolfgang Denk wrote: Dear Heiko Schocher, In message4bb238e9.7060...@denx.de you wrote: if ethaddr is not setup in the environment, fill the device enetaddr with the contents of the eeprom, and only the device enetaddr, not the mac address registers! Tested on the magnesium board. Signed-off-by: Heiko Schocherh...@denx.de --- - changes since v1 posted here: http://lists.denx.de/pipermail/u-boot/2010-March/069192.html - splitted in two patches as Wolfgang suggested Thanks. Note that it would also have been an excellent idea to put the responsible custodian on Cc: drivers/net/fec_mxc.c |9 + 1 files changed, 5 insertions(+), 4 deletions(-) Applied, thanks. Ben, this is (as far as I see it) an undisputed bug fix, so I'm pulling this patch (and only this one from this series of 4) directly. Hope this is ok with you. Hold on a second. This patch is wrong. As Mike has pointed out, the net library already gets the MAC address from the environment. The correct flow is: 1. Read from hardware in initialize() function 2. Read from environment in net/eth.c after initialize() 3. Give priority to the value in the environment if a conflict 4. Program hardware in the device's init() function. If somebody wants to subvert the 'design philosophy', the right way is to call eth_dev-init() in board code. regards, Ben ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] fix print_size printing fractional gigabyte numbers on 32-bit platforms
Timur Tabi wrote: Scott Wood wrote: In changing d from phys_size_t to unsigned long, I think you're introducing overflow in n * d (consider 5.5G rather than 1.5G). Wouldn't a more straightforward fix, that doesn't affect the function signature, be to just change 10 * to 10ULL *? I don't see how that suggestion would make the code any different. It would make the 10 * (...) product 64-bit regardless of phys_size_t, without changing the function signature (overflow is an internal implementation detail). Here's the expression: (10 * (size - (n * d)) + (d / 2) ) / d; I made 'size' into a u64, and I assume that the compiler will evaluate every other subexpression as a u64. That may be wrong. The n * d subexpression does not involve size, and thus will not be 64-bit. However, changing 10 to 10ULL makes the same assumption. The difference is that d remains phys_size_t, rather than being converted to unsigned long. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] fdt: Add fdt_del_node_and_alias helper
Hi Kumar,
Kumar Gala wrote:
Add a helper function that given an alias will delete both the node
the alias points to and the alias itself
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
I assume you will want to apply this with the 8xxx patch that uses it, so...
Acked-by: Gerald Van Baren vanba...@cideas.com
---
* Make alias param const
common/fdt_support.c | 13 +
include/fdt_support.h |2 ++
2 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index f89a3ee..0d0f513 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -757,3 +757,16 @@ int fdt_fixup_nor_flash_size(void *blob, int cs, u32
size)
return -1;
}
#endif
+
+void fdt_del_node_and_alias(void *blob, const char *alias)
+{
+ int off = fdt_path_offset(blob, alias);
+
+ if (off 0)
+ return;
+
+ fdt_del_node(blob, off);
+
+ off = fdt_path_offset(blob, /aliases);
+ fdt_delprop(blob, off, alias);
+}
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 0a9dd0d..5388c29 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -81,5 +81,7 @@ int fdt_resize(void *blob);
int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size);
+void fdt_del_node_and_alias(void *blob, const char *alias);
+
#endif /* ifdef CONFIG_OF_LIBFDT */
#endif /* ifndef __FDT_SUPPORT_H */
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Re: [U-Boot] [PATCH] fix print_size printing fractional gigabyte numbers on 32-bit platforms
Scott Wood wrote: It would make the 10 * (...) product 64-bit regardless of phys_size_t, without changing the function signature (overflow is an internal implementation detail). You are right that (n * d) is evaluated as a 32-bit integer: print_size(5905580032)= 6.35 GB However, changing 10 to 10ULL does not fix this. I think this is because we are both expecting integer sizes to commute across arithmetic operations. That is, I assumed that: u64 - (u32 * u32) would be treated as u64 - ((u64)u32 * u32) And you assumed that u64 * (u32 - u32) would be treated as u64 * (u32 - (u64) u32) Both appear to be wrong. If we want to treat (n * d) as a u64, we need to be explicit. Casting (n * d) to a u64 just doesn't work. We have to cast (or make) either 'n' or 'd' to a u64. I think the simplest approach is make 'd' into a u64. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] [v2] fix print_size printing fractional gigabyte numbers on 32-bit platforms
In print_size(), the math that calculates the fractional remainder of a number
used the same integer size as a physical address. However, the 10 * factor
of the algorithm means that a large number (e.g. 1.5GB) can overflow the
integer if we're running on a 32-bit system. Therefore, we need to
disassociate this function from the size of a physical address.
Signed-off-by: Timur Tabi ti...@freescale.com
---
include/common.h |2 +-
lib_generic/display_options.c |6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/common.h b/include/common.h
index a133e34..4e77727 100644
--- a/include/common.h
+++ b/include/common.h
@@ -218,7 +218,7 @@ voidhang(void) __attribute__
((noreturn));
/* */
phys_size_t initdram (int);
intdisplay_options (void);
-void print_size (phys_size_t, const char *);
+void print_size(unsigned long long, const char *);
intprint_buffer (ulong addr, void* data, uint width, uint count, uint
linelen);
/* common/main.c */
diff --git a/lib_generic/display_options.c b/lib_generic/display_options.c
index 2dc2567..da17a62 100644
--- a/lib_generic/display_options.c
+++ b/lib_generic/display_options.c
@@ -43,10 +43,10 @@ int display_options (void)
* xxx GB, or xxx.y GB as needed; allow for optional trailing string
* (like \n)
*/
-void print_size (phys_size_t size, const char *s)
+void print_size(unsigned long long size, const char *s)
{
- ulong m = 0, n;
- phys_size_t d = 1 30;/* 1 GB */
+ unsigned long m = 0, n;
+ unsigned long long d = 1 30; /* 1 GB */
char c = 'G';
if (size d) { /* try MB */
--
1.6.5
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Re: [U-Boot] [PATCH] fix print_size printing fractional gigabyte numbers on 32-bit platforms
Timur Tabi wrote: Scott Wood wrote: It would make the 10 * (...) product 64-bit regardless of phys_size_t, without changing the function signature (overflow is an internal implementation detail). You are right that (n * d) is evaluated as a 32-bit integer: print_size(5905580032)= 6.35 GB However, changing 10 to 10ULL does not fix this. It's not supposed to. There are two different overflows, 10*expr and n*d. Today, 10*expr overflows and n*d doesn't. With your patch, n*d overflows and 10*expr doesn't. I was suggesting a simple way to fix 10*expr without other changes. I think this is because we are both expecting integer sizes to commute across arithmetic operations. That is, I assumed that: u64 - (u32 * u32) would be treated as u64 - ((u64)u32 * u32) And you assumed that u64 * (u32 - u32) would be treated as u64 * (u32 - (u64) u32) I assumed no such thing. What I assumed was that the n*d overflow only matters if phys_size_t is 64-bit, because it should always be less than size. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] [v2] fix print_size printing fractional gigabyte numbers on 32-bit platforms
Timur Tabi wrote: In print_size(), the math that calculates the fractional remainder of a number used the same integer size as a physical address. However, the 10 * factor of the algorithm means that a large number (e.g. 1.5GB) can overflow the integer if we're running on a 32-bit system. Therefore, we need to disassociate this function from the size of a physical address. Signed-off-by: Timur Tabi ti...@freescale.com --- include/common.h |2 +- lib_generic/display_options.c |6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/common.h b/include/common.h index a133e34..4e77727 100644 --- a/include/common.h +++ b/include/common.h @@ -218,7 +218,7 @@ void hang(void) __attribute__ ((noreturn)); /* */ phys_size_t initdram (int); int display_options (void); -void print_size (phys_size_t, const char *); +void print_size(unsigned long long, const char *); As stated before, the overflow is an implementation detail. There's no reason to change the interface unless there's a desire to support printing sizes larger than phys_size_t, which is a distinct issue from the bugfix. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] [v2] fix print_size printing fractional gigabyte numbers on 32-bit platforms
Scott Wood wrote: As stated before, the overflow is an implementation detail. There's no reason to change the interface unless there's a desire to support printing sizes larger than phys_size_t, which is a distinct issue from the bugfix. You are correct. I'll post a new patch. However, there's a lot of value in being able to print 4GB numbers on a 32-bit system, and it seems silly to make two patches. I'll post a new patch, and Wolfgang can decide what he wants. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] [v3] fix print_size printing fractional gigabyte numbers on 32-bit platforms
In print_size(), the math that calculates the fractional remainder of a number
used the same integer size as a physical address. However, the 10 * factor
of the algorithm means that a large number (e.g. 1.5GB) can overflow the
integer if we're running on a 32-bit system. Therefore, we need to
disassociate this function from the size of a physical address.
Signed-off-by: Timur Tabi ti...@freescale.com
---
lib_generic/display_options.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/lib_generic/display_options.c b/lib_generic/display_options.c
index 2dc2567..08a7914 100644
--- a/lib_generic/display_options.c
+++ b/lib_generic/display_options.c
@@ -45,8 +45,8 @@ int display_options (void)
*/
void print_size (phys_size_t size, const char *s)
{
- ulong m = 0, n;
- phys_size_t d = 1 30;/* 1 GB */
+ unsigned long m = 0, n;
+ unsigned long long d = 1 30; /* 1 GB */
char c = 'G';
if (size d) { /* try MB */
--
1.6.5
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[U-Boot] [PATCH] allow print_size to print large numbers on 32-bit systems
Modify print_size() so that it can accept numbers larger than 4GB on 32-bit
systems.
Signed-off-by: Timur Tabi ti...@freescale.com
---
include/common.h |2 +-
lib_generic/display_options.c |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/common.h b/include/common.h
index a133e34..4e77727 100644
--- a/include/common.h
+++ b/include/common.h
@@ -218,7 +218,7 @@ voidhang(void) __attribute__
((noreturn));
/* */
phys_size_t initdram (int);
intdisplay_options (void);
-void print_size (phys_size_t, const char *);
+void print_size(unsigned long long, const char *);
intprint_buffer (ulong addr, void* data, uint width, uint count, uint
linelen);
/* common/main.c */
diff --git a/lib_generic/display_options.c b/lib_generic/display_options.c
index 08a7914..da17a62 100644
--- a/lib_generic/display_options.c
+++ b/lib_generic/display_options.c
@@ -43,7 +43,7 @@ int display_options (void)
* xxx GB, or xxx.y GB as needed; allow for optional trailing string
* (like \n)
*/
-void print_size (phys_size_t size, const char *s)
+void print_size(unsigned long long size, const char *s)
{
unsigned long m = 0, n;
unsigned long long d = 1 30; /* 1 GB */
--
1.6.5
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[U-Boot] [PATCH v5] nios2: add altera cf reset
This patch toggles power to reset the cf card.
Signed-off-by: Thomas Chou tho...@wytron.com.tw
---
more checkpatch.pl fixes
board/altera/common/cfide.c | 33 +
1 files changed, 33 insertions(+), 0 deletions(-)
create mode 100644 board/altera/common/cfide.c
diff --git a/board/altera/common/cfide.c b/board/altera/common/cfide.c
new file mode 100644
index 000..40d6a12
--- /dev/null
+++ b/board/altera/common/cfide.c
@@ -0,0 +1,33 @@
+/*
+ * Altera CF drvier
+ *
+ * (C) Copyright 2010, Thomas Chou tho...@wytron.com.tw
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include common.h
+#include asm/io.h
+
+#if defined(CONFIG_IDE_RESET) defined(CONFIG_SYS_CF_CTL_BASE)
+/* ide_set_reset for Altera CF interface */
+#define ALTERA_CF_CTL_STATUS 0
+#define ALTERA_CF_IDE_CTL 4
+#define ALTERA_CF_CTL_STATUS_PRESENT_MSK (0x1)
+#define ALTERA_CF_CTL_STATUS_POWER_MSK (0x2)
+#define ALTERA_CF_CTL_STATUS_RESET_MSK (0x4)
+#define ALTERA_CF_CTL_STATUS_IRQ_EN_MSK(0x8)
+#define ALTERA_CF_IDE_CTL_IRQ_EN_MSK (0x1)
+
+void ide_set_reset(int idereset)
+{
+ int i;
+ writel(idereset ? ALTERA_CF_CTL_STATUS_RESET_MSK :
+ ALTERA_CF_CTL_STATUS_POWER_MSK,
+ CONFIG_SYS_CF_CTL_BASE + ALTERA_CF_CTL_STATUS);
+ /* wait 500 ms for power to stabilize */
+ for (i = 0; i 500; i++)
+ udelay(1000);
+}
+#endif
--
1.6.6.1
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[U-Boot] [PATCH 1/5] nios2: add nios2-generic board
This is a generic approach to port u-boot for nios2 boards. You may find the usage of this approach on the nioswiki, http://nioswiki.com/DasUBoot In order to better support MMU and NOMMU targets, we will use virtual addressing in the config file. All references to devices except for the main memory (sdram), should be mapped to uncached (bypass), IO region. While the main memory should use cached, kernel region. In stead of editing the hex number of base address, we will use the resource header file generated with Altera SOPC tools. For example the SMC device def will become, #define CONFIG_SMC9_BASE((LAN91C111_BASE + \ LAN91C111_LAN91C111_REGISTERS_OFFSET) \ | IO_REGION_BASE) /* Base addr */ where the LAN91C111_xxx will be defined in the SOPC generated header file. Then when you reassign the base address or turn on/off the MMU, you will only need to regenerate the resource header file. Signed-off-by: Thomas Chou tho...@wytron.com.tw --- board/altera/nios2-generic/Makefile| 60 board/altera/nios2-generic/config.mk | 32 +++ board/altera/nios2-generic/nios2-generic.c | 73 +++ board/altera/nios2-generic/text_base.S | 21 + board/altera/nios2-generic/u-boot.lds | 136 5 files changed, 322 insertions(+), 0 deletions(-) create mode 100644 board/altera/nios2-generic/Makefile create mode 100644 board/altera/nios2-generic/config.mk create mode 100644 board/altera/nios2-generic/nios2-generic.c create mode 100644 board/altera/nios2-generic/text_base.S create mode 100644 board/altera/nios2-generic/u-boot.lds diff --git a/board/altera/nios2-generic/Makefile b/board/altera/nios2-generic/Makefile new file mode 100644 index 000..2a6f69b --- /dev/null +++ b/board/altera/nios2-generic/Makefile @@ -0,0 +1,60 @@ +# +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# (C) Copyright 2010, Thomas Chou tho...@wytron.com.tw +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB= $(obj)lib$(BOARD).a + +COBJS-y:= $(BOARD).o +COBJS-$(CONFIG_CMD_IDE) += ../common/cfide.o +COBJS-$(CONFIG_EPLED) += ../common/epled.o +COBJS-$(CONFIG_GPIOLED) += ../common/gpioled.o +COBJS-$(CONFIG_SEVENSEG) += ../common/sevenseg.o + +SOBJS-y:= text_base.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB):$(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/altera/nios2-generic/config.mk b/board/altera/nios2-generic/config.mk new file mode 100644 index 000..cb7c68e --- /dev/null +++ b/board/altera/nios2-generic/config.mk @@ -0,0 +1,32 @@ +# +# (C) Copyright 2005, Psyent Corporation www.psyent.com +# Scott McNutt smcn...@psyent.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# we get text_base from board config header, so do not use this +#TEXT_BASE = do-not-use-me + +PLATFORM_CPPFLAGS += -mno-hw-div
[U-Boot] [PATCH 3/5] nios2: add Altera EP3C120 board
This patch supports the Altera CycloneIII Nios dev board using the example FPGA design at http://nioswiki.com/Linux. Signed-off-by: Thomas Chou tho...@wytron.com.tw --- MAINTAINERS |1 + MAKEALL |1 + Makefile |2 +- board/altera/nios2-generic/default_mmu.h | 371 include/configs/EP3C120.h| 394 ++ 5 files changed, 768 insertions(+), 1 deletions(-) create mode 100644 board/altera/nios2-generic/default_mmu.h create mode 100644 include/configs/EP3C120.h diff --git a/MAINTAINERS b/MAINTAINERS index 1f33146..30ac451 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -851,6 +851,7 @@ Scott McNutt smcn...@psyent.com EP1S10 Nios-II EP1S40 Nios-II EP2C35 Nios-II + EP3C120 Nios-II # # MicroBlaze Systems: # diff --git a/MAKEALL b/MAKEALL index 8ab3358..886d608 100755 --- a/MAKEALL +++ b/MAKEALL @@ -824,6 +824,7 @@ LIST_nios2=\ PCI5441 \ PK1C20 \ EP2C35 \ + EP3C120 \ # diff --git a/Makefile b/Makefile index a27b002..5b3c589 100644 --- a/Makefile +++ b/Makefile @@ -3534,7 +3534,7 @@ PCI5441_config : unconfig @$(MKCONFIG) PCI5441 nios2 nios2 pci5441 psyent # nios2 generic boards -NIOS2_GENERIC = EP2C35 +NIOS2_GENERIC = EP2C35 EP3C120 $(NIOS2_GENERIC:%=%_config) : unconfig @$(MKCONFIG) $(@:_config=) nios2 nios2 nios2-generic altera diff --git a/board/altera/nios2-generic/default_mmu.h b/board/altera/nios2-generic/default_mmu.h new file mode 100644 index 000..dc14dc2 --- /dev/null +++ b/board/altera/nios2-generic/default_mmu.h @@ -0,0 +1,371 @@ +#ifndef _ALTERA_LINUX_CPU_H_ +#define _ALTERA_LINUX_CPU_H_ + +/* Note, this file was manually edited after generation + * since the multiple inclusion proctetion macro above collides with + * include/linux/cpu.h + */ + +/* + * This file was automatically generated by the swinfo2header utility. + * + * Created from SOPC Builder system 'nios2_linux_3c120_125mhz_sys_sopc' in + * file 'default//nios2_linux_3c120_125mhz_sys_sopc.sopcinfo'. + */ + +/* + * This file contains macros for module 'linux_cpu' and devices + * connected to the following masters: + * instruction_master + * tightly_coupled_instruction_master_0 + * data_master + * tightly_coupled_data_master_0 + * + * Do not #include this header file and another header file created for a + * different module or master group at the same time. + * Doing so may result in duplicate #defines. + * Instead, use the system header file which has #defines with unique names. + */ + +/* + * Macros for module 'linux_cpu', class 'altera_nios2'. + * The macros have no prefix. + */ +#define CPU_IMPLEMENTATION fast +#define ICACHE_LINE_SIZE 32 +#define ICACHE_LINE_SIZE_LOG2 5 +#define ICACHE_SIZE 32768 +#define DCACHE_LINE_SIZE 32 +#define DCACHE_LINE_SIZE_LOG2 5 +#define DCACHE_SIZE 32768 +#define INITDA_SUPPORTED +#define FLUSHDA_SUPPORTED +#define HAS_JMPI_INSTRUCTION +#define MMU_PRESENT +#define KERNEL_REGION_BASE 0xc000 +#define IO_REGION_BASE 0xe000 +#define KERNEL_MMU_REGION_BASE 0x8000 +#define USER_REGION_BASE 0x0 +#define PROCESS_ID_NUM_BITS 8 +#define TLB_NUM_WAYS 16 +#define TLB_PTR_SZ 7 +#define TLB_NUM_ENTRIES 128 +#define FAST_TLB_MISS_EXCEPTION_ADDR 0xc7fff400 +#define EXCEPTION_ADDR 0xd020 +#define RESET_ADDR 0xc280 +#define BREAK_ADDR 0xc7fff820 +#define HAS_DEBUG_STUB +#define HAS_DEBUG_CORE 1 +#define HAS_ILLEGAL_INSTRUCTION_EXCEPTION +#define HAS_ILLEGAL_MEMORY_ACCESS_EXCEPTION +#define HAS_EXTRA_EXCEPTION_INFO +#define CPU_ID_SIZE 1 +#define CPU_ID_VALUE 0x0 +#define HARDWARE_DIVIDE_PRESENT 1 +#define HARDWARE_MULTIPLY_PRESENT 1 +#define HARDWARE_MULX_PRESENT 0 +#define INST_ADDR_WIDTH 29 +#define DATA_ADDR_WIDTH 29 + +/* + * Macros for device 'cfi_flash_64m', class 'altera_avalon_cfi_flash' + * The macros are prefixed with 'CFI_FLASH_64M_'. + * The prefix is the slave descriptor. + */ +#define CFI_FLASH_64M_BASE 0x0 +#define CFI_FLASH_64M_SPAN 67108864u +#define CFI_FLASH_64M_SETUP_VALUE 75 +#define CFI_FLASH_64M_WAIT_VALUE 35 +#define CFI_FLASH_64M_HOLD_VALUE 1 +#define CFI_FLASH_64M_TIMING_UNITS ns +#define CFI_FLASH_64M_SIZE 67108864u + +/* + * Macros for device 'fast_tlb_miss_ram_1k', class 'altera_avalon_onchip_memory2' + * The macros are prefixed with 'FAST_TLB_MISS_RAM_1K_'. + * The prefix is the slave descriptor. + */ +#define FAST_TLB_MISS_RAM_1K_BASE 0x7fff400 +#define FAST_TLB_MISS_RAM_1K_SPAN 1024u +#define FAST_TLB_MISS_RAM_1K_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 +#define FAST_TLB_MISS_RAM_1K_INIT_CONTENTS_FILE fast_tlb_miss_ram_1k +#define
[U-Boot] [PATCH 5/5] nios2: fix no flash, add nand and mmc init in board.c
This patch fixes error when CONFIG_SYS_NO_FLASH. And adds nand flash and mmc initialization, Signed-off-by: Thomas Chou tho...@wytron.com.tw --- lib_nios2/board.c | 14 ++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/lib_nios2/board.c b/lib_nios2/board.c index 311d66c..d5f6c14 100644 --- a/lib_nios2/board.c +++ b/lib_nios2/board.c @@ -100,7 +100,9 @@ void board_init (void) bd = gd-bd; bd-bi_memstart = CONFIG_SYS_SDRAM_BASE; bd-bi_memsize = CONFIG_SYS_SDRAM_SIZE; +#ifndef CONFIG_SYS_NO_FLASH bd-bi_flashstart = CONFIG_SYS_FLASH_BASE; +#endif #ifdefined(CONFIG_SYS_SRAM_BASE) defined(CONFIG_SYS_SRAM_SIZE) bd-bi_sramstart= CONFIG_SYS_SRAM_BASE; bd-bi_sramsize = CONFIG_SYS_SRAM_SIZE; @@ -119,8 +121,20 @@ void board_init (void) /* The Malloc area is immediately below the monitor copy in RAM */ mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN); +#ifndef CONFIG_SYS_NO_FLASH WATCHDOG_RESET (); bd-bi_flashsize = flash_init(); +#endif + +#ifdef CONFIG_CMD_NAND + puts(NAND: ); + nand_init(); +#endif + +#ifdef CONFIG_GENERIC_MMC + puts(MMC: ); + mmc_initialize(bd); +#endif WATCHDOG_RESET (); env_relocate(); -- 1.6.6.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/5] nios2: add Altera EP2C35 board
This patch supports the Altera CycloneII Nios dev board using the example FPGA design at http://nioswiki.com/Linux. Signed-off-by: Thomas Chou tho...@wytron.com.tw --- MAINTAINERS |1 + MAKEALL |1 + Makefile |6 + board/altera/nios2-generic/2c35_cf.h | 757 ++ include/configs/EP2C35.h | 372 + 5 files changed, 1137 insertions(+), 0 deletions(-) create mode 100644 board/altera/nios2-generic/2c35_cf.h create mode 100644 include/configs/EP2C35.h diff --git a/MAINTAINERS b/MAINTAINERS index bb03f17..1f33146 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -850,6 +850,7 @@ Scott McNutt smcn...@psyent.com EP1C20 Nios-II EP1S10 Nios-II EP1S40 Nios-II + EP2C35 Nios-II # # MicroBlaze Systems: # diff --git a/MAKEALL b/MAKEALL index a88c31e..8ab3358 100755 --- a/MAKEALL +++ b/MAKEALL @@ -823,6 +823,7 @@ LIST_nios2=\ EP1S40 \ PCI5441 \ PK1C20 \ + EP2C35 \ # diff --git a/Makefile b/Makefile index f5b556c..a27b002 100644 --- a/Makefile +++ b/Makefile @@ -3533,6 +3533,12 @@ PK1C20_config : unconfig PCI5441_config : unconfig @$(MKCONFIG) PCI5441 nios2 nios2 pci5441 psyent +# nios2 generic boards +NIOS2_GENERIC = EP2C35 + +$(NIOS2_GENERIC:%=%_config) : unconfig + @$(MKCONFIG) $(@:_config=) nios2 nios2 nios2-generic altera + # ## Microblaze # diff --git a/board/altera/nios2-generic/2c35_cf.h b/board/altera/nios2-generic/2c35_cf.h new file mode 100644 index 000..a08b35c --- /dev/null +++ b/board/altera/nios2-generic/2c35_cf.h @@ -0,0 +1,757 @@ +#ifndef _ALTERA_2C35_CF_FPGA_H_ +#define _ALTERA_2C35_CF_FPGA_H_ + +/* + * This file was automatically generated by the swinfo2header utility. + * + * Created from SOPC Builder system 'NiosII_cycloneII_2c35_full_featured_sopc' in + * file './NiosII_cycloneII_2c35_full_featured_sopc.sopcinfo'. + */ + +/* + * This file contains macros for module 'cpu' and devices + * connected to the following masters: + * instruction_master + * tightly_coupled_instruction_master_0 + * data_master + * tightly_coupled_data_master_0 + * + * Do not include this header file and another header file created for a + * different module or master group at the same time. + * Doing so may result in duplicate macro names. + * Instead, use the system header file which has macros with unique names. + */ + +/* + * Macros for module 'cpu', class 'altera_nios2'. + * The macros have no prefix. + */ +#define CPU_IMPLEMENTATION fast +#define BIG_ENDIAN 0 +#define CPU_FREQ 8500 +#define ICACHE_LINE_SIZE 32 +#define ICACHE_LINE_SIZE_LOG2 5 +#define ICACHE_SIZE 4096 +#define DCACHE_LINE_SIZE 32 +#define DCACHE_LINE_SIZE_LOG2 5 +#define DCACHE_SIZE 2048 +#define INITDA_SUPPORTED +#define FLUSHDA_SUPPORTED +#define HAS_JMPI_INSTRUCTION +#define MMU_PRESENT +#define KERNEL_REGION_BASE 0xc000 +#define IO_REGION_BASE 0xe000 +#define KERNEL_MMU_REGION_BASE 0x8000 +#define USER_REGION_BASE 0x0 +#define PROCESS_ID_NUM_BITS 10 +#define TLB_NUM_WAYS 16 +#define TLB_NUM_WAYS_LOG2 4 +#define TLB_PTR_SZ 7 +#define TLB_NUM_ENTRIES 128 +#define FAST_TLB_MISS_EXCEPTION_ADDR 0xc800 +#define EXCEPTION_ADDR 0xc620 +#define RESET_ADDR 0xc000 +#define BREAK_ADDR 0xc2120020 +#define HAS_DEBUG_STUB +#define HAS_DEBUG_CORE 1 +#define HAS_ILLEGAL_INSTRUCTION_EXCEPTION +#define HAS_ILLEGAL_MEMORY_ACCESS_EXCEPTION +#define HAS_EXTRA_EXCEPTION_INFO +#define CPU_ID_SIZE 1 +#define CPU_ID_VALUE 0x0 +#define HARDWARE_DIVIDE_PRESENT 0 +#define HARDWARE_MULTIPLY_PRESENT 1 +#define HARDWARE_MULX_PRESENT 0 +#define INST_ADDR_WIDTH 28 +#define DATA_ADDR_WIDTH 28 +#define NUM_OF_SHADOW_REG_SETS 0 + +/* + * Macros for device 'ext_flash', class 'altera_avalon_cfi_flash' + * The macros are prefixed with 'EXT_FLASH_'. + * The prefix is the slave descriptor. + */ +#define EXT_FLASH_COMPONENT_TYPE altera_avalon_cfi_flash +#define EXT_FLASH_COMPONENT_NAME ext_flash +#define EXT_FLASH_BASE 0x0 +#define EXT_FLASH_SPAN 16777216 +#define EXT_FLASH_END 0xff +#define EXT_FLASH_SETUP_VALUE 45 +#define EXT_FLASH_WAIT_VALUE 160 +#define EXT_FLASH_HOLD_VALUE 35 +#define EXT_FLASH_TIMING_UNITS ns +#define EXT_FLASH_SIZE 16777216 +#define EXT_FLASH_MEMORY_INFO_MEM_INIT_DATA_WIDTH 8 +#define EXT_FLASH_MEMORY_INFO_HAS_BYTE_LANE 0 +#define EXT_FLASH_MEMORY_INFO_IS_FLASH 1 +#define EXT_FLASH_MEMORY_INFO_GENERATE_DAT_SYM 1 +#define EXT_FLASH_MEMORY_INFO_GENERATE_FLASH 1 +#define
[U-Boot] [PATCH] nios2: Set CONFIG_SYS_HZ to 1000 all nios2 boards.
CONFIG_SYS_HZ was being calculated (incorrectly) in nios2 configuration headers. Updated comments to accurately describe timebase macros. Signed-off-by: Scott McNutt smcn...@psyent.com --- include/configs/EP1C20.h | 14 -- include/configs/EP1S10.h | 14 -- include/configs/EP1S40.h | 14 -- include/configs/PCI5441.h | 14 -- include/configs/PK1C20.h | 14 -- 5 files changed, 40 insertions(+), 30 deletions(-) diff --git a/include/configs/EP1C20.h b/include/configs/EP1C20.h index dc82e54..3920d35 100644 --- a/include/configs/EP1C20.h +++ b/include/configs/EP1C20.h @@ -124,14 +124,16 @@ * TIMEBASE -- * * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. + * registers, the interrupt frequency can be reduced using TMRCNT. + * If the default period is acceptable, TMRCNT can be left undefined. + * TMRMS represents the desired mecs per tick (msecs per interrupt). *--*/ +#define CONFIG_SYS_HZ 1000/* Always 1000 */ #define CONFIG_SYS_NIOS_TMRBASE0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) +#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num*/ +#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/ +#define CONFIG_SYS_NIOS_TMRCNT \ + (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) /* * STATUS LED -- Provides a simple blinking led. For Nios2 each board diff --git a/include/configs/EP1S10.h b/include/configs/EP1S10.h index 498f26d..bfbf8c1 100644 --- a/include/configs/EP1S10.h +++ b/include/configs/EP1S10.h @@ -119,14 +119,16 @@ * TIMEBASE -- * * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. + * registers, the interrupt frequency can be reduced using TMRCNT. + * If the default period is acceptable, TMRCNT can be left undefined. + * TMRMS represents the desired mecs per tick (msecs per interrupt). *--*/ +#define CONFIG_SYS_HZ 1000/* Always 1000 */ #define CONFIG_SYS_NIOS_TMRBASE0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) +#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/ +#define CONFIG_SYS_NIOS_TMRCNT \ + (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) /* * STATUS LED -- Provides a simple blinking led. For Nios2 each board diff --git a/include/configs/EP1S40.h b/include/configs/EP1S40.h index 4ad65d8..4d905fe 100644 --- a/include/configs/EP1S40.h +++ b/include/configs/EP1S40.h @@ -119,14 +119,16 @@ * TIMEBASE -- * * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. + * registers, the interrupt frequency can be reduced using TMRCNT. + * If the default period is acceptable, TMRCNT can be left undefined. + * TMRMS represents the desired mecs per tick (msecs per interrupt). *--*/ +#define CONFIG_SYS_HZ 1000/* Always 1000 */ #define CONFIG_SYS_NIOS_TMRBASE0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) +#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec) */ +#define CONFIG_SYS_NIOS_TMRCNT \ +
[U-Boot] [PATCH] nios2: Fix AMDLV065D flash write bug in altera board common tree.
Signed-off-by: Scott McNutt smcn...@psyent.com --- board/altera/common/AMDLV065D.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/board/altera/common/AMDLV065D.c b/board/altera/common/AMDLV065D.c index 72b0a9f..7a1b4d3 100644 --- a/board/altera/common/AMDLV065D.c +++ b/board/altera/common/AMDLV065D.c @@ -172,7 +172,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) writeb (0xaa, cmd); writeb (0x55, cmd); writeb (0xa0, cmd); - writeb (dst, b); + writeb (b, dst); /* Verify write */ start = get_timer (0); -- 1.6.0.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] s5p6442: Support Samsung s5p6442 SoC
Dear Wolfgang Denk, On 31 March 2010 06:00, Wolfgang Denk w...@denx.de wrote: Dear Joonyoung Shim, In message 4bb016dc.5000...@samsung.com you wrote: This patch adds support s5p6442 SoC. The s5p6442 SoC is ARM1176 processor. Cc: Minkyu Kang mk7.k...@samsung.com Cc: Kyungmin Park kyungmin.p...@samsung.com Signed-off-by: Joonyoung Shim jy0922.s...@samsung.com ... +#define S5P6442_PWR_CFG 0xE010C000 ... +#define S5P6442_EINT_WAKEUP_MASK 0xE010C004 +#define S5P6442_WAKEUP_MASK 0xE010C008 +#define S5P6442_PWR_MODE 0xE010C00C +#define S5P6442_PWR_MODE_SLEEP (1 2) +#define S5P6442_NORMAL_CFG 0xE010C010 +#define S5P6442_IDLE_CFG 0xE010C020 +#define S5P6442_STOP_CFG 0xE010C030 +#define S5P6442_STOP_MEM_CFG 0xE010C034 +#define S5P6442_SLEEP_CFG 0xE010C040 +#define S5P6442_OSC_FREQ 0xE010C100 +#define S5P6442_OSC_STABLE 0xE010C104 +#define S5P6442_PWR_STABLE 0xE010C108 +#define S5P6442_MTC_STABLE 0xE010C110 +#define S5P6442_CLAMP_STABLE 0xE010C114 +#define S5P6442_WAKEUP_STAT 0xE010C200 +#define S5P6442_OTHERS 0xE010E000 +#define S5P6442_OTHERS_SYSCON_INT_DISABLE (1 0) +#define S5P6442_MIE_CONTROL 0xE010E800 +#define S5P6442_HDMI_CONTROL 0xE010E804 +#define S5P6442_USB_PHY_CON 0xE010E80C +#define S5P6442_DAC_CONTROL 0xE010E810 +#define S5P6442_MIPI_DPHY_CONTROL 0xE010E814 +#define S5P6442_ADC_CONTROL 0xE010E818 +#define S5P6442_PS_HOLD_CONTROL 0xE010E81C +#define S5P6442_PS_HOLD_DIR_OUTPUT (1 9) +#define S5P6442_PS_HOLD_DIR_INPUT (0 9) +#define S5P6442_PS_HOLD_DATA_HIGH (1 8) +#define S5P6442_PS_HOLD_DATA_LOW (0 8) +#define S5P6442_PS_HOLD_OUT_EN (1 0) +#define S5P6442_INFORM0 0xE010F000 +#define S5P6442_INFORM1 0xE010F004 +#define S5P6442_INFORM2 0xE010F008 +#define S5P6442_INFORM3 0xE010F00C +#define S5P6442_INFORM4 0xE010F010 +#define S5P6442_INFORM5 0xE010F014 +#define S5P6442_INFORM6 0xE010F018 +#define S5P6442_INFORM7 0xE010F01C Please use C structs to describe these registers. These registers are used at asm code. So, can't make C struct. But, It seemed to there are defined unused registers also. Joonyoung, Please remove unused defines. Thanks Minkyu Kang -- from. prom. www.promsoft.net ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] nios2: Set CONFIG_SYS_HZ to 1000 all nios2 boards.
So it might be cleaner to let user define the HZ as the actual tick rate and increase the tick count by one in the tmr_isr. This was discussed/debated thoroughly over the past year: CONFIG_SYS_HZ at 1000 is mandatory. -timestamp += CONFIG_SYS_NIOS_TMRMS; +timestamp++; This means that each interrupt is exactly 1 msec. That's not what was intended and not what was implemented Forcing the interrupt period to 1 msec is an unnecessary constraint. If you want the isr to increment the timestamp by 1, then set CONFIG_SYS_NIOS_TMRMS to 1 ... and set your timer accordingly. --Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] fdt: Add fdt_del_node_and_alias helper
On Mar 30, 2010, at 5:20 PM, Gerald Van Baren wrote: Hi Kumar, Kumar Gala wrote: Add a helper function that given an alias will delete both the node the alias points to and the alias itself Signed-off-by: Kumar Gala ga...@kernel.crashing.org I assume you will want to apply this with the 8xxx patch that uses it, so... Acked-by: Gerald Van Baren vanba...@cideas.com Yep, thanks. - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] nios2: pass command line and initrd to linux in bootm.c
Thomas,
Applied.
Theank you,
--Scott
Thomas Chou wrote:
This patch adds bootargs passing to nios2 linux.
The args passing is enabled with,
r4 : 'NIOS' magic
r5 : pointer to initrd start
r6 : pointer to initrd end
r7 : pointer to command line
Signed-off-by: Thomas Chou tho...@wytron.com.tw
---
lib_nios2/bootm.c | 19 ---
1 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/lib_nios2/bootm.c b/lib_nios2/bootm.c
index 675bfac..5d25edf 100644
--- a/lib_nios2/bootm.c
+++ b/lib_nios2/bootm.c
@@ -26,21 +26,26 @@
#include asm/byteorder.h
#include asm/cache.h
+#define NIOS_MAGIC 0x534f494e /* enable command line and initrd passing */
+
int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
{
- void (*kernel)(void) = (void (*)(void))images-ep;
+ void (*kernel)(int, int, int, char *) = (void *)images-ep;
+ char *commandline = getenv(bootargs);
+ ulong initrd_start = images-rd_start;
+ ulong initrd_end = images-rd_end;
if ((flag != 0) (flag != BOOTM_STATE_OS_GO))
return 1;
/* flushes data and instruction caches before calling the kernel */
- flush_dcache (0,CONFIG_SYS_DCACHE_SIZE);
- flush_icache (0,CONFIG_SYS_ICACHE_SIZE);
+ disable_interrupts();
+ flush_dcache((ulong)kernel, CONFIG_SYS_DCACHE_SIZE);
+ flush_icache((ulong)kernel, CONFIG_SYS_ICACHE_SIZE);
- /* For now we assume the Microtronix linux ... which only
- * needs to be called ;-)
- */
- kernel ();
+ debug(bootargs=%s @ 0x%lx\n, commandline, (ulong)commandline);
+ debug(initrd=0x%lx-0x%lx\n, (ulong)initrd_start, (ulong)initrd_end);
+ kernel(NIOS_MAGIC, initrd_start, initrd_end, commandline);
/* does not return */
return 1;
___
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Re: [U-Boot] [PATCH] nios2: Set CONFIG_SYS_HZ to 1000 all nios2 boards.
On 03/31/2010 10:09 AM, Scott McNutt wrote: So it might be cleaner to let user define the HZ as the actual tick rate and increase the tick count by one in the tmr_isr. This was discussed/debated thoroughly over the past year: CONFIG_SYS_HZ at 1000 is mandatory. -timestamp += CONFIG_SYS_NIOS_TMRMS; +timestamp++; This means that each interrupt is exactly 1 msec. That's not what was intended and not what was implemented Forcing the interrupt period to 1 msec is an unnecessary constraint. If you want the isr to increment the timestamp by 1, then set CONFIG_SYS_NIOS_TMRMS to 1 ... and set your timer accordingly. - Hi Scott, Thanks for the explanation. I will set HZ to 1000 and TMRMS to 1. I tried to follow your patch nios2: Set CONFIG_SYS_HZ to 1000 all nios2 boards. But got cfi flash buffer write timeout on EP2C35 board. If I set TMRMS to 1, it works with HZ at 100, 1000 and 2000. Best regards, Thomas ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] net: add opencore 10/100 ethernet mac driver
Hi Wolfgang, Do we have a network drivers custodian? ... or should I just handle this patch through the nios repository? I'm guessing that this will only be used with nios2 in the near term. I'm not sure if any Microblaze (Xilinx) folks have worked with this -- perhaps Michal can comment? Regards, --Scott Thomas Chou wrote: This patch ports the opencore 10/100 ethernet mac driver ethoc.c from linux kernel to u-boot. Signed-off-by: Thomas Chou tho...@wytron.com.tw --- drivers/net/Makefile |1 + drivers/net/ethoc.c | 533 ++ include/netdev.h |1 + 3 files changed, 535 insertions(+), 0 deletions(-) create mode 100644 drivers/net/ethoc.c diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 1ec0ba1..0e68e52 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -39,6 +39,7 @@ COBJS-$(CONFIG_E1000) += e1000.o COBJS-$(CONFIG_EEPRO100) += eepro100.o COBJS-$(CONFIG_ENC28J60) += enc28j60.o COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o +COBJS-$(CONFIG_ETHOC) += ethoc.o COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o COBJS-$(CONFIG_FTMAC100) += ftmac100.o diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c new file mode 100644 index 000..c1eb239 --- /dev/null +++ b/drivers/net/ethoc.c @@ -0,0 +1,533 @@ +/* + * Opencore 10/100 ethernet mac driver + * + * Copyright (C) 2007-2008 Avionic Design Development GmbH + * Copyright (C) 2008-2009 Avionic Design GmbH + * Thierry Reding thierry.red...@avionic-design.de + * Copyright (C) 2010 Thomas Chou tho...@wytron.com.tw + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include common.h +#include command.h +#include malloc.h +#include net.h +#include miiphy.h +#include asm/io.h +#include asm/cache.h + +/* register offsets */ +#define MODER 0x00 +#define INT_SOURCE 0x04 +#define INT_MASK0x08 +#define IPGT0x0c +#define IPGR1 0x10 +#define IPGR2 0x14 +#define PACKETLEN 0x18 +#define COLLCONF0x1c +#define TX_BD_NUM 0x20 +#define CTRLMODER 0x24 +#define MIIMODER0x28 +#define MIICOMMAND 0x2c +#define MIIADDRESS 0x30 +#define MIITX_DATA 0x34 +#define MIIRX_DATA 0x38 +#define MIISTATUS 0x3c +#define MAC_ADDR0 0x40 +#define MAC_ADDR1 0x44 +#define ETH_HASH0 0x48 +#define ETH_HASH1 0x4c +#define ETH_TXCTRL 0x50 + +/* mode register */ +#define MODER_RXEN (1 0) /* receive enable */ +#define MODER_TXEN (1 1) /* transmit enable */ +#define MODER_NOPRE (1 2) /* no preamble */ +#define MODER_BRO (1 3) /* broadcast address */ +#define MODER_IAM (1 4) /* individual address mode */ +#define MODER_PRO (1 5) /* promiscuous mode */ +#define MODER_IFG (1 6) /* interframe gap for incoming frames */ +#define MODER_LOOP (1 7) /* loopback */ +#define MODER_NBO (1 8) /* no back-off */ +#define MODER_EDE (1 9) /* excess defer enable */ +#define MODER_FULLD (1 10) /* full duplex */ +#define MODER_RESET (1 11) /* FIXME: reset (undocumented) */ +#define MODER_DCRC (1 12) /* delayed CRC enable */ +#define MODER_CRC (1 13) /* CRC enable */ +#define MODER_HUGE (1 14) /* huge packets enable */ +#define MODER_PAD (1 15) /* padding enabled */ +#define MODER_RSM (1 16) /* receive small packets */ + +/* interrupt source and mask registers */ +#define INT_MASK_TXF(1 0)/* transmit frame */ +#define INT_MASK_TXE(1 1)/* transmit error */ +#define INT_MASK_RXF(1 2)/* receive frame */ +#define INT_MASK_RXE(1 3)/* receive error */ +#define INT_MASK_BUSY (1 4) +#define INT_MASK_TXC(1 5)/* transmit control frame */ +#define INT_MASK_RXC(1 6)/* receive control frame */ + +#define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE) +#define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE) + +#define INT_MASK_ALL ( \ + INT_MASK_TXF | INT_MASK_TXE | \ + INT_MASK_RXF | INT_MASK_RXE | \ + INT_MASK_TXC | INT_MASK_RXC | \ + INT_MASK_BUSY \ + ) + +/* packet length register */ +#define PACKETLEN_MIN(min) (((min) 0x) 16) +#define PACKETLEN_MAX(max) (((max) 0x) 0)
[U-Boot] [PATCH 2/5 v2] nios2: add Altera EP2C35 board
This patch supports the Altera CycloneII Nios dev board using the example FPGA design at http://nioswiki.com/Linux. Signed-off-by: Thomas Chou tho...@wytron.com.tw --- change CONFIG_SYS_HZ to 1000. MAINTAINERS |1 + MAKEALL |1 + Makefile |6 + board/altera/nios2-generic/2c35_cf.h | 757 ++ include/configs/EP2C35.h | 373 + 5 files changed, 1138 insertions(+), 0 deletions(-) create mode 100644 board/altera/nios2-generic/2c35_cf.h create mode 100644 include/configs/EP2C35.h diff --git a/MAINTAINERS b/MAINTAINERS index bb03f17..1f33146 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -850,6 +850,7 @@ Scott McNutt smcn...@psyent.com EP1C20 Nios-II EP1S10 Nios-II EP1S40 Nios-II + EP2C35 Nios-II # # MicroBlaze Systems: # diff --git a/MAKEALL b/MAKEALL index a88c31e..8ab3358 100755 --- a/MAKEALL +++ b/MAKEALL @@ -823,6 +823,7 @@ LIST_nios2=\ EP1S40 \ PCI5441 \ PK1C20 \ + EP2C35 \ # diff --git a/Makefile b/Makefile index f5b556c..a27b002 100644 --- a/Makefile +++ b/Makefile @@ -3533,6 +3533,12 @@ PK1C20_config : unconfig PCI5441_config : unconfig @$(MKCONFIG) PCI5441 nios2 nios2 pci5441 psyent +# nios2 generic boards +NIOS2_GENERIC = EP2C35 + +$(NIOS2_GENERIC:%=%_config) : unconfig + @$(MKCONFIG) $(@:_config=) nios2 nios2 nios2-generic altera + # ## Microblaze # diff --git a/board/altera/nios2-generic/2c35_cf.h b/board/altera/nios2-generic/2c35_cf.h new file mode 100644 index 000..a08b35c --- /dev/null +++ b/board/altera/nios2-generic/2c35_cf.h @@ -0,0 +1,757 @@ +#ifndef _ALTERA_2C35_CF_FPGA_H_ +#define _ALTERA_2C35_CF_FPGA_H_ + +/* + * This file was automatically generated by the swinfo2header utility. + * + * Created from SOPC Builder system 'NiosII_cycloneII_2c35_full_featured_sopc' in + * file './NiosII_cycloneII_2c35_full_featured_sopc.sopcinfo'. + */ + +/* + * This file contains macros for module 'cpu' and devices + * connected to the following masters: + * instruction_master + * tightly_coupled_instruction_master_0 + * data_master + * tightly_coupled_data_master_0 + * + * Do not include this header file and another header file created for a + * different module or master group at the same time. + * Doing so may result in duplicate macro names. + * Instead, use the system header file which has macros with unique names. + */ + +/* + * Macros for module 'cpu', class 'altera_nios2'. + * The macros have no prefix. + */ +#define CPU_IMPLEMENTATION fast +#define BIG_ENDIAN 0 +#define CPU_FREQ 8500 +#define ICACHE_LINE_SIZE 32 +#define ICACHE_LINE_SIZE_LOG2 5 +#define ICACHE_SIZE 4096 +#define DCACHE_LINE_SIZE 32 +#define DCACHE_LINE_SIZE_LOG2 5 +#define DCACHE_SIZE 2048 +#define INITDA_SUPPORTED +#define FLUSHDA_SUPPORTED +#define HAS_JMPI_INSTRUCTION +#define MMU_PRESENT +#define KERNEL_REGION_BASE 0xc000 +#define IO_REGION_BASE 0xe000 +#define KERNEL_MMU_REGION_BASE 0x8000 +#define USER_REGION_BASE 0x0 +#define PROCESS_ID_NUM_BITS 10 +#define TLB_NUM_WAYS 16 +#define TLB_NUM_WAYS_LOG2 4 +#define TLB_PTR_SZ 7 +#define TLB_NUM_ENTRIES 128 +#define FAST_TLB_MISS_EXCEPTION_ADDR 0xc800 +#define EXCEPTION_ADDR 0xc620 +#define RESET_ADDR 0xc000 +#define BREAK_ADDR 0xc2120020 +#define HAS_DEBUG_STUB +#define HAS_DEBUG_CORE 1 +#define HAS_ILLEGAL_INSTRUCTION_EXCEPTION +#define HAS_ILLEGAL_MEMORY_ACCESS_EXCEPTION +#define HAS_EXTRA_EXCEPTION_INFO +#define CPU_ID_SIZE 1 +#define CPU_ID_VALUE 0x0 +#define HARDWARE_DIVIDE_PRESENT 0 +#define HARDWARE_MULTIPLY_PRESENT 1 +#define HARDWARE_MULX_PRESENT 0 +#define INST_ADDR_WIDTH 28 +#define DATA_ADDR_WIDTH 28 +#define NUM_OF_SHADOW_REG_SETS 0 + +/* + * Macros for device 'ext_flash', class 'altera_avalon_cfi_flash' + * The macros are prefixed with 'EXT_FLASH_'. + * The prefix is the slave descriptor. + */ +#define EXT_FLASH_COMPONENT_TYPE altera_avalon_cfi_flash +#define EXT_FLASH_COMPONENT_NAME ext_flash +#define EXT_FLASH_BASE 0x0 +#define EXT_FLASH_SPAN 16777216 +#define EXT_FLASH_END 0xff +#define EXT_FLASH_SETUP_VALUE 45 +#define EXT_FLASH_WAIT_VALUE 160 +#define EXT_FLASH_HOLD_VALUE 35 +#define EXT_FLASH_TIMING_UNITS ns +#define EXT_FLASH_SIZE 16777216 +#define EXT_FLASH_MEMORY_INFO_MEM_INIT_DATA_WIDTH 8 +#define EXT_FLASH_MEMORY_INFO_HAS_BYTE_LANE 0 +#define EXT_FLASH_MEMORY_INFO_IS_FLASH 1 +#define EXT_FLASH_MEMORY_INFO_GENERATE_DAT_SYM 1 +#define
[U-Boot] [PATCH 3/5 v2] nios2: add Altera EP3C120 board
This patch supports the Altera CycloneIII Nios dev board using the example FPGA design at http://nioswiki.com/Linux. Signed-off-by: Thomas Chou tho...@wytron.com.tw --- change CONFIG_SYS_HZ to 1000. MAINTAINERS |1 + MAKEALL |1 + Makefile |2 +- board/altera/nios2-generic/default_mmu.h | 371 include/configs/EP3C120.h| 395 ++ 5 files changed, 769 insertions(+), 1 deletions(-) create mode 100644 board/altera/nios2-generic/default_mmu.h create mode 100644 include/configs/EP3C120.h diff --git a/MAINTAINERS b/MAINTAINERS index 1f33146..30ac451 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -851,6 +851,7 @@ Scott McNutt smcn...@psyent.com EP1S10 Nios-II EP1S40 Nios-II EP2C35 Nios-II + EP3C120 Nios-II # # MicroBlaze Systems: # diff --git a/MAKEALL b/MAKEALL index 8ab3358..886d608 100755 --- a/MAKEALL +++ b/MAKEALL @@ -824,6 +824,7 @@ LIST_nios2=\ PCI5441 \ PK1C20 \ EP2C35 \ + EP3C120 \ # diff --git a/Makefile b/Makefile index a27b002..5b3c589 100644 --- a/Makefile +++ b/Makefile @@ -3534,7 +3534,7 @@ PCI5441_config : unconfig @$(MKCONFIG) PCI5441 nios2 nios2 pci5441 psyent # nios2 generic boards -NIOS2_GENERIC = EP2C35 +NIOS2_GENERIC = EP2C35 EP3C120 $(NIOS2_GENERIC:%=%_config) : unconfig @$(MKCONFIG) $(@:_config=) nios2 nios2 nios2-generic altera diff --git a/board/altera/nios2-generic/default_mmu.h b/board/altera/nios2-generic/default_mmu.h new file mode 100644 index 000..dc14dc2 --- /dev/null +++ b/board/altera/nios2-generic/default_mmu.h @@ -0,0 +1,371 @@ +#ifndef _ALTERA_LINUX_CPU_H_ +#define _ALTERA_LINUX_CPU_H_ + +/* Note, this file was manually edited after generation + * since the multiple inclusion proctetion macro above collides with + * include/linux/cpu.h + */ + +/* + * This file was automatically generated by the swinfo2header utility. + * + * Created from SOPC Builder system 'nios2_linux_3c120_125mhz_sys_sopc' in + * file 'default//nios2_linux_3c120_125mhz_sys_sopc.sopcinfo'. + */ + +/* + * This file contains macros for module 'linux_cpu' and devices + * connected to the following masters: + * instruction_master + * tightly_coupled_instruction_master_0 + * data_master + * tightly_coupled_data_master_0 + * + * Do not #include this header file and another header file created for a + * different module or master group at the same time. + * Doing so may result in duplicate #defines. + * Instead, use the system header file which has #defines with unique names. + */ + +/* + * Macros for module 'linux_cpu', class 'altera_nios2'. + * The macros have no prefix. + */ +#define CPU_IMPLEMENTATION fast +#define ICACHE_LINE_SIZE 32 +#define ICACHE_LINE_SIZE_LOG2 5 +#define ICACHE_SIZE 32768 +#define DCACHE_LINE_SIZE 32 +#define DCACHE_LINE_SIZE_LOG2 5 +#define DCACHE_SIZE 32768 +#define INITDA_SUPPORTED +#define FLUSHDA_SUPPORTED +#define HAS_JMPI_INSTRUCTION +#define MMU_PRESENT +#define KERNEL_REGION_BASE 0xc000 +#define IO_REGION_BASE 0xe000 +#define KERNEL_MMU_REGION_BASE 0x8000 +#define USER_REGION_BASE 0x0 +#define PROCESS_ID_NUM_BITS 8 +#define TLB_NUM_WAYS 16 +#define TLB_PTR_SZ 7 +#define TLB_NUM_ENTRIES 128 +#define FAST_TLB_MISS_EXCEPTION_ADDR 0xc7fff400 +#define EXCEPTION_ADDR 0xd020 +#define RESET_ADDR 0xc280 +#define BREAK_ADDR 0xc7fff820 +#define HAS_DEBUG_STUB +#define HAS_DEBUG_CORE 1 +#define HAS_ILLEGAL_INSTRUCTION_EXCEPTION +#define HAS_ILLEGAL_MEMORY_ACCESS_EXCEPTION +#define HAS_EXTRA_EXCEPTION_INFO +#define CPU_ID_SIZE 1 +#define CPU_ID_VALUE 0x0 +#define HARDWARE_DIVIDE_PRESENT 1 +#define HARDWARE_MULTIPLY_PRESENT 1 +#define HARDWARE_MULX_PRESENT 0 +#define INST_ADDR_WIDTH 29 +#define DATA_ADDR_WIDTH 29 + +/* + * Macros for device 'cfi_flash_64m', class 'altera_avalon_cfi_flash' + * The macros are prefixed with 'CFI_FLASH_64M_'. + * The prefix is the slave descriptor. + */ +#define CFI_FLASH_64M_BASE 0x0 +#define CFI_FLASH_64M_SPAN 67108864u +#define CFI_FLASH_64M_SETUP_VALUE 75 +#define CFI_FLASH_64M_WAIT_VALUE 35 +#define CFI_FLASH_64M_HOLD_VALUE 1 +#define CFI_FLASH_64M_TIMING_UNITS ns +#define CFI_FLASH_64M_SIZE 67108864u + +/* + * Macros for device 'fast_tlb_miss_ram_1k', class 'altera_avalon_onchip_memory2' + * The macros are prefixed with 'FAST_TLB_MISS_RAM_1K_'. + * The prefix is the slave descriptor. + */ +#define FAST_TLB_MISS_RAM_1K_BASE 0x7fff400 +#define FAST_TLB_MISS_RAM_1K_SPAN 1024u +#define FAST_TLB_MISS_RAM_1K_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 +#define FAST_TLB_MISS_RAM_1K_INIT_CONTENTS_FILE
[U-Boot] [PATCH 4/5 v2] nios2: add Altera NEEK board
This patch supports the Altera Nios2 Embedded Evaluation Kit using the example FPGA design at http://nioswiki.com/Linux. Signed-off-by: Thomas Chou tho...@wytron.com.tw --- change CONFIG_SYS_HZ to 1000. MAINTAINERS |1 + MAKEALL |1 + Makefile |2 +- board/altera/nios2-generic/neek_ocm_spi_mmu.h | 406 + include/configs/NEEK.h| 367 ++ 5 files changed, 776 insertions(+), 1 deletions(-) create mode 100644 board/altera/nios2-generic/neek_ocm_spi_mmu.h create mode 100644 include/configs/NEEK.h diff --git a/MAINTAINERS b/MAINTAINERS index 30ac451..9c0707d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -852,6 +852,7 @@ Scott McNutt smcn...@psyent.com EP1S40 Nios-II EP2C35 Nios-II EP3C120 Nios-II + NEEKNios-II # # MicroBlaze Systems: # diff --git a/MAKEALL b/MAKEALL index 886d608..694b20e 100755 --- a/MAKEALL +++ b/MAKEALL @@ -825,6 +825,7 @@ LIST_nios2=\ PK1C20 \ EP2C35 \ EP3C120 \ + NEEK\ # diff --git a/Makefile b/Makefile index 5b3c589..ab708a0 100644 --- a/Makefile +++ b/Makefile @@ -3534,7 +3534,7 @@ PCI5441_config : unconfig @$(MKCONFIG) PCI5441 nios2 nios2 pci5441 psyent # nios2 generic boards -NIOS2_GENERIC = EP2C35 EP3C120 +NIOS2_GENERIC = EP2C35 EP3C120 NEEK $(NIOS2_GENERIC:%=%_config) : unconfig @$(MKCONFIG) $(@:_config=) nios2 nios2 nios2-generic altera diff --git a/board/altera/nios2-generic/neek_ocm_spi_mmu.h b/board/altera/nios2-generic/neek_ocm_spi_mmu.h new file mode 100644 index 000..5e62059 --- /dev/null +++ b/board/altera/nios2-generic/neek_ocm_spi_mmu.h @@ -0,0 +1,406 @@ +#ifndef _ALTERA_CPU_H_ +#define _ALTERA_CPU_H_ + +/* + * This file was automatically generated by the swinfo2header utility. + * + * Created from SOPC Builder system 'cycloneIII_embedded_evaluation_kit_standard_sopc' in + * file './cycloneIII_embedded_evaluation_kit_standard_sopc.sopcinfo'. + */ + +/* + * This file contains macros for module 'cpu' and devices + * connected to the following masters: + * instruction_master + * tightly_coupled_instruction_master_0 + * data_master + * tightly_coupled_data_master_0 + * + * Do not #include this header file and another header file created for a + * different module or master group at the same time. + * Doing so may result in duplicate #defines. + * Instead, use the system header file which has #defines with unique names. + */ + +/* + * Macros for module 'cpu', class 'altera_nios2'. + * The macros have no prefix. + */ +#define CPU_IMPLEMENTATION fast +#define CPU_FREQ 1u +#define ICACHE_LINE_SIZE 32 +#define ICACHE_LINE_SIZE_LOG2 5 +#define ICACHE_SIZE 8192 +#define DCACHE_LINE_SIZE 32 +#define DCACHE_LINE_SIZE_LOG2 5 +#define DCACHE_SIZE 4096 +#define INITDA_SUPPORTED +#define FLUSHDA_SUPPORTED +#define HAS_JMPI_INSTRUCTION +#define MMU_PRESENT +#define KERNEL_REGION_BASE 0xc000 +#define IO_REGION_BASE 0xe000 +#define KERNEL_MMU_REGION_BASE 0x8000 +#define USER_REGION_BASE 0x0 +#define PROCESS_ID_NUM_BITS 10 +#define TLB_NUM_WAYS 16 +#define TLB_NUM_WAYS_LOG2 4 +#define TLB_PTR_SZ 8 +#define TLB_NUM_ENTRIES 256 +#define FAST_TLB_MISS_EXCEPTION_ADDR 0xc900 +#define EXCEPTION_ADDR 0xc020 +#define RESET_ADDR 0xc400 +#define BREAK_ADDR 0xc620 +#define HAS_DEBUG_STUB +#define HAS_DEBUG_CORE 1 +#define HAS_ILLEGAL_INSTRUCTION_EXCEPTION +#define HAS_ILLEGAL_MEMORY_ACCESS_EXCEPTION +#define HAS_EXTRA_EXCEPTION_INFO +#define CPU_ID_SIZE 1 +#define CPU_ID_VALUE 0x0 +#define HARDWARE_DIVIDE_PRESENT 0 +#define HARDWARE_MULTIPLY_PRESENT 1 +#define HARDWARE_MULX_PRESENT 0 +#define INST_ADDR_WIDTH 28 +#define DATA_ADDR_WIDTH 28 + +/* + * Macros for device 'ddr_sdram', class 'altmemddr' + * The macros are prefixed with 'DDR_SDRAM_'. + * The prefix is the slave descriptor. + */ +#define DDR_SDRAM_COMPONENT_TYPE altmemddr +#define DDR_SDRAM_COMPONENT_NAME ddr_sdram +#define DDR_SDRAM_BASE 0x0 +#define DDR_SDRAM_SPAN 33554432 + +/* + * Macros for device 'lcd_sgdma', class 'altera_avalon_sgdma' + * The macros are prefixed with 'LCD_SGDMA_'. + * The prefix is the slave descriptor. + */ +#define LCD_SGDMA_COMPONENT_TYPE altera_avalon_sgdma +#define LCD_SGDMA_COMPONENT_NAME lcd_sgdma +#define LCD_SGDMA_BASE 0x200 +#define LCD_SGDMA_SPAN 1024u +#define LCD_SGDMA_IRQ 5 +#define LCD_SGDMA_READ_BLOCK_DATA_WIDTH 64 +#define LCD_SGDMA_WRITE_BLOCK_DATA_WIDTH 64 +#define LCD_SGDMA_STREAM_DATA_WIDTH 64 +#define LCD_SGDMA_ADDRESS_WIDTH 32 +#define LCD_SGDMA_HAS_READ_BLOCK 1 +#define LCD_SGDMA_HAS_WRITE_BLOCK 0
Re: [U-Boot] [PATCH v2] net: add opencore 10/100 ethernet mac driver
Hi Scott, On Tue, Mar 30, 2010 at 8:07 PM, Scott McNutt smcn...@psyent.com wrote: Hi Wolfgang, Do we have a network drivers custodian? ... or should I just handle this patch through the nios repository? I'm guessing that this will only be used with nios2 in the near term. I'm not sure if any Microblaze (Xilinx) folks have worked with this -- perhaps Michal can comment? This is my jurisdiction. I just haven't found time yet to properly review the submission. Hopefully over the next couple of days. regards, Ben ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] nios2: Set CONFIG_SYS_HZ to 1000 all nios2 boards.
Hi Thomas, Thomas Chou wrote: On 03/31/2010 10:09 AM, Scott McNutt wrote: So it might be cleaner to let user define the HZ as the actual tick rate and increase the tick count by one in the tmr_isr. This was discussed/debated thoroughly over the past year: CONFIG_SYS_HZ at 1000 is mandatory. -timestamp += CONFIG_SYS_NIOS_TMRMS; +timestamp++; This means that each interrupt is exactly 1 msec. That's not what was intended and not what was implemented Forcing the interrupt period to 1 msec is an unnecessary constraint. If you want the isr to increment the timestamp by 1, then set CONFIG_SYS_NIOS_TMRMS to 1 ... and set your timer accordingly. I tried to follow your patch nios2: Set CONFIG_SYS_HZ to 1000 all nios2 boards. But got cfi flash buffer write timeout on EP2C35 board. If I set TMRMS to 1, it works with HZ at 100, 1000 and 2000. The patch should not affect your EP2C35 board configuration since it hasn't been added yet. So I'm not sure I understand the scenario you are describing. If your TMRMS is set to 1 and your TMRCNT is set to match, then you should be ticking at 1000 Hz. And if CONFIG_SYS_HZ is set to 1000, we should achieve oneness with u-boot ;-) In any case, for the benefit of the nios2 folks who might be following this thread: CONFIG_SYS_TMRMS -- this is the _actual_ period (in msec) of the timer interrupt that is added to the timestamp on every interrupt. It's what board developers choose based on their requirements. It's intended to be cpu clock and timer configuration agnostic. CONFIG_SYS_NIOS_TMRCNT -- this is what (optionally) gets loaded into the timer period registers. If the default configuration of the timer matches TMRMS, then there's no need to define this value. However, if for some reason you want to slow down the interrupt frequency, you can do so by defining an appropriate value. How to calculate these values is up to the board developer. For the Altera EP1xxx boards, we start with a desired period of 10 ms, so TMRMS is set to 10. Then TMRCNT is calculated based on the system clock frequency. And none of the above has anything to do with CONFIG_SYS_HZ ... which for the most part is just a synonym for the value 1000. If you set CONFIG_SYS_HZ to anything less than 1000 you end up with a timeout of zero in cfi_flash ... at least until we rebase to the mothership to get the latest cfi patches ... at which point it should be 1. A timeout of zero is probably not what we want. ;-) In any case, I'll try to fire up my 2C35 board and have a look. Best Regards, --Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Loading and Running u-boot from context RAM
Hello, I am working on PPC440 based customized board having 4MB context ram. what are all changes need to perform to skip relocation of u-boot in DDR and relocated it to context ram and run from the same location. ~Ronny The INTERNET now has a personality. YOURS! See your Yahoo! Homepage. http://in.yahoo.com/___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] 85xx: Added various P1012/P1013/P1021/P1022 defines
There are various locations that we have chip specific info:
* Makefile for which ddr code to build
* Added P1012/P1013/P1021/P1022 to cpu_type_list and SVR list
* Added number of LAWs for P1012/P1013/P1021/P1022
* Set CONFIG_MAX_CPUS to 2 for P1021/P1022
* PCI port config
Signed-off-by: Haiying Wang haiying.w...@freescale.com
Signed-off-by: Srikanth Srinivasan srikanth.sriniva...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
cpu/mpc85xx/Makefile|4
cpu/mpc8xxx/cpu.c |8
cpu/mpc8xxx/pci_cfg.c | 28 ++--
drivers/misc/fsl_law.c |2 ++
include/asm-ppc/config.h|1 +
include/asm-ppc/processor.h |8
6 files changed, 49 insertions(+), 2 deletions(-)
diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile
index 56de7eb..f064fee 100644
--- a/cpu/mpc85xx/Makefile
+++ b/cpu/mpc85xx/Makefile
@@ -50,7 +50,11 @@ COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
COBJS-$(CONFIG_MPC8569)+= ddr-gen3.o
COBJS-$(CONFIG_P1011) += ddr-gen3.o
+COBJS-$(CONFIG_P1012) += ddr-gen3.o
+COBJS-$(CONFIG_P1013) += ddr-gen3.o
COBJS-$(CONFIG_P1020) += ddr-gen3.o
+COBJS-$(CONFIG_P1021) += ddr-gen3.o
+COBJS-$(CONFIG_P1022) += ddr-gen3.o
COBJS-$(CONFIG_P2010) += ddr-gen3.o
COBJS-$(CONFIG_P2020) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o
diff --git a/cpu/mpc8xxx/cpu.c b/cpu/mpc8xxx/cpu.c
index d191263..e8c1bf8 100644
--- a/cpu/mpc8xxx/cpu.c
+++ b/cpu/mpc8xxx/cpu.c
@@ -66,8 +66,16 @@ struct cpu_type cpu_type_list [] = {
CPU_TYPE_ENTRY(8572, 8572_E, 2),
CPU_TYPE_ENTRY(P1011, P1011, 1),
CPU_TYPE_ENTRY(P1011, P1011_E, 1),
+ CPU_TYPE_ENTRY(P1012, P1012, 1),
+ CPU_TYPE_ENTRY(P1012, P1012_E, 1),
+ CPU_TYPE_ENTRY(P1013, P1013, 1),
+ CPU_TYPE_ENTRY(P1013, P1013_E, 1),
CPU_TYPE_ENTRY(P1020, P1020, 2),
CPU_TYPE_ENTRY(P1020, P1020_E, 2),
+ CPU_TYPE_ENTRY(P1021, P1021, 2),
+ CPU_TYPE_ENTRY(P1021, P1021_E, 2),
+ CPU_TYPE_ENTRY(P1022, P1022, 2),
+ CPU_TYPE_ENTRY(P1022, P1022_E, 2),
CPU_TYPE_ENTRY(P2010, P2010, 1),
CPU_TYPE_ENTRY(P2010, P2010_E, 1),
CPU_TYPE_ENTRY(P2020, P2020, 2),
diff --git a/cpu/mpc8xxx/pci_cfg.c b/cpu/mpc8xxx/pci_cfg.c
index d53781b..67bb562 100644
--- a/cpu/mpc8xxx/pci_cfg.c
+++ b/cpu/mpc8xxx/pci_cfg.c
@@ -25,7 +25,7 @@
#include pci.h
struct pci_info {
- u16 cfg;
+ u32 cfg;
};
/* The cfg field is a bit mask in which each bit represents the value of
@@ -153,7 +153,8 @@ static struct pci_info pci_config_info[] =
(1 7) | (1 0xe) | (1 0xf),
},
};
-#elif defined(CONFIG_P1011) || defined(CONFIG_P1020)
+#elif defined(CONFIG_P1011) || defined(CONFIG_P1020) \
+ defined(CONFIG_P1012) || defined(CONFIG_P1021)
static struct pci_info pci_config_info[] =
{
[LAW_TRGT_IF_PCIE_1] = {
@@ -163,6 +164,29 @@ static struct pci_info pci_config_info[] =
.cfg = (1 0xe),
},
};
+#elif defined(CONFIG_P1013) || defined(CONFIG_P1022)
+static struct pci_info pci_config_info[] =
+{
+ [LAW_TRGT_IF_PCIE_1] = {
+ .cfg = (1 6) | (1 7) | (1 9) | (1 0xa) |
+(1 0xb) | (1 0xd) | (1 0xe) |
+(1 0xf) | (1 0x15) | (1 0x16) |
+(1 0x17) | (1 0x18) | (1 0x19) |
+(1 0x1a) | (1 0x1b) | (1 0x1c) |
+(1 0x1d) | (1 0x1e) | (1 0x1f),
+ },
+ [LAW_TRGT_IF_PCIE_2] = {
+ .cfg = (1 0) | (1 1) | (1 6) | (1 7) |
+(1 9) | (1 0xa) | (1 0xb) | (1 0xd) |
+(1 0x15) | (1 0x16) | (1 0x17) |
+(1 0x18) | (1 0x1c),
+ },
+ [LAW_TRGT_IF_PCIE_3] = {
+ .cfg = (1 6) | (1 7) | (1 9) | (1 0xd) |
+(1 0x15) | (1 0x16) | (1 0x17) | (1 0x18) |
+(1 0x19) | (1 0x1a) | (1 0x1b),
+ },
+};
#elif defined(CONFIG_P2010) || defined(CONFIG_P2020)
static struct pci_info pci_config_info[] =
{
diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c
index 287e555..7b33bb7 100644
--- a/drivers/misc/fsl_law.c
+++ b/drivers/misc/fsl_law.c
@@ -39,6 +39,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define FSL_HW_NUM_LAWS 10
#elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572) || \
defined(CONFIG_P1011) || defined(CONFIG_P1020) || \
+ defined(CONFIG_P1012) || defined(CONFIG_P1021) || \
+ defined(CONFIG_P1013) || defined(CONFIG_P1022) || \
defined(CONFIG_P2010) || defined(CONFIG_P2020)
#define FSL_HW_NUM_LAWS 12
#elif defined(CONFIG_PPC_P4080)
diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h
index 0d78aa4..ac0f809 100644
--- a/include/asm-ppc/config.h
+++ b/include/asm-ppc/config.h
@@ -41,6 +41,7 @@
#endif
#if
Re: [U-Boot] [PATCH 1/2 v2] net, fec_mxc: only setup the device enetaddr with eeprom value, if ethaddr is not setup
Hello Ben,
Ben Warren wrote:
Wolfgang,
On 3/30/2010 1:34 PM, Wolfgang Denk wrote:
Dear Heiko Schocher,
In message4bb238e9.7060...@denx.de you wrote:
if ethaddr is not setup in the environment, fill the device
enetaddr with the contents of the eeprom, and only
the device enetaddr, not the mac address registers!
Tested on the magnesium board.
Signed-off-by: Heiko Schocherh...@denx.de
---
- changes since v1 posted here:
http://lists.denx.de/pipermail/u-boot/2010-March/069192.html
- splitted in two patches as Wolfgang suggested
Thanks. Note that it would also have been an excellent idea to put
the responsible custodian on Cc:
drivers/net/fec_mxc.c |9 +
1 files changed, 5 insertions(+), 4 deletions(-)
Applied, thanks.
Ben, this is (as far as I see it) an undisputed bug fix, so I'm
pulling this patch (and only this one from this series of 4)
directly. Hope this is ok with you.
Hold on a second. This patch is wrong. As Mike has pointed out, the
Now I got lost ... I think the critical part of my patch v1 is splitted
out to 2/2 v2 ... or?
net library already gets the MAC address from the environment. The
correct flow is:
1. Read from hardware in initialize() function
Ah, Ok, so that is the right way? If so, then I should remove
+ if (!eth_getenv_enetaddr(ethaddr, ethaddr)) {
from my patch, and then it should be OK, right?
Actual fec_mxc.c driver is *not* correct, because if in eeprom
is a correct mac, it *always* programms this in the mac address
registers from the chip!
This is not OK, and must be fixed!
2. Read from environment in net/eth.c after initialize()
3. Give priority to the value in the environment if a conflict
4. Program hardware in the device's init() function.
If somebody wants to subvert the 'design philosophy', the right way is
to call eth_dev-init() in board code.
Maybe this list should go in a doc?
bye
Heiko
--
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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Re: [U-Boot] net, fec_mxc: init mac address before using network commands
On Tuesday 30 March 2010 01:38:33 Heiko Schocher wrote: initialize mac address with the value from ethaddr, before doing some network commands. This is not in line with u-boot design principle not to initalize not used devices, and maybe should go away, if there is a solution for passing the mac address to arm linux kernels. NACK like i already said -- net drivers should only ever be reading eth_driver-enetaddr. they should never touch the environment as the common net code takes care of this. i would instead fix the fec_probe() to stop writing ethaddr since it already writes to eth_driver-enetaddr. -mike signature.asc Description: This is a digitally signed message part. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] net, kirkwood_egiga: init mac address before using network commands
On Tuesday 30 March 2010 01:38:39 Heiko Schocher wrote:
diff --git a/drivers/net/kirkwood_egiga.c b/drivers/net/kirkwood_egiga.c
index 2ad7fea..e8b3777 100644
--- a/drivers/net/kirkwood_egiga.c
+++ b/drivers/net/kirkwood_egiga.c
@@ -678,7 +678,7 @@ int kirkwood_egiga_initialize(bd_t * bis)
return -1;
}
- while (!eth_getenv_enetaddr(s, dev-enetaddr)) {
+ if (!eth_getenv_enetaddr(s, dev-enetaddr)) {
this too is broken (not just your change, but also the existing code). please
instead fix it to follow the documented MAC handling. the initialize function
should seed dev-enetaddr with the eeprom value only while the init function
should take care of programming dev-enetaddr into the hardware's MAC
registers.
-mike
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Re: [U-Boot] net, kirkwood_egiga: init mac address before using network commands
On Tue, 30 Mar 2010 07:38:39 +0200 Heiko Schocher h...@denx.de wrote: initialize mac address with the value from ethaddr, before doing some network commands. This is not in line with u-boot design principle not to initalize not used devices, and maybe should go away, if there is a solution for passing the mac address to arm linux kernels. I also tried this change half a year ago, but it got NACK:ed. The discussion is here if you are interested: http://www.mail-archive.com/u-boot@lists.denx.de/msg16994.html // Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] net, fec_mxc: init mac address before using network commands
Dear Heiko Schocher,
In message 4bb18e59.5000...@denx.de you wrote:
initialize mac address with the value from ethaddr, before
doing some network commands. This is not in line with u-boot
design principle not to initalize not used devices, and
maybe should go away, if there is a solution for passing
the mac address to arm linux kernels.
Tested on the magnesium board.
Note 1: I would have expected that this commit is marked as a
follow-up to your earlier posting from Wed, 24 Mar 2010,
titled [PATCH] net, fec_mxc: use mac address stored in env
before looking in eeprom
(http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/76173)
Unfortunately your new posting contains no indication of a
previous patch (i. e. there is no v2 or similar in the
Subject, nor is there a description of the changes against the
previous version below the --- line. In addition, the
Subject has been changed which makes it even more difficult
to match this to the older posting.
Note 2: I think this description is actually incomplete. You are
mixing two independent modifications here.
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 5af9cdb..9029490 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -749,11 +749,18 @@ static int fec_probe(bd_t *bd)
eth_register(edev);
- if (fec_get_hwaddr(edev, ethaddr) == 0) {
- printf(got MAC address from EEPROM: %pM\n, ethaddr);
- memcpy(edev-enetaddr, ethaddr, 6);
- fec_set_hwaddr(edev);
+ if (!eth_getenv_enetaddr(ethaddr, ethaddr)) {
+ /* ethaddr is not set in the environment */
+ if (fec_get_hwaddr(edev, ethaddr) == 0) {
+ printf(got MAC address from EEPROM: %pM\n, ethaddr);
+ eth_setenv_enetaddr(ethaddr, ethaddr);
+ } else {
+ printf (no MAC found\n);
+ return -1;
+ }
This part of the commit is the previously dicussed bug fix: without
this change, the board would, under certain conditions, ignore the
ethaddr setting stored in the environment. This is a clear bug fix
and as such should get added to the current code. As far as I can
tell, this part does not violate any design rules.
}
+ memcpy(edev-enetaddr, ethaddr, 6);
+ fec_set_hwaddr(edev);
This is a completely different issue. Here you add new code to change
the system behaviour in a way that indeed violates the design rules.
Please split this patch into two separate commits. The first part is
obviously a fix. I will ACK it and even pull it in the upcoming
release (assuming you are fast enough).
I dislike the second part, but I will not actively block it either.
Let's see what others (especially Ben) say about it.
Best regards,
Wolfgang Denk
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Re: [U-Boot] net, kirkwood_egiga: init mac address before using network commands
Hello Heiko, initialize mac address with the value from ethaddr, before doing some network commands. This is not in line with u-boot design principle not to initalize not used devices, and maybe should go away, if there is a solution for passing the mac address to arm linux kernels. Tested on the suen3 board. Signed-off-by: Heiko Schocher h...@denx.de Acked-by: Detlev Zundel d...@denx.de My question about why doing this can negatively effect U-Boot still stands. I also actively request the U-Boot community to give feedback here - after all, this _is_ a community project and fixing real problems is one of the main tasks of a bootloader. Cheers Detlev -- Wenn ein Kopf und ein Buch zusammenstossen und es klingt hohl; ist denn das allemal im Buche? - Lichtenberg -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: d...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] net, fec_mxc: init mac address before using network commands
Hello Heiko, initialize mac address with the value from ethaddr, before doing some network commands. This is not in line with u-boot design principle not to initalize not used devices, and maybe should go away, if there is a solution for passing the mac address to arm linux kernels. Tested on the magnesium board. Signed-off-by: Heiko Schocher h...@denx.de Acked-by: Detlev Zundel d...@denx.de Cheers Detlev -- I think that level of generalization is too abstract for useful thinking. -- Richard Stallman in e19n344-0006q9...@fencepost.gnu.org -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: d...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] net, kirkwood_egiga: init mac address before using network commands
On Tue, 30 Mar 2010 09:52:29 +0200 Detlev Zundel d...@denx.de wrote: I also actively request the U-Boot community to give feedback here - after all, this _is_ a community project and fixing real problems is one of the main tasks of a bootloader. Personally, I'd prefer using Heikos approach until Arm Linux has moved to device trees. I know it's a deviation from how it's supposed to work, but it also solves a real problem without introducing kludges elsewhere. I think most people (myself included) would just solve the problem by carrying a private patch to setup the MAC address in U-boot anyway. // Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] net, kirkwood_egiga: init mac address before using network commands
Dear Heiko Schocher,
In message 4bb18e5f.6060...@denx.de you wrote:
initialize mac address with the value from ethaddr, before
doing some network commands. This is not in line with u-boot
design principle not to initalize not used devices, and
maybe should go away, if there is a solution for passing
the mac address to arm linux kernels.
Tested on the suen3 board.
Signed-off-by: Heiko Schocher h...@denx.de
---
posting this patch as a result of this discussion:
http://lists.denx.de/pipermail/u-boot/2010-March/069025.html
Hm... it seems I misunderstood you there :-(
You wrote (here:
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/76173/focus=76338):
| know about these, of course). So if kirkwood_egiga is clean (in this
| respect), there is no need to change it.
|
| It ends in the same problem, as the fec_mxc.c driver has ...
At this point I thought that you were referring to the problem that
the fec_mxc.c would under certain conditions ignore the ethaddr
environment setting.
}
- while (!eth_getenv_enetaddr(s, dev-enetaddr)) {
+ if (!eth_getenv_enetaddr(s, dev-enetaddr)) {
I think this change is actually not related to the other modifi-
cations in this patch. Axctually, it is not even needed. OK, you can
call it paranoid and a waste of time to re-check the setting of the
environment variable after running setenv(), but then it's not a real
bug either. In any case it is unrelated and should not be mixed into
this commit.
dev-enetaddr[0] = 0x02;
dev-enetaddr[1] = 0x50;
@@ -688,6 +688,7 @@ int kirkwood_egiga_initialize(bd_t * bis)
dev-enetaddr[5] = get_random_hex();
eth_setenv_enetaddr(s, dev-enetaddr);
}
+ port_uc_addr_set(dkwgbe-regs, dev-enetaddr);
This is another issue - this is not a bug fix.
I will leave it up to others (especially Ben) to comment on this part.
Best regards,
Wolfgang Denk
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Re: [U-Boot] net, kirkwood_egiga: init mac address before using network commands
Dear Simon Kagstrom, In message 20100330100127.5f364...@marrow.netinsight.se you wrote: I also actively request the U-Boot community to give feedback here - after all, this _is_ a community project and fixing real problems is one of the main tasks of a bootloader. Personally, I'd prefer using Heikos approach until Arm Linux has moved to device trees. I know it's a deviation from how it's supposed to work, but it also solves a real problem without introducing kludges elsewhere. If we do not even raise issues with the current Linux code with the Linux developers they will not even be aware that there are problems. In the end, things will never change. It is always wrong to not even try to fix the root cause of problems. I think most people (myself included) would just solve the problem by carrying a private patch to setup the MAC address in U-boot anyway. Interesting. Why would you do this? Why would you not rather fix the Linux driver instead? [This is what I would do.] Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de You can have my Unix system when you pry it from my cold, dead fingers.- Cal Keegan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] net, kirkwood_egiga: init mac address before using network commands
On Tue, 30 Mar 2010 10:26:59 +0200 Wolfgang Denk w...@denx.de wrote: Personally, I'd prefer using Heikos approach until Arm Linux has moved to device trees. I know it's a deviation from how it's supposed to work, but it also solves a real problem without introducing kludges elsewhere. If we do not even raise issues with the current Linux code with the Linux developers they will not even be aware that there are problems. In the end, things will never change. I believe they are aware of this especially since many developers work on both projects anyway. If I remember the discussion on ARM device trees a year ago or so correct, this was one of the issues brought up in support of the device trees (or it should have, anyway). I think most people (myself included) would just solve the problem by carrying a private patch to setup the MAC address in U-boot anyway. Interesting. Why would you do this? Why would you not rather fix the Linux driver instead? [This is what I would do.] Basically two reasons: First, it's a simpler fix in U-boot (a oneliner for Kirkwood), and secondly because (as far as I understand, correct me if I'm wrong), it lacks any well-defined protocol to transfer this knowledge to the kernel driver. I know mostly how it looks on the OpenRD board, where the MAC address is stored in the U-boot environment. Easy to access in U-boot, but a lot trickier from Linux. Sure, you could transfer it via a command-line parameter or something, but personally I think this is uglier than setting it up in U-boot anyway. // Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] net, kirkwood_egiga: init mac address before using network commands
Hi Simon, Interesting. Why would you do this? Why would you not rather fix the Linux driver instead? [This is what I would do.] Basically two reasons: First, it's a simpler fix in U-boot (a oneliner for Kirkwood), and secondly because (as far as I understand, correct me if I'm wrong), it lacks any well-defined protocol to transfer this knowledge to the kernel driver. Yes, this is one reason, which will be fixed once the device tree is available (for the boards using it, device tree on ARM in the foreseeable future will only be optional, not mandatory). But this is not the only reason for me personally. I know mostly how it looks on the OpenRD board, where the MAC address is stored in the U-boot environment. Easy to access in U-boot, but a lot trickier from Linux. Sure, you could transfer it via a command-line parameter or something, but personally I think this is uglier than setting it up in U-boot anyway. This is the other reason for me indeed. For the current problem at hand, we would need to extend the protocol, the protocol handlers and the linux drivers in order to pass 6 bytes into Linux which then get simply programmed into registers. Why not regard the MAC registers as the protocol to pass this information to the linux driver? This already exists and needs no further change whatsoever. Moreover, linux drivers do not initialize _everything_ for the devices they use, not even in PowerPC world. Take for example the GPIOs on a 5200 board. They are configured by this (admittedly inelegant) central portconfig register. The linux drivers accessing pins (which can be either gpios or function pins) do not touch this portconfig but rely on its correct setting in U-Boot. So for the 5200 boards in U-Boot, we set this portconfig in U-Boot even though we may never touch any of the devices this configuration touches. This is just one example I'm personally aware of, I'm sure one can find many more like this. Of course we can surely extend the device tree with yet more information, but in my personal view it is also perfectly fine to delegate some taks to the firmware. We only have to be clear about what tasks are to be done by firmware and what the operating system will do by itself. In the long run I think that if we extend all linux drivers to be capable to initialize everything about their context, we have an unmaintainable mess in the linux drivers. I'd rather like to see linux drivers implement the shared functionality and firmware to setup a context of bare usability. So the cut between what firmware can and/or should initialize is not always as black and white for me personally but still an important question to discuss. Cheers Detlev -- Music scenes ain't real life / They won't get rid of the bomb Won't eliminate rape / Or bring down the banks / any kind of change Takes more time and work / than changing channels on a TV set -- Jello Biafra -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: d...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/4] s5p6442: Add support SMDK6442 board
2010/3/29 Minkyu Kang proms...@gmail.com:
Dear Joonyoung Shim,
On 29 March 2010 11:56, Joonyoung Shim jy0922.s...@samsung.com wrote:
This patch adds the new board SMDK6442 that uses s5p6442 SoC.
Cc: Minkyu Kang mk7.k...@samsung.com
Cc: Kyungmin Park kyungmin.p...@samsung.com
Signed-off-by: Joonyoung Shim jy0922.s...@samsung.com
---
MAKEALL | 1 +
Makefile | 3 +
board/samsung/smdk6442/Makefile | 55 +++
board/samsung/smdk6442/config.mk | 6 +
board/samsung/smdk6442/lowlevel_init.S | 202 ++
board/samsung/smdk6442/mem_setup.S | 175 +++
board/samsung/smdk6442/onenand.c | 41 ++
board/samsung/smdk6442/smdk6442.c | 54 +++
include/configs/smdk6442.h | 242
9 files changed, 779 insertions(+), 0 deletions(-)
create mode 100644 board/samsung/smdk6442/Makefile
create mode 100644 board/samsung/smdk6442/config.mk
create mode 100644 board/samsung/smdk6442/lowlevel_init.S
create mode 100644 board/samsung/smdk6442/mem_setup.S
create mode 100644 board/samsung/smdk6442/onenand.c
create mode 100644 board/samsung/smdk6442/smdk6442.c
create mode 100644 include/configs/smdk6442.h
Please add smdk6442 at MAINTAINERS entry.
OK.
diff --git a/board/samsung/smdk6442/config.mk
b/board/samsung/smdk6442/config.mk
new file mode 100644
index 000..9c39c8a
--- /dev/null
+++ b/board/samsung/smdk6442/config.mk
@@ -0,0 +1,6 @@
+#
+# Copyright (C) 2010 Samsung Elecgtronics
Is Elecgtronics typo?
Elecgtronics - Electronics
+# Minkyu Kang mk7.k...@samsung.com
+#
+
+TEXT_BASE = 0x3480
diff --git a/board/samsung/smdk6442/smdk6442.c
b/board/samsung/smdk6442/smdk6442.c
new file mode 100644
index 000..bb8d469
--- /dev/null
+++ b/board/samsung/smdk6442/smdk6442.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Minkyu Kang mk7.k...@samsung.com
+ * Joonyoung Shim jy0922.s...@samsung.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ gd-bd-bi_arch_number = MACH_TYPE_SMDK6442;
+ gd-bd-bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd-bd-bi_dram[0].start = PHYS_SDRAM_1;
+ gd-bd-bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ gd-bd-bi_dram[1].start = PHYS_SDRAM_2;
+ gd-bd-bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+ return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ printf(Board:\t6442\n);
Please fix it to SMDK6442.
OK.
+ return 0;
+}
+#endif
Thanks
Minkyu Kang
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Re: [U-Boot] [PATCH 3/4] s5p6442: Support serial driver
2010/3/29 Minkyu Kang proms...@gmail.com:
Dear Joonyoung Shim,
On 29 March 2010 11:56, Joonyoung Shim jy0922.s...@samsung.com wrote:
This patch is for serial support of s5p6442 SoC.
Cc: Minkyu Kang mk7.k...@samsung.com
Cc: Kyungmin Park kyungmin.p...@samsung.com
Signed-off-by: Joonyoung Shim jy0922.s...@samsung.com
---
common/serial.c | 2 +-
drivers/serial/Makefile | 1 +
drivers/serial/serial_s5p.c | 5 +
include/serial.h | 2 +-
4 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/common/serial.c b/common/serial.c
index 94e1921..385c42b 100644
--- a/common/serial.c
+++ b/common/serial.c
@@ -69,7 +69,7 @@ struct serial_device *__default_serial_console (void)
#else
#error CONFIG_SERIAL? missing.
#endif
-#elif defined(CONFIG_S5PC1XX)
+#elif defined(CONFIG_S5PC1XX) || defined(CONFIG_S5P64XX)
#if defined(CONFIG_SERIAL0)
return s5p_serial0_device;
#elif defined(CONFIG_SERIAL1)
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 71392e6..110b7e1 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -34,6 +34,7 @@ COBJS-$(CONFIG_SYS_NS16550) += ns16550.o
COBJS-$(CONFIG_DRIVER_S3C4510_UART) += s3c4510b_uart.o
COBJS-$(CONFIG_S3C64XX) += s3c64xx.o
COBJS-$(CONFIG_S5PC1XX) += serial_s5p.o
+COBJS-$(CONFIG_S5P64XX) += serial_s5p.o
COBJS-$(CONFIG_SYS_NS16550_SERIAL) += serial.o
COBJS-$(CONFIG_CLPS7111_SERIAL) += serial_clps7111.o
COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index 68b8d01..1e7426d 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -31,10 +31,15 @@ static inline struct s5p_uart *s5p_get_base_uart(int
dev_index)
{
u32 offset = dev_index * sizeof(struct s5p_uart);
+#ifdef CONFIG_S5PC1XX
if (cpu_is_s5pc100())
return (struct s5p_uart *)(S5PC100_UART_BASE + offset);
else
return (struct s5p_uart *)(S5PC110_UART_BASE + offset);
+#elif CONFIG_S5P64XX
+ if (cpu_is_s5p6442())
+ return (struct s5p_uart *)(S5P6442_UART_BASE + offset);
need else or return.
Right. I will add return NULL.
Thanks.
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Re: [U-Boot] mpc8548cds can't support uhci usb
Hi 万时光, you should not send any mails to u-boot-ow...@lists.denx.de, but rather to u-b...@lists.denx.de. hello everyone,I want to make the u-boot support the uhci usb on the board MPC8548CDS,I has used the driver of amigaoneg3se,but ,I get the error: COMMAND phase dir 1 lun 0 cmdlen 12 cmd 3ffbdf88 datalen 18 pdata 3ffbdf98 cmd[0] 0x3 cmd[1] 0x0 cmd[2] 0x0 cmd[3] 0x0 cmd[4] 0x12 cmd[5] 0x0 cmd[6] 0x0 cmd[7] 0x0 cmd[8] 0x0 cmd[9] 0x0 cmd[10] 0x0 cmd[11] 0x0 usb_stor_BBB_comdat:usb_bulk_msg error failed to send CBW status 2147483648 BBB_reset uhci_submit_control start len 0, maxsize 80 uhci_submit_control end (1 tmp_tds used) BBB_reset result 0: status 8000 reset uhci_submit_control start len 0, maxsize 80 uhci_submit_control end (1 tmp_tds used) BBB_reset result 0: status 8000 clearing IN endpoint uhci_submit_control start len 0, maxsize 80 uhci_submit_control end (1 tmp_tds used) BBB_reset result 0: status 8000 clearing OUT endpoint BBB_reset done Request Sense returned 00 00 00 Device NOT ready Request Sense returned 00 00 00 i=2 0 Storage Device(s) found thank for your any help! Maybe someone from the mailing list knows more. Cheers Detlev -- Zivilisation ist der Zaubertrick, der uns unsere wahre Natur verbirgt. -- Salman Rushdie -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: d...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ppc4xx: Fix problem with I2C bus = 1 initialization
On Monday 29 March 2010 15:35:43 Stefan Roese wrote: This patch fixes a problem introduced with patch eb5eb2b0 [ppc4xx: Cleanup PPC4xx I2C infrastructure]. We need to assign the I2C base address to the i2c pointer inside of the controller loop. Otherwise controller 0 is initialized multiple times instead of initializing each I2C controller sequentially. Tested on Katmai. Applied to u-boot-ppc4xx/master. Thanks. Cheers, Stefan -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: off...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Please pull u-boot-ppc4xx/master
Hi Wolfgang, please pull this last minute fix into master. Thanks. The following changes since commit 060f28532b09dd3d2c78423bdd809ac768a27629: Wolfgang Denk (1): cmd_usb.c: print debug messages only when DEBUG is defined are available in the git repository at: git://www.denx.de/git/u-boot-ppc4xx.git master Stefan Roese (1): ppc4xx: Fix problem with I2C bus = 1 initialization cpu/ppc4xx/i2c.c |5 - 1 files changed, 4 insertions(+), 1 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/1] at91sam9x: driver to use the internal RTT as RTC
Based on the linux driver. Signed-off-by: Alexander Holler hol...@ahsoftware.de --- README |1 + drivers/rtc/Makefile |1 + drivers/rtc/at91sam9-rtc.c | 162 3 files changed, 164 insertions(+), 0 deletions(-) create mode 100644 drivers/rtc/at91sam9-rtc.c diff --git a/README b/README index 940b507..afe2aa6 100644 --- a/README +++ b/README @@ -733,6 +733,7 @@ The following options need to be configured: CONFIG_RTC_ISL1208 - use Intersil ISL1208 RTC CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC CONFIG_SYS_RTC_DS1337_NOOSC - Turn off the OSC output for DS1337 + CONFIG_RTC_AT91SAM9 - use internal RTT of AT91SAM9x Note that if the RTC uses I2C, then the I2C interface must also be configured. See I2C Support, below. diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 772a49a..4a48231 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -62,6 +62,7 @@ COBJS-$(CONFIG_RTC_RX8025) += rx8025.o COBJS-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o COBJS-$(CONFIG_RTC_S3C44B0) += s3c44b0_rtc.o COBJS-$(CONFIG_RTC_X1205) += x1205.o +COBJS-$(CONFIG_RTC_AT91SAM9) += at91sam9-rtc.o COBJS := $(sort $(COBJS-y)) SRCS := $(COBJS:.o=.c) diff --git a/drivers/rtc/at91sam9-rtc.c b/drivers/rtc/at91sam9-rtc.c new file mode 100644 index 000..d0a263a --- /dev/null +++ b/drivers/rtc/at91sam9-rtc.c @@ -0,0 +1,162 @@ +/* + * RTT as Real Time Clock driver for AT91SAM9 SoC family + * + * (C) Copyright 2010 + * Alexander Holler hol...@ahsoftware.de + * + * Based on rtc-at91sam9.c from Michel Benoit + * Based on rtc-at91rm9200.c by Rick Bronson + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This driver uses two configurable hardware resources that live in the + * AT91SAM9 backup power domain (intended to be powered at all times) + * to implement the Real Time Clock interfaces + * + * - A Real-time Timer (RTT) counts up in seconds from a base time. + *We can't assign the counter value (CRTV) ... but we can reset it. + * + * - One of the General Purpose Backup Registers (GPBRs) holds the + *base time, normally an offset from the beginning of the POSIX + *epoch (1970-Jan-1 00:00:00 UTC). Some systems also include the + *local timezone's offset. + * + * The RTC's value is the RTT counter plus that offset. The RTC's alarm + * is likewise a base (ALMV) plus that offset. + * + * Not all RTTs will be used as RTCs; some systems have multiple RTTs to + * choose from, or a real RTC module. All systems have multiple GPBR + * registers available, likewise usable for more than RTC support. + * + * In addition to CONFIG_CMD_DATE these additional defines must be set: + * + * #define CONFIG_RTC_AT91SAM9 + * #define CONFIG_RTC_AT91SAM9_RTT AT91_RTT0_BASE + * #define CONFIG_RTC_AT91SAM9_GPBR 0 + * + */ +#include common.h +#include command.h +#include asm/arch/io.h +#include asm/arch/hardware.h +#include rtc.h + +#if defined(CONFIG_CMD_DATE) + +#undef RTC_DEBUG + +#ifdef RTC_DEBUG +# define DPRINTF(x,args...) printf(at91sam9-rtc: x , ##args) +#else +# define DPRINTF(x,args...) +#endif + +/* Defines copied from linux/arch/arm/mach-at91/include/mach/at91_rtt.h */ +#define AT91_RTT_MR0x00/* Real-time Mode Register */ +#define AT91_RTT_AR0x04/* Real-time Alarm Register */ +#define AT91_RTT_VR0x08/* Real-time Value Register */ +#define AT91_RTT_RTPRES(0x 0) /* Real-time Timer Prescaler Value */ +#define AT91_RTT_ALMIEN(1 16) /* Alarm Interrupt Enable */ +#define AT91_RTT_RTTINCIEN (1 17) /* Real Time Timer Increment Interrupt Enable */ +#define AT91_RTT_RTTRST(1 18) /* Real Time Timer Restart */ + +/* + * We store ALARM_DISABLED in ALMV to record that no alarm is set. + * It's also the reset value for that field. + */ +#define ALARM_DISABLED ((u32)~0) + +#define rtt_readl(field) \ + readl(CONFIG_RTC_AT91SAM9_RTT + AT91_RTT_ ## field) +#define rtt_writel(field, val) \ + writel((val),
[U-Boot] [PATCH 0/1] at91samm9x: fix for the rtc-driver
Hello, here is corrected patch 2/2 to add an driver for at91sam9x which uses the internal RTT as RTC. Sorry for not testing my last minute changes before. It was late. ;) The previous send patch 1/2 which adds some defines is still needed. Tested on an AT91SAM9263. Kind regards, Alexander Holler ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] add new board pm9g45
Hello Tom, In respond of the message 4ba51dad.5020...@windriver.com you wrote: there is a second version of the this patch in e-mail with message-id 1268928021-31632-1-git-send-email-di...@ronetix.at and subject [U-Boot][PATCH v2] add new board pm9g45 from 18.03.2010. Regards, Asen ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Saving environment variables in MMC
Hello, --- On Mon, 29/3/10, Mike Frysinger vap...@gentoo.org wrote: From: Mike Frysinger vap...@gentoo.org Subject: Re: [U-Boot] Saving environment variables in MMC To: u-boot@lists.denx.de, nitin...@yahoo.com Date: Monday, 29 March, 2010, 11:12 PM On Monday 29 March 2010 11:21:22 Nitin Mahajan wrote: I want to save and retrieve environment variables from a file in MMC. Can I get some pointers towards this? Whether env_relocate_spec() and other such functions, has some implementation for MMC also? search the archives. some people have posted some patches recently. -mike I checked the mails and I would go through the patches. In addition to this, I need to modify the environment variables(stored in a file) from Linux userland. Whether it is OK to follow such an approach? For this whether tools\fw_env.c is the right option? regards -Nitin Get your preferred Email name! Now you can @ymail.com and @rocketmail.com. http://mail.promotions.yahoo.com/newdomains/aa/ ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Saving environment variables in MMC
2010/3/30 Nitin Mahajan nitin...@yahoo.com: Hello, --- On Mon, 29/3/10, Mike Frysinger vap...@gentoo.org wrote: From: Mike Frysinger vap...@gentoo.org Subject: Re: [U-Boot] Saving environment variables in MMC To: u-boot@lists.denx.de, nitin...@yahoo.com Date: Monday, 29 March, 2010, 11:12 PM On Monday 29 March 2010 11:21:22 Nitin Mahajan wrote: I want to save and retrieve environment variables from a file in MMC. Can I get some pointers towards this? Found this in the past: http://bitshrine.org/gpp/u-boot-200910-cd77dd10-save-the-env-var-to-SDcard-and-SPI.patch might be a useful starter. Have fun! Frans ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] doc: Fix ramdisk examples in doc/uImage.FIT/multi.its
The ramdisk sections in doc/uImage.FIT/multi.its lack
load address and entry point properties. Using examples
from this file will result in unbootable image, u-boot
will issue the following error messages:
Can't get ramdisk subimage load address!
Ramdisk image is corrupt or invalid
This patch adds missing properties to ramdisk sections.
Signed-off-by: Felix Radensky fe...@embedded-sol.com
---
doc/uImage.FIT/multi.its |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/doc/uImage.FIT/multi.its b/doc/uImage.FIT/multi.its
index a120da0..881b749 100644
--- a/doc/uImage.FIT/multi.its
+++ b/doc/uImage.FIT/multi.its
@@ -61,6 +61,8 @@
arch = ppc;
os = linux;
compression = gzip;
+ load = ;
+ entry = ;
h...@1 {
algo = sha1;
};
@@ -73,6 +75,8 @@
arch = ppc;
os = linux;
compression = gzip;
+ load = ;
+ entry = ;
h...@1 {
algo = crc32;
};
--
1.5.4.3
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[U-Boot] [PATCH v2] mpc86xx: set the DDR BATs after calculating true DDR size
From: Timur Tabi ti...@freescale.com
After determining how much DDR is actually in the system, set DBAT0 and
IBAT0 accordingly. This ensures that the CPU won't attempt to access
(via speculation) addresses outside of actual memory.
On 86xx systems, DBAT0 and IBAT0 (the BATs for DDR) are initialized to 2GB
and kept that way. If the system has less than 2GB of memory (typical for
an MPC8610 HPCD), the CPU may attempt to access this memory during
speculation. The zlib code is notorious for generating such memory reads,
and indeed on the MPC8610, uncompressing the Linux kernel causes a machine
check (without this patch).
Signed-off-by: Timur Tabi ti...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
* Fixed TO_BATU_BL to handle non-power of two
* Fixed write_bat to use computed 'bl' not always 2G size
* removed comment that wasn't need anymore
board/freescale/mpc8610hpcd/mpc8610hpcd.c |2 +
board/freescale/mpc8641hpcn/mpc8641hpcn.c |2 +
cpu/mpc86xx/cpu.c | 30 +
cpu/mpc86xx/cpu_init.c|4 +++
include/asm-ppc/mmu.h |6 -
include/configs/MPC8610HPCD.h |6 +---
include/configs/MPC8641HPCN.h |4 +--
include/mpc86xx.h |2 +
8 files changed, 48 insertions(+), 8 deletions(-)
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index 784a2ed..ab5f800 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -127,6 +127,8 @@ initdram(int board_type)
dram_size = fixed_sdram();
#endif
+ setup_ddr_bat(dram_size);
+
puts( DDR: );
return dram_size;
}
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index c521527..443c9fd 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -74,6 +74,8 @@ initdram(int board_type)
dram_size = fixed_sdram();
#endif
+ setup_ddr_bat(dram_size);
+
puts(DDR: );
return dram_size;
}
diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
index f7e012d..ac171f5 100644
--- a/cpu/mpc86xx/cpu.c
+++ b/cpu/mpc86xx/cpu.c
@@ -197,3 +197,33 @@ void mpc86xx_reginfo(void)
printf(\tBR7\t0x%08X\tOR7\t0x%08X \n, in_be32(lbc-br7),
in_be32(lbc-or7));
}
+
+/*
+ * Set the DDR BATs to reflect the actual size of DDR.
+ *
+ * dram_size is the actual size of DDR, in bytes
+ *
+ * Note: we assume that CONFIG_MAX_MEM_MAPPED is 2G or smaller as we only
+ * are using a single BAT to cover DDR.
+ *
+ * If this is not true, (e.g. CONFIG_MAX_MEM_MAPPED is 2GB but HID0_XBSEN
+ * is not defined) then we might have a situation where U-Boot will attempt
+ * to relocated itself outside of the region mapped by DBAT0.
+ * This will cause a machine check.
+ *
+ */
+void setup_ddr_bat(phys_addr_t dram_size)
+{
+ unsigned long batu, bl;
+
+ bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED));
+
+ if (BATU_SIZE(bl) != dram_size) {
+ u64 sz = (u64)dram_size - BATU_SIZE(bl);
+ print_size(sz, left unmapped\n);
+ }
+
+ batu = bl | BATU_VS | BATU_VP;
+ write_bat(DBAT0, batu, CONFIG_SYS_DBAT0L);
+ write_bat(IBAT0, batu, CONFIG_SYS_IBAT0L);
+}
diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c
index 5a78a9c..b4f047d 100644
--- a/cpu/mpc86xx/cpu_init.c
+++ b/cpu/mpc86xx/cpu_init.c
@@ -138,8 +138,12 @@ int cpu_init_r(void)
/* Set up BAT registers */
void setup_bats(void)
{
+#if defined(CONFIG_SYS_DBAT0U) defined(CONFIG_SYS_DBAT0L)
write_bat(DBAT0, CONFIG_SYS_DBAT0U, CONFIG_SYS_DBAT0L);
+#endif
+#if defined(CONFIG_SYS_IBAT0U) defined(CONFIG_SYS_IBAT0L)
write_bat(IBAT0, CONFIG_SYS_IBAT0U, CONFIG_SYS_IBAT0L);
+#endif
write_bat(DBAT1, CONFIG_SYS_DBAT1U, CONFIG_SYS_DBAT1L);
write_bat(IBAT1, CONFIG_SYS_IBAT1U, CONFIG_SYS_IBAT1L);
write_bat(DBAT2, CONFIG_SYS_DBAT2U, CONFIG_SYS_DBAT2L);
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index fd10249..ce7f081 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -213,7 +213,11 @@ extern void print_bats(void);
#define BATL_PADDR(x) ((phys_addr_t)((x 0xfffe) \
| ((x 0x0e00ULL) 24) \
| ((x 0x04ULL) 30)))
-#define BATU_SIZE(x) (1UL (fls((x BATU_BL_MAX) 2) + 17))
+#define BATU_SIZE(x) (1ULL (fls((x BATU_BL_MAX) 2) + 17))
+
+/* bytes into BATU_BL */
+#define TO_BATU_BL(x) \
+ (u32)1ull __ilog2_u64((u64)x)) / (128 * 1024)) - 1) * 4)
/* Used to set up SDR1 register */
#define HASH_TABLE_SIZE_64K0x0001
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 1d2d659..fed441e 100644
--- a/include/configs/MPC8610HPCD.h
+++
Re: [U-Boot] [PATCH v2] mpc86xx: set the DDR BATs after calculating true DDR size
Kumar Gala wrote:
+void setup_ddr_bat(phys_addr_t dram_size)
+{
+ unsigned long batu, bl;
+
+ bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED));
+
+ if (BATU_SIZE(bl) != dram_size) {
+ u64 sz = (u64)dram_size - BATU_SIZE(bl);
+ print_size(sz, left unmapped\n);
+ }
We still have the problem that, on a 1.5GB system, U-Boot will think that there
are 1.5GB of DDR, but the BAT will be set to 1GB. When U-Boot tries to
relocate itself, it will machine check.
We need a way to tell U-Boot that we only have 1GB of DDR, but still have it
tell Linux that we have 1.5GB of DDR.
--
Timur Tabi
Linux kernel developer at Freescale
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[U-Boot] [PATCH] 85xx: Add defines for BUCSR bits to make code more readable
Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- cpu/mpc85xx/release.S |5 +++-- cpu/mpc85xx/start.S |7 --- include/asm-ppc/processor.h |3 +++ 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index 00c4c54..36ea8c3 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Copyright 2008-2010 Freescale Semiconductor, Inc. * Kumar Gala kumar.g...@freescale.com * * See file CREDITS for list of people who contributed to this @@ -61,7 +61,8 @@ __secondary_start_page: #endif /* Enable branch prediction */ - li r3,0x201 + lis r3,bucsr_ena...@h + ori r3,r3,bucsr_ena...@l mtspr SPRN_BUCSR,r3 /* Ensure TB is 0 */ diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 386fa81..5f63979 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007-2009 Freescale Semiconductor, Inc. + * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc. * Copyright (C) 2003 Motorola,Inc. * * See file CREDITS for list of people who contributed to this @@ -185,8 +185,9 @@ _start_e500: /* Enable Branch Prediction */ #if defined(CONFIG_BTB) - li r0,0x201/* BBFI = 1, BPEN = 1 */ - mtspr BUCSR,r0 + lis r0,bucsr_ena...@h + ori r0,r0,bucsr_ena...@l + mtspr SPRN_BUCSR,r0 #endif #if defined(CONFIG_SYS_INIT_DBCR) diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index c6da411..b6aeb9f 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -531,6 +531,9 @@ #define SPRN_MCSRR00x23a /* Machine Check Save and Restore Register 0 */ #define SPRN_MCSRR10x23b /* Machine Check Save and Restore Register 1 */ #define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */ +#define BUCSR_BBFI0x0200 /* Branch buffer flash invalidate */ +#define BUCSR_BPEN0x0001 /* Branch prediction enable */ +#define BUCSR_ENABLE (BUCSR_BBFI|BUCSR_BPEN) #define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ #define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ #define SPRN_PID1 0x279 /* Process ID Register 1 */ -- 1.6.0.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] ppc/8xxx: Delete PCI nodes from device tree if not configured
If the PCI controller wasn't configured or enabled delete from the
device tree (include its alias).
For the case that we didn't even configure u-boot with knowledge of
the controller we can use the fact that the pci_controller pointer
is NULL to delete the node in the device tree. We determine that
a controller was not setup (because of HW config) based on the fact
that cfg_addr wasn't setup.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
drivers/pci/fsl_pci_init.c | 12 ++--
1 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index fe57926..3a60236 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -513,10 +513,18 @@ void ft_fsl_pci_setup(void *blob, const char *pci_alias,
struct pci_controller *hose)
{
int off = fdt_path_offset(blob, pci_alias);
+ u32 bus_range[2];
- if (off = 0) {
- u32 bus_range[2];
+ if (off 0)
+ return;
+
+ /* We assume a cfg_addr not being set means we didn't setup the
controller */
+ if ((hose == NULL) || (hose-cfg_addr == NULL)) {
+ fdt_del_node(blob, off);
+ off = fdt_path_offset(blob, /aliases);
+ fdt_delprop(blob, off, pci_alias);
+ } else {
bus_range[0] = 0;
bus_range[1] = hose-last_busno - hose-first_busno;
fdt_setprop(blob, off, bus-range, bus_range[0], 2*4);
--
1.6.0.6
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Re: [U-Boot] [PATCH v2] mpc86xx: set the DDR BATs after calculating true DDR size
On Mar 30, 2010, at 9:37 AM, Timur Tabi wrote:
Kumar Gala wrote:
+void setup_ddr_bat(phys_addr_t dram_size)
+{
+unsigned long batu, bl;
+
+bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED));
+
+if (BATU_SIZE(bl) != dram_size) {
+u64 sz = (u64)dram_size - BATU_SIZE(bl);
+print_size(sz, left unmapped\n);
+}
We still have the problem that, on a 1.5GB system, U-Boot will think that
there are 1.5GB of DDR, but the BAT will be set to 1GB. When U-Boot tries to
relocate itself, it will machine check.
We need a way to tell U-Boot that we only have 1GB of DDR, but still have it
tell Linux that we have 1.5GB of DDR.
is this situation you have today? (or just a concern?)
- k
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[U-Boot] [PATCH] fdt: Add fdt_del_node_and_alias helper
Add a helper function that given an alias will delete both the node
the alias points to and the alias itself
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
common/fdt_support.c | 13 +
include/fdt_support.h |2 ++
2 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index f89a3ee..dd46be9 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -757,3 +757,16 @@ int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size)
return -1;
}
#endif
+
+void fdt_del_node_and_alias(void *blob, char *alias)
+{
+ int off = fdt_path_offset(blob, alias);
+
+ if (off 0)
+ return;
+
+ fdt_del_node(blob, off);
+
+ off = fdt_path_offset(blob, /aliases);
+ fdt_delprop(blob, off, alias);
+}
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 0a9dd0d..e3949dd 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -81,5 +81,7 @@ int fdt_resize(void *blob);
int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size);
+void fdt_del_node_and_alias(void *blob, char *alias);
+
#endif /* ifdef CONFIG_OF_LIBFDT */
#endif /* ifndef __FDT_SUPPORT_H */
--
1.6.0.6
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Re: [U-Boot] [PATCH v2] mpc86xx: set the DDR BATs after calculating true DDR size
Kumar Gala wrote: We still have the problem that, on a 1.5GB system, U-Boot will think that there are 1.5GB of DDR, but the BAT will be set to 1GB. When U-Boot tries to relocate itself, it will machine check. We need a way to tell U-Boot that we only have 1GB of DDR, but still have it tell Linux that we have 1.5GB of DDR. is this situation you have today? (or just a concern?) Just a concern. Technically, we have the same problem on e500, except on e500 we use multiple TLBs to map the memory. In theory, we need at most one TLB/BAT per DIMM slot, which means we would need four BATS on the MPC8641 HPCN. Do we want to tell customers that U-Boot/Linux only supports power-of-two sizes of DDR? -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] ppc/8xxx: Delete PCI nodes from device tree if not configured
If the PCI controller wasn't configured or enabled delete from the
device tree (include its alias).
For the case that we didn't even configure u-boot with knowledge of
the controller we can use the fact that the pci_controller pointer
is NULL to delete the node in the device tree. We determine that
a controller was not setup (because of HW config) based on the fact
that cfg_addr wasn't setup.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
* Use new fdt_del_node_and_alias helper
drivers/pci/fsl_pci_init.c |9 +++--
1 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index fe57926..0d93686 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -513,10 +513,15 @@ void ft_fsl_pci_setup(void *blob, const char *pci_alias,
struct pci_controller *hose)
{
int off = fdt_path_offset(blob, pci_alias);
+ u32 bus_range[2];
- if (off = 0) {
- u32 bus_range[2];
+ if (off 0)
+ return;
+ /* We assume a cfg_addr not being set means we didn't setup the
controller */
+ if ((hose == NULL) || (hose-cfg_addr == NULL)) {
+ fdt_del_node_and_alias(blob, pci_alias);
+ } else {
bus_range[0] = 0;
bus_range[1] = hose-last_busno - hose-first_busno;
fdt_setprop(blob, off, bus-range, bus_range[0], 2*4);
--
1.6.0.6
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Re: [U-Boot] [PATCH v2] mpc86xx: set the DDR BATs after calculating true DDR size
On Mar 30, 2010, at 10:21 AM, Timur Tabi wrote: Kumar Gala wrote: We still have the problem that, on a 1.5GB system, U-Boot will think that there are 1.5GB of DDR, but the BAT will be set to 1GB. When U-Boot tries to relocate itself, it will machine check. We need a way to tell U-Boot that we only have 1GB of DDR, but still have it tell Linux that we have 1.5GB of DDR. is this situation you have today? (or just a concern?) Just a concern. Technically, we have the same problem on e500, except on e500 we use multiple TLBs to map the memory. In theory, we need at most one TLB/BAT per DIMM slot, which means we would need four BATS on the MPC8641 HPCN. Do we want to tell customers that U-Boot/Linux only supports power-of-two sizes of DDR? We can make this work by updating how get_effective_memsize() works in lib_ppc/board.c. We just need to make it aware of the amount of mapped memory. The simplest thing might be to just add in a gd-mem_map_size to deal with the issue on both 86xx/44x/85xx - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] mpc86xx: set the DDR BATs after calculating true DDR size
Kumar Gala wrote: We can make this work by updating how get_effective_memsize() works in lib_ppc/board.c. We just need to make it aware of the amount of mapped memory. Is this something you want handled in this patch? The simplest thing might be to just add in a gd-mem_map_size to deal with the issue on both 86xx/44x/85xx I don't know about 44x, but like I said, I don't think it's a problem in 85xx, because we use up to 8 TLBs to map DDR, which is more than enough to cover all memory size possibilities. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] mpc86xx: set the DDR BATs after calculating true DDR size
On Mar 30, 2010, at 10:32 AM, Timur Tabi wrote: Kumar Gala wrote: We can make this work by updating how get_effective_memsize() works in lib_ppc/board.c. We just need to make it aware of the amount of mapped memory. Is this something you want handled in this patch? Not really. I was trying to get this patch in a state that we could get it into v2010.03. That change is a bit more intrusive. So if 8610 works for you I'll add the patch into my tree for Wolfgang to pull. - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] mpc86xx: set the DDR BATs after calculating true DDR size
Kumar Gala wrote: Not really. I was trying to get this patch in a state that we could get it into v2010.03. That change is a bit more intrusive. Isn't it already too late for 2010.03? So if 8610 works for you I'll add the patch into my tree for Wolfgang to pull. I'll test it and let you know. But please add a comment to the changelog and/or source code that it will limit DDR for U-Boot and Linux to the next lowest power of two. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mpc86xx: set the DDR BATs after calculating true DDR size
On Mon, Mar 29, 2010 at 11:21 PM, Kumar Gala ga...@kernel.crashing.org wrote: Why do we need BATL_MEMCOHERENCE on 8641 but not on 8610? dual core on 8641, single core on 8610. The 8610 does lots of DMA for audio and video. Don't we need coherence for that? I read the e600 manual, but I couldn't glean whether we need the M bit set to make DMA work. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] fdt: Add fdt_del_node_and_alias helper
Add a helper function that given an alias will delete both the node
the alias points to and the alias itself
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
* Make alias param const
common/fdt_support.c | 13 +
include/fdt_support.h |2 ++
2 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index f89a3ee..0d0f513 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -757,3 +757,16 @@ int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size)
return -1;
}
#endif
+
+void fdt_del_node_and_alias(void *blob, const char *alias)
+{
+ int off = fdt_path_offset(blob, alias);
+
+ if (off 0)
+ return;
+
+ fdt_del_node(blob, off);
+
+ off = fdt_path_offset(blob, /aliases);
+ fdt_delprop(blob, off, alias);
+}
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 0a9dd0d..5388c29 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -81,5 +81,7 @@ int fdt_resize(void *blob);
int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size);
+void fdt_del_node_and_alias(void *blob, const char *alias);
+
#endif /* ifdef CONFIG_OF_LIBFDT */
#endif /* ifndef __FDT_SUPPORT_H */
--
1.6.0.6
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Re: [U-Boot] [PATCH] mpc86xx: set the DDR BATs after calculating true DDR size
On Mar 30, 2010, at 10:46 AM, Timur Tabi wrote: On Mon, Mar 29, 2010 at 11:21 PM, Kumar Gala ga...@kernel.crashing.org wrote: Why do we need BATL_MEMCOHERENCE on 8641 but not on 8610? dual core on 8641, single core on 8610. The 8610 does lots of DMA for audio and video. Don't we need coherence for that? I read the e600 manual, but I couldn't glean whether we need the M bit set to make DMA work. No, M in the core is only for other cores, has nothing to do w/DMAs. - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] mpc86xx: set the DDR BATs after calculating true DDR size
From: Timur Tabi ti...@freescale.com
After determining how much DDR is actually in the system, set DBAT0 and
IBAT0 accordingly. This ensures that the CPU won't attempt to access
(via speculation) addresses outside of actual memory.
On 86xx systems, DBAT0 and IBAT0 (the BATs for DDR) are initialized to 2GB
and kept that way. If the system has less than 2GB of memory (typical for
an MPC8610 HPCD), the CPU may attempt to access this memory during
speculation. The zlib code is notorious for generating such memory reads,
and indeed on the MPC8610, uncompressing the Linux kernel causes a machine
check (without this patch).
Currently we are limited to power of two sized DDR since we only use a
single bat. If a non-power of two size is used that is less than
CONFIG_MAX_MEM_MAPPED u-boot will crash.
Signed-off-by: Timur Tabi ti...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
* updated comments and copyright on cpu.c
board/freescale/mpc8610hpcd/mpc8610hpcd.c |2 +
board/freescale/mpc8641hpcn/mpc8641hpcn.c |2 +
cpu/mpc86xx/cpu.c | 36 -
cpu/mpc86xx/cpu_init.c|4 +++
include/asm-ppc/mmu.h |6 -
include/configs/MPC8610HPCD.h |6 +---
include/configs/MPC8641HPCN.h |4 +--
include/mpc86xx.h |2 +
8 files changed, 53 insertions(+), 9 deletions(-)
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index 784a2ed..ab5f800 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -127,6 +127,8 @@ initdram(int board_type)
dram_size = fixed_sdram();
#endif
+ setup_ddr_bat(dram_size);
+
puts( DDR: );
return dram_size;
}
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index c521527..443c9fd 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -74,6 +74,8 @@ initdram(int board_type)
dram_size = fixed_sdram();
#endif
+ setup_ddr_bat(dram_size);
+
puts(DDR: );
return dram_size;
}
diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
index f7e012d..1887575 100644
--- a/cpu/mpc86xx/cpu.c
+++ b/cpu/mpc86xx/cpu.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2006,2009 Freescale Semiconductor, Inc.
+ * Copyright 2006,2009-2010 Freescale Semiconductor, Inc.
* Jeff Brown
* Srikanth Srinivasan (srikanth.sriniva...@freescale.com)
*
@@ -197,3 +197,37 @@ void mpc86xx_reginfo(void)
printf(\tBR7\t0x%08X\tOR7\t0x%08X \n, in_be32(lbc-br7),
in_be32(lbc-or7));
}
+
+/*
+ * Set the DDR BATs to reflect the actual size of DDR.
+ *
+ * dram_size is the actual size of DDR, in bytes
+ *
+ * Note: we assume that CONFIG_MAX_MEM_MAPPED is 2G or smaller as we only
+ * are using a single BAT to cover DDR.
+ *
+ * If this is not true, (e.g. CONFIG_MAX_MEM_MAPPED is 2GB but HID0_XBSEN
+ * is not defined) then we might have a situation where U-Boot will attempt
+ * to relocated itself outside of the region mapped by DBAT0.
+ * This will cause a machine check.
+ *
+ * Currently we are limited to power of two sized DDR since we only use a
+ * single bat. If a non-power of two size is used that is less than
+ * CONFIG_MAX_MEM_MAPPED u-boot will crash.
+ *
+ */
+void setup_ddr_bat(phys_addr_t dram_size)
+{
+ unsigned long batu, bl;
+
+ bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED));
+
+ if (BATU_SIZE(bl) != dram_size) {
+ u64 sz = (u64)dram_size - BATU_SIZE(bl);
+ print_size(sz, left unmapped\n);
+ }
+
+ batu = bl | BATU_VS | BATU_VP;
+ write_bat(DBAT0, batu, CONFIG_SYS_DBAT0L);
+ write_bat(IBAT0, batu, CONFIG_SYS_IBAT0L);
+}
diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c
index 5a78a9c..b4f047d 100644
--- a/cpu/mpc86xx/cpu_init.c
+++ b/cpu/mpc86xx/cpu_init.c
@@ -138,8 +138,12 @@ int cpu_init_r(void)
/* Set up BAT registers */
void setup_bats(void)
{
+#if defined(CONFIG_SYS_DBAT0U) defined(CONFIG_SYS_DBAT0L)
write_bat(DBAT0, CONFIG_SYS_DBAT0U, CONFIG_SYS_DBAT0L);
+#endif
+#if defined(CONFIG_SYS_IBAT0U) defined(CONFIG_SYS_IBAT0L)
write_bat(IBAT0, CONFIG_SYS_IBAT0U, CONFIG_SYS_IBAT0L);
+#endif
write_bat(DBAT1, CONFIG_SYS_DBAT1U, CONFIG_SYS_DBAT1L);
write_bat(IBAT1, CONFIG_SYS_IBAT1U, CONFIG_SYS_IBAT1L);
write_bat(DBAT2, CONFIG_SYS_DBAT2U, CONFIG_SYS_DBAT2L);
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index fd10249..ce7f081 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -213,7 +213,11 @@ extern void print_bats(void);
#define BATL_PADDR(x) ((phys_addr_t)((x 0xfffe) \
| ((x 0x0e00ULL) 24) \
| ((x 0x04ULL) 30)))
-#define
Re: [U-Boot] [PATCH 1/3] fsl-ddr: Fix the turnaround timing for TIMING_CFG_4
On Mar 22, 2010, at 5:51 PM, Wolfgang Denk wrote: Dear Kumar Gala, In message 1269194951-17996-1-git-send-email-ga...@kernel.crashing.org you wrote: From: Dave Liu dave...@freescale.com Read-to-read/Write-to-write turnaround for same chip select of DDR3 memory, BL/2+2 cycles is enough for them at BC4 and OTF case, BL/2 cycles is enough for fixed BL8. Cutting down the turnaround from BL/2+4 to BL/2+2 or BL/2 will improve the memory performance. Signed-off-by: Dave Liu dave...@freescale.com --- cpu/mpc8xxx/ddr/ctrl_regs.c | 19 +-- 1 files changed, 13 insertions(+), 6 deletions(-) diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index adc4f6e..caac943 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Copyright 2008-2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License ... * Version 2 as published by the Free Software Foundation. As it turns out, basicly all FSL DDR code (and lots more of the FSL code) are GPL v2 only: board/freescale/mpc8323erdb/mpc8323erdb.c board/freescale/mpc8536ds/ddr.c board/freescale/mpc8540ads/ddr.c board/freescale/mpc8541cds/ddr.c board/freescale/mpc8544ds/ddr.c board/freescale/mpc8548cds/ddr.c board/freescale/mpc8555cds/ddr.c board/freescale/mpc8560ads/ddr.c board/freescale/mpc8568mds/ddr.c board/freescale/mpc8572ds/ddr.c board/freescale/mpc8610hpcd/ddr.c board/freescale/mpc8641hpcn/ddr.c board/freescale/mpc8569mds/ddr.c board/freescale/p2020ds/ddr.c board/mpc8540eval/ddr.c cpu/mpc85xx/ddr-gen2.c cpu/mpc85xx/ddr-gen1.c cpu/mpc85xx/ddr-gen3.c cpu/mpc86xx/ddr-8641.c cpu/mpc86xx/fdt.c cpu/mpc8xxx/ddr/common_timing_params.h cpu/mpc8xxx/ddr/Makefile cpu/mpc8xxx/ddr/lc_common_dimm_params.c cpu/mpc8xxx/ddr/ddr.h cpu/mpc8xxx/ddr/ddr1_dimm_params.c cpu/mpc8xxx/ddr/ddr2_dimm_params.c cpu/mpc8xxx/ddr/main.c cpu/mpc8xxx/ddr/ddr3_dimm_params.c cpu/mpc8xxx/ddr/util.c cpu/mpc8xxx/ddr/ctrl_regs.c cpu/mpc8xxx/ddr/options.c cpu/mpc8xxx/Makefile drivers/i2c/fsl_i2c.c drivers/pci/fsl_pci_init.c include/asm-m68k/fsl_i2c.h include/asm-ppc/fsl_i2c.h include/asm-ppc/fsl_ddr_dimm_params.h include/asm-ppc/fsl_law.h include/asm-ppc/mpc8xxx_spi.h include/asm-ppc/fsl_dma.h include/asm-ppc/fsl_ddr_sdram.h include/configs/MPC8323ERDB.h include/configs/MPC8610HPCD.h etc. etc. Can we please fix this? I'm looking into it, but am not holding up these patches on it. Ok? - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Please pull u-boot-mpc85xx for v2010.03
(I know these are late in the cycle, but they are bug fixes for issues see on HW). - k The following changes since commit 060f28532b09dd3d2c78423bdd809ac768a27629: Wolfgang Denk (1): cmd_usb.c: print debug messages only when DEBUG is defined are available in the git repository at: git://git.denx.de/u-boot-mpc85xx master Kumar Gala (1): 85xx: Fix enabling of L1 cache parity on secondary cores Timur Tabi (1): mpc86xx: set the DDR BATs after calculating true DDR size board/freescale/mpc8610hpcd/mpc8610hpcd.c |2 + board/freescale/mpc8641hpcn/mpc8641hpcn.c |2 + cpu/mpc85xx/release.S | 38 ++-- cpu/mpc85xx/start.S | 38 + cpu/mpc86xx/cpu.c | 36 ++- cpu/mpc86xx/cpu_init.c|4 +++ include/asm-ppc/mmu.h |6 - include/asm-ppc/processor.h |2 + include/configs/MPC8610HPCD.h |6 +--- include/configs/MPC8641HPCN.h |4 +-- include/mpc86xx.h |2 + 11 files changed, 118 insertions(+), 22 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] mpc86xx: set the DDR BATs after calculating true DDR size
Did I miss something here? Why did you change the coherence attribute
in the BAT? Please add an explanation to the comment, assuming you
have a good reason for this (I'm not awake enough to think about this
right now :)
Otherwise, a couple of minor nits below.
On Mar 30, 2010, at 9:25 AM, Kumar Gala wrote:
From: Timur Tabi ti...@freescale.com
After determining how much DDR is actually in the system, set DBAT0
and
IBAT0 accordingly. This ensures that the CPU won't attempt to access
(via speculation) addresses outside of actual memory.
On 86xx systems, DBAT0 and IBAT0 (the BATs for DDR) are initialized
to 2GB
and kept that way. If the system has less than 2GB of memory
(typical for
an MPC8610 HPCD), the CPU may attempt to access this memory during
speculation. The zlib code is notorious for generating such memory
reads,
and indeed on the MPC8610, uncompressing the Linux kernel causes a
machine
check (without this patch).
Signed-off-by: Timur Tabi ti...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
* Fixed TO_BATU_BL to handle non-power of two
* Fixed write_bat to use computed 'bl' not always 2G size
* removed comment that wasn't need anymore
board/freescale/mpc8610hpcd/mpc8610hpcd.c |2 +
board/freescale/mpc8641hpcn/mpc8641hpcn.c |2 +
cpu/mpc86xx/cpu.c | 30
+
cpu/mpc86xx/cpu_init.c|4 +++
include/asm-ppc/mmu.h |6 -
include/configs/MPC8610HPCD.h |6 +---
include/configs/MPC8641HPCN.h |4 +--
include/mpc86xx.h |2 +
8 files changed, 48 insertions(+), 8 deletions(-)
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/
freescale/mpc8610hpcd/mpc8610hpcd.c
index 784a2ed..ab5f800 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -127,6 +127,8 @@ initdram(int board_type)
dram_size = fixed_sdram();
#endif
+ setup_ddr_bat(dram_size);
+
puts( DDR: );
return dram_size;
}
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/
freescale/mpc8641hpcn/mpc8641hpcn.c
index c521527..443c9fd 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -74,6 +74,8 @@ initdram(int board_type)
dram_size = fixed_sdram();
#endif
+ setup_ddr_bat(dram_size);
+
puts(DDR: );
return dram_size;
}
diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
index f7e012d..ac171f5 100644
--- a/cpu/mpc86xx/cpu.c
+++ b/cpu/mpc86xx/cpu.c
@@ -197,3 +197,33 @@ void mpc86xx_reginfo(void)
printf(\tBR7\t0x%08X\tOR7\t0x%08X \n, in_be32(lbc-br7),
in_be32(lbc-or7));
}
+
+/*
+ * Set the DDR BATs to reflect the actual size of DDR.
+ *
+ * dram_size is the actual size of DDR, in bytes
+ *
+ * Note: we assume that CONFIG_MAX_MEM_MAPPED is 2G or smaller as
we only
+ * are using a single BAT to cover DDR.
+ *
+ * If this is not true, (e.g. CONFIG_MAX_MEM_MAPPED is 2GB but
HID0_XBSEN
+ * is not defined) then we might have a situation where U-Boot will
attempt
+ * to relocated itself outside of the region mapped by DBAT0.
+ * This will cause a machine check.
At the very least, fix this comment to mention the problem with not
being able to map all the RAM as well, if you're going to leave it
that way. Can you test a board with a strange amount of RAM (1.5GB,
or something), and see what happens with this patch? I really don't
like leaving things this way.
+ *
+ */
+void setup_ddr_bat(phys_addr_t dram_size)
+{
+ unsigned long batu, bl;
+
+ bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED));
+
+ if (BATU_SIZE(bl) != dram_size) {
+ u64 sz = (u64)dram_size - BATU_SIZE(bl);
+ print_size(sz, left unmapped\n);
+ }
+
+ batu = bl | BATU_VS | BATU_VP;
+ write_bat(DBAT0, batu, CONFIG_SYS_DBAT0L);
+ write_bat(IBAT0, batu, CONFIG_SYS_IBAT0L);
+}
diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c
index 5a78a9c..b4f047d 100644
--- a/cpu/mpc86xx/cpu_init.c
+++ b/cpu/mpc86xx/cpu_init.c
@@ -138,8 +138,12 @@ int cpu_init_r(void)
/* Set up BAT registers */
void setup_bats(void)
{
+#if defined(CONFIG_SYS_DBAT0U) defined(CONFIG_SYS_DBAT0L)
write_bat(DBAT0, CONFIG_SYS_DBAT0U, CONFIG_SYS_DBAT0L);
+#endif
+#if defined(CONFIG_SYS_IBAT0U) defined(CONFIG_SYS_IBAT0L)
write_bat(IBAT0, CONFIG_SYS_IBAT0U, CONFIG_SYS_IBAT0L);
+#endif
write_bat(DBAT1, CONFIG_SYS_DBAT1U, CONFIG_SYS_DBAT1L);
write_bat(IBAT1, CONFIG_SYS_IBAT1U, CONFIG_SYS_IBAT1L);
write_bat(DBAT2, CONFIG_SYS_DBAT2U, CONFIG_SYS_DBAT2L);
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index fd10249..ce7f081 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -213,7 +213,11 @@ extern void
Re: [U-Boot] [PATCH v2] mpc86xx: set the DDR BATs after calculating true DDR size
On Mar 30, 2010, at 12:02 PM, Becky Bruce wrote:
Did I miss something here? Why did you change the coherence attribute
in the BAT? Please add an explanation to the comment, assuming you
have a good reason for this (I'm not awake enough to think about this
right now :)
Ah, my brain comes online - I see you only did this for 8610. Carry
on :)
-B
Otherwise, a couple of minor nits below.
On Mar 30, 2010, at 9:25 AM, Kumar Gala wrote:
From: Timur Tabi ti...@freescale.com
After determining how much DDR is actually in the system, set DBAT0
and
IBAT0 accordingly. This ensures that the CPU won't attempt to access
(via speculation) addresses outside of actual memory.
On 86xx systems, DBAT0 and IBAT0 (the BATs for DDR) are initialized
to 2GB
and kept that way. If the system has less than 2GB of memory
(typical for
an MPC8610 HPCD), the CPU may attempt to access this memory during
speculation. The zlib code is notorious for generating such memory
reads,
and indeed on the MPC8610, uncompressing the Linux kernel causes a
machine
check (without this patch).
Signed-off-by: Timur Tabi ti...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
* Fixed TO_BATU_BL to handle non-power of two
* Fixed write_bat to use computed 'bl' not always 2G size
* removed comment that wasn't need anymore
board/freescale/mpc8610hpcd/mpc8610hpcd.c |2 +
board/freescale/mpc8641hpcn/mpc8641hpcn.c |2 +
cpu/mpc86xx/cpu.c | 30
+
cpu/mpc86xx/cpu_init.c|4 +++
include/asm-ppc/mmu.h |6 -
include/configs/MPC8610HPCD.h |6 +---
include/configs/MPC8641HPCN.h |4 +--
include/mpc86xx.h |2 +
8 files changed, 48 insertions(+), 8 deletions(-)
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/
freescale/mpc8610hpcd/mpc8610hpcd.c
index 784a2ed..ab5f800 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -127,6 +127,8 @@ initdram(int board_type)
dram_size = fixed_sdram();
#endif
+setup_ddr_bat(dram_size);
+
puts( DDR: );
return dram_size;
}
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/
freescale/mpc8641hpcn/mpc8641hpcn.c
index c521527..443c9fd 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -74,6 +74,8 @@ initdram(int board_type)
dram_size = fixed_sdram();
#endif
+setup_ddr_bat(dram_size);
+
puts(DDR: );
return dram_size;
}
diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
index f7e012d..ac171f5 100644
--- a/cpu/mpc86xx/cpu.c
+++ b/cpu/mpc86xx/cpu.c
@@ -197,3 +197,33 @@ void mpc86xx_reginfo(void)
printf(\tBR7\t0x%08X\tOR7\t0x%08X \n, in_be32(lbc-br7),
in_be32(lbc-or7));
}
+
+/*
+ * Set the DDR BATs to reflect the actual size of DDR.
+ *
+ * dram_size is the actual size of DDR, in bytes
+ *
+ * Note: we assume that CONFIG_MAX_MEM_MAPPED is 2G or smaller as
we only
+ * are using a single BAT to cover DDR.
+ *
+ * If this is not true, (e.g. CONFIG_MAX_MEM_MAPPED is 2GB but
HID0_XBSEN
+ * is not defined) then we might have a situation where U-Boot will
attempt
+ * to relocated itself outside of the region mapped by DBAT0.
+ * This will cause a machine check.
At the very least, fix this comment to mention the problem with not
being able to map all the RAM as well, if you're going to leave it
that way. Can you test a board with a strange amount of RAM (1.5GB,
or something), and see what happens with this patch? I really don't
like leaving things this way.
+ *
+ */
+void setup_ddr_bat(phys_addr_t dram_size)
+{
+unsigned long batu, bl;
+
+bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED));
+
+if (BATU_SIZE(bl) != dram_size) {
+u64 sz = (u64)dram_size - BATU_SIZE(bl);
+print_size(sz, left unmapped\n);
+}
+
+batu = bl | BATU_VS | BATU_VP;
+write_bat(DBAT0, batu, CONFIG_SYS_DBAT0L);
+write_bat(IBAT0, batu, CONFIG_SYS_IBAT0L);
+}
diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c
index 5a78a9c..b4f047d 100644
--- a/cpu/mpc86xx/cpu_init.c
+++ b/cpu/mpc86xx/cpu_init.c
@@ -138,8 +138,12 @@ int cpu_init_r(void)
/* Set up BAT registers */
void setup_bats(void)
{
+#if defined(CONFIG_SYS_DBAT0U) defined(CONFIG_SYS_DBAT0L)
write_bat(DBAT0, CONFIG_SYS_DBAT0U, CONFIG_SYS_DBAT0L);
+#endif
+#if defined(CONFIG_SYS_IBAT0U) defined(CONFIG_SYS_IBAT0L)
write_bat(IBAT0, CONFIG_SYS_IBAT0U, CONFIG_SYS_IBAT0L);
+#endif
write_bat(DBAT1, CONFIG_SYS_DBAT1U, CONFIG_SYS_DBAT1L);
write_bat(IBAT1, CONFIG_SYS_IBAT1U, CONFIG_SYS_IBAT1L);
write_bat(DBAT2, CONFIG_SYS_DBAT2U, CONFIG_SYS_DBAT2L);
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index fd10249..ce7f081 100644
---
Re: [U-Boot] [PATCH v2] mpc86xx: set the DDR BATs after calculating true DDR size
On Mar 30, 2010, at 10:33 AM, Kumar Gala wrote: On Mar 30, 2010, at 10:32 AM, Timur Tabi wrote: Kumar Gala wrote: We can make this work by updating how get_effective_memsize() works in lib_ppc/board.c. We just need to make it aware of the amount of mapped memory. Is this something you want handled in this patch? Not really. I was trying to get this patch in a state that we could get it into v2010.03. That change is a bit more intrusive. More intrusive, but needs to be done soon. Having u-boot thinking it has more ram than it does is fraught with peril. We shouldn't leave this as it is, or it's going to get swept under the rug until it bites us. -B ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] add CONFIG_SYS_FEC_NO_SHARED_PHY for MCF5445x
This patch adds the possibility to handle seperate PHYs to MCF5445x.
Naming is chosen to resemble the contrary CONFIG_FEC_SHARED_PHY in the
linux kernel.
Signed-off-by: Wolfgang Wegner w.weg...@astro-kom.de
---
cpu/mcf5445x/cpu_init.c | 11 +++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c
index 8d51d35..db03296 100644
--- a/cpu/mcf5445x/cpu_init.c
+++ b/cpu/mcf5445x/cpu_init.c
@@ -185,8 +185,19 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
struct fec_info_s *info = (struct fec_info_s *)dev-priv;
if (setclear) {
+#ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
+ if (info-iobase == CONFIG_SYS_FEC0_IOBASE)
+ gpio-par_feci2c |=
+ (GPIO_PAR_FECI2C_MDC0_MDC0 |
+GPIO_PAR_FECI2C_MDIO0_MDIO0);
+ else
+ gpio-par_feci2c |=
+ (GPIO_PAR_FECI2C_MDC1_MDC1 |
+GPIO_PAR_FECI2C_MDIO1_MDIO1);
+#else
gpio-par_feci2c |=
(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
+#endif
if (info-iobase == CONFIG_SYS_FEC0_IOBASE)
gpio-par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
--
1.5.6.5
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[U-Boot] [PATCH] add CONFIG_SYS_FEC_FULL_MII for MCF5445x
This patch adds support for full MII interface on MCF5445x (in contrast
to RMII as used on the evaluation boards).
Signed-off-by: Wolfgang Wegner w.weg...@astro-kom.de
---
cpu/mcf5445x/cpu_init.c | 13 +++--
1 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c
index db03296..2389019 100644
--- a/cpu/mcf5445x/cpu_init.c
+++ b/cpu/mcf5445x/cpu_init.c
@@ -207,10 +207,19 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
gpio-par_feci2c =
~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
- if (info-iobase == CONFIG_SYS_FEC0_IOBASE)
+ if (info-iobase == CONFIG_SYS_FEC0_IOBASE) {
+#ifdef CONFIG_SYS_FEC_FULL_MII
+ gpio-par_fec |= GPIO_PAR_FEC_FEC0_MII;
+#else
gpio-par_fec = GPIO_PAR_FEC_FEC0_UNMASK;
- else
+#endif
+ } else {
+#ifdef CONFIG_SYS_FEC_FULL_MII
+ gpio-par_fec |= GPIO_PAR_FEC_FEC1_MII;
+#else
gpio-par_fec = GPIO_PAR_FEC_FEC1_UNMASK;
+#endif
+ }
}
return 0;
}
--
1.5.6.5
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[U-Boot] [PATCH] fix lockup in mcfmii/mii_discover_phy() in case communication fails
Signed-off-by: Wolfgang Wegner w.weg...@astro-kom.de
---
drivers/net/mcfmii.c |6 +-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c
index 4acc29e..83c0873 100644
--- a/drivers/net/mcfmii.c
+++ b/drivers/net/mcfmii.c
@@ -185,7 +185,11 @@ int mii_discover_phy(struct eth_device *dev)
printf(PHY @ 0x%x pass %d\n, phyno, pass);
#endif
- for (i = 0; i (sizeof(phyinfo) /
sizeof(phy_info_t)); i++) {
+ for (i = 0;
+ (i (sizeof(phyinfo)
+ / sizeof(phy_info_t)))
+(phyinfo[i].phyid != 0);
+ i++) {
if (phyinfo[i].phyid == phytype) {
#ifdef ET_DEBUG
printf(phyid %x - %s\n,
--
1.5.6.5
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[U-Boot] [PATCH] add missing PCS3 for MCF5445x
This patch adds the code for handling PCS3 (DSPI chip select 3) in cpu_init.c and m5445x.h Signed-off-by: Wolfgang Wegner w.weg...@astro-kom.de --- cpu/mcf5445x/cpu_init.c |7 +++ include/asm-m68k/m5445x.h |1 + 2 files changed, 8 insertions(+), 0 deletions(-) diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c index 2389019..fdcd185 100644 --- a/cpu/mcf5445x/cpu_init.c +++ b/cpu/mcf5445x/cpu_init.c @@ -258,6 +258,10 @@ int cfspi_claim_bus(uint bus, uint cs) gpio-par_dspi = ~GPIO_PAR_DSPI_PCS2_PCS2; gpio-par_dspi |= GPIO_PAR_DSPI_PCS2_PCS2; break; + case 3: + gpio-par_dma = GPIO_PAR_DMA_DACK0_UNMASK; + gpio-par_dma |= GPIO_PAR_DMA_DACK0_PCS3; + break; case 5: gpio-par_dspi = ~GPIO_PAR_DSPI_PCS5_PCS5; gpio-par_dspi |= GPIO_PAR_DSPI_PCS5_PCS5; @@ -284,6 +288,9 @@ void cfspi_release_bus(uint bus, uint cs) case 2: gpio-par_dspi = ~GPIO_PAR_DSPI_PCS2_PCS2; break; + case 3: + gpio-par_dma = GPIO_PAR_DMA_DACK0_UNMASK; + break; case 5: gpio-par_dspi = ~GPIO_PAR_DSPI_PCS5_PCS5; break; diff --git a/include/asm-m68k/m5445x.h b/include/asm-m68k/m5445x.h index dfddde6..c575b8f 100644 --- a/include/asm-m68k/m5445x.h +++ b/include/asm-m68k/m5445x.h @@ -314,6 +314,7 @@ #define GPIO_PAR_DMA_DREQ1_GPIO(0x00) #define GPIO_PAR_DMA_DACK0_UNMASK (0xF3) #define GPIO_PAR_DMA_DACK0_DACK1 (0x0C) +#define GPIO_PAR_DMA_DACK0_PCS3(0x08) #define GPIO_PAR_DMA_DACK0_ULPI_DIR(0x04) #define GPIO_PAR_DMA_DACK0_GPIO(0x00) #define GPIO_PAR_DMA_DREQ0_DREQ0 (0x01) -- 1.5.6.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] add CONFIG_SYS_FEC_NO_SHARED_PHY for MCF5445x
Acked.
Best Regards,
TsiChung
-Original Message-
From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de]
On Behalf Of Wolfgang Wegner
Sent: Tuesday, March 30, 2010 12:20 PM
To: u-boot@lists.denx.de
Cc: Wolfgang Wegner
Subject: [U-Boot] [PATCH] add CONFIG_SYS_FEC_NO_SHARED_PHY for MCF5445x
This patch adds the possibility to handle seperate PHYs to MCF5445x.
Naming is chosen to resemble the contrary CONFIG_FEC_SHARED_PHY in the
linux kernel.
Signed-off-by: Wolfgang Wegner w.weg...@astro-kom.de
---
cpu/mcf5445x/cpu_init.c | 11 +++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c index
8d51d35..db03296 100644
--- a/cpu/mcf5445x/cpu_init.c
+++ b/cpu/mcf5445x/cpu_init.c
@@ -185,8 +185,19 @@ int fecpin_setclear(struct eth_device *dev, int
setclear)
struct fec_info_s *info = (struct fec_info_s *)dev-priv;
if (setclear) {
+#ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
+ if (info-iobase == CONFIG_SYS_FEC0_IOBASE)
+ gpio-par_feci2c |=
+ (GPIO_PAR_FECI2C_MDC0_MDC0 |
+GPIO_PAR_FECI2C_MDIO0_MDIO0);
+ else
+ gpio-par_feci2c |=
+ (GPIO_PAR_FECI2C_MDC1_MDC1 |
+GPIO_PAR_FECI2C_MDIO1_MDIO1);
+#else
gpio-par_feci2c |=
(GPIO_PAR_FECI2C_MDC0_MDC0 |
GPIO_PAR_FECI2C_MDIO0_MDIO0);
+#endif
if (info-iobase == CONFIG_SYS_FEC0_IOBASE)
gpio-par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
--
1.5.6.5
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Re: [U-Boot] [PATCH] add missing PCS3 for MCF5445x
Acked. Best Regards, TsiChung -Original Message- From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Wolfgang Wegner Sent: Tuesday, March 30, 2010 12:21 PM To: u-boot@lists.denx.de Cc: Wolfgang Wegner Subject: [U-Boot] [PATCH] add missing PCS3 for MCF5445x This patch adds the code for handling PCS3 (DSPI chip select 3) in cpu_init.c and m5445x.h Signed-off-by: Wolfgang Wegner w.weg...@astro-kom.de --- cpu/mcf5445x/cpu_init.c |7 +++ include/asm-m68k/m5445x.h |1 + 2 files changed, 8 insertions(+), 0 deletions(-) diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c index 2389019..fdcd185 100644 --- a/cpu/mcf5445x/cpu_init.c +++ b/cpu/mcf5445x/cpu_init.c @@ -258,6 +258,10 @@ int cfspi_claim_bus(uint bus, uint cs) gpio-par_dspi = ~GPIO_PAR_DSPI_PCS2_PCS2; gpio-par_dspi |= GPIO_PAR_DSPI_PCS2_PCS2; break; + case 3: + gpio-par_dma = GPIO_PAR_DMA_DACK0_UNMASK; + gpio-par_dma |= GPIO_PAR_DMA_DACK0_PCS3; + break; case 5: gpio-par_dspi = ~GPIO_PAR_DSPI_PCS5_PCS5; gpio-par_dspi |= GPIO_PAR_DSPI_PCS5_PCS5; @@ -284,6 +288,9 @@ void cfspi_release_bus(uint bus, uint cs) case 2: gpio-par_dspi = ~GPIO_PAR_DSPI_PCS2_PCS2; break; + case 3: + gpio-par_dma = GPIO_PAR_DMA_DACK0_UNMASK; + break; case 5: gpio-par_dspi = ~GPIO_PAR_DSPI_PCS5_PCS5; break; diff --git a/include/asm-m68k/m5445x.h b/include/asm-m68k/m5445x.h index dfddde6..c575b8f 100644 --- a/include/asm-m68k/m5445x.h +++ b/include/asm-m68k/m5445x.h @@ -314,6 +314,7 @@ #define GPIO_PAR_DMA_DREQ1_GPIO(0x00) #define GPIO_PAR_DMA_DACK0_UNMASK (0xF3) #define GPIO_PAR_DMA_DACK0_DACK1 (0x0C) +#define GPIO_PAR_DMA_DACK0_PCS3(0x08) #define GPIO_PAR_DMA_DACK0_ULPI_DIR(0x04) #define GPIO_PAR_DMA_DACK0_GPIO(0x00) #define GPIO_PAR_DMA_DREQ0_DREQ0 (0x01) -- 1.5.6.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2 v2] net, fec_mxc: only setup the device enetaddr with eeprom value, if ethaddr is not setup
if ethaddr is not setup in the environment, fill the device
enetaddr with the contents of the eeprom, and only
the device enetaddr, not the mac address registers!
Tested on the magnesium board.
Signed-off-by: Heiko Schocher h...@denx.de
---
- changes since v1 posted here:
http://lists.denx.de/pipermail/u-boot/2010-March/069192.html
- splitted in two patches as Wolfgang suggested
drivers/net/fec_mxc.c |9 +
1 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 5af9cdb..98ff64b 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -749,10 +749,11 @@ static int fec_probe(bd_t *bd)
eth_register(edev);
- if (fec_get_hwaddr(edev, ethaddr) == 0) {
- printf(got MAC address from EEPROM: %pM\n, ethaddr);
- memcpy(edev-enetaddr, ethaddr, 6);
- fec_set_hwaddr(edev);
+ if (!eth_getenv_enetaddr(ethaddr, ethaddr)) {
+ if (fec_get_hwaddr(edev, ethaddr) == 0) {
+ printf(got MAC address from EEPROM: %pM\n, ethaddr);
+ memcpy(edev-enetaddr, ethaddr, 6);
+ }
}
return 0;
--
1.6.2.5
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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