[U-Boot] environmental baudrate not used at boot up
Hi list, I have a board based on an Atmel AT91SAM9263-EK running U-boot 2009.01. I can't seem to get the environmental variable baudrate to be used properly, though. Here's the sequence: 1. Power on board, baudrate=115200 2. setenv baudrate 9600 (change terminal baud to 9600) saveenv saveenv reset 3. Gibberish is output to the terminal at 9600 4. Change terminal baud to 115200, everything ok As much as I've looked through the code in lib_arm/board.c, serial_init() and init_baudrate() seem to be coded correctly. Any advice on where to take it from here? Thanks, Chris ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] environmental baudrate not used at boot up
Le 16/01/2011 15:01, chr...@cyberswitching.com a écrit : Hi list, I have a board based on an Atmel AT91SAM9263-EK running U-boot 2009.01. I can't seem to get the environmental variable baudrate to be used properly, though. Here's the sequence: 1. Power on board, baudrate=115200 2. setenv baudrate 9600 (change terminal baud to 9600) saveenv saveenv reset 3. Gibberish is output to the terminal at 9600 4. Change terminal baud to 115200, everything ok As much as I've looked through the code in lib_arm/board.c, serial_init() and init_baudrate() seem to be coded correctly. Any advice on where to take it from here? Hmm... 2009.1 is very old code. Current u-boot-at91/master seems to build at91sam9263ek; maybe you could try it. Thanks, Chris Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] environmental baudrate not used at boot up
On Sun, Jan 16, 2011 at 03:42:25PM +0100, Albert ARIBAUD wrote: Le 16/01/2011 15:01, chr...@cyberswitching.com a ?crit : I have a board based on an Atmel AT91SAM9263-EK running U-boot 2009.01. I can't seem to get the environmental variable baudrate to be used properly, though. Hmm... 2009.1 is very old code. Current u-boot-at91/master seems to build at91sam9263ek; maybe you could try it. Hi Albert, Thanks for the advice. I had considered that prior to sending the message to the list, but wanted to verify if the problem was fixed there before porting over all the board-specific code just for a test. (I don't have the -EK board anymore.) If anyone out there has a -EK working with the latest and can provide some insights on whether this works, it would be much appreciated! Thanks, Chris ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] iMX5: EfikaMX: Preliminary board support
On 01/13/2011 06:27 PM, Marek Vasut wrote: As for the PMIC, other boards don't use any #defines for those constants either, which obviously doens't mean it's right. Well, this is not true. You use in yourd board a lot of these constants. There are only a few of them that are not used and + + /* NOTE: if (is_soc_rev(CHIP_REV_2_0) = 0) */ You can drop this line + + /* Set core voltage to 1.1V */ + val = pmic_reg_read(REG_SW_0); + val = (val (~0x1F)) | 0x14; + pmic_reg_write(REG_SW_0, val); Values are defined in Table 47 in MC13892.h manual. The low level is 0.6 Volt, that corresponds to 0x0, and each bit increments the voltage by 25mV. I can suggest to add a macro to mc13892.h that return the value for register when the desired voltage (in millivolt) is passed. + + /* Setup VCC (SW2) to 1.25 */ + val = pmic_reg_read(REG_SW_1); + val = (val (~0x1F)) | 0x1A; + pmic_reg_write(REG_SW_1, val); ..and use it here, too. + + /* Setup 1V2_DIG1 (SW3) to 1.25 */ + val = pmic_reg_read(REG_SW_2); + val = (val (~0x1F)) | 0x1A; + pmic_reg_write(REG_SW_2, val); + udelay(50); ..and here. +/** I have not checked before, but this is not the coding style for multiline comments. -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: off...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] SPI: mxc_spi: fix swapping bug and add missing swapping in unaligned rx case
We need to shift only one time in each cycle in the swapping loop
for unaligned tx case. Currently two byte shift operations are
performed in each loop cycle causing zero gaps in the transmited
data, so not all data scheduled for transmition is actually
transmited.
The proper swapping in unaligned rx case is missing, so add it
as we need to put the received data into the rx buffer in the
correct byte order.
Signed-off-by: Anatolij Gustschin ag...@denx.de
---
drivers/spi/mxc_spi.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index d558137..9ed2891 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -304,7 +304,7 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int
bitlen,
/* Buffer is not 32-bit aligned */
if ((unsigned long)dout 0x03) {
data = 0;
- for (i = 0; i 4; i++, data = 8) {
+ for (i = 0; i 4; i++) {
data = (data 8) | (*dout++ 0xFF);
}
} else {
@@ -337,11 +337,11 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int
bitlen,
if (bitlen % 32) {
data = reg_read(mxcs-base + MXC_CSPIRXDATA);
cnt = (bitlen % 32) / 8;
+ data = cpu_to_be32(data) ((sizeof(data) - cnt) * 8);
debug(SPI Rx unaligned: 0x%x\n, data);
if (din) {
- for (i = 0; i cnt; i++, data = 8) {
- *din++ = data 0xFF;
- }
+ memcpy(din, data, cnt);
+ din += cnt;
}
nbytes -= cnt;
}
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] SPI: mxc_spi: add SPI clock calculation and setup to the driver
The MXC SPI driver didn't calculate the SPI clock up to
now and just used lowest possible divider 512 for DATA
RATE in the control register. This results in very low
transfer rates.
The patch adds code to calculate and setup the SPI clock
frequency for transfers.
Signed-off-by: Anatolij Gustschin ag...@denx.de
---
drivers/spi/mxc_spi.c | 22 +-
1 files changed, 21 insertions(+), 1 deletions(-)
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 9ed2891..07c62c2 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -438,12 +438,25 @@ static int decode_cs(struct mxc_spi_slave *mxcs, unsigned
int cs)
return cs;
}
+u32 get_cspi_div(u32 div)
+{
+ int i;
+
+ for (i = 0; i 8; i++) {
+ if (div = (4 i))
+ return i;
+ }
+ return i;
+}
+
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
unsigned int ctrl_reg;
struct mxc_spi_slave *mxcs;
int ret;
+ u32 clk_src;
+ u32 div;
if (bus = ARRAY_SIZE(spi_bases))
return NULL;
@@ -477,9 +490,16 @@ struct spi_slave *spi_setup_slave(unsigned int bus,
unsigned int cs,
return NULL;
}
#else
+ clk_src = mx31_get_ipg_clk();
+ div = clk_src / max_hz;
+ div = get_cspi_div(div);
+
+ debug(clk %d Hz, div %d, real clk %d Hz\n,
+ max_hz, div, clk_src / (4 div));
+
ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
MXC_CSPICTRL_BITCOUNT(31) |
- MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */
+ MXC_CSPICTRL_DATARATE(div) |
MXC_CSPICTRL_EN |
MXC_CSPICTRL_MODE;
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/2] arm: a320 timer: move static data to global_data struct
Dear Wolfgang, On Mon, Dec 20, 2010 at 5:00 PM, Po-Yu Chuang ratbert.chu...@gmail.com wrote: From: Po-Yu Chuang ratb...@faraday-tech.com timer.c used static data and are called before relocation. Move all static variables into global_data structure. Also cleanup timer.c from unused stubs and make it truly use 64 bit tick values. Based on Reinhard Meyer u-b...@emk-elektronik.de's patch 5dca710a3d7703e41da0e9894f2d71f9e25bea6b Signed-off-by: Po-Yu Chuang ratb...@faraday-tech.com --- v2: rebase use gd-timer_rate_hz. remove unused global variable timestamp and lastdec. move register bases to local variables arch/arm/cpu/arm920t/a320/timer.c | 147 ++--- 1 files changed, 56 insertions(+), 91 deletions(-) Would you please check this patch series? Or should I rebase and resubmit? best regards, Po-Yu Chuang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4] mpq101: initial support for Mercury Computer Systems MPQ101 board
Environment is configured to precede the actual u-boot image so that it's located at the beginning of flash erase block (made necessary by the recent changes to the embedded environment handling). I assume customer linker script is because of where you have the environment. If so might be useful to add that to the commit comment. I was under impression that commit message and comment in the linker script make it rather clear. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] sh: add checking the CONFIG_SYS_NO_FLASH
Signed-off-by: Yoshihiro Shimoda yoshihiro.shimoda...@renesas.com
---
arch/sh/lib/board.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c
index cdac382..b8cd8f3 100644
--- a/arch/sh/lib/board.c
+++ b/arch/sh/lib/board.c
@@ -43,6 +43,7 @@ const char version_string[] = U_BOOT_VERSION (U_BOOT_DATE
- U_BOOT_TIME);
unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
+#if !defined(CONFIG_SYS_NO_FLASH)
static int sh_flash_init(void)
{
gd-bd-bi_flashsize = flash_init();
@@ -54,6 +55,7 @@ static int sh_flash_init(void)
return 0;
}
+#endif
#if defined(CONFIG_CMD_NAND)
# include nand.h
@@ -125,7 +127,9 @@ init_fnc_t *init_sequence[] =
dram_init, /* SDRAM init */
timer_init, /* SuperH Timer (TCNT0 only) init */
sh_mem_env_init,
+#if !defined(CONFIG_SYS_NO_FLASH)
sh_flash_init, /* Flash memory(NOR) init*/
+#endif
INIT_FUNC_NAND_INIT/* Flash memory (NAND) init */
INIT_FUNC_PCI_INIT /* PCI init */
stdio_init,
@@ -157,7 +161,9 @@ void sh_generic_init(void)
bd = gd-bd;
bd-bi_memstart = CONFIG_SYS_SDRAM_BASE;
bd-bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+#if !defined(CONFIG_SYS_NO_FLASH)
bd-bi_flashstart = CONFIG_SYS_FLASH_BASE;
+#endif
#if defined(CONFIG_SYS_SRAM_BASE) defined(CONFIG_SYS_SRAM_SIZE)
bd-bi_sramstart = CONFIG_SYS_SRAM_BASE;
bd-bi_sramsize = CONFIG_SYS_SRAM_SIZE;
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] add checking the CONFIG_ENV_IS_IN_SPI_FLASH in Enbedded env
Fix the problem which cannot build the U-boot, if we only set the CONFIG_ENV_IS_IN_SPI_FLASH. Signed-off-by: Yoshihiro Shimoda yoshihiro.shimoda...@renesas.com --- include/environment.h |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/environment.h b/include/environment.h index 082b3e1..8a4f393 100644 --- a/include/environment.h +++ b/include/environment.h @@ -106,6 +106,7 @@ extern unsigned long nand_env_oob_offset; /* Embedded env is only supported for some flash types */ #ifdef CONFIG_ENV_IS_EMBEDDED # if !defined(CONFIG_ENV_IS_IN_FLASH) \ + !defined(CONFIG_ENV_IS_IN_SPI_FLASH) \ !defined(CONFIG_ENV_IS_IN_NAND) \ !defined(CONFIG_ENV_IS_IN_ONENAND) # error CONFIG_ENV_IS_EMBEDDED not supported for your flash type -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] spi: add support SuperH SPI module
SH7757 has SPI module. This patch supports it.
Signed-off-by: Yoshihiro Shimoda yoshihiro.shimoda...@renesas.com
---
drivers/spi/Makefile |1 +
drivers/spi/sh_spi.c | 295 ++
2 files changed, 296 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/sh_spi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index e34a124..d582fbb 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -37,6 +37,7 @@ COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
+COBJS-$(CONFIG_SH_SPI) += sh_spi.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/spi/sh_spi.c b/drivers/spi/sh_spi.c
new file mode 100644
index 000..89ea5e2
--- /dev/null
+++ b/drivers/spi/sh_spi.c
@@ -0,0 +1,295 @@
+/*
+ * SH SPI driver
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ */
+
+#include common.h
+#include malloc.h
+#include spi.h
+#include asm/io.h
+
+#define SPI_TBR0x00
+#define SPI_RBR0x00
+#define SPI_CR10x08
+#define SPI_CR20x10
+#define SPI_CR30x18
+#define SPI_CR40x20
+
+/* CR1 */
+#define SPI_TBE0x80
+#define SPI_TBF0x40
+#define SPI_RBE0x20
+#define SPI_RBF0x10
+#define SPI_PFONRD 0x08
+#define SPI_SSDB 0x04
+#define SPI_SSD0x02
+#define SPI_SSA0x01
+
+/* CR2 */
+#define SPI_RSTF 0x80
+#define SPI_LOOPBK 0x40
+#define SH_SPI_CPOL0x20
+#define SH_SPI_CPHA0x10
+#define SPI_L1M0 0x08
+
+/* CR3 */
+#define SPI_MAX_BYTE 0xFF
+
+/* CR4 */
+#define SPI_TBEI 0x80
+#define SPI_TBFI 0x40
+#define SPI_RBEI 0x20
+#define SPI_RBFI 0x10
+#define SPI_WPABRT 0x04
+#define SPI_SSS0x01
+
+#define SPI_FIFO_SIZE 32
+
+static void sh_spi_write(unsigned long data, unsigned long offset)
+{
+ writel(data, CONFIG_SH_SPI_BASE + offset);
+}
+
+static unsigned long sh_spi_read(unsigned long offset)
+{
+ return readl(CONFIG_SH_SPI_BASE + offset);
+}
+
+static void sh_spi_set_bit(unsigned long val, unsigned long offset)
+{
+ unsigned long tmp;
+
+ tmp = sh_spi_read(offset);
+ tmp |= val;
+ sh_spi_write(tmp, offset);
+}
+
+static void sh_spi_clear_bit(unsigned long val, unsigned long offset)
+{
+ unsigned long tmp;
+
+ tmp = sh_spi_read(offset);
+ tmp = ~val;
+ sh_spi_write(tmp, offset);
+}
+
+static void clear_fifo(void)
+{
+ sh_spi_set_bit(SPI_RSTF, SPI_CR2);
+ sh_spi_clear_bit(SPI_RSTF, SPI_CR2);
+}
+
+static int recvbuf_wait(void)
+{
+ while (sh_spi_read(SPI_CR1) SPI_RBE) {
+ if (ctrlc())
+ return 1;
+ udelay(10);
+ }
+ return 0;
+}
+
+static int write_fifo_full_wait(void)
+{
+ while (sh_spi_read(SPI_CR1) SPI_TBF) {
+ udelay(10);
+ if (ctrlc())
+ return 1;
+ }
+ return 0;
+}
+
+static int write_fifo_empty_wait(void)
+{
+ while (!(sh_spi_read(SPI_CR1) SPI_TBE)) {
+ if (ctrlc())
+ return 1;
+ udelay(10);
+ }
+ return 0;
+}
+
+void spi_init(void)
+{
+
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct spi_slave *slave;
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
+ slave = malloc(sizeof(struct spi_slave));
+ if (!slave)
+ return NULL;
+
+ slave-bus = bus;
+ slave-cs = cs;
+
+ /* SPI sycle stop */
+ sh_spi_write(0xfe, SPI_CR1);
+ /* CR1 init */
+ sh_spi_write(0x00, SPI_CR1);
+ /* CR3 init */
+ sh_spi_write(0x00, SPI_CR3);
+
+ clear_fifo();
+
+ /* 1/8 clock */
+ sh_spi_write(sh_spi_read(SPI_CR2) | 0x07, SPI_CR2);
+ udelay(10);
+
+ return slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ free(slave);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ return 0;
+}
+
+void
[U-Boot] [PATCH 1/2] net: sh_eth: add cache handling
Some CPU needs cache handling. So this patch add the config of CONFIG_SH_ETHER_CACHE_WRITEBACK, and it calls wback function. Signed-off-by: Yoshihiro Shimoda yoshihiro.shimoda...@renesas.com --- drivers/net/sh_eth.c |9 + 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 86cc324..53d918d 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -36,6 +36,12 @@ #ifndef CONFIG_SH_ETHER_PHY_ADDR # error Please define CONFIG_SH_ETHER_PHY_ADDR #endif +#ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK +#define flush_cache_wback(addr, len) \ + dcache_wback_range((u32)addr, (u32)(addr + len - 1)) +#else +#define flush_cache_wback(...) +#endif #define SH_ETH_PHY_DELAY 5 @@ -197,6 +203,7 @@ int sh_eth_send(struct eth_device *dev, volatile void *packet, int len) } /* Update tx descriptor */ + flush_cache_wback(packet, len); port_info-tx_desc_cur-td2 = ADDR_TO_PHY(packet); port_info-tx_desc_cur-td1 = len 16; /* Must preserve the end of descriptor list indication */ @@ -312,6 +319,7 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) tmp_addr = (u32) (((int)port_info-tx_desc_malloc + TX_DESC_SIZE - 1) ~(TX_DESC_SIZE - 1)); + flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s)); /* Make sure we use a P2 address (non-cacheable) */ port_info-tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr); port_info-tx_desc_cur = port_info-tx_desc_base; @@ -361,6 +369,7 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) tmp_addr = (u32) (((int)port_info-rx_desc_malloc + RX_DESC_SIZE - 1) ~(RX_DESC_SIZE - 1)); + flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s)); /* Make sure we use a P2 address (non-cacheable) */ port_info-rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr); -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] net: sh_eth: add support for SH7757's ETHER
SH7757 has ETHER and GETHER. This patch supports EHTER only.
Signed-off-by: Yoshihiro Shimoda yoshihiro.shimoda...@renesas.com
---
drivers/net/sh_eth.c | 42 --
drivers/net/sh_eth.h | 53 +++--
2 files changed, 89 insertions(+), 6 deletions(-)
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 53d918d..155acca 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -277,6 +277,7 @@ int sh_eth_recv(struct eth_device *dev)
static int sh_eth_reset(struct sh_eth_dev *eth)
{
int port = eth-port;
+#if defined(CONFIG_CPU_SH7763)
int ret = 0, i;
/* Start e-dmac transmitter and receiver */
@@ -296,6 +297,13 @@ static int sh_eth_reset(struct sh_eth_dev *eth)
}
return ret;
+#else
+ outl(inl(EDMR(port)) | EDMR_SRST, EDMR(port));
+ udelay(3000);
+ outl(inl(EDMR(port)) ~EDMR_SRST, EDMR(port));
+
+ return 0;
+#endif
}
static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
@@ -339,9 +347,11 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
/* Point the controller to the tx descriptor list. Must use physical
addresses */
outl(ADDR_TO_PHY(port_info-tx_desc_base), TDLAR(port));
+#if defined(CONFIG_CPU_SH7763)
outl(ADDR_TO_PHY(port_info-tx_desc_base), TDFAR(port));
outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port));
outl(0x01, TDFFR(port));/* Last discriptor bit */
+#endif
err:
return ret;
@@ -405,9 +415,11 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
/* Point the controller to the rx descriptor list */
outl(ADDR_TO_PHY(port_info-rx_desc_base), RDLAR(port));
+#if defined(CONFIG_CPU_SH7763)
outl(ADDR_TO_PHY(port_info-rx_desc_base), RDFAR(port));
outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port));
outl(RDFFR_RDLF, RDFFR(port));
+#endif
return ret;
@@ -532,11 +544,18 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
outl(0, TFTR(port));
outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port));
outl(RMCR_RST, RMCR(port));
+#ifndef CONFIG_CPU_SH7757
outl(0, RPADIR(port));
+#endif
outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port));
/* Configure e-mac registers */
+#if defined(CONFIG_CPU_SH7757)
+ outl(ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP |
+ ECSIPR_MPDIP | ECSIPR_ICDIP, ECSIPR(port));
+#else
outl(0, ECSIPR(port));
+#endif
/* Set Mac address */
val = dev-enetaddr[0] 24 | dev-enetaddr[1] 16 |
@@ -547,11 +566,16 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
outl(val, MALR(port));
outl(RFLR_RFL_MIN, RFLR(port));
+#ifndef CONFIG_CPU_SH7757
outl(0, PIPR(port));
+#endif
outl(APR_AP, APR(port));
outl(MPR_MP, MPR(port));
+#ifdef CONFIG_CPU_SH7757
+ outl(TPAUSER_UNLIMITED, TPAUSER(port));
+#else
outl(TPAUSER_TPAUSE, TPAUSER(port));
-
+#endif
/* Configure phy */
ret = sh_eth_phy_config(eth);
if (ret) {
@@ -562,6 +586,8 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
phy_status = sh_eth_mii_read_phy_reg(port, port_info-phy_addr, 1);
/* Set the transfer speed */
+ val = 0x0;
+#ifdef CONFIG_CPU_SH7763
if (phy_status (PHY_S_100X_F|PHY_S_100X_H)) {
printf(SHETHER_NAME : 100Base/);
outl(GECMR_100B, GECMR(port));
@@ -569,14 +595,24 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
printf(SHETHER_NAME : 10Base/);
outl(GECMR_10B, GECMR(port));
}
+#endif
+#if defined(CONFIG_CPU_SH7757)
+ if (phy_status (PHY_S_100X_F|PHY_S_100X_H)) {
+ printf(100Base/);
+ outl(1, RTRATE(port));
+ } else {
+ printf(10Base/);
+ outl(0, RTRATE(port));
+ }
+#endif
/* Check if full duplex mode is supported by the phy */
if (phy_status (PHY_S_100X_F|PHY_S_10T_F)) {
printf(Full\n);
- outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port));
+ outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port));
} else {
printf(Half\n);
- outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port));
+ outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port));
}
return ret;
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index e153849..51e5d5b 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -1,5 +1,5 @@
/*
- * sh_eth.h - Driver for Renesas SH7763's gigabit ethernet controler.
+ * sh_eth.h - Driver for Renesas SuperH ethernet controler.
*
* Copyright (C) 2008 Renesas Solutions Corp.
* Copyright (c) 2008 Nobuhiro Iwamatsu
@@ -30,7 +30,11 @@
#define ADDR_TO_P2(addr) int)(addr) ~0xe000) | 0xa000))
/* The ethernet controller needs to
[U-Boot] [PATCH] sh: add support for sh7757lcr board
The R0P7757LC0030RL board has SH7757, 256MB DDR3-SDRAM, SPI ROM, Ethernet, and more. This patch supports the following functions: - 256MB DDR3-SDRAM - SPI ROM - Ethernet Signed-off-by: Yoshihiro Shimoda yoshihiro.shimoda...@renesas.com --- arch/sh/include/asm/cpu_sh4.h |2 + arch/sh/include/asm/cpu_sh7757.h| 263 +++ board/renesas/sh7757lcr/Makefile| 42 +++ board/renesas/sh7757lcr/config.mk | 28 ++ board/renesas/sh7757lcr/lowlevel_init.S | 558 +++ board/renesas/sh7757lcr/sh7757lcr.c | 436 board/renesas/sh7757lcr/spi-boot.c | 111 ++ board/renesas/sh7757lcr/u-boot.lds | 101 ++ boards.cfg |1 + doc/README.sh7757lcr| 64 include/configs/sh7757lcr.h | 143 11 files changed, 1749 insertions(+), 0 deletions(-) create mode 100644 arch/sh/include/asm/cpu_sh7757.h create mode 100644 board/renesas/sh7757lcr/Makefile create mode 100644 board/renesas/sh7757lcr/config.mk create mode 100644 board/renesas/sh7757lcr/lowlevel_init.S create mode 100644 board/renesas/sh7757lcr/sh7757lcr.c create mode 100644 board/renesas/sh7757lcr/spi-boot.c create mode 100644 board/renesas/sh7757lcr/u-boot.lds create mode 100644 doc/README.sh7757lcr create mode 100644 include/configs/sh7757lcr.h diff --git a/arch/sh/include/asm/cpu_sh4.h b/arch/sh/include/asm/cpu_sh4.h index fdcebd6..9b29d3a 100644 --- a/arch/sh/include/asm/cpu_sh4.h +++ b/arch/sh/include/asm/cpu_sh4.h @@ -44,6 +44,8 @@ # include asm/cpu_sh7722.h #elif defined (CONFIG_CPU_SH7723) # include asm/cpu_sh7723.h +#elif defined (CONFIG_CPU_SH7757) +# include asm/cpu_sh7757.h #elif defined (CONFIG_CPU_SH7763) # include asm/cpu_sh7763.h #elif defined (CONFIG_CPU_SH7780) diff --git a/arch/sh/include/asm/cpu_sh7757.h b/arch/sh/include/asm/cpu_sh7757.h new file mode 100644 index 000..eb9ff5b --- /dev/null +++ b/arch/sh/include/asm/cpu_sh7757.h @@ -0,0 +1,263 @@ +/* + * Copyright (C) 2011 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CPU_SH7757_H_ +#define _ASM_CPU_SH7757_H_ + +#define CCR0xFF1C +#define WTCNT 0xFFCC +#define CCR_CACHE_INIT 0x090b +#defineCACHE_OC_NUM_WAYS 1 + +/* Exception */ +#define EXPEVT 0xff24 +#define INTEVT 0xff28 + +/* Watchdog */ +#define WTCSR0 0xffcc0002 +#define WRSTCSR_R 0xffcc0003 +#define WRSTCSR_W 0xffcc0002 +#define WTCSR_PREFIX 0xa500 +#define WRSTCSR_PREFIX 0x6900 +#define WRSTCSR_WOVF_PREFIX0x9600 + + +/* SCIF */ +#define SCIF0_BASE 0xfe4b /* The real name is SCIF2 */ +#define SCIF1_BASE 0xfe4c /* The real name is SCIF3 */ +#define SCIF2_BASE 0xfe4d /* The real name is SCIF4 */ + +/* SerMux */ +#define SMR0 0xfe47 + +/* TMU0 */ +#define TSTR 0xFE430004 +#define TOCR 0xFE43 +#define TSTR0 0xFE430004 +#define TCOR0 0xFE430008 +#define TCNT0 0xFE43000C +#define TCR0 0xFE430010 +#define TCOR1 0xFE430014 +#define TCNT1 0xFE430018 +#define TCR1 0xFE43001C +#define TCOR2 0xFE430020 +#define TCNT2 0xFE430024 +#define TCR2 0xFE430028 +#define TCPR2 0xFE43002C + +/* BSC */ +#define BCR0xFE801000 +#define CS0BCR 0xFF802000 +#define CS0WCR 0xFF802008 +#define CS4BCR 0xFF802040 +#define CS4WCR 0xFF802048 +#define CS5BCR 0xFF802050 +#define CS5WCR 0xFF802058 +#define CS6BCR 0xFF802060 +#define CS6WCR 0xFF802068 + +/* DDR3IF */ +#define DDR3IF_BASE0xfe80 +#define DBSTATE0 (DDR3IF_BASE + 0x0008) +#define DBSTATE1 (DDR3IF_BASE + 0x000c) +#define DBACEN (DDR3IF_BASE + 0x0010) +#define DBRFEN (DDR3IF_BASE + 0x0014) +#define DBCMD (DDR3IF_BASE + 0x0018) +#define DBWAIT (DDR3IF_BASE + 0x001c) +#define DBKIND (DDR3IF_BASE + 0x0020) +#define DBCONF (DDR3IF_BASE + 0x0024) +#define DBTR0 (DDR3IF_BASE + 0x0040) +#define DBTR1 (DDR3IF_BASE + 0x0044) +#define DBTR2
Re: [U-Boot] [RFC PATCH v2] ARM: Avoid compiler optimization for usages of readb, writeb and friends.
Hello, Am 20.12.2010 17:08, schrieb John Rigby: Earlier in this thread Alexander said: I haven't add the definitions which are using a memory barrier because I haven't found a place in the kernel where they were actually enabled (CONFIG_ARM_DMA_MEM_BUFFERABLE). Because I've just run again into such a search problem: Don't use git grep on a kernel configured for x86, when you are searching an option for another architecture. ;) Regards, Alexander ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH][v1] Fix wrong CONFIG_SYS_MPC85xx_SERDES1_ADDR
CONFIG_SYS_MPC85xx_SERDES1_ADDR was defined wrong as
CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET.
It should be as
CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET.
Signed-off-by: Prabhakar prabha...@freescale.com
---
Based of http://git.denx.de/u-boot.git (branch master)
Top commit:
commit c6b734f5aea2ba75caaa1929f7e649ecda8d2f31
Merge: 072f412 a972089
Author: Wolfgang Denk w...@denx.de
Date: Wed Jan 12 23:59:53 2011 +0100
Merge branch 'master' of git://git.denx.de/u-boot-sh
Changes for v1: Incorporated Wolfgang Denk's comments
- Fixed header length to 74
- Rebased to http://git.denx.de/u-boot.git (branch master)
arch/powerpc/include/asm/immap_85xx.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 30c64eb..6a2daf2 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2307,7 +2307,7 @@ typedef struct ccsr_pme {
#define CONFIG_SYS_MPC85xx_CPM_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
#define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
#define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
--
1.6.3.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V4 0/5] Add Pantheon soc and dkb board support
-Original Message- From: Lei Wen [mailto:lei...@marvell.com] Sent: Tuesday, January 11, 2011 6:05 AM To: Wolfgang Denk; u-boot@lists.denx.de; Prafulla Wadaskar; Yu Tang; Ashish Karkare; Prabhanjan Sarnaik; Lei Wen Subject: [PATCH V4 0/5] Add Pantheon soc and dkb board support This patch set add the Pantheon soc and dkb board support. V2: This patch seris update the seperate mv_common part as suggested. V3: Fix config.h include place and copyright claim year. V4: Add change log to each patch. Lei Wen (5): mv: seperate kirkwood and armada from common setting ARM: Add Support for Marvell Pantheon Familiy SoCs serial: add pantheon soc support mvmfp: add MFP configuration support for PANTHEON Pantheon: Add Board Support for Marvell dkb board MAINTAINERS |4 + arch/arm/cpu/arm926ejs/pantheon/Makefile | 46 ++ arch/arm/cpu/arm926ejs/pantheon/cpu.c | 78 ++ arch/arm/cpu/arm926ejs/pantheon/dram.c| 130 arch/arm/cpu/arm926ejs/pantheon/timer.c | 204 + arch/arm/include/asm/arch-armada100/config.h | 50 ++ arch/arm/include/asm/arch-kirkwood/config.h | 145 ++ arch/arm/include/asm/arch-pantheon/config.h | 44 ++ arch/arm/include/asm/arch-pantheon/cpu.h | 79 ++ arch/arm/include/asm/arch-pantheon/mfp.h | 42 + arch/arm/include/asm/arch-pantheon/pantheon.h | 54 +++ board/Marvell/dkb/Makefile| 51 ++ board/Marvell/dkb/dkb.c | 53 +++ boards.cfg|1 + drivers/gpio/mvmfp.c |2 + drivers/serial/serial.c |2 + include/configs/aspenite.h|1 + include/configs/dkb.h | 64 include/configs/mv-common.h | 147 +++--- 19 files changed, 1071 insertions(+), 126 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/pantheon/Makefile create mode 100644 arch/arm/cpu/arm926ejs/pantheon/cpu.c create mode 100644 arch/arm/cpu/arm926ejs/pantheon/dram.c create mode 100644 arch/arm/cpu/arm926ejs/pantheon/timer.c create mode 100644 arch/arm/include/asm/arch-armada100/config.h create mode 100644 arch/arm/include/asm/arch-kirkwood/config.h create mode 100644 arch/arm/include/asm/arch-pantheon/config.h create mode 100644 arch/arm/include/asm/arch-pantheon/cpu.h create mode 100644 arch/arm/include/asm/arch-pantheon/mfp.h create mode 100644 arch/arm/include/asm/arch-pantheon/pantheon.h create mode 100644 board/Marvell/dkb/Makefile create mode 100644 board/Marvell/dkb/dkb.c create mode 100644 include/configs/dkb.h Dear Lei Acked-by: Prafulla Wadaskar prafu...@marvell.com This is valid for entire patch series. I will pull those patches to u-boot-marvell.git Regards.. Prafulla . . ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5] mpq101: initial support for Mercury Computer Systems MPQ101 board
Mpq101 is a RapidIO development board in AMC form factor, featuring MPC8548 processor, 512MB of hardwired DDR2 RAM, 128MB of hardwired NAND flash memory, real time clock and additional serial EEPROM on i2c bus (enabled). USB controller is available, but not presently enabled. Additional board information is available at: http://www.mc.com/products/boards/ensemble_mpq101_rapidio_powerquicc_iii.aspx Environment is configured to precede the actual u-boot image so that it's located at the beginning of flash erase block (made necessary by the recent changes to the embedded environment handling). This is achieved by means of custom ld script. Signed-off-by: Alex Dubov oa...@yahoo.com --- Changes for v5: - Use new common SRIO configuration definitions. - Replace initdram() with platform required fixed_sdram(). - Don't use get_ram_size() in fixed_sdram() as TLBs are set after it exits by common platform code. Changes for v4: - Replace config.mk supplied linker flags with custom linker script. - Fix checkpatch errors. Changes for v3: - Use io accessor functions for all mmio accesses. - Add configuration options for RTC and EEPROM on I2C buses. Changes for v2: - Remove some stale configuration code from board initialization functions. MAINTAINERS |3 + board/mercury/mpq101/Makefile | 53 ++ board/mercury/mpq101/law.c | 52 + board/mercury/mpq101/mpq101.c | 129 + board/mercury/mpq101/tlb.c | 82 board/mercury/mpq101/u-boot.lds | 132 + boards.cfg |1 + include/configs/mpq101.h| 391 +++ 8 files changed, 843 insertions(+), 0 deletions(-) create mode 100644 board/mercury/mpq101/Makefile create mode 100644 board/mercury/mpq101/law.c create mode 100644 board/mercury/mpq101/mpq101.c create mode 100644 board/mercury/mpq101/tlb.c create mode 100644 board/mercury/mpq101/u-boot.lds create mode 100644 include/configs/mpq101.h diff --git a/MAINTAINERS b/MAINTAINERS index a799037..d0fc7dc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -138,6 +138,9 @@ Jon Diekema jon.diek...@smiths-aerospace.com sbc8260 MPC8260 +Alex Dubov oa...@yahoo.com + mpq101 MPC8548 + Dirk Eibach eib...@gdsys.de devconcenterPPC460EX diff --git a/board/mercury/mpq101/Makefile b/board/mercury/mpq101/Makefile new file mode 100644 index 000..58bc1b3 --- /dev/null +++ b/board/mercury/mpq101/Makefile @@ -0,0 +1,53 @@ +# +# Copyright 2007 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS-y+= $(BOARD).o +COBJS-y+= law.o +COBJS-y+= tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB):$(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/mercury/mpq101/law.c b/board/mercury/mpq101/law.c new file mode 100644 index 000..0e23a6a --- /dev/null +++ b/board/mercury/mpq101/law.c @@ -0,0 +1,52 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, w...@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of
