Re: [U-Boot] [U-BOOT] [PATCH V2] bootm: replace blob_start with image_start
Le 04/02/2011 03:32, Lei Wen a écrit :
> Hi Albert,
>
> On Mon, Jan 10, 2011 at 6:21 PM, Lei Wen wrote:
>> For uImage always has a 64 bytes header, we couldn't expect to do
>> the xip from the header but should xip from the image start.
>>
>> The latter logic in that section is also move the image from image_start
>> to the load address, so sync this logic to the xip operation.
>>
>> Signed-off-by: Lei Wen
>> ---
>> V2: keep the original XIP setting to compare with blob_start.
>> This would make original uImage still could works, since
>> it modify the make uImage Makefile in the kernel.
>>
>> common/cmd_bootm.c |2 +-
>> 1 files changed, 1 insertions(+), 1 deletions(-)
>>
>> diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
>> index 18019d6..778f6a4 100644
>> --- a/common/cmd_bootm.c
>> +++ b/common/cmd_bootm.c
>> @@ -344,7 +344,7 @@ static int bootm_load_os(image_info_t os, ulong
>> *load_end, int boot_progress)
>>
>> switch (comp) {
>> case IH_COMP_NONE:
>> - if (load == blob_start) {
>> + if (load == blob_start || load == image_start) {
>> printf (" XIP %s ... ", type_name);
>> } else {
>> printf (" Loading %s ... ", type_name);
>> --
>> 1.7.0.4
>
> How about merge this patch into arm git tree?
Mike,
Did you re-test patch V2?
> Thanks,
> Lei
Amicalement,
--
Albert.
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Re: [U-Boot] [PATCH] arm relocation: Fix calculation of board_init_r
Hi Alexander, Le 03/02/2011 21:52, Alexander Stein a écrit : > Signed-off-by: Alexander Stein > --- > Hello, > > I just played a bit with my at91sam9g20ek and tried using a new u-boot. > So I compiled 656b990daa84bfdd512407ee2e3d2610e305a455 (atmel/wip110202) load > it into memory using jtag to 0x2200 while it was linked to 0x2000. Side note: loading and starting U-Boot at an address different from the one which it was linked for is not currently supported. > I stepped through the relocation code and at start.S:291 'mov pc, lr' the pc > gets an invalid address (0x25F81D70 while memory ends at 0x2400). > While stepping to start.S:286 some registers have the following contents: > r0: 0d70 > r1: 2200 > r9: 03f81000 > lr: 22000d70 > The content if r0 seems ok, but r1 seems wrong, it should be 0x2000. > Indeed r1 should contain the linked address of _start not the address > relative from the current code. Correct, since we're trying to find the post-relocation address of board_init_r, we should add the relocation offet to its link-time address, not run-time address -- the fact that both are the same right now is only incidental. Thus: Applied to u-boot-arm, thanks. Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] BSS footprint of FAT very high - SPL issues
Hi Aneesh, Le 03/02/2011 11:38, Aneesh V a écrit : > On second thoughts I would like to keep the entire bss in SDRAM. With > MMC and FAT support, the SPL is already nearing the IRAM budget in > OMAP3. It helps to save some space by moving out bss to SDRAM. > > If needed, I can fix up the start.S by defining something like > _end_of_data. But is that really needed. I do not see any SPL that > needs relocation and SDRAM bss at the same time. "Patches Welcome" :) -- with added thanks for patching all start.S / u-boot.lds in the ARM arch consistently. > Best regards, > Aneesh Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V8 0/5] Add Pantheon soc and dkb board support
Hi All, Le 28/01/2011 10:19, Lei Wen a écrit : > This patch set add the Pantheon soc and dkb board support. Prafulla, Is this patchset going to go into u-boot-marvell and requested for pull before 2011-03 is out? Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch V6 0/4] Add basic NVIDIA Tegra2 SoC support
Le 02/02/2011 19:44, Albert ARIBAUD a écrit : > Le 02/02/2011 18:06, Tom Warren a écrit : >> Mike, >> >> On Wed, Feb 2, 2011 at 12:57 AM, Mike Rapoport wrote: >>> On 02/02/11 02:09, Tom Warren wrote: I haven't seen any new feedback on this version (V6) of the patchset since it was posted. Wolfgang, Mike, Peter, et al - are you happy with the current patch? >>> >>> I'm Ok with the current patch. >> Thanks, Mike. Appreciate your help. >>> If so, when can I expect it to be pushed? >> Who has to push/accept/apply the patch? Wolfgang, or the ARM custodian? > > That would be me. Wolfgang, since the V1 patch series predates the merge > window close and you have not yet pulled in my request, do you accept > that I take these patches in and re-send a pull request? Seeing as rc1 is out with my previous pull request pulled in: Patchset applied to u-boot-arm (with trivial merge to boards.cfg), will send a new pull request today for rc2. Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-BOOT] [PATCH] env: reduce the stack footprint for the env buf
Hi Wolfgang, On Sat, Feb 5, 2011 at 5:18 AM, Wolfgang Denk wrote: > Dear Lei Wen, > > In message <1296788903-7604-1-git-send-email-lei...@marvell.com> you wrote: >> Original env buf directly locate at stack lead large stack footprint >> when call those env functions. It is not good when the system memory >> is critical or only want the uboot run at restrict range, that is not >> to touch the memory of other place at its best. >> >> So now this patch move the env buf to the heap area, which reduce the >> area uboot need to touch. > > In which way do you think this will save any memory? This patch is not intend to save memory... > > Your switch from automatic variables to manually allocated ones has, > in my opinion several disadvantages: > > 1) It increases the code size. Yes, I agree. > > 2) It increases the probability of bugs like memory leaks etc. > > 3) Instead of using the stack, which gets allocated fully dynamically > and gets freed guaranteed completely when the function returns, > you now need at least the same space in the malloc arena - where > you have to allocate it statically, and where allocations of > buffers like that can easily lead to memory fragmentation, > increasing the memory footprint further. > > Did you do any specific measurements of memory footprint, or what > makes you believe your code is preferrable? One of our project need to confine the ddr usage of uboot in the smallest case, not to pollute other area. So for us, the small stack is good one... For now the uboot is relocated to the end of the dram, and malloc area is almost a fix value, uboot would live happily in this area. But for env case, it allocate a range which could be large, due to the CONFIG_ENV_SIZE could be a big one, in the stack range. Because the stack is grown downwards, so it takes more memory range than it is allocated in the malloc method. Best regards, Lei ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] IXP42x patch series version 3
Dear Michael Schwingen, In message <1296860763-16149-1-git-send-email-mich...@schwingen.org> you wrote: > > here is the third incarnation of the IXP patch series. I hope I addressed > all the comments from version 2: > - timer system now uses no BSS-based variables > - use I/O accessors > - remove config.mk from board directories > - set -ffunction-sections/--gc-sections globally (for IXP architecture) Sorry, but please consider it all NAKed. See the note at bullet 2 at http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions for the rationale. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de "We don't have to protect the environment -- the Second Coming is at hand." - James Watt ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 16/17] IXP42x PCI rewrite
clean up IXP PCI handling: get rid of IXP-private bus scan, BAR assign etc.
code and use u-boot's PCI infrastructure instead. Move board-specific PCI
setup code (clock/reset) to board directory.
Signed-off-by: Michael Schwingen
---
arch/arm/include/asm/arch-ixp/ixp425pci.h | 130 +--
drivers/pci/pci.c |4 -
drivers/pci/pci_indirect.c| 13 +-
drivers/pci/pci_ixp.c | 608 ++---
4 files changed, 213 insertions(+), 542 deletions(-)
diff --git a/arch/arm/include/asm/arch-ixp/ixp425pci.h
b/arch/arm/include/asm/arch-ixp/ixp425pci.h
index 9ea3319..acafea7 100644
--- a/arch/arm/include/asm/arch-ixp/ixp425pci.h
+++ b/arch/arm/include/asm/arch-ixp/ixp425pci.h
@@ -22,88 +22,21 @@
* MA 02111-1307 USA
*/
-#ifndef _IXP425PCI_H_
-#define _IXP425PCI_H_
+#ifndef _IXP425PCI_H
+#define _IXP425PCI_H
-#define TRUE 1
-#define FALSE 0
#define OK 0
#define ERROR -1
-#define BOOL int
-#define IXP425_PCI_MAX_BAR_PER_FUNC 6
-#define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC * \
- IXP425_PCI_MAX_FUNC_ON_BUS)
-
-enum PciBarId
-{
- CSR_BAR=0,
- IO_BAR,
- SD_BAR,
- NO_BAR
-};
-
-/*Base address register descriptor*/
-typedef struct
-{
- unsigned int size;
- unsigned int address;
-} PciBar;
-
-typedef struct
-{
- unsigned int bus;
- unsigned int device;
- unsigned int func;
- unsigned int irq;
- BOOL error;
- unsigned short vendor_id;
- unsigned short device_id;
- /*We need an extra entry in this array for dummy placeholder*/
- PciBar bar[IXP425_PCI_MAX_BAR_PER_FUNC + 1];
-} PciDevice;
+struct pci_controller;
+extern void pci_ixp_init(struct pci_controller *hose);
/* Mask definitions*/
-#define IXP425_PCI_TOP_WORD_OF_LONG_MASK 0x
-#define IXP425_PCI_TOP_BYTE_OF_LONG_MASK 0xff00
-#define IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK0x
-#define IXP425_PCI_BOTTOM_TRIBYTES_OF_LONG_MASK 0x00ff
#define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK 0x000f
-#define IXP425_PCI_MAX_UINT32 0x
-
-
-#define IXP425_PCI_BAR_QUERY 0x
-
-#define IXP425_PCI_BAR_MEM_BASE 0x10
-#define IXP425_PCI_BAR_IO_BASE 0x00
-
-/*define the maximum number of bus segments - we support a single segment*/
-#define IXP425_PCI_MAX_BUS 1
-/*define the maximum number of cards per bus segment*/
-#define IXP425_PCI_MAX_DEV 4
-/*define the maximum number of functions per device*/
-#define IXP425_PCI_MAX_FUNC 8
-/* define the maximum number of separate functions that we can
- potentially have on the bus*/
-#define IXP425_PCI_MAX_FUNC_ON_BUS (1+ IXP425_PCI_MAX_FUNC * \
- IXP425_PCI_MAX_DEV *\
- IXP425_PCI_MAX_BUS)
-/*define the maximum number of BARs per function*/
-#define IXP425_PCI_MAX_BAR_PER_FUNC 6
-#define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC * \
- IXP425_PCI_MAX_FUNC_ON_BUS)
#define PCI_NP_CBE_BESL (4)
#define PCI_NP_AD_FUNCSL (8)
-#define REG_WRITE(b,o,v) (*(volatile unsigned int*)((b+o))=(v))
-#define REG_READ(b,o,v) ((v)=(*(volatile unsigned int*)((b+o
-
-#define PCI_DELAY 500
-#define USEC_LOOP_COUNT 533
-#define PCI_SETTLE_USEC 200
-#define PCI_MIN_RESET_ASSERT_USEC 2000
-
/*Register addressing definitions for PCI controller configuration
and status registers*/
@@ -150,28 +83,6 @@ typedef struct
#define NP_CMD_CONFIGWRITE (0xb)
*/
-/*define the default setting of the AHB memory base reg*/
-#define IXP425_PCI_AHBMEMBASE_DEFAULT 0x00010203
-#define IXP425_PCI_AHBIOBASE_DEFAULT 0x0
-#define IXP425_PCI_PCIMEMBASE_DEFAULT 0x0
-
-/*define the default settings for the controller's BARs*/
-#ifdef IXP425_PCI_SIMPLE_MAPPING
-#define IXP425_PCI_BAR_0_DEFAULT 0x
-#define IXP425_PCI_BAR_1_DEFAULT 0x0100
-#define IXP425_PCI_BAR_2_DEFAULT 0x0200
-#define IXP425_PCI_BAR_3_DEFAULT 0x0300
-#define IXP425_PCI_BAR_4_DEFAULT 0x
-#define IXP425_PCI_BAR_5_DEFAULT 0x
-#else
-#define IXP425_PCI_BAR_0_DEFAULT 0x4000
-#define IXP425_PCI_BAR_1_DEFAULT 0x4100
-#define IXP425_PCI_BAR_2_DEFAULT 0x4200
-#define IXP425_PCI_BAR_3_DEFAULT 0x4300
-#define IXP425_PCI_BAR_4_DEFAULT 0x
-#define IXP425_PCI_BAR_5_DEFAULT 0x
-#endif
-
/*Configuration Port register bit definitions*/
#define PCI_CRP_WRITE BIT(16)
@@ -228,17 +139,6 @@ typedef struct
#define PCI_CFG_SPECIAL_USE0x41
#define PCI_CFG_MODE 0x43
-/*Specify the initial command we send to PCI devices*/
-#define INITIAL_PCI_CMD (PCI_CMD_IO_ENABLE\
-| PCI_CMD_MEM_ENABLE \
-| PCI_CMD_MASTER_ENABLE \
-| PCI_CMD_WI_ENABLE)
-
-/*define the sub vendor and subsystem to be used */
-#define IXP425_
[U-Boot] [PATCH 10/17] update/fix AcTux3 board
Signed-off-by: Michael Schwingen
---
board/actux3/actux3.c| 126 +++--
board/actux3/config.mk |6 --
board/actux3/u-boot.lds | 53
include/configs/actux3.h | 38 +-
4 files changed, 120 insertions(+), 103 deletions(-)
delete mode 100644 board/actux3/config.mk
diff --git a/board/actux3/actux3.c b/board/actux3/actux3.c
index 63bf365..bfcf508 100644
--- a/board/actux3/actux3.c
+++ b/board/actux3/actux3.c
@@ -36,72 +36,76 @@
#include
#include
#include
-
#include
-
#include "actux3_hw.h"
DECLARE_GLOBAL_DATA_PTR;
-int board_init (void)
+int board_early_init_f(void)
+{
+ /* CS1: IPAC-X */
+ writel(0x94d10013, IXP425_EXP_CS1);
+ /* CS5: Debug port */
+ writel(0x9d520003, IXP425_EXP_CS5);
+ /* CS6: Release/Option register */
+ writel(0x81860001, IXP425_EXP_CS6);
+ /* CS7: LEDs */
+ writel(0x8093, IXP425_EXP_CS7);
+
+ return 0;
+}
+
+int board_init(void)
{
gd->bd->bi_arch_number = MACH_TYPE_ACTUX3;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x0100;
- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_ETHRST);
- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DSR);
- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DCD);
- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED5_GN);
- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED6_RT);
- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED6_GN);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED5_GN);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_RT);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_GN);
- GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
- GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_ETHRST);
+ GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
+ GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST);
- GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_DSR);
- GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_DCD);
+ GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR);
+ GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD);
- GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED5_GN);
- GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED6_RT);
- GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED6_GN);
+ GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED5_GN);
+ GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_RT);
+ GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_GN);
/*
* Setup GPIO's for Interrupt inputs
*/
- GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_DBGINT);
- GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_ETHINT);
+ GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT);
+ GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT);
/*
* Setup GPIO's for 33MHz clock output
*/
- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
- *IXP425_GPIO_GPCLKR = 0x011001FF;
-
- /* CS1: IPAC-X */
- *IXP425_EXP_CS1 = 0x94d10013;
- /* CS5: Debug port */
- *IXP425_EXP_CS5 = 0x9d520003;
- /* CS6: Release/Option register */
- *IXP425_EXP_CS6 = 0x81860001;
- /* CS7: LEDs */
- *IXP425_EXP_CS7 = 0x8093;
-
- udelay (533);
- GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
- GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_ETHRST);
-
- ACTUX3_LED1_RT (1);
- ACTUX3_LED1_GN (0);
- ACTUX3_LED2_RT (0);
- ACTUX3_LED2_GN (0);
- ACTUX3_LED3_RT (0);
- ACTUX3_LED3_GN (0);
- ACTUX3_LED4_GN (0);
- ACTUX3_LED5_RT (0);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
+ writel(0x011001FF, IXP425_GPIO_GPCLKR);
+
+ /* we need a minimum PCI reset pulse width after enabling the clock */
+ udelay(533);
+ GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
+ GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST);
+
+ ACTUX3_LED1_RT(1);
+ ACTUX3_LED1_GN(0);
+ ACTUX3_LED2_RT(0);
+ ACTUX3_LED2_GN(0);
+ ACTUX3_LED3_RT(0);
+ ACTUX3_LED3_GN(0);
+ ACTUX3_LED4_GN(0);
+ ACTUX3_LED5_RT(0);
return 0;
}
@@ -109,20 +113,20 @@ int board_init (void)
/*
* Check Board Identity
*/
-int checkboard (void)
+int checkboard(void)
{
- char *s = getenv ("serial#");
+ char *s = getenv("serial#");
- puts ("Board: AcTux-3 rev.");
- putc (ACTUX3_BOARDREL + 'A' - 1);
+ puts("Board: AcTux-3 rev.");
+ putc(ACTUX3_BOARDREL + 'A' - 1);
if (s != NULL) {
- puts (", serial# ");
- puts (s);
+ puts(", serial# ");
+ puts(s);
}
- putc ('\n');
+ putc('\n');
- return (0);
+ return 0;
}
/*
[U-Boot] [PATCH 17/17] run arm_pci_init after relocation
Signed-off-by: Michael Schwingen
---
arch/arm/lib/board.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index c620d2c..50e63c7 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -262,9 +262,6 @@ init_fnc_t *init_sequence[] = {
init_func_i2c,
#endif
dram_init, /* configure available RAM banks */
-#if defined(CONFIG_CMD_PCI) || defined (CONFIG_PCI)
- arm_pci_init,
-#endif
NULL,
};
@@ -529,6 +526,9 @@ void board_init_r (gd_t *id, ulong dest_addr)
/* initialize environment */
env_relocate ();
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+ arm_pci_init();
+#endif
#ifdef CONFIG_VFD
/* must do this after the framebuffer is allocated */
drv_vfd_init();
--
1.7.2.3
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[U-Boot] [PATCH 13/17] add dvlhost (dLAN 200 AV Wireless G) board
Signed-off-by: Michael Schwingen
---
MAINTAINERS|1 +
board/dvlhost/Makefile | 50 +
board/dvlhost/dvlhost.c| 130 +++
board/dvlhost/dvlhost_hw.h | 47 +
board/dvlhost/u-boot.lds | 86 +++
board/dvlhost/watchdog.c | 43
boards.cfg |1 +
include/configs/dvlhost.h | 248
8 files changed, 606 insertions(+), 0 deletions(-)
create mode 100644 board/dvlhost/Makefile
create mode 100644 board/dvlhost/dvlhost.c
create mode 100644 board/dvlhost/dvlhost_hw.h
create mode 100644 board/dvlhost/u-boot.lds
create mode 100644 board/dvlhost/watchdog.c
create mode 100644 include/configs/dvlhost.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 709c5d9..d30e18b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -810,6 +810,7 @@ Michael Schwingen
actux2 xscale/ixp
actux3 xscale/ixp
actux4 xscale/ixp
+ dvlhost xscale/ixp
Andrea Scian
diff --git a/board/dvlhost/Makefile b/board/dvlhost/Makefile
new file mode 100644
index 000..af9a644
--- /dev/null
+++ b/board/dvlhost/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS := dvlhost.o watchdog.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/dvlhost/dvlhost.c b/board/dvlhost/dvlhost.c
new file mode 100644
index 000..561e47f
--- /dev/null
+++ b/board/dvlhost/dvlhost.c
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2009
+ * Michael Schwingen, mich...@schwingen.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#ifdef CONFIG_PCI
+#include
+#include
+#endif
+
+#include "dvlhost_hw.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /* CS1: LED Latch */
+ writel(0xBFFF0002, IXP425_EXP_CS1);
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_DVLHOST;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0x0100;
+
+ /* Setup GPIOs used as output */
+ GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_WDGTRIGGER);
+ GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DLAN_PAIRING);
+ GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PCIRST);
+
+ /*
+* LED latch enable and watchdog enable are tied to the same GPIO,
+* so we need to trigger the watchdog if we want to enable the LEDs.
+ */
+#ifdef CONFIG_HW_WATCHDOG
+ GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_WDG_LED_EN);
+#else
+ GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_WDG_LED_EN);
+#endif
+
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_WDGTRIGGER);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DLAN_PAIRING);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_WDG
[U-Boot] [PATCH 01/17] add XScale sub architecture (IXP/PXA) to maintainer list
Signed-off-by: Michael Schwingen --- MAINTAINERS | 44 ++-- 1 files changed, 22 insertions(+), 22 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index b37ed0c..709c5d9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -559,8 +559,8 @@ Stefano Babic ea20davinci mx35pdk i.MX35 mx51evk i.MX51 - polaris xscale - trizepsiv xscale + polaris xscale/pxa + trizepsiv xscale/pxa vision2 i.MX51 Jason Liu @@ -592,7 +592,7 @@ Andreas Bie Cliff Brake - pxa255_idp xscale + pxa255_idp xscale/pxa Rick Bronson @@ -698,7 +698,7 @@ Sergey Kubushyn Prakash Kumar - cerf250 xscale + cerf250 xscale/pxa Vipin Kumar @@ -776,9 +776,9 @@ John Rigby Stefan Roese - ixdpg425xscale - pdnb3 xscale - scpuxscale + ixdpg425xscale/ixp + pdnb3 xscale/ixp + scpuxscale/ixp Alessandro Rubini Nomadik Linux Team @@ -801,15 +801,15 @@ Heiko Schocher Robert Schwebel - csb226 xscale - innokom xscale + csb226 xscale/pxa + innokom xscale/pxa Michael Schwingen - actux1 xscale - actux2 xscale - actux3 xscale - actux4 xscale + actux1 xscale/ixp + actux2 xscale/ixp + actux3 xscale/ixp + actux4 xscale/ixp Andrea Scian @@ -833,12 +833,12 @@ Greg Ungerer Marek Vasut - balloon3xscale - colibri_pxa270 xscale - palmld xscale - palmtc xscale - vpac270 xscale - zipitz2 xscale + balloon3xscale/pxa + colibri_pxa270 xscale/pxa + palmld xscale/pxa + palmtc xscale/pxa + vpac270 xscale/pxa + zipitz2 xscale/pxa efikamx i.MX51 Hugo Villeneuve @@ -880,9 +880,9 @@ Sughosh Ganu Unknown / orphaned boards: Board CPU Last known maintainer / Comment . - cradle xscale Kyle Harris / dead address - ixdp425 xscale Kyle Harris / dead address - lubbock xscale Kyle Harris / dead address + cradle xscale/pxa Kyle Harris / dead address + ixdp425 xscale/ixp Kyle Harris / dead address + lubbock xscale/pxa Kyle Harris / dead address imx31_phycore_eet i.MX31 Guennadi Liakhovetski / resigned mx31ads i.MX31 Guennadi Liakhovetski / resigned -- 1.7.2.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 15/17] update/fix PDNB3 board
Signed-off-by: Michael Schwingen
---
board/prodrive/pdnb3/config.mk |2 --
include/configs/pdnb3.h| 10 +++---
2 files changed, 7 insertions(+), 5 deletions(-)
delete mode 100644 board/prodrive/pdnb3/config.mk
diff --git a/board/prodrive/pdnb3/config.mk b/board/prodrive/pdnb3/config.mk
deleted file mode 100644
index 817541f..000
--- a/board/prodrive/pdnb3/config.mk
+++ /dev/null
@@ -1,2 +0,0 @@
-#
-CONFIG_SYS_TEXT_BASE = 0x01f0
diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h
index 33fa6ee..7fe9e5b 100644
--- a/include/configs/pdnb3.h
+++ b/include/configs/pdnb3.h
@@ -50,9 +50,6 @@
/*
* Misc configuration options
*/
-#define CONFIG_USE_IRQ 1 /* we need IRQ stuff for timer */
-#define CONFIG_TIMER_IRQ
-
#define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */
#define CONFIG_SYS_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram
*/
@@ -117,6 +114,7 @@
#define CONFIG_SYS_MEMTEST_END 0x0080 /* 4 ... 8 MB in DRAM
*/
#define CONFIG_SYS_LOAD_ADDR 0x0001 /* default load address
*/
+#define CONFIG_IXP425_TIMER_CLK
#define CONFIG_SYS_HZ 1000/* decrementer freq: 1
ms ticks */
/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
@@ -188,6 +186,7 @@
#define PHYS_SDRAM_10x /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x0200 /* 32 MB */
+#define CONFIG_SYS_TEXT_BASE 0x5000
#define CONFIG_SYS_FLASH_BASE 0x5000
#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_FLASH_BASE
#if defined(CONFIG_SCPU)
@@ -345,4 +344,9 @@
*/
#define CONFIG_SYS_CACHELINE_SIZE 32
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE 0x
+#define CONFIG_SYS_INIT_SP_ADDR\
+ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
#endif /* __CONFIG_H */
--
1.7.2.3
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[U-Boot] [PATCH 14/17] update/fix IXDP425 / IXDPG425 boards
Signed-off-by: Michael Schwingen
---
board/ixdp425/config.mk|2 -
board/ixdp425/flash.c | 427
board/ixdp425/ixdp425.c| 155 ++---
boards.cfg |2 +-
include/configs/ixdp425.h | 196 ++---
include/configs/ixdpg425.h |9 +-
6 files changed, 274 insertions(+), 517 deletions(-)
delete mode 100644 board/ixdp425/config.mk
delete mode 100644 board/ixdp425/flash.c
diff --git a/board/ixdp425/config.mk b/board/ixdp425/config.mk
deleted file mode 100644
index 509c894..000
--- a/board/ixdp425/config.mk
+++ /dev/null
@@ -1,2 +0,0 @@
-#
-CONFIG_SYS_TEXT_BASE = 0x00f8
diff --git a/board/ixdp425/flash.c b/board/ixdp425/flash.c
deleted file mode 100644
index f1d9190..000
--- a/board/ixdp425/flash.c
+++ /dev/null
@@ -1,427 +0,0 @@
-/*
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. khar...@nexus-tech.net
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include
-#include
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips
*/
-
-/* Board support for 1 or 2 flash devices */
-#undef FLASH_PORT_WIDTH32
-#define FLASH_PORT_WIDTH16
-
-#ifdef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH ushort
-#define FLASH_PORT_WIDTHV vu_short
-#define SWAP(x)x
-#else
-#define FLASH_PORT_WIDTH ulong
-#define FLASH_PORT_WIDTHV vu_long
-#define SWAP(x)__swab32(x)
-#endif
-
-#define FPWFLASH_PORT_WIDTH
-#define FPWV FLASH_PORT_WIDTHV
-
-#define mb() __asm__ __volatile__ ("" : : : "memory")
-
-/*---
- * Functions
- */
-static ulong flash_get_size (FPW * addr, flash_info_t * info);
-static int write_data (flash_info_t * info, ulong dest, FPW data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-void inline spin_wheel (void);
-
-/*---
- */
-
-unsigned long flash_init (void)
-{
- int i;
- ulong size = 0;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- switch (i) {
- case 0:
- flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
- flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
- break;
- default:
- panic ("configured too many flash banks!\n");
- break;
- }
- size += flash_info[i].size;
- }
-
- /* Protect monitor and environment sectors
-*/
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE + _bss_start - _armboot_start,
- &flash_info[0]);
-
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-
- return size;
-}
-
-/*---
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
- info->protect[i] = 0;
- }
- }
-}
-
-/*---
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL:
- printf ("INTEL ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
-
[U-Boot] [PATCH 08/17] update/fix AcTux1 board
Signed-off-by: Michael Schwingen
---
board/actux1/actux1.c| 111 --
board/actux1/config.mk |6 ---
board/actux1/u-boot.lds | 42 -
boards.cfg |5 ++-
include/configs/actux1.h | 63 +++---
5 files changed, 127 insertions(+), 100 deletions(-)
delete mode 100644 board/actux1/config.mk
diff --git a/board/actux1/actux1.c b/board/actux1/actux1.c
index e73aff8..8fb8065 100644
--- a/board/actux1/actux1.c
+++ b/board/actux1/actux1.c
@@ -37,49 +37,57 @@
#include
#include
#include
+#ifdef CONFIG_PCI
+#include
+#include
+#endif
#include "actux1_hw.h"
DECLARE_GLOBAL_DATA_PTR;
-int board_init (void)
+int board_early_init_f(void)
+{
+ /* CS5: Debug port */
+ writel(0x9d520003, IXP425_EXP_CS5);
+ /* CS6: HwRel */
+ writel(0x81860001, IXP425_EXP_CS6);
+ /* CS7: LEDs */
+ writel(0x8093, IXP425_EXP_CS7);
+ return 0;
+}
+
+int board_init(void)
{
gd->bd->bi_arch_number = MACH_TYPE_ACTUX1;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x0100;
- GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
+ GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
- /* Setup GPIO's for PCI INTA */
- GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI1_INTA);
- GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI1_INTA);
+ /* Setup GPIOs for PCI INTA */
+ GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI1_INTA);
+ GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI1_INTA);
- /* Setup GPIO's for 33MHz clock output */
- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
- *IXP425_GPIO_GPCLKR = 0x011001FF;
+ /* Setup GPIOs for 33MHz clock output */
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
+ writel(0x011001FF, IXP425_GPIO_GPCLKR);
- /* CS5: Debug port */
- *IXP425_EXP_CS5 = 0x9d520003;
- /* CS6: HwRel */
- *IXP425_EXP_CS6 = 0x81860001;
- /* CS7: LEDs */
- *IXP425_EXP_CS7 = 0x8093;
-
- udelay (533);
- GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
+ udelay(533);
+ GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
- ACTUX1_LED1 (2);
- ACTUX1_LED2 (2);
- ACTUX1_LED3 (0);
- ACTUX1_LED4 (0);
- ACTUX1_LED5 (0);
- ACTUX1_LED6 (0);
- ACTUX1_LED7 (0);
+ ACTUX1_LED1(2);
+ ACTUX1_LED2(2);
+ ACTUX1_LED3(0);
+ ACTUX1_LED4(0);
+ ACTUX1_LED5(0);
+ ACTUX1_LED6(0);
+ ACTUX1_LED7(0);
- ACTUX1_HS (ACTUX1_HS_DCD);
+ ACTUX1_HS(ACTUX1_HS_DCD);
return 0;
}
@@ -87,20 +95,20 @@ int board_init (void)
/*
* Check Board Identity
*/
-int checkboard (void)
+int checkboard(void)
{
- char *s = getenv ("serial#");
+ char *s = getenv("serial#");
- puts ("Board: AcTux-1 rev.");
- putc (ACTUX1_BOARDREL + 'A' - 1);
+ puts("Board: AcTux-1 rev.");
+ putc(ACTUX1_BOARDREL + 'A' - 1);
if (s != NULL) {
- puts (", serial# ");
- puts (s);
+ puts(", serial# ");
+ puts(s);
}
- putc ('\n');
+ putc('\n');
- return (0);
+ return 0;
}
/*
@@ -109,39 +117,36 @@ int checkboard (void)
* 1 = Rev. A
* 2 = Rev. B
*/
-u32 get_board_rev (void)
+u32 get_board_rev(void)
{
return ACTUX1_BOARDREL;
}
-int dram_init (void)
+int dram_init(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return (0);
+ gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
+ return 0;
}
-#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
-extern struct pci_controller hose;
-extern void pci_ixp_init (struct pci_controller *hose);
-void pci_init_board (void)
+#ifdef CONFIG_PCI
+struct pci_controller hose;
+
+void pci_init_board(void)
{
- extern void pci_ixp_init (struct pci_controller *hose);
- pci_ixp_init (&hose);
+ pci_ixp_init(&hose);
}
#endif
-void reset_phy (void)
+void reset_phy(void)
{
u16 id1, id2;
/* initialize the PHY */
- miiphy_reset ("NPE0", CONFIG_PHY_ADDR);
+ miiphy_reset("NPE0", CONFIG_PHY_ADDR);
- miiphy_read ("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1);
- miiphy_read ("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2);
+ miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1);
+ miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2);
id2 &= 0xFFF0; /* mask out revision bits */
@@ -152,9 +157,9 @@ void reset_ph
[U-Boot] [PATCH 07/17] use -ffunction-sections / --gc-sections on IXP42x
Signed-off-by: Michael Schwingen
---
arch/arm/cpu/ixp/config.mk |5 +
arch/arm/cpu/ixp/u-boot.lds |8
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/ixp/config.mk b/arch/arm/cpu/ixp/config.mk
index deca3f4..5868cba 100644
--- a/arch/arm/cpu/ixp/config.mk
+++ b/arch/arm/cpu/ixp/config.mk
@@ -27,6 +27,11 @@ BIG_ENDIAN = y
PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float -mbig-endian
PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100
+
+# -fdata-sections triggers "section .bss overlaps section .rel.dyn" linker
error
+PLATFORM_RELFLAGS += -ffunction-sections
+LDFLAGS_u-boot += --gc-sections
+
# =
#
# Supply options according to compiler version
diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds
index a55eb8a..747a7b6 100644
--- a/arch/arm/cpu/ixp/u-boot.lds
+++ b/arch/arm/cpu/ixp/u-boot.lds
@@ -31,8 +31,8 @@ SECTIONS
. = ALIGN(4);
.text :
{
- arch/arm/cpu/ixp/start.o(.text)
- *(.text)
+ arch/arm/cpu/ixp/start.o(.text*)
+ *(.text*)
}
. = ALIGN(4);
@@ -40,7 +40,7 @@ SECTIONS
. = ALIGN(4);
.data : {
- *(.data)
+ *(.data*)
}
. = ALIGN(4);
@@ -65,7 +65,7 @@ SECTIONS
.bss __rel_dyn_start (OVERLAY) : {
__bss_start = .;
- *(.bss)
+ *(.bss*)
. = ALIGN(4);
_end = .;
}
--
1.7.2.3
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[U-Boot] [PATCH 06/17] support CONFIG_SYS_LDSCRIPT on ARM
Signed-off-by: Michael Schwingen --- arch/arm/config.mk |6 ++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/arch/arm/config.mk b/arch/arm/config.mk index a6a4742..a7c4d27 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -63,7 +63,13 @@ ifeq (,$(findstring arch/arm/lib/eabi_compat.o,$(PLATFORM_LIBS))) PLATFORM_LIBS += $(OBJTREE)/arch/arm/lib/eabi_compat.o endif endif + +ifdef CONFIG_SYS_LDSCRIPT +# need to strip off double quotes +LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT)) +else LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds +endif # needed for relocation ifndef CONFIG_NAND_SPL -- 1.7.2.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 04/17] Fix IXP code to work after relocation was added
- jump to real flash location after reset before turning off flash mirror
- fix timer system to use HZ == 1000, remove broken interrupt-based code
Signed-off-by: Michael Schwingen
---
arch/arm/cpu/ixp/cpu.c |5 --
arch/arm/cpu/ixp/start.S | 59 ++--
arch/arm/cpu/ixp/timer.c | 124 +++-
arch/arm/include/asm/arch-ixp/ixp425.h |5 +-
arch/arm/include/asm/global_data.h |3 +
5 files changed, 68 insertions(+), 128 deletions(-)
diff --git a/arch/arm/cpu/ixp/cpu.c b/arch/arm/cpu/ixp/cpu.c
index ce275e5..942845d 100644
--- a/arch/arm/cpu/ixp/cpu.c
+++ b/arch/arm/cpu/ixp/cpu.c
@@ -36,8 +36,6 @@
#include
#include
-ulong loops_per_jiffy;
-
static void cache_flush(void);
#if defined(CONFIG_DISPLAY_CPUINFO)
@@ -51,17 +49,14 @@ int print_cpuinfo (void)
puts("CPU: Intel IXP425 at ");
switch ((id & 0x03f0) >> 4) {
case 0x1c:
- loops_per_jiffy = 887467;
speed = 533;
break;
case 0x1d:
- loops_per_jiffy = 666016;
speed = 400;
break;
case 0x1f:
- loops_per_jiffy = 442901;
speed = 266;
break;
}
diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S
index f71a398..844aebf 100644
--- a/arch/arm/cpu/ixp/start.S
+++ b/arch/arm/cpu/ixp/start.S
@@ -65,7 +65,8 @@
.endm
.globl _start
-_start: b reset
+_start:
+ ldr pc, _reset
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
@@ -74,6 +75,7 @@ _start: b reset
ldr pc, _irq
ldr pc, _fiq
+_reset: .word reset
_undefined_instruction: .word undefined_instruction
_software_interrupt: .word software_interrupt
_prefetch_abort: .word prefetch_abort
@@ -163,12 +165,6 @@ reset:
str r1, [r2]
/* make sure flash is visible at 0 */
-#if 0
- ldr r2, =IXP425_EXP_CFG0
- ldr r1, [r2]
- orr r1, r1, #0x8000
- str r1, [r2]
-#endif
mov r1, #CONFIG_SYS_SDR_CONFIG
ldr r2, =IXP425_SDR_CONFIG
str r1, [r2]
@@ -212,19 +208,6 @@ reset:
str r1, [r4]
DELAY_FOR 0x4000, r0
- /* copy */
- mov r0, #0
- mov r4, r0
- add r2, r0, #CONFIG_SYS_MONITOR_LEN
- mov r1, #0x1000
- mov r5, r1
-
-30:
- ldr r3, [r0], #4
- str r3, [r1], #4
- cmp r0, r2
- bne 30b
-
/* invalidate I & D caches & BTB */
mcr p15, 0, r0, c7, c7, 0
CPWAIT r0
@@ -237,19 +220,12 @@ reset:
mcr p15, 0, r0, c7, c10, 4
CPWAIT r0
- /* move flash to 0x5000 */
+ /* remove flash mirror at 0x */
ldr r2, =IXP425_EXP_CFG0
ldr r1, [r2]
bic r1, r1, #0x8000
str r1, [r2]
- nop
- nop
- nop
- nop
- nop
- nop
-
/* invalidate I & Data TLB */
mcr p15, 0, r0, c8, c7, 0
CPWAIT r0
@@ -265,7 +241,7 @@ reset:
orr r0,r0,#0x13
msr cpsr,r0
-/* Set stackpointer in internal RAM to call board_init_f */
+/* Set initial stackpointer in SDRAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
@@ -576,28 +552,3 @@ reset_endless:
b reset_endless
-#ifdef CONFIG_USE_IRQ
-
-.LC0: .word loops_per_jiffy
-
-/*
- * 0 <= r0 <= 2000
- */
-.globl __udelay
-__udelay:
- mov r2, #0x6800
- orr r2, r2, #0x00db
- mul r0, r2, r0
- ldr r2, .LC0
- ldr r2, [r2]@ max = 0x0fff
- mov r0, r0, lsr #11 @ max = 0x3fff
- mov r2, r2, lsr #11 @ max = 0x0003
- mul r0, r2, r0 @ max = 2^32-1
- movsr0, r0, lsr #6
-
-delay_loop:
- subsr0, r0, #1
- bne delay_loop
- mov pc, lr
-
-#endif /* CONFIG_USE_IRQ */
diff --git a/arch/arm/cpu/ixp/timer.c b/arch/arm/cpu/ixp/timer.c
index edf341f..7a44a08 100644
--- a/arch/arm/cpu/ixp/timer.c
+++ b/arch/arm/cpu/ixp/timer.c
@@ -1,4 +1,7 @@
/*
+ * (C) Copyright 2010
+ * Michael Schwingen, mich...@schwingen.org
+ *
* (C) Copyright 2006
* Stefan Roese, DENX Software Engineering, s...@denx.de.
*
@@ -31,105 +34,94 @@
#include
#include
+#include
+#include
-#ifdef CONFIG_TIMER_IRQ
-
-#define FREQ
-#define CLOCK_TICK_RATE(((FREQ / CONFIG_SYS_HZ &
~IXP425_OST_RELOAD_MASK) + 1) * CONFIG_SYS_HZ)
-#define LATCH ((CLOCK_TICK_RATE + CONFIG_SYS_HZ/2) / CONFIG_SYS_HZ)
/* For divider */
+DECLARE_GLOBAL_DATA_PTR;
/*
- * When interrupts
[U-Boot] [PATCH 12/17] IXP NPE: add support for fixed-speed MII ports
Signed-off-by: Michael Schwingen
---
arch/arm/cpu/ixp/npe/npe.c | 67 +++
1 files changed, 42 insertions(+), 25 deletions(-)
diff --git a/arch/arm/cpu/ixp/npe/npe.c b/arch/arm/cpu/ixp/npe/npe.c
index 6d92c53..f0e02bf 100644
--- a/arch/arm/cpu/ixp/npe/npe.c
+++ b/arch/arm/cpu/ixp/npe/npe.c
@@ -359,36 +359,53 @@ static int npe_init(struct eth_device *dev, bd_t * bis)
debug("%s: 1\n", __FUNCTION__);
- miiphy_read (dev->name, p_npe->phy_no, MII_BMSR, ®_short);
-
- /*
-* Wait if PHY is capable of autonegotiation and autonegotiation is not
complete
-*/
- if ((reg_short & BMSR_ANEGCAPABLE) && !(reg_short & BMSR_ANEGCOMPLETE))
{
- puts ("Waiting for PHY auto negotiation to complete");
- i = 0;
- while (!(reg_short & BMSR_ANEGCOMPLETE)) {
- /*
-* Timeout reached ?
-*/
- if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
- puts (" TIMEOUT !\n");
- break;
- }
+#ifdef CONFIG_MII_NPE0_FIXEDLINK
+ if (0 == p_npe->eth_id) {
+ speed = CONFIG_MII_NPE0_SPEED;
+ duplex = CONFIG_MII_NPE0_FULLDUPLEX ? FULL : HALF;
+ } else
+#endif
+#ifdef CONFIG_MII_NPE1_FIXEDLINK
+ if (1 == p_npe->eth_id) {
+ speed = CONFIG_MII_NPE1_SPEED;
+ duplex = CONFIG_MII_NPE1_FULLDUPLEX ? FULL : HALF;
+ } else
+#endif
+ {
+ miiphy_read(dev->name, p_npe->phy_no, MII_BMSR, ®_short);
+
+ /*
+* Wait if PHY is capable of autonegotiation and
+* autonegotiation is not complete
+*/
+ if ((reg_short & BMSR_ANEGCAPABLE) &&
+ !(reg_short & BMSR_ANEGCOMPLETE)) {
+ puts("Waiting for PHY auto negotiation to complete");
+ i = 0;
+ while (!(reg_short & BMSR_ANEGCOMPLETE)) {
+ /*
+* Timeout reached ?
+*/
+ if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
+ puts(" TIMEOUT !\n");
+ break;
+ }
- if ((i++ % 1000) == 0) {
- putc ('.');
- miiphy_read (dev->name, p_npe->phy_no,
MII_BMSR, ®_short);
+ if ((i++ % 1000) == 0) {
+ putc('.');
+ miiphy_read(dev->name, p_npe->phy_no,
+MII_BMSR, ®_short);
+ }
+ udelay(1000); /* 1 ms */
}
- udelay (1000); /* 1 ms */
+ puts(" done\n");
+ /* another 500 ms (results in faster booting) */
+ udelay(50);
}
- puts (" done\n");
- udelay (50);/* another 500 ms (results in faster
booting) */
+ speed = miiphy_speed(dev->name, p_npe->phy_no);
+ duplex = miiphy_duplex(dev->name, p_npe->phy_no);
}
- speed = miiphy_speed (dev->name, p_npe->phy_no);
- duplex = miiphy_duplex (dev->name, p_npe->phy_no);
-
if (p_npe->print_speed) {
p_npe->print_speed = 0;
printf ("ENET Speed is %d Mbps - %s duplex connection\n",
--
1.7.2.3
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[U-Boot] [PATCH 09/17] update/fix AcTux2 board
Signed-off-by: Michael Schwingen
---
board/actux2/actux2.c| 99 +++--
board/actux2/config.mk |6 ---
board/actux2/u-boot.lds | 47 +
include/configs/actux2.h | 36 +++--
4 files changed, 103 insertions(+), 85 deletions(-)
delete mode 100644 board/actux2/config.mk
diff --git a/board/actux2/actux2.c b/board/actux2/actux2.c
index d6aaad6..400388c 100644
--- a/board/actux2/actux2.c
+++ b/board/actux2/actux2.c
@@ -43,50 +43,55 @@
DECLARE_GLOBAL_DATA_PTR;
-int board_init (void)
+int board_early_init_f(void)
+{
+ /* CS1: IPAC-X */
+ writel(0x94d10013, IXP425_EXP_CS1);
+ /* CS5: Debug port */
+ writel(0x9d520003, IXP425_EXP_CS5);
+ /* CS6: HW release register */
+ writel(0x81860001, IXP425_EXP_CS6);
+ /* CS7: LEDs */
+ writel(0x8093, IXP425_EXP_CS7);
+
+ return 0;
+}
+
+int board_init(void)
{
gd->bd->bi_arch_number = MACH_TYPE_ACTUX2;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x0100;
- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_ETHRST);
- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DSR);
- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DCD);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD);
- GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
- GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_ETHRST);
+ GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
+ GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST);
- GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_DSR);
- GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_DCD);
+ GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR);
+ GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD);
- /* Setup GPIO's for Interrupt inputs */
- GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_DBGINT);
- GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_ETHINT);
+ /* Setup GPIOs for Interrupt inputs */
+ GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT);
+ GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT);
- /* Setup GPIO's for 33MHz clock output */
- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
- *IXP425_GPIO_GPCLKR = 0x011001FF;
+ /* Setup GPIOs for 33MHz clock output */
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
+ writel(0x011001FF, IXP425_GPIO_GPCLKR);
- /* CS1: IPAC-X */
- *IXP425_EXP_CS1 = 0x94d10013;
- /* CS5: Debug port */
- *IXP425_EXP_CS5 = 0x9d520003;
- /* CS6: HW release register */
- *IXP425_EXP_CS6 = 0x81860001;
- /* CS7: LEDs */
- *IXP425_EXP_CS7 = 0x8093;
+ udelay(533);
+ GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
+ GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST);
- udelay (533);
- GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
- GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_ETHRST);
-
- ACTUX2_LED1 (1);
- ACTUX2_LED2 (0);
- ACTUX2_LED3 (0);
- ACTUX2_LED4 (0);
+ ACTUX2_LED1(1);
+ ACTUX2_LED2(0);
+ ACTUX2_LED3(0);
+ ACTUX2_LED4(0);
return 0;
}
@@ -94,28 +99,26 @@ int board_init (void)
/*
* Check Board Identity
*/
-int checkboard (void)
+int checkboard(void)
{
- char *s = getenv ("serial#");
+ char *s = getenv("serial#");
- puts ("Board: AcTux-2 rev.");
- putc (ACTUX2_BOARDREL + 'A' - 1);
+ puts("Board: AcTux-2 rev.");
+ putc(ACTUX2_BOARDREL + 'A' - 1);
if (s != NULL) {
- puts (", serial# ");
- puts (s);
+ puts(", serial# ");
+ puts(s);
}
- putc ('\n');
+ putc('\n');
- return (0);
+ return 0;
}
-int dram_init (void)
+int dram_init(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return (0);
+ gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
+ return 0;
}
/*
@@ -124,13 +127,13 @@ int dram_init (void)
* 1 = Rev. A
* 2 = Rev. B
*/
-u32 get_board_rev (void)
+u32 get_board_rev(void)
{
return ACTUX2_BOARDREL;
}
-void reset_phy (void)
+void reset_phy(void)
{
/* init IcPlus IP175C ethernet switch to native IP175C mode */
- miiphy_write ("NPE0", 29, 31, 0x175C);
+ miiphy_write("NPE0", 29, 31, 0x175C);
}
diff --git a/board/actux2/config.mk b/board/actux2/config.mk
deleted file mode 100644
index 88634f7..000
--- a/board/actux2/config.mk
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0x00e0
-
-# include NPE ethernet driver
-BOARDLI
[U-Boot] [PATCH 05/17] fix "depend" target in npe directory
Signed-off-by: Michael Schwingen --- arch/arm/cpu/ixp/npe/Makefile |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/ixp/npe/Makefile b/arch/arm/cpu/ixp/npe/Makefile index c756a1d..14ab3c7 100644 --- a/arch/arm/cpu/ixp/npe/Makefile +++ b/arch/arm/cpu/ixp/npe/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libnpe.o LOCAL_CFLAGS += -I$(TOPDIR)/arch/arm/cpu/ixp/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB -D__linux CFLAGS += $(LOCAL_CFLAGS) +CPPFLAGS += $(LOCAL_CFLAGS) # needed for depend HOSTCFLAGS += $(LOCAL_CFLAGS) COBJS-$(CONFIG_IXP4XX_NPE) := npe.o \ -- 1.7.2.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 11/17] update/fix AcTux4 board
Signed-off-by: Michael Schwingen
---
board/actux4/actux4.c| 103 ++---
board/actux4/config.mk |4 --
include/configs/actux4.h | 40 --
3 files changed, 86 insertions(+), 61 deletions(-)
delete mode 100644 board/actux4/config.mk
diff --git a/board/actux4/actux4.c b/board/actux4/actux4.c
index f373b58..d20d881 100644
--- a/board/actux4/actux4.c
+++ b/board/actux4/actux4.c
@@ -35,92 +35,107 @@
#include
#include
#include
-
+#include
#include
+#ifdef CONFIG_PCI
+#include
+#include
+#endif
#include "actux4_hw.h"
DECLARE_GLOBAL_DATA_PTR;
-int board_init (void)
+int board_early_init_f(void)
+{
+ writel(0xbd113c42, IXP425_EXP_CS1);
+ return 0;
+}
+
+int board_init(void)
{
gd->bd->bi_arch_number = MACH_TYPE_ACTUX4;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x0100;
- GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_nPWRON);
- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_nPWRON);
+ GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_nPWRON);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_nPWRON);
- GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
+ GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
/* led not populated on board*/
- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED3);
- GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED3);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED3);
+ GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED3);
/* middle LED */
- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED2);
- GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED2);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED2);
+ GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED2);
/* right LED */
/* weak pulldown = LED weak on */
- GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_LED1);
- GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED1);
+ GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_LED1);
+ GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED1);
/* Setup GPIO's for Interrupt inputs */
- GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTA);
- GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTB);
- GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTC);
- GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_RTCINT);
- GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI_INTA);
- GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI_INTB);
-
- GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTA);
- GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTB);
- GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTC);
- GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_RTCINT);
- GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI_INTA);
- GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI_INTB);
+ GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTA);
+ GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTB);
+ GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTC);
+ GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RTCINT);
+ GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA);
+ GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB);
+
+ GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTA);
+ GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTB);
+ GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTC);
+ GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RTCINT);
+ GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA);
+ GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB);
/* Setup GPIO's for 33MHz clock output */
- *IXP425_GPIO_GPCLKR = 0x011001FF;
- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
-
- *IXP425_EXP_CS1 = 0xbd113c42;
+ writel(0x011001FF, IXP425_GPIO_GPCLKR);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
- udelay (1);
- GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
- udelay (1);
- GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
- udelay (1);
- GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
+ udelay(1);
+ GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
+ udelay(1);
+ GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
+ udelay(1);
+ GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
return 0;
}
/* Check Board Identity */
-int checkboard (void)
+int checkboard(void)
{
- puts ("Board: AcTux-4\n");
- return (0);
+ puts("Board: AcTux-4\n");
+ return 0;
}
-int dram_init (void)
+int dram_init(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
+ return 0;
+}
- return (0);
+#ifdef CONFIG_PCI
+struct pci_controller hose;
+
+void pci_init_board(void)
+{
+ pci_ixp_init(&hose);
}
+#endif
/*
* Hardcoded flash setup:
* Flash 0 is a non-CFI SST 39VF020 flash, 8 bit flash / 8 bit bus.
* Flash 1 is an Intel *16
[U-Boot] [PATCH 02/17] add support for IXP42x Rev. B1 and newer
Signed-off-by: Michael Schwingen
---
arch/arm/cpu/ixp/npe/npe.c |7 +--
1 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/ixp/npe/npe.c b/arch/arm/cpu/ixp/npe/npe.c
index 857bcad..6d92c53 100644
--- a/arch/arm/cpu/ixp/npe/npe.c
+++ b/arch/arm/cpu/ixp/npe/npe.c
@@ -621,9 +621,12 @@ int npe_initialize(bd_t * bis)
if (ixFeatureCtrlDeviceRead() ==
IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X) {
switch (ixFeatureCtrlProductIdRead() &
IX_FEATURE_CTRL_SILICON_STEPPING_MASK) {
case IX_FEATURE_CTRL_SILICON_TYPE_B0:
+ default: /* newer than B0 */
/*
-* If it is B0 Silicon, we only enable
port when its corresponding
-* Eth Coprocessor is available.
+* If it is B0 or newer Silicon, we
+* only enable port when its
+* corresponding Eth Coprocessor is
+* available.
*/
if
(ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
IX_FEATURE_CTRL_COMPONENT_ENABLED)
--
1.7.2.3
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[U-Boot] IXP42x patch series version 3
Hi, here is the third incarnation of the IXP patch series. I hope I addressed all the comments from version 2: - timer system now uses no BSS-based variables - use I/O accessors - remove config.mk from board directories - set -ffunction-sections/--gc-sections globally (for IXP architecture) Furthermore, I got a stab at the IXDP425 board, which resulted in a overhaul of the IXP42x PCI code. That patch was not part of the previous series, so if this causes concern, it should cause no problems to leave out the PCI patch for this release and handle it later. The patch removes big hunks of IXP42x-private code, and uses the general PCI infrastructure in u-boot instead. As a side-product, this gets rid of some IXP42x switches in global headers. My own boards plus IXDP425 are tested here. I can't test IXDGP425 and PDNB3. [PATCH 01/17] add XScale sub architecture (IXP/PXA) to maintainer list [PATCH 02/17] add support for IXP42x Rev. B1 and newer [PATCH 03/17] trigger hardware watchdog in IXP42x serial driver [PATCH 04/17] Fix IXP code to work after relocation was added [PATCH 05/17] fix "depend" target in npe directory [PATCH 06/17] support CONFIG_SYS_LDSCRIPT on ARM [PATCH 07/17] use -ffunction-sections / --gc-sections on IXP42x [PATCH 08/17] update/fix AcTux1 board [PATCH 09/17] update/fix AcTux2 board [PATCH 10/17] update/fix AcTux3 board [PATCH 11/17] update/fix AcTux4 board [PATCH 12/17] IXP NPE: add support for fixed-speed MII ports [PATCH 13/17] add dvlhost (dLAN 200 AV Wireless G) board [PATCH 14/17] update/fix IXDP425 / IXDPG425 boards [PATCH 15/17] update/fix PDNB3 board [PATCH 16/17] IXP42x PCI rewrite [PATCH 17/17] run arm_pci_init after relocation cu Michael ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 03/17] trigger hardware watchdog in IXP42x serial driver
Signed-off-by: Michael Schwingen
---
drivers/serial/serial_ixp.c |7 +--
1 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/serial/serial_ixp.c b/drivers/serial/serial_ixp.c
index dd26af4..a9acd47 100644
--- a/drivers/serial/serial_ixp.c
+++ b/drivers/serial/serial_ixp.c
@@ -30,6 +30,7 @@
#include
#include
+#include
/*
* 14.7456 MHz
@@ -85,7 +86,8 @@ int serial_init (void)
void serial_putc (const char c)
{
/* wait for room in the tx FIFO on UART */
- while ((LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_TEMT) == 0);
+ while ((LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_TEMT) == 0)
+ WATCHDOG_RESET(); /* Reset HW Watchdog, if needed */
THR(CONFIG_SYS_IXP425_CONSOLE) = c;
@@ -111,7 +113,8 @@ int serial_tstc (void)
*/
int serial_getc (void)
{
- while (!(LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR));
+ while (!(LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR))
+ WATCHDOG_RESET(); /* Reset HW Watchdog, if needed */
return (char) RBR(CONFIG_SYS_IXP425_CONSOLE) & 0xff;
}
--
1.7.2.3
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***SEND YOUR DETAILS TO OUR PROCESSING UNIT TO GET FULL INFO Lu c ky# : 12-12-23-35-40-41(12) Tic k et# : 00869575733664 CG PN : 7-22-71-00-66-12 Amount Won: £ 850,000 UK Pounds. For full information send your contact: VERIFICATION / PROCESSING UNIT :giveawayinfoservic...@gmail.com :claimsgooglegivea...@bigmir.net Congratulations!! Mr. José Eduardo Monteiro (PROMO ANNOUNCER) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Introduce a new linker flag LDFLAGS_FINAL
On 02/02/11 06:51, Scott Wood wrote: > On Tue, 1 Feb 2011 20:32:29 +0100 > Wolfgang Denk wrote: > >> Dear Scott Wood, >> >> In message <20110201102446.23b4a...@udp111988uds.am.freescale.net> you wrote: >>> >>> Prior to the introduction of LDFLAGS_u-boot, was LDFLAGS not what was >>> used? So before, anything that board/cpu code adds directly to LDFLAGS >>> (maybe they're supposed to use PLATFORM_LDFLAGS, but not all do) was >>> used in the final link. After 8aba9dc, only things in >>> PLATFORM_LDFLAGS plus -Bstatic and -T are used in the final link. >> >> And this is correct for all boards? > > By "this" do you mean the switch to PLATFORM_LDFLAGS in 8aba9dc, or the > switch back to LDFLAGS? It's not obvious to me that the dropping of > board/cpu modifications to LDFLAGS except during partial link was an > intentional change, or a correct one for all boards. > > The only case I see where it makes any difference at all is arch/i386, > which does LDFLAGS += --cref. From the description of --cref in the > linker manual, it probably actually belongs in LDFLAGS_FINAL, though > I'm not sure if it's harmless to include it in partial link or not. > Currently, with 8aba9dc, it's included *only* in partial link. > > It's also not clear to me what this option has to do with i386... it > looks like an arch-neutral debugging feature that doesn't affect the > actual u-boot image at all (the output goes into the map file). --cref can be dropped from x86 - I really should send a patch to rename i386 to x86 ;) Since x86 is currently a very simple platform to maintain (one CPU, one board) and I have been dealing with breakages do to non x86 cleanups for a while, I have no problem with tweaking the x86 linker options to be more arch neutral. Regards, Graeme ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 02/32] x86: Align config.mk and linker scripts with other arches
On 05/02/11 07:42, Scott Wood wrote: > On Fri, 4 Feb 2011 23:35:29 +1100 > Graeme Russ wrote: > >> LDFLAGS += --cref >> -LDFLAGS_u-boot += --gc-sections >> -PLATFORM_RELFLAGS += -ffunction-sections >> +LDFLAGS_u-boot += --gc-sections -pie >> +LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds > > The use of --cref came up recently (see > http://lists.denx.de/pipermail/u-boot/2011-February/086698.html). > > During what link phase is --cref supposed to be used? Currently it is being > used during partial links only, and not the final link, as a result of > commit 8aba9dceebb14144e07d19593111ee3a999c37fc. As the toplevel > config.mk currently stands, it would have to go in PLATFORM_LDFLAGS to > be used in all link phases, or LDFLAGS_u-boot to be used when linking > the final image only. > > BTW, is it really enabled because of something to do with i386? Or just > maintainer preference (in which case it should probably be a non-arch config, > or in this case just enabled unconditionally, since I don't think there's > any harm to it). I think --cref is historical. I have just performed a build without it and it runs fine, so I think it can be safely removed. Maybe it might be worth starting a separate discussion thread with the goal of unifying and documenting the linker, make and config.mk files? Regards, Graeme ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/8xxx: Display DIMM model
Beside displaying RDIMM or UDIMM, this patch adds display of the model numbers
embedded in SPD.
Signed-off-by: York Sun
---
.../cpu/mpc8xxx/ddr/lc_common_dimm_params.c| 11 +++
1 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
index a58e5a9..684b2f4 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
@@ -207,10 +207,15 @@ compute_lowest_common_dimm_parameters(const dimm_params_t
*dimm_params,
temp1 = temp2 = 0;
for (i = 0; i < number_of_dimms; i++) {
if (dimm_params[i].n_ranks) {
- if (dimm_params[i].registered_dimm)
+ if (dimm_params[i].registered_dimm) {
temp1 = 1;
- if (!dimm_params[i].registered_dimm)
+ printf("Detected RDIMM %s\n",
+ dimm_params[i].mpart);
+ } else {
temp2 = 1;
+ printf("Detected UDIMM %s\n",
+ dimm_params[i].mpart);
+ }
}
}
@@ -218,10 +223,8 @@ compute_lowest_common_dimm_parameters(const dimm_params_t
*dimm_params,
outpdimm->all_DIMMs_unbuffered = 0;
if (temp1 && !temp2) {
outpdimm->all_DIMMs_registered = 1;
- printf("Detected RDIMM(s)\n");
} else if (!temp1 && temp2) {
outpdimm->all_DIMMs_unbuffered = 1;
- printf("Detected UDIMM(s)\n");
} else {
printf("ERROR: Mix of registered buffered and unbuffered "
"DIMMs detected!\n");
--
1.7.0.4
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[U-Boot] [PATCH] powerpc/85xx: Update fixed DDR3 timing table for P4080DS
Most of time U-boot doesn't get an exact clock number. For example, clock
900MHz may be detected as 899.99MHz. 800MHz could be 799.99MHz. Update the
table to align the desired clocks in the middle.
Signed-off-by: York Sun
---
board/freescale/corenet_ds/p4080ds_ddr.c | 16
1 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/board/freescale/corenet_ds/p4080ds_ddr.c
b/board/freescale/corenet_ds/p4080ds_ddr.c
index ccb9da8..844e1d7 100644
--- a/board/freescale/corenet_ds/p4080ds_ddr.c
+++ b/board/freescale/corenet_ds/p4080ds_ddr.c
@@ -334,17 +334,17 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = {
};
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
- {800, 900, &ddr_cfg_regs_800},
- {900, 1000, &ddr_cfg_regs_900},
- {1000, 1200, &ddr_cfg_regs_1000},
- {1200, 1300, &ddr_cfg_regs_1200},
+ {750, 850, &ddr_cfg_regs_800},
+ {850, 950, &ddr_cfg_regs_900},
+ {950, 1050, &ddr_cfg_regs_1000},
+ {1050, 1250, &ddr_cfg_regs_1200},
{0, 0, NULL}
};
fixed_ddr_parm_t fixed_ddr_parm_1[] = {
- {800, 900, &ddr_cfg_regs_800_2nd},
- {900, 1000, &ddr_cfg_regs_900_2nd},
- {1000, 1200, &ddr_cfg_regs_1000_2nd},
- {1200, 1300, &ddr_cfg_regs_1200_2nd},
+ {750, 850, &ddr_cfg_regs_800_2nd},
+ {850, 950, &ddr_cfg_regs_900_2nd},
+ {950, 1050, &ddr_cfg_regs_1000_2nd},
+ {1050, 1250, &ddr_cfg_regs_1200_2nd},
{0, 0, NULL}
};
--
1.7.0.4
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Re: [U-Boot] [U-BOOT] [PATCH] env: reduce the stack footprint for the env buf
Dear Lei Wen, In message <1296788903-7604-1-git-send-email-lei...@marvell.com> you wrote: > Original env buf directly locate at stack lead large stack footprint > when call those env functions. It is not good when the system memory > is critical or only want the uboot run at restrict range, that is not > to touch the memory of other place at its best. > > So now this patch move the env buf to the heap area, which reduce the > area uboot need to touch. In which way do you think this will save any memory? Your switch from automatic variables to manually allocated ones has, in my opinion several disadvantages: 1) It increases the code size. 2) It increases the probability of bugs like memory leaks etc. 3) Instead of using the stack, which gets allocated fully dynamically and gets freed guaranteed completely when the function returns, you now need at least the same space in the malloc arena - where you have to allocate it statically, and where allocations of buffers like that can easily lead to memory fragmentation, increasing the memory footprint further. Did you do any specific measurements of memory footprint, or what makes you believe your code is preferrable? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de As far as the laws of mathematics refer to reality, they are not cer- tain, and as far as they are certain, they do not refer to reality. -- Albert Einstein ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] powerpc/8xxx: Fix LAW init to respect pre-initialized entries
If some pre-boot or earlier stage bootloader (NAND SPL) has setup LAW
entries consider them good and mark them used.
In the NAND SPL case we skip re-initializing based on the law_table
since the SPL phase already did that.
Signed-off-by: Kumar Gala
---
* Fix problem in non-NAND case we didn't set the law_table
drivers/misc/fsl_law.c | 20
1 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c
index 63c08bf..e440d29 100644
--- a/drivers/misc/fsl_law.c
+++ b/drivers/misc/fsl_law.c
@@ -24,6 +24,7 @@
*/
#include
+#include
#include
#include
@@ -246,6 +247,25 @@ void init_laws(void)
#error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes
#endif
+ /*
+* Any LAWs that were set up before we booted assume they are meant to
+* be around and mark them used.
+*/
+ for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
+ u32 lawar = in_be32(LAWAR_ADDR(i));
+
+ if (lawar & LAW_EN)
+ gd->used_laws |= (1 << i);
+ }
+
+#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+ /*
+* in NAND boot we've already parsed the law_table and setup those LAWs
+* so don't do it again.
+*/
+ return;
+#endif
+
for (i = 0; i < num_law_entries; i++) {
if (law_table[i].index == -1)
set_next_law(law_table[i].addr, law_table[i].size,
--
1.7.2.3
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[U-Boot] [GIT PULL] lease pull u-boot-mpc85xx.git
Some bug fix and errata fixes. - k The following changes since commit 42d44f631c4e8e5359775bdc098f2fffde4e5c05: Prepare v2011.03-rc1 (2011-02-02 22:37:32 +0100) are available in the git repository at: git://git.denx.de/u-boot-mpc85xx.git master Kumar Gala (3): powerpc/85xx: Enable ESDHC111 Erratum on P2010/P2020 SoCs fsl_esdhc: Add the workaround for erratum ESDHC-A001 (enable on P2020) powerpc/8xxx: Fix possible compile issue related to P1013 York Sun (5): powerpc/85xx: Remove unnecessary polling loop from DDR init powerpc/85xx: Enable Errata command on MPC8572DS powerpc/85xx: Rename MPC8572 DDR erratum to DDR115 powerpc/mpc85xx: implement workaround for errata DDR111 and DDR134 powerpc/85xx: Enable ECC on MPC8572DS arch/powerpc/cpu/mpc85xx/Makefile |2 +- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 11 +++- arch/powerpc/cpu/mpc85xx/ddr-gen3.c | 111 +++- arch/powerpc/include/asm/config_mpc85xx.h |6 ++ arch/powerpc/include/asm/fsl_ddr_sdram.h |5 ++ drivers/mmc/fsl_esdhc.c |5 ++ include/configs/MPC8572DS.h |3 +- 7 files changed, 136 insertions(+), 7 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/8xxx: Fix possible compile issue related to P1013
On Feb 4, 2011, at 12:56 PM, Kumar Gala wrote: > The P1013 is a single core version of P1022 and thus should use the > p1022_serdes.c code. It was acciently pointing to p1013_serdes.c which > doesn't exist. > > Reported-by: Renaud Barbier > Signed-off-by: Kumar Gala > --- > arch/powerpc/cpu/mpc85xx/Makefile |2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) applied to 85xx - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Pull request: nand flash
Dear Scott Wood, In message <20110202221646.GA7634@udp111988uds> you wrote: > The following changes since commit 42d44f631c4e8e5359775bdc098f2fffde4e5c05: > > Prepare v2011.03-rc1 (2011-02-02 22:37:32 +0100) > > are available in the git repository at: > git://git.denx.de/u-boot-nand-flash.git ..BRANCH.NOT.VERIFIED.. > > Alexander Holler (1): > NAND: Fix saving of redundand environment > > common/env_nand.c |2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) Master branch applied, thanks. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Bradley's Bromide: If computers get too powerful, we can organize them into a committee - that will do them in. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2 v3] powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from board
Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards
pretty much do the same thing. The only variations are in how many
controllers or DIMMs per controller exist. To make this work we
standardize on the names of the SPD_EEPROM_ADDRESS defines based on the
use case of the board.
We allow boards to override get_spd to either do board specific fixups
to the SPD data or deal with any unique behavior of how the SPD eeproms
are wired up.
Signed-off-by: Kumar Gala
---
* Changed __get_spd error message from debug -> printf
arch/powerpc/cpu/mpc8xxx/ddr/main.c | 63 +--
board/freescale/corenet_ds/ddr.c| 27 ---
board/freescale/mpc8536ds/ddr.c | 21 ---
board/freescale/mpc8540ads/ddr.c| 22
board/freescale/mpc8541cds/ddr.c| 21 ---
board/freescale/mpc8544ds/ddr.c | 22
board/freescale/mpc8548cds/ddr.c| 22
board/freescale/mpc8555cds/ddr.c| 21 ---
board/freescale/mpc8560ads/ddr.c| 22
board/freescale/mpc8568mds/ddr.c| 22
board/freescale/mpc8569mds/ddr.c| 22
board/freescale/mpc8572ds/ddr.c | 23 -
board/freescale/mpc8610hpcd/ddr.c | 21 ---
board/freescale/mpc8641hpcn/ddr.c | 30
board/freescale/p1022ds/ddr.c | 18 --
board/freescale/p2020ds/ddr.c | 19 --
board/sbc8548/ddr.c | 22
board/sbc8560/ddr.c | 22
board/sbc8641d/ddr.c| 30
board/socrates/ddr.c| 22
board/stx/stxgp3/ddr.c | 22
board/stx/stxssa/ddr.c | 21 ---
board/xes/xpedite517x/ddr.c | 25 +-
board/xes/xpedite520x/ddr.c | 17 +-
board/xes/xpedite537x/ddr.c | 17 +-
board/xes/xpedite550x/ddr.c | 15 +
include/configs/MPC8569MDS.h|3 +-
include/configs/MPC8610HPCD.h |2 +-
include/configs/P1022DS.h |2 +-
include/configs/P2020DS.h |2 +-
include/configs/xpedite550x.h |2 +-
31 files changed, 69 insertions(+), 551 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index bb96d66..c8fa123 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -13,6 +13,7 @@
*/
#include
+#include
#include
#include "ddr.h"
@@ -26,9 +27,65 @@ extern void fsl_ddr_set_lawbar(
extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num);
-/* Board-specific functions defined in each board's ddr.c */
-extern void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
- unsigned int ctrl_num);
+#if defined(SPD_EEPROM_ADDRESS) || \
+defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
+defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
+#if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
+u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
+ [0][0] = SPD_EEPROM_ADDRESS,
+};
+#endif
+#if (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
+u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
+ [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
+ [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
+};
+#endif
+#if (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
+ [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
+ [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
+ [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
+ [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
+};
+#endif
+
+static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
+{
+ int ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
+ sizeof(generic_spd_eeprom_t));
+
+ if (ret) {
+ printf("DDR: failed to read SPD from address %u\n",
i2c_address);
+ memset(spd, 0, sizeof(generic_spd_eeprom_t));
+ }
+}
+
+__attribute__((weak, alias("__get_spd")))
+void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
+
+void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
+ unsigned int ctrl_num)
+{
+ unsigned int i;
+ unsigned int i2c_address = 0;
+
+ if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) {
+ printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
+ return;
+ }
+
+ for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+ i2c_address = spd_i2c_addr[ctrl_num][i];
+ get_spd(&(
[U-Boot] [PATCH v2] powerpc/8xxx: Fix LAW init to respect pre-initialized entries
If some pre-boot or earlier stage bootloader (NAND SPL) has setup LAW
entries consider them good and mark them used.
In the NAND SPL case we skip re-initializing based on the law_table
since the SPL phase already did that.
Signed-off-by: Kumar Gala
---
* Fixed wording in comment per Timur's feedback
drivers/misc/fsl_law.c | 20
1 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c
index 63c08bf..8b37a2f 100644
--- a/drivers/misc/fsl_law.c
+++ b/drivers/misc/fsl_law.c
@@ -24,6 +24,7 @@
*/
#include
+#include
#include
#include
@@ -246,6 +247,25 @@ void init_laws(void)
#error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes
#endif
+ /*
+* Any LAWs that were set up before we booted assume they are meant to
+* be around and mark them used.
+*/
+ for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
+ u32 lawar = in_be32(LAWAR_ADDR(i));
+
+ if (lawar & LAW_EN)
+ gd->used_laws |= (1 << i);
+ }
+
+#ifndef CONFIG_NAND_SPL
+ /*
+* in NAND boot we've already parsed the law_table and setup those LAWs
+* so don't do it again.
+*/
+ return;
+#endif
+
for (i = 0; i < num_law_entries; i++) {
if (law_table[i].index == -1)
set_next_law(law_table[i].addr, law_table[i].size,
--
1.7.2.3
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[U-Boot] [PATCH] fsl_pci: Add support for FSL PCIe controllers v2.x
From: Prabhakar Kushwaha
FSL PCIe controller v2.1:
- New MSI inbound window
- Same Inbound windows address as PCIe controller v1.x
Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window
FSL PCIe controller v2.2 and v2.3:
- Different addresses for PCIe inbound window 3,2,1
- Exposed PCIe inbound window 0
- New PCIe interrupt status register
Added new Interrupt Status register to struct ccsr_pci & updated pit_t array
size to reflect the 4 inbound windows.
To maintain backward compatiblilty, on V2.2 or greater controllers we
start with inbound window 1 and leave inbound 0 with its default value
(which maps to CCSRBAR).
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Kumar Gala
---
arch/powerpc/include/asm/fsl_pci.h | 20
drivers/pci/fsl_pci_init.c | 12 ++--
2 files changed, 26 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_pci.h
b/arch/powerpc/include/asm/fsl_pci.h
index 0a98bde..82d75be 100644
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -25,6 +25,9 @@
#include
#include
+#define PEX_IP_BLK_REV_2_2 0x02080202
+#define PEX_IP_BLK_REV_2_3 0x02080203
+
int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
int fsl_is_pci_agent(struct pci_controller *hose);
void fsl_pci_config_unlock(struct pci_controller *hose);
@@ -73,7 +76,8 @@ typedef struct ccsr_pci {
u32 out_comp_to;/* 0x00C - PCI Outbound Completion Timeout
Register */
u32 out_conf_to;/* 0x010 - PCI Configuration Timeout Register */
u32 config; /* 0x014 - PCIE CONFIG Register */
- charres2[8];
+ u32 int_status; /* 0x018 - PCIE interrupt status register */
+ charres2[4];
u32 pme_msg_det;/* 0x020 - PCIE PME & message detect register */
u32 pme_msg_dis;/* 0x024 - PCIE PME & message disable register
*/
u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable
register */
@@ -83,8 +87,11 @@ typedef struct ccsr_pci {
u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */
pot_t pot[5]; /* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3,
and 4 */
- u32 res5[64];
- pit_t pit[3]; /* 0xda0 - 0xdff Inbound ATMU's 3, 2, and 1 */
+ u32 res5[24];
+ pit_t pmit; /* 0xd00 - 0xd9c Inbound ATMU's MSI */
+ u32 res6[24];
+ pit_t pit[4]; /* 0xd80 - 0xdff Inbound ATMU's 3, 2, 1 and 0 */
+
#define PIT3 0
#define PIT2 1
#define PIT1 2
@@ -158,6 +165,11 @@ typedef struct ccsr_pci {
u32 pdb_stat; /* 0xf00 - PCIE Debug Status */
charres24[252];
} ccsr_fsl_pci_t;
+#define PCIE_CONFIG_PC 0x0002
+#define PCIE_CONFIG_OB_CK 0x2000
+#define PCIE_CONFIG_SAC0x0010
+#define PCIE_CONFIG_SP 0x8002
+#define PCIE_CONFIG_SCC0x8001
struct fsl_pci_info {
unsigned long regs;
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 6c168c1..853b441 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
@@ -223,6 +223,7 @@ void fsl_pci_init(struct pci_controller *hose, struct
fsl_pci_info *pci_info)
u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data;
u16 temp16;
u32 temp32;
+ u32 block_rev;
int enabled, r, inbound = 0;
u16 ltssm;
u8 temp8, pcie_cap;
@@ -232,13 +233,20 @@ void fsl_pci_init(struct pci_controller *hose, struct
fsl_pci_info *pci_info)
/* Initialize ATMU registers based on hose regions and flags */
volatile pot_t *po = &pci->pot[1]; /* skip 0 */
- volatile pit_t *pi = &pci->pit[2]; /* ranges from: 3 to 1 */
+ volatile pit_t *pi;
u64 out_hi = 0, out_lo = -1ULL;
u32 pcicsrbar, pcicsrbar_sz;
pci_setup_indirect(hose, cfg_addr, cfg_data);
+ block_rev = in_be32(&pci->block_rev1);
+ if (PEX_IP_BLK_REV_2_2 <= block_rev) {
+ pi = &pci->pit[2]; /* 0xDC0 */
+ } else {
+ pi = &pci->pit[3]; /* 0xDE0 */
+ }
+
/* Handle setup of outbound windows first */
for (r = 0; r < hose->region_count; r++) {
unsigned long flags = hose->regions[r].flags;
--
1.7
Re: [U-Boot] [PATCH 02/32] x86: Align config.mk and linker scripts with other arches
On Fri, 4 Feb 2011 23:35:29 +1100 Graeme Russ wrote: > LDFLAGS += --cref > -LDFLAGS_u-boot += --gc-sections > -PLATFORM_RELFLAGS += -ffunction-sections > +LDFLAGS_u-boot += --gc-sections -pie > +LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds The use of --cref came up recently (see http://lists.denx.de/pipermail/u-boot/2011-February/086698.html). During what link phase is --cref supposed to be used? Currently it is being used during partial links only, and not the final link, as a result of commit 8aba9dceebb14144e07d19593111ee3a999c37fc. As the toplevel config.mk currently stands, it would have to go in PLATFORM_LDFLAGS to be used in all link phases, or LDFLAGS_u-boot to be used when linking the final image only. BTW, is it really enabled because of something to do with i386? Or just maintainer preference (in which case it should probably be a non-arch config, or in this case just enabled unconditionally, since I don't think there's any harm to it). -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] powerpc/85xx: Add support for Freescale P1023/P1017 Processors
From: Roy Zang
Add P1023 (dual core) & P1017 (single core) specific information:
* SERDES Table
* Added P1023/P1017 to cpu_type_list and SVR list
(fixed issue with P1013 not being sorted correctly).
* Added P1023/P1027 to config_mpc85xx.h
* Added new LAW type introduced on P1023/P1017
* Updated a few immap register/defines unique to P1023/P1017
Signed-off-by: Roy Zang
Signed-off-by: Kumar Gala
---
arch/powerpc/cpu/mpc85xx/Makefile |2 +
arch/powerpc/cpu/mpc85xx/p1023_serdes.c | 53 +
arch/powerpc/cpu/mpc8xxx/cpu.c|6 +++-
arch/powerpc/include/asm/config_mpc85xx.h | 20 +++
arch/powerpc/include/asm/fsl_law.h|1 +
arch/powerpc/include/asm/immap_85xx.h | 14
arch/powerpc/include/asm/processor.h |4 ++
7 files changed, 99 insertions(+), 1 deletions(-)
create mode 100644 arch/powerpc/cpu/mpc85xx/p1023_serdes.c
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile
b/arch/powerpc/cpu/mpc85xx/Makefile
index 628e1cf..cc16db3 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -92,9 +92,11 @@ COBJS-$(CONFIG_P1011)+= p1021_serdes.o
COBJS-$(CONFIG_P1012) += p1021_serdes.o
COBJS-$(CONFIG_P1013) += p1022_serdes.o
COBJS-$(CONFIG_P1014) += p1010_serdes.o
+COBJS-$(CONFIG_P1017) += p1023_serdes.o
COBJS-$(CONFIG_P1020) += p1021_serdes.o
COBJS-$(CONFIG_P1021) += p1021_serdes.o
COBJS-$(CONFIG_P1022) += p1022_serdes.o
+COBJS-$(CONFIG_P1023) += p1023_serdes.o
COBJS-$(CONFIG_P2010) += p2020_serdes.o
COBJS-$(CONFIG_P2020) += p2020_serdes.o
COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
new file mode 100644
index 000..c8ab5d6
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Author: Roy Zang
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define SRDS1_MAX_LANES4
+
+static u32 serdes1_prtcl_map;
+
+static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
+ [0x00] = {PCIE1, PCIE2, NONE, NONE},
+ [0x01] = {PCIE1, PCIE2, PCIE3, NONE},
+ [0x02] = {PCIE1, PCIE2, PCIE3, SGMII_FM1_DTSEC2},
+ [0x03] = {PCIE1, PCIE2, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2},
+};
+
+int is_serdes_configured(enum srds_prtcl device)
+{
+ int ret = (1 << device) & serdes1_prtcl_map;
+ return ret;
+}
+
+void fsl_serdes_init(void)
+{
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ u32 pordevsr = in_be32(&gur->pordevsr);
+ u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+ MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+ int lane;
+
+ debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
+
+ if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+ printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
+ return;
+ }
+ for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
+ serdes1_prtcl_map |= (1 << lane_prtcl);
+ }
+
+}
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 4335fb4..d2baaf0 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -71,15 +71,19 @@ struct cpu_type cpu_type_list [] = {
CPU_TYPE_ENTRY(P1012, P1012, 1),
CPU_TYPE_ENTRY(P1012, P1012_E, 1),
CPU_TYPE_ENTRY(P1013, P1013, 1),
+ CPU_TYPE_ENTRY(P1013, P1013_E, 1),
CPU_TYPE_ENTRY(P1014, P1014_E, 1),
CPU_TYPE_ENTRY(P1014, P1014, 1),
- CPU_TYPE_ENTRY(P1013, P1013_E, 1),
+ CPU_TYPE_ENTRY(P1017, P1017, 1),
+ CPU_TYPE_ENTRY(P1017, P1017, 1),
CPU_TYPE_ENTRY(P1020, P1020, 2),
CPU_TYPE_ENTRY(P1020, P1020_E, 2),
CPU_TYPE_ENTRY(P1021, P1021, 2),
CPU_TYPE_ENTRY(P1021, P1021_E, 2),
CPU_TYPE_ENTRY(P1022, P1022, 2),
CPU_TYPE_ENTRY(P1022, P1022_E, 2),
+ CPU_TYPE_ENTRY(P1023, P1023, 2),
+ CPU_TYPE_ENTRY(P1023, P1023_E, 2),
CPU_TYPE_ENTRY(P2010, P2010, 1),
CPU_TYPE_ENTRY(P2010, P2010_E, 1),
CPU_TYPE_ENTRY(P2020, P2020, 2),
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index 57d252c..9c7ae8c 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -110,6 +110,16 @@
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
+#elif defined(CONFIG_P1017)
+#define CONFIG_MAX_CPUS1
+#define CONFIG_SYS_FSL_NUM_LAWS
[U-Boot] [PATCH 2/2] powerpc/85xx: Refactor Qman/Portal support to be shared between SoCs
From: Haiying Wang
There are some differences between CoreNet (P2040, P3041, P5020, P4080)
and and non-CoreNet (P1017, P1023) based SoCs in what features exist and
the memory maps.
* Rename various immap defines to remove _CORENET_ if they are shared
* Added P1023/P1017 specific memory offsets
* Only setup LIODNs or LIODN related code on CORENET based SoCs
(features doesn't exist on P1023/P1017)
Signed-off-by: Haiying Wang
Signed-off-by: Kumar Gala
---
arch/powerpc/cpu/mpc85xx/Makefile |2 +-
arch/powerpc/cpu/mpc85xx/portals.c| 32 +++-
arch/powerpc/cpu/mpc85xx/speed.c |7 +++
arch/powerpc/include/asm/fsl_liodn.h | 10 +-
arch/powerpc/include/asm/immap_85xx.h | 12 ++--
include/configs/corenet_ds.h |1 +
6 files changed, 43 insertions(+), 21 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile
b/arch/powerpc/cpu/mpc85xx/Makefile
index cc16db3..5791be0 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -69,7 +69,7 @@ COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
COBJS-$(CONFIG_FSL_CORENET) += liodn.o
COBJS-$(CONFIG_MP) += mp.o
COBJS-$(CONFIG_PCI)+= pci.o
-COBJS-$(CONFIG_FSL_CORENET) += portals.o
+COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
# various SoC specific assignments
COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
diff --git a/arch/powerpc/cpu/mpc85xx/portals.c
b/arch/powerpc/cpu/mpc85xx/portals.c
index 01aec6e..e8d53bb 100644
--- a/arch/powerpc/cpu/mpc85xx/portals.c
+++ b/arch/powerpc/cpu/mpc85xx/portals.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -30,18 +30,13 @@
#include
#include
-static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_CORENET_QMAN_ADDR;
+static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
void setup_portals(void)
{
+#ifdef CONFIG_FSL_CORENET
int i;
- /* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
-#ifdef CONFIG_PHYS_64BIT
- out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
-#endif
- out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
-
for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
u8 sdest = qp_info[i].sdest;
u16 fliodn = qp_info[i].fliodn;
@@ -53,6 +48,13 @@ void setup_portals(void)
/* set frame liodn */
out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn);
}
+#endif
+
+ /* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
+#ifdef CONFIG_PHYS_64BIT
+ out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
+#endif
+ out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
}
/* Update portal containter to match LAW setup of portal in phy map */
@@ -118,9 +120,12 @@ void fdt_portal(void *blob, const char *compat, const char
*container,
static int fdt_qportal(void *blob, int off, int id, char *name,
enum fsl_dpaa_dev dev, int create)
{
- int childoff, dev_off, num, ret = 0;
+ int childoff, dev_off, ret = 0;
uint32_t dev_handle;
+#ifdef CONFIG_FSL_CORENET
+ int num;
u32 liodns[2];
+#endif
childoff = fdt_subnode_offset(blob, off, name);
if (create) {
@@ -154,9 +159,11 @@ static int fdt_qportal(void *blob, int off, int id, char
*name,
if (ret < 0)
return ret;
+#ifdef CONFIG_FSL_CORENET
num = get_dpaa_liodn(dev, &liodns[0], id);
ret = fdt_setprop(blob, childoff, "fsl,liodn",
&liodns[0], sizeof(u32) * num);
+#endif
} else {
return childoff;
}
@@ -184,7 +191,9 @@ void fdt_fixup_qportals(void *blob)
off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
while (off != -FDT_ERR_NOTFOUND) {
+#ifdef CONFIG_FSL_CORENET
u32 liodns[2];
+#endif
const int *ci = fdt_getprop(blob, off, "cell-index", NULL);
int j, i = *ci;
@@ -192,6 +201,7 @@ void fdt_fixup_qportals(void *blob)
if (err < 0)
goto err;
+#ifdef CONFIG_FSL_CORENET
liodns[0] = qp_info[i].dliodn;
liodns[1] = qp_info[i].fliodn;
@@ -199,6 +209,7 @@ void fdt_fixup_qportals(void *blob)
&liodns, sizeof(u32) * 2);
if (err < 0)
goto err;
+#endif
i++;
@@ -207,6 +218,7 @@ void fdt_fixup_qportals(void *blob)
if (err < 0)
goto err;
+#ifdef CONFIG_FSL_CORENET
#ifdef CONFIG_SYS_DPAA_PME
err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORT
Re: [U-Boot] [U-BOOT] [PATCH] env: reduce the stack footprint for the env buf
On Fri, 4 Feb 2011 11:08:23 +0800 Lei Wen wrote: > Original env buf directly locate at stack lead large stack footprint > when call those env functions. It is not good when the system memory > is critical or only want the uboot run at restrict range, that is not > to touch the memory of other place at its best. > > So now this patch move the env buf to the heap area, which reduce the > area uboot need to touch. > > Signed-off-by: Lei Wen > --- > common/env_dataflash.c |8 +++- > common/env_eeprom.c|8 +++- > common/env_mgdisk.c| 10 +- > common/env_mmc.c |9 - > common/env_nand.c | 10 +- > common/env_nvram.c |9 - > common/env_sf.c|9 - > 7 files changed, 56 insertions(+), 7 deletions(-) NAND bits are Acked-by: Scott Wood -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Pull request: nand flash
On Fri, 4 Feb 2011 20:37:58 +0100 Wolfgang Denk wrote: > Dear Scott Wood, > > In message <20110202221646.GA7634@udp111988uds> you wrote: > > The following changes since commit 42d44f631c4e8e5359775bdc098f2fffde4e5c05: > > > > Prepare v2011.03-rc1 (2011-02-02 22:37:32 +0100) > > > > are available in the git repository at: > > git://git.denx.de/u-boot-nand-flash.git ..BRANCH.NOT.VERIFIED.. > > Which branch should I pull? Doh, forgot to push and didn't notice the "not verified" message. Fixed now, it's the master branch. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] Add support Asix's AX88783 ethernet chip v1.00
for more information about this chip, please check:
http://www.asix.com.tw/products.php?op=pItemdetail&PItemID=98;65;86&PLine=6
Signed-off-by: Joe Xue
Cc: Wolfgang Denk
Cc: Stefano Babic
---
README|6 +
drivers/net/Makefile |1 +
drivers/net/ax88783.c | 295 +
drivers/net/ax88783.h | 102 +
include/netdev.h |1 +
5 files changed, 405 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/ax88783.c
create mode 100644 drivers/net/ax88783.h
diff --git a/README b/README
index 755d17c..b5e3c48 100644
--- a/README
+++ b/README
@@ -891,6 +891,12 @@ The following options need to be configured:
Define this if data bus is 16 bits. If your processor
automatically converts one 32 bit word to two 16 bit
words you may also try CONFIG_SMC911X_32_BIT.
+ CONFIG_DRIVER_AX88783
+ Support for ASIX's AX88783 chip
+
+ CONFIG_AX88783_BASE
+ Define this to hold the physical address
+ of the device (I/O space)
- USB Support:
At the moment only the UHCI host controller is
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index fd9d0b4..7cd6e2c 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -30,6 +30,7 @@ COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o
COBJS-$(CONFIG_ALTERA_TSE) += altera_tse.o
COBJS-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o
+COBJS-$(CONFIG_DRIVER_AX88783) += ax88783.o
COBJS-$(CONFIG_BCM570x) += bcm570x.o
COBJS-$(CONFIG_BCM570x) += bcm570x_autoneg.o
COBJS-$(CONFIG_BCM570x) += 5701rls.o
diff --git a/drivers/net/ax88783.c b/drivers/net/ax88783.c
new file mode 100644
index 000..f24288c
--- /dev/null
+++ b/drivers/net/ax88783.c
@@ -0,0 +1,295 @@
+/*
+ * (C) Copyright 2011 Joe Xue
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+
+/*
+ * AX88783 has two ethernet ports, this driver uses port 0 in u-boot
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "ax88783.h"
+
+static int ax88783_phy_initial(struct eth_device *dev)
+{
+ int i;
+ int reg_num;
+ unsigned int tmp;
+ struct ax88783_reg * reg = (struct ax88783_reg *)dev->iobase;
+
+ /* reset chip */
+ tmp = readl(®->cr);
+ writel((tmp & ~CR_CHIP_RESET), ®->cr);
+ udelay(1000);
+
+ writel((tmp | CR_CHIP_RESET), ®->cr);
+
+ /* phy init */
+ tmp = readl(®->pcr);
+ tmp |= PCR_PHY0_RESET_CLEAR;
+
+ writel(tmp, ®->pcr);
+ /* this delay is a bit long, but the physical initialization
+* only be called once when the board is starting, so it's
+* acceptable */
+ udelay(10);
+
+ tmp = readl(®->pollcr);
+ tmp &= POLLCR_PORT0_PHYID_MASK;
+ tmp |= POLLCR_PORT0_PHYID(0x10);
+ writel(tmp, ®->pollcr);
+
+ /* write MII mode */
+ tmp = readl(®->miicr) & 0xFF;
+ tmp &= (~MIICR_PORT0_MII_CLK_GEN);
+ tmp &= (~MIICR_PORT0_PHY_RMII);
+ writel(tmp, ®->miicr);
+
+ /* set LED mode */
+ tmp = readl(®->ledcr);
+ tmp |= LEDCR_PORT_LED_ON(0) | LEDCR_LED0(PHY_LED_RX | PHY_LED_TX);
+ tmp |= LEDCR_PORT_LED_ON(1) | LEDCR_LED1(PHY_LED_LINK);
+ writel(tmp, ®->ledcr);
+
+ /* set auto polling */
+ tmp = readl(®->pollcr);
+ tmp |= (POLLCR_PORT0_AUTO_POOLING);
+ writel(tmp, ®->pollcr);
+
+ /* set link speed */
+ for (i = 0; i < 2; i++) {
+ reg_num = i*8+16;
+ tmp = MDCR_READ | MDCR_PHY_ID(0x10) | MDCR_PHY_REG(reg_num);
+ writel(tmp, ®->mdcr);
+ tmp = readl(®->mdcr);
+ if (tmp & MDCR_VALID) {
+ puts("link speed init failed!\n");
+ return 1;
+ }
+
+ tmp = readl(®->mdcr) & MDCR_VALUE_MASK;
+ tmp = tmp | 0x1000 | MDCR_WRITE | \
+ MDCR_PHY_ID(0x10) | MDCR_PHY_REG(reg_num);
+ writel(tmp, ®->mdcr);
+ tmp = readl(®->mdcr);
+ if (tmp & MDCR_VALID) {
+ puts("link speed init failed!\n");
+ return 1;
+
Re: [U-Boot] ATMEL maintainer (WAS Re: [PATCH] atmel nand patch CE don't care NAND)
On 02/04/2011 08:10 PM, Wolfgang Denk wrote: > Dear Michael Trimarchi, > > In message <4d4c4a77.4060...@gandalf.sssup.it> you wrote: >> I have seen that there is not an atmel maintainer. Is it correct to send the >> patch to arm >> one? Who is the right person? > Where have you seen that? > > The official source of this information is > http://www.denx.de/wiki/U-Boot/Custodians It was a mistake throw the gitweb. I have seen the at91 tree, sorry Michael > There you can see that Reinhard is the custodian for Atmel systems. > > Best regards, > > Wolfgang Denk > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Pull request: u-boot-sh
Dear Nobuhiro Iwamatsu,
In message you
wrote:
>
> git://git.denx.de/u-boot-sh.git master
>
> Nobuhiro Iwamatsu (14):
> sh: Remove config.mk for MigoR board
> sh: Remove config.mk for ap325rxa board
> sh: Remove config.mk for r2dplus board
> sh: Remove config.mk for r7780mp board
> sh: Remove config.mk for rsk7203 board
> sh: Remove config.mk for sh7763rdp board
> sh: Remove config.mk for sh7785lcr board
> sh: Remove config.mk for ms7720se board
> sh: Remove config.mk for ms7722se board
> sh: Remove config.mk for ms7750se board
> sh: Remove config.mk for mpr2 board
> sh: Remove config.mk for espt board
> sh: Remove config.mk for shmin board
> sh: sh7785lcr: Fix out of tree building
>
> Yoshihiro Shimoda (6):
> sh: add support the CONFIG_SYS_LDSCRIPT
> README: add description of sh_eth driver
> net: sh_eth: add cache handling
> spi: add support SuperH SPI module
> sh: add support for sh7757lcr board
> change email address in MAINTAINERS
>
> MAINTAINERS|3 +-
> README | 17 +
> arch/sh/config.mk |6 +
> arch/sh/include/asm/cpu_sh4.h |2 +
> arch/sh/include/asm/cpu_sh7757.h | 218
> board/espt/config.mk |9 -
> board/mpr2/config.mk | 37 --
> board/ms7720se/config.mk | 34 --
> board/ms7722se/config.mk | 31 --
> board/ms7750se/config.mk | 23 -
> board/renesas/ap325rxa/config.mk | 26 -
> board/renesas/r2dplus/config.mk| 23 -
> board/renesas/r7780mp/config.mk| 27 -
> board/renesas/rsk7203/config.mk| 28 -
> .../{MigoR/config.mk => sh7757lcr/Makefile}| 38 +-
> board/renesas/sh7757lcr/lowlevel_init.S| 558
>
> board/renesas/sh7757lcr/sh7757lcr.c| 454
> board/renesas/sh7757lcr/spi-boot.c | 109
> board/renesas/sh7757lcr/u-boot.lds | 101
> board/renesas/sh7763rdp/config.mk | 11 -
> board/renesas/sh7785lcr/Makefile |8 +-
> board/renesas/sh7785lcr/config.mk | 31 --
> board/shmin/config.mk | 27 -
> boards.cfg |1 +
> doc/README.sh7757lcr | 64 +++
> drivers/net/sh_eth.c |9 +
> drivers/spi/Makefile |1 +
> drivers/spi/sh_spi.c | 261 +
> drivers/spi/sh_spi.h | 79 +++
> include/configs/MigoR.h|1 +
> include/configs/ap325rxa.h |2 +
> include/configs/espt.h |1 +
> include/configs/mpr2.h |2 +
> include/configs/ms7720se.h |1 +
> include/configs/ms7722se.h |1 +
> include/configs/ms7750se.h |1 +
> include/configs/r2dplus.h |1 +
> include/configs/r7780mp.h |1 +
> include/configs/rsk7203.h |1 +
> include/configs/sh7757lcr.h| 146 +
> include/configs/sh7763rdp.h|1 +
> include/configs/sh7785lcr.h|2 +
> include/configs/shmin.h|1 +
> 43 files changed, 2075 insertions(+), 323 deletions(-)
> create mode 100644 arch/sh/include/asm/cpu_sh7757.h
> delete mode 100644 board/espt/config.mk
> delete mode 100644 board/mpr2/config.mk
> delete mode 100644 board/ms7720se/config.mk
> delete mode 100644 board/ms7722se/config.mk
> delete mode 100644 board/ms7750se/config.mk
> delete mode 100644 board/renesas/ap325rxa/config.mk
> delete mode 100644 board/renesas/r2dplus/config.mk
> delete mode 100644 board/renesas/r7780mp/config.mk
> delete mode 100644 board/renesas/rsk7203/config.mk
> rename board/renesas/{MigoR/config.mk => sh7757lcr/Makefile} (54%)
> create mode 100644 board/renesas/sh7757lcr/lowlevel_init.S
> create mode 100644 board/renesas/sh7757lcr/sh7757lcr.c
> create mode 100644 board/renesas/sh7757lcr/spi-boot.c
> create mode 100644 board/renesas/sh7757lcr/u-boot.lds
> delete mode 100644 board/renesas/sh7763rdp/config.mk
> delete mode 100644 board/renesas/sh7785lcr/config.mk
> delete mode 100644 board/shmin/config.mk
> create mode 100644 doc/README.sh7757lcr
> create mode 100644 drivers/spi/sh_spi.c
> create mode 100644 drivers/spi/
Re: [U-Boot] Pull request: nand flash
Dear Scott Wood, In message <20110202221646.GA7634@udp111988uds> you wrote: > The following changes since commit 42d44f631c4e8e5359775bdc098f2fffde4e5c05: > > Prepare v2011.03-rc1 (2011-02-02 22:37:32 +0100) > > are available in the git repository at: > git://git.denx.de/u-boot-nand-flash.git ..BRANCH.NOT.VERIFIED.. Which branch should I pull? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de "Security is mostly a superstition. It does not exist in nature... Life is either a daring adventure or nothing." - Helen Keller ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ATMEL maintainer (WAS Re: [PATCH] atmel nand patch CE don't care NAND)
Dear Michael Trimarchi, In message <4d4c4a77.4060...@gandalf.sssup.it> you wrote: > > I have seen that there is not an atmel maintainer. Is it correct to send the > patch to arm > one? Who is the right person? Where have you seen that? The official source of this information is http://www.denx.de/wiki/U-Boot/Custodians There you can see that Reinhard is the custodian for Atmel systems. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de "Whoever undertakes to set himself up as a judge of Truth and Know- ledge is shipwrecked by the laughter of the gods." - Albert Einstein ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/8xxx: Fix possible compile issue related to P1013
The P1013 is a single core version of P1022 and thus should use the p1022_serdes.c code. It was acciently pointing to p1013_serdes.c which doesn't exist. Reported-by: Renaud Barbier Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/Makefile |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index b7f51e7..cbb0fc6 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -89,7 +89,7 @@ COBJS-$(CONFIG_MPC8569) += mpc8569_serdes.o COBJS-$(CONFIG_MPC8572) += mpc8572_serdes.o COBJS-$(CONFIG_P1011) += p1021_serdes.o COBJS-$(CONFIG_P1012) += p1021_serdes.o -COBJS-$(CONFIG_P1013) += p1013_serdes.o +COBJS-$(CONFIG_P1013) += p1022_serdes.o COBJS-$(CONFIG_P1020) += p1021_serdes.o COBJS-$(CONFIG_P1021) += p1021_serdes.o COBJS-$(CONFIG_P1022) += p1022_serdes.o -- 1.7.2.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] ATMEL maintainer (WAS Re: [PATCH] atmel nand patch CE don't care NAND)
Dear Wolfgang I have seen that there is not an atmel maintainer. Is it correct to send the patch to arm one? Who is the right person? Michael Trimarchi On 02/02/2011 04:11 PM, Michael Trimarchi wrote: > Hi, > > this patch fix the support for CE don't care nand > > Michael Trimarchi > > > ___ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-boot-file] arch/powerpc/cpu/mpc85xx/p1013_serdes.c is missing
On Feb 4, 2011, at 11:30 AM, Renaud Barbier wrote: > just noticed the following: > > The object file p1013_serdes.o is referenced in the > file arch/powerpc/cpu/mpc85xx/Makefile: > COBJS-$(CONFIG_P1013) += p1013_serdes.o > > However, the source code is not found in the directory. I'll fix it, it should be COBJS-$(CONFIG_P1013) += p1022_serdes.o (p1013 is single core version of p1022) - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] omap3_beagle: enable the use of a plain text file named uEnv.txt instead of boot.scr
On Mon, Jan 24, 2011 at 6:08 PM, Alexander Holler wrote:
> Using the new env import command it is possible to use plain text files
> instead
> of script-images. Plain text files are much easier to handle.
I agree this has been a frequent concern of BeagleBoard users. I
would like to see this patch get accepted.
>
> E.g. If your boot.scr contains the following:
> ---
> setenv dvimode 1024x768-16@60
> run loaduimage
> run mmcboot
> ---
> you could create a file named uEnv.txt and use that instead of boot.scr:
> ---
> dvimode=1024x768-16@60
> uenvcmd=run loaduimage; run mmcboot
> ---
> The variable uenvcmd (if existent) will be executed (using run) after uEnv.txt
> was loaded. If uenvcmd doesn't exist the default boot sequence will be
> started,
> therefore you could just use
> ---
> dvimode=1024x768-16@60
> ---
> as uEnv.txt because loaduimage and mmcboot is part of the default boot
> sequence.
>
> For backwards compatibility the use of boot.scr is still supported.
>
> Signed-off-by: Alexander Holler
> ---
> include/configs/omap3_beagle.h | 25 -
> 1 files changed, 20 insertions(+), 5 deletions(-)
>
> diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
> index 5cfa4cb..0214c7f 100644
> --- a/include/configs/omap3_beagle.h
> +++ b/include/configs/omap3_beagle.h
> @@ -218,6 +218,9 @@
> "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
> "bootscript=echo Running bootscript from mmc ...; " \
> "source ${loadaddr}\0" \
> + "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
> + "importbootenv=echo Importing environment from mmc ...; " \
> + "env import -t $loadaddr $filesize\0" \
> "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
> "mmcboot=echo Booting from mmc ...; " \
> "run mmcargs; " \
> @@ -229,12 +232,24 @@
>
> #define CONFIG_BOOTCOMMAND \
> "if mmc rescan ${mmcdev}; then " \
> - "if run loadbootscript; then " \
> - "run bootscript; " \
> + "if run loadbootenv; then " \
> + "run importbootenv;" \
> + "if test -n $uenvcmd; then " \
> + "echo Running uenvcmd ...;run uenvcmd;" \
> + "else " \
I believe the code would be cleaner without this else clause. You
could simply put the test for the boot environment variable loaded out
of uEnv.txt ahead of the test for loading boot.scr. The running of
uenvcmd should prevent any other boot operations from occurring if it
succeeds, so you can leave out the else entirely and just close the if
statement. I think the end result is the same, but the code would be
more readable, less nested, and each edit wouldn't impact the rest of
the bootcmd. I made a patch that did this, but I have some
dependencies on commands that I haven't yet got accepted.[1]
[1]
http://gitorious.org/beagleboard-validation/u-boot/blobs/dcbcbcded81e92a30081663371e2bd458ecccaba/include/configs/omap3_beagle.h
> + "if run loaduimage; then " \
> + "run mmcboot; " \
> + "else run nandboot; " \
> + "fi; " \
> + "fi; " \
> "else " \
> - "if run loaduimage; then " \
> - "run mmcboot; " \
> - "else run nandboot; " \
> + "if run loadbootscript; then " \
> + "run bootscript; " \
> + "else " \
> + "if run loaduimage; then " \
> + "run mmcboot; " \
> + "else run nandboot; " \
> + "fi; " \
> "fi; " \
> "fi; " \
> "else run nandboot; fi"
> --
> 1.7.2.2
>
> ___
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> http://lists.denx.de/mailman/listinfo/u-boot
>
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[U-Boot] [U-boot-file] arch/powerpc/cpu/mpc85xx/p1013_serdes.c is missing
just noticed the following: The object file p1013_serdes.o is referenced in the file arch/powerpc/cpu/mpc85xx/Makefile: COBJS-$(CONFIG_P1013) += p1013_serdes.o However, the source code is not found in the directory. -- Renaud Barbier 14, Links Place 3/2 great Michael House Edinburgh, EH67EN Tel: +44 131 561 3532 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] omap3 mux enabling
Am 02.02.2011 15:50, schrieb jacopo mondi: > Mine is a question related to an end-user problem, since I'm no more > able to do multiplexing for my DM3730 Beagleboard xM platform. > The problem is quite simple, multiplexer configurations are totally > ignored by u-boot (v2010.12), and I'm not able to do what I was used > to do with my previous C4 board (with v2010.06 and v2010.03). U-Boot still setups the multiplexing (and the kernel does that too). If pin-multiplexing wouldn't work, the LEDs wouldn't go on and you wouldn't be able to boot something. So something else must be wrong on your side. Maybe your are using a broken toolchain. Search the post for this month for the subject WARNING to find something on that topic. Regards, Alexander ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [STATUS] v2011.03-rc1 released
On Thu, 3 Feb 2011 18:52:58 +0100 Alexander Holler wrote: > Hello, > > Am 02.02.2011 22:55, schrieb Wolfgang Denk: > > * U-Boot v2011.03-rc1 was released on Wed, 02 Feb 2011. > > > > * Release "v2011.03" is scheduled in 39 days - on March 13, 2011. > > > > Please help testing, and check if all your relevant patches have been > > included. > > I'm missing my patch for the problem with redundand environments in NAND: > > http://lists.denx.de/pipermail/u-boot/2011-January/086293.html > > I think this should go into the 2010.03 too. I sent a pull request on Wedensday: http://lists.denx.de/pipermail/u-boot/2011-February/086760.html -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Add support for ASIX's AX88783 ethernet chip
Dear Joe XUE,
In message you wrote:
>
> > > Signed-off-by: Joe Xue
> > >
> >
> > Please add a version number to your patch to make easier tracking which
> > is your last version.
> >
> Will add it.
> > Do not forget to add always the net Maintainer to CC (Wolfgang Denk), I
> > added him now.
> >
> Not exactly understand your meaning. You mean I should add wd as maintainer
> to my code or just add him in mail.
Only email, please.
An easy way to not forget this is to add a "Cc:" line below your
Signed-off-by: line - then "git send-email" will automatically
generate the needed Cc:s
> > > +static void ax88783_halt(struct eth_device *dev)
> > > +{
> > > + unsigned int tmp;
> > > + struct ax88783_reg *reg = (struct ax88783_reg *)dev->iobase;
> > > + tmp = readl(®->pcr);
> > > + writel((tmp | PCR_LOOP_BACK), ®->pcr);
> > > +}
> >
> > From the name it seems you set the controller in loopback, instead of
> > disabling it. Is it correct ?
> >
> mmn. I just make it can't receive the data outside.The other way is make it
> into sleep mode.
Please put it in sleep mode, then.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
Most legends have their basis in facts.
-- Kirk, "And The Children Shall Lead", stardate 5029.5
___
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Re: [U-Boot] [PATCH] Introduce a new linker flag LDFLAGS_FINAL
Dear Wolfgang, On Tue, 2011-02-01 at 14:40 -0600, Scott Wood wrote: > On Tue, 1 Feb 2011 21:20:50 +0100 > Wolfgang Denk wrote: > > > Dear Scott Wood, > > > > In message <20110201135136.0817f...@udp111988uds.am.freescale.net> you > > wrote: > > > > > > > > Prior to the introduction of LDFLAGS_u-boot, was LDFLAGS not what was > > > > > used? So before, anything that board/cpu code adds directly to > > > > > LDFLAGS > > > > > (maybe they're supposed to use PLATFORM_LDFLAGS, but not all do) was > > > > > used in the final link. After 8aba9dc, only things in > > > > > PLATFORM_LDFLAGS plus -Bstatic and -T are used in the final link. > > > > > > > > And this is correct for all boards? > > > > > > By "this" do you mean the switch to PLATFORM_LDFLAGS in 8aba9dc, or the > > > switch back to LDFLAGS? It's not obvious to me that the dropping of > > > > I don;t understand why you contine to talk about "switch to > > PLATFORM_LDFLAGS in 8aba9dc". There was no such switch - at least I > > cannot see it. > > > > I see only a switch in your patch. This is why I'm asking. > > Before 8aba9dc, the flags for the final link were produced by taking > the existing LDFLAGS, and adding: > -Bstatic -T $(PLATFORM_LDFLAGS) -Ttext . > > This included anything that cpu/board code added to LDFLAGS -- some > architectures added --gc-sections, x86 added --cref, etc. Since the above > flags are added to LDFLAGS, rather than replacing them, these flags got used > in the final link. > > Commit 8aba9dc introduces LDFLAGS_u-boot, so that LDFLAGS is no longer the > source for the flags for the final link. It generates LDFLAGS_u-boot using > PLATFORM_LDFLAGS, not LDFLAGS. It converts most of the board/cpu updates to > LDFLAGS into LDFLAGS_u-boot, but it missed --cref. > > I don't see any other LDFLAGS changes in board/cpu code, so the distinction > between using LDFLAGS and PLATFORM_LDFLAGS should have no other impact on > current boards. However, the patch appears to be intended to support > platform linker flags that need to be used during partial link, which > would involve board/cpu additions to LDFLAGS. This change would break that > only if those options need to be used for partial link *only*, and cannot be > used in the final link. In such a case I'd suggest using something like > LDFLAGS_PARTIAL to make this explicit. But I'd be surprised if that > were actually the case. > > If you're looking to cut down on the number of variables, it's not clear to > me what PLATFORM_LDFLAGS is supposed to mean distinct from adding to > LDFLAGS. > > -Scott Do you have time to read Scott's email and give us any further recommendation? We do need to solve the issues of partial linking caused by commit 8aba9dc. Thanks. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2] EfikaMX: switch to MACH_TYPE_MX51_EFIKAMX
On 02/03/2011 03:19 PM, Loïc Minier wrote: > Upstream linux moved from MACH_TYPE_MX51_LANGE51 to > MACH_TYPE_MX51_EFIKAMX. > > Signed-off-by: Loïc Minier > --- > Changes for V2: > * Add Signed-off-by Applied to u-boot-imx, as this is a fix, thanks. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: off...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Add support for ASIX's AX88783 ethernet chip
On 02/04/2011 03:47 PM, Joe XUE wrote: >> Do not forget to add always the net Maintainer to CC (Wolfgang Denk), I >> added him now. >> > > Not exactly understand your meaning. You mean I should add wd as > maintainer to my code or > just add him in mail. Only add him in mail. He is the maintainer for net code. >> From the name it seems you set the controller in loopback, instead of >> disabling it. Is it correct ? >> > > mmn. I just make it can't receive the data outside. > The other way is make it into sleep mode. I do not know your chip, I cannot help. However, this function is thought to put the controller in a not operative state. It is a good law to leave your hardware disable and let the kernel to reinitialize it again when your system boots. > I refer to the newest net driver patch ftgmac100.c, it uses this > function to get > mac address from environmental setting. and I checked the > code eth_getenv_enetaddr > also call the is_valid_ether_addr(). I checked this driver, too.IMHO it is wrong, and I do not know why in ftgmac100_set_mac_from_env() is called getenv instead of using directly the values in dev->enetaddr. Anyway, I missed my chance to send my comments ;-) You can check in other drivers in drivers/net, most of them do not call getenv, because the net subsystem is responsible to do this. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: off...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Add support for ASIX's AX88783 ethernet chip
Than you Stefano.
> Date: Wed, 2 Feb 2011 19:02:11 +0100
> From: sba...@denx.de
> To: lg...@hotmail.com
> CC: u-boot@lists.denx.de; w...@denx.de
> Subject: Re: [U-Boot] [PATCH] Add support for ASIX's AX88783 ethernet chip
>
> On 01/31/2011 06:42 PM, Joe Xue wrote:
> > for more information about this chip, please check:
> > http://www.asix.com.tw/products.php?op=pItemdetail&PItemID=98;65;86&PLine=65
> >
> > Signed-off-by: Joe Xue
> >
>
> Please add a version number to your patch to make easier tracking which
> is your last version.
>
Will add it.
> Do not forget to add always the net Maintainer to CC (Wolfgang Denk), I
> added him now.
>
Not exactly understand your meaning. You mean I should add wd as maintainer to
my code or just add him in mail.
> > --- /dev/null
> > +++ b/drivers/net/ax88783.c
> > @@ -0,0 +1,297 @@
> > +/*
> > + *
>
> You should drop this line
>
will drop it.
> > +
> > +static int ax88183_phy_initial(struct eth_device *dev)
>
> You forget to replace the name of the function. It has still ax88183_
>
will change, sorry for it.
> > + /* phy init */
> > + tmp = readl(®->pcr);
> > + tmp |= PCR_PHY0_RESET_CLEAR;
> > +
> > + writel(tmp, ®->pcr);
> > + udelay(10);
>
> you already explained why you need such a long delay. It is not bad to
> add your explanation as comment here, so everyone knows your answer.
>
will do.
> > +static void ax88783_halt(struct eth_device *dev)
> > +{
> > + unsigned int tmp;
> > + struct ax88783_reg *reg = (struct ax88783_reg *)dev->iobase;
> > + tmp = readl(®->pcr);
> > + writel((tmp | PCR_LOOP_BACK), ®->pcr);
> > +}
>
> From the name it seems you set the controller in loopback, instead of
> disabling it. Is it correct ?
>
mmn. I just make it can't receive the data outside.The other way is make it
into sleep mode.
> > +
> > + res = eth_getenv_enetaddr("ethaddr", dev->enetaddr);
> > + if (!res) {
> > + puts("Please set your MAC address!");
> > + free(dev);
> > + return 0;
> > + }
>
> This is wrong. A network driver should not call directly
> eth_getenv_enetaddr, and you do not need. If you want to check the mac
> addrsss, use is_valid_ether_addr() inside ax88783_init() before copying
> the mac to the hardware.
>
I refer to the newest net driver patch ftgmac100.c, it uses this function to
getmac address from environmental setting. and I checked the code
eth_getenv_enetaddralso call the is_valid_ether_addr().
Anyway, will change it according to your advice.
> > +
> > + res = ax88183_phy_initial(dev);
>
> Name must be changed.
>
will change.
> > diff --git a/drivers/net/ax88783.h b/drivers/net/ax88783.h
> > new file mode 100644
> > index 000..09ac9ed
> > --- /dev/null
> > +++ b/drivers/net/ax88783.h
> > @@ -0,0 +1,100 @@
> > +/*
> > + *
>
> As explained, all headers start with copyright on the second line. Drop
> this line.
>
Yes, thank you for your patience :-)
> Best regards,
> Stefano Babic
Best wishes,
Joe
>
> --
> =
> DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: off...@denx.de
> =
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[U-Boot] multiple serial in evaluation board
Hello, I would like to configure multiple serial (UART's) in the OMAP l-138 evaluation board (da850evm). I thought that in the serial section of the da850evm.h I should only add CONFIG_SERIAL_MULTI, but then I got compilation problem: \common\serial.c " #error No default console ". It also seem that this file is only being compiled when using the CONFIG_SERIAL_MULTI flag. I can also add that I thought it is better to use that flag becuase I want to use the functions in \drivers\serial\serial.c such as serial_getc_dev instead of _serial_getc, but I see that inorder to use this function I need to define this flag (CONFIG_SERIAL_MULTI) Should this flag be used whenever using more then one UART ? I appreciate your help! Ran ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] [NEXT] Make STANDALONE_LOAD_ADDR configurable per board
Rename STANDALONE_LOAD_ADDR into CONFIG_STANDALONE_LOAD_ADDR and allow that the architecture-specific default value gets overwritten by defining the value in the board header file. Signed-off-by: Wolfgang Denk Cc: Mike Frysinger Cc: Shinya Kuribayashi Cc: Daniel Hellstrom Cc: Tsi Chung Liew Cc: Nobuhiro Iwamatsu --- Note that some architectures (blackfin, coldfire, mips, sh, sparc) misuse the CONFIG_STANDALONE_LOAD_ADDR variable to not only specify the load address (as the name suggests), but also to supply additional linker options: arch/blackfin/config.mk:CONFIG_STANDALONE_LOAD_ADDR ?= 0x1000 -m elf32bfin arch/m68k/config.mk:CONFIG_STANDALONE_LOAD_ADDR ?= 0x2 -L $(clibdir) arch/mips/config.mk:CONFIG_STANDALONE_LOAD_ADDR ?= 0x8020 -T mips.lds arch/sh/config.mk:CONFIG_STANDALONE_LOAD_ADDR += -EB arch/sparc/config.mk:CONFIG_STANDALONE_LOAD_ADDR ?= 0x -L $(gcclibdir) -T sparc.lds Please clean this up! Thanks -- wd README |8 arch/arm/config.mk |8 +++- arch/avr32/config.mk |2 +- arch/blackfin/config.mk |2 +- arch/i386/config.mk |2 +- arch/m68k/config.mk |2 +- arch/microblaze/config.mk|2 +- arch/mips/config.mk |2 +- arch/powerpc/config.mk |2 +- arch/sh/config.mk|4 ++-- arch/sparc/config.mk |2 +- examples/standalone/Makefile |2 +- include/configs/omap2420h4.h |2 ++ 13 files changed, 24 insertions(+), 16 deletions(-) diff --git a/README b/README index 755d17c..e8567c7 100644 --- a/README +++ b/README @@ -1952,6 +1952,14 @@ The following options need to be configured: example, some LED's) on your board. At the moment, the following checkpoints are implemented: +- Standalone program support: + CONFIG_STANDALONE_LOAD_ADDR + + This option allows to define board specific values + for the address where standalone program gets loaded, + thus overwriting the architecutre dependent default + settings. + Legacy uImage format: Arg Where When diff --git a/arch/arm/config.mk b/arch/arm/config.mk index a6a4742..fcc26a2 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -23,13 +23,11 @@ CROSS_COMPILE ?= arm-linux- -ifeq ($(BOARD),omap2420h4) -STANDALONE_LOAD_ADDR = 0x8030 -else +ifndef CONFIG_STANDALONE_LOAD_ADDR ifeq ($(SOC),omap3) -STANDALONE_LOAD_ADDR = 0x8030 +CONFIG_STANDALONE_LOAD_ADDR = 0x8030 else -STANDALONE_LOAD_ADDR = 0xc10 +CONFIG_STANDALONE_LOAD_ADDR = 0xc10 endif endif diff --git a/arch/avr32/config.mk b/arch/avr32/config.mk index 1121ca1..9488c49 100644 --- a/arch/avr32/config.mk +++ b/arch/avr32/config.mk @@ -23,7 +23,7 @@ CROSS_COMPILE ?= avr32-linux- -STANDALONE_LOAD_ADDR = 0x +CONFIG_STANDALONE_LOAD_ADDR ?= 0x PLATFORM_RELFLAGS += -ffixed-r5 -fPIC -mno-init-got -mrelax PLATFORM_LDFLAGS += --relax diff --git a/arch/blackfin/config.mk b/arch/blackfin/config.mk index 0cba294..441c23e 100644 --- a/arch/blackfin/config.mk +++ b/arch/blackfin/config.mk @@ -23,7 +23,7 @@ CROSS_COMPILE ?= bfin-uclinux- -STANDALONE_LOAD_ADDR = 0x1000 -m elf32bfin +CONFIG_STANDALONE_LOAD_ADDR ?= 0x1000 -m elf32bfin CONFIG_BFIN_BOOT_MODE := $(strip $(subst ",,$(CONFIG_BFIN_BOOT_MODE))) diff --git a/arch/i386/config.mk b/arch/i386/config.mk index 3fb97c1..27ac3de 100644 --- a/arch/i386/config.mk +++ b/arch/i386/config.mk @@ -23,7 +23,7 @@ CROSS_COMPILE ?= i386-linux- -STANDALONE_LOAD_ADDR = 0x4 +CONFIG_STANDALONE_LOAD_ADDR ?= 0x4 PLATFORM_CPPFLAGS += -fno-strict-aliasing PLATFORM_CPPFLAGS += -Wstrict-prototypes diff --git a/arch/m68k/config.mk b/arch/m68k/config.mk index 749c389..863f3dd 100644 --- a/arch/m68k/config.mk +++ b/arch/m68k/config.mk @@ -24,7 +24,7 @@ CROSS_COMPILE ?= m68k-elf- clibdir = $(shell dirname `$(CC) $(CFLAGS) -print-file-name=libc.a`) -STANDALONE_LOAD_ADDR = 0x2 -L $(clibdir) +CONFIG_STANDALONE_LOAD_ADDR ?= 0x2 -L $(clibdir) PLATFORM_CPPFLAGS += -DCONFIG_M68K -D__M68K__ PLATFORM_LDFLAGS += -n diff --git a/arch/microblaze/config.mk b/arch/microblaze/config.mk index c3c9f95..abea70b 100644 --- a/arch/microblaze/config.mk +++ b/arch/microblaze/config.mk @@ -26,6 +26,6 @@ CROSS_COMPILE ?= mb- -STANDALONE_LOAD_ADDR = 0x80F0 +CONFIG_STANDALONE_LOAD_ADDR ?= 0x80F0 PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__ diff --git a/arch/mips/config.mk b/arch/mips/config.mk index aa06761..318d34b 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -23,7 +23,7 @@ CROSS_COMPILE ?= mips_4KC- -STANDALONE_LOAD_ADDR = 0x8020 -T mips.lds +CONFIG_STANDALONE_LOAD_ADDR ?= 0x8020 -T mips.lds PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk index 64191c7..fa24131 100644 --- a/arch/powerpc
[U-Boot] [PATCH 19/32] eNET: General code cleanup
Signed-off-by: Graeme Russ
---
board/eNET/eNET.c | 17 +--
board/eNET/eNET_start.S |7 -
include/configs/eNET.h | 290 ---
3 files changed, 129 insertions(+), 185 deletions(-)
diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
index 8e11acf..e64a395 100644
--- a/board/eNET/eNET.c
+++ b/board/eNET/eNET.c
@@ -35,16 +35,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#undef SC520_CDP_DEBUG
-
-#ifdef SC520_CDP_DEBUG
-#definePRINTF(fmt,args...) printf (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
-
-unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
-
static void enet_timer_isr(void);
static void enet_toggle_run_led(void);
static void enet_setup_pars(void);
@@ -199,22 +189,23 @@ int last_stage_init(void)
outb(0x00, LED_LATCH_ADDRESS);
- register_timer_isr (enet_timer_isr);
+ register_timer_isr(enet_timer_isr);
printf("Serck Controls eNET\n");
return 0;
}
-ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
{
if (banknum == 0) { /* non-CFI boot flash */
info->portwidth = FLASH_CFI_8BIT;
info->chipwidth = FLASH_CFI_BY8;
info->interface = FLASH_CFI_X8;
return 1;
- } else
+ } else {
return 0;
+ }
}
int board_eth_init(bd_t *bis)
diff --git a/board/eNET/eNET_start.S b/board/eNET/eNET_start.S
index 137fe41..1b3d289 100644
--- a/board/eNET/eNET_start.S
+++ b/board/eNET/eNET_start.S
@@ -29,10 +29,3 @@ early_board_init:
/* No 32-bit board specific initialisation */
jmp early_board_init_ret
-.globl cpu_halt_asm
-cpu_halt_asm:
- movb$0x0f, %al
- movw$LED_LATCH_ADDRESS, %dx
- outb%al, %dx
- hlt
- jmp cpu_halt_asm
diff --git a/include/configs/eNET.h b/include/configs/eNET.h
index faeb52f..b018f8b 100644
--- a/include/configs/eNET.h
+++ b/include/configs/eNET.h
@@ -30,123 +30,113 @@
#define __CONFIG_H
/*
- * Stuff still to be dealt with -
- */
-#define CONFIG_RTC_MC146818
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
-
-/*
* High Level Configuration Options
* (easy to change)
*/
-#define DEBUG_PARSER
-
-#define CONFIG_X86 1 /* Intel X86 CPU */
-#define CONFIG_SYS_SC520 1 /* AMD SC520 */
+#define CONFIG_X86
+#define CONFIG_SYS_SC520
#define CONFIG_SYS_SC520_SSI
-#define CONFIG_SHOW_BOOT_PROGRESS 1
-#define CONFIG_LAST_STAGE_INIT 1
+#define CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_LAST_STAGE_INIT
-/*
- * If CONFIG_HW_WATCHDOG is not defined, the watchdog jumper on the
+/*---
+ * Watchdog Configuration
+ * NOTE: If CONFIG_HW_WATCHDOG is NOT defined, the watchdog jumper on the
* bottom (processor) board MUST be removed!
*/
#undef CONFIG_WATCHDOG
#define CONFIG_HW_WATCHDOG
- /*---
- * Serial Configuration
- */
+/*---
+ * Real Time Clock Configuration
+ */
+#define CONFIG_RTC_MC146818
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
+
+/*---
+ * Serial Configuration
+ */
#define CONFIG_SERIAL_MULTI
-#define CONFIG_CONS_INDEX 1
+#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE1
-#define CONFIG_SYS_NS16550_CLK 1843200
-#define CONFIG_BAUDRATE9600
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1UART0_BASE
-#define CONFIG_SYS_NS16550_COM2UART1_BASE
-#define CONFIG_SYS_NS16550_COM3(0x1000 + UART0_BASE)
-#define CONFIG_SYS_NS16550_COM4(0x1000 + UART1_BASE)
+#define CONFIG_SYS_NS16550_REG_SIZE1
+#define CONFIG_SYS_NS16550_CLK 1843200
+#define CONFIG_BAUDRATE9600
+#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \
+9600, 19200, 38400, 115200}
+#define CONFIG_SYS_NS16550_COM1UART0_BASE
+#define CONFIG_SYS_NS16550_COM2UART1_BASE
+#define CONFIG_SYS_NS16550_COM3(0x1000 + UART0_BASE)
+#define CONFIG_SYS_NS16550_COM4(0x1000 + UART1_BASE)
#define CONFIG_SYS_NS16550_PORT_MAPPED
- /*---
- * Video Configuration
- */
-#undef CONFIG_VIDEO/* No Video Hardware */
-#undef CONFIG_CFB_CONSOL
[U-Boot] [PATCH 18/32] eNET: Rearrange PAR assignments
Signed-off-by: Graeme Russ
---
board/eNET/eNET.c | 61 ---
include/configs/eNET.h | 15 ---
2 files changed, 46 insertions(+), 30 deletions(-)
diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
index 546406a..8e11acf 100644
--- a/board/eNET/eNET.c
+++ b/board/eNET/eNET.c
@@ -47,6 +47,7 @@ unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
static void enet_timer_isr(void);
static void enet_toggle_run_led(void);
+static void enet_setup_pars(void);
/*
* Miscellaneous platform dependent initializations
@@ -89,21 +90,7 @@ int board_early_init_f(void)
/* Clear FPGA program mode */
writew(CONFIG_SYS_ENET_FPGA_PROG, &sc520_mmcr->pioset31_16);
- /* Configure Programmable Address Regions */
- writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[2]);
- writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[3]);
- writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[4]);
- writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[5]);
- writel(CONFIG_SYS_SC520_SDRAM_PAR, &sc520_mmcr->par[6]);
- writel(CONFIG_SYS_SC520_SF1_PAR, &sc520_mmcr->par[7]);
- writel(CONFIG_SYS_SC520_SF2_PAR, &sc520_mmcr->par[8]);
- writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[9]);
- writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[10]);
- writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[11]);
- writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[12]);
- writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[13]);
-/* writel(CONFIG_SYS_SC520_BOOTCS_PAR, &sc520_mmcr->par14); */
-/* writel(CONFIG_SYS_SC520_LLIO_PAR, &sc520_mmcr->par15); */
+ enet_setup_pars();
/* Disable Watchdog */
writew(0x, &sc520_mmcr->wdtmrctl);
@@ -128,6 +115,50 @@ int board_early_init_f(void)
return 0;
}
+static void enet_setup_pars(void)
+{
+ /*
+* PARs 11 and 12 are 2MB SRAM @ 0x1900
+*
+* These are setup now because older version of U-Boot have them
+* mapped to a different PAR which gets clobbered which prevents
+* using SRAM for warm-booting a new image
+*/
+ writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[11]);
+ writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[12]);
+
+ /* PARs 0 and 1 are Compact Flash slots (4kB each) */
+ writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[0]);
+ writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[1]);
+
+ /* PAR 2 is used for Cache-As-RAM */
+
+ /*
+* PARs 5 through 8 are additional NS16550 UARTS
+* 8 bytes each @ 0x013f8, 0x012f8, 0x011f8 and 0x010f8
+*/
+ writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[5]);
+ writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[6]);
+ writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[7]);
+ writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[8]);
+
+ /* PARs 9 and 10 are 32MB StrataFlash @ 0x1000 */
+ writel(CONFIG_SYS_SC520_SF1_PAR, &sc520_mmcr->par[9]);
+ writel(CONFIG_SYS_SC520_SF2_PAR, &sc520_mmcr->par[10]);
+
+ /* PAR 13 is 4kB DPRAM @ 0x1810 (implemented in FPGA) */
+ writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[13]);
+
+ /*
+* PAR 14 is Low Level I/O (LEDs, Hex Switches etc)
+* Already configured in board_init16 (eNET_start16.S)
+*
+* PAR 15 is Boot ROM
+* Already configured in board_init16 (eNET_start16.S)
+*/
+}
+
+
int board_early_init_r(void)
{
/* CPU Speed to 100MHz */
diff --git a/include/configs/eNET.h b/include/configs/eNET.h
index efdc168..faeb52f 100644
--- a/include/configs/eNET.h
+++ b/include/configs/eNET.h
@@ -614,21 +614,6 @@
*/
#define CONFIG_SYS_SC520_DPRAM_PAR 0x50018100
-/*---
- * PAR for SDRAM - 128MB @ 0x
- * 111 0 0 0 1 111 00 }- 0xe3ffc000
- * \ / | | | | \+/ \-+--/
- * | | | | | |+-- Start at 0x
- * | | | | | +--- 128MB Region Size
- * | | | | | ((2047 + 1) * 64kB)
- * | | | | +-- 64kB Page Size
- * | | | + Writes Enabled
- * | | +-- Caching Enabled
- * | + Execution Enabled
- * +--- SDRAM
- */
-#define CONFIG_SYS_SC520_SDRAM_PAR 0xe3ffc000
-
#ifndef __ASSEMBLER__
extern unsigned long ip;
--
1.7.1.422.g049e9
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[U-Boot] [PATCH 16/32] eNET: Add RTC support to eNET
The SC520 has an inbuilt MC146818 - Enable it for the eNET board Signed-off-by: Graeme Russ --- drivers/rtc/mc146818.c |6 ++ include/configs/eNET.h |2 ++ 2 files changed, 8 insertions(+), 0 deletions(-) diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c index ac4eb6a..59f6765 100644 --- a/drivers/rtc/mc146818.c +++ b/drivers/rtc/mc146818.c @@ -31,6 +31,12 @@ #include #include +#ifdef __I386__ +#include +#define in8(p) inb(p) +#define out8(p, v) outb(v, p) +#endif + #if defined(CONFIG_CMD_DATE) static uchar rtc_read (uchar reg); diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 78cab29..082f681 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -33,6 +33,7 @@ * Stuff still to be dealt with - */ #define CONFIG_RTC_MC146818 +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 /* * High Level Configuration Options @@ -91,6 +92,7 @@ #define CONFIG_CMD_BDI /* bdinfo */ #define CONFIG_CMD_BOOTD /* bootd*/ #define CONFIG_CMD_CONSOLE /* coninfo */ +#define CONFIG_CMD_DATE #define CONFIG_CMD_ECHO/* echo arguments */ #define CONFIG_CMD_FLASH /* flinfo, erase, protect */ #define CONFIG_CMD_FPGA/* FPGA configuration Support */ -- 1.7.1.422.g049e9 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 25/32] x86: Move test for cold boot into init functions
Signed-off-by: Graeme Russ
---
arch/i386/cpu/sc520/sc520.c |7 ---
arch/i386/lib/board.c | 17 +++--
2 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c
index d5597ca..e5dcac6 100644
--- a/arch/i386/cpu/sc520/sc520.c
+++ b/arch/i386/cpu/sc520/sc520.c
@@ -45,15 +45,16 @@ int cpu_init_f(void)
gd->cpu_clk = 1;
}
-
/* wait at least one millisecond */
asm("movl $0x2000, %%ecx\n"
"0: pushl %%ecx\n"
"popl %%ecx\n"
"loop 0b\n": : : "ecx");
- /* turn on the SDRAM write buffer */
- writeb(0x11, &sc520_mmcr->dbctl);
+ if (gd->flags & GD_FLG_COLD_BOOT) {
+ /* turn on the SDRAM write buffer */
+ writeb(0x11, &sc520_mmcr->dbctl);
+ }
return x86_cpu_init_f();
}
diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c
index 1d47a55..73aaadc 100644
--- a/arch/i386/lib/board.c
+++ b/arch/i386/lib/board.c
@@ -207,16 +207,13 @@ void board_init_f(ulong boot_flags)
dest_addr -= (bss_end - text_start);
rel_offset = text_start - dest_addr;
- /* Perform low-level initialization only when cold booted */
- if (gd->flags & GD_FLG_COLD_BOOT) {
- /* First stage CPU initialization */
- if (cpu_init_f() != 0)
- hang();
-
- /* First stage Board initialization */
- if (board_early_init_f() != 0)
- hang();
- }
+ /* First stage CPU initialization */
+ if (cpu_init_f() != 0)
+ hang();
+
+ /* First stage Board initialization */
+ if (board_early_init_f() != 0)
+ hang();
/* Copy U-Boot into RAM */
dst_addr = (ulong *)dest_addr;
--
1.7.1.422.g049e9
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[U-Boot] [PATCH 32/32] eNET: Move initial Global Data into CAR
Signed-off-by: Graeme Russ --- include/configs/eNET.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 50ee73e..0358b97 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -169,7 +169,7 @@ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* Address of temporary Global Data */ -#define CONFIG_SYS_INIT_GD_ADDR0x1904 +#define CONFIG_SYS_INIT_GD_ADDRCONFIG_SYS_CAR_ADDR /* allow to overwrite serial and ethaddr */ -- 1.7.1.422.g049e9 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 30/32] x86: Convert board_init_f to use an init_sequence
Signed-off-by: Graeme Russ
---
arch/i386/lib/board.c | 70
1 files changed, 29 insertions(+), 41 deletions(-)
diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c
index 4751e49..0c37c23 100644
--- a/arch/i386/lib/board.c
+++ b/arch/i386/lib/board.c
@@ -156,7 +156,28 @@ static void display_flash_config (ulong size)
*/
typedef int (init_fnc_t) (void);
-init_fnc_t *init_sequence[] = {
+static int calculate_relocation_address(void);
+static int copy_uboot_to_ram(void);
+static int clear_bss(void);
+static int do_elf_reloc_fixups(void);
+
+init_fnc_t *init_sequence_f[] = {
+ cpu_init_f,
+ board_early_init_f,
+ env_init,
+ init_baudrate,
+ serial_init,
+ console_init_f,
+ dram_init_f,
+ calculate_relocation_address,
+ copy_uboot_to_ram,
+ clear_bss,
+ do_elf_reloc_fixups,
+
+ NULL,
+};
+
+init_fnc_t *init_sequence_r[] = {
cpu_init_r, /* basic cpu dependent setup */
board_early_init_r, /* basic board dependent setup */
dram_init, /* configure available RAM banks */
@@ -235,41 +256,12 @@ static int do_elf_reloc_fixups(void)
*/
void board_init_f(ulong boot_flags)
{
- /* First stage CPU initialization */
- if (cpu_init_f() != 0)
- hang();
-
- /* First stage Board initialization */
- if (board_early_init_f() != 0)
- hang();
-
- if (env_init() != 0)
- hang();
-
- if (init_baudrate() != 0)
- hang();
-
- if (serial_init() != 0)
- hang();
-
- if (console_init_f() != 0)
- hang();
-
- if (dram_init_f() != 0)
- hang();
-
- if (calculate_relocation_address() != 0)
- hang();
-
- /* Copy U-Boot into RAM */
- if (copy_uboot_to_ram() != 0)
- hang();
-
- if (clear_bss() != 0)
- hang();
+ init_fnc_t **init_fnc_ptr;
- if (do_elf_reloc_fixups() != 0)
- hang();
+ for (init_fnc_ptr = init_sequence_f; *init_fnc_ptr; ++init_fnc_ptr) {
+ if ((*init_fnc_ptr)() != 0)
+ hang();
+ }
gd->flags |= GD_FLG_RELOC;
@@ -283,7 +275,6 @@ void board_init_f(ulong boot_flags)
void board_init_r(gd_t *id, ulong dest_addr)
{
char *s;
- int i;
ulong size;
static bd_t bd_data;
static gd_t gd_data;
@@ -307,12 +298,9 @@ void board_init_r(gd_t *id, ulong dest_addr)
mem_malloc_initulong)dest_addr - CONFIG_SYS_MALLOC_LEN)+3)&~3,
CONFIG_SYS_MALLOC_LEN);
- for (init_fnc_ptr = init_sequence, i=0; *init_fnc_ptr; ++init_fnc_ptr,
i++) {
- show_boot_progress(0xa130|i);
-
- if ((*init_fnc_ptr)() != 0) {
+ for (init_fnc_ptr = init_sequence_r; *init_fnc_ptr; ++init_fnc_ptr) {
+ if ((*init_fnc_ptr)() != 0)
hang ();
- }
}
show_boot_progress(0x23);
--
1.7.1.422.g049e9
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[U-Boot] [PATCH 31/32] sc520: Release CAR and enable caching
Signed-off-by: Graeme Russ
---
arch/i386/cpu/sc520/sc520.c | 16 +++-
1 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c
index e5dcac6..d0c313b 100644
--- a/arch/i386/cpu/sc520/sc520.c
+++ b/arch/i386/cpu/sc520/sc520.c
@@ -51,14 +51,20 @@ int cpu_init_f(void)
"popl %%ecx\n"
"loop 0b\n": : : "ecx");
- if (gd->flags & GD_FLG_COLD_BOOT) {
- /* turn on the SDRAM write buffer */
- writeb(0x11, &sc520_mmcr->dbctl);
- }
-
return x86_cpu_init_f();
}
+int cpu_init_r(void)
+{
+ /* Disable the PAR used for CAR */
+ writel(0x000, &sc520_mmcr->par[2]);
+
+ /* turn on the SDRAM write buffer */
+ writeb(0x11, &sc520_mmcr->dbctl);
+
+ return x86_cpu_init_r();
+}
+
#ifdef CONFIG_SYS_SC520_RESET
void reset_cpu(ulong addr)
{
--
1.7.1.422.g049e9
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[U-Boot] [PATCH 29/32] x86: Rearrange function calls in board_init_f
Signed-off-by: Graeme Russ
---
arch/i386/lib/board.c | 16
1 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c
index 44e871b..4751e49 100644
--- a/arch/i386/lib/board.c
+++ b/arch/i386/lib/board.c
@@ -235,6 +235,14 @@ static int do_elf_reloc_fixups(void)
*/
void board_init_f(ulong boot_flags)
{
+ /* First stage CPU initialization */
+ if (cpu_init_f() != 0)
+ hang();
+
+ /* First stage Board initialization */
+ if (board_early_init_f() != 0)
+ hang();
+
if (env_init() != 0)
hang();
@@ -253,14 +261,6 @@ void board_init_f(ulong boot_flags)
if (calculate_relocation_address() != 0)
hang();
- /* First stage CPU initialization */
- if (cpu_init_f() != 0)
- hang();
-
- /* First stage Board initialization */
- if (board_early_init_f() != 0)
- hang();
-
/* Copy U-Boot into RAM */
if (copy_uboot_to_ram() != 0)
hang();
--
1.7.1.422.g049e9
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[U-Boot] [PATCH 28/32] x86: Split board_init_f() into init_fnc_t compatible functions
Signed-off-by: Graeme Russ
---
arch/i386/include/asm/global_data.h | 12 +++-
arch/i386/lib/board.c | 111 +--
2 files changed, 74 insertions(+), 49 deletions(-)
diff --git a/arch/i386/include/asm/global_data.h
b/arch/i386/include/asm/global_data.h
index cd067f5..f8a16d6 100644
--- a/arch/i386/include/asm/global_data.h
+++ b/arch/i386/include/asm/global_data.h
@@ -46,6 +46,8 @@ typedef struct global_data {
unsigned long env_valid; /* Checksum of Environment valid? */
unsigned long cpu_clk;/* CPU clock in Hz! */
unsigned long bus_clk;
+ unsigned long relocaddr; /* Start address of U-Boot in RAM */
+ unsigned long start_addr_sp; /* start_addr_stackpointer */
phys_size_t ram_size; /* RAM size */
unsigned long reset_status; /* reset status register at boot */
void**jt; /* jump table */
@@ -67,11 +69,13 @@ extern gd_t *gd;
#define GD_ENV_VALID 7
#define GD_CPU_CLK 8
#define GD_BUS_CLK 9
-#define GD_RAM_SIZE10
-#define GD_RESET_STATUS11
-#define GD_JT 12
+#define GD_RELOC_ADDR 10
+#define GD_START_ADDR_SP 11
+#define GD_RAM_SIZE12
+#define GD_RESET_STATUS13
+#define GD_JT 14
-#define GD_SIZE13
+#define GD_SIZE15
/*
* Global Data Flags
diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c
index 02cb67d..44e871b 100644
--- a/arch/i386/lib/board.c
+++ b/arch/i386/lib/board.c
@@ -170,30 +170,71 @@ init_fnc_t *init_sequence[] = {
gd_t *gd;
-/*
- * Load U-Boot into RAM, initialize BSS, perform relocation adjustments
- */
-void board_init_f(ulong boot_flags)
+static int calculate_relocation_address(void)
{
void *text_start = &__text_start;
- void *data_end = &__data_end;
- void *rel_dyn_start = &__rel_dyn_start;
- void *rel_dyn_end = &__rel_dyn_end;
+ void *bss_end = &__bss_end;
+ void *dest_addr;
+ ulong rel_offset;
+
+ /* Calculate destination RAM Address and relocation offset */
+ dest_addr = (void *)gd->ram_size;
+ dest_addr -= CONFIG_SYS_STACK_SIZE;
+ dest_addr -= (bss_end - text_start);
+ rel_offset = dest_addr - text_start;
+
+ gd->start_addr_sp = gd->ram_size;
+ gd->relocaddr = (ulong)dest_addr;
+ gd->reloc_off = rel_offset;
+
+ return 0;
+}
+
+static int copy_uboot_to_ram(void)
+{
+ ulong *dst_addr = (ulong *)gd->relocaddr;
+ ulong *src_addr = (ulong *)&__text_start;
+ ulong *end_addr = (ulong *)&__data_end;
+
+ while (src_addr < end_addr)
+ *dst_addr++ = *src_addr++;
+
+ return 0;
+}
+
+static int clear_bss(void)
+{
void *bss_start = &__bss_start;
void *bss_end = &__bss_end;
- ulong *dst_addr;
- ulong *src_addr;
- ulong *end_addr;
+ ulong *dst_addr = (ulong *)(bss_start + gd->reloc_off);
+ ulong *end_addr = (ulong *)(bss_end + gd->reloc_off);;
- void *addr_sp;
- void *dest_addr;
- ulong rel_offset;
- Elf32_Rel *re_src;
- Elf32_Rel *re_end;
+ while (dst_addr < end_addr)
+ *dst_addr++ = 0x;
+
+ return 0;
+}
- gd->flags = boot_flags;
+static int do_elf_reloc_fixups(void)
+{
+ Elf32_Rel *re_src = (Elf32_Rel *)(&__rel_dyn_start);
+ Elf32_Rel *re_end = (Elf32_Rel *)(&__rel_dyn_end);
+
+ do {
+ if (re_src->r_offset >= CONFIG_SYS_TEXT_BASE)
+ if (*(Elf32_Addr *)(re_src->r_offset + gd->reloc_off)
>= CONFIG_SYS_TEXT_BASE)
+ *(Elf32_Addr *)(re_src->r_offset +
gd->reloc_off) += gd->reloc_off;
+ } while (re_src++ < re_end);
+
+ return 0;
+}
+/*
+ * Load U-Boot into RAM, initialize BSS, perform relocation adjustments
+ */
+void board_init_f(ulong boot_flags)
+{
if (env_init() != 0)
hang();
@@ -209,12 +250,8 @@ void board_init_f(ulong boot_flags)
if (dram_init_f() != 0)
hang();
- /* Calculate destination RAM Address and relocation offset */
- dest_addr = (void *)gd->ram_size;
- addr_sp = dest_addr;
- dest_addr -= CONFIG_SYS_STACK_SIZE;
- dest_addr -= (bss_end - text_start);
- rel_offset = dest_addr - text_start;
+ if (calculate_relocation_address() != 0)
+ hang();
/* First stage CPU initialization */
if (cpu_init_f() != 0)
@@ -225,35 +262,19 @@ void board_init_f(ulong boot_flags)
hang();
/* Copy U-Boot into RAM */
- dst_addr = (ulong *)dest_addr;
- src_addr = (ulong *)(text_start + gd->load_off);
- end_addr = (ulong *)(data_end + gd->load_off);
-
- while (src_addr < end_addr)
- *dst_addr++ = *src_addr++;
-
- /* Clear BSS */
- dst_addr = (ulong *)(bss_start + rel_of
[U-Boot] [PATCH 27/32] x86: Fix incorrect usage of relocation offset
x86 has always used relocation offset in the opposite sense to the ELF
standard - Fix this
Signed-off-by: Graeme Russ
---
arch/i386/cpu/start.S |2 +-
arch/i386/lib/board.c | 10 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/i386/cpu/start.S b/arch/i386/cpu/start.S
index fd018bf..0031389 100644
--- a/arch/i386/cpu/start.S
+++ b/arch/i386/cpu/start.S
@@ -120,7 +120,7 @@ relocate_code:
/* Setup call address of in-RAM copy of board_init_r() */
movl$board_init_r, %ebp
- subl(GD_RELOC_OFF * 4)(%edx), %ebp
+ addl(GD_RELOC_OFF * 4)(%edx), %ebp
/* Setup parameters to board_init_r() */
movl%edx, %eax
diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c
index 1a9..02cb67d 100644
--- a/arch/i386/lib/board.c
+++ b/arch/i386/lib/board.c
@@ -214,7 +214,7 @@ void board_init_f(ulong boot_flags)
addr_sp = dest_addr;
dest_addr -= CONFIG_SYS_STACK_SIZE;
dest_addr -= (bss_end - text_start);
- rel_offset = text_start - dest_addr;
+ rel_offset = dest_addr - text_start;
/* First stage CPU initialization */
if (cpu_init_f() != 0)
@@ -233,8 +233,8 @@ void board_init_f(ulong boot_flags)
*dst_addr++ = *src_addr++;
/* Clear BSS */
- dst_addr = (ulong *)(bss_start - rel_offset);
- end_addr = (ulong *)(bss_end - rel_offset);
+ dst_addr = (ulong *)(bss_start + rel_offset);
+ end_addr = (ulong *)(bss_end + rel_offset);
while (dst_addr < end_addr)
*dst_addr++ = 0x;
@@ -245,8 +245,8 @@ void board_init_f(ulong boot_flags)
do {
if (re_src->r_offset >= CONFIG_SYS_TEXT_BASE)
- if (*(Elf32_Addr *)(re_src->r_offset - rel_offset) >=
CONFIG_SYS_TEXT_BASE)
- *(Elf32_Addr *)(re_src->r_offset - rel_offset)
-= rel_offset;
+ if (*(Elf32_Addr *)(re_src->r_offset + rel_offset) >=
CONFIG_SYS_TEXT_BASE)
+ *(Elf32_Addr *)(re_src->r_offset + rel_offset)
+= rel_offset;
} while (re_src++ < re_end);
gd->reloc_off = rel_offset;
--
1.7.1.422.g049e9
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[U-Boot] [PATCH 26/32] x86: Move console initialisation into board_init_f
Signed-off-by: Graeme Russ
---
arch/i386/lib/board.c | 15 ---
1 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c
index 73aaadc..1a9 100644
--- a/arch/i386/lib/board.c
+++ b/arch/i386/lib/board.c
@@ -162,9 +162,6 @@ init_fnc_t *init_sequence[] = {
dram_init, /* configure available RAM banks */
interrupt_init, /* set up exceptions */
timer_init,
- env_init, /* initialize environment */
- init_baudrate, /* initialze baudrate settings */
- serial_init,/* serial communications setup */
display_banner,
display_dram_config,
@@ -197,6 +194,18 @@ void board_init_f(ulong boot_flags)
gd->flags = boot_flags;
+ if (env_init() != 0)
+ hang();
+
+ if (init_baudrate() != 0)
+ hang();
+
+ if (serial_init() != 0)
+ hang();
+
+ if (console_init_f() != 0)
+ hang();
+
if (dram_init_f() != 0)
hang();
--
1.7.1.422.g049e9
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[U-Boot] [PATCH 24/32] x86: Move call to dram_init_f into board_init_f
Signed-off-by: Graeme Russ --- arch/i386/cpu/start.S |3 --- arch/i386/include/asm/u-boot-i386.h |1 + arch/i386/lib/board.c |3 +++ 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/i386/cpu/start.S b/arch/i386/cpu/start.S index 77f0332..fd018bf 100644 --- a/arch/i386/cpu/start.S +++ b/arch/i386/cpu/start.S @@ -93,9 +93,6 @@ car_init_ret: subl$1b, %ecx movl%ecx, (GD_LOAD_OFF * 4)(%ebp) - /* size memory */ - calldram_init_f - /* Set parameter to board_init_f() to boot flags */ movl(GD_FLAGS * 4)(%ebp), %eax diff --git a/arch/i386/include/asm/u-boot-i386.h b/arch/i386/include/asm/u-boot-i386.h index 80db52f..7b39bd2 100644 --- a/arch/i386/include/asm/u-boot-i386.h +++ b/arch/i386/include/asm/u-boot-i386.h @@ -37,6 +37,7 @@ int register_timer_isr (timer_fnc_t *isr_func); /* Architecture specific - can be in arch/i386/cpu/, arch/i386/lib/, or $(BOARD)/ */ int timer_init(void); +int dram_init_f(void); /* cpu/.../interrupts.c */ int cpu_init_interrupts(void); diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c index e3869d6..1d47a55 100644 --- a/arch/i386/lib/board.c +++ b/arch/i386/lib/board.c @@ -197,6 +197,9 @@ void board_init_f(ulong boot_flags) gd->flags = boot_flags; + if (dram_init_f() != 0) + hang(); + /* Calculate destination RAM Address and relocation offset */ dest_addr = (void *)gd->ram_size; addr_sp = dest_addr; -- 1.7.1.422.g049e9 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 23/32] x86: Defer setup of final stack
Signed-off-by: Graeme Russ --- arch/i386/cpu/start.S | 44 +--- arch/i386/lib/board.c |6 -- 2 files changed, 33 insertions(+), 17 deletions(-) diff --git a/arch/i386/cpu/start.S b/arch/i386/cpu/start.S index 95be5a2..77f0332 100644 --- a/arch/i386/cpu/start.S +++ b/arch/i386/cpu/start.S @@ -96,21 +96,6 @@ car_init_ret: /* size memory */ calldram_init_f - /* Setup stack in SDRAM */ - movl(GD_RAM_SIZE * 4)(%ebp), %esp - - /* Test the stack */ - pushl $0 - popl%ecx - cmpl$0, %ecx - jne die - push$0x55aa55aa - popl%ecx - cmpl$0x55aa55aa, %ecx - jne die - - wbinvd - /* Set parameter to board_init_f() to boot flags */ movl(GD_FLAGS * 4)(%ebp), %eax @@ -118,6 +103,35 @@ car_init_ret: /* indicate (lack of) progress */ movw$0x85, %ax + jmp die + +.globl relocate_code +.type relocate_code, @function +relocate_code: + /* +* SDRAM has been initialised, U-Boot code has been copied into +* RAM, BSS has been cleared and relocation adjustments have been +* made. It is now time to jump into the in-RAM copy of U-Boot +* +* %eax = Address of top of stack +* %edx = Address of Global Data +* %ecx = Base address of in-RAM copy of U-Boot +*/ + + /* Setup stack in RAM */ + movl%eax, %esp + + /* Setup call address of in-RAM copy of board_init_r() */ + movl$board_init_r, %ebp + subl(GD_RELOC_OFF * 4)(%edx), %ebp + + /* Setup parameters to board_init_r() */ + movl%edx, %eax + movl%ecx, %edx + + /* Jump to in-RAM copy of board_init_r() */ + call*%ebp + die: hlt jmp die hlt diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c index 09816df..e3869d6 100644 --- a/arch/i386/lib/board.c +++ b/arch/i386/lib/board.c @@ -189,6 +189,7 @@ void board_init_f(ulong boot_flags) ulong *src_addr; ulong *end_addr; + void *addr_sp; void *dest_addr; ulong rel_offset; Elf32_Rel *re_src; @@ -198,6 +199,7 @@ void board_init_f(ulong boot_flags) /* Calculate destination RAM Address and relocation offset */ dest_addr = (void *)gd->ram_size; + addr_sp = dest_addr; dest_addr -= CONFIG_SYS_STACK_SIZE; dest_addr -= (bss_end - text_start); rel_offset = text_start - dest_addr; @@ -242,9 +244,9 @@ void board_init_f(ulong boot_flags) gd->flags |= GD_FLG_RELOC; /* Enter the relocated U-Boot! */ - (board_init_r - rel_offset)(gd, (ulong)dest_addr); + relocate_code((ulong)addr_sp, gd, (ulong)dest_addr); - /* NOTREACHED - board_init_f() does not return */ + /* NOTREACHED - relocate_code() does not return */ while(1); } -- 1.7.1.422.g049e9 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 22/32] sc520: Move RAM sizing code from asm to C
Signed-off-by: Graeme Russ
---
arch/i386/cpu/sc520/Makefile |2 +-
arch/i386/cpu/sc520/sc520.c | 110 ---
arch/i386/cpu/sc520/sc520_asm.S | 608 -
arch/i386/cpu/sc520/sc520_sdram.c | 532
arch/i386/cpu/start.S | 48 +--
arch/i386/include/asm/ic/sc520.h | 57
arch/i386/lib/board.c | 10 +-
board/eNET/eNET.c |6 -
board/eNET/eNET_start16.S |5 -
include/configs/eNET.h|2 +-
10 files changed, 612 insertions(+), 768 deletions(-)
delete mode 100644 arch/i386/cpu/sc520/sc520_asm.S
create mode 100644 arch/i386/cpu/sc520/sc520_sdram.c
diff --git a/arch/i386/cpu/sc520/Makefile b/arch/i386/cpu/sc520/Makefile
index 3c25cba..54260b6 100644
--- a/arch/i386/cpu/sc520/Makefile
+++ b/arch/i386/cpu/sc520/Makefile
@@ -33,10 +33,10 @@ LIB := $(obj)lib$(SOC).o
COBJS-$(CONFIG_SYS_SC520) += sc520.o
COBJS-$(CONFIG_PCI) += sc520_pci.o
+COBJS-$(CONFIG_SYS_SC520) += sc520_sdram.o
COBJS-$(CONFIG_SYS_SC520_SSI) += sc520_ssi.o
COBJS-$(CONFIG_SYS_SC520_TIMER) += sc520_timer.o
-SOBJS-$(CONFIG_SYS_SC520) += sc520_asm.o
SOBJS-$(CONFIG_SYS_SC520) += sc520_car.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c
index 76de6be..d5597ca 100644
--- a/arch/i386/cpu/sc520/sc520.c
+++ b/arch/i386/cpu/sc520/sc520.c
@@ -31,13 +31,6 @@
DECLARE_GLOBAL_DATA_PTR;
-/*
- * utility functions for boards based on the AMD sc520
- *
- * void init_sc520(void)
- * unsigned long init_sc520_dram(void)
- */
-
sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)SC520_MMCR_BASE;
int cpu_init_f(void)
@@ -65,109 +58,6 @@ int cpu_init_f(void)
return x86_cpu_init_f();
}
-unsigned long init_sc520_dram(void)
-{
- bd_t *bd = gd->bd;
-
- u32 dram_present=0;
- u32 dram_ctrl;
-
-#ifdef CONFIG_SYS_SDRAM_DRCTMCTL
- /* these memory control registers are set up in the assember part,
-* in sc520_asm.S, during 'mem_init'. If we muck with them here,
-* after we are running a stack in RAM, we have troubles. Besides,
-* these refresh and delay values are better ? simply specified
-* outright in the include/configs/{cfg} file since the HW designer
-* simply dictates it.
-*/
-#else
- u8 tmp;
- u8 val;
-
- int cas_precharge_delay = CONFIG_SYS_SDRAM_PRECHARGE_DELAY;
- int refresh_rate= CONFIG_SYS_SDRAM_REFRESH_RATE;
- int ras_cas_delay = CONFIG_SYS_SDRAM_RAS_CAS_DELAY;
-
- /* set SDRAM speed here */
-
- refresh_rate /= 78;
- if (refresh_rate <= 1) {
- val = 0;/* 7.8us */
- } else if (refresh_rate == 2) {
- val = 1;/* 15.6us */
- } else if (refresh_rate == 3 || refresh_rate == 4) {
- val = 2;/* 31.2us */
- } else {
- val = 3;/* 62.4us */
- }
-
- tmp = (readb(&sc520_mmcr->drcctl) & 0xcf) | (val<<4);
- writeb(tmp, &sc520_mmcr->drcctl);
-
- val = readb(&sc520_mmcr->drctmctl) & 0xf0;
-
- if (cas_precharge_delay==3) {
- val |= 0x04;/* 3T */
- } else if (cas_precharge_delay==4) {
- val |= 0x08;/* 4T */
- } else if (cas_precharge_delay>4) {
- val |= 0x0c;
- }
-
- if (ras_cas_delay > 3) {
- val |= 2;
- } else {
- val |= 1;
- }
- writeb(val, &c520_mmcr->drctmctl);
-#endif
-
- /*
-* We read-back the configuration of the dram
-* controller that the assembly code wrote
-*/
- dram_ctrl = readl(&sc520_mmcr->drcbendadr);
-
- bd->bi_dram[0].start = 0;
- if (dram_ctrl & 0x80) {
- /* bank 0 enabled */
- dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
- bd->bi_dram[0].size = bd->bi_dram[1].start;
- } else {
- bd->bi_dram[0].size = 0;
- bd->bi_dram[1].start = bd->bi_dram[0].start;
- }
-
- if (dram_ctrl & 0x8000) {
- /* bank 1 enabled */
- dram_present = bd->bi_dram[2].start = (dram_ctrl & 0x7f00) <<
14;
- bd->bi_dram[1].size = bd->bi_dram[2].start -
bd->bi_dram[1].start;
- } else {
- bd->bi_dram[1].size = 0;
- bd->bi_dram[2].start = bd->bi_dram[1].start;
- }
-
- if (dram_ctrl & 0x80) {
- /* bank 2 enabled */
- dram_present = bd->bi_dram[3].start = (dram_ctrl & 0x7f) <<
6;
- bd->bi_dram[2].size = bd->bi_dram[3].start -
bd->bi_dram[2].start;
- } else {
- bd->bi_dram[2].size = 0;
- bd->bi_dram[3].start = bd->bi_dram[2].start;
- }
-
- if (dram_ctrl & 0x8000) {
- /* bank 3 enabled */
- dram_present
[U-Boot] [PATCH 21/32] x86: Use Cache-As-RAM for initial stack
Signed-off-by: Graeme Russ --- arch/i386/cpu/sc520/Makefile|1 + arch/i386/cpu/sc520/sc520_asm.S |6 +- arch/i386/cpu/sc520/sc520_car.S | 94 +++ arch/i386/cpu/start.S | 35 +++--- include/configs/eNET.h | 20 5 files changed, 135 insertions(+), 21 deletions(-) create mode 100644 arch/i386/cpu/sc520/sc520_car.S diff --git a/arch/i386/cpu/sc520/Makefile b/arch/i386/cpu/sc520/Makefile index b962b02..3c25cba 100644 --- a/arch/i386/cpu/sc520/Makefile +++ b/arch/i386/cpu/sc520/Makefile @@ -37,6 +37,7 @@ COBJS-$(CONFIG_SYS_SC520_SSI) += sc520_ssi.o COBJS-$(CONFIG_SYS_SC520_TIMER) += sc520_timer.o SOBJS-$(CONFIG_SYS_SC520) += sc520_asm.o +SOBJS-$(CONFIG_SYS_SC520) += sc520_car.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/arch/i386/cpu/sc520/sc520_asm.S b/arch/i386/cpu/sc520/sc520_asm.S index 9f6cce3..901aa61 100644 --- a/arch/i386/cpu/sc520/sc520_asm.S +++ b/arch/i386/cpu/sc520/sc520_asm.S @@ -515,7 +515,7 @@ bad_ram: dram_done: /* Restore Boot Flags */ movl%ebx, %ebp - jmp mem_init_ret + ret #if CONFIG_SYS_SDRAM_ECC_ENABLE .globl init_ecc @@ -560,7 +560,7 @@ set_ecc: movb%al,(%edi) out: - jmp init_ecc_ret + ret #endif /* @@ -605,4 +605,4 @@ bank3: movl(%edi), %eax done: movl%edx, %eax - jmp get_mem_size_ret + ret diff --git a/arch/i386/cpu/sc520/sc520_car.S b/arch/i386/cpu/sc520/sc520_car.S new file mode 100644 index 000..22f5225 --- /dev/null +++ b/arch/i386/cpu/sc520/sc520_car.S @@ -0,0 +1,94 @@ +/* + * (C) Copyright 2010 + * Graeme Russ . + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include + +.section .text + +.globl car_init +car_init: + /* +* How to enable Cache-As-RAM for the AMD Elan SC520: +* 1. Turn off the CPU Cache (may not be strictly required) +* 2. Set code execution PAR (usually the BOOTCS region) to be +* non-cachable +* 3. Create a Cachable PAR Region for an area of memory which is +* a) NOT where the code is being executed +* b) NOT SDRAM (Controller not initialised yet) +* c) WILL response to read requests +* The easiest way to do this is to create a second BOOTCS +* PAR mappnig with an address != the PAR in step 2 +* 4. Issue a wbinvd to invalidate the CPU cache +* 5. Turn on the CPU Cache +* 6. Read 16kB from the cached PAR region setup in step 3 +* 7. Turn off the CPU Cache (but DO NOT issue a wbinvd) +* +* The following code uses PAR2 as the cached PAR (PAR0 and PAR1 +* are avoided as these are the only two PARs which can be used +* as PCI BUS Memory regions which the board might require) +* +* The configuration of PAR2 must be set in the board configuration +* file as CONFIG_SYS_SC520_CAR_PAR +*/ + + /* Configure Cache-As-RAM PAR */ + movl$CONFIG_SYS_SC520_CAR_PAR, %eax + movl$SC520_PAR2, %edi + movl%eax, (%edi) + + /* Trash the cache then turn it on */ + wbinvd + movl%cr0, %eax + andl$~(X86_CR0_NW | X86_CR0_CD), %eax + movl%eax, %cr0 + + /* +* The cache is now enabled and empty. Map a region of memory to +* it by reading that region. +*/ + movl$CONFIG_SYS_CAR_ADDR, %esi + movl$CONFIG_SYS_CAR_SIZE, %ecx + shrl$2, %ecx/* we are reading longs */ + cld + rep lodsl + + /* Turn off the cache, but don't trash it */ + movl%cr0, %eax + orl $(X86_CR0_NW | X86_CR0_CD), %eax + movl%eax, %cr0 + + /* Clear the CAR region */ + xorl%eax, %eax + movl$CONFIG_SYS_CAR_ADDR, %edi + movl$CONFIG_SYS_CAR_SIZE, %ecx + shrl$2, %ecx/* we are writing longs */ + rep stosl + + /* +* Done - We should now have CONFIG_SYS_CAR_SIZE b
[U-Boot] [PATCH 20/32] x86: Move initial gd to fixed location
Signed-off-by: Graeme Russ
---
arch/i386/cpu/start.S | 12 +-
arch/i386/include/asm/global_data.h |7 +-
arch/i386/lib/board.c | 36 +++---
include/configs/eNET.h |3 ++
4 files changed, 39 insertions(+), 19 deletions(-)
diff --git a/arch/i386/cpu/start.S b/arch/i386/cpu/start.S
index 97bac8f..0ce9713 100644
--- a/arch/i386/cpu/start.S
+++ b/arch/i386/cpu/start.S
@@ -127,13 +127,13 @@ mem_ok:
/* Set the upper memory limit parameter */
subl$CONFIG_SYS_STACK_SIZE, %eax
- /* Reserve space for global data */
- subl$(GD_SIZE * 4), %eax
+ /* Pointer to temporary global data */
+ movl$CONFIG_SYS_INIT_GD_ADDR, %edx
- /* %eax points to the global data structure */
- movl%esp, (GD_RAM_SIZE * 4)(%eax)
- movl%ebx, (GD_FLAGS * 4)(%eax)
- movl%ecx, (GD_LOAD_OFF * 4)(%eax)
+ /* %edx points to the global data structure */
+ movl%esp, (GD_RAM_SIZE * 4)(%edx)
+ movl%ebx, (GD_FLAGS * 4)(%edx)
+ movl%ecx, (GD_LOAD_OFF * 4)(%edx)
callboard_init_f/* Enter, U-boot! */
diff --git a/arch/i386/include/asm/global_data.h
b/arch/i386/include/asm/global_data.h
index e9000c3..cd067f5 100644
--- a/arch/i386/include/asm/global_data.h
+++ b/arch/i386/include/asm/global_data.h
@@ -87,7 +87,12 @@ extern gd_t *gd;
#define GD_FLG_COLD_BOOT 0x00100 /* Cold Boot */
#define GD_FLG_WARM_BOOT 0x00200 /* Warm Boot */
-
+#if 0
#define DECLARE_GLOBAL_DATA_PTR
+#else
+#define XTRN_DECLARE_GLOBAL_DATA_PTRextern
+#define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \
+gd_t *gd
+#endif
#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c
index 2cadce8..4227312 100644
--- a/arch/i386/lib/board.c
+++ b/arch/i386/lib/board.c
@@ -45,7 +45,15 @@
#include
#endif
-DECLARE_GLOBAL_DATA_PTR;
+/*
+ * Pointer to initial global data area
+ *
+ * Here we initialize it.
+ */
+#undef XTRN_DECLARE_GLOBAL_DATA_PTR
+#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
+DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR);
+
/* Exports from the Linker Script */
extern ulong __text_start;
@@ -168,7 +176,7 @@ gd_t *gd;
/*
* Load U-Boot into RAM, initialize BSS, perform relocation adjustments
*/
-void board_init_f (ulong gdp)
+void board_init_f(ulong mem_top)
{
void *text_start = &__text_start;
void *data_end = &__data_end;
@@ -187,11 +195,11 @@ void board_init_f (ulong gdp)
Elf32_Rel *re_end;
/* Calculate destination RAM Address and relocation offset */
- dest_addr = (void *)gdp - (bss_end - text_start);
+ dest_addr = (void *)mem_top - (bss_end - text_start);
rel_offset = text_start - dest_addr;
/* Perform low-level initialization only when cold booted */
- if (((gd_t *)gdp)->flags & GD_FLG_COLD_BOOT) {
+ if (gd->flags & GD_FLG_COLD_BOOT) {
/* First stage CPU initialization */
if (cpu_init_f() != 0)
hang();
@@ -203,8 +211,8 @@ void board_init_f (ulong gdp)
/* Copy U-Boot into RAM */
dst_addr = (ulong *)dest_addr;
- src_addr = (ulong *)(text_start + ((gd_t *)gdp)->load_off);
- end_addr = (ulong *)(data_end + ((gd_t *)gdp)->load_off);
+ src_addr = (ulong *)(text_start + gd->load_off);
+ end_addr = (ulong *)(data_end + gd->load_off);
while (src_addr < end_addr)
*dst_addr++ = *src_addr++;
@@ -217,8 +225,8 @@ void board_init_f (ulong gdp)
*dst_addr++ = 0x;
/* Perform relocation adjustments */
- re_src = (Elf32_Rel *)(rel_dyn_start + ((gd_t *)gdp)->load_off);
- re_end = (Elf32_Rel *)(rel_dyn_end + ((gd_t *)gdp)->load_off);
+ re_src = (Elf32_Rel *)(rel_dyn_start + gd->load_off);
+ re_end = (Elf32_Rel *)(rel_dyn_end + gd->load_off);
do {
if (re_src->r_offset >= CONFIG_SYS_TEXT_BASE)
@@ -226,11 +234,11 @@ void board_init_f (ulong gdp)
*(Elf32_Addr *)(re_src->r_offset - rel_offset)
-= rel_offset;
} while (re_src++ < re_end);
- ((gd_t *)gdp)->reloc_off = rel_offset;
- ((gd_t *)gdp)->flags |= GD_FLG_RELOC;
+ gd->reloc_off = rel_offset;
+ gd->flags |= GD_FLG_RELOC;
/* Enter the relocated U-Boot! */
- (board_init_r - rel_offset)((gd_t *)gdp, (ulong)dest_addr);
+ (board_init_r - rel_offset)(gd, (ulong)dest_addr);
/* NOTREACHED - board_init_f() does not return */
while(1);
@@ -242,11 +250,15 @@ void board_init_r(gd_t *id, ulong dest_addr)
int i;
ulong size;
static bd_t bd_data;
+ static gd_t gd_data;
init_fnc_t **init_fnc_ptr;
show_boot_progress(0x21);
- gd = id;
+ /* Global data pointer is now w
[U-Boot] [PATCH 17/32] eNET: Define MMCR values in config.h
Signed-off-by: Graeme Russ
---
board/eNET/eNET.c | 104 +++-
board/eNET/eNET_start16.S |5 +-
include/configs/eNET.h| 382 +
3 files changed, 445 insertions(+), 46 deletions(-)
diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
index 3b74ce9..546406a 100644
--- a/board/eNET/eNET.c
+++ b/board/eNET/eNET.c
@@ -53,36 +53,57 @@ static void enet_toggle_run_led(void);
*/
int board_early_init_f(void)
{
- writeb(0x01, &sc520_mmcr->gpcsrt); /* GP Chip Select
Recovery Time */
- writeb(0x07, &sc520_mmcr->gpcspw); /* GP Chip Select Pulse
Width */
- writeb(0x00, &sc520_mmcr->gpcsoff); /* GP Chip Select
Offset */
- writeb(0x05, &sc520_mmcr->gprdw); /* GP Read pulse width
*/
- writeb(0x01, &sc520_mmcr->gprdoff); /* GP Read offset */
- writeb(0x05, &sc520_mmcr->gpwrw); /* GP Write pulse width
*/
- writeb(0x01, &sc520_mmcr->gpwroff); /* GP Write offset */
-
- writew(0x0630, &sc520_mmcr->piodata15_0); /* PIO15_PIO0 Data */
- writew(0x2000, &sc520_mmcr->piodata31_16); /* PIO31_PIO16 Data */
- writew(0x2000, &sc520_mmcr->piodir31_16); /* GPIO Direction */
- writew(0x87b5, &sc520_mmcr->piodir15_0);/* GPIO Direction */
- writew(0x0dfe, &sc520_mmcr->piopfs31_16); /* GPIO pin function
31-16 reg */
- writew(0x200a, &sc520_mmcr->piopfs15_0);/* GPIO pin function
15-0 reg */
- writeb(0xf8, &sc520_mmcr->cspfs); /* Chip Select Pin
Function Select */
-
- writel(0x200713f8, &sc520_mmcr->par[2]);/* Uart A (GPCS0,
0x013f8, 8 Bytes) */
- writel(0x2c0712f8, &sc520_mmcr->par[3]);/* Uart B (GPCS3,
0x012f8, 8 Bytes) */
- writel(0x300711f8, &sc520_mmcr->par[4]);/* Uart C (GPCS4,
0x011f8, 8 Bytes) */
- writel(0x340710f8, &sc520_mmcr->par[5]);/* Uart D (GPCS5,
0x010f8, 8 Bytes) */
- writel(0xe3ffc000, &sc520_mmcr->par[6]);/* SDRAM (0x,
128MB) */
- writel(0xaa3fd000, &sc520_mmcr->par[7]);/* StrataFlash (ROMCS1,
0x1000, 16MB) */
- writel(0xca3fd100, &sc520_mmcr->par[8]);/* StrataFlash (ROMCS2,
0x1100, 16MB) */
- writel(0x4203d900, &sc520_mmcr->par[9]);/* SRAM (GPCS0,
0x1900, 1MB) */
- writel(0x4e03d910, &sc520_mmcr->par[10]); /* SRAM (GPCS3,
0x1910, 1MB) */
- writel(0x50018100, &sc520_mmcr->par[11]); /* DP-RAM (GPCS4,
0x1810, 4kB) */
- writel(0x5402, &sc520_mmcr->par[12]); /* CFLASH1
(0x2, 4kB) */
- writel(0x5c020001, &sc520_mmcr->par[13]); /* CFLASH2
(0x20001, 4kB) */
-/* writel(0x8bfff800, &sc520_mmcr->par14); */ /* BOOTCS at
0x1800 */
-/* writel(0x38201000, &sc520_mmcr->par15); */ /* LEDs etc (GPCS6,
0x1000, 20 Bytes */
+ u16 pio_out_cfg = 0x;
+
+ /* Configure General Purpose Bus timing */
+ writeb(CONFIG_SYS_SC520_GPCSRT, &sc520_mmcr->gpcsrt);
+ writeb(CONFIG_SYS_SC520_GPCSPW, &sc520_mmcr->gpcspw);
+ writeb(CONFIG_SYS_SC520_GPCSOFF, &sc520_mmcr->gpcsoff);
+ writeb(CONFIG_SYS_SC520_GPRDW, &sc520_mmcr->gprdw);
+ writeb(CONFIG_SYS_SC520_GPRDOFF, &sc520_mmcr->gprdoff);
+ writeb(CONFIG_SYS_SC520_GPWRW, &sc520_mmcr->gpwrw);
+ writeb(CONFIG_SYS_SC520_GPWROFF, &sc520_mmcr->gpwroff);
+
+ /* Configure Programmable Input/Output Pins */
+ writew(CONFIG_SYS_SC520_PIODIR15_0, &sc520_mmcr->piodir15_0);
+ writew(CONFIG_SYS_SC520_PIODIR31_16, &sc520_mmcr->piodir31_16);
+ writew(CONFIG_SYS_SC520_PIOPFS31_16, &sc520_mmcr->piopfs31_16);
+ writew(CONFIG_SYS_SC520_PIOPFS15_0, &sc520_mmcr->piopfs15_0);
+ writeb(CONFIG_SYS_SC520_CSPFS, &sc520_mmcr->cspfs);
+ writeb(CONFIG_SYS_SC520_CLKSEL, &sc520_mmcr->clksel);
+
+ /*
+* Turn off top board
+* Set StrataFlash chips to 16-bit width
+* Set StrataFlash chips to normal (non reset/power down) mode
+*/
+ pio_out_cfg |= CONFIG_SYS_ENET_TOP_BRD_PWR;
+ pio_out_cfg |= CONFIG_SYS_ENET_SF_WIDTH;
+ pio_out_cfg |= CONFIG_SYS_ENET_SF1_MODE;
+ pio_out_cfg |= CONFIG_SYS_ENET_SF2_MODE;
+ writew(pio_out_cfg, &sc520_mmcr->pioset15_0);
+
+ /* Turn off auxiliary power output */
+ writew(CONFIG_SYS_ENET_AUX_PWR, &sc520_mmcr->pioclr15_0);
+
+ /* Clear FPGA program mode */
+ writew(CONFIG_SYS_ENET_FPGA_PROG, &sc520_mmcr->pioset31_16);
+
+ /* Configure Programmable Address Regions */
+ writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[2]);
+ writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[3]);
+ writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[4]);
+ writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[5]);
+ writel(CONFIG_SYS_SC520_SDRAM_PAR, &sc520_mmcr->par[6]);
+
[U-Boot] [PATCH 15/32] eNET: Fix eNET Interrupt Setup for Linux
Fix minor issues with the configuration of the hardware interrupts for Linux when booting the eNET board Signed-off-by: Graeme Russ --- board/eNET/eNET.c | 15 +-- 1 files changed, 9 insertions(+), 6 deletions(-) diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index b2f349f..3b74ce9 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -191,10 +191,18 @@ void setup_pcat_compatibility() */ writew(0x,&sc520_mmcr->intpinpol); - /* Set PIT 0 -> IRQ0, RTC -> IRQ8, FP error -> IRQ13 */ + /* +* PIT 0 -> IRQ0 +* RTC -> IRQ8 +* FP error -> IRQ13 +* UART1 -> IRQ4 +* UART2 -> IRQ3 +*/ writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]); writeb(SC520_IRQ8, &sc520_mmcr->rtcmap); writeb(SC520_IRQ13, &sc520_mmcr->ferrmap); + writeb(SC520_IRQ4, &sc520_mmcr->uart_int_map[0]); + writeb(SC520_IRQ3, &sc520_mmcr->uart_int_map[1]); /* Disable all other interrupt sources */ writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]); @@ -202,11 +210,6 @@ void setup_pcat_compatibility() writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]); writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]); writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]); - writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[0]);/* disable PCI INT A */ - writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[1]);/* disable PCI INT B */ - writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[2]);/* disable PCI INT C */ - writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[3]);/* disable PCI INT D */ - writeb(SC520_IRQ_DISABLED, &sc520_mmcr->dmabcintmap); /* disable DMA INT */ writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap); writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap); writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap); -- 1.7.1.422.g049e9 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 13/32] sc520: Move board specific settings to board init function
Signed-off-by: Graeme Russ
---
arch/i386/cpu/sc520/sc520.c | 19 ---
board/eNET/eNET.c |9 +
2 files changed, 9 insertions(+), 19 deletions(-)
diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c
index 7caa4c8..19a678d 100644
--- a/arch/i386/cpu/sc520/sc520.c
+++ b/arch/i386/cpu/sc520/sc520.c
@@ -42,25 +42,6 @@ sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)SC520_MMCR_BASE;
int cpu_init_f(void)
{
- /*
-* Set the UARTxCTL register at it's slower,
-* baud clock giving us a 1.8432 MHz reference
-*/
- writeb(0x07, &sc520_mmcr->uart1ctl);
- writeb(0x07, &sc520_mmcr->uart2ctl);
-
- /* first set the timer pin mapping */
- writeb(0x72, &sc520_mmcr->clksel); /* no clock frequency selected,
use 1.1892MHz */
-
- /* enable PCI bus arbiter (concurrent mode) */
- writeb(0x02, &sc520_mmcr->sysarbctl);
-
- /* enable external grants */
- writeb(0x1f, &sc520_mmcr->sysarbmenb);
-
- /* enable posted-writes */
- writeb(0x04, &sc520_mmcr->hbctl);
-
if (CONFIG_SYS_SC520_HIGH_SPEED) {
/* set it to 133 MHz and write back */
writeb(0x02, &sc520_mmcr->cpuctl);
diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
index 30d8750..b2f349f 100644
--- a/board/eNET/eNET.c
+++ b/board/eNET/eNET.c
@@ -94,12 +94,21 @@ int board_early_init_f(void)
writew(0x0615, &sc520_mmcr->romcs1ctl);
writew(0x0615, &sc520_mmcr->romcs2ctl);
+ /*
+* Set the timer pin mapping
+* no clock frequency selected, use 1.1892MHz
+*/
+ writeb(0x72, &sc520_mmcr->clksel);
+
writeb(0x00, &sc520_mmcr->adddecctl);
writeb(0x07, &sc520_mmcr->uart1ctl);
writeb(0x07, &sc520_mmcr->uart2ctl);
writeb(0x06, &sc520_mmcr->sysarbctl);
writew(0x0003, &sc520_mmcr->sysarbmenb);
+ /* enable posted-writes */
+ writeb(0x04, &sc520_mmcr->hbctl);
+
return 0;
}
--
1.7.1.422.g049e9
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[U-Boot] [PATCH 14/32] sc520: Remove printf calls from cpu_init_f
In later patches, cpu_init_f will be called before console has been
initialised and printf will not be legitimately available
Signed-off-by: Graeme Russ
---
arch/i386/cpu/sc520/sc520.c |2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c
index 19a678d..76de6be 100644
--- a/arch/i386/cpu/sc520/sc520.c
+++ b/arch/i386/cpu/sc520/sc520.c
@@ -46,11 +46,9 @@ int cpu_init_f(void)
/* set it to 133 MHz and write back */
writeb(0x02, &sc520_mmcr->cpuctl);
gd->cpu_clk = 13300;
- printf("## CPU Speed set to 133MHz\n");
} else {
/* set it to 100 MHz and write back */
writeb(0x01, &sc520_mmcr->cpuctl);
- printf("## CPU Speed set to 100MHz\n");
gd->cpu_clk = 1;
}
--
1.7.1.422.g049e9
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[U-Boot] [PATCH 12/32] sc520: Define MMCR address in include file
Signed-off-by: Graeme Russ
---
arch/i386/cpu/sc520/sc520.c |2 +-
arch/i386/cpu/sc520/sc520_asm.S | 49 -
arch/i386/include/asm/ic/sc520.h | 36 ++-
board/eNET/eNET_start16.S|7 +++--
4 files changed, 55 insertions(+), 39 deletions(-)
diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c
index b99408c..7caa4c8 100644
--- a/arch/i386/cpu/sc520/sc520.c
+++ b/arch/i386/cpu/sc520/sc520.c
@@ -38,7 +38,7 @@ DECLARE_GLOBAL_DATA_PTR;
* unsigned long init_sc520_dram(void)
*/
-volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)0xfffef000;
+sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)SC520_MMCR_BASE;
int cpu_init_f(void)
{
diff --git a/arch/i386/cpu/sc520/sc520_asm.S b/arch/i386/cpu/sc520/sc520_asm.S
index 63c14b7..9f6cce3 100644
--- a/arch/i386/cpu/sc520/sc520_asm.S
+++ b/arch/i386/cpu/sc520/sc520_asm.S
@@ -142,16 +142,9 @@
*/
#include
+#include
.section .text
-.equDRCCTL, 0x0fffef010 /* DRAM control register */
-.equDRCTMCTL, 0x0fffef012 /* DRAM timing control register */
-.equDRCCFG, 0x0fffef014 /* DRAM bank configuration register
*/
-.equDRCBENDADR, 0x0fffef018 /* DRAM bank ending address register
*/
-.equECCCTL, 0x0fffef020 /* DRAM ECC control register */
-.equECCINT, 0x0fffefd18 /* DRAM ECC nmi-INT mapping */
-.equDBCTL, 0x0fffef040 /* DRAM buffer control register */
-
.equCACHELINESZ, 0x0010 /* size of our cache line (read
buffer) */
.equCOL11_ADR, 0x0e001e00/* 11 col addrs */
.equCOL10_ADR, 0x0e000e00/* 10 col addrs */
@@ -179,27 +172,27 @@ mem_init:
/* initialize dram controller registers */
xorw%ax, %ax
- movl$DBCTL, %edi
+ movl$SC520_DBCTL, %edi
movb%al, (%edi) /* disable write buffer */
- movl$ECCCTL, %edi
+ movl$SC520_ECCCTL, %edi
movb%al, (%edi) /* disable ECC */
- movl$DRCTMCTL, %edi
+ movl$SC520_DRCTMCTL, %edi
movb$0x1e, %al /* Set SDRAM timing for slowest */
movb%al, (%edi)
/* setup loop to do 4 external banks starting with bank 3 */
movl$0xff00, %eax /* enable last bank and setup */
- movl$DRCBENDADR, %edi /* ending address register */
+ movl$SC520_DRCBENDADR, %edi /* ending address register */
movl%eax, (%edi)
- movl$DRCCFG, %edi /* setup */
+ movl$SC520_DRCCFG, %edi /* setup */
movw$0x, %ax/* dram config register for */
movw%ax, (%edi)
/* issue a NOP to all DRAMs */
- movl$DRCCTL, %edi /* setup DRAM control register with */
+ movl$SC520_DRCCTL, %edi /* setup DRAM control register with */
movb$0x01, %al /* Disable refresh,disable write buffer
*/
movb%al, (%edi)
movl$CACHELINESZ, %esi /* just a dummy address to write for */
@@ -409,7 +402,7 @@ bad_reint:
/*
* issue all banks precharge
*/
- movl$DRCCTL, %esi /* setup DRAM control register with */
+ movl$SC520_DRCCTL, %esi /* setup DRAM control register with */
movb$0x02, %al /* All banks precharge */
movb%al, (%esi)
movl$CACHELINESZ, %esi /* address to init read buffer */
@@ -418,7 +411,7 @@ bad_reint:
/*
* update ENDING ADDRESS REGISTER
*/
- movl$DRCBENDADR, %edi /* DRAM ending address register */
+ movl$SC520_DRCBENDADR, %edi /* DRAM ending address register */
movl%ecx, %ebx
addl%ebx, %edi
movb%dh, (%edi)
@@ -435,7 +428,7 @@ bad_reint:
shlw%cl, %bx
notw%bx
xchgw %cx, %ax
- movl$DRCCFG, %edi
+ movl$SC520_DRCCFG, %edi
movw(%edi), %ax
andw%bx, %ax
orw %dx, %ax
@@ -444,7 +437,7 @@ bad_reint:
decw%cx
movl%ecx, %ebx
- movl$DRCBENDADR, %edi /* DRAM ending address register */
+ movl$SC520_DRCBENDADR, %edi /* DRAM ending address register */
movb$0xff, %al
addl%ebx, %edi
movb%al, (%edi)
@@ -452,7 +445,7 @@ bad_reint:
/*
* set control register to NORMAL mode
*/
- movl$DRCCTL, %esi /* setup DRAM control register with */
+ movl$SC520_DRCCTL, %esi /* setup DRAM control register with */
movb$0x00, %al /* Normal mode value */
movb%al, (%esi)
movl$CACHELINESZ, %esi /* address to init read buffer */
@@ -460,7 +453,7 @@ bad_reint:
jmp nextbank
cleanup
[U-Boot] [PATCH 11/32] x86: Make cpu init functions weak
Signed-off-by: Graeme Russ
---
arch/i386/cpu/cpu.c | 14 --
arch/i386/cpu/sc520/sc520.c | 11 +++
arch/i386/include/asm/u-boot-i386.h |2 ++
board/eNET/eNET.c | 22 --
4 files changed, 17 insertions(+), 32 deletions(-)
diff --git a/arch/i386/cpu/cpu.c b/arch/i386/cpu/cpu.c
index e96380a..2339cd4 100644
--- a/arch/i386/cpu/cpu.c
+++ b/arch/i386/cpu/cpu.c
@@ -87,7 +87,7 @@ static void reload_gdt(void)
}
-int cpu_init_f(void)
+int x86_cpu_init_f(void)
{
const u32 em_rst = ~X86_CR0_EM;
const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
@@ -102,15 +102,25 @@ int cpu_init_f(void)
return 0;
}
+int cpu_init_f(void) __attribute__((weak, alias("x86_cpu_init_f")));
-int cpu_init_r(void)
+int x86_cpu_init_r(void)
{
+ const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD);
+
+ /* turn on the cache and disable write through */
+ asm("movl %%cr0, %%eax\n"
+ "andl %0, %%eax\n"
+ "movl %%eax, %%cr0\n"
+ "wbinvd\n" : : "i" (nw_cd_rst) : "eax");
+
reload_gdt();
/* Initialize core interrupt and exception functionality of CPU */
cpu_init_interrupts ();
return 0;
}
+int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c
index 21037d2..b99408c 100644
--- a/arch/i386/cpu/sc520/sc520.c
+++ b/arch/i386/cpu/sc520/sc520.c
@@ -1,6 +1,6 @@
/*
* (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB .
+ * Daniel Engstr�m, Omicron Ceti AB .
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -40,10 +40,8 @@ DECLARE_GLOBAL_DATA_PTR;
volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)0xfffef000;
-void init_sc520(void)
+int cpu_init_f(void)
{
- const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD);
-
/*
* Set the UARTxCTL register at it's slower,
* baud clock giving us a 1.8432 MHz reference
@@ -85,10 +83,7 @@ void init_sc520(void)
/* turn on the SDRAM write buffer */
writeb(0x11, &sc520_mmcr->dbctl);
- /* turn on the cache and disable write through */
- asm("movl %%cr0, %%eax\n"
- "andl %0, %%eax\n"
- "movl %%eax, %%cr0\n" : : "i" (nw_cd_rst) : "eax");
+ return x86_cpu_init_f();
}
unsigned long init_sc520_dram(void)
diff --git a/arch/i386/include/asm/u-boot-i386.h
b/arch/i386/include/asm/u-boot-i386.h
index ce097a3..80db52f 100644
--- a/arch/i386/include/asm/u-boot-i386.h
+++ b/arch/i386/include/asm/u-boot-i386.h
@@ -25,7 +25,9 @@
#define _U_BOOT_I386_H_1
/* cpu/.../cpu.c */
+int x86_cpu_init_r(void);
int cpu_init_r(void);
+int x86_cpu_init_f(void);
int cpu_init_f(void);
/* cpu/.../timer.c */
diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
index 7f0e257..30d8750 100644
--- a/board/eNET/eNET.c
+++ b/board/eNET/eNET.c
@@ -48,33 +48,11 @@ unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
static void enet_timer_isr(void);
static void enet_toggle_run_led(void);
-void init_sc520_enet (void)
-{
- /* Set CPU Speed to 100MHz */
- writeb(0x01, &sc520_mmcr->cpuctl);
-
- /* wait at least one millisecond */
- asm("movl $0x2000,%%ecx\n"
- "0: pushl %%ecx\n"
- "popl %%ecx\n"
- "loop 0b\n": : : "ecx");
-
- /* turn on the SDRAM write buffer */
- writeb(0x11, &sc520_mmcr->dbctl);
-
- /* turn on the cache and disable write through */
- asm("movl %%cr0, %%eax\n"
- "andl $0x9fff, %%eax\n"
- "movl %%eax, %%cr0\n" : : : "eax");
-}
-
/*
* Miscellaneous platform dependent initializations
*/
int board_early_init_f(void)
{
- init_sc520_enet();
-
writeb(0x01, &sc520_mmcr->gpcsrt); /* GP Chip Select
Recovery Time */
writeb(0x07, &sc520_mmcr->gpcspw); /* GP Chip Select Pulse
Width */
writeb(0x00, &sc520_mmcr->gpcsoff); /* GP Chip Select
Offset */
--
1.7.1.422.g049e9
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[U-Boot] [PATCH 09/32] x86: Add processor flags header from linux
Signed-off-by: Graeme Russ
---
arch/i386/cpu/cpu.c | 13 +++-
arch/i386/cpu/interrupts.c |3 +-
arch/i386/cpu/sc520/sc520.c |7 ++-
arch/i386/cpu/start.S |3 +-
arch/i386/cpu/start16.S |5 +-
arch/i386/include/asm/processor-flags.h | 100 +++
6 files changed, 121 insertions(+), 10 deletions(-)
create mode 100644 arch/i386/include/asm/processor-flags.h
diff --git a/arch/i386/cpu/cpu.c b/arch/i386/cpu/cpu.c
index 1dcbb98..e96380a 100644
--- a/arch/i386/cpu/cpu.c
+++ b/arch/i386/cpu/cpu.c
@@ -36,6 +36,7 @@
#include
#include
#include
+#include
#include
/* Constructor for a conventional segment GDT (or LDT) entry */
@@ -88,12 +89,16 @@ static void reload_gdt(void)
int cpu_init_f(void)
{
+ const u32 em_rst = ~X86_CR0_EM;
+ const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
+
/* initialize FPU, reset EM, set MP and NE */
asm ("fninit\n" \
-"movl %cr0, %eax\n" \
-"andl $~0x4, %eax\n" \
-"orl $0x22, %eax\n" \
-"movl %eax, %cr0\n" );
+"movl %%cr0, %%eax\n" \
+"andl %0, %%eax\n" \
+"orl %1, %%eax\n" \
+"movl %%eax, %%cr0\n" \
+: : "i" (em_rst), "i" (mp_ne_set) : "eax");
return 0;
}
diff --git a/arch/i386/cpu/interrupts.c b/arch/i386/cpu/interrupts.c
index cdff3d9..1cefe02 100644
--- a/arch/i386/cpu/interrupts.c
+++ b/arch/i386/cpu/interrupts.c
@@ -30,6 +30,7 @@
#include
#include
#include
+#include
#define DECLARE_INTERRUPT(x) \
".globl irq_"#x"\n" \
@@ -237,7 +238,7 @@ int disable_interrupts(void)
asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
- return (flags&0x200); /* IE flags is bit 9 */
+ return flags & X86_EFLAGS_IF; /* IE flags is bit 9 */
}
/* IRQ Low-Level Service Routine */
diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c
index 7acd471..21037d2 100644
--- a/arch/i386/cpu/sc520/sc520.c
+++ b/arch/i386/cpu/sc520/sc520.c
@@ -26,6 +26,7 @@
#include
#include
+#include
#include
DECLARE_GLOBAL_DATA_PTR;
@@ -41,6 +42,8 @@ volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t
*)0xfffef000;
void init_sc520(void)
{
+ const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD);
+
/*
* Set the UARTxCTL register at it's slower,
* baud clock giving us a 1.8432 MHz reference
@@ -84,8 +87,8 @@ void init_sc520(void)
/* turn on the cache and disable write through */
asm("movl %%cr0, %%eax\n"
- "andl $0x9fff, %%eax\n"
- "movl %%eax, %%cr0\n" : : : "eax");
+ "andl %0, %%eax\n"
+ "movl %%eax, %%cr0\n" : : "i" (nw_cd_rst) : "eax");
}
unsigned long init_sc520_dram(void)
diff --git a/arch/i386/cpu/start.S b/arch/i386/cpu/start.S
index ab9338a..460c21b 100644
--- a/arch/i386/cpu/start.S
+++ b/arch/i386/cpu/start.S
@@ -26,6 +26,7 @@
#include
#include
#include
+#include
.section .text
@@ -46,7 +47,7 @@ _i386boot_start:
/* Turn of cache (this might require a 486-class CPU) */
movl%cr0, %eax
- orl $0x6000, %eax
+ orl $(X86_CR0_NW | X86_CR0_CD), %eax
movl%eax, %cr0
wbinvd
diff --git a/arch/i386/cpu/start16.S b/arch/i386/cpu/start16.S
index 0a5823d..7dc5358 100644
--- a/arch/i386/cpu/start16.S
+++ b/arch/i386/cpu/start16.S
@@ -23,6 +23,7 @@
*/
#include
+#include
#define BOOT_SEG 0x /* linear segment of boot code */
#define a32.byte 0x67;
@@ -45,7 +46,7 @@ board_init16_ret:
/* Turn of cache (this might require a 486-class CPU) */
movl%cr0, %eax
- orl $0x6000, %eax
+ orl $(X86_CR0_NW & X86_CR0_CD), %eax
movl%eax, %cr0
wbinvd
@@ -55,7 +56,7 @@ o32 cslgdtgdt_ptr
/* Now, we enter protected mode */
movl%cr0, %eax
- orl $1, %eax
+ orl $X86_CR0_PE, %eax
movl%eax, %cr0
/* Flush the prefetch queue */
diff --git a/arch/i386/include/asm/processor-flags.h
b/arch/i386/include/asm/processor-flags.h
new file mode 100644
index 000..7a3e836
--- /dev/null
+++ b/arch/i386/include/asm/processor-flags.h
@@ -0,0 +1,100 @@
+#ifndef _ASM_X86_PROCESSOR_FLAGS_H
+#define _ASM_X86_PROCESSOR_FLAGS_H
+/* Various flags defined: can be included from assembler. */
+
+/*
+ * EFLAGS bits
+ */
+#define X86_EFLAGS_CF 0x0001 /* Carry Flag */
+#define X86_EFLAGS_PF 0x0004 /* Parity Flag */
+#define X86_EFLAGS_AF 0x0010 /* Auxillary carry Flag */
+#define X86_EFLAGS_ZF 0x0040 /* Zero Flag */
+#define X86_EFLAGS_SF 0x0080 /* Sign Flag */
+#define X86_EFLAGS_TF 0x0100 /* Trap Flag */
+#define X86_EFLAGS_IF 0x0200 /* Interrupt Flag */
+#define X86_EFLAGS_DF 0x0400 /* Direction Flag
[U-Boot] [PATCH 10/32] x86: Call early_board_init when warm booting
early_board_init has been skipped to avoid SDRAM corruption in the case that a fully relocatable image has been loaded into SDRAM and is being executed from SDRAM. x86 is being aligned with other architectures (ARM and PPC in particlar) and will be using Cache-As-RAM to run a C environment from Flash (or SRAM if you have some). early_board_init may be needed to assist in the setup of Cache-As-RAM and the early C environment Signed-off-by: Graeme Russ --- arch/i386/cpu/start.S | 10 +- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/i386/cpu/start.S b/arch/i386/cpu/start.S index 460c21b..97bac8f 100644 --- a/arch/i386/cpu/start.S +++ b/arch/i386/cpu/start.S @@ -67,16 +67,16 @@ _start: /* Clear the interupt vectors */ lidtblank_idt_ptr - /* Skip low-level initialization if not starting from cold-reset */ - movl%ebx, %ecx - andl$GD_FLG_COLD_BOOT, %ecx - jz skip_mem_init - /* Early platform init (setup gpio, etc ) */ jmp early_board_init .globl early_board_init_ret early_board_init_ret: + /* Skip memory initialization if not starting from cold-reset */ + movl%ebx, %ecx + andl$GD_FLG_COLD_BOOT, %ecx + jz skip_mem_init + /* size memory */ jmp mem_init .globl mem_init_ret -- 1.7.1.422.g049e9 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 08/32] x86: Move Global Descriptor Table defines to processor.h
Signed-off-by: Graeme Russ --- arch/i386/cpu/cpu.c |8 +--- arch/i386/include/asm/processor.h |9 ++--- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/arch/i386/cpu/cpu.c b/arch/i386/cpu/cpu.c index ae40384..1dcbb98 100644 --- a/arch/i386/cpu/cpu.c +++ b/arch/i386/cpu/cpu.c @@ -35,6 +35,7 @@ #include #include +#include #include /* Constructor for a conventional segment GDT (or LDT) entry */ @@ -46,13 +47,6 @@ (((base) & 0x00ffULL) << 16) |\ (((limit) & 0xULL))) -/* Simple and small GDT entries for booting only */ - -#define GDT_ENTRY_32BIT_CS 2 -#define GDT_ENTRY_32BIT_DS (GDT_ENTRY_32BIT_CS + 1) -#define GDT_ENTRY_16BIT_CS (GDT_ENTRY_32BIT_DS + 1) -#define GDT_ENTRY_16BIT_DS (GDT_ENTRY_16BIT_CS + 1) - /* * Set up the GDT */ diff --git a/arch/i386/include/asm/processor.h b/arch/i386/include/asm/processor.h index 5dedba8..22a1298 100644 --- a/arch/i386/include/asm/processor.h +++ b/arch/i386/include/asm/processor.h @@ -23,7 +23,10 @@ #ifndef __ASM_PROCESSOR_H_ #define __ASM_PROCESSOR_H_ 1 -/* Currently this header is unused in the i386 port - * but some generic files #include - * so this file is a placeholder. */ + +#define GDT_ENTRY_32BIT_CS 2 +#define GDT_ENTRY_32BIT_DS (GDT_ENTRY_32BIT_CS + 1) +#define GDT_ENTRY_16BIT_CS (GDT_ENTRY_32BIT_DS + 1) +#define GDT_ENTRY_16BIT_DS (GDT_ENTRY_16BIT_CS + 1) + #endif -- 1.7.1.422.g049e9 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 07/32] x86: Add stack dump to register dump
Signed-off-by: Graeme Russ
---
arch/i386/cpu/interrupts.c | 16
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/arch/i386/cpu/interrupts.c b/arch/i386/cpu/interrupts.c
index e4d0868..cdff3d9 100644
--- a/arch/i386/cpu/interrupts.c
+++ b/arch/i386/cpu/interrupts.c
@@ -29,6 +29,7 @@
#include
#include
+#include
#define DECLARE_INTERRUPT(x) \
".globl irq_"#x"\n" \
@@ -108,6 +109,7 @@ void dump_regs(struct irq_regs *regs)
{
unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
unsigned long d0, d1, d2, d3, d6, d7;
+ unsigned long sp;
printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n",
(u16)regs->xcs, regs->eip, regs->eflags);
@@ -139,6 +141,20 @@ void dump_regs(struct irq_regs *regs)
d7 = get_debugreg(7);
printf("DR6: %08lx DR7: %08lx\n",
d6, d7);
+
+ printf("Stack:\n");
+ sp = regs->esp;
+
+ sp += 64;
+
+ while (sp > (regs->esp - 16)) {
+ if (sp == regs->esp)
+ printf("--->");
+ else
+ printf("");
+ printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp));
+ sp -= 4;
+ }
}
struct idt_entry {
--
1.7.1.422.g049e9
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[U-Boot] [PATCH 06/32] x86: Fix mangled umlauts
git mergetool has a nasty habit of mangling umlats - fix ones that have been missed in previous submissions Signed-off-by: Graeme Russ --- arch/i386/cpu/start.S |2 +- arch/i386/lib/board.c |2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/i386/cpu/start.S b/arch/i386/cpu/start.S index 829468f..ab9338a 100644 --- a/arch/i386/cpu/start.S +++ b/arch/i386/cpu/start.S @@ -1,7 +1,7 @@ /* * U-boot - i386 Startup Code * - * Copyright (c) 2002 Omicron Ceti AB, Daniel Engstr�m + * Copyright (c) 2002 Omicron Ceti AB, Daniel Engström * * See file CREDITS for list of people who contributed to this * project. diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c index 30cb9a2..2cadce8 100644 --- a/arch/i386/lib/board.c +++ b/arch/i386/lib/board.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2002 - * Daniel Engstr�m, Omicron Ceti AB, dan...@omicron.se + * Daniel Engström, Omicron Ceti AB, dan...@omicron.se * * (C) Copyright 2002 * Wolfgang Denk, DENX Software Engineering, w...@denx.de. -- 1.7.1.422.g049e9 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 04/32] x86: Parametize values used in linker script
Signed-off-by: Graeme Russ
---
arch/i386/config.mk |1 +
arch/i386/cpu/config.mk |6 ++
arch/i386/cpu/u-boot.lds | 24
arch/i386/lib/realmode.c |8
board/eNET/config.mk |1 +
5 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/arch/i386/config.mk b/arch/i386/config.mk
index 77a33dd..5a62a98 100644
--- a/arch/i386/config.mk
+++ b/arch/i386/config.mk
@@ -32,6 +32,7 @@ PLATFORM_CPPFLAGS += $(call cc-option, -fno-toplevel-reorder,
$(call cc-option,
PLATFORM_CPPFLAGS += $(call cc-option, -fno-stack-protector)
PLATFORM_CPPFLAGS += $(call cc-option, -mpreferred-stack-boundary=2)
PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm
+PLATFORM_CPPFLAGS += -DREALMODE_BASE=0x7c0
PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden
diff --git a/arch/i386/cpu/config.mk b/arch/i386/cpu/config.mk
index ec1d102..9b2e2c9 100644
--- a/arch/i386/cpu/config.mk
+++ b/arch/i386/cpu/config.mk
@@ -24,3 +24,9 @@
CROSS_COMPILE ?= i386-linux-
PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__ -march=i386 -Werror
+
+# DO NOT MODIFY THE FOLLOWING UNLESS YOU REALLY KNOW WHAT YOU ARE DOING!
+LDPPFLAGS += -DRESET_SEG_START=0x
+LDPPFLAGS += -DRESET_SEG_SIZE=0x1
+LDPPFLAGS += -DRESET_VEC_LOC=0xfff0
+LDPPFLAGS += -DSTART_16=0xf800
diff --git a/arch/i386/cpu/u-boot.lds b/arch/i386/cpu/u-boot.lds
index 3eeb2a2..98a548d 100644
--- a/arch/i386/cpu/u-boot.lds
+++ b/arch/i386/cpu/u-boot.lds
@@ -73,7 +73,7 @@ SECTIONS
/DISCARD/ : { *(.gnu*) }
/* 16bit realmode trampoline code */
- .realmode 0x7c0 : AT ( LOADADDR(.rel.dyn) + SIZEOF(.rel.dyn) ) {
KEEP(*(.realmode)) }
+ .realmode REALMODE_BASE : AT ( LOADADDR(.rel.dyn) + SIZEOF(.rel.dyn) )
{ KEEP(*(.realmode)) }
__realmode_start = LOADADDR(.realmode);
__realmode_size = SIZEOF(.realmode);
@@ -84,21 +84,13 @@ SECTIONS
__bios_start = LOADADDR(.bios);
__bios_size = SIZEOF(.bios);
- /* The load addresses below assumes that the flash
-* will be mapped so that 0x387f == 0x
-* at reset time
-*
-* The fe00 and ff00 offsets of the start32 and start16
-* segments are arbitrary, the just have to be mapped
-* at reset and the code have to fit.
-* The fff0 offset of resetvec is important, however.
+ /*
+* The following expressions place the 16-bit Real-Mode code and
+* Reset Vector at the end of the Flash ROM
*/
- . = 0xfe00;
- .start32 : AT (CONFIG_SYS_TEXT_BASE + 0x3fe00) { KEEP(*(.start32)); }
+ . = START_16;
+ .start16 : AT (CONFIG_SYS_TEXT_BASE + (FLASH_SIZE - RESET_SEG_SIZE +
START_16)) { KEEP(*(.start16)); }
- . = 0xf800;
- .start16 : AT (CONFIG_SYS_TEXT_BASE + 0x3f800) { KEEP(*(.start16)); }
-
- . = 0xfff0;
- .resetvec : AT (CONFIG_SYS_TEXT_BASE + 0x3fff0) { KEEP(*(.resetvec)); }
+ . = RESET_VEC_LOC;
+ .resetvec : AT (CONFIG_SYS_TEXT_BASE + (FLASH_SIZE - RESET_SEG_SIZE +
RESET_VEC_LOC)) { KEEP(*(.resetvec)); }
}
diff --git a/arch/i386/lib/realmode.c b/arch/i386/lib/realmode.c
index 60fe181..2dda95b 100644
--- a/arch/i386/lib/realmode.c
+++ b/arch/i386/lib/realmode.c
@@ -27,7 +27,6 @@
#include
-#define REALMODE_BASE((char*)0x7c0)
#define REALMODE_MAILBOX ((char*)0xe00)
@@ -41,13 +40,14 @@ int realmode_setup(void)
ulong realmode_size = (ulong)&__realmode_size;
/* copy the realmode switch code */
- if (realmode_size > (REALMODE_MAILBOX-REALMODE_BASE)) {
+ if (realmode_size > (REALMODE_MAILBOX - (char *)REALMODE_BASE)) {
printf("realmode switch too large (%ld bytes, max is %d)\n",
- realmode_size, (REALMODE_MAILBOX-REALMODE_BASE));
+ realmode_size,
+ (REALMODE_MAILBOX - (char *)REALMODE_BASE));
return -1;
}
- memcpy(REALMODE_BASE, (void*)realmode_start, realmode_size);
+ memcpy((char *)REALMODE_BASE, (void *)realmode_start, realmode_size);
asm("wbinvd\n");
return 0;
diff --git a/board/eNET/config.mk b/board/eNET/config.mk
index 4257141..9d2dfa5 100644
--- a/board/eNET/config.mk
+++ b/board/eNET/config.mk
@@ -21,3 +21,4 @@
# MA 02111-1307 USA
#
+LDPPFLAGS += -DFLASH_SIZE=0x4
--
1.7.1.422.g049e9
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[U-Boot] [PATCH 05/32] sc520: Sort Makefile
Signed-off-by: Graeme Russ --- arch/i386/cpu/sc520/Makefile |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/i386/cpu/sc520/Makefile b/arch/i386/cpu/sc520/Makefile index fb47c20..b962b02 100644 --- a/arch/i386/cpu/sc520/Makefile +++ b/arch/i386/cpu/sc520/Makefile @@ -32,9 +32,9 @@ include $(TOPDIR)/config.mk LIB:= $(obj)lib$(SOC).o COBJS-$(CONFIG_SYS_SC520) += sc520.o +COBJS-$(CONFIG_PCI) += sc520_pci.o COBJS-$(CONFIG_SYS_SC520_SSI) += sc520_ssi.o COBJS-$(CONFIG_SYS_SC520_TIMER) += sc520_timer.o -COBJS-$(CONFIG_PCI) += sc520_pci.o SOBJS-$(CONFIG_SYS_SC520) += sc520_asm.o -- 1.7.1.422.g049e9 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 03/32] eNET: Create distinct board configurations
Position independant functionality is due for removal from the x86 architecture, so create two distinct configurations - One for Flash and one for SRAM Signed-off-by: Graeme Russ --- board/eNET/config.mk |1 - boards.cfg |3 ++- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/eNET/config.mk b/board/eNET/config.mk index ce575ab..4257141 100644 --- a/board/eNET/config.mk +++ b/board/eNET/config.mk @@ -21,4 +21,3 @@ # MA 02111-1307 USA # -CONFIG_SYS_TEXT_BASE = 0x0600 diff --git a/boards.cfg b/boards.cfg index c3b164e..94347b1 100644 --- a/boards.cfg +++ b/boards.cfg @@ -199,7 +199,8 @@ ibf-dsp561 blackfinblackfin ip04 blackfinblackfin tcm-bf518blackfinblackfin tcm-bf537blackfinblackfin -eNET i386i386- - sc520 +eNET i386i386eNET- sc520 eNET:SYS_TEXT_BASE=0x3804 +eNET_SRAMi386i386eNET- sc520 eNET:SYS_TEXT_BASE=0x1900 idmr m68kmcf52x2 TASREG m68kmcf52x2 tasreg esd M5208EVBEm68kmcf52x2 m5208evbe freescale -- 1.7.1.422.g049e9 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 02/32] x86: Align config.mk and linker scripts with other arches
Signed-off-by: Graeme Russ
---
arch/i386/config.mk | 13 --
arch/i386/cpu/config.mk |4 +-
arch/i386/cpu/u-boot.lds | 104 ++
board/eNET/config.mk |4 --
board/eNET/u-boot.lds| 104 --
5 files changed, 114 insertions(+), 115 deletions(-)
create mode 100644 arch/i386/cpu/u-boot.lds
delete mode 100644 board/eNET/u-boot.lds
diff --git a/arch/i386/config.mk b/arch/i386/config.mk
index 3fb97c1..77a33dd 100644
--- a/arch/i386/config.mk
+++ b/arch/i386/config.mk
@@ -21,8 +21,6 @@
# MA 02111-1307 USA
#
-CROSS_COMPILE ?= i386-linux-
-
STANDALONE_LOAD_ADDR = 0x4
PLATFORM_CPPFLAGS += -fno-strict-aliasing
@@ -33,8 +31,13 @@ PLATFORM_CPPFLAGS += $(call cc-option, -ffreestanding)
PLATFORM_CPPFLAGS += $(call cc-option, -fno-toplevel-reorder, $(call
cc-option, -fno-unit-at-a-time))
PLATFORM_CPPFLAGS += $(call cc-option, -fno-stack-protector)
PLATFORM_CPPFLAGS += $(call cc-option, -mpreferred-stack-boundary=2)
-PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__
+PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm
+
+PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden
+
+PLATFORM_LDFLAGS += --emit-relocs -Bsymbolic -Bsymbolic-functions
LDFLAGS += --cref
-LDFLAGS_u-boot += --gc-sections
-PLATFORM_RELFLAGS += -ffunction-sections
+LDFLAGS_u-boot += --gc-sections -pie
+LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
+
diff --git a/arch/i386/cpu/config.mk b/arch/i386/cpu/config.mk
index 16a160d..ec1d102 100644
--- a/arch/i386/cpu/config.mk
+++ b/arch/i386/cpu/config.mk
@@ -21,6 +21,6 @@
# MA 02111-1307 USA
#
-PLATFORM_RELFLAGS +=
+CROSS_COMPILE ?= i386-linux-
-PLATFORM_CPPFLAGS += -march=i386 -Werror
+PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__ -march=i386 -Werror
diff --git a/arch/i386/cpu/u-boot.lds b/arch/i386/cpu/u-boot.lds
new file mode 100644
index 000..3eeb2a2
--- /dev/null
+++ b/arch/i386/cpu/u-boot.lds
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, dan...@omicron.se.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
+OUTPUT_ARCH(i386)
+ENTRY(_start)
+
+SECTIONS
+{
+ . = CONFIG_SYS_TEXT_BASE; /* Location of bootcode in flash */
+ __text_start = .;
+ .text : { *(.text*); }
+
+ . = ALIGN(4);
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ . = ALIGN(4);
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : { *(.data*) }
+
+ . = ALIGN(4);
+ .dynsym : { *(.dynsym*) }
+
+ . = ALIGN(4);
+ .hash : { *(.hash*) }
+
+ . = ALIGN(4);
+ .got : { *(.got*) }
+
+ . = ALIGN(4);
+ __data_end = .;
+
+ . = ALIGN(4);
+ __bss_start = ABSOLUTE(.);
+ .bss (NOLOAD) : { *(.bss) }
+ . = ALIGN(4);
+ __bss_end = ABSOLUTE(.);
+
+ . = ALIGN(4);
+ __rel_dyn_start = .;
+ .rel.dyn : { *(.rel.dyn) }
+ __rel_dyn_end = .;
+
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
+
+ /* 16bit realmode trampoline code */
+ .realmode 0x7c0 : AT ( LOADADDR(.rel.dyn) + SIZEOF(.rel.dyn) ) {
KEEP(*(.realmode)) }
+
+ __realmode_start = LOADADDR(.realmode);
+ __realmode_size = SIZEOF(.realmode);
+
+ /* 16bit BIOS emulation code (just enough to boot Linux) */
+ .bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) {
KEEP(*(.bios)) }
+
+ __bios_start = LOADADDR(.bios);
+ __bios_size = SIZEOF(.bios);
+
+ /* The load addresses below assumes that the flash
+* will be mapped so that 0x387f == 0x
+* at reset time
+*
+* The fe00 and ff00 offsets of the start32 and start16
+* segments are arbitrary, the just have to be mapped
+* at reset and the code have to fit.
+* The fff0 offset of resetvec is important, however.
+*/
+ . = 0xfe00;
+ .start32 : AT (CONF
[U-Boot] [PATCH 01/32] x86: Fix definition of global_data struct for asm-offsets.c
Signed-off-by: Graeme Russ
---
arch/i386/include/asm/global_data.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/i386/include/asm/global_data.h
b/arch/i386/include/asm/global_data.h
index e3f8a25..e9000c3 100644
--- a/arch/i386/include/asm/global_data.h
+++ b/arch/i386/include/asm/global_data.h
@@ -35,7 +35,7 @@
#ifndef __ASSEMBLY__
-typedefstruct {
+typedefstruct global_data {
bd_t*bd;
unsigned long flags;
unsigned long baudrate;
--
1.7.1.422.g049e9
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[U-Boot] [PATCH 00/32] Massive x86 Update - Bring x86 in line with ARM and PPC
This patch series marks a considerably significant milestone in the x86 port of U-Boot - Running the initial init sequence from Flash using the CPU on-die cache as a temporary stack. Prior to this patch series, the low-level assembler code running in Flash was responsible for initialising SDRAM and getting the C environment (the stack) set up. The C code would then simply copy the U-Boot image to RAM, do some relocation adjustments and jump into the in-RAM copy - only then would the init sequence run. Thank to the assistance of Juergen Beisert (who had done a Cache-As-RAM implementation for the sc520 quite some time ago), the x86 boot sequence is more 'standard': - Initialise Cache-As-RAM (CAR) - Setup a restricted 'C' environment - Setup initial global data in CAR - Run init sequence from Flash - Copy global data to a newly malloc'd block - Jump to RAM This patch does have three 'negative' impacts: - Boot time is slightly slower due to running the init sequence from Flash rather than SDRAM - The image is no longer position independent - If you want to create a warm-boot u-boot image, you need to link it to a different address - You can no longer do a warm-boot to a new u-boot image from SDARM (SDRAM is always re-initialised during the init sequence) Regards, Graeme Changes since RFC: - Ran checkpatch.pl and fixed (most) errors and warnings (a few long lines remain for readability and sc520_enable_ecc() in arch\i386\cpu\sc520 contains raw asm which is #ifdef'd out - This is ECC initialisation copied from the original asm file which is retained in case someone with ECC capable hardware (which I do not have) would care to implement properly - Merged some patches that logically belonged together - Added a code tidy-up for eNET - #defined all 'magic numbers' in the eNET configuration file - rebased to u-boot/master Graeme Russ (32): x86: Fix definition of global_data struct for asm-offsets.c x86: Align config.mk and linker scripts with other arches eNET: Create distinct board configurations x86: Parametize values used in linker script sc520: Sort Makefile x86: Fix mangled umlauts x86: Add stack dump to register dump x86: Move Global Descriptor Table defines to processor.h x86: Add processor flags header from linux x86: Call early_board_init when warm booting x86: Make cpu init functions weak sc520: Define MMCR address in include file sc520: Move board specific settings to board init function sc520: Remove printf calls from cpu_init_f eNET: Fix eNET Interrupt Setup for Linux eNET: Add RTC support to eNET eNET: Define MMCR values in config.h eNET: Rearrange PAR assignments eNET: General code cleanup x86: Move initial gd to fixed location x86: Use Cache-As-RAM for initial stack sc520: Move RAM sizing code from asm to C x86: Defer setup of final stack x86: Move call to dram_init_f into board_init_f x86: Move test for cold boot into init functions x86: Move console initialisation into board_init_f x86: Fix incorrect usage of relocation offset x86: Split board_init_f() into init_fnc_t compatible functions x86: Rearrange function calls in board_init_f x86: Convert board_init_f to use an init_sequence sc520: Release CAR and enable caching eNET: Move initial Global Data into CAR arch/i386/config.mk | 14 +- arch/i386/cpu/config.mk | 10 +- arch/i386/cpu/cpu.c | 35 +- arch/i386/cpu/interrupts.c | 19 +- arch/i386/cpu/sc520/Makefile|5 +- arch/i386/cpu/sc520/sc520.c | 148 +--- arch/i386/cpu/sc520/sc520_asm.S | 615 arch/i386/cpu/sc520/sc520_car.S | 94 + arch/i386/cpu/sc520/sc520_sdram.c | 532 arch/i386/cpu/start.S | 107 +++--- arch/i386/cpu/start16.S |5 +- arch/i386/cpu/u-boot.lds| 96 + arch/i386/include/asm/global_data.h | 21 +- arch/i386/include/asm/ic/sc520.h| 93 - arch/i386/include/asm/processor-flags.h | 100 + arch/i386/include/asm/processor.h |9 +- arch/i386/include/asm/u-boot-i386.h |3 + arch/i386/lib/board.c | 144 --- arch/i386/lib/realmode.c|8 +- board/eNET/config.mk|6 +- board/eNET/eNET.c | 192 + board/eNET/eNET_start.S |7 - board/eNET/eNET_start16.S | 15 +- board/eNET/u-boot.lds | 104 - boards.cfg |3 +- drivers/rtc/mc146818.c |6 + include/configs/eNET.h | 678 +++ 27 files changed, 1786 insertions(+), 1283 deletions(-) delete mode 100644 arch/i386/cpu/sc520/sc520_asm.S create mode 100644 arch/i386/cpu/sc520/sc520
[U-Boot] [PATCH] Fix gunzip to work for any gziped uImage size
Signed-off-by: Catalin Radu
---
lib/gunzip.c | 16 ++--
1 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/lib/gunzip.c b/lib/gunzip.c
index 482a476..8b16b24 100644
--- a/lib/gunzip.c
+++ b/lib/gunzip.c
@@ -106,12 +106,16 @@ int zunzip(void *dst, int dstlen, unsigned char *src,
unsigned long *lenp,
s.avail_in = *lenp - offset;
s.next_out = dst;
s.avail_out = dstlen;
- r = inflate(&s, Z_FINISH);
- if ((r != Z_STREAM_END) && (stoponerr==1)) {
- printf ("Error: inflate() returned %d\n", r);
- inflateEnd(&s);
- return (-1);
- }
+ do {
+ r = inflate(&s, Z_FINISH);
+ if (r != Z_STREAM_END && r != Z_BUF_ERROR && stoponerr == 1) {
+ printf("Error: inflate() returned %d\n", r);
+ inflateEnd(&s);
+ return -1;
+ }
+ s.avail_in = *lenp - offset - (int)(s.next_out - (unsigned
char*)dst);
+ s.avail_out = dstlen;
+ } while (r == Z_BUF_ERROR);
*lenp = s.next_out - (unsigned char *) dst;
inflateEnd(&s);
--
1.6.3.3
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Re: [U-Boot] [PATCH] Fix gunzip to work for any gziped uImage size
Anthony Foiani wrote:
> Catalin, greetings!
>
> Some very minor code style issues that I noticed. All cosmetic.
>
> Catalin Radu writes:
>
>
>> Signed-off-by: Catalin Radu
>> ---
>> lib/gunzip.c | 16 ++--
>> 1 files changed, 10 insertions(+), 6 deletions(-)
>>
>> diff --git a/lib/gunzip.c b/lib/gunzip.c
>> index 482a476..2922608 100644
>> --- a/lib/gunzip.c
>> +++ b/lib/gunzip.c
>> @@ -106,12 +106,16 @@ int zunzip(void *dst, int dstlen, unsigned char *src,
>> unsigned long *lenp,
>> s.avail_in = *lenp - offset;
>> s.next_out = dst;
>> s.avail_out = dstlen;
>> -r = inflate(&s, Z_FINISH);
>> -if ((r != Z_STREAM_END) && (stoponerr==1)) {
>> -printf ("Error: inflate() returned %d\n", r);
>> -inflateEnd(&s);
>> -return (-1);
>> -}
>> +do {
>> +r = inflate(&s, Z_FINISH);
>>
>
> Space after function name?
>
>
>> +if ((r != Z_STREAM_END)&& (r != Z_BUF_ERROR)&&
>> (stoponerr==1)) {
>>
>
> Inconsistent spacing around && operator.
>
> Parentheses around each condition are unnecessary (both "==" and "!="
> bind tighter than "&&"), but I suppose that's basically personal
> preference (and the code being replaced did it that way.)
>
>
>> +printf ("Error: inflate() returned %d\n", r);
>> +inflateEnd(&s);
>>
>
> Space after function name?
>
>
>> +return (-1);
>>
>
> These parentheses are unnecessary. (Another question of taste:
> "return" is a keyword, not a function.)
>
>
>> +}
>> +s.avail_in = *lenp - offset - (int)(s.next_out - (unsigned
>> char*)dst);
>> +s.avail_out = dstlen;
>> +} while (r == Z_BUF_ERROR);
>> *lenp = s.next_out - (unsigned char *) dst;
>> inflateEnd(&s);
>>
>
> Space after function name?
>
> As I said, all totally trivial, but especially those "&& " caught my eye. :)
>
> Best regards,
> Tony
>
Greetings Tony,
Thanks for the formatting observations. I will resend the re-formatted
patch.
Regards,
Catalin
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Re: [U-Boot] Uboot and memory test
Dear marku...@bredband.net, In message you wrote: > > This is a question related to memory testing from within Uboot: Actually this is not quite correct. Your question is a very general one and only artially related to U-Boot, if at all. > On a CPU (ppc476) there is 2 GB RAM which is tested in Uboot (the > operating system uses this memory). On the same CPU there is an > additional 256 MB memory chip which is used only by the IP-stack and not > the operating system. You are talking about some out-of-tree port, so we do not know either the actual code you are referring to nor the design criteria that were applied when creating this port - it is therefor impossible for us to know what U-Boot is doing on your board. Even if a certain RAM area is reserved for specal purposes in some OS this does not necessarily mean that this is true also for U-Boot. > The question is, should this 256 MB memory be > tested from Uboot or should the IP-stack test this memory? It depends on your specific requirements whether you test the memory at all, how thoroughly you test it (just using the basic test in get_ram_size() or the mtest variants or the full POST test code?), when and how often you test it (at boot, at shut down, at specific command? Only sometimes or always?), and which memory regions you include into the test. There are literally hundrets of systems in mainline wehre U-Boot does not perform any memory tests at all. The only clear answer I have for you is that it is certain that the IP stack shall NOT perform any memory tests. This is not what it was designed for. Well, yes, you can use a microscope as a hammer, but such use is strongly discouraged. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de If a train station is a place where a train stops, then what's a workstation? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Uboot and memory test
Hi, This is a question related to memory testing from within Uboot: On a CPU (ppc476) there is 2 GB RAM which is tested in Uboot (the operating system uses this memory). On the same CPU there is an additional 256 MB memory chip which is used only by the IP-stack and not the operating system. The question is, should this 256 MB memory be tested from Uboot or should the IP-stack test this memory? What is the advantage/disadvantages? Brs, Markus ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch 2/2] update EB+CPU9K2 board
* eb_cpux9k2: fix chip select initialization for frame buffer
(increase speed)
Signed-off-by: Jens Scharsig
---
board/BuS/eb_cpux9k2/cpux9k2.c |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/board/BuS/eb_cpux9k2/cpux9k2.c b/board/BuS/eb_cpux9k2/cpux9k2.c
index fe62a0f..d6acbbc 100644
--- a/board/BuS/eb_cpux9k2/cpux9k2.c
+++ b/board/BuS/eb_cpux9k2/cpux9k2.c
@@ -264,11 +264,12 @@ int drv_video_init(void)
display_height = 256;
printf("%ld x %ld pixel matrix\n", display_width, display_height);
- /* RWH = 7 | RWS =7 | TDF = 15 | NWS = 0x7F */
- csr = AT91_SMC_CSR_RWHOLD(7) | AT91_SMC_CSR_RWSETUP(7) |
- AT91_SMC_CSR_TDF(15) | AT91_SMC_CSR_NWS(127) |
+ /* RWH = 2 | RWS =2 | TDF = 4 | NWS = 0x6 */
+ csr = AT91_SMC_CSR_RWHOLD(2) | AT91_SMC_CSR_RWSETUP(2) |
+ AT91_SMC_CSR_TDF(4) | AT91_SMC_CSR_NWS(6) |
AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_16 |
AT91_SMC_CSR_BAT_16 | AT91_SMC_CSR_WSEN;
+
writel(csr, &mc->smc.csr[2]);
writel(1 << AT91_ID_PIOB, &pmc->pcer);
--
1.6.6.1
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