[U-Boot] [PATCH V5 6/6] I2C: add i2c support for Armada100 platform

2011-03-27 Thread Lei Wen 
Add i2c support to aspenite board with Armada100 soc.

Signed-off-by: Lei Wen 
---
Changelog:
V2:
NO CHANGE

V3:
clean code sytle issue
Add i2c clock enable code include in I2C configure define block

V4:
make i2c definition include in the ifdef

V5:
NO CHANGE

 arch/arm/cpu/arm926ejs/armada100/cpu.c|   16 +++
 arch/arm/include/asm/arch-armada100/mfp.h |   40 -
 board/Marvell/aspenite/aspenite.c |5 +++
 include/configs/aspenite.h|   14 ++
 4 files changed, 57 insertions(+), 18 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/armada100/cpu.c 
b/arch/arm/cpu/arm926ejs/armada100/cpu.c
index 62aa175..c21938e 100644
--- a/arch/arm/cpu/arm926ejs/armada100/cpu.c
+++ b/arch/arm/cpu/arm926ejs/armada100/cpu.c
@@ -62,6 +62,16 @@ int arch_cpu_init(void)
/* Enable GPIO clock */
writel(APBC_APBCLK, &apb1clkres->gpio);
 
+#ifdef CONFIG_I2C_MV
+   /* Enable general I2C clock */
+   writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
+   writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
+
+   /* Enable power I2C clock */
+   writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
+   writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
+#endif
+
/*
 * Enable Functional and APB clock at 14.7456MHz
 * for configured UART console
@@ -90,3 +100,9 @@ int print_cpuinfo(void)
return 0;
 }
 #endif
+
+#ifdef CONFIG_I2C_MV
+void i2c_clk_enable(void)
+{
+}
+#endif
diff --git a/arch/arm/include/asm/arch-armada100/mfp.h 
b/arch/arm/include/asm/arch-armada100/mfp.h
index d21a79f..73783a7 100644
--- a/arch/arm/include/asm/arch-armada100/mfp.h
+++ b/arch/arm/include/asm/arch-armada100/mfp.h
@@ -37,28 +37,32 @@
  * offset, pull,pF, drv,dF, edge,eF ,afn,aF
  */
 /* UART1 */
-#define MFP107_UART1_TXD   MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST
-#define MFP107_UART1_RXD   MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST
-#define MFP108_UART1_RXD   MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST
-#define MFP108_UART1_TXD   MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST
-#define MFP109_UART1_CTS   MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM
-#define MFP109_UART1_RTS   MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM
-#define MFP110_UART1_RTS   MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM
-#define MFP110_UART1_CTS   MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM
-#define MFP111_UART1_RIMFP_REG(0x01bc) | MFP_AF1 | 
MFP_DRIVE_MEDIUM
-#define MFP111_UART1_DSR   MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM
-#define MFP112_UART1_DTR   MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM
-#define MFP112_UART1_DCD   MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM
+#define MFP107_UART1_TXD   (MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST)
+#define MFP107_UART1_RXD   (MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST)
+#define MFP108_UART1_RXD   (MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST)
+#define MFP108_UART1_TXD   (MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST)
+#define MFP109_UART1_CTS   (MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MFP109_UART1_RTS   (MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFP110_UART1_RTS   (MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MFP110_UART1_CTS   (MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFP111_UART1_RI(MFP_REG(0x01bc) | MFP_AF1 | 
MFP_DRIVE_MEDIUM)
+#define MFP111_UART1_DSR   (MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFP112_UART1_DTR   (MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MFP112_UART1_DCD   (MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM)
 
 /* UART2 */
-#define MFP47_UART2_RXDMFP_REG(0x0028) | MFP_AF6 | 
MFP_DRIVE_MEDIUM
-#define MFP48_UART2_TXDMFP_REG(0x002c) | MFP_AF6 | 
MFP_DRIVE_MEDIUM
-#define MFP88_UART2_RXDMFP_REG(0x0160) | MFP_AF2 | 
MFP_DRIVE_MEDIUM
-#define MFP89_UART2_TXDMFP_REG(0x0164) | MFP_AF2 | 
MFP_DRIVE_MEDIUM
+#define MFP47_UART2_RXD(MFP_REG(0x0028) | MFP_AF6 | 
MFP_DRIVE_MEDIUM)
+#define MFP48_UART2_TXD(MFP_REG(0x002c) | MFP_AF6 | 
MFP_DRIVE_MEDIUM)
+#define MFP88_UART2_RXD(MFP_REG(0x0160) | MFP_AF2 | 
MFP_DRIVE_MEDIUM)
+#define MFP89_UART2_TXD(MFP_REG(0x0164) | MFP_AF2 | 
MFP_DRIVE_MEDIUM)
 
 /* UART3 */
-#define MFPO8_UART3_RXDMFP_REG(0x06c) | MFP_AF2 | 
MFP_DRIVE_MEDIUM
-#define MFPO9_UART3_TXDMFP_REG(0x070) | MFP_AF2 | 
MFP_DRIVE_MEDIUM
+#define MFPO8_UART3_RXD(MFP_REG(0x06c) | MFP_AF2 | 
MFP_DRIVE_MEDIUM)
+#define MFPO9_UART3_TXD(MFP_REG(0x070) | MFP_AF2 | 
MFP_DRIVE_MEDIUM)
+
+/* I2c */
+#define MFP105_CI2C_SDA(MFP_REG(0x1a4) | MFP_AF1 | 
MFP_DRIVE_MEDIUM)
+#define MFP106_CI2C_SCL(MFP_REG(0x1a8) | MFP_AF1 | 
MFP_DRIVE_

[U-Boot] [PATCH V5 5/6] I2C: mv_i2c: add multi bus support

2011-03-27 Thread Lei Wen 
Add the ability to support multiple i2c bus for mv_i2c

Signed-off-by: Lei Wen 
---
Changelog:
V2:
NO CHANGE

V3:
clean code style issue

V4:
V5:
NO CHANGE

 drivers/i2c/mv_i2c.c |   36 +++-
 1 files changed, 35 insertions(+), 1 deletions(-)

diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c
index 734148b..7a808c9 100644
--- a/drivers/i2c/mv_i2c.c
+++ b/drivers/i2c/mv_i2c.c
@@ -66,7 +66,35 @@ struct pxa_i2c {
u32 isar;
 };
 
-static struct pxa_i2c *base = (struct pxa_i2c *)CONFIG_PXA_I2C_REG;
+static struct pxa_i2c *base;
+#ifdef CONFIG_I2C_MULTI_BUS
+static u32 i2c_regs[CONFIG_PXA_I2C_NUM] = CONFIG_PXA_I2C_REG;
+static unsigned int bus_initialized[CONFIG_PXA_I2C_NUM];
+static unsigned int current_bus;
+
+int i2c_set_bus_num(unsigned int bus)
+{
+   if ((bus < 0) || (bus >= CONFIG_PXA_I2C_NUM)) {
+   printf("Bad bus: %d\n", bus);
+   return -1;
+   }
+
+   base = (struct pxa_i2c *)i2c_regs[bus];
+   current_bus = bus;
+
+   if (!bus_initialized[current_bus]) {
+   i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+   bus_initialized[current_bus] = 1;
+   }
+
+   return 0;
+}
+
+unsigned int i2c_get_bus_num(void)
+{
+   return current_bus;
+}
+#endif
 
 /*
  * i2c_pxa_reset: - reset the host controller
@@ -235,6 +263,12 @@ i2c_transfer_finish:
 /*  */
 void i2c_init(int speed, int slaveaddr)
 {
+#ifdef CONFIG_I2C_MULTI_BUS
+   base = (struct pxa_i2c *)i2c_regs[current_bus];
+#else
+   base = (struct pxa_i2c *)CONFIG_PXA_I2C_REG;
+#endif
+
 #ifdef CONFIG_SYS_I2C_INIT_BOARD
u32 icr;
/* call board specific i2c bus reset routine before accessing the   */
-- 
1.7.0.4

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[U-Boot] [PATCH V5 2/6] pxa: move i2c driver to the common place

2011-03-27 Thread Lei Wen 
For better sharing with other platform other than pxa's,
it is more convenient to put the driver to the common place.

Signed-off-by: Lei Wen 
---
Changelog:
v2: rename previous pxa_i2c to mvi2c.

V3: change previous name from pxa_i2c to mv_i2c
clean code style issue exist in original code

V4:
V5:
NO CHANGE

 arch/arm/cpu/pxa/Makefile |1 -
 arch/arm/cpu/pxa/i2c.c|  469 -
 drivers/i2c/Makefile  |1 +
 drivers/i2c/mv_i2c.c  |  452 +++
 include/configs/innokom.h |1 +
 include/configs/xm250.h   |1 +
 6 files changed, 455 insertions(+), 470 deletions(-)
 delete mode 100644 arch/arm/cpu/pxa/i2c.c
 create mode 100644 drivers/i2c/mv_i2c.c

diff --git a/arch/arm/cpu/pxa/Makefile b/arch/arm/cpu/pxa/Makefile
index 49a6ed3..e8b59a3 100644
--- a/arch/arm/cpu/pxa/Makefile
+++ b/arch/arm/cpu/pxa/Makefile
@@ -28,7 +28,6 @@ LIB   = $(obj)lib$(CPU).o
 START  = start.o
 
 COBJS  += cpu.o
-COBJS  += i2c.o
 COBJS  += pxafb.o
 COBJS  += timer.o
 COBJS  += usb.o
diff --git a/arch/arm/cpu/pxa/i2c.c b/arch/arm/cpu/pxa/i2c.c
deleted file mode 100644
index 7aa49ae..000
--- a/arch/arm/cpu/pxa/i2c.c
+++ /dev/null
@@ -1,469 +0,0 @@
-/*
- * (C) Copyright 2000
- * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arse...@tin.it
- *
- * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH 
- * Marius Groeger 
- *
- * (C) Copyright 2003 Pengutronix e.K.
- * Robert Schwebel 
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Back ported to the 8xx platform (from the 8260 platform) by
- * murray.jen...@cmst.csiro.au, 27-Jan-01.
- */
-
-/* FIXME: this file is PXA255 specific! What about other XScales? */
-
-#include 
-#include 
-
-#ifdef CONFIG_HARD_I2C
-
-/*
- * - CONFIG_SYS_I2C_SPEED
- * - I2C_PXA_SLAVE_ADDR
- */
-
-#include 
-#include 
-#include 
-
-/*#define  DEBUG_I2C   1   /###* activate local debugging output  
*/
-#define I2C_PXA_SLAVE_ADDR 0x1 /* slave pxa unit address   */
-
-#if (CONFIG_SYS_I2C_SPEED == 40)
-#define I2C_ICR_INIT   (ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | 
ICR_SCLE)
-#else
-#define I2C_ICR_INIT   (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
-#endif
-
-#define I2C_ISR_INIT   0x7FF
-
-#ifdef DEBUG_I2C
-#define PRINTD(x) printf x
-#else
-#define PRINTD(x)
-#endif
-
-
-/* Shall the current transfer have a start/stop condition? */
-#define I2C_COND_NORMAL0
-#define I2C_COND_START 1
-#define I2C_COND_STOP  2
-
-/* Shall the current transfer be ack/nacked or being waited for it? */
-#define I2C_ACKNAK_WAITACK 1
-#define I2C_ACKNAK_SENDACK 2
-#define I2C_ACKNAK_SENDNAK 4
-
-/* Specify who shall transfer the data (master or slave) */
-#define I2C_READ   0
-#define I2C_WRITE  1
-
-/* All transfers are described by this data structure */
-struct i2c_msg {
-   u8 condition;
-   u8 acknack;
-   u8 direction;
-   u8 data;
-};
-
-
-/**
- * i2c_pxa_reset: - reset the host controller
- *
- */
-
-static void i2c_reset( void )
-{
-   writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */
-   writel(readl(ICR) | ICR_UR, ICR);   /* reset the unit */
-   udelay(100);
-   writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */
-#ifdef CONFIG_CPU_MONAHANS
-   /* | CKENB_1_PWM1 | CKENB_0_PWM0); */
-   writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
-#else /* CONFIG_CPU_MONAHANS */
-   /* set the global I2C clock on */
-   writel(readl(CKEN) | CKEN14_I2C, CKEN);
-#endif
-   writel(I2C_PXA_SLAVE_ADDR, ISAR);   /* set our slave address */
-   writel(I2C_ICR_INIT, ICR);  /* set control reg values */
-   writel(I2C_ISR_INIT, ISR);  /* set clear interrupt bits */
-   writel(readl(ICR) | ICR_IUE, ICR);  /* enable unit */
-   udelay(100);
-}
-
-
-/**
- * i2c_isr_set_cleared: - wait until certain bits of the I2C status register
- *   are set and cleared
- *
- * @return: 1 in case of success, 0 means timeout (no match within 10 ms).
- */
-static int i2c_isr_set_cleared( unsigned long set_mask, unsigned long 
clear

[U-Boot] [PATCH V5 3/6] mv_i2c: use structure to replace the direclty define

2011-03-27 Thread Lei Wen 
Add i2c_clk_enable in the cpu specific code, since previous platform it,
while new platform don't need. In the pantheon and armada100 platform,
this function is defined as NULL one.

Signed-off-by: Lei Wen 
---
Changelog:
V2:
NO CHANGE

V3:
clean code sytle issue

V4:
V5:
NO CHANGE

 arch/arm/cpu/pxa/cpu.c   |   11 +++
 arch/arm/include/asm/arch-pxa/pxa-regs.h |   56 -
 board/innokom/innokom.c  |9 +--
 drivers/i2c/mv_i2c.c |  131 ++
 drivers/i2c/mv_i2c.h |   83 +++
 include/configs/innokom.h|1 +
 include/configs/xm250.h  |1 +
 7 files changed, 159 insertions(+), 133 deletions(-)
 create mode 100644 drivers/i2c/mv_i2c.h

diff --git a/arch/arm/cpu/pxa/cpu.c b/arch/arm/cpu/pxa/cpu.c
index 7d49cbb..24b59e7 100644
--- a/arch/arm/cpu/pxa/cpu.c
+++ b/arch/arm/cpu/pxa/cpu.c
@@ -318,3 +318,14 @@ int arch_cpu_init(void)
pxa_clock_setup();
return 0;
 }
+
+void i2c_clk_enable(void)
+{
+#ifdef CONFIG_CPU_MONAHANS
+   /* | CKENB_1_PWM1 | CKENB_0_PWM0); */
+   writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
+#else /* CONFIG_CPU_MONAHANS */
+   /* set the global I2C clock on */
+   writel(readl(CKEN) | CKEN14_I2C, CKEN);
+#endif
+}
diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h 
b/arch/arm/include/asm/arch-pxa/pxa-regs.h
index 65a387f..109fdc0 100644
--- a/arch/arm/include/asm/arch-pxa/pxa-regs.h
+++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h
@@ -456,62 +456,6 @@ typedef void   (*ExcpHndlr) (void) ;
IrSR_XMITIR_IR_MODE)
 
 /*
- * I2C registers
- */
-#define IBMR   0x40301680  /* I2C Bus Monitor Register - IBMR */
-#define IDBR   0x40301688  /* I2C Data Buffer Register - IDBR */
-#define ICR0x40301690  /* I2C Control Register - ICR */
-#define ISR0x40301698  /* I2C Status Register - ISR */
-#define ISAR   0x403016A0  /* I2C Slave Address Register - ISAR */
-
-#ifdef CONFIG_CPU_MONAHANS
-#define PWRIBMR0x40f500C0  /* Power I2C Bus Monitor 
Register-IBMR */
-#define PWRIDBR0x40f500C4  /* Power I2C Data Buffer 
Register-IDBR */
-#define PWRICR 0x40f500C8  /* Power I2C Control Register - ICR */
-#define PWRISR 0x40f500CC  /* Power I2C Status Register - ISR */
-#define PWRISAR0x40f500D0  /* Power I2C Slave Address 
Register-ISAR */
-#else
-#define PWRIBMR0x40f00180  /* Power I2C Bus Monitor 
Register-IBMR */
-#define PWRIDBR0x40f00188  /* Power I2C Data Buffer 
Register-IDBR */
-#define PWRICR 0x40f00190  /* Power I2C Control Register - ICR */
-#define PWRISR 0x40f00198  /* Power I2C Status Register - ISR */
-#define PWRISAR0x40f001A0  /* Power I2C Slave Address 
Register-ISAR */
-#endif
-
-/* - Control register bits  */
-
-#define ICR_START  0x1 /* start bit */
-#define ICR_STOP   0x2 /* stop bit */
-#define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */
-#define ICR_TB 0x8 /* transfer byte bit */
-#define ICR_MA 0x10/* master abort */
-#define ICR_SCLE   0x20/* master clock enable, mona SCLEA */
-#define ICR_IUE0x40/* unit enable */
-#define ICR_GCD0x80/* general call disable */
-#define ICR_ITEIE  0x100   /* enable tx interrupts */
-#define ICR_IRFIE  0x200   /* enable rx interrupts, mona: DRFIE */
-#define ICR_BEIE   0x400   /* enable bus error ints */
-#define ICR_SSDIE  0x800   /* slave STOP detected int enable */
-#define ICR_ALDIE  0x1000  /* enable arbitration interrupt */
-#define ICR_SADIE  0x2000  /* slave address detected int enable */
-#define ICR_UR 0x4000  /* unit reset */
-#define ICR_FM 0x8000  /* Fast Mode */
-
-/* - Status register bits - */
-
-#define ISR_RWM0x1 /* read/write mode */
-#define ISR_ACKNAK 0x2 /* ack/nak status */
-#define ISR_UB 0x4 /* unit busy */
-#define ISR_IBB0x8 /* bus busy */
-#define ISR_SSD0x10/* slave stop detected */
-#define ISR_ALD0x20/* arbitration loss detected */
-#define ISR_ITE0x40/* tx buffer empty */
-#define ISR_IRF0x80/* rx buffer full */
-#define ISR_GCAD   0x100   /* general call address detected */
-#define ISR_SAD0x200   /* slave address detected */
-#define ISR_BED0x400   /* bus error no ACK/NAK */
-
-/*
  * Serial Audio Controller
  */
 /* FIXME the audio defin

[U-Boot] [PATCH V5 4/6] I2C: add i2c support for Pantheon platform

2011-03-27 Thread Lei Wen 
Add i2c support to dkb board with pantheon soc.

Signed-off-by: Lei Wen 
---
Changelog:
V2:
NO CHANGE

V3:
clean code sytle issue
Add i2c clock enable code include in I2C configure define block

V4:
make i2c definition included in the ifdef

V5:
NO CHANGE

 arch/arm/cpu/arm926ejs/pantheon/cpu.c|   12 
 arch/arm/include/asm/arch-pantheon/cpu.h |4 +++-
 arch/arm/include/asm/arch-pantheon/mfp.h |6 --
 board/Marvell/dkb/dkb.c  |4 
 include/configs/dkb.h|   13 +
 5 files changed, 36 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c 
b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
index 9ddc77c..8b2eafa 100644
--- a/arch/arm/cpu/arm926ejs/pantheon/cpu.c
+++ b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
@@ -59,6 +59,12 @@ int arch_cpu_init(void)
/* Enable GPIO clock */
writel(APBC_APBCLK, &apbclkres->gpio);
 
+#ifdef CONFIG_I2C_MV
+   /* Enable I2C clock */
+   writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
+   writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
+#endif
+
icache_enable();
 
return 0;
@@ -76,3 +82,9 @@ int print_cpuinfo(void)
return 0;
 }
 #endif
+
+#ifdef CONFIG_I2C_MV
+void i2c_clk_enable(void)
+{
+}
+#endif
diff --git a/arch/arm/include/asm/arch-pantheon/cpu.h 
b/arch/arm/include/asm/arch-pantheon/cpu.h
index 30f4393..60955c5 100644
--- a/arch/arm/include/asm/arch-pantheon/cpu.h
+++ b/arch/arm/include/asm/arch-pantheon/cpu.h
@@ -50,7 +50,9 @@ struct panthapb_registers {
u32 uart0;  /*0x000*/
u32 uart1;  /*0x004*/
u32 gpio;   /*0x008*/
-   u8 pad0[0x034 - 0x08 - 4];
+   u8 pad0[0x02c - 0x08 - 4];
+   u32 twsi;   /*0x02c*/
+   u8 pad1[0x034 - 0x2c - 4];
u32 timers; /*0x034*/
 };
 
diff --git a/arch/arm/include/asm/arch-pantheon/mfp.h 
b/arch/arm/include/asm/arch-pantheon/mfp.h
index fb291cf..e939196 100644
--- a/arch/arm/include/asm/arch-pantheon/mfp.h
+++ b/arch/arm/include/asm/arch-pantheon/mfp.h
@@ -32,8 +32,10 @@
  * offset, pull,pF, drv,dF, edge,eF ,afn,aF
  */
 /* UART2 */
-#define MFP47_UART2_RXDMFP_REG(0x198) | MFP_AF6 | 
MFP_DRIVE_MEDIUM
-#define MFP48_UART2_TXDMFP_REG(0x19c) | MFP_AF6 | 
MFP_DRIVE_MEDIUM
+#define MFP47_UART2_RXD(MFP_REG(0x198) | MFP_AF6 | 
MFP_DRIVE_MEDIUM)
+#define MFP48_UART2_TXD(MFP_REG(0x19c) | MFP_AF6 | 
MFP_DRIVE_MEDIUM)
+#define MFP53_CI2C_SCL (MFP_REG(0x1b0) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFP54_CI2C_SDA (MFP_REG(0x1b4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
 
 /* More macros can be defined here... */
 
diff --git a/board/Marvell/dkb/dkb.c b/board/Marvell/dkb/dkb.c
index 72a2d2a..00f73e7 100644
--- a/board/Marvell/dkb/dkb.c
+++ b/board/Marvell/dkb/dkb.c
@@ -36,6 +36,10 @@ int board_early_init_f(void)
MFP47_UART2_RXD,
MFP48_UART2_TXD,
 
+   /* I2C */
+   MFP53_CI2C_SCL,
+   MFP54_CI2C_SDA,
+
MFP_EOC /*End of configureation*/
};
/* configure MFP's */
diff --git a/include/configs/dkb.h b/include/configs/dkb.h
index 638af5e..599c8b8 100644
--- a/include/configs/dkb.h
+++ b/include/configs/dkb.h
@@ -56,6 +56,19 @@
 #include "mv-common.h"
 
 #undef CONFIG_ARCH_MISC_INIT
+
+/*
+ * I2C definition
+ */
+#define CONFIG_CMD_I2C
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_I2C_MV  1
+#define CONFIG_PXA_I2C_REG 0xd4011000
+#define CONFIG_HARD_I2C1
+#define CONFIG_SYS_I2C_SPEED   0
+#define CONFIG_SYS_I2C_SLAVE   0xfe
+#endif
+
 /*
  * Environment variables configurations
  */
-- 
1.7.0.4

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[U-Boot] [PATCH V5 1/6] io: add and* and or* operation api to set and clear bit

2011-03-27 Thread Lei Wen 
Those api take use of read*/write* to align the current dmb usage.
Also this could short the code length in one line.

Signed-off-by: Lei Wen 
---
Changelog:
V2:
V3:
V4:
Move original driver specific bit set to the general place

V5:
fix code style issue

 arch/arm/include/asm/io.h |8 
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 1fbc531..71e85e8 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -141,6 +141,14 @@ extern inline void __raw_readsl(unsigned int addr, void 
*data, int longlen)
 #define readw(c)   ({ u16 __v = __arch_getw(c); __iormb(); __v; })
 #define readl(c)   ({ u32 __v = __arch_getl(c); __iormb(); __v; })
 
+#define orb(v, c)   writeb(readb(c) | v, c)
+#define orw(v, c)   writew(readw(c) | v, c)
+#define orl(v, c)   writel(readl(c) | v, c)
+
+#define andb(v, c)  writeb(readb(c) & v, c)
+#define andw(v, c)  writew(readw(c) & v, c)
+#define andl(v, c)  writel(readl(c) & v, c)
+
 /*
  * The compiler seems to be incapable of optimising constants
  * properly.  Spell it out to the compiler in some cases.
-- 
1.7.0.4

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[U-Boot] [PATCH V5 0/6] add i2c support to pantheon and aramada100

2011-03-27 Thread Lei Wen 
V2:
rename the previous pxa_i2c to mvi2c, since this driver would be shared
by many other Marvell platforms.

V3:
Clean the code sytle issue

V4:
add and* and or* to make set bit operation generic
Also make i2c definition included in the ifdef

V5:
Fix code style issue of the first patch
 
Lei Wen (6):
  io: add and* and or* operation api to set and clear bit
  pxa: move i2c driver to the common place
  mv_i2c: use structure to replace the direclty define
  I2C: add i2c support for Pantheon platform
  I2C: mv_i2c: add multi bus support
  I2C: add i2c support for Armada100 platform

 arch/arm/cpu/arm926ejs/armada100/cpu.c|   16 +
 arch/arm/cpu/arm926ejs/pantheon/cpu.c |   12 +
 arch/arm/cpu/pxa/Makefile |1 -
 arch/arm/cpu/pxa/cpu.c|   11 +
 arch/arm/cpu/pxa/i2c.c|  469 
 arch/arm/include/asm/arch-armada100/mfp.h |   40 ++-
 arch/arm/include/asm/arch-pantheon/cpu.h  |4 +-
 arch/arm/include/asm/arch-pantheon/mfp.h  |6 +-
 arch/arm/include/asm/arch-pxa/pxa-regs.h  |   56 
 arch/arm/include/asm/io.h |8 +
 board/Marvell/aspenite/aspenite.c |5 +
 board/Marvell/dkb/dkb.c   |4 +
 board/innokom/innokom.c   |9 +-
 drivers/i2c/Makefile  |1 +
 drivers/i2c/mv_i2c.c  |  479 +
 drivers/i2c/mv_i2c.h  |   83 +
 include/configs/aspenite.h|   14 +
 include/configs/dkb.h |   13 +
 include/configs/innokom.h |2 +
 include/configs/xm250.h   |2 +
 20 files changed, 680 insertions(+), 555 deletions(-)
 delete mode 100644 arch/arm/cpu/pxa/i2c.c
 create mode 100644 drivers/i2c/mv_i2c.c
 create mode 100644 drivers/i2c/mv_i2c.h

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Re: [U-Boot] current head don;t compile for mpc52xx based boards

2011-03-27 Thread Wolfgang Denk 
Dear Heiko Schocher,

In message <4d90289f.2000...@denx.de> you wrote:
> 
> actual head doesn;t longer compile for the mpc52xx based
> digsy_mtc_rev5 board (and a fast check, it seems it is
> for mp52xx, 8xx, ppc4xx based boards):

I think ALL PowerPC boards are affecte.

Po-Yu Chuang, can you please look into this, it's urgent?

Best regards,

Wolfgang Denk

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Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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To steal ideas from one person is plagiarism; to steal from
many is research.
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Re: [U-Boot] [PATCH V4 1/6] io: add and* and or* operation api to set and clear bit

2011-03-27 Thread Wolfgang Denk 
Dear Lei Wen,

In message <1301292225-15069-1-git-send-email-lei...@marvell.com> you wrote:
> Those api take use of read*/write* to align the current dmb usage.
> Also this could short the code length in one line.
> 
> Signed-off-by: Lei Wen 
> ---
> Changelog:
> V4.1
> fix code style issue

That should be V4.1 (or better V5) in the Subject then, too.


Please also note that all your patches are missing a correct
changelog.

1/6 has no changelog at all.
2/6 fails to document the v4 changes
3/6 shows only V3 changes
4/6 ditto
5/6 ditto
6/6 ditto 

This is not acceptable.  I do not intend to read and compare ll the
previous versions, so I refuse to review this.

You may consider this a NAK to the whole patch series.

Best regards,

Wolfgang Denk

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Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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someday it will have to be maintained."
- The Tao of Programming
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[U-Boot] [PATCH 0/2] rtc, rv3029: add support for trickle charger

2011-03-27 Thread Heiko Schocher 
This patchseries adds trickle charger support for the
RTC RV3029 and add it to the existing digsy_mtc board
(rev5 boards only).

checkpatch says:

total: 0 errors, 0 warnings, 117 lines checked

20110328/0001-rtc-rv3029-add-trickle-charger-support.patch has no obvious style 
problems and is ready for submission.
total: 0 errors, 0 warnings, 7 lines checked

20110328/0002-mpc52xx-digsy_mtc-add-trickle-charger-support-for-re.patch has no 
obvious style problems and is ready for submission.

Heiko Schocher (2):
  rtc, rv3029: add trickle charger support.
  mpc52xx, digsy_mtc: add trickle charger support for rev5 boards.

 README  |2 +
 drivers/rtc/rv3029.c|   87 +++
 include/configs/digsy_mtc.h |1 +
 3 files changed, 90 insertions(+), 0 deletions(-)

-- 
1.7.4

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[U-Boot] [PATCH 1/2] rtc, rv3029: add trickle charger support.

2011-03-27 Thread Heiko Schocher 
Signed-off-by: Heiko Schocher 
---
 README   |2 +
 drivers/rtc/rv3029.c |   87 ++
 2 files changed, 89 insertions(+), 0 deletions(-)

diff --git a/README b/README
index 21cd71b..45b32e7 100644
--- a/README
+++ b/README
@@ -743,6 +743,8 @@ The following options need to be configured:
CONFIG_RTC_ISL1208  - use Intersil ISL1208 RTC
CONFIG_RTC_MAX6900  - use Maxim, Inc. MAX6900 RTC
CONFIG_SYS_RTC_DS1337_NOOSC - Turn off the OSC output for 
DS1337
+   CONFIG_SYS_RV3029_TCR   - enable trickle charger on
+ RV3029 RTC.
 
Note that if the RTC uses I2C, then the I2C interface
must also be configured. See I2C Support, below.
diff --git a/drivers/rtc/rv3029.c b/drivers/rtc/rv3029.c
index 3ebc768..e012168 100644
--- a/drivers/rtc/rv3029.c
+++ b/drivers/rtc/rv3029.c
@@ -25,6 +25,12 @@
 #include 
 #include 
 
+#define RTC_RV3029_CTRL1   0x00
+#define RTC_RV3029_CTRL1_EERE  (1 << 3)
+
+#define RTC_RV3029_CTRL_STATUS 0x03
+#define RTC_RV3029_CTRLS_EEBUSY(1 << 7)
+
 #define RTC_RV3029_CTRL_RESET  0x04
 #define RTC_RV3029_CTRL_SYS_R  (1 << 4)
 
@@ -42,6 +48,12 @@
 #define RV3029C2_REG_HR_12_24  (1 << 6)  /* 24h/12h mode */
 #define RV3029C2_REG_HR_PM (1 << 5)  /* PM/AM bit in 12h mode */
 
+#define RTC_RV3029_EEPROM_CTRL 0x30
+#define RTC_RV3029_TRICKLE_1K  (1 << 4)
+#define RTC_RV3029_TRICKLE_5K  (1 << 5)
+#define RTC_RV3029_TRICKLE_20K (1 << 6)
+#define RTC_RV3029_TRICKLE_80K (1 << 7)
+
 int rtc_get( struct rtc_time *tmp )
 {
int ret;
@@ -113,6 +125,41 @@ int rtc_set( struct rtc_time *tmp )
return 0;
 }
 
+/* sets EERE-Bit  (automatic EEPROM refresh) */
+static void set_eere_bit(int state)
+{
+   int ret;
+   unsigned char reg_ctrl1;
+
+   ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_CTRL1, 1,
+   ®_ctrl1, 1);
+
+   if (state)
+   reg_ctrl1 |= RTC_RV3029_CTRL1_EERE;
+   else
+   reg_ctrl1 &= (~RTC_RV3029_CTRL1_EERE);
+
+   ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_CTRL1, 1,
+   ®_ctrl1, 1);
+}
+
+/* waits until EEPROM page is no longer busy (times out after 10ms*loops) */
+static int wait_eebusy(int loops)
+{
+   int i, ret;
+   unsigned char ctrl_status;
+
+   for (i = 0; i < loops; i++) {
+   ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_CTRL_STATUS,
+   1, &ctrl_status, 1);
+
+   if ((ctrl_status & RTC_RV3029_CTRLS_EEBUSY) == 0)
+   break;
+   udelay(1);
+   }
+   return i;
+}
+
 void rtc_reset (void)
 {
int ret;
@@ -121,4 +168,44 @@ void rtc_reset (void)
buf[0] = RTC_RV3029_CTRL_SYS_R;
ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_CTRL_RESET, 1,
buf, 1);
+
+#if defined(CONFIG_SYS_RV3029_TCR)
+   /*
+* because EEPROM_CTRL register is in EEPROM page it is necessary to
+* disable automatic EEPROM refresh and check if EEPROM is busy
+* before EEPORM_CTRL register may be accessed
+*/
+   set_eere_bit(0);
+   wait_eebusy(100);
+   /* read current trickle charger setting */
+   ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_EEPROM_CTRL,
+   1, buf, 1);
+   /* enable automatic EEPROM refresh again */
+   set_eere_bit(1);
+
+   /*
+* to minimize EEPROM access write trickle charger setting only if it
+* differs from current value
+*/
+   if ((buf[0] & 0xF0) != CONFIG_SYS_RV3029_TCR) {
+   buf[0] = (buf[0] & 0x0F) | CONFIG_SYS_RV3029_TCR;
+   /*
+* write trickle charger setting (disable autom. EEPROM
+* refresh and wait until EEPROM is idle)
+*/
+   set_eere_bit(0);
+   wait_eebusy(100);
+   ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR,
+   RTC_RV3029_EEPROM_CTRL, 1, buf, 1);
+   /*
+* it is necessary to wait 10ms before EEBUSY-Bit may be read
+* (this is not documented in the data sheet yet, but the
+* manufacturer recommends it)
+*/
+   udelay(1);
+   /* wait until EEPROM write access is finished */
+   wait_eebusy(100);
+   set_eere_bit(1);
+   }
+#endif
 }
-- 
1.7.4

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[U-Boot] [PATCH 2/2] mpc52xx, digsy_mtc: add trickle charger support for rev5 boards.

2011-03-27 Thread Heiko Schocher 
Signed-off-by: Heiko Schocher 
---
 include/configs/digsy_mtc.h |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h
index e7fd0f7..7e50a86 100644
--- a/include/configs/digsy_mtc.h
+++ b/include/configs/digsy_mtc.h
@@ -252,6 +252,7 @@
 #if defined(CONFIG_DIGSY_REV5)
 #define CONFIG_SYS_I2C_RTC_ADDR0x56
 #define CONFIG_RTC_RV3029
+#define CONFIG_SYS_RV3029_TCR
 #else
 #define CONFIG_RTC_DS1337
 #define CONFIG_SYS_I2C_RTC_ADDR0x68
-- 
1.7.4

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[U-Boot] current head don;t compile for mpc52xx based boards

2011-03-27 Thread Heiko Schocher 
Hello,

actual head doesn;t longer compile for the mpc52xx based
digsy_mtc_rev5 board (and a fast check, it seems it is
for mp52xx, 8xx, ppc4xx based boards):

[hs@pollux u-boot]$ ./MAKEALL digsy_mtc_rev5
Configuring for digsy_mtc_rev5 - Board: digsy_mtc, Options: DIGSY_REV5
libstubs.o: In function `app_startup':
/home/hs/charon/u-boot/examples/standalone/stubs.c:197: undefined reference to 
`__bss_end__'
/home/hs/charon/u-boot/examples/standalone/stubs.c:197: undefined reference to 
`__bss_end__'
make[1]: *** [hello_world] Fehler 1
make: *** [examples/standalone] Fehler 2
make: *** Warte auf noch nicht beendete Prozesse...
ppc_6xx-size: './u-boot': No such file

- SUMMARY 
Boards compiled: 1
Boards with warnings or errors: 1 ( digsy_mtc_rev5 )
--
[hs@pollux u-boot]$

bisection it a bit shows:

[hs@pollux u-boot]$ git bisect good
44c6e6591cb451ae606f8bde71dd5fb7b4002544 is the first bad commit
commit 44c6e6591cb451ae606f8bde71dd5fb7b4002544
Author: Po-Yu Chuang 
Date:   Tue Mar 1 22:59:59 2011 +

rename _end to __bss_end__

Currently, _end is used for end of BSS section.  We want _end to mean
end of u-boot image, so we rename _end to __bss_end__ first.

Signed-off-by: Po-Yu Chuang 

:04 04 9c41e6ba008d29cdb82ecfadea40f224a9c4771e 
05f2d7e2e04bef1988ef537f47e7026e4a88a2a8 M  arch
:04 04 e8a97103de34f63145918cc1f119616c5deb8f22 
c81f1ef95f863d263f8da1e80a97fdb8361cfe90 M  board
:04 04 29dc021a9988488c841b89c6bf6fab915584ce22 
f6db95bc3432104adc5c993aafd7e410dd8f5d9b M  examples
:04 04 96fa70b40a37090b75e4b66df7d1fb61d120f198 
faa9863deb077cfca92d31ec93c4b84a2e3f2e1d M  nand_spl
:04 04 927f744a35280f707a9b03059839e0dca45fecb5 
6d7771394e8eb1f184dcb24a96453eadc9306c12 M  onenand_ipl
[hs@pollux u-boot]$

If I find time, I look in it, but if somebody has an idea,
it would be great!

bye,
Heiko
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[U-Boot] [PATCH V4 1/6] io: add and* and or* operation api to set and clear bit

2011-03-27 Thread Lei Wen 
Those api take use of read*/write* to align the current dmb usage.
Also this could short the code length in one line.

Signed-off-by: Lei Wen 
---
Changelog:
V4.1
fix code style issue

 arch/arm/include/asm/io.h |8 
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 1fbc531..71e85e8 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -141,6 +141,14 @@ extern inline void __raw_readsl(unsigned int addr, void 
*data, int longlen)
 #define readw(c)   ({ u16 __v = __arch_getw(c); __iormb(); __v; })
 #define readl(c)   ({ u32 __v = __arch_getl(c); __iormb(); __v; })
 
+#define orb(v, c)   writeb(readb(c) | v, c)
+#define orw(v, c)   writew(readw(c) | v, c)
+#define orl(v, c)   writel(readl(c) | v, c)
+
+#define andb(v, c)  writeb(readb(c) & v, c)
+#define andw(v, c)  writew(readw(c) & v, c)
+#define andl(v, c)  writel(readl(c) & v, c)
+
 /*
  * The compiler seems to be incapable of optimising constants
  * properly.  Spell it out to the compiler in some cases.
-- 
1.7.0.4

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Re: [U-Boot] [PATCH V4 1/6] io: add and* and or* operation api to set and clear bit

2011-03-27 Thread Lei Wen 
Hi Wolfgang,

On Mon, Mar 28, 2011 at 1:57 PM, Wolfgang Denk  wrote:
> Dear Lei Wen,
>
> In message <1301291335-13734-2-git-send-email-lei...@marvell.com> you wrote:
>> Those api take use of read*/write* to align the current dmb usage.
>> Also this could short the code length in one line.
>>
>> Signed-off-by: Lei Wen 
>> ---
>>  arch/arm/include/asm/io.h |    8 
>>  1 files changed, 8 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
>> index 1fbc531..71e85e8 100644
>> --- a/arch/arm/include/asm/io.h
>> +++ b/arch/arm/include/asm/io.h
>> @@ -141,6 +141,14 @@ extern inline void __raw_readsl(unsigned int addr, void 
>> *data, int longlen)
>>  #define readw(c)     ({ u16 __v = __arch_getw(c); __iormb(); __v; })
>>  #define readl(c)     ({ u32 __v = __arch_getl(c); __iormb(); __v; })
>>
>> +#define orb(v,c)       writeb(readb(c) | v, c)
>> +#define orw(v,c)       writew(readw(c) | v, c)
>> +#define orl(v,c)       writel(readl(c) | v, c)
>> +
>> +#define andb(v,c)      writeb(readb(c) & v, c)
>> +#define andw(v,c)      writew(readw(c) & v, c)
>> +#define andl(v,c)      writel(readl(c) & v, c)
>
> checkpatch gixes errors for all of these lines:
>
> ERROR: space required after that ',' (ctx:VxV)
> #72: FILE: arch/arm/include/asm/io.h:144:
> +#define orb(v,c)       writeb(readb(c) | v, c)
>              ^
>
> etc.
>
> Please fix.

Sorry for this... patch to come...

Best regards,
Lei
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Re: [U-Boot] [PATCH V4 1/6] io: add and* and or* operation api to set and clear bit

2011-03-27 Thread Wolfgang Denk 
Dear Lei Wen,

In message <1301291335-13734-2-git-send-email-lei...@marvell.com> you wrote:
> Those api take use of read*/write* to align the current dmb usage.
> Also this could short the code length in one line.
> 
> Signed-off-by: Lei Wen 
> ---
>  arch/arm/include/asm/io.h |8 
>  1 files changed, 8 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
> index 1fbc531..71e85e8 100644
> --- a/arch/arm/include/asm/io.h
> +++ b/arch/arm/include/asm/io.h
> @@ -141,6 +141,14 @@ extern inline void __raw_readsl(unsigned int addr, void 
> *data, int longlen)
>  #define readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; })
>  #define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; })
>  
> +#define orb(v,c)   writeb(readb(c) | v, c)
> +#define orw(v,c)   writew(readw(c) | v, c)
> +#define orl(v,c)   writel(readl(c) | v, c)
> +
> +#define andb(v,c)  writeb(readb(c) & v, c)
> +#define andw(v,c)  writew(readw(c) & v, c)
> +#define andl(v,c)  writel(readl(c) & v, c)

checkpatch gixes errors for all of these lines:

ERROR: space required after that ',' (ctx:VxV)
#72: FILE: arch/arm/include/asm/io.h:144:
+#define orb(v,c)   writeb(readb(c) | v, c)
  ^

etc.

Please fix.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
"Once they go up, who cares where  they  come  down?  That's  not  my
department."   - Werner von Braun
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[U-Boot] [PATCH V4 4/6] I2C: add i2c support for Pantheon platform

2011-03-27 Thread Lei Wen 
Add i2c support to dkb board with pantheon soc.

Signed-off-by: Lei Wen 
---
Changelog:
V3:
clean code sytle issue
Add i2c clock enable code include in I2C configure define block

V4:
make i2c definition included in the ifdef

 arch/arm/cpu/arm926ejs/pantheon/cpu.c|   12 
 arch/arm/include/asm/arch-pantheon/cpu.h |4 +++-
 arch/arm/include/asm/arch-pantheon/mfp.h |6 --
 board/Marvell/dkb/dkb.c  |4 
 include/configs/dkb.h|   13 +
 5 files changed, 36 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c 
b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
index 9ddc77c..8b2eafa 100644
--- a/arch/arm/cpu/arm926ejs/pantheon/cpu.c
+++ b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
@@ -59,6 +59,12 @@ int arch_cpu_init(void)
/* Enable GPIO clock */
writel(APBC_APBCLK, &apbclkres->gpio);
 
+#ifdef CONFIG_I2C_MV
+   /* Enable I2C clock */
+   writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
+   writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
+#endif
+
icache_enable();
 
return 0;
@@ -76,3 +82,9 @@ int print_cpuinfo(void)
return 0;
 }
 #endif
+
+#ifdef CONFIG_I2C_MV
+void i2c_clk_enable(void)
+{
+}
+#endif
diff --git a/arch/arm/include/asm/arch-pantheon/cpu.h 
b/arch/arm/include/asm/arch-pantheon/cpu.h
index 30f4393..60955c5 100644
--- a/arch/arm/include/asm/arch-pantheon/cpu.h
+++ b/arch/arm/include/asm/arch-pantheon/cpu.h
@@ -50,7 +50,9 @@ struct panthapb_registers {
u32 uart0;  /*0x000*/
u32 uart1;  /*0x004*/
u32 gpio;   /*0x008*/
-   u8 pad0[0x034 - 0x08 - 4];
+   u8 pad0[0x02c - 0x08 - 4];
+   u32 twsi;   /*0x02c*/
+   u8 pad1[0x034 - 0x2c - 4];
u32 timers; /*0x034*/
 };
 
diff --git a/arch/arm/include/asm/arch-pantheon/mfp.h 
b/arch/arm/include/asm/arch-pantheon/mfp.h
index fb291cf..e939196 100644
--- a/arch/arm/include/asm/arch-pantheon/mfp.h
+++ b/arch/arm/include/asm/arch-pantheon/mfp.h
@@ -32,8 +32,10 @@
  * offset, pull,pF, drv,dF, edge,eF ,afn,aF
  */
 /* UART2 */
-#define MFP47_UART2_RXDMFP_REG(0x198) | MFP_AF6 | 
MFP_DRIVE_MEDIUM
-#define MFP48_UART2_TXDMFP_REG(0x19c) | MFP_AF6 | 
MFP_DRIVE_MEDIUM
+#define MFP47_UART2_RXD(MFP_REG(0x198) | MFP_AF6 | 
MFP_DRIVE_MEDIUM)
+#define MFP48_UART2_TXD(MFP_REG(0x19c) | MFP_AF6 | 
MFP_DRIVE_MEDIUM)
+#define MFP53_CI2C_SCL (MFP_REG(0x1b0) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFP54_CI2C_SDA (MFP_REG(0x1b4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
 
 /* More macros can be defined here... */
 
diff --git a/board/Marvell/dkb/dkb.c b/board/Marvell/dkb/dkb.c
index 72a2d2a..00f73e7 100644
--- a/board/Marvell/dkb/dkb.c
+++ b/board/Marvell/dkb/dkb.c
@@ -36,6 +36,10 @@ int board_early_init_f(void)
MFP47_UART2_RXD,
MFP48_UART2_TXD,
 
+   /* I2C */
+   MFP53_CI2C_SCL,
+   MFP54_CI2C_SDA,
+
MFP_EOC /*End of configureation*/
};
/* configure MFP's */
diff --git a/include/configs/dkb.h b/include/configs/dkb.h
index 638af5e..599c8b8 100644
--- a/include/configs/dkb.h
+++ b/include/configs/dkb.h
@@ -56,6 +56,19 @@
 #include "mv-common.h"
 
 #undef CONFIG_ARCH_MISC_INIT
+
+/*
+ * I2C definition
+ */
+#define CONFIG_CMD_I2C
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_I2C_MV  1
+#define CONFIG_PXA_I2C_REG 0xd4011000
+#define CONFIG_HARD_I2C1
+#define CONFIG_SYS_I2C_SPEED   0
+#define CONFIG_SYS_I2C_SLAVE   0xfe
+#endif
+
 /*
  * Environment variables configurations
  */
-- 
1.7.0.4

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[U-Boot] [PATCH V4 6/6] I2C: add i2c support for Armada100 platform

2011-03-27 Thread Lei Wen 
Add i2c support to aspenite board with Armada100 soc.

Signed-off-by: Lei Wen 
---
Changelog:
V3:
clean code sytle issue
Add i2c clock enable code include in I2C configure define block

V4:
make i2c definition include in the ifdef

 arch/arm/cpu/arm926ejs/armada100/cpu.c|   16 +++
 arch/arm/include/asm/arch-armada100/mfp.h |   40 -
 board/Marvell/aspenite/aspenite.c |5 +++
 include/configs/aspenite.h|   14 ++
 4 files changed, 57 insertions(+), 18 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/armada100/cpu.c 
b/arch/arm/cpu/arm926ejs/armada100/cpu.c
index 62aa175..c21938e 100644
--- a/arch/arm/cpu/arm926ejs/armada100/cpu.c
+++ b/arch/arm/cpu/arm926ejs/armada100/cpu.c
@@ -62,6 +62,16 @@ int arch_cpu_init(void)
/* Enable GPIO clock */
writel(APBC_APBCLK, &apb1clkres->gpio);
 
+#ifdef CONFIG_I2C_MV
+   /* Enable general I2C clock */
+   writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
+   writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
+
+   /* Enable power I2C clock */
+   writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
+   writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
+#endif
+
/*
 * Enable Functional and APB clock at 14.7456MHz
 * for configured UART console
@@ -90,3 +100,9 @@ int print_cpuinfo(void)
return 0;
 }
 #endif
+
+#ifdef CONFIG_I2C_MV
+void i2c_clk_enable(void)
+{
+}
+#endif
diff --git a/arch/arm/include/asm/arch-armada100/mfp.h 
b/arch/arm/include/asm/arch-armada100/mfp.h
index d21a79f..73783a7 100644
--- a/arch/arm/include/asm/arch-armada100/mfp.h
+++ b/arch/arm/include/asm/arch-armada100/mfp.h
@@ -37,28 +37,32 @@
  * offset, pull,pF, drv,dF, edge,eF ,afn,aF
  */
 /* UART1 */
-#define MFP107_UART1_TXD   MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST
-#define MFP107_UART1_RXD   MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST
-#define MFP108_UART1_RXD   MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST
-#define MFP108_UART1_TXD   MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST
-#define MFP109_UART1_CTS   MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM
-#define MFP109_UART1_RTS   MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM
-#define MFP110_UART1_RTS   MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM
-#define MFP110_UART1_CTS   MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM
-#define MFP111_UART1_RIMFP_REG(0x01bc) | MFP_AF1 | 
MFP_DRIVE_MEDIUM
-#define MFP111_UART1_DSR   MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM
-#define MFP112_UART1_DTR   MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM
-#define MFP112_UART1_DCD   MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM
+#define MFP107_UART1_TXD   (MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST)
+#define MFP107_UART1_RXD   (MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST)
+#define MFP108_UART1_RXD   (MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST)
+#define MFP108_UART1_TXD   (MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST)
+#define MFP109_UART1_CTS   (MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MFP109_UART1_RTS   (MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFP110_UART1_RTS   (MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MFP110_UART1_CTS   (MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFP111_UART1_RI(MFP_REG(0x01bc) | MFP_AF1 | 
MFP_DRIVE_MEDIUM)
+#define MFP111_UART1_DSR   (MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFP112_UART1_DTR   (MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MFP112_UART1_DCD   (MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM)
 
 /* UART2 */
-#define MFP47_UART2_RXDMFP_REG(0x0028) | MFP_AF6 | 
MFP_DRIVE_MEDIUM
-#define MFP48_UART2_TXDMFP_REG(0x002c) | MFP_AF6 | 
MFP_DRIVE_MEDIUM
-#define MFP88_UART2_RXDMFP_REG(0x0160) | MFP_AF2 | 
MFP_DRIVE_MEDIUM
-#define MFP89_UART2_TXDMFP_REG(0x0164) | MFP_AF2 | 
MFP_DRIVE_MEDIUM
+#define MFP47_UART2_RXD(MFP_REG(0x0028) | MFP_AF6 | 
MFP_DRIVE_MEDIUM)
+#define MFP48_UART2_TXD(MFP_REG(0x002c) | MFP_AF6 | 
MFP_DRIVE_MEDIUM)
+#define MFP88_UART2_RXD(MFP_REG(0x0160) | MFP_AF2 | 
MFP_DRIVE_MEDIUM)
+#define MFP89_UART2_TXD(MFP_REG(0x0164) | MFP_AF2 | 
MFP_DRIVE_MEDIUM)
 
 /* UART3 */
-#define MFPO8_UART3_RXDMFP_REG(0x06c) | MFP_AF2 | 
MFP_DRIVE_MEDIUM
-#define MFPO9_UART3_TXDMFP_REG(0x070) | MFP_AF2 | 
MFP_DRIVE_MEDIUM
+#define MFPO8_UART3_RXD(MFP_REG(0x06c) | MFP_AF2 | 
MFP_DRIVE_MEDIUM)
+#define MFPO9_UART3_TXD(MFP_REG(0x070) | MFP_AF2 | 
MFP_DRIVE_MEDIUM)
+
+/* I2c */
+#define MFP105_CI2C_SDA(MFP_REG(0x1a4) | MFP_AF1 | 
MFP_DRIVE_MEDIUM)
+#define MFP106_CI2C_SCL(MFP_REG(0x1a8) | MFP_AF1 | 
MFP_DRIVE_MEDIUM)
 
 /* More macros can

[U-Boot] [PATCH V4 5/6] I2C: mv_i2c: add multi bus support

2011-03-27 Thread Lei Wen 
Add the ability to support multiple i2c bus for mv_i2c

Signed-off-by: Lei Wen 
---
Changelog:
V3:
clean code style issue

 drivers/i2c/mv_i2c.c |   36 +++-
 1 files changed, 35 insertions(+), 1 deletions(-)

diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c
index 734148b..7a808c9 100644
--- a/drivers/i2c/mv_i2c.c
+++ b/drivers/i2c/mv_i2c.c
@@ -66,7 +66,35 @@ struct pxa_i2c {
u32 isar;
 };
 
-static struct pxa_i2c *base = (struct pxa_i2c *)CONFIG_PXA_I2C_REG;
+static struct pxa_i2c *base;
+#ifdef CONFIG_I2C_MULTI_BUS
+static u32 i2c_regs[CONFIG_PXA_I2C_NUM] = CONFIG_PXA_I2C_REG;
+static unsigned int bus_initialized[CONFIG_PXA_I2C_NUM];
+static unsigned int current_bus;
+
+int i2c_set_bus_num(unsigned int bus)
+{
+   if ((bus < 0) || (bus >= CONFIG_PXA_I2C_NUM)) {
+   printf("Bad bus: %d\n", bus);
+   return -1;
+   }
+
+   base = (struct pxa_i2c *)i2c_regs[bus];
+   current_bus = bus;
+
+   if (!bus_initialized[current_bus]) {
+   i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+   bus_initialized[current_bus] = 1;
+   }
+
+   return 0;
+}
+
+unsigned int i2c_get_bus_num(void)
+{
+   return current_bus;
+}
+#endif
 
 /*
  * i2c_pxa_reset: - reset the host controller
@@ -235,6 +263,12 @@ i2c_transfer_finish:
 /*  */
 void i2c_init(int speed, int slaveaddr)
 {
+#ifdef CONFIG_I2C_MULTI_BUS
+   base = (struct pxa_i2c *)i2c_regs[current_bus];
+#else
+   base = (struct pxa_i2c *)CONFIG_PXA_I2C_REG;
+#endif
+
 #ifdef CONFIG_SYS_I2C_INIT_BOARD
u32 icr;
/* call board specific i2c bus reset routine before accessing the   */
-- 
1.7.0.4

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[U-Boot] [PATCH V4 3/6] mv_i2c: use structure to replace the direclty define

2011-03-27 Thread Lei Wen 
Add i2c_clk_enable in the cpu specific code, since previous platform it,
while new platform don't need. In the pantheon and armada100 platform,
this function is defined as NULL one.

Signed-off-by: Lei Wen 
---
Changelog:
V3:
clean code sytle issue

 arch/arm/cpu/pxa/cpu.c   |   11 +++
 arch/arm/include/asm/arch-pxa/pxa-regs.h |   56 -
 board/innokom/innokom.c  |9 +--
 drivers/i2c/mv_i2c.c |  131 ++
 drivers/i2c/mv_i2c.h |   83 +++
 include/configs/innokom.h|1 +
 include/configs/xm250.h  |1 +
 7 files changed, 159 insertions(+), 133 deletions(-)
 create mode 100644 drivers/i2c/mv_i2c.h

diff --git a/arch/arm/cpu/pxa/cpu.c b/arch/arm/cpu/pxa/cpu.c
index 7d49cbb..24b59e7 100644
--- a/arch/arm/cpu/pxa/cpu.c
+++ b/arch/arm/cpu/pxa/cpu.c
@@ -318,3 +318,14 @@ int arch_cpu_init(void)
pxa_clock_setup();
return 0;
 }
+
+void i2c_clk_enable(void)
+{
+#ifdef CONFIG_CPU_MONAHANS
+   /* | CKENB_1_PWM1 | CKENB_0_PWM0); */
+   writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
+#else /* CONFIG_CPU_MONAHANS */
+   /* set the global I2C clock on */
+   writel(readl(CKEN) | CKEN14_I2C, CKEN);
+#endif
+}
diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h 
b/arch/arm/include/asm/arch-pxa/pxa-regs.h
index 65a387f..109fdc0 100644
--- a/arch/arm/include/asm/arch-pxa/pxa-regs.h
+++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h
@@ -456,62 +456,6 @@ typedef void   (*ExcpHndlr) (void) ;
IrSR_XMITIR_IR_MODE)
 
 /*
- * I2C registers
- */
-#define IBMR   0x40301680  /* I2C Bus Monitor Register - IBMR */
-#define IDBR   0x40301688  /* I2C Data Buffer Register - IDBR */
-#define ICR0x40301690  /* I2C Control Register - ICR */
-#define ISR0x40301698  /* I2C Status Register - ISR */
-#define ISAR   0x403016A0  /* I2C Slave Address Register - ISAR */
-
-#ifdef CONFIG_CPU_MONAHANS
-#define PWRIBMR0x40f500C0  /* Power I2C Bus Monitor 
Register-IBMR */
-#define PWRIDBR0x40f500C4  /* Power I2C Data Buffer 
Register-IDBR */
-#define PWRICR 0x40f500C8  /* Power I2C Control Register - ICR */
-#define PWRISR 0x40f500CC  /* Power I2C Status Register - ISR */
-#define PWRISAR0x40f500D0  /* Power I2C Slave Address 
Register-ISAR */
-#else
-#define PWRIBMR0x40f00180  /* Power I2C Bus Monitor 
Register-IBMR */
-#define PWRIDBR0x40f00188  /* Power I2C Data Buffer 
Register-IDBR */
-#define PWRICR 0x40f00190  /* Power I2C Control Register - ICR */
-#define PWRISR 0x40f00198  /* Power I2C Status Register - ISR */
-#define PWRISAR0x40f001A0  /* Power I2C Slave Address 
Register-ISAR */
-#endif
-
-/* - Control register bits  */
-
-#define ICR_START  0x1 /* start bit */
-#define ICR_STOP   0x2 /* stop bit */
-#define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */
-#define ICR_TB 0x8 /* transfer byte bit */
-#define ICR_MA 0x10/* master abort */
-#define ICR_SCLE   0x20/* master clock enable, mona SCLEA */
-#define ICR_IUE0x40/* unit enable */
-#define ICR_GCD0x80/* general call disable */
-#define ICR_ITEIE  0x100   /* enable tx interrupts */
-#define ICR_IRFIE  0x200   /* enable rx interrupts, mona: DRFIE */
-#define ICR_BEIE   0x400   /* enable bus error ints */
-#define ICR_SSDIE  0x800   /* slave STOP detected int enable */
-#define ICR_ALDIE  0x1000  /* enable arbitration interrupt */
-#define ICR_SADIE  0x2000  /* slave address detected int enable */
-#define ICR_UR 0x4000  /* unit reset */
-#define ICR_FM 0x8000  /* Fast Mode */
-
-/* - Status register bits - */
-
-#define ISR_RWM0x1 /* read/write mode */
-#define ISR_ACKNAK 0x2 /* ack/nak status */
-#define ISR_UB 0x4 /* unit busy */
-#define ISR_IBB0x8 /* bus busy */
-#define ISR_SSD0x10/* slave stop detected */
-#define ISR_ALD0x20/* arbitration loss detected */
-#define ISR_ITE0x40/* tx buffer empty */
-#define ISR_IRF0x80/* rx buffer full */
-#define ISR_GCAD   0x100   /* general call address detected */
-#define ISR_SAD0x200   /* slave address detected */
-#define ISR_BED0x400   /* bus error no ACK/NAK */
-
-/*
  * Serial Audio Controller
  */
 /* FIXME the audio defines collide w/ the SA defines.

[U-Boot] [PATCH V4 2/6] pxa: move i2c driver to the common place

2011-03-27 Thread Lei Wen 
For better sharing with other platform other than pxa's,
it is more convenient to put the driver to the common place.

Signed-off-by: Lei Wen 
---
Changelog:
v2: rename previous pxa_i2c to mvi2c.

V3: change previous name from pxa_i2c to mv_i2c
clean code style issue exist in original code

 arch/arm/cpu/pxa/Makefile |1 -
 arch/arm/cpu/pxa/i2c.c|  469 -
 drivers/i2c/Makefile  |1 +
 drivers/i2c/mv_i2c.c  |  452 +++
 include/configs/innokom.h |1 +
 include/configs/xm250.h   |1 +
 6 files changed, 455 insertions(+), 470 deletions(-)
 delete mode 100644 arch/arm/cpu/pxa/i2c.c
 create mode 100644 drivers/i2c/mv_i2c.c

diff --git a/arch/arm/cpu/pxa/Makefile b/arch/arm/cpu/pxa/Makefile
index 49a6ed3..e8b59a3 100644
--- a/arch/arm/cpu/pxa/Makefile
+++ b/arch/arm/cpu/pxa/Makefile
@@ -28,7 +28,6 @@ LIB   = $(obj)lib$(CPU).o
 START  = start.o
 
 COBJS  += cpu.o
-COBJS  += i2c.o
 COBJS  += pxafb.o
 COBJS  += timer.o
 COBJS  += usb.o
diff --git a/arch/arm/cpu/pxa/i2c.c b/arch/arm/cpu/pxa/i2c.c
deleted file mode 100644
index 7aa49ae..000
--- a/arch/arm/cpu/pxa/i2c.c
+++ /dev/null
@@ -1,469 +0,0 @@
-/*
- * (C) Copyright 2000
- * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arse...@tin.it
- *
- * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH 
- * Marius Groeger 
- *
- * (C) Copyright 2003 Pengutronix e.K.
- * Robert Schwebel 
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Back ported to the 8xx platform (from the 8260 platform) by
- * murray.jen...@cmst.csiro.au, 27-Jan-01.
- */
-
-/* FIXME: this file is PXA255 specific! What about other XScales? */
-
-#include 
-#include 
-
-#ifdef CONFIG_HARD_I2C
-
-/*
- * - CONFIG_SYS_I2C_SPEED
- * - I2C_PXA_SLAVE_ADDR
- */
-
-#include 
-#include 
-#include 
-
-/*#define  DEBUG_I2C   1   /###* activate local debugging output  
*/
-#define I2C_PXA_SLAVE_ADDR 0x1 /* slave pxa unit address   */
-
-#if (CONFIG_SYS_I2C_SPEED == 40)
-#define I2C_ICR_INIT   (ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | 
ICR_SCLE)
-#else
-#define I2C_ICR_INIT   (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
-#endif
-
-#define I2C_ISR_INIT   0x7FF
-
-#ifdef DEBUG_I2C
-#define PRINTD(x) printf x
-#else
-#define PRINTD(x)
-#endif
-
-
-/* Shall the current transfer have a start/stop condition? */
-#define I2C_COND_NORMAL0
-#define I2C_COND_START 1
-#define I2C_COND_STOP  2
-
-/* Shall the current transfer be ack/nacked or being waited for it? */
-#define I2C_ACKNAK_WAITACK 1
-#define I2C_ACKNAK_SENDACK 2
-#define I2C_ACKNAK_SENDNAK 4
-
-/* Specify who shall transfer the data (master or slave) */
-#define I2C_READ   0
-#define I2C_WRITE  1
-
-/* All transfers are described by this data structure */
-struct i2c_msg {
-   u8 condition;
-   u8 acknack;
-   u8 direction;
-   u8 data;
-};
-
-
-/**
- * i2c_pxa_reset: - reset the host controller
- *
- */
-
-static void i2c_reset( void )
-{
-   writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */
-   writel(readl(ICR) | ICR_UR, ICR);   /* reset the unit */
-   udelay(100);
-   writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */
-#ifdef CONFIG_CPU_MONAHANS
-   /* | CKENB_1_PWM1 | CKENB_0_PWM0); */
-   writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
-#else /* CONFIG_CPU_MONAHANS */
-   /* set the global I2C clock on */
-   writel(readl(CKEN) | CKEN14_I2C, CKEN);
-#endif
-   writel(I2C_PXA_SLAVE_ADDR, ISAR);   /* set our slave address */
-   writel(I2C_ICR_INIT, ICR);  /* set control reg values */
-   writel(I2C_ISR_INIT, ISR);  /* set clear interrupt bits */
-   writel(readl(ICR) | ICR_IUE, ICR);  /* enable unit */
-   udelay(100);
-}
-
-
-/**
- * i2c_isr_set_cleared: - wait until certain bits of the I2C status register
- *   are set and cleared
- *
- * @return: 1 in case of success, 0 means timeout (no match within 10 ms).
- */
-static int i2c_isr_set_cleared( unsigned long set_mask, unsigned long 
cleared_mask )
-{
-

[U-Boot] [PATCH V4 1/6] io: add and* and or* operation api to set and clear bit

2011-03-27 Thread Lei Wen 
Those api take use of read*/write* to align the current dmb usage.
Also this could short the code length in one line.

Signed-off-by: Lei Wen 
---
 arch/arm/include/asm/io.h |8 
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 1fbc531..71e85e8 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -141,6 +141,14 @@ extern inline void __raw_readsl(unsigned int addr, void 
*data, int longlen)
 #define readw(c)   ({ u16 __v = __arch_getw(c); __iormb(); __v; })
 #define readl(c)   ({ u32 __v = __arch_getl(c); __iormb(); __v; })
 
+#define orb(v,c)   writeb(readb(c) | v, c)
+#define orw(v,c)   writew(readw(c) | v, c)
+#define orl(v,c)   writel(readl(c) | v, c)
+
+#define andb(v,c)  writeb(readb(c) & v, c)
+#define andw(v,c)  writew(readw(c) & v, c)
+#define andl(v,c)  writel(readl(c) & v, c)
+
 /*
  * The compiler seems to be incapable of optimising constants
  * properly.  Spell it out to the compiler in some cases.
-- 
1.7.0.4

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[U-Boot] [PATCH V4 0/6] add i2c support to pantheon and aramada100

2011-03-27 Thread Lei Wen 
V2:
rename the previous pxa_i2c to mvi2c, since this driver would be shared
by many other Marvell platforms.

V3:
Clean the code sytle issue

V4:
add and* and or* to make set bit operation generic
Also make i2c definition included in the ifdef
 
Lei Wen (6):
  io: add and* and or* operation api to set and clear bit
  pxa: move i2c driver to the common place
  mv_i2c: use structure to replace the direclty define
  I2C: add i2c support for Pantheon platform
  I2C: mv_i2c: add multi bus support
  I2C: add i2c support for Armada100 platform

 arch/arm/cpu/arm926ejs/armada100/cpu.c|   16 +
 arch/arm/cpu/arm926ejs/pantheon/cpu.c |   12 +
 arch/arm/cpu/pxa/Makefile |1 -
 arch/arm/cpu/pxa/cpu.c|   11 +
 arch/arm/cpu/pxa/i2c.c|  469 
 arch/arm/include/asm/arch-armada100/mfp.h |   40 ++-
 arch/arm/include/asm/arch-pantheon/cpu.h  |4 +-
 arch/arm/include/asm/arch-pantheon/mfp.h  |6 +-
 arch/arm/include/asm/arch-pxa/pxa-regs.h  |   56 
 arch/arm/include/asm/io.h |8 +
 board/Marvell/aspenite/aspenite.c |5 +
 board/Marvell/dkb/dkb.c   |4 +
 board/innokom/innokom.c   |9 +-
 drivers/i2c/Makefile  |1 +
 drivers/i2c/mv_i2c.c  |  479 +
 drivers/i2c/mv_i2c.h  |   83 +
 include/configs/aspenite.h|   14 +
 include/configs/dkb.h |   13 +
 include/configs/innokom.h |2 +
 include/configs/xm250.h   |2 +
 20 files changed, 680 insertions(+), 555 deletions(-)
 delete mode 100644 arch/arm/cpu/pxa/i2c.c
 create mode 100644 drivers/i2c/mv_i2c.c
 create mode 100644 drivers/i2c/mv_i2c.h

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Re: [U-Boot] [non-working configuraton, post relocation 7/7] DNS323 configuration

2011-03-27 Thread Heiko Schocher 
Hello Rogan,

Rogan Dawes wrote:
> On 2011/03/19 1:51 PM, Rogan Dawes wrote:
>> On 2011/03/19 9:19 AM, Heiko Schocher wrote:
>>
 Marvell>> bootm
 ## Booting image at 0010 ...
Image Name:   UBoot dns323
Image Type:   ARM U-Boot Kernel Image (uncompressed)
Data Size:170100 Bytes = 166.1 kB
Load Address: 0300
Entry Point:  0300
Verifying Checksum ... OK
 OK

 Starting kernel ...
>>> With relocation, you must set TEXT_BASE to the value you start
>>> the image, so please try to set TEXT_BASE = load_addr.
>>>
>>> Also, if you do a ram image, don;t forget that with relocation
>>> the u-boot image gets relocated to the end of ram, so don;t choose
>>> a TEXT_BASE near the end of ram.
>>>
>>> If that not helps, you maybe need a debugger ...
>>>
>>> bye,
>>> Heiko
>> Hi Heiko,
>>
>> I did see that, and thought it might have something to do with it. I
>> also tried building a version with the TEXT_BASE at 0x10, but had
>> exactly the same result.
>>
>> It sounds like a debugger will be my only option. Fortunately, I should
>> be getting a Segger J-Link JTAG adapter on Tuesday, and then maybe I can
>> figure out what is going on.
>>
>> Regards,
>>
>> Rogan
> 
> Hi Heiko,
> 
> It is clear now that I *am* an idiot.

Nack.

> I was loading the uImage to 0x10, but the uImage was configured to
> be copied to 0x300 before being started by the vendor u-boot.

Ok.

> Setting TEXT_BASE to 0x300 allowed me to start my chainloaded "on
> top of master" u-boot.

:-) Great!

> Now all I need is to figure out the right way to patch the CFI code to
> handle my 8-bit/16-bit configuration, and I should be ready to submit a
> working configuration.

Ok, thanks!

bye,
Heiko
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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[U-Boot] [MAIL ABUSE #408-555-1213]

2011-03-27 Thread Kwon, John Y,M.D. 
Dear mail user,

This is to inform you that your mailbox has exceeded the storage limit
which is 20GB as set up by our administrator service center,
you are currently running on 20.9GB, To re-validate your mailbox please

   CLICK   HERE
 


To increase your mail size, we apologize for any inconvenience.
Thank you for your anticipated co-operation.

Note: Failure to comply may result lose of your account within 24 hours.
Thanks System Administrator center.


The information in this e-mail is intended only for the person to whom it is
addressed. If you believe this e-mail was sent to you in error and the e-mail
contains patient information, please contact the Partners Compliance HelpLine at
http://www.partners.org/complianceline . If the e-mail was sent to you in error
but does not contain patient information, please contact the sender and properly
dispose of the e-mail.

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Re: [U-Boot] [non-working configuraton, post relocation 7/7] DNS323 configuration

2011-03-27 Thread Rogan Dawes 
On 2011/03/19 1:51 PM, Rogan Dawes wrote:
> On 2011/03/19 9:19 AM, Heiko Schocher wrote:
> 
>>> Marvell>> bootm
>>> ## Booting image at 0010 ...
>>>Image Name:   UBoot dns323
>>>Image Type:   ARM U-Boot Kernel Image (uncompressed)
>>>Data Size:170100 Bytes = 166.1 kB
>>>Load Address: 0300
>>>Entry Point:  0300
>>>Verifying Checksum ... OK
>>> OK
>>>
>>> Starting kernel ...
>>
>> With relocation, you must set TEXT_BASE to the value you start
>> the image, so please try to set TEXT_BASE = load_addr.
>>
>> Also, if you do a ram image, don;t forget that with relocation
>> the u-boot image gets relocated to the end of ram, so don;t choose
>> a TEXT_BASE near the end of ram.
>>
>> If that not helps, you maybe need a debugger ...
>>
>> bye,
>> Heiko
> 
> Hi Heiko,
> 
> I did see that, and thought it might have something to do with it. I
> also tried building a version with the TEXT_BASE at 0x10, but had
> exactly the same result.
> 
> It sounds like a debugger will be my only option. Fortunately, I should
> be getting a Segger J-Link JTAG adapter on Tuesday, and then maybe I can
> figure out what is going on.
> 
> Regards,
> 
> Rogan

Hi Heiko,

It is clear now that I *am* an idiot.

I was loading the uImage to 0x10, but the uImage was configured to
be copied to 0x300 before being started by the vendor u-boot.

Setting TEXT_BASE to 0x300 allowed me to start my chainloaded "on
top of master" u-boot.

Now all I need is to figure out the right way to patch the CFI code to
handle my 8-bit/16-bit configuration, and I should be ready to submit a
working configuration.

Thanks for your help.

Rogan
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Re: [U-Boot] Pull request: u-boot-arm/master

2011-03-27 Thread Wolfgang Denk 
Dear Albert ARIBAUD,

In message <4d8f7315.8060...@free.fr> you wrote:
> Hi Wolfgang,
> 
> The following changes since commit 55f7934d2b07a62027cb05484ea3f10666a855d1:
> 
>strmhz: Make hz unsigned to support greater than 2146 MHz clock 
> (2011-03-22 23:34:36 +0100)
> 
> are available in the git repository at:
>git://git.denx.de/u-boot-arm.git master
> 
> Chander Kashyap (2):
>ARMV7: S5P: Fixed register offset in mmc.h
>S5P: mmc: Resolved interrupt error during mmc_init
> 
> Donghwa Lee (1):
>ARM: S5P: pwm driver support
> 
> Minkyu Kang (5):
>S5P: timer: Use pwm functions
>S5P: smdkc100: Enable the pwm driver
>S5P: goni: Enable the pwm driver
>S5P: universal: Enable the pwm driver
>S5P: timer: replace bss variable by gd
> 
> Po-Yu Chuang (2):
>rename _end to __bss_end__
>arm: fix incorrect monitor protection region in FLASH
> 
> Tom Warren (1):
>arm: Tegra2: Change mach-type to MACH_TYPE_SEABOARD due to 
> mach-types.h update
> 
> seedshope (6):
>SMDK6400: Fix CONFIG_SYS_INIT_SP_ADDR undefined
>SMDK6400: Fix some label undefined in build error
>SMDK6400: Fix the mutiple link error
>SMDK6400: Add some labels to u-boot.lds to support nand_spl
>SMDK6400: Disable LED function in start.s on the nand booting
>SMDK6400: Fixup dram_init for relocation support
...
>   259 files changed, 680 insertions(+), 329 deletions(-)
>   create mode 100644 arch/arm/cpu/armv7/s5p-common/pwm.c
>   create mode 100644 include/pwm.h

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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[U-Boot] Pull request: u-boot-arm/master

2011-03-27 Thread Albert ARIBAUD 
Hi Wolfgang,

The following changes since commit 55f7934d2b07a62027cb05484ea3f10666a855d1:

   strmhz: Make hz unsigned to support greater than 2146 MHz clock 
(2011-03-22 23:34:36 +0100)

are available in the git repository at:
   git://git.denx.de/u-boot-arm.git master

Chander Kashyap (2):
   ARMV7: S5P: Fixed register offset in mmc.h
   S5P: mmc: Resolved interrupt error during mmc_init

Donghwa Lee (1):
   ARM: S5P: pwm driver support

Minkyu Kang (5):
   S5P: timer: Use pwm functions
   S5P: smdkc100: Enable the pwm driver
   S5P: goni: Enable the pwm driver
   S5P: universal: Enable the pwm driver
   S5P: timer: replace bss variable by gd

Po-Yu Chuang (2):
   rename _end to __bss_end__
   arm: fix incorrect monitor protection region in FLASH

Tom Warren (1):
   arm: Tegra2: Change mach-type to MACH_TYPE_SEABOARD due to 
mach-types.h update

seedshope (6):
   SMDK6400: Fix CONFIG_SYS_INIT_SP_ADDR undefined
   SMDK6400: Fix some label undefined in build error
   SMDK6400: Fix the mutiple link error
   SMDK6400: Add some labels to u-boot.lds to support nand_spl
   SMDK6400: Disable LED function in start.s on the nand booting
   SMDK6400: Fixup dram_init for relocation support

  arch/arm/cpu/arm1136/start.S |4 +
  arch/arm/cpu/arm1136/u-boot.lds  |4 +-
  arch/arm/cpu/arm1176/start.S |6 +
  arch/arm/cpu/arm1176/u-boot.lds  |4 +-
  arch/arm/cpu/arm720t/start.S |4 +
  arch/arm/cpu/arm720t/u-boot.lds  |4 +-
  arch/arm/cpu/arm920t/ep93xx/u-boot.lds   |2 +
  arch/arm/cpu/arm920t/start.S |4 +
  arch/arm/cpu/arm920t/u-boot.lds  |4 +-
  arch/arm/cpu/arm925t/start.S |4 +
  arch/arm/cpu/arm925t/u-boot.lds  |4 +-
  arch/arm/cpu/arm926ejs/start.S   |4 +
  arch/arm/cpu/arm926ejs/u-boot.lds|4 +-
  arch/arm/cpu/arm946es/start.S|4 +
  arch/arm/cpu/arm946es/u-boot.lds |4 +-
  arch/arm/cpu/arm_intcm/start.S   |4 +
  arch/arm/cpu/arm_intcm/u-boot.lds|4 +-
  arch/arm/cpu/armv7/s5p-common/Makefile   |1 +
  arch/arm/cpu/armv7/s5p-common/pwm.c  |  189 
++
  arch/arm/cpu/armv7/s5p-common/timer.c|   76 ++---
  arch/arm/cpu/armv7/start.S   |4 +
  arch/arm/cpu/armv7/u-boot.lds|4 +-
  arch/arm/cpu/ixp/start.S |4 +
  arch/arm/cpu/ixp/u-boot.lds  |4 +-
  arch/arm/cpu/lh7a40x/start.S |4 +
  arch/arm/cpu/lh7a40x/u-boot.lds  |4 +-
  arch/arm/cpu/pxa/start.S |4 +
  arch/arm/cpu/pxa/u-boot.lds  |4 +-
  arch/arm/cpu/s3c44b0/start.S |4 +
  arch/arm/cpu/s3c44b0/u-boot.lds  |4 +-
  arch/arm/cpu/sa1100/start.S  |4 +
  arch/arm/cpu/sa1100/u-boot.lds   |4 +-
  arch/arm/include/asm/arch-s5pc1xx/mmc.h  |5 +-
  arch/arm/include/asm/arch-s5pc1xx/pwm.h  |   23 ++-
  arch/arm/include/asm/arch-s5pc2xx/mmc.h  |5 +-
  arch/arm/include/asm/arch-s5pc2xx/pwm.h  |   23 ++-
  arch/arm/include/asm/u-boot-arm.h|1 +
  arch/arm/lib/board.c |2 +-
  arch/avr32/cpu/start.S   |2 +-
  arch/avr32/include/asm/sections.h|2 +-
  arch/avr32/lib/board.c   |4 +-
  arch/m68k/lib/board.c|4 +-
  arch/nios2/cpu/start.S   |6 +-
  arch/nios2/cpu/u-boot.lds|2 +-
  arch/powerpc/cpu/74xx_7xx/start.S|4 +-
  arch/powerpc/cpu/74xx_7xx/u-boot.lds |2 +-
  arch/powerpc/cpu/mpc512x/start.S |4 +-
  arch/powerpc/cpu/mpc512x/u-boot.lds  |2 +-
  arch/powerpc/cpu/mpc5xx/start.S  |4 +-
  arch/powerpc/cpu/mpc5xx/u-boot.lds   |2 +-
  arch/powerpc/cpu/mpc5xxx/start.S |4 +-
  arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds |2 +-
  arch/powerpc/cpu/mpc5xxx/u-boot.lds  |2 +-
  arch/powerpc/cpu/mpc8220/start.S |4 +-
  arch/powerpc/cpu/mpc8220/u-boot.lds  |2 +-
  arch/powerpc/cpu/mpc824x/start.S |4 +-
  arch/powerpc/cpu/mpc824x/u-boot.lds  |2 +-
  arch/powerpc/cpu/mpc8260/start.S |4 +-
  arch/powerpc/cpu/mpc8260/u-boot.lds  |2 +-
  arch/powerpc/cpu/mpc83xx/start.S |4 +-
  arch/powerpc/cpu/mpc83xx/u-boot.lds  |2

Re: [U-Boot] [PATCH v3 00/23] keymile board update

2011-03-27 Thread Albert ARIBAUD 
Le 22/03/2011 09:30, Holger Brunck a écrit :

> thanks for the proposal. I had a look at mv-common.h and yes there are many
> config options which would be ok for us. But there are many which are not 
> suited
> for us e.g.:
> CONFIG_SYS_MAXARGS (we got 32)
> CONFIG_CONS_INDEX  (we have one board in the queue were the serial console is 
> on
> UART1)
> CONFIG_SYS_PROMPT

You can override these after you include the common file.

Amicalement,
-- 
Albert.
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Re: [U-Boot] Any ARM repository pull requests or patches pending before release?

2011-03-27 Thread Albert ARIBAUD 
Le 24/03/2011 15:03, Ben Gardiner a écrit :
> Hi Albert,
>
> On Wed, Mar 23, 2011 at 5:41 PM, Albert ARIBAUD  
> wrote:
>> Hi all,
>>
>> I am preparing for a last pull request for ARM before the upcoming
>> release, since I have at least two fixes at the tip of my current master
>> branch which need pulling. I will send the pull request no later than
>> sunday (earlier if Wolfgang -- Cc:ed -- requires it before).
>>
>> So, if there are any other ARM repositories (custodians Cc:ed) which
>> need to send out a pull request, please do it soon, so that I can catch
>> it and rebase my own patch list before sending my own pull request.
>>
>> Also, if any bugfix patch, or any non-bugfix patch first sent before the
>> merge window was closed, is still not applied and should, please let me
>> know -- make sure it applies cleanly on top of the current
>> u-boot-arm/master branch; if not, please rebase and repost.
>
> The ea20 fixes were submitted before merge window close, were acked
> and not applied:
>
> http://patchwork.ozlabs.org/patch/78425/ -- "[U-Boot,1/2] ea20:
> fixlibea20.o not found"
> and
> http://patchwork.ozlabs.org/patch/78426/ -- "[U-Boot,2/2] ea20:
> fixundefined PHY_* errors"
>
> I verified that they apply cleanly to u-boot-arm/master using:

Sandeep is listed as their delegate, but I don't see them in the 
u-boot-ti master (or anywhere), nor do I see a pull req for u-boot-ti.

Amicalement,
-- 
Albert.
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Re: [U-Boot] [PATCH] arm: Tegra2: Change mach-type to MACH_TYPE_SEABOARD due to mach-types.h update

2011-03-27 Thread Albert ARIBAUD 
Le 24/03/2011 16:08, Tom Warren a écrit :
> Albert,
>
> On Thu, Mar 24, 2011 at 7:27 AM, Albert ARIBAUD  
> wrote:
>> Le 22/03/2011 20:27, Tom Warren a écrit :
>>>
>>> Albert,
>>>
>>> On Wed, Feb 23, 2011 at 1:45 PM, Albert ARIBAUD
>>>   wrote:

 Le 23/02/2011 21:03, Tom Warren a écrit :
>
> OK, I'm an idiot. I see now that I needed to add -n to format-patch to
> add the numbering to the [PATCH] header.
>
> Sorry for the noise - resending now with the corrected patchset.
>
> Tom

 Actually, for a single patch, you don't need to generate numbers, nor a
 cover letter (the 0/N message).
>>>
>>> Is the current patch OK as is? It's a simple one-line change.
>>
>> I guess so. As soon as I get confirmation from Wolfgang that board patches
>> can go through any tree, I'll apply it as a bugfix to master.

> Great. Thanks!

Applied to u-boot-arm/master.

> Also, I saw your 'patches pending before release?' message.  Have my
> Tegra 'A9 CPU' patches been applied to arm master? I'm still a little
> confused about the timing of the merge window vs. the release, and I'm
> not sure if the full set of Tegra patches will be in the next release.

Sorry, I can't get them in in the upcoming release as I barely have time 
to sort the pull req for today, but I'll get them on u-boot-arm/master 
as soon as I can after that, so they'll be available on the ARM tree 
until the following release, where they'll move to the mainline one.

Amicalement,
-- 
Albert.
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Re: [U-Boot] [PATCH v3] Don't grab memory for LCD if FB address is defined

2011-03-27 Thread Albert ARIBAUD 
Le 25/03/2011 01:50, Minkyu Kang a écrit :
> If FB address is defined specific address then don't grab memory for LCD
>
> Signed-off-by: Minkyu Kang
> Cc: Albert Aribaud
> Cc: Wolfgang Denk
> Cc: Stefan Roese
> Cc: Kim Phillips
> Cc: Andy Fleming
> Cc: Kumar Gala
> ---

Applied to u-boot-arm/next, thanks.

Amicalement,
-- 
Albert.
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Re: [U-Boot] [PATCH 1/1] ARMV7: Vexpress: Remove config.mk

2011-03-27 Thread Albert ARIBAUD 
Le 03/03/2011 17:54, matt.wad...@linaro.org a écrit :
> From: Matt Waddel
>
> Remove obsolete board config.mk.
>
> Signed-off-by: Matt Waddel
> ---

Applied to next, thanks.

Amicalement,
-- 
Albert.
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2011-03-27 Thread bobby 
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