Re: [U-Boot] [PATCH 0/9] Update support for CM-T35
Ping! Wolfgang, should I have also send this to Albert or/and Sandeep? On 04/05/11 10:08, Igor Grinberg wrote: This patch serie s based on the latest U-Boot release (v2011.03) and updates support for Compulab CM-T35 board: 1) Some clean up 2) MMC/SD Card fix 3) Add Green Status LED 4) Add support for CM-T3730 which is basically the same board, but has TI's DM3730 SoC and therefore some changes are required Igor Grinberg (9): OMAP3: CM-T35: Move DECLARE_GLOBAL_DATA_PTR to file scope OMAP3: CM-T35: update config OMAP3: CM-T35: update board files header information OMAP3: CM-T35: update MAINTAINERS file OMAP3: CM-T35: add MMC1 pinmux OMAP3: CM-T35: fix mmc OMAP3: CM-T35: remove redundand i2c initialization OMAP3: CM-T35: enable the green LED OMAP3: CM-T35: Add support for CM-T3730 MAINTAINERS |8 ++-- board/cm_t35/Makefile|2 +- board/cm_t35/cm_t35.c| 116 -- board/cm_t35/leds.c | 45 ++ include/configs/cm_t35.h | 41 +++- 5 files changed, 160 insertions(+), 52 deletions(-) create mode 100644 board/cm_t35/leds.c -- Regards, Igor. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] fsl_esdhc: Deal with watermark level register related changes
On 03/07/2011 05:14 AM, Kumar Gala wrote: From: Priyanka Jain priyanka.j...@freescale.com P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark level register description has been changed: 9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00 25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00 Signed-off-by: Priyanka Jain priyanka.j...@freescale.com Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- Tested on i.MX51. Tested-by: Stefano Babic sba...@denx.de Regards, Stefano -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: off...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] MX31: mx31pdk: Add watchdog support
On 03/09/2011 05:35 PM, Fabio Estevam wrote: Signed-off-by: Fabio Estevam fabio.este...@freescale.com --- board/freescale/mx31pdk/mx31pdk.c | 16 include/configs/mx31pdk.h |1 + 2 files changed, 17 insertions(+), 0 deletions(-) diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c index a9f0fb4..4a5d3ef 100644 Hi Fabio, diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 86c758f..1f1de46 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -61,6 +61,7 @@ #define CONFIG_MXC_UART 1 #define CONFIG_SYS_MX31_UART11 +#define CONFIG_HW_WATCHDOG #define CONFIG_HARD_SPI 1 #define CONFIG_MXC_SPI 1 Applying this patch I have not found BOARD_LATE_INIT in mx31pdk.h. How can the watchdog be enabled ? Best regards, Stefano -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: off...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] fsl_esdhc: Deal with watermark level register related changes
On Apr 10, 2011, at 10:30 AM, Stefano Babic wrote: On 03/07/2011 05:14 AM, Kumar Gala wrote: From: Priyanka Jain priyanka.j...@freescale.com P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark level register description has been changed: 9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00 25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00 Signed-off-by: Priyanka Jain priyanka.j...@freescale.com Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- Tested on i.MX51. Tested-by: Stefano Babic sba...@denx.de applied to 85xx - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Please pull u-boot-mpc85xx.git
The following changes since commit 4db2fa7f9446d0f2fe8db3d62184b1212fe22707: Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx (2011-04-05 12:24:20 +0200) are available in the git repository at: git://git.denx.de/u-boot-mpc85xx master Haiying Wang (1): powerpc/85xx: Add P1021 specific QE and UEC support Jiang Yutang (3): powerpc/85xx: Enable support for ATI graphics cards on P1022DS powerpc/85xx: Add support usb2/etsec and tdm/audio pin multiplex on P1022DS powerpc/85xx: Update default hwconfig on P1022DS Kumar Gala (1): powerpc/85xx: Drop CONFIG_VIDEO support on corenet_ds boards Matthew McClintock (1): powerpc/85xx: rename NAND prefixes to CONFIG_SYS Priyanka Jain (1): fsl_esdhc: Deal with watermark level register related changes Shaohui Xie (1): powerpc/85xx: Add PBL boot from SPI flash support on P4080DS Timur Tabi (2): p4080ds: add README.p4080ds which documents the serdes hwconfig option p4080ds: remove rev1-specific code for the SERDES8 erratum Zhao Chenhui (2): powerpc/85xx: don't init SDRAM when CONFIG_SYS_RAMBOOT powerpc/85xx: Add some defines registers in immap_85xx.h arch/powerpc/cpu/mpc85xx/cpu.c| 11 +++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 19 + arch/powerpc/cpu/mpc85xx/cpu_init_nand.c |8 +- arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 106 +++-- arch/powerpc/cpu/mpc85xx/speed.c |8 ++- arch/powerpc/include/asm/config_mpc85xx.h | 14 +++ arch/powerpc/include/asm/fsl_ddr_sdram.h |1 + arch/powerpc/include/asm/immap_85xx.h | 53 ++-- board/freescale/corenet_ds/tlb.c | 12 +++- board/freescale/p1022ds/p1022ds.c | 56 +++--- boards.cfg|1 + doc/README.p1022ds| 24 ++ doc/README.p4080ds| 32 drivers/mmc/fsl_esdhc.c |8 +- drivers/qe/uec.c | 37 +- include/configs/MPC8536DS.h | 18 ++-- include/configs/MPC8569MDS.h | 12 ++-- include/configs/MPC8572DS.h | 18 ++-- include/configs/P1022DS.h | 17 include/configs/P1_P2_RDB.h | 12 ++-- include/configs/P2020DS.h | 14 ++-- include/configs/corenet_ds.h | 50 ++-- include/fsl_esdhc.h | 15 +++- 23 files changed, 394 insertions(+), 152 deletions(-) create mode 100644 doc/README.p1022ds create mode 100644 doc/README.p4080ds ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Removed clearing of L2-as-SRAM
On Feb 14, 2011, at 5:59 AM, Fabian Cenedese wrote: Removed clearing of L2 cache as SRAM as it is not necessary without ECC. This also speeds up the booting process. Signed-off-by: Fabian Cenedese cened...@indel.ch Cc: Kumar Gala ga...@kernel.crashing.org --- arch/powerpc/cpu/mpc85xx/cpu_init_nand.c |7 --- 1 files changed, 0 insertions(+), 7 deletions(-) applied to 85xx - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/2] MX31: mx31pdk: Add watchdog support
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
Changes since v1:
- define BOARD_LATE_INIT in /mx31pdk.h
board/freescale/mx31pdk/mx31pdk.c | 16
include/configs/mx31pdk.h |3 +++
2 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/board/freescale/mx31pdk/mx31pdk.c
b/board/freescale/mx31pdk/mx31pdk.c
index 3f291fc..4ef548f 100644
--- a/board/freescale/mx31pdk/mx31pdk.c
+++ b/board/freescale/mx31pdk/mx31pdk.c
@@ -28,9 +28,17 @@
#include netdev.h
#include asm/arch/clock.h
#include asm/arch/imx-regs.h
+#include watchdog.h
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_HW_WATCHDOG
+void hw_watchdog_reset(void)
+{
+ mxc_hw_watchdog_reset();
+}
+#endif
+
int dram_init(void)
{
/* dram_init must store complete ramsize in gd-ram_size */
@@ -68,6 +76,14 @@ int board_init(void)
return 0;
}
+int board_late_init(void)
+{
+#ifdef CONFIG_HW_WATCHDOG
+ mxc_hw_watchdog_enable();
+#endif
+ return 0;
+}
+
int checkboard(void)
{
printf(Board: i.MX31 MAX PDK (3DS)\n);
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index d4c6d16..f5d3ee7 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -61,6 +61,7 @@
#define CONFIG_MXC_UART1
#define CONFIG_SYS_MX31_UART1 1
+#define CONFIG_HW_WATCHDOG
#define CONFIG_HARD_SPI1
#define CONFIG_MXC_SPI 1
@@ -98,6 +99,8 @@
*/
#undef CONFIG_CMD_IMLS
+#define BOARD_LATE_INIT
+
#define CONFIG_BOOTDELAY 3
#defineCONFIG_EXTRA_ENV_SETTINGS
\
--
1.6.0.4
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[U-Boot] [PATCH v2 2/2] MX31: mx31pdk: Print the cause of reset
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
Changes since v1:
- Use 3 bits for rcsr mask
board/freescale/mx31pdk/mx31pdk.c | 25 -
1 files changed, 24 insertions(+), 1 deletions(-)
diff --git a/board/freescale/mx31pdk/mx31pdk.c
b/board/freescale/mx31pdk/mx31pdk.c
index 4ef548f..5fc6319 100644
--- a/board/freescale/mx31pdk/mx31pdk.c
+++ b/board/freescale/mx31pdk/mx31pdk.c
@@ -86,7 +86,30 @@ int board_late_init(void)
int checkboard(void)
{
- printf(Board: i.MX31 MAX PDK (3DS)\n);
+ u32 cause;
+ struct clock_control_regs *ccm =
+ (struct clock_control_regs *)CCM_BASE;
+ puts(Board: MX31PDK [);
+
+ cause = ccm-rcsr 0x07;
+ switch (cause) {
+ case 0x:
+ puts(POR);
+ break;
+ case 0x0001:
+ puts(RST);
+ break;
+ case 0x0002:
+ puts(WDOG);
+ break;
+ case 0x0006:
+ puts(JTAG);
+ break;
+ default:
+ puts(unknown);
+ }
+
+ puts(]\n);
return 0;
}
--
1.6.0.4
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Re: [U-Boot] Please pull u-boot-cfi-flash
Dear Stefan Roese, In message 201104071025.32882...@denx.de you wrote: Hi Wolfgang, please pull the following changes: The following changes since commit 4db2fa7f9446d0f2fe8db3d62184b1212fe22707: Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx (2011-04-05 12:24:20 +0200) are available in the git repository at: git://www.denx.de/git/u-boot-cfi-flash.git master Heiko Schocher (1): mtd, cfi: introduce void flash_protect_default(void) Mario Schuknecht (1): cfi_flash: use AMD fixups for AMIC (e.g. A29L160A series) too drivers/mtd/cfi_flash.c | 80 +- include/flash.h |1 + 2 files changed, 44 insertions(+), 37 deletions(-) Applied, thanks. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de The project was large enough and management communication poor enough to prompt many members of the team to see themselves as contestants making brownie points, rather than as builders making programming products. Each suboptimized his piece to meet his targets; few stopped to think about the total effect on the customer. - Fred Brooks, The Mythical Man Month ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Pull request u-boot-blackfin.git
Dear Mike Frysinger, In message 1302238070-32427-1-git-send-email-vap...@gentoo.org you wrote: The following changes since commit 4db2fa7f9446d0f2fe8db3d62184b1212fe22707: Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx (2011-04-05 12:24:20 +0200) are available in the git repository at: git://www.denx.de/git/u-boot-blackfin.git master Andreas Schallenberg (1): Blackfin: dnp5370: new board port Chong Huang (1): Blackfin: bf525-ucr2: new board port Cliff Cai (1): Blackfin: bfin_sdh: set all timer bits before transfer Kyle Moffett (1): Blackfin: replace bfin_reset_or_hang() with panic() Mike Frysinger (29): Blackfin: bf518f-ezbrd: don't require SPI logic all the time Blackfin: skip RAM display for 0 mem systems Blackfin: drop CONFIG_SYS_TEXT_BASE from boards Blackfin: unify bootmode based LDR_FLAGS setup Blackfin: move CONFIG_BFIN_CPU back to board config.h Blackfin: bf527-sdp: update custom CFLAGS paths Blackfin: bf537-pnav/blackstamp/blackvme: drop empty config.mk files Blackfin: serial: clean up muxing a bit Blackfin: bf537-minotaur/bf537-srv1: undefine nfs when net is disabled Blackfin: bf537: fix L1 data defines Blackfin: bf561-ezkit/ibf-dsp561: invert env offset/addr logic Blackfin: fix bd_t handling Blackfin: BF50x: new processor port Blackfin: drop duplicate system mmr and L1 scratch defines Blackfin: BF52x: unify duplicated headers Blackfin: BF537: unify duplicated headers Blackfin: only check for os log when we have external memory Blackfin: turn off caches when self initializing Blackfin: default to L1 bank A when L1 bank B does not exist Blackfin: bf506f-ezkit: new board port Blackfin: adi boards: drop old ELF define Blackfin: bootrom.h: sync with toolchain Blackfin: bootldr: use common defines Blackfin: ldrinfo: new command Blackfin: adi boards: enable ldrinfo Blackfin: adi boards: enable CONFIG_MONITOR_IS_IN_RAM Blackfin: bf548-ezkit: move env sector Blackfin: bf518f-ezbrd: get MAC from flash Blackfin: bf526-ezbrd: get MAC from flash Sonic Zhang (1): Blackfin: bfin_sdh: add support for multiblock operations MAINTAINERS| 10 + README |1 + arch/blackfin/config.mk| 15 +- arch/blackfin/cpu/cpu.h|1 - arch/blackfin/cpu/gpio.c |8 +- arch/blackfin/cpu/initcode.c | 25 +- arch/blackfin/cpu/reset.c | 18 +- arch/blackfin/cpu/serial.h | 72 +- arch/blackfin/cpu/start.S | 45 +- arch/blackfin/cpu/traps.c |2 +- arch/blackfin/include/asm/blackfin_cdef.h |6 + arch/blackfin/include/asm/blackfin_def.h | 10 + arch/blackfin/include/asm/config.h | 10 +- arch/blackfin/include/asm/mach-bf506/BF504_cdef.h | 1782 arch/blackfin/include/asm/mach-bf506/BF504_def.h | 944 +++ arch/blackfin/include/asm/mach-bf506/BF506_cdef.h | 11 + arch/blackfin/include/asm/mach-bf506/BF506_def.h | 11 + arch/blackfin/include/asm/mach-bf506/anomaly.h | 128 ++ arch/blackfin/include/asm/mach-bf506/def_local.h |5 + arch/blackfin/include/asm/mach-bf506/gpio.h| 52 + arch/blackfin/include/asm/mach-bf506/portmux.h | 148 ++ arch/blackfin/include/asm/mach-bf506/ports.h | 59 + arch/blackfin/include/asm/mach-bf518/BF512_def.h |6 - .../asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h | 994 --- .../asm/mach-bf527/ADSP-EDN-BF52x-extended_def.h | 503 -- arch/blackfin/include/asm/mach-bf527/BF522_cdef.h | 986 +++- arch/blackfin/include/asm/mach-bf527/BF522_def.h | 495 ++- arch/blackfin/include/asm/mach-bf527/BF524_cdef.h | 20 +- arch/blackfin/include/asm/mach-bf527/BF524_def.h | 12 +- arch/blackfin/include/asm/mach-bf527/BF526_cdef.h | 358 + arch/blackfin/include/asm/mach-bf527/BF526_def.h | 181 +-- arch/blackfin/include/asm/mach-bf533/BF531_def.h |6 - arch/blackfin/include/asm/mach-bf533/BF532_def.h |6 - arch/blackfin/include/asm/mach-bf533/BF533_def.h |6 - .../asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h | 1624 -- .../asm/mach-bf537/ADSP-EDN-BF534-extended_def.h | 819 - arch/blackfin/include/asm/mach-bf537/BF534_cdef.h | 1614 ++- arch/blackfin/include/asm/mach-bf537/BF534_def.h | 816 +- arch/blackfin/include/asm/mach-bf538/BF538_def.h |6 - arch/blackfin/include/asm/mach-bf561/BF561_def.h |7 +- .../include/asm/mach-common/bits/bootrom.h
Re: [U-Boot] [Nios] Pull Request
Dear Scott McNutt, In message 4d9f09ec.70...@psyent.com you wrote: Dear Wolfgang, The following changes since commit 4db2fa7f9446d0f2fe8db3d62184b1212fe22707: Wolfgang Denk (1): Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx are available in the git repository at: git://git.denx.de/u-boot-nios.git next Thomas Chou (1): nios2: reset cfi flash before reading env board/altera/nios2-generic/nios2-generic.c | 16 1 files changed, 16 insertions(+), 0 deletions(-) Applied, thanks. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Philosophy is a game with objectives and no rules. Mathematics is a game with rules and no objectives. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-mpc85xx.git
Dear Kumar Gala, In message alpine.lfd.2.00.1104101120030.23...@right.am.freescale.net you wrote: The following changes since commit 4db2fa7f9446d0f2fe8db3d62184b1212fe22707: Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx (2011-04-05 12:24:20 +0200) are available in the git repository at: git://git.denx.de/u-boot-mpc85xx master Haiying Wang (1): powerpc/85xx: Add P1021 specific QE and UEC support Jiang Yutang (3): powerpc/85xx: Enable support for ATI graphics cards on P1022DS powerpc/85xx: Add support usb2/etsec and tdm/audio pin multiplex on P1022DS powerpc/85xx: Update default hwconfig on P1022DS Kumar Gala (1): powerpc/85xx: Drop CONFIG_VIDEO support on corenet_ds boards Matthew McClintock (1): powerpc/85xx: rename NAND prefixes to CONFIG_SYS Priyanka Jain (1): fsl_esdhc: Deal with watermark level register related changes Shaohui Xie (1): powerpc/85xx: Add PBL boot from SPI flash support on P4080DS Timur Tabi (2): p4080ds: add README.p4080ds which documents the serdes hwconfig option p4080ds: remove rev1-specific code for the SERDES8 erratum Zhao Chenhui (2): powerpc/85xx: don't init SDRAM when CONFIG_SYS_RAMBOOT powerpc/85xx: Add some defines registers in immap_85xx.h arch/powerpc/cpu/mpc85xx/cpu.c| 11 +++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 19 + arch/powerpc/cpu/mpc85xx/cpu_init_nand.c |8 +- arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 106 +++-- arch/powerpc/cpu/mpc85xx/speed.c |8 ++- arch/powerpc/include/asm/config_mpc85xx.h | 14 +++ arch/powerpc/include/asm/fsl_ddr_sdram.h |1 + arch/powerpc/include/asm/immap_85xx.h | 53 ++-- board/freescale/corenet_ds/tlb.c | 12 +++- board/freescale/p1022ds/p1022ds.c | 56 +++--- boards.cfg|1 + doc/README.p1022ds| 24 ++ doc/README.p4080ds| 32 drivers/mmc/fsl_esdhc.c |8 +- drivers/qe/uec.c | 37 +- include/configs/MPC8536DS.h | 18 ++-- include/configs/MPC8569MDS.h | 12 ++-- include/configs/MPC8572DS.h | 18 ++-- include/configs/P1022DS.h | 17 include/configs/P1_P2_RDB.h | 12 ++-- include/configs/P2020DS.h | 14 ++-- include/configs/corenet_ds.h | 50 ++-- include/fsl_esdhc.h | 15 +++- 23 files changed, 394 insertions(+), 152 deletions(-) create mode 100644 doc/README.p1022ds create mode 100644 doc/README.p4080ds Applied, thanks. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Faith: not *wanting* to know what is true.- Friedrich Nietzsche ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] cfi_flash: reverse geometry for M29W800DT parts
The M29W800DT parts also report their geometry with the sector layout
reversed. So add that ID to the flash_fixup_stm function.
Otherwise, we get:
bfin flinfo
Bank # 1: CFI conformant FLASH (16 x 16) Size: 1 MB in 19 Sectors
AMD Standard command set, Manufacturer ID: 0x20, Device ID: 0x22D7
Erase timeout: 8192 ms, write timeout: 1 ms
Sector Start Addresses:
20002000400020006000200080002001
20022003200420052006
200720082009200A200B
200C200D200E200F
Reported-by: Jianxi Fu fujia...@gmail.com
Signed-off-by: Mike Frysinger vap...@gentoo.org
---
drivers/mtd/cfi_flash.c |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index 0909fe7..69f12d3 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -1852,9 +1852,10 @@ static void flash_fixup_stm(flash_info_t *info, struct
cfi_qry *qry)
if (qry-num_erase_regions 1) {
/* reverse geometry if top boot part */
if (info-cfi_version 0x3131) {
- /* CFI 1.1, guess by device id (M29W320{DT,ET} only)
*/
- if (info-device_id == 0x22CA ||
- info-device_id == 0x2256) {
+ /* CFI 1.1, guess by device id */
+ if (info-device_id == 0x22CA || /* M29W320DT */
+ info-device_id == 0x2256 || /* M29W320ET */
+ info-device_id == 0x22D7) { /* M29W800DT */
cfi_reverse_geometry(qry);
}
}
--
1.7.5.rc1
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[U-Boot] [PATCH] Fix the issue of _end symbol not being found while building
Fix the nand_spl build for the hawkboard
Signed-off-by: Sughosh Ganu urwithsugh...@gmail.com
---
nand_spl/board/davinci/da8xxevm/u-boot.lds |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/nand_spl/board/davinci/da8xxevm/u-boot.lds
b/nand_spl/board/davinci/da8xxevm/u-boot.lds
index c86117b..638ffd9 100644
--- a/nand_spl/board/davinci/da8xxevm/u-boot.lds
+++ b/nand_spl/board/davinci/da8xxevm/u-boot.lds
@@ -68,6 +68,8 @@ SECTIONS
__got_end = .;
+ _end = .;
+
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) }
--
1.7.1
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Re: [U-Boot] [PATCH] cfi_flash: reverse geometry for M29W800DT parts
On Sunday 10 April 2011 22:06:29 Mike Frysinger wrote:
The M29W800DT parts also report their geometry with the sector layout
reversed. So add that ID to the flash_fixup_stm function.
Maybe rework the stuff below into some table or it'll be a mess soon?
Cheers
Otherwise, we get:
bfin flinfo
Bank # 1: CFI conformant FLASH (16 x 16) Size: 1 MB in 19 Sectors
AMD Standard command set, Manufacturer ID: 0x20, Device ID: 0x22D7
Erase timeout: 8192 ms, write timeout: 1 ms
Sector Start Addresses:
20002000400020006000200080002001
20022003200420052006
200720082009200A200B
200C200D200E200F
Reported-by: Jianxi Fu fujia...@gmail.com
Signed-off-by: Mike Frysinger vap...@gentoo.org
---
drivers/mtd/cfi_flash.c |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index 0909fe7..69f12d3 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -1852,9 +1852,10 @@ static void flash_fixup_stm(flash_info_t *info,
struct cfi_qry *qry) if (qry-num_erase_regions 1) {
/* reverse geometry if top boot part */
if (info-cfi_version 0x3131) {
- /* CFI 1.1, guess by device id (M29W320{DT,ET} only)
*/
- if (info-device_id == 0x22CA ||
- info-device_id == 0x2256) {
+ /* CFI 1.1, guess by device id */
+ if (info-device_id == 0x22CA || /* M29W320DT */
+ info-device_id == 0x2256 || /* M29W320ET */
+ info-device_id == 0x22D7) { /* M29W800DT */
cfi_reverse_geometry(qry);
}
}
___
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Re: [U-Boot] [PATCH v7 01/10] nds32: add header files support for nds32
Hi Wolfgang, I did check typedefs one by one by myself in hand and eye checking. If some thing is not suitable for using typedefs please let me know. Please don't add any new typedef's. I think we still have to discuss about the typedef's. What does the new typedef means? According to the checkpatch result, typedef warning exists in 4 files. arch/nds32/include/asm/posix_types.h arch/nds32/include/asm/types.h arch/nds32/include/asm/global_data.h arch/nds32/include/asm/u-boot.h. I've found the origin purpose of adding typedef check to checkpatch.pl from the author apw. Please refer to url http://lkml.indiana.edu/hypermail/linux/kernel/0801.0/0354.html; I quote his words as below. Andy Whitcroft (apw said..) It is checkpatch's role to point out things which are likely to be wrong. There will always be exceptions. Lines which are much more readable if they spill over 80 characters, typedefs which do make sense. atomic_t's for example. This may well be a valid use of them. Note that this is mentioned as a WARNING not an ERROR. As is stated in the patch submission notes, you are meant to be comfortable with everything which checkpatch is still reporting. checkpatch is a style _guide_, not the be all and end all. It is meant to carry a preferred style to try and maintain some consistency kernel wide. There is also a section of the coding style which related to typedef in Linux Kernel's Documents. Please also refer to Chapter 5, typedef in Documentation/CodingStyle. Hope this information is helping other patch submitters. Thanks. -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v8 02/10] nds32: add NDS32 support into common header file
Add NDS32 support into common header file. Signed-off-by: Macpaul Lin macp...@andestech.com --- include/common.h |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/include/common.h b/include/common.h index 54503ed..423bbd8 100644 --- a/include/common.h +++ b/include/common.h @@ -273,6 +273,10 @@ intsetenv (char *, char *); #ifdef CONFIG_I386 /* x86 version to be fixed! */ # include asm/u-boot-i386.h #endif /* CONFIG_I386 */ +#ifdef CONFIG_NDS32 +# include asm/mach-types.h +# include asm/u-boot-nds32.h /* NDS32 version to be fixed! */ +#endif /* CONFIG_NDS32 */ #ifdef CONFIG_AUTO_COMPLETE int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf); -- 1.7.3.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v8 01/10] nds32: add header files support for nds32
Add generic header files support for nds32 architecture.
Cache, ptrace, data type and other definitions are included.
Signed-off-by: Macpaul Lin macp...@andestech.com
---
Changes for v1-v4:
- Code cleanup and style formatting.
Changes for v5-v6:
- This patch also updated the following changes against the
change after master tree (v2010.12-rc1).
- fix upper case definitions in cache.h
- Support GD_FLG_ENV_READY and env_buf vars in nds32 global_data.h.
- Add readsb, writesb functions into io.h.
Changes for v7:
- clean up
- volatile:
- types.h
- remove typedef volatile unsigned char vuchar;
- remove typedef volatile unsigned long vulong;
- remove typedef volatile unsigned short vushort;
- u-boot.h: remove bd_info_ext bi_ext
- bitops.h: add accessor function to bit operation with volatile var.
- system.h: add system.h for local_irq operation with flag.
Changes for v8:
- ptrace.h: rewrite the pt_reg structure, and merge ptregs.h.
- ptregs.h: removed
arch/nds32/include/asm/bitops.h | 186 +++
arch/nds32/include/asm/byteorder.h| 36 +++
arch/nds32/include/asm/cache.h| 54 +
arch/nds32/include/asm/config.h | 26 ++
arch/nds32/include/asm/global_data.h | 82 +++
arch/nds32/include/asm/io.h | 410 +
arch/nds32/include/asm/mach-types.h | 29 +++
arch/nds32/include/asm/memory.h | 19 ++
arch/nds32/include/asm/posix_types.h | 84 +++
arch/nds32/include/asm/processor.h| 25 ++
arch/nds32/include/asm/ptrace.h | 88 +++
arch/nds32/include/asm/string.h | 57 +
arch/nds32/include/asm/system.h | 88 +++
arch/nds32/include/asm/types.h| 63 +
arch/nds32/include/asm/u-boot-nds32.h | 50
arch/nds32/include/asm/u-boot.h | 63 +
arch/nds32/include/asm/unaligned.h| 31 +++
17 files changed, 1391 insertions(+), 0 deletions(-)
create mode 100644 arch/nds32/include/asm/bitops.h
create mode 100644 arch/nds32/include/asm/byteorder.h
create mode 100644 arch/nds32/include/asm/cache.h
create mode 100644 arch/nds32/include/asm/config.h
create mode 100644 arch/nds32/include/asm/global_data.h
create mode 100644 arch/nds32/include/asm/io.h
create mode 100644 arch/nds32/include/asm/mach-types.h
create mode 100644 arch/nds32/include/asm/memory.h
create mode 100644 arch/nds32/include/asm/posix_types.h
create mode 100644 arch/nds32/include/asm/processor.h
create mode 100644 arch/nds32/include/asm/ptrace.h
create mode 100644 arch/nds32/include/asm/string.h
create mode 100644 arch/nds32/include/asm/system.h
create mode 100644 arch/nds32/include/asm/types.h
create mode 100644 arch/nds32/include/asm/u-boot-nds32.h
create mode 100644 arch/nds32/include/asm/u-boot.h
create mode 100644 arch/nds32/include/asm/unaligned.h
diff --git a/arch/nds32/include/asm/bitops.h b/arch/nds32/include/asm/bitops.h
new file mode 100644
index 000..c56f04b
--- /dev/null
+++ b/arch/nds32/include/asm/bitops.h
@@ -0,0 +1,186 @@
+/*
+ * Copyright 1995, Russell King.
+ * Various bits and pieces copyrights include:
+ * Linus Torvalds (test_bit).
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation nobuh...@andestech.com
+ *
+ * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
+ *
+ * Please note that the code in this file should never be included
+ * from user space. Many of these are not implemented in assembler
+ * since they would be too costly. Also, they require priviledged
+ * instructions (which are not available from user mode) to ensure
+ * that they are atomic.
+ */
+
+#ifndef __ASM_NDS_BITOPS_H
+#define __ASM_NDS_BITOPS_H
+
+#ifdef __KERNEL__
+
+#include asm/system.h
+
+#define smp_mb__before_clear_bit() do { } while (0)
+#define smp_mb__after_clear_bit() do { } while (0)
+
+/*
+ * Function prototypes to keep gcc -Wall happy.
+ */
+extern void set_bit(int nr, volatile void *addr);
+
+static inline void __set_bit(int nr, volatile void *addr)
+{
+ int *a = (int *)addr;
+ int mask;
+
+ a += nr 5;
+ mask = 1 (nr 0x1f);
+ *a |= mask;
+}
+
+extern void clear_bit(int nr, volatile void *addr);
+
+static inline void __clear_bit(int nr, volatile void *addr)
+{
+ int *a = (int *)addr;
+ int mask;
+ unsigned long flags;
+
+ a += nr 5;
+ mask = 1 (nr 0x1f);
+ local_irq_save(flags);
+ *a = ~mask;
+ local_irq_restore(flags);
+}
+
+extern void change_bit(int nr, volatile void *addr);
+
+static inline void __change_bit(int nr, volatile void *addr)
+{
+ int mask;
+ unsigned long *ADDR = (unsigned long *)addr;
+
+ ADDR += nr 5;
+ mask = 1 (nr 31);
+ *ADDR ^= mask;
+}
+
+extern int test_and_set_bit(int nr, volatile void *addr);
+
+static inline int __test_and_set_bit(int nr, volatile void *addr)
+{
+ int mask,
[U-Boot] [PATCH v8 03/10] nds32/core N1213: NDS32 N12 core family N1213
Add N1213 cpu core (N12 Core family) support for NDS32 arch. This patch includes start.S for the initialize procedure of N1213. NDS32 Core N1213 has the following hardware features. Core: - 16-/32-bit mixable instruction format - 32 general-purpose 32-bit registers - 8-stage pipeline - Dynamic branch prediction - 32/64/128/256 BTB - Return address stack (RAS) - Vector interrupts for internal/external - 3 HW-level nested interruptions - User and super-user mode support - Memory-mapped I/O - Address space up to 4GB Memory Management Unit: - TLB - Optional hardware page table walker - Two groups of page size support Memory Subsystem: - I D cache - I D local memory (LM) Bus Interface: - Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports Start procedure: start.S will start up the N1213 CPU core at first, then jump to SoC dependent lowlevel_init.S and watchdog.S to configure peripheral devices. Signed-off-by: Macpaul Lin macp...@andestech.com --- arch/nds32/cpu/n1213/Makefile | 50 + arch/nds32/cpu/n1213/start.S| 447 +++ arch/nds32/cpu/n1213/u-boot.lds | 68 ++ 3 files changed, 565 insertions(+), 0 deletions(-) create mode 100644 arch/nds32/cpu/n1213/Makefile create mode 100644 arch/nds32/cpu/n1213/start.S create mode 100644 arch/nds32/cpu/n1213/u-boot.lds diff --git a/arch/nds32/cpu/n1213/Makefile b/arch/nds32/cpu/n1213/Makefile new file mode 100644 index 000..111d14f --- /dev/null +++ b/arch/nds32/cpu/n1213/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# Copyright (C) 2011 Andes Technology Corporation +# Shawn Lin, Andes Technology Corporation nobuh...@andestech.com +# Macpaul Lin, Andes Technology Corporation macp...@andestech.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(CPU).o + +START = start.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB):$(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S new file mode 100644 index 000..b04f3a5 --- /dev/null +++ b/arch/nds32/cpu/n1213/start.S @@ -0,0 +1,447 @@ +/* + * Andesboot - Startup Code for Whitiger core + * + * Copyright (C) 2006 Andes Technology Corporation + * Copyright (C) 2006 Shawn Lin nobuh...@andestech.com + * Copyright (C) 2011 Macpaul macp...@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include config.h +#include common.h +#include version.h + +/* + * Jump vector table for EVIC mode + */ +#define ENA_DCAC 2UL +#define DIS_DCAC ~ENA_DCAC +#define ICAC_MEM_KBF_ISET (0x07) ! I Cache sets per way +#define ICAC_MEM_KBF_IWAY (0x073) ! I cache ways +#define ICAC_MEM_KBF_ISZ (0x076) ! I cache line size +#define DCAC_MEM_KBF_DSET (0x07) ! D Cache sets per way +#define DCAC_MEM_KBF_DWAY (0x073) ! D cache ways +#define
[U-Boot] [PATCH v8 04/10] nds32/ag101: dev offset header of SoC ag101
Add header file of device offset support for SoC ag101. SoC ag101 is the first chip using NDS32 N1213 cpu core. Note: Ag101 is actually use ftsdmc021 instead of ftsdmc020 as dram controller, which is probably wrong in the datasheet. Signed-off-by: Macpaul Lin macp...@andestech.com --- arch/nds32/include/asm/arch-ag101/ag101.h | 68 + 1 files changed, 68 insertions(+), 0 deletions(-) create mode 100644 arch/nds32/include/asm/arch-ag101/ag101.h diff --git a/arch/nds32/include/asm/arch-ag101/ag101.h b/arch/nds32/include/asm/arch-ag101/ag101.h new file mode 100644 index 000..011989a --- /dev/null +++ b/arch/nds32/include/asm/arch-ag101/ag101.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Nobuhiro Lin, Andes Technology Corporation nobuh...@andestech.com + * Macpaul Lin, Andes Technology Corporation macp...@andestech.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __AG101_H +#define __AG101_H + +/* Hardware register bases */ +#define CONFIG_FTAHBC020S_BASE 0x9010 /* AHB Controller */ +#define CONFIG_FTSMC020_BASE 0x9020 /* Static Memory Controller (SRAM) */ +#define CONFIG_FTSDMC021_BASE 0x9030 /* FTSDMC020/021 SDRAM Controller */ +#define CONFIG_FTDMAC020_BASE 0x9040 /* DMA Controller */ +#define CONFIG_FTAPBBRG020S_01_BASE0x9050 /* AHB-to-APB Bridge */ +#define CONFIG_FTLCDC100_BASE 0x9060 /* LCD Controller */ +#define CONFIG_RESERVED_01_BASE0x9070 /* Reserved */ +#define CONFIG_RESERVED_02_BASE0x9080 /* Reserved */ +#define CONFIG_FTMAC100_BASE 0x9090 /* Ethernet */ +#define CONFIG_EXT_USB_HOST_BASE 0x90A0 /* External USB host */ +#define CONFIG_USB_DEV_BASE0x90B0 /* USB Device */ +#define CONFIG_EXT_AHBPCIBRG_BASE 0x90C0 /* External AHB-to-PCI Bridge (FTPCI100 not exist in ag101) */ +#define CONFIG_RESERVED_03_BASE0x90D0 /* Reserved */ +#define CONFIG_EXT_AHBAPBBRG_BASE 0x90E0 /* External AHB-to-APB Bridger (FTAPBBRG020S_02) */ +#define CONFIG_EXT_AHBSLAVE01_BASE 0x90F0 /* External AHB slave1 (LCD) */ + +#define CONFIG_EXT_AHBSLAVE02_BASE 0x9200 /* External AHB slave2 (FUSBH200) */ + +/* DEBUG LED */ +#define CONFIG_DEBUG_LED 0x902C /* Debug LED */ + +/* APB Device definitions */ +#define CONFIG_FTPMU010_BASE 0x9810 /* Power Management Unit */ +#define CONFIG_FTUART010_01_BASE 0x9830 /* BT UART 2/IrDA (UART 01 in Linux) */ +#define CONFIG_FTTMR010_BASE 0x9840 /* Counter/Timers */ +#define CONFIG_FTWDT010_BASE 0x9850 /* Watchdog Timer */ +#define CONFIG_FTRTC010_BASE 0x9860 /* Real Time Clock */ +#define CONFIG_FTGPIO010_BASE 0x9870 /* GPIO */ +#define CONFIG_FTINTC010_BASE 0x9880 /* Interrupt Controller */ +#define CONFIG_FTIIC010_BASE 0x98A0 /* I2C */ +#define CONFIG_RESERVED_04_BASE0x98C0 /* Reserved */ +#define CONFIG_FTCFC010_BASE 0x98D0 /* Compat Flash Controller */ +#define CONFIG_FTSDC010_BASE 0x98E0 /* SD Controller */ + +#define CONFIG_FTSSP010_02_BASE0x9940 /* Synchronous Serial Port Controller (SSP) I2S/AC97 */ +#define CONFIG_FTUART010_02_BASE 0x9960 /* ST UART ? SSP 02 (UART 02 in Linux) */ + +/* The following address was not defined in Linux */ +#define CONFIG_FTUART010_03_BASE 0x9820 /* FF UART 3 */ +#define CONFIG_FTSSP010_01_BASE0x98B0 /* Synchronous Serial Port Controller (SSP) 01 */ +#define CONFIG_IRDA_BASE 0x9890 /* IrDA */ +#define CONFIG_PMW_BASE0x9910 /* PWM - Pulse Width Modulator Controller */ + +#endif /* __AG101_H */ -- 1.7.3.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v8 05/10] nds32/ag101: lowlevel_init.S of ag101
lowlevel_init.S is a peripheral initial procedure of ag101. It configures onboard dram, clock, and power settings. It also prepars the dram environment before moving u-boot from rom and flash into dram. This version of lowlevel_init.S also replace hardcode value by MARCO defines from the GPL version andesboot for better code quality. Signed-off-by: Macpaul Lin macp...@andestech.com --- ChangeLog from v1-v4: - Code clean up and formatting style. ChangeLog from v5-v6 - Change hard code value into MARCO definitions. - ftsmc010 - Fix FTSMC020_TPR_AT2 from 1 to 3 (0xff3ff) - ftsdmc021 - Fix hardcoded address of CR1, CR2, TR1, TR2, BANK0 registers. - Fix the default configuration value of FTSDMC and FTSMC controller. - Remove some ftpmu010 and flash probe code to C functions. arch/nds32/cpu/n1213/ag101/lowlevel_init.S | 160 1 files changed, 160 insertions(+), 0 deletions(-) create mode 100644 arch/nds32/cpu/n1213/ag101/lowlevel_init.S diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S new file mode 100644 index 000..96969ba --- /dev/null +++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S @@ -0,0 +1,160 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuh...@andestech.com + * Macpaul Lin, Andes Technology Corporation macp...@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +.text + +#include common.h +#include config.h + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +.globl lowlevel_init +lowlevel_init: + move$r10, $lp + jal mem_init + jal remap + + ret $r10 + +mem_init: + move$r11, $lp + + /* +* mem_init: +* There are 2 bank connected to FTSMC020 on AG101 +* BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM. +* we need to set onboard SDRAM before remap and relocation. +*/ + li $r0, (CONFIG_FTSMC020_BASE+FTSMC020_BANK0_CR) + li $r1, (FTSMC020_BANK1_CONFIG)! 0x1052 + swi $r1, [$r0] + li $r1, (FTSMC020_BANK1_TIMING)! 0x00151151 + swi $r1, [$r0+FTSMC020_BANK0_TPR] + + /* +* config AHB Controller +*/ + li $r0, (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6) + li $r1, (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6) + swi $r1, [$r0] + + /* +* config PMU +*/ + li $r0, (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0) + lwi $r1, [$r0] + ! ftpmu010_dlldis_disable, must do it in lowleve_init + li $r2, FTPMU010_PDLLCR0_DLLDIS! 0x0001 + or $r1, $r1, $r2 + swi $r1, [$r0] + + /* +* config SDRAM controller +*/ + li $r0, (CONFIG_FTSDMC021_BASE) + li $r1, (CONFIG_SYS_FTSDMC021_TP1) ! 0x00011312 + swi $r1, [$r0] + li $r1, (CONFIG_SYS_FTSDMC021_TP2) ! 0x00480180 + swi $r1, [$r0+FTSDMC021_OFFSET_TP2] + li $r1, (CONFIG_SYS_FTSDMC021_CR1) ! 0x2326 + swi $r1, [$r0+FTSDMC021_OFFSET_CR1] + li $r1, (FTSDMC021_CR2_IPREC) ! 0x0010 + swi $r1, [$r0+FTSDMC021_OFFSET_CR2] +1: + lwi $r1, [$r0+FTSDMC021_OFFSET_CR2] + andi$r1, $r1, (CONFIG_SYS_FTSDMC021_CR2)! 0x1C + bnez$r1, 1b + + li $r1, (FTSDMC021_CR2_ISMR) ! 0x0004 + swi $r1, [$r0+FTSDMC021_OFFSET_CR2] +2: + lwi $r1, [$r0+FTSDMC021_OFFSET_CR2] + bnez$r1, 2b + + li $r1, (FTSDMC021_CR2_IREF) ! 0x0008 + swi $r1, [$r0+FTSDMC021_OFFSET_CR2] +3: + lwi $r1, [$r0+FTSDMC021_OFFSET_CR2] + bnez$r1, 3b + + move$lp, $r11 + ret + +remap: + move$r11, $lp +#ifdef __NDS32_N1213_43U1H__ /* AG101 */ + bal 2f +relo_base: + move$r0, $lp +#else +relo_base: + mfusr $r0, $pc +#endif + + /* +* relocation, copy ROM code to SDRAM (current at 0x1000) +*/ + li $r4, CONFIG_SYS_RELO_ADDR
[U-Boot] [PATCH v8 06/10] nds32/ag101: cpu and init funcs of SoC ag101
Add main function of SoC ag101 based on NDS32 n1213 core. cpu.c According to the bootstrap procedure in n1213 Core, to turn off watchdog timer is suggested after the cpu is in superuser mdoe. 1. bootstrap 1.1 reset - start of Andesboot 1.2 to superuser mode - as is when reset 1.3 Turn off watchdog timer If you take look into the start.S in n1213, you will find that system will turn off watchdog after start.S has been retunred from lowlevel_init. Since the watchdog device is depends on the SoC is choosed. It should be belonged to the SoC (ag101) folder. watchdog.S: If you've ran another bootloader before u-boot was started the watchdog might have been enabled already. Signed-off-by: Macpaul Lin macp...@andestech.com --- Changes for v5-v6: - Split watchdog.S from lowlevel_init.S. - Fix hardware reset by using watchdog reset in do_reset() in cpu.c. - reset_cpu was remove inside do_reset(). Changes for v7: - clean up. arch/nds32/cpu/n1213/ag101/Makefile | 58 + arch/nds32/cpu/n1213/ag101/cpu.c | 207 + arch/nds32/cpu/n1213/ag101/timer.c| 204 arch/nds32/cpu/n1213/ag101/watchdog.S | 48 4 files changed, 517 insertions(+), 0 deletions(-) create mode 100644 arch/nds32/cpu/n1213/ag101/Makefile create mode 100644 arch/nds32/cpu/n1213/ag101/cpu.c create mode 100644 arch/nds32/cpu/n1213/ag101/timer.c create mode 100644 arch/nds32/cpu/n1213/ag101/watchdog.S diff --git a/arch/nds32/cpu/n1213/ag101/Makefile b/arch/nds32/cpu/n1213/ag101/Makefile new file mode 100644 index 000..e96b1e4 --- /dev/null +++ b/arch/nds32/cpu/n1213/ag101/Makefile @@ -0,0 +1,58 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor www.marvell.com +# Written-by: Prafulla Wadaskar prafu...@marvell.com +# +# Copyright (C) 2011 Andes Technology Corporation +# Shawn Lin, Andes Technology Corporation nobuh...@andestech.com +# Macpaul Lin, Andes Technology Corporation macp...@andestech.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(SOC).o + +COBJS-y:= cpu.o timer.o + +ifndef CONFIG_SKIP_LOWLEVEL_INIT +SOBJS := lowlevel_init.o +endif + +ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG +SOBJS += watchdog.o +endif + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) + +all: $(obj).depend $(LIB) + +$(LIB):$(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/arch/nds32/cpu/n1213/ag101/cpu.c b/arch/nds32/cpu/n1213/ag101/cpu.c new file mode 100644 index 000..8e7eb0a --- /dev/null +++ b/arch/nds32/cpu/n1213/ag101/cpu.c @@ -0,0 +1,207 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH www.elinos.com + * Marius Groeger mgroe...@sysgo.de + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, g...@denx.de + * + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuh...@andestech.com + * Macpaul Lin, Andes Technology Corporation macp...@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* CPU specific code */ +#include common.h +#include command.h +#include watchdog.h +#include
[U-Boot] [PATCH v8 07/10] nds32/lib: add generic funcs in NDS32 lib
Add Makefile, board.c, interrupts.c and bootm.c functions to nds32 architecture. Signed-off-by: Macpaul Lin macp...@andestech.com --- Changes for v1-v4: - code clean up and formatting style. Changes for v5-v6: - board.c - Do some clean up and add code - Remove display banner which hasn't support. - Add ftpmu010 related power management unit code. - Remove useless LED related code. - Move SDRAM init to board sepecific files. (ex. adp-ag101.c) - Remove CONFIG_SOFT_I2C which hasn't been support. - Remove CONFIG_FSL_ESDHC which hasn't been support. - clean up. Changes for v7: - clean up. - move single file patch arch/nds32/config.mk to this commit. - interrupts.c refine origin interrupt enable and disable. Changes for v8: - interrups.c: fix up for new ptraces.h. arch/nds32/config.mk| 35 + arch/nds32/lib/Makefile | 52 +++ arch/nds32/lib/board.c | 346 +++ arch/nds32/lib/bootm.c | 241 ++ arch/nds32/lib/interrupts.c | 131 5 files changed, 805 insertions(+), 0 deletions(-) create mode 100644 arch/nds32/config.mk create mode 100644 arch/nds32/lib/Makefile create mode 100644 arch/nds32/lib/board.c create mode 100644 arch/nds32/lib/bootm.c create mode 100644 arch/nds32/lib/interrupts.c diff --git a/arch/nds32/config.mk b/arch/nds32/config.mk new file mode 100644 index 000..ac5d0cf --- /dev/null +++ b/arch/nds32/config.mk @@ -0,0 +1,35 @@ +# +# (C) Copyright 2000-2002 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# (C) Copyright 2011 +# Shawn Lin, Andes Technology Corporation nobuh...@andestech.com +# Macpaul Lin, Andes Technology Corporation macp...@andestech.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +CROSS_COMPILE ?= nds32le-linux- + +STANDALONE_LOAD_ADDR = 0x30 -T nds32.lds + +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common +PLATFORM_RELFLAGS += -gdwarf-2 +PLATFORM_CPPFLAGS += -DCONFIG_NDS32 -D__nds32__ -G0 -ffixed-8 + +LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds diff --git a/arch/nds32/lib/Makefile b/arch/nds32/lib/Makefile new file mode 100644 index 000..eca4324 --- /dev/null +++ b/arch/nds32/lib/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# Copyright (C) 2011 Andes Technology Corporation +# Shawn Lin, Andes Technology Corporation nobuh...@andestech.com +# Macpaul Lin, Andes Technology Corporation macp...@andestech.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(ARCH).o + +OBJS := board.o bootm.o interrupts.o + +all: $(LIB) + +$(LIB):$(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c new file mode 100644 index 000..6ed4194 --- /dev/null +++ b/arch/nds32/lib/board.c @@ -0,0 +1,346 @@ +/* + * (C) Copyright 2002-2006 + * Wolfgang Denk, DENX Software Engineering, w...@denx.de. + * + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation
[U-Boot] [PATCH v8 08/10] nds32: standalone support
Add standalone program related support for nds32 architecture.
Signed-off-by: Macpaul Lin macp...@andestech.com
---
examples/standalone/nds32.lds | 64 +
examples/standalone/stubs.c | 17 +-
examples/standalone/x86-testapp.c | 12 +++
3 files changed, 92 insertions(+), 1 deletions(-)
create mode 100644 examples/standalone/nds32.lds
diff --git a/examples/standalone/nds32.lds b/examples/standalone/nds32.lds
new file mode 100644
index 000..c2ac107
--- /dev/null
+++ b/examples/standalone/nds32.lds
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation nobuh...@andestech.com
+ * Macpaul Lin, Andes Technology Corporation macp...@andestech.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT(elf32-nds32, elf32-nds32, elf32-nds32)
+OUTPUT_ARCH(nds32)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+
+ .got : {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ __bss_end = .;
+
+ . = ALIGN(4);
+ .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
+
+ _end = .;
+
+ . = 0x0200;
+ .u_boot_ohci_data_st : { *(.u_boot_ohci_data_st) }
+}
diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c
index 2d2e709..b711926 100644
--- a/examples/standalone/stubs.c
+++ b/examples/standalone/stubs.c
@@ -167,8 +167,23 @@ gd_t *global_data;
jmp %%g1\n \
nop\n \
: : i(offsetof(gd_t, jt)), i(XF_ ## x * sizeof(void *)) : g1 );
-
+#elif defined(CONFIG_NDS32)
+/*
+ * r16 holds the pointer to the global_data. gp is call clobbered.
+ * not support reduced register (16 GPR).
+ */
+#define EXPORT_FUNC(x) \
+ asm volatile ( \
+ .globl #x \n\
+#x :\n \
+ lwi $r16, [$gp + (%0)]\n \
+ lwi $r16, [$r16 + (%1)]\n \
+ jr $r16\n \
+ : : i(offsetof(gd_t, jt)), i(XF_ ## x * sizeof(void *)) : $r16);
#else
+/*addi$sp, $sp, -24\n\
+ br $r16\n \*/
+
#error stubs definition missing for this architecture
#endif
diff --git a/examples/standalone/x86-testapp.c
b/examples/standalone/x86-testapp.c
index e8603d9..a4ac6f8 100644
--- a/examples/standalone/x86-testapp.c
+++ b/examples/standalone/x86-testapp.c
@@ -52,6 +52,16 @@ asm volatile (
\
lw $25, %1($25)\n \
jr $25\n \
: : i(offsetof(xxx_t, pfunc)), i(XF_ ## x * sizeof(void *)) : t9);
+#elif defined(__nds32__)
+#define EXPORT_FUNC(x) \
+asm volatile ( \
+ .globl mon_ #x \n\
+mon_ #x :\n\
+ lwi $r16, [$gp + (%0)]\n \
+ lwi $r16, [$r16 + (%1)]\n \
+ jr $r16\n \
+ : : i(offsetof(xxx_t, pfunc)), i(XF_ ## x * sizeof(void *)) :
$r16);
+
#else
#error [No stub code for this arch]
#endif
@@ -72,6 +82,8 @@ int main(void)
register volatile xxx_t *pq asm(r8);
#elif defined(__mips__)
register volatile xxx_t *pq asm(k0);
+#elif defined(__nds32__)
+ register volatile xxx_t *pq asm($r16);
#endif
char buf[32];
--
1.7.3.5
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[U-Boot] [PATCH v8 09/10] nds32: common bdinfo, bootm, image support
Add support of NDS32 to common commands bdinfo, bootm, and image format.
Signed-off-by: Macpaul Lin macp...@andestech.com
---
common/cmd_bdinfo.c | 28 +++-
common/cmd_bootm.c |2 ++
common/image.c |1 +
include/image.h |5 +
4 files changed, 35 insertions(+), 1 deletions(-)
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index bba7374..908091d 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -411,13 +411,39 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
return 0;
}
+#elif defined(CONFIG_NDS32)
+
+int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int i;
+ bd_t *bd = gd-bd;
+
+ print_num(arch_number,bd-bi_arch_number);
+ print_num(env_t, (ulong)bd-bi_env);
+ print_num(boot_params,(ulong)bd-bi_boot_params);
+
+ for (i = 0; i CONFIG_NR_DRAM_BANKS; ++i) {
+ print_num(DRAM bank, i);
+ print_num(- start, bd-bi_dram[i].start);
+ print_num(- size,bd-bi_dram[i].size);
+ }
+
+#if defined(CONFIG_CMD_NET)
+ print_eth(0);
+ printf(ip_addr = %pI4\n, bd-bi_ip_addr);
+#endif
+ printf(baudrate= %d bps\n, bd-bi_baudrate);
+
+ return 0;
+}
+
#else
#error a case for this architecture does not exist!
#endif
static void print_num(const char *name, ulong value)
{
- printf (%-12s= 0x%08lX\n, name, value);
+ printf(%-12s= 0x%08lX\n, name, value);
}
#if !(defined(CONFIG_ARM) || defined(CONFIG_M68K)) || defined(CONFIG_CMD_NET)
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 18019d6..59fbc45 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -187,6 +187,8 @@ void arch_preboot_os(void) __attribute__((weak,
alias(__arch_preboot_os)));
#define IH_INITRD_ARCH IH_ARCH_SH
#elif defined(__sparc__)
#define IH_INITRD_ARCH IH_ARCH_SPARC
+#elif defined(__nds32__)
+ #define IH_INITRD_ARCH IH_ARCH_NDS32
#else
# error Unknown CPU type
#endif
diff --git a/common/image.c b/common/image.c
index f63a2ff..afe5957 100644
--- a/common/image.c
+++ b/common/image.c
@@ -93,6 +93,7 @@ static const table_entry_t uimage_arch[] = {
{ IH_ARCH_SPARC64,sparc64, SPARC 64 Bit, },
{ IH_ARCH_BLACKFIN, blackfin, Blackfin, },
{ IH_ARCH_AVR32, avr32,AVR32,},
+ { IH_ARCH_NDS32, nds32,NDS32,},
{ -1, , , },
};
diff --git a/include/image.h b/include/image.h
index 005e0d2..1a2be5e 100644
--- a/include/image.h
+++ b/include/image.h
@@ -106,6 +106,7 @@
#define IH_ARCH_BLACKFIN 16 /* Blackfin */
#define IH_ARCH_AVR32 17 /* AVR32*/
#define IH_ARCH_ST200 18 /* STMicroelectronics ST200 */
+#define IH_ARCH_NDS32 19 /* ANDES Technology - NDS32 */
/*
* Image Types
@@ -504,6 +505,8 @@ static inline int image_check_target_arch (const
image_header_t *hdr)
if (!image_check_arch (hdr, IH_ARCH_SH))
#elif defined(__sparc__)
if (!image_check_arch (hdr, IH_ARCH_SPARC))
+#elif defined(__nds32__)
+ if (!image_check_arch(hdr, IH_ARCH_NDS32))
#else
# error Unknown CPU type
#endif
@@ -656,6 +659,8 @@ static inline int fit_image_check_target_arch (const void
*fdt, int node)
if (!fit_image_check_arch (fdt, node, IH_ARCH_SH))
#elif defined(__sparc__)
if (!fit_image_check_arch (fdt, node, IH_ARCH_SPARC))
+#elif defined(__nds32__)
+ if (!fit_image_check_arch(fdt, node, IH_ARCH_NDS32))
#else
# error Unknown CPU type
#endif
--
1.7.3.5
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[U-Boot] [PATCH v8 10/10] adp-ag101: add board adp-ag101 support
Add evaluation board adp-ag101 aconfiguration file adp-ag101.h.
Add adp-ag101.c board config and related settings.
Add board adp-ag101 into boards.cfg
Signed-off-by: Macpaul Lin macp...@andestech.com
---
Changes for v1-v4:
- code clean up
Changes for v5-v6:
- Refine the definitions and parameters about CLK,
AHB controller, SDRAM controller, Static memory controllers.
- Add APB_CLK, AHB_CLK, SYS_CLK definitions for backward compatible.
- ftahbc010:
- Update include path of ftahbc010.
- ftsdmc021:
- Update include path of ftsdmc021.
- ftsmc020:
- Update include path of ftsmc020.
- ftwdt010:
- Fix WDT define and update include path.
- Fix ftwdt010 for hardware reset.
- ftpmu010:
- Remove duplicate PMU definitions.
- Add related configurations.
- Fix MAX malloc len and fix saveenv.
- clean up.
Changes for v7:
- adp-ag101.c
- Fix Makefile and remove config.mk
- adp-ag101.h:
- clean up.
- Move CONFIG_SYS_TEXT_BASE from board/config.mk.
MAINTAINERS | 11 +
MAKEALL |6 +
board/AndesTech/adp-ag101/Makefile| 57 +
board/AndesTech/adp-ag101/adp-ag101.c | 81 +++
boards.cfg|1 +
include/configs/adp-ag101.h | 378 +
6 files changed, 534 insertions(+), 0 deletions(-)
create mode 100644 board/AndesTech/adp-ag101/Makefile
create mode 100644 board/AndesTech/adp-ag101/adp-ag101.c
create mode 100644 include/configs/adp-ag101.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 8af9b09..0390c40 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1123,5 +1123,16 @@ Chong Huang chu...@ucrobotics.com
bf525-ucr2 BF525
#
+# NDS32 Systems: #
+# #
+# Maintainer Name, Email Address #
+# Board CPU #
+#
+
+Macpaul Lin macp...@andestech.com
+
+ ADP-AG101 N1213 (AG101 SoC)
+
+#
# End of MAINTAINERS list #
#
diff --git a/MAKEALL b/MAKEALL
index e1b928f..286d158 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -610,6 +610,12 @@ LIST_sh=$(boards_by_arch sh)
LIST_sparc=$(boards_by_arch sparc)
+#
+## NDS32 Systems
+#
+
+LIST_nds32=$(boards_by_arch nds32)
+
#---
build_target() {
diff --git a/board/AndesTech/adp-ag101/Makefile
b/board/AndesTech/adp-ag101/Makefile
new file mode 100644
index 000..5a403b1
--- /dev/null
+++ b/board/AndesTech/adp-ag101/Makefile
@@ -0,0 +1,57 @@
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation nobuh...@andestech.com
+# Macpaul Lin, Andes Technology Corporation macp...@andestech.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS := adp-ag101.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+ifdef CONFIG_SYS_LDSCRIPT
+LDSCRIPT := $(subst ,,$(CONFIG_SYS_LDSCRIPT))
+else
+LDSCRIPT := $(SRCTREE)/arch/$(ARCH)/cpu/$(CPU)/u-boot.lds
+endif
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git
[U-Boot] [PATCH v2] ARM: mx31: Print the silicon version
Use the same method of the Linux kernel to print the MX31 silicon version on
boot.
Tested on a MX31PDK with a 2.0 silicon, where it shows:
CPU: Freescale i.MX31 at 531 MHz
MX31 silicon rev 2.0
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
Changes since v1:
- rename the CPU detect function name to get_cpu_rev
- Use struct to access iim register
arch/arm/cpu/arm1136/mx31/generic.c | 18
arch/arm/include/asm/arch-mx31/imx-regs.h | 20 +
arch/arm/include/asm/imx_soc_revision.h | 42 +
3 files changed, 80 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/imx_soc_revision.h
diff --git a/arch/arm/cpu/arm1136/mx31/generic.c
b/arch/arm/cpu/arm1136/mx31/generic.c
index fa07fec..cfcb3d8 100644
--- a/arch/arm/cpu/arm1136/mx31/generic.c
+++ b/arch/arm/cpu/arm1136/mx31/generic.c
@@ -24,6 +24,7 @@
#include common.h
#include asm/arch/imx-regs.h
#include asm/io.h
+#include asm/imx_soc_revision.h
static u32 mx31_decode_pll(u32 reg, u32 infreq)
{
@@ -106,11 +107,28 @@ void mx31_set_pad(enum iomux_pins pin, u32 config)
}
+void get_cpu_rev(void)
+{
+ u32 i, srev;
+
+ /* read SREV register from IIM module */
+ struct iim_regs *iim = (struct iim_regs *)MX31_IIM_BASE_ADDR;
+ srev = readl(iim-iim_srev);
+
+ for (i = 0; i ARRAY_SIZE(mx31_cpu_type); i++)
+ if (srev == mx31_cpu_type[i].srev) {
+ printf(MX31 silicon rev %s\n, mx31_cpu_type[i].v);
+ return;
+ }
+ printf(Unknown CPU identifier. srev = %02x\n, srev);
+}
+
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo (void)
{
printf(CPU: Freescale i.MX31 at %d MHz\n,
mx31_get_mcu_main_clk() / 100);
+ get_cpu_rev();
return 0;
}
#endif
diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h
b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 37337f2..6401a37 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -84,6 +84,24 @@ struct wdog_regs {
u16 wrsr; /* Reset Status */
};
+/* IIM Control Registers */
+struct iim_regs {
+ u32 iim_stat;
+ u32 iim_statm;
+ u32 iim_err;
+ u32 iim_emask;
+ u32 iim_fctl;
+ u32 iim_ua;
+ u32 iim_la;
+ u32 iim_sdat;
+ u32 iim_prev;
+ u32 iim_srev;
+ u32 iim_prog_p;
+ u32 iim_scs0;
+ u32 iim_scs1;
+ u32 iim_scs2;
+ u32 iim_scs3;
+};
#define IOMUX_PADNUM_MASK 0x1ff
#define IOMUX_PIN(gpionum, padnum) ((padnum) IOMUX_PADNUM_MASK)
@@ -480,6 +498,8 @@ enum iomux_pins {
#define CCMR_FPM (1 1)
#define CCMR_CKIH (2 1)
+#define MX31_IIM_BASE_ADDR 0x5001C000
+
#define PDR0_CSI_PODF(x) (((x) 0x1ff) 23)
#define PDR0_PER_PODF(x) (((x) 0x1f) 16)
#define PDR0_HSP_PODF(x) (((x) 0x7) 11)
diff --git a/arch/arm/include/asm/imx_soc_revision.h
b/arch/arm/include/asm/imx_soc_revision.h
new file mode 100644
index 000..0179d52
--- /dev/null
+++ b/arch/arm/include/asm/imx_soc_revision.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * Fabio Estevam fabio.este...@freescale.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ */
+
+#define IMX_CHIP_REVISION_1_0 0x10
+#define IMX_CHIP_REVISION_1_1 0x11
+#define IMX_CHIP_REVISION_1_2 0x12
+#define IMX_CHIP_REVISION_1_3 0x13
+#define IMX_CHIP_REVISION_2_0 0x20
+#define IMX_CHIP_REVISION_2_1 0x21
+#define IMX_CHIP_REVISION_2_2 0x22
+#define IMX_CHIP_REVISION_2_3 0x23
+#define IMX_CHIP_REVISION_3_0 0x30
+#define IMX_CHIP_REVISION_3_1 0x31
+#define IMX_CHIP_REVISION_3_2 0x32
+#define IMX_CHIP_REVISION_3_3 0x33
+#define IMX_CHIP_REVISION_UNKNOWN 0xff
+
+struct mx3_cpu_type {
+ u8 srev;
+ const char *name;
+ const char *v;
+ unsigned int rev;
+};
+
+struct mx3_cpu_type mx31_cpu_type[] = {
+ { .srev = 0x00, .name = i.MX31(L), .v = 1.0, .rev =
IMX_CHIP_REVISION_1_0 },
+ { .srev = 0x10, .name = i.MX31,.v = 1.1, .rev =
IMX_CHIP_REVISION_1_1 },
+ { .srev = 0x11, .name = i.MX31L, .v = 1.1, .rev =
IMX_CHIP_REVISION_1_1 },
+ { .srev = 0x12, .name = i.MX31,.v = 1.15, .rev =
IMX_CHIP_REVISION_1_1 },
+ { .srev = 0x13, .name = i.MX31L, .v = 1.15, .rev =
IMX_CHIP_REVISION_1_1 },
+ { .srev = 0x14, .name = i.MX31,.v = 1.2, .rev =
IMX_CHIP_REVISION_1_2 },
+ { .srev = 0x15, .name = i.MX31L, .v = 1.2, .rev =
IMX_CHIP_REVISION_1_2 },
+ { .srev = 0x28, .name = i.MX31,.v = 2.0, .rev =
IMX_CHIP_REVISION_2_0 },
+ { .srev = 0x29, .name = i.MX31L, .v
Re: [U-Boot] [PATCH] ARM: mx31: Print the silicon version
Hi Stefano,
On 3/11/2011 10:33 AM, Stefano Babic wrote:
On 03/10/2011 08:26 PM, Fabio Estevam wrote:
+void mx31_read_cpu_rev(void)
Generally, for exported function, I would prefer to remove the processor
name. For other i.MX processors we use the convention
mxc_function_name, as we can get rid of nasty #ifdef inside the
drivers. You can see a lot of examples in code.
Ok.
+{
+u32 i, srev;
+
+/* read SREV register from IIM module */
+srev = __raw_readl(MX31_IIM_BASE_ADDR + MXC_IIMSREV);
We have already used the IIM registers on other i.MX processors, you can
see for i.MX35/MX51/MX53. You should set a structure for the iim
registers and use it, instead of using offset.
I know the i.MX31, as it was the first i.MX31, does not follow this
rule, but it means it should be clean up.
Ok.
diff --git a/arch/arm/include/asm/arch-mx31/mx31-regs.h
b/arch/arm/include/asm/arch-mx31/mx31-regs.h
index 37337f2..cc0ffc8 100644
--- a/arch/arm/include/asm/arch-mx31/mx31-regs.h
+++ b/arch/arm/include/asm/arch-mx31/mx31-regs.h
@@ -480,6 +480,10 @@ enum iomux_pins {
#define CCMR_FPM(1 1)
#define CCMR_CKIH (2 1)
+#define MX31_SPBA0_BASE_ADDR0x5000
+#define MX31_IIM_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x1c000)
+#define MXC_IIMSREV 0x0024
As I said, replace them with a structure.
Ok.
+++ b/arch/arm/include/asm/imx_soc_revision.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * Fabio Estevam fabio.este...@freescale.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ */
+
+#define IMX_CHIP_REVISION_1_0 0x10
+#define IMX_CHIP_REVISION_1_1 0x11
+#define IMX_CHIP_REVISION_1_2 0x12
+#define IMX_CHIP_REVISION_1_3 0x13
+#define IMX_CHIP_REVISION_2_0 0x20
+#define IMX_CHIP_REVISION_2_1 0x21
+#define IMX_CHIP_REVISION_2_2 0x22
+#define IMX_CHIP_REVISION_2_3 0x23
+#define IMX_CHIP_REVISION_3_0 0x30
+#define IMX_CHIP_REVISION_3_1 0x31
+#define IMX_CHIP_REVISION_3_2 0x32
+#define IMX_CHIP_REVISION_3_3 0x33
+#define IMX_CHIP_REVISION_UNKNOWN 0xff
Is there a good reason to add a further file and not put them inside
inside the mx31-regs.h file ?
Yes, the idea is that other i.MX processors can reuse this file.
We currently use this same approach in the kernel.
Will post v2 with your recommendations.
Regards,
Fabio Estevam
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[U-Boot] Daughter card detection
Hi I am trying to detect a daughter card chip. From data sheet I was able to find the address for that chip. But when I use i2c probe command from uboot shell, it is showing me only 4 addresses. And these 4 addresses does not contain the address of any chip on the daughter card. So my query is : 1. how can I detect the daughter card chips using i2c. 2. why i2c probe command is not showing the chip addresses for daughter card as mentioned on the data sheet. But that is giving the correct address of EEPROM. Here I want to mention that the card is working fine but not able to identify the chips on the daughter card mounted on davinci evm board. Information contained and transmitted by this e-mail is confidential and proprietary to Patni Computer Systems Ltd and its affiliates (hitherto referred as Patni Computers) and is intended for use only by the recipient. If you are not the intended recipient , you are hereby notified that any dissemination, distribution, copying or use of this e-mail is strictly prohibited and you are requested to delete this e-mail immediately and notify the originator or netad...@patni.com. Patni Computers does not enter into any agreement with any party by e-mail. Any views expressed by an individual do not necessarily reflect the view of Patni Computers. Patni Computers is not responsible for the consequences of any actions taken on the basis of information provided, through this email. The contents of an attachment to this e-mail may contain software viruses, which could damage your own computer system. While Patni Computers has taken every reasonable precaution to minimise this risk, we cannot accept liability for any damage which you sustain as a result of software viruses. You should carry out your own virus checks before opening an attachment. To know more about Patni Computers please visit www.patni.com. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] fsl_esdhc: Fix multi-block read restriction on i.MX53 eSDHCv2
Hi, Kumar Gala 2011/3/22 Jason Liu jason@linaro.org: For freescale i.MX53 eSDHCv2, when using CMD12, cmdtype need to be set to ABORT, otherwise, next read command will hang. This is a software Software Restrictions in i.MX53 reference manual: 29.7.8 Multi-block Read For pre-defined multi-block read operation, that is,the number of blocks to read has been defined by previous CMD23 for MMC, or pre-defined number of blocks in CMD53 for SDIO/SDCombo,or whatever multi-block read without abort command at card side, an abort command, either automatic or manual CMD12/CMD52, is still required by ESDHC after the pre-defined number of blocks are done, to drive the internal state machine to idle mode. In this case, the card may not respond to this extra abort command and ESDHC will get Response Timeout. It is recommended to manually send an abort command with RSPTYP[1:0] both bits cleared. Signed-off-by: Jason Liu jason@linaro.org --- drivers/mmc/fsl_esdhc.c | 4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index f3cccbe..5c3618b 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -99,6 +99,10 @@ uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) else if (cmd-resp_type MMC_RSP_PRESENT) xfertyp |= XFERTYP_RSPTYP_48; +#ifdef CONFIG_MX53 + if (cmd-cmdidx == MMC_CMD_STOP_TRANSMISSION) + xfertyp |= XFERTYP_CMDTYP_ABORT; +#endif return XFERTYP_CMD(cmd-cmdidx) | xfertyp; } Ping, Any comments? -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] fsl_esdhc: Fix multi-block read restriction on i.MX53 eSDHCv2
On Apr 10, 2011, at 11:43 PM, Jason Liu wrote: Hi, Kumar Gala 2011/3/22 Jason Liu jason@linaro.org: For freescale i.MX53 eSDHCv2, when using CMD12, cmdtype need to be set to ABORT, otherwise, next read command will hang. This is a software Software Restrictions in i.MX53 reference manual: 29.7.8 Multi-block Read For pre-defined multi-block read operation, that is,the number of blocks to read has been defined by previous CMD23 for MMC, or pre-defined number of blocks in CMD53 for SDIO/SDCombo,or whatever multi-block read without abort command at card side, an abort command, either automatic or manual CMD12/CMD52, is still required by ESDHC after the pre-defined number of blocks are done, to drive the internal state machine to idle mode. In this case, the card may not respond to this extra abort command and ESDHC will get Response Timeout. It is recommended to manually send an abort command with RSPTYP[1:0] both bits cleared. Signed-off-by: Jason Liu jason@linaro.org --- drivers/mmc/fsl_esdhc.c |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index f3cccbe..5c3618b 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -99,6 +99,10 @@ uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) else if (cmd-resp_type MMC_RSP_PRESENT) xfertyp |= XFERTYP_RSPTYP_48; +#ifdef CONFIG_MX53 + if (cmd-cmdidx == MMC_CMD_STOP_TRANSMISSION) + xfertyp |= XFERTYP_CMDTYP_ABORT; +#endif return XFERTYP_CMD(cmd-cmdidx) | xfertyp; } Ping, Any comments? No issues as this is protected with a CONFIG_MX53 so will not impact an PPC SoCs - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
