[U-Boot] [PATCH 5/6] powerpc/corenet_ds: Master module for boot from PCIE
For the powerpc processors with PCIE interface, boot location can be
configured from one PCIE interface by RCW. The processor booting from PCIE
can do without flash for u-boot image. The image can be fetched from another
processor's memory space by PCIE link connected between them.
The processor booting from PCIE is slave, the processor booting from normal
flash memory space is master, and it can help slave to boot from master's
memory space.
When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.
Environment and requirement:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image is in master NOR flash.
3. Normally boot from local NOR flash.
4. Configure PCIE system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to one PCIE interface by RCW.
3. RCW should configure the SerDes, PCIE interfaces correctly.
4. Must set all the cores in holdoff by RCW.
5. Must be powered on before master's boot.
For the master module, need to finish these processes:
1. Initialize the PCIE port and address space.
2. Set inbound PCIE windows covered slave's u-boot image stored in
master's NOR flash.
3. Set outbound windows in order to configure slave's registers
for the core's releasing.
4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2"
or "PCIE3" using the following command:
setenv bootmaster PCIE1
saveenv
Signed-off-by: Liu Gang
---
arch/powerpc/cpu/mpc8xxx/srio.c | 44
drivers/pci/fsl_pci_init.c | 111 ++-
include/configs/corenet_ds.h| 18 +++---
3 files changed, 140 insertions(+), 33 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index 0ba7e2a..02b830d 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -107,44 +107,44 @@ void srio_boot_master(int port)
/* configure inbound window for slave's u-boot image */
debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
- (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS,
- (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS1,
- CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
+ (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
+ (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
+ CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwtar,
- CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS >> 12);
+ CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwbar,
- CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS1 >> 12);
+ CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12);
out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwar,
SRIO_IB_ATMU_AR
- | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
+ | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE));
/* configure inbound window for slave's u-boot image */
debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
- (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS,
- (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS2,
- CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
+ (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
+ (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
+ CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwtar,
- CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS >> 12);
+ CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwbar,
- CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS2 >> 12);
+ CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12);
out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwar,
SRIO_IB_ATMU_AR
- | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
+ | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE));
/* configure inbound window for slave's ucode and ENV */
debug("SRIOBOOT - MASTER: Inbound window for slave's ucode and ENV; "
"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
- (u64)CONFIG_SR
[U-Boot] [PATCH 6/6] powerpc/corenet_ds: Slave module for boot from PCIE
When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.
Slave's ucode and ENV can be stored in master's memory space, then slave
can fetch them through PCIE interface. For the corenet platform, ucode is
for Fman.
NOTE: Because the slave can not erase, write master's NOR flash by
PCIE interface, so it can not modify the ENV parameters stored
in master's NOR flash using "saveenv" or other commands.
environment and requirement:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image is in master NOR flash.
3. Put the slave's ucode and ENV into it's own memory space.
4. Normally boot from local NOR flash.
5. Configure PCIE system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to one PCIE interface by RCW.
3. RCW should configure the SerDes, PCIE interfaces correctly.
4. Must set all the cores in holdoff by RCW.
5. Must be powered on before master's boot.
For the slave module, need to finish these processes:
1. Set the boot location to one PCIE interface by RCW.
2. Set a specific TLB entry for the boot process.
3. Set a LAW entry with the TargetID of one PCIE for the boot.
4. Set a specific TLB entry in order to fetch ucode and ENV from
master.
5. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
6. Slave's u-boot image should be generated specifically by
make _SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF8 and other configurations.
In addition, the processes are very similar between boot from SRIO and
boot from PCIE. Some configurations like the address spaces can be set to
the same. So the module of boot from PCIE was added based on the existing
module of boot from SRIO, and the following changes were needed:
1. Updated the README.srio-boot-corenet to add descriptions about
boot from PCIE, and change the name to
README.srio-pcie-boot-corenet.
2. Changed the compile config "_SRIOBOOT_SLAVE" to
"_SRIO_PCIE_BOOT", and the image builded with
"_SRIO_PCIE_BOOT" can support both the boot from SRIO and
from PCIE.
3. Updated other macros and documents if needed to add information
about boot from PCIE.
Signed-off-by: Liu Gang
---
board/freescale/common/p_corenet/tlb.c | 18 +++---
boards.cfg |6 ++--
common/env_remote.c|4 +-
drivers/misc/fsl_law.c | 39 +++-
include/configs/corenet_ds.h | 28 +++---
5 files changed, 61 insertions(+), 34 deletions(-)
diff --git a/board/freescale/common/p_corenet/tlb.c
b/board/freescale/common/p_corenet/tlb.c
index da21627..e5cf208 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -66,13 +66,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
-#elif defined(CONFIG_SRIOBOOT_SLAVE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
-* SRIOBOOT-SLAVE. When slave boot, the address of the
+* SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
* space is at 0xfff0, it covered the 0xf000.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_SLAVE_ADDR,
- CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
#else
@@ -147,13 +147,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_1M, 1),
#endif
-#ifdef CONFIG_SRIOBOOT_SLAVE
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/*
-* SRIOBOOT-SLAVE. 1M space from 0xffe0 for fetching ucode
-* and ENV from master
+* SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe0 for
+* fetching ucode and ENV from master
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR,
- CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
0, 17, BOOKE_PAGESZ_1M, 1),
#endif
diff --git a/boards.cfg b/boards.cfg
index
[U-Boot] [PATCH 4/6] powerpc/corenet_ds: Update README and README.srio-pcie-boot-corenet
Added descriptions about boot from PCIE in the files README and doc/README.srio-pcie-boot-corenet, and changed the name of the doc/README.srio-boot-corenet to doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang --- README| 12 ++-- doc/README.srio-boot-corenet | 99 doc/README.srio-pcie-boot-corenet | 112 + 3 files changed, 118 insertions(+), 105 deletions(-) delete mode 100644 doc/README.srio-boot-corenet create mode 100644 doc/README.srio-pcie-boot-corenet diff --git a/README b/README index 6919392..fda7ddc 100644 --- a/README +++ b/README @@ -3045,12 +3045,12 @@ to save the current settings. These two #defines specify the address and size of the environment area within the remote memory space. The local device can get the environment from remote memory - space by SRIO or other links. + space by SRIO or PCIE links. BE CAREFUL! For some special cases, the local device can not use "saveenv" command. For example, the local device will get the -environment stored in a remote NOR flash by SRIO link, but it can -not erase, write this NOR flash by SRIO interface. +environment stored in a remote NOR flash by SRIO or PCIE link, +but it can not erase, write this NOR flash by SRIO or PCIE interface. - CONFIG_ENV_IS_IN_NAND: @@ -3491,9 +3491,9 @@ within that device. - CONFIG_SYS_QE_FMAN_FW_IN_REMOTE Specifies that QE/FMAN firmware is located in the remote (master) memory space. CONFIG_SYS_FMAN_FW_ADDR is a virtual address which - can be mapped from slave TLB->slave LAW->slave SRIO outbound window - ->master inbound window->master LAW->the ucode address in master's - NOR flash. + can be mapped from slave TLB->slave LAW->slave SRIO or PCIE outbound + window->master inbound window->master LAW->the ucode address in + master's memory space. Building the Software: == diff --git a/doc/README.srio-boot-corenet b/doc/README.srio-boot-corenet deleted file mode 100644 index 6a13e9c..000 --- a/doc/README.srio-boot-corenet +++ /dev/null @@ -1,99 +0,0 @@ --- -SRIO Boot on Corenet Platforms --- - -For some PowerPC processors with SRIO interface, boot location can be configured -to SRIO by RCW. The processor booting from SRIO can do without flash for u-boot -image, ucode and ENV. All the images can be fetched from another processor's -memory space by SRIO link connected between them. - -This document describes the processes based on an example implemented on P4080DS -platforms and a RCW example with boot from SRIO configuration. - -Environment of the SRIO boot: - a) Master and slave can be SOCs in one board or SOCs in separate boards. - b) They are connected with SRIO links, whether 1x or 4x, and directly or - through switch system. - c) Only Master has NorFlash for booting, and all the Master's and Slave's - U-Boot images, UCodes will be stored in this flash. - d) Slave has its own EEPROM for RCW and PBI. - e) Slave's RCW should configure the SerDes for SRIO boot port, set the boot - location to SRIO, and holdoff all the cores. - - ----- --- - | | | | | | - | | | | | | - | NorFlash|<->| Master |SRIO | Slave |<>[EEPROM] - | | | |<===>| | - | | | | | | - ----- --- - -The example based on P4080DS platform: - Two P4080DS platforms can be used to implement the boot from SRIO. Their SRIO - ports 1 will be connected directly and will be used for the boot from SRIO. - - 1. Slave's RCW example for boot from SRIO port 1 and all cores in holdoff. - : aa55 aa55 010e 0100 0c58 - 0010: 1818 1818 7440 4000 2000 - 0020: f440 0100 - 0030: 0083 - 0040: 0813 8040 063c 778f - - 2. Sequence in Step by Step. - a) Update RCW for slave with boot from SRIO port 1 configuration. - b) Program slave's U-Boot image, UCode, and ENV parameters into master's - NorFlash. - c) Set environment variable "bootmaster" to "SRIO1" and save environment - for master. - setenv bootmaster SRIO1 - saveenv - d) Restart up master and it will boot up normally from its NorF
[U-Boot] [PATCH 1/6] powerpc/corenet_ds: Update README.srio-boot-corenet
Update some descriptions due to the implementation changes: For master: Get rid of the SRIOBOOT_MASTER build target, and to support for serving as a SRIO boot master via environment variable. For slave: 1. When compile the slave image for boot from SRIO, no longer need to specify which SRIO port it will boot from. 2. All slave's cores should be in hold off. Signed-off-by: Liu Gang --- doc/README.srio-boot-corenet | 70 -- 1 files changed, 33 insertions(+), 37 deletions(-) diff --git a/doc/README.srio-boot-corenet b/doc/README.srio-boot-corenet index 56b094c..6a13e9c 100644 --- a/doc/README.srio-boot-corenet +++ b/doc/README.srio-boot-corenet @@ -18,7 +18,7 @@ Environment of the SRIO boot: U-Boot images, UCodes will be stored in this flash. d) Slave has its own EEPROM for RCW and PBI. e) Slave's RCW should configure the SerDes for SRIO boot port, set the boot - location to SRIO, and holdoff all the cores if needed. + location to SRIO, and holdoff all the cores. ----- --- | | | | | | @@ -30,63 +30,55 @@ Environment of the SRIO boot: The example based on P4080DS platform: Two P4080DS platforms can be used to implement the boot from SRIO. Their SRIO - ports 0 will be connected directly and will be used for the boot from SRIO. + ports 1 will be connected directly and will be used for the boot from SRIO. - 1. Slave's RCW example for boot from SRIO port 0 and core 0 not in holdoff. - : aa55 aa55 010e 0100 0c58 - 0010: 1818 1818 7440 4000 2000 - 0020: f400 0100 - 0030: 0083 - 0040: 0813 8040 698b 93fe - - 2. Slave's RCW example for boot from SRIO port 0 and all cores in holdoff. + 1. Slave's RCW example for boot from SRIO port 1 and all cores in holdoff. : aa55 aa55 010e 0100 0c58 0010: 1818 1818 7440 4000 2000 0020: f440 0100 0030: 0083 0040: 0813 8040 063c 778f - 3. Sequence in Step by Step. - a) Update RCW for slave with boot from SRIO port 0 configuration. + 2. Sequence in Step by Step. + a) Update RCW for slave with boot from SRIO port 1 configuration. b) Program slave's U-Boot image, UCode, and ENV parameters into master's NorFlash. - c) Start up master and it will boot up normally from its NorFlash. + c) Set environment variable "bootmaster" to "SRIO1" and save environment + for master. + setenv bootmaster SRIO1 + saveenv + d) Restart up master and it will boot up normally from its NorFlash. Then, it will finish necessary configurations for slave's boot from - SRIO port 0. - d) Master will set inbound SRIO windows covered slave's U-Boot image stored + SRIO port 1. + e) Master will set inbound SRIO windows covered slave's U-Boot image stored in master's NorFlash. - e) Master will set an inbound SRIO window covered slave's UCode stored in - master's NorFlash. - f) Master will set an inbound SRIO window covered slave's ENV stored in - master's NorFlash. - g) If need to release slave's core, master will set outbound SRIO windows - in order to configure slave's registers for the core's releasing. - h) If all cores of slave in holdoff, slave should be powered on before all - the above master's steps, and wait to be released by master. If not all - cores in holdoff, that means core 0 will start up normally, slave should - be powered on after all the above master's steps. In the startup phase - of the slave from SRIO, it will finish some necessary configurations. + f) Master will set an inbound SRIO window covered slave's UCode and ENV + stored in master's NorFlash. + g) Master will set outbound SRIO windows in order to configure slave's + registers for the core's releasing. + h) Since all cores of slave in holdoff, slave should be powered on before all + the above master's steps, and wait to be released by master.
[U-Boot] [PATCH 2/6] powerpc/corenet_ds: Get rid of the SRIOBOOT_MASTER build target
Get rid of the SRIOBOOT_MASTER build target, and to support for serving as
a SRIO boot master via environment variable. Set the environment variable
"bootmaster" to "SRIO1" or "SRIO2" using the following command:
setenv bootmaster SRIO1
saveenv
The "bootmaster" will enable the function of the SRIO boot master, and
this has the following advantages compared with SRIOBOOT_MASTER build
configuration:
1. Reduce a build configuration item in boards.cfg file.
No longer need to build a special image for master, just use a
normal target image and set the "bootmaster" variable.
2. No longer need to rebuild an image when change the SRIO port for
boot from SRIO, just set the corresponding value to "bootmaster"
based on the using SRIO port.
Signed-off-by: Liu Gang
---
arch/powerpc/cpu/mpc85xx/cpu_init.c | 17 +++--
arch/powerpc/cpu/mpc8xxx/srio.c | 137 ---
arch/powerpc/include/asm/fsl_srio.h |8 +--
boards.cfg |3 -
include/configs/corenet_ds.h| 32 ++--
5 files changed, 68 insertions(+), 129 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 2cd5db7..4c8b005 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -442,12 +442,17 @@ skip_l2:
#ifdef CONFIG_SYS_SRIO
srio_init();
-#ifdef CONFIG_SRIOBOOT_MASTER
- srio_boot_master();
-#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
- srio_boot_master_release_slave();
-#endif
-#endif
+ char *s = getenv("bootmaster");
+ if (s) {
+ if (!strcmp(s, "SRIO1")) {
+ srio_boot_master(1);
+ srio_boot_master_release_slave(1);
+ }
+ if (!strcmp(s, "SRIO2")) {
+ srio_boot_master(2);
+ srio_boot_master_release_slave(2);
+ }
+ }
#endif
#if defined(CONFIG_MP)
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index c7f3949..0ba7e2a 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -95,126 +95,91 @@ void srio_init(void)
}
}
-#ifdef CONFIG_SRIOBOOT_MASTER
-void srio_boot_master(void)
+void srio_boot_master(int port)
{
struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
/* set port accept-all */
- out_be32((void *)&srio->impl.port[CONFIG_SRIOBOOT_MASTER_PORT].ptaacr,
+ out_be32((void *)&srio->impl.port[port - 1].ptaacr,
SRIO_PORT_ACCEPT_ALL);
- debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n",
- CONFIG_SRIOBOOT_MASTER_PORT);
+ debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n", port);
/* configure inbound window for slave's u-boot image */
debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
- (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1,
- (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1,
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS,
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS1,
CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
- out_be32((void *)&srio->atmu
- .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwtar,
- CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 >> 12);
- out_be32((void *)&srio->atmu
- .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwbar,
- CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 >> 12);
- out_be32((void *)&srio->atmu
- .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwar,
+ out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwtar,
+ CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS >> 12);
+ out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwbar,
+ CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS1 >> 12);
+ out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwar,
SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
/* configure inbound window for slave's u-boot image */
debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
- (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2,
- (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2,
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS,
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS2,
CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
- out_be32((void *)&srio->atmu
- .port[CONFIG_SRIOBOOT_MASTER_
[U-Boot] [PATCH 3/6] powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macro
When compile the slave image for boot from SRIO, no longer need to
specify which SRIO port it will boot from. The code will get this
information from RCW and then finishes corresponding configurations.
This has the following advantages:
1. No longer need to rebuild an image when change the SRIO port for
boot from SRIO, just rewrite the new RCW with selected port,
then the code will get the port information by reading new RCW.
2. It will be easier to support other boot location options, for
example, boot from PCIE.
Signed-off-by: Liu Gang
---
arch/powerpc/include/asm/immap_85xx.h |1 +
board/freescale/common/p_corenet/law.c | 13 -
drivers/misc/fsl_law.c | 27 +++
include/configs/corenet_ds.h |3 ---
4 files changed, 28 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 632e3c1..48a00b9 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1758,6 +1758,7 @@ typedef struct ccsr_gur {
#define FSL_CORENET_RCWSR5_DDR_SYNC0x0080
#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
#define FSL_CORENET_RCWSR5_SRDS_EN 0x2000
+#define FSL_CORENET_RCWSR6_BOOT_LOC0x0f80
#define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c00 /* bits 162..165 */
#define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c /* bits 170..173 */
#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x0040
diff --git a/board/freescale/common/p_corenet/law.c
b/board/freescale/common/p_corenet/law.c
index c4566dd..09ef561 100644
--- a/board/freescale/common/p_corenet/law.c
+++ b/board/freescale/common/p_corenet/law.c
@@ -48,19 +48,6 @@ struct law_entry law_table[] = {
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
-#ifdef CONFIG_SRIOBOOT_SLAVE
-#if defined(CONFIG_SRIOBOOT_SLAVE_PORT0)
- SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
- LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
- SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
- LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
-#elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1)
- SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
- LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
- SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
- LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
-#endif
-#endif
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c
index a7d04b7..a71a0ce 100644
--- a/drivers/misc/fsl_law.c
+++ b/drivers/misc/fsl_law.c
@@ -275,5 +275,32 @@ void init_laws(void)
law_table[i].size, law_table[i].trgt_id);
}
+#ifdef CONFIG_SRIOBOOT_SLAVE
+ /* check RCW to get which port is used for boot */
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ u32 bootloc = in_be32(&gur->rcwsr[6]);
+ /* in SRIO boot we need to set specail LAWs for SRIO interfaces */
+ switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) {
+ case 0x8: /* boot from SRIO1 */
+ set_next_law(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+ LAW_SIZE_1M,
+ LAW_TRGT_IF_RIO_1);
+ set_next_law(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+ LAW_SIZE_1M,
+ LAW_TRGT_IF_RIO_1);
+ break;
+ case 0x9: /* boot from SRIO2 */
+ set_next_law(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+ LAW_SIZE_1M,
+ LAW_TRGT_IF_RIO_2);
+ set_next_law(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+ LAW_SIZE_1M,
+ LAW_TRGT_IF_RIO_2);
+ break;
+ default:
+ break;
+ }
+#endif
+
return ;
}
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 1f9fdfd..f2e48f5 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -413,9 +413,6 @@
* SRIOBOOT - SLAVE
*/
#ifdef CONFIG_SRIOBOOT_SLAVE
-/* slave port for srioboot */
-#define CONFIG_SRIOBOOT_SLAVE_PORT0
-/* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */
#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR 0xFFE0
#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS \
(0x3ull | CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR)
--
1.7.1
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[U-Boot] [PATCH 5/8 V2] I2C: S3C24X0: Add offset to calculate next i2c channel base address
As exynos has more than one i2c channels. This patch adds offset padding
for struct s3c24x0_i2c, in order to get the new base address of next i2c
channel.
Signed-off-by: Alim Akhtar
Signed-off-by: Rajeshwari Shinde
Acked-by: Simon Glass
---
drivers/i2c/s3c24x0_i2c.h |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/i2c/s3c24x0_i2c.h b/drivers/i2c/s3c24x0_i2c.h
index 2dd4b06..d357a0a 100644
--- a/drivers/i2c/s3c24x0_i2c.h
+++ b/drivers/i2c/s3c24x0_i2c.h
@@ -29,5 +29,8 @@ struct s3c24x0_i2c {
u32 iicadd;
u32 iicds;
u32 iiclc;
+#ifdef CONFIG_EXYNOS5
+ uchar res1[0xffec];
+#endif
};
#endif /* _S3C24X0_I2C_H */
--
1.7.4.4
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[U-Boot] [PATCH 4/8 V2] I2C: Move struct s3c24x0_i2c to a common place.
struct s3c24x0_i2c is being moved to common local header file so that
the same can be used by s3c series and exynos series SoCs.
Signed-off-by: Alim Akhtar
Signed-off-by: Doug Anderson
Signed-off-by: Rajeshwari Shinde
Acked-by: Simon Glass
---
arch/arm/include/asm/arch-s3c24x0/s3c24x0.h | 10
drivers/i2c/s3c24x0_i2c.h | 33 +++
2 files changed, 33 insertions(+), 10 deletions(-)
create mode 100644 drivers/i2c/s3c24x0_i2c.h
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
index ca978c9..0f75c31 100644
--- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
@@ -343,16 +343,6 @@ struct s3c24x0_watchdog {
u32 wtcnt;
};
-
-/* IIC (see manual chapter 20) */
-struct s3c24x0_i2c {
- u32 iiccon;
- u32 iicstat;
- u32 iicadd;
- u32 iicds;
-};
-
-
/* IIS (see manual chapter 21) */
struct s3c24x0_i2s {
#ifdef __BIG_ENDIAN
diff --git a/drivers/i2c/s3c24x0_i2c.h b/drivers/i2c/s3c24x0_i2c.h
new file mode 100644
index 000..2dd4b06
--- /dev/null
+++ b/drivers/i2c/s3c24x0_i2c.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _S3C24X0_I2C_H
+#define _S3C24X0_I2C_H
+
+struct s3c24x0_i2c {
+ u32 iiccon;
+ u32 iicstat;
+ u32 iicadd;
+ u32 iicds;
+ u32 iiclc;
+};
+#endif /* _S3C24X0_I2C_H */
--
1.7.4.4
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[U-Boot] [PATCH 8/8 V2] CONFIG: SMDK5250: I2C: Enable I2C
This enables I2C support on smdk5250. Signed-off-by: Alim Akhtar Signed-off-by: Doug Anderson Signed-off-by: Rajeshwari Shinde Acked-by: Simon Glass --- include/configs/smdk5250.h |8 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 9659f9e..1fca652 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -190,6 +190,14 @@ #define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_LOAD_ADDR - 0x100) +/* I2C */ +#define CONFIG_HARD_I2C +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_SPEED 10 /* 100 Kbps */ +#define CONFIG_DRIVER_S3C24X0_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_MAX_I2C_NUM 8 + /* Ethernet Controllor Driver */ #ifdef CONFIG_CMD_NET #define CONFIG_SMC911X -- 1.7.4.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 6/8 V2] I2C: Modify the I2C driver for EXYNOS5
This patch modifies the S3C I2C driver to suppport EXYNOS5.
The cahnges made to driver are as follows:
- I2C base address is passed as a parameter to many
functions to avoid multiple #ifdef
- I2C init for Exynos5 is made as different function.
- Channel initialisation is moved to a commom funation
as it is required by both the i2c_init.
- Separate functions written to get I2C base address,
peripheral id for pinmux support.
- Hardcoding for I2CCON_ACKGEN removed.
- Replaced printf with debug.
- Checkpatch issues resolved.
Signed-off-by: Alim Akhtar
Signed-off-by: Doug Anderson
Signed-off-by: Rajeshwari Shinde
Acked-by: Simon Glass
---
Changes in V2:
- Removed #define for I2C cahnnels from hearder file except for I2C0.
- Incorporated review comments from Simon Glass.
drivers/i2c/s3c24x0_i2c.c | 254 -
drivers/i2c/s3c24x0_i2c.h |3 +
2 files changed, 184 insertions(+), 73 deletions(-)
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index ba6f39b..a71f147 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -27,10 +27,17 @@
*/
#include
+#ifdef CONFIG_EXYNOS5
+#include
+#include
+#include
+#include
+#else
#include
-
+#endif
#include
#include
+#include "s3c24x0_i2c.h"
#ifdef CONFIG_HARD_I2C
@@ -45,6 +52,7 @@
#define I2CSTAT_BSY0x20/* Busy bit */
#define I2CSTAT_NACK 0x01/* Nack bit */
+#define I2CCON_ACKGEN 0x80/* Acknowledge generation */
#define I2CCON_IRPND 0x10/* Interrupt pending bit */
#define I2C_MODE_MT0xC0/* Master Transmit Mode */
#define I2C_MODE_MR0x80/* Master Receive Mode */
@@ -53,6 +61,44 @@
#define I2C_TIMEOUT 1 /* 1 second */
+#ifdef CONFIG_EXYNOS5
+static unsigned int g_current_bus; /* Stores Current I2C Bus */
+
+/* We should not rely on any particular ordering of these IDs */
+static enum periph_id periph_for_dev[] = {
+ PERIPH_ID_I2C0,
+ PERIPH_ID_I2C1,
+ PERIPH_ID_I2C2,
+ PERIPH_ID_I2C3,
+ PERIPH_ID_I2C4,
+ PERIPH_ID_I2C5,
+ PERIPH_ID_I2C6,
+ PERIPH_ID_I2C7,
+};
+
+static enum periph_id i2c_get_periph_id(unsigned dev_index)
+{
+ if (dev_index < ARRAY_SIZE(periph_for_dev))
+ return periph_for_dev[dev_index];
+
+ debug("%s: invalid bus %d", __func__, dev_index);
+
+ return PERIPH_ID_NONE;
+}
+
+static struct s3c24x0_i2c *get_base_i2c(int bus_idx)
+{
+ struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)samsung_get_base_i2c();
+
+ return &i2c[bus_idx];
+}
+
+static inline struct exynos5_gpio_part1 *exynos_get_base_gpio1(void)
+{
+ return (struct exynos5_gpio_part1 *)(EXYNOS5_GPIO_PART1_BASE);
+}
+
+#else
static int GetI2CSDA(void)
{
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
@@ -77,16 +123,17 @@ static void SetI2CSCL(int x)
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
#ifdef CONFIG_S3C2410
- writel((readl(&gpio->gpedat) & ~0x4000) | (x & 1) << 14, &gpio->gpedat);
+ writel((readl(&gpio->gpedat) & ~0x4000) |
+ (x & 1) << 14, &gpio->gpedat);
#endif
#ifdef CONFIG_S3C2400
writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat);
#endif
}
+#endif
-static int WaitForXfer(void)
+static int WaitForXfer(struct s3c24x0_i2c *i2c)
{
- struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
int i;
i = I2C_TIMEOUT * 1;
@@ -98,25 +145,84 @@ static int WaitForXfer(void)
return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
}
-static int IsACK(void)
+static int IsACK(struct s3c24x0_i2c *i2c)
{
- struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
-
return !(readl(&i2c->iicstat) & I2CSTAT_NACK);
}
-static void ReadWriteByte(void)
+static void ReadWriteByte(struct s3c24x0_i2c *i2c)
{
- struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
-
writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
}
+static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
+{
+ ulong freq, pres = 16, div;
+#ifdef CONFIG_EXYNOS5
+ freq = get_i2c_clk();
+#else
+ freq = get_PCLK();
+#endif
+ /* calculate prescaler and divisor values */
+ if ((freq / pres / (16 + 1)) > speed)
+ /* set prescaler to 512 */
+ pres = 512;
+
+ div = 0;
+ while ((freq / pres / (div + 1)) > speed)
+ div++;
+
+ /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
+ writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
+
+ /* init to SLAVE REVEIVE and set slaveaddr */
+ writel(0, &i2c->iicstat);
+ writel(slaveadd, &i2c->iicadd);
+ /* program Master Transmit (and implicit STOP) */
+ writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicst
[U-Boot] [PATCH 7/8 V2] I2C: Add support for Multi channel
This adds multiple i2c channel support for I2C.
Signed-off-by: Alim Akhtar
Signed-off-by: Rajeshwari Shinde
Acked-by: Simon Glass
---
drivers/i2c/s3c24x0_i2c.c | 27 +++
1 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index a71f147..7521cb8 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -191,6 +191,33 @@ static void i2c_bus_init(struct s3c24x0_i2c *i2c, unsigned
int bus)
i2c_ch_init(i2c, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
}
+/*
+ * MULTI BUS I2C support
+ */
+
+#ifdef CONFIG_I2C_MULTI_BUS
+int i2c_set_bus_num(unsigned int bus)
+{
+ struct s3c24x0_i2c *i2c;
+
+ if ((bus < 0) || (bus >= CONFIG_MAX_I2C_NUM)) {
+ debug("Bad bus: %d\n", bus);
+ return -1;
+ }
+
+ g_current_bus = bus;
+ i2c = get_base_i2c(g_current_bus);
+ i2c_bus_init(i2c, g_current_bus);
+
+ return 0;
+}
+
+unsigned int i2c_get_bus_num(void)
+{
+ return g_current_bus;
+}
+#endif
+
#ifdef CONFIG_EXYNOS5
void i2c_init(int speed, int slaveadd)
{
--
1.7.4.4
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[U-Boot] [PATCH 3/8 V2] EXYNOS: PINMUX: Add pinmux support for I2C
This patch adds pinmux code for I2C.
Signed-off-by: Rajeshwari Shinde
Acked-by: Simon Glass
---
Changes in V2:
- Aligned the pinmux functionality as per the latest comments.
This patch depends on the following patch:
"[U-Boot] [PATCH 1/2 V6] EXYNOS5: PINMUX: Added default pinumx settings"
arch/arm/cpu/armv7/exynos/pinmux.c| 52 +
arch/arm/include/asm/arch-exynos/periph.h |8
2 files changed, 60 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
b/arch/arm/cpu/armv7/exynos/pinmux.c
index 597e487..d3314a1 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -182,6 +182,48 @@ static void exynos5_sromc_config(int flags)
}
}
+static void exynos5_i2c_config(int peripheral, int flags)
+{
+
+ struct exynos5_gpio_part1 *gpio1 =
+ (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+
+ switch (peripheral) {
+ case PERIPH_ID_I2C0:
+ s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C1:
+ s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C2:
+ s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C3:
+ s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C4:
+ s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C5:
+ s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C6:
+ s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
+ s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
+ break;
+ case PERIPH_ID_I2C7:
+ s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
+ break;
+ }
+}
+
static int exynos5_pinmux_config(int peripheral, int flags)
{
switch (peripheral) {
@@ -200,6 +242,16 @@ static int exynos5_pinmux_config(int peripheral, int flags)
case PERIPH_ID_SROMC:
exynos5_sromc_config(flags);
break;
+ case PERIPH_ID_I2C0:
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ case PERIPH_ID_I2C3:
+ case PERIPH_ID_I2C4:
+ case PERIPH_ID_I2C5:
+ case PERIPH_ID_I2C6:
+ case PERIPH_ID_I2C7:
+ exynos5_i2c_config(peripheral, flags);
+ break;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return -1;
diff --git a/arch/arm/include/asm/arch-exynos/periph.h
b/arch/arm/include/asm/arch-exynos/periph.h
index 5db25aa..b861d7d 100644
--- a/arch/arm/include/asm/arch-exynos/periph.h
+++ b/arch/arm/include/asm/arch-exynos/periph.h
@@ -30,6 +30,14 @@
*
*/
enum periph_id {
+ PERIPH_ID_I2C0,
+ PERIPH_ID_I2C1,
+ PERIPH_ID_I2C2,
+ PERIPH_ID_I2C3,
+ PERIPH_ID_I2C4,
+ PERIPH_ID_I2C5,
+ PERIPH_ID_I2C6,
+ PERIPH_ID_I2C7,
PERIPH_ID_SDMMC0,
PERIPH_ID_SDMMC1,
PERIPH_ID_SDMMC2,
--
1.7.4.4
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[U-Boot] [PATCH 2/8 V2] EXYNOS: Add I2C base address.
This patch adds the base address for I2C. Signed-off-by: Alim Akhtar Signed-off-by: Rajeshwari Shinde Acked-by: Simon Glass --- arch/arm/include/asm/arch-exynos/cpu.h |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index b1e22f2..093bcc1 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -48,6 +48,7 @@ #define EXYNOS4_SROMC_BASE 0x1257 #define EXYNOS4_USBPHY_BASE0x125B #define EXYNOS4_UART_BASE 0x1380 +#define EXYNOS4_I2C_BASE 0x1386 #define EXYNOS4_ADC_BASE 0x1391 #define EXYNOS4_PWMTIMER_BASE 0x139D #define EXYNOS4_MODEM_BASE 0x13A0 @@ -74,6 +75,7 @@ #define EXYNOS5_USBOTG_BASE0x1248 #define EXYNOS5_USBPHY_BASE0x1248 #define EXYNOS5_UART_BASE 0x12C0 +#define EXYNOS5_I2C_BASE 0x12C6 #define EXYNOS5_PWMTIMER_BASE 0x12DD #define EXYNOS5_GPIO_PART2_BASE0x1340 #define EXYNOS5_FIMD_BASE 0x1440 @@ -146,6 +148,7 @@ SAMSUNG_BASE(adc, ADC_BASE) SAMSUNG_BASE(clock, CLOCK_BASE) SAMSUNG_BASE(sysreg, SYSREG_BASE) SAMSUNG_BASE(fimd, FIMD_BASE) +SAMSUNG_BASE(i2c, I2C_BASE) SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE) SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE) SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE) -- 1.7.4.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/8 V2] EXYNOS: CLK: Add i2c clock
This adds i2c clock information for EXYNOS5.
Signed-off-by: Alim Akhtar
Signed-off-by: Doug Anderson
Signed-off-by: Rajeshwari Shinde
Acked-by: Simon Glass
---
changes in V2:
- Incorporated comments from Simon Glass which are removed extra
braces around (readl(&clk->div_top1)) >> 24 and gave a tab space for
return statement.
arch/arm/cpu/armv7/exynos/clock.c | 33
arch/arm/include/asm/arch-exynos/clk.h |1 +
2 files changed, 34 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 330bd75..a80928b 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -578,6 +578,29 @@ void exynos4_set_mipi_clk(void)
writel(cfg, &clk->div_lcd0);
}
+/*
+ * I2C
+ *
+ * exynos5: obtaining the I2C clock
+ */
+static unsigned long exynos5_get_i2c_clk(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned long aclk_66, aclk_66_pre, sclk;
+ unsigned int ratio;
+
+ sclk = get_pll_clk(MPLL);
+
+ ratio = (readl(&clk->div_top1)) >> 24;
+ ratio &= (0x7);
+ aclk_66_pre = sclk/(ratio+1);
+ ratio = readl(&clk->div_top0);
+ ratio &= (0x7);
+ aclk_66 = aclk_66_pre/(ratio+1);
+ return aclk_66;
+}
+
unsigned long get_pll_clk(int pllreg)
{
if (cpu_is_exynos5())
@@ -594,6 +617,16 @@ unsigned long get_arm_clk(void)
return exynos4_get_arm_clk();
}
+unsigned long get_i2c_clk(void)
+{
+ if (cpu_is_exynos5()) {
+ return exynos5_get_i2c_clk();
+ } else {
+ debug("I2C clock is not set for this CPU\n");
+ return 0;
+ }
+}
+
unsigned long get_pwm_clk(void)
{
if (cpu_is_exynos5())
diff --git a/arch/arm/include/asm/arch-exynos/clk.h
b/arch/arm/include/asm/arch-exynos/clk.h
index 637fb4b..72dc655 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -30,6 +30,7 @@
unsigned long get_pll_clk(int pllreg);
unsigned long get_arm_clk(void);
+unsigned long get_i2c_clk(void);
unsigned long get_pwm_clk(void);
unsigned long get_uart_clk(int dev_index);
void set_mmc_clk(int dev_index, unsigned int div);
--
1.7.4.4
___
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U-Boot@lists.denx.de
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[U-Boot] [PATCH 0/8 V2] EXYNOS5: Enable I2C support
This patch set enables I2C support for EXYNOS5. This patchset modifies the s3c24x0 I2C driver to use same for EXYNOS5. Multichannel support has been added to the s3c24x0 I2C driver. s3c24x0_i2c struct has been moved to a common place as it can used by different SOC's. Changes in V2: - Incorporated review comments from Simon Glass. - Aligned the pinmux functionality as per latest comments. This patchset depends on the following patch: "[U-Boot] [PATCH 1/2 V6] EXYNOS5: PINMUX: Added default pinumx settings" Rajeshwari Shinde (8): EXYNOS: CLK: Add i2c clock EXYNOS: Add I2C base address. EXYNOS: PINMUX: Add pinmux support for I2C I2C: Move struct s3c24x0_i2c to a common place. I2C: S3C24X0: Add offset to calculate next i2c channel base address I2C: Modify the I2C driver for EXYNOS5 I2C: Add support for Multi channel CONFIG: SMDK5250: I2C: Enable I2C arch/arm/cpu/armv7/exynos/clock.c | 33 +++ arch/arm/cpu/armv7/exynos/pinmux.c | 52 + arch/arm/include/asm/arch-exynos/clk.h |1 + arch/arm/include/asm/arch-exynos/cpu.h |3 + arch/arm/include/asm/arch-exynos/periph.h |8 + arch/arm/include/asm/arch-s3c24x0/s3c24x0.h | 10 - drivers/i2c/s3c24x0_i2c.c | 281 --- drivers/i2c/s3c24x0_i2c.h | 39 include/configs/smdk5250.h |8 + 9 files changed, 352 insertions(+), 83 deletions(-) create mode 100644 drivers/i2c/s3c24x0_i2c.h -- 1.7.4.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2 V6] EXYNOS5: PINMUX: Added default pinumx settings
This patch performs the pinmux configuration in a common file.
As of now only EXYNOS5 pinmux for SDMMC, UART and Ethernet is
supported.
Signed-off-by: Abhilash Kesavan
Signed-off-by: Che-Liang Chiou
Signed-off-by: Rajeshwari Shinde
Acked-by: Chander Kashyap
Acked-by: Simon Glass
---
Changes in V2:
- Adding pinmux.c to Makefile moved to this patch.
- exynos5_pinmux_config made static
Changes in V3:
- Separate functions made for each peripheral
- enum periph_id moved to a separate periph.h
Changes in V4:
- removed variable declarations from exynos5_pinmux_config
Changes in V5:
- added a return statement for function exynos5_mmc_config
and added a check for same
Changes in V6:
- Added a blank line
arch/arm/cpu/armv7/exynos/Makefile|2 +-
arch/arm/cpu/armv7/exynos/pinmux.c| 220 +
arch/arm/include/asm/arch-exynos/periph.h | 47 ++
arch/arm/include/asm/arch-exynos/pinmux.h | 58
4 files changed, 326 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/cpu/armv7/exynos/pinmux.c
create mode 100644 arch/arm/include/asm/arch-exynos/periph.h
create mode 100644 arch/arm/include/asm/arch-exynos/pinmux.h
diff --git a/arch/arm/cpu/armv7/exynos/Makefile
b/arch/arm/cpu/armv7/exynos/Makefile
index 90ec2bd..9119961 100644
--- a/arch/arm/cpu/armv7/exynos/Makefile
+++ b/arch/arm/cpu/armv7/exynos/Makefile
@@ -22,7 +22,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).o
-COBJS += clock.o power.o soc.o system.o
+COBJS += clock.o power.o soc.o system.o pinmux.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
b/arch/arm/cpu/armv7/exynos/pinmux.c
new file mode 100644
index 000..d2b7d2c
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -0,0 +1,220 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics.
+ * Abhilash Kesavan
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+
+static void exynos5_uart_config(int peripheral)
+{
+ struct exynos5_gpio_part1 *gpio1 =
+ (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+ struct s5p_gpio_bank *bank;
+ int i, start, count;
+
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ bank = &gpio1->a0;
+ start = 0;
+ count = 4;
+ break;
+ case PERIPH_ID_UART1:
+ bank = &gpio1->a0;
+ start = 4;
+ count = 4;
+ break;
+ case PERIPH_ID_UART2:
+ bank = &gpio1->a1;
+ start = 0;
+ count = 4;
+ break;
+ case PERIPH_ID_UART3:
+ bank = &gpio1->a1;
+ start = 4;
+ count = 2;
+ break;
+ }
+ for (i = start; i < start + count; i++) {
+ s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+ s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ }
+}
+
+static int exynos5_mmc_config(int peripheral, int flags)
+{
+ struct exynos5_gpio_part1 *gpio1 =
+ (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+ struct s5p_gpio_bank *bank, *bank_ext;
+ int i;
+
+ switch (peripheral) {
+ case PERIPH_ID_SDMMC0:
+ bank = &gpio1->c0;
+ bank_ext = &gpio1->c1;
+ break;
+ case PERIPH_ID_SDMMC1:
+ bank = &gpio1->c1;
+ bank_ext = NULL;
+ break;
+ case PERIPH_ID_SDMMC2:
+ bank = &gpio1->c2;
+ bank_ext = &gpio1->c3;
+ break;
+ case PERIPH_ID_SDMMC3:
+ bank = &gpio1->c3;
+ bank_ext = NULL;
+ break;
+ }
+ if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
+ debug("SDMMC device %d does not support 8bit mode",
+ peripheral);
+ return -1;
+ }
+ if (flags & PINMUX_FLAG_8BIT_MODE) {
+ for (i = 3; i <= 6; i++) {
+ s5p_gpi
[U-Boot] [PATCH 2/2 V6] EXYNOS: SMDK5250: Enable the pinmux setup
Use the pinmux configuration function for SMDK5250.
Signed-off-by: Abhilash Kesavan
Signed-off-by: Rajeshwari Shinde
Acked-by: Chander Kashyap
Acked-by: Simon Glass
---
Changes in V2:
- Removed exynos5_gpio_part1 *gpio1 global variable as initialised in
pinmux.c.
Changes in V3:
- Added a error return for smc9115_pre_init and board_uart_init.
Changes in V6:
- none
board/samsung/smdk5250/smdk5250.c | 176 -
1 files changed, 38 insertions(+), 138 deletions(-)
diff --git a/board/samsung/smdk5250/smdk5250.c
b/board/samsung/smdk5250/smdk5250.c
index 32786e2..3b078da 100644
--- a/board/samsung/smdk5250/smdk5250.c
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -26,81 +26,16 @@
#include
#include
#include
+#include
#include
DECLARE_GLOBAL_DATA_PTR;
-struct exynos5_gpio_part1 *gpio1;
#ifdef CONFIG_SMC911X
-static void smc9115_pre_init(void)
+static int smc9115_pre_init(void)
{
u32 smc_bw_conf, smc_bc_conf;
- int i;
-
- /*
-* SROM:CS1 and EBI
-*
-* GPY0[0] SROM_CSn[0]
-* GPY0[1] SROM_CSn[1](2)
-* GPY0[2] SROM_CSn[2]
-* GPY0[3] SROM_CSn[3]
-* GPY0[4] EBI_OEn(2)
-* GPY0[5] EBI_EEn(2)
-*
-* GPY1[0] EBI_BEn[0](2)
-* GPY1[1] EBI_BEn[1](2)
-* GPY1[2] SROM_WAIT(2)
-* GPY1[3] EBI_DATA_RDn(2)
-*/
- s5p_gpio_cfg_pin(&gpio1->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
- s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2));
- s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2));
-
- for (i = 0; i < 4; i++)
- s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2));
-
- /*
-* EBI: 8 Addrss Lines
-*
-* GPY3[0] EBI_ADDR[0](2)
-* GPY3[1] EBI_ADDR[1](2)
-* GPY3[2] EBI_ADDR[2](2)
-* GPY3[3] EBI_ADDR[3](2)
-* GPY3[4] EBI_ADDR[4](2)
-* GPY3[5] EBI_ADDR[5](2)
-* GPY3[6] EBI_ADDR[6](2)
-* GPY3[7] EBI_ADDR[7](2)
-*
-* EBI: 16 Data Lines
-*
-* GPY5[0] EBI_DATA[0](2)
-* GPY5[1] EBI_DATA[1](2)
-* GPY5[2] EBI_DATA[2](2)
-* GPY5[3] EBI_DATA[3](2)
-* GPY5[4] EBI_DATA[4](2)
-* GPY5[5] EBI_DATA[5](2)
-* GPY5[6] EBI_DATA[6](2)
-* GPY5[7] EBI_DATA[7](2)
-*
-* GPY6[0] EBI_DATA[8](2)
-* GPY6[1] EBI_DATA[9](2)
-* GPY6[2] EBI_DATA[10](2)
-* GPY6[3] EBI_DATA[11](2)
-* GPY6[4] EBI_DATA[12](2)
-* GPY6[5] EBI_DATA[13](2)
-* GPY6[6] EBI_DATA[14](2)
-* GPY6[7] EBI_DATA[15](2)
-*/
- for (i = 0; i < 8; i++) {
- s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2));
- s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP);
-
- s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2));
- s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP);
-
- s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2));
- s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP);
- }
+ int err;
/* Ethernet needs data bus width of 16 bits */
smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK)
@@ -112,14 +47,20 @@ static void smc9115_pre_init(void)
| SROMC_BC_PMC(0x01);
/* Select and configure the SROMC bank */
+ err = exynos_pinmux_config(PERIPH_ID_SROMC,
+ CONFIG_ENV_SROM_BANK | PINMUX_FLAG_16BIT);
+ if (err) {
+ debug("SROMC not configured\n");
+ return err;
+ }
+
s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
+ return 0;
}
#endif
int board_init(void)
{
- gpio1 = (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
-
gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
return 0;
}
@@ -168,7 +109,8 @@ void dram_init_banksize(void)
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_SMC911X
- smc9115_pre_init();
+ if (smc9115_pre_init())
+ return -1;
return smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
return 0;
@@ -186,31 +128,12 @@ int checkboard(void)
#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
- int i, err;
-
- /*
-* MMC2 SD card GPIO:
-*
-* GPC2[0] SD_2_CLK(2)
-* GPC2[1] SD_2_CMD(2)
-* GPC2[2] SD_2_CDn
-* GPC2[3:6]SD_2_DATA[0:3](2)
-*/
- for (i = 0; i < 7; i++) {
- /* GPC2[0:6] special function 2 */
- s5p_gpio_cfg_pin(&gpio1->c2, i, GPIO_FUNC(0x2));
-
- /* GPK2[0:6] drv 4x */
- s5p_gpio_set_drv(&gpio1->c2, i, GPIO_DRV_4X);
+ int err;
- /* GPK2[0:1] pull disable */
-
[U-Boot] [PATCH 2/2] ARM: bcm2835: add Raspberry Pi model B board
The Raspberry Pi model B uses the BCM2835 SoC, has 256MB of RAM, contains
an SMSC 9512 USB LAN/Hub chip, and various IO connectors. For more details,
see http://www.raspberrypi.org/.
Signed-off-by: Stephen Warren
---
MAINTAINERS |4 ++
board/raspberrypi/rpi_b/Makefile | 34
board/raspberrypi/rpi_b/rpi_b.c | 32 +++
boards.cfg |1 +
include/configs/rpi_b.h | 80 ++
5 files changed, 151 insertions(+)
create mode 100644 board/raspberrypi/rpi_b/Makefile
create mode 100644 board/raspberrypi/rpi_b/rpi_b.c
create mode 100644 include/configs/rpi_b.h
diff --git a/MAINTAINERS b/MAINTAINERS
index f796872..f12d862 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -913,6 +913,10 @@ Stephen Warren
ventana Tegra2 (ARM7 & A9 Dual Core)
paz00 Tegra2 (ARM7 & A9 Dual Core)
+Stephen Warren
+
+ rpi_b BCM2835 (ARM1176)
+
Thomas Weber
devkit8000 ARM ARMV7 (OMAP3530 SoC)
diff --git a/board/raspberrypi/rpi_b/Makefile b/board/raspberrypi/rpi_b/Makefile
new file mode 100644
index 000..9d0c377
--- /dev/null
+++ b/board/raspberrypi/rpi_b/Makefile
@@ -0,0 +1,34 @@
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License
+# version 2 as published by the Free Software Foundation.
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB):$(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/raspberrypi/rpi_b/rpi_b.c b/board/raspberrypi/rpi_b/rpi_b.c
new file mode 100644
index 000..f39440f
--- /dev/null
+++ b/board/raspberrypi/rpi_b/rpi_b.c
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2012 Stephen Warren
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = SZ_256M;
+
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index 0dee43f..b82534e 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -48,6 +48,7 @@ mx35pdk arm arm1136 -
freesca
apollon arm arm1136 apollon
- omap24xx
omap2420h4 arm arm1136 - ti
omap24xx
tnetv107x_evmarm arm1176 tnetv107xevmti
tnetv107x
+rpi_barm arm1176 rpi_b
raspberrypibcm2835
integratorap_cm720t arm arm720t integrator
armltd - integratorap:CM720T
integratorap_cm920t arm arm920t integrator
armltd - integratorap:CM920T
integratorcp_cm920t arm arm920t integrator
armltd - integratorcp:CM920T
diff --git a/include/configs/rpi_b.h b/include/configs/rpi_b.h
new file mode 100644
index 000..f547027
--- /dev/null
+++ b/include/configs/rpi_b.h
@@ -0,0 +1,80 @@
+/*
+ * (C) Copyright 2012 Stephen Warren
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include
+
+/* Architecture,
[U-Boot] [PATCH 1/2] ARM: add basic support for the Broadcom BCM2835 SoC
This SoC is used in the Raspberry Pi, for example. Initial support is enough to boot to a serial console, and execute a minimal set of U-Boot commands. No drivers are implemented. For more details, see http://www.broadcom.com/products/BCM2835 or http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf. Signed-off-by: Stephen Warren --- arch/arm/cpu/arm1176/bcm2835/Makefile| 37 + arch/arm/cpu/arm1176/bcm2835/config.mk | 19 + arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S | 19 + arch/arm/cpu/arm1176/bcm2835/reset.c | 27 + arch/arm/cpu/arm1176/bcm2835/timer.c | 55 ++ arch/arm/include/asm/arch-bcm2835/timer.h| 37 + 6 files changed, 194 insertions(+) create mode 100644 arch/arm/cpu/arm1176/bcm2835/Makefile create mode 100644 arch/arm/cpu/arm1176/bcm2835/config.mk create mode 100644 arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S create mode 100644 arch/arm/cpu/arm1176/bcm2835/reset.c create mode 100644 arch/arm/cpu/arm1176/bcm2835/timer.c create mode 100644 arch/arm/include/asm/arch-bcm2835/timer.h diff --git a/arch/arm/cpu/arm1176/bcm2835/Makefile b/arch/arm/cpu/arm1176/bcm2835/Makefile new file mode 100644 index 000..4ea6d6b --- /dev/null +++ b/arch/arm/cpu/arm1176/bcm2835/Makefile @@ -0,0 +1,37 @@ +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License +# version 2 as published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(SOC).o + +SOBJS := lowlevel_init.o +COBJS := reset.o timer.o + +SRCS := $(SOBJS:.o=.c) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB):$(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/arch/arm/cpu/arm1176/bcm2835/config.mk b/arch/arm/cpu/arm1176/bcm2835/config.mk new file mode 100644 index 000..b87ce24 --- /dev/null +++ b/arch/arm/cpu/arm1176/bcm2835/config.mk @@ -0,0 +1,19 @@ +# +# (C) Copyright 2012 Stephen Warren +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License +# version 2 as published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# Don't attempt to override the target CPU/ABI options; +# the Raspberry Pi toolchain does the right thing by default. +PLATFORM_RELFLAGS := $(filter-out -msoft-float,$(PLATFORM_RELFLAGS)) +PLATFORM_CPPFLAGS := $(filter-out -march=armv5t,$(PLATFORM_CPPFLAGS)) diff --git a/arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S b/arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S new file mode 100644 index 000..c7b0843 --- /dev/null +++ b/arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S @@ -0,0 +1,19 @@ +/* + * (C) Copyright 2012 Stephen Warren + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +.globl lowlevel_init +lowlevel_init: + mov pc, lr diff --git a/arch/arm/cpu/arm1176/bcm2835/reset.c b/arch/arm/cpu/arm1176/bcm2835/reset.c new file mode 100644 index 000..69c9577 --- /dev/null +++ b/arch/arm/cpu/arm1176/bcm2835/reset.c @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2012 Stephen Warren + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without
Re: [U-Boot] [PATCH 1/5] ARM: cache: Move the cp15 CR register read before flushing the cache.
Hi Marek Vasut, >> Ping.. > > +1 Thanks.. Thanks, Sricharan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2 V5] EXYNOS: SMDK5250: Enable the pinmux setup
On Mon, Jun 4, 2012 at 10:52 PM, Rajeshwari Shinde wrote:
> Use the pinmux configuration function for SMDK5250.
>
> Signed-off-by: Abhilash Kesavan
> Signed-off-by: Rajeshwari Shinde
> Acked-by: Chander Kashyap
> Acked-by: Simon Glass
>
Looks good
Acked-by: Simon Glass
> ---
> Changes in V2:
>- Removed exynos5_gpio_part1 *gpio1 global variable as initialised
> in
> pinmux.c.
> Changes in V3:
>- Added a error return for smc9115_pre_init and board_uart_init.
> board/samsung/smdk5250/smdk5250.c | 176
> -
> 1 files changed, 38 insertions(+), 138 deletions(-)
>
> diff --git a/board/samsung/smdk5250/smdk5250.c
> b/board/samsung/smdk5250/smdk5250.c
> index 32786e2..3b078da 100644
> --- a/board/samsung/smdk5250/smdk5250.c
> +++ b/board/samsung/smdk5250/smdk5250.c
> @@ -26,81 +26,16 @@
> #include
> #include
> #include
> +#include
> #include
>
> DECLARE_GLOBAL_DATA_PTR;
> -struct exynos5_gpio_part1 *gpio1;
>
> #ifdef CONFIG_SMC911X
> -static void smc9115_pre_init(void)
> +static int smc9115_pre_init(void)
> {
>u32 smc_bw_conf, smc_bc_conf;
> - int i;
> -
> - /*
> -* SROM:CS1 and EBI
> -*
> -* GPY0[0] SROM_CSn[0]
> -* GPY0[1] SROM_CSn[1](2)
> -* GPY0[2] SROM_CSn[2]
> -* GPY0[3] SROM_CSn[3]
> -* GPY0[4] EBI_OEn(2)
> -* GPY0[5] EBI_EEn(2)
> -*
> -* GPY1[0] EBI_BEn[0](2)
> -* GPY1[1] EBI_BEn[1](2)
> -* GPY1[2] SROM_WAIT(2)
> -* GPY1[3] EBI_DATA_RDn(2)
> -*/
> - s5p_gpio_cfg_pin(&gpio1->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
> - s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2));
> - s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2));
> -
> - for (i = 0; i < 4; i++)
> - s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2));
> -
> - /*
> -* EBI: 8 Addrss Lines
> -*
> -* GPY3[0] EBI_ADDR[0](2)
> -* GPY3[1] EBI_ADDR[1](2)
> -* GPY3[2] EBI_ADDR[2](2)
> -* GPY3[3] EBI_ADDR[3](2)
> -* GPY3[4] EBI_ADDR[4](2)
> -* GPY3[5] EBI_ADDR[5](2)
> -* GPY3[6] EBI_ADDR[6](2)
> -* GPY3[7] EBI_ADDR[7](2)
> -*
> -* EBI: 16 Data Lines
> -*
> -* GPY5[0] EBI_DATA[0](2)
> -* GPY5[1] EBI_DATA[1](2)
> -* GPY5[2] EBI_DATA[2](2)
> -* GPY5[3] EBI_DATA[3](2)
> -* GPY5[4] EBI_DATA[4](2)
> -* GPY5[5] EBI_DATA[5](2)
> -* GPY5[6] EBI_DATA[6](2)
> -* GPY5[7] EBI_DATA[7](2)
> -*
> -* GPY6[0] EBI_DATA[8](2)
> -* GPY6[1] EBI_DATA[9](2)
> -* GPY6[2] EBI_DATA[10](2)
> -* GPY6[3] EBI_DATA[11](2)
> -* GPY6[4] EBI_DATA[12](2)
> -* GPY6[5] EBI_DATA[13](2)
> -* GPY6[6] EBI_DATA[14](2)
> -* GPY6[7] EBI_DATA[15](2)
> -*/
> - for (i = 0; i < 8; i++) {
> - s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2));
> - s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP);
> -
> - s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2));
> - s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP);
> -
> - s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2));
> - s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP);
> - }
> + int err;
>
>/* Ethernet needs data bus width of 16 bits */
>smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK)
> @@ -112,14 +47,20 @@ static void smc9115_pre_init(void)
>| SROMC_BC_PMC(0x01);
>
>/* Select and configure the SROMC bank */
> + err = exynos_pinmux_config(PERIPH_ID_SROMC,
> + CONFIG_ENV_SROM_BANK | PINMUX_FLAG_16BIT);
> + if (err) {
> + debug("SROMC not configured\n");
> + return err;
> + }
> +
>s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
> + return 0;
> }
> #endif
>
> int board_init(void)
> {
> - gpio1 = (struct exynos5_gpio_part1 *)
> samsung_get_base_gpio_part1();
> -
>gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
>return 0;
> }
> @@ -168,7 +109,8 @@ void dram_init_banksize(void)
> int board_eth_init(bd_t *bis)
> {
> #ifdef CONFIG_SMC911X
> - smc9115_pre_init();
> + if (smc9115_pre_init())
> + return -1;
>return smc911x_initialize(0, CONFIG_SMC911X_BASE);
> #endif
>return 0;
> @@ -186,31 +128,12 @@ int checkboard(void)
> #ifdef CONFIG_GENERIC_MMC
> int board_mmc_init(bd_t *bis)
> {
> - int i, err;
> -
> - /*
> -* MMC2 SD card GPIO:
> -*
> -* GPC2[0] SD_2_CLK(2)
> -* GPC2[1] SD_2_CMD(2)
> -* GPC2[2] SD_2_CDn
> -* GPC2[3:6]
Re: [U-Boot] [PATCH 1/2 V5] EXYNOS5: PINMUX: Added default pinumx settings
Hi,
On Mon, Jun 4, 2012 at 10:52 PM, Rajeshwari Shinde wrote:
> This patch performs the pinmux configuration in a common file.
> As of now only EXYNOS5 pinmux for SDMMC, UART and Ethernet is
> supported.
>
> Signed-off-by: Abhilash Kesavan
> Signed-off-by: Che-Liang Chiou
> Signed-off-by: Rajeshwari Shinde
> Acked-by: Chander Kashyap
>
Acked-by: Simon Glass
> ---
> Changes in V2:
>- Adding pinmux.c to Makefile moved to this patch.
>- exynos5_pinmux_config made static
> Changes in V3:
>- Separate functions made for each peripheral
>- enum periph_id moved to a separate periph.h
> Changes in V4:
>- removed variable declarations from exynos5_pinmux_config
> Chnages in V5:
>- added a return statement for function exynos5_mmc_config
>and added a check for same
> arch/arm/cpu/armv7/exynos/Makefile|2 +-
> arch/arm/cpu/armv7/exynos/pinmux.c| 219
> +
> arch/arm/include/asm/arch-exynos/periph.h | 47 ++
> arch/arm/include/asm/arch-exynos/pinmux.h | 58
> 4 files changed, 325 insertions(+), 1 deletions(-)
> create mode 100644 arch/arm/cpu/armv7/exynos/pinmux.c
> create mode 100644 arch/arm/include/asm/arch-exynos/periph.h
> create mode 100644 arch/arm/include/asm/arch-exynos/pinmux.h
>
> diff --git a/arch/arm/cpu/armv7/exynos/Makefile
> b/arch/arm/cpu/armv7/exynos/Makefile
> index 90ec2bd..9119961 100644
> --- a/arch/arm/cpu/armv7/exynos/Makefile
> +++ b/arch/arm/cpu/armv7/exynos/Makefile
> @@ -22,7 +22,7 @@ include $(TOPDIR)/config.mk
>
> LIB= $(obj)lib$(SOC).o
>
> -COBJS += clock.o power.o soc.o system.o
> +COBJS += clock.o power.o soc.o system.o pinmux.o
>
> SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
> diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
> b/arch/arm/cpu/armv7/exynos/pinmux.c
> new file mode 100644
> index 000..23ed2bf
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/exynos/pinmux.c
> @@ -0,0 +1,219 @@
> +/*
> + * Copyright (c) 2012 Samsung Electronics.
> + * Abhilash Kesavan
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +
> +static void exynos5_uart_config(int peripheral)
> +{
> + struct exynos5_gpio_part1 *gpio1 =
> + (struct exynos5_gpio_part1 *)
> samsung_get_base_gpio_part1();
> + struct s5p_gpio_bank *bank;
> + int i, start, count;
> +
> + switch (peripheral) {
> + case PERIPH_ID_UART0:
> + bank = &gpio1->a0;
> + start = 0;
> + count = 4;
> + break;
> + case PERIPH_ID_UART1:
> + bank = &gpio1->a0;
> + start = 4;
> + count = 4;
> + break;
> + case PERIPH_ID_UART2:
> + bank = &gpio1->a1;
> + start = 0;
> + count = 4;
> + break;
> + case PERIPH_ID_UART3:
> + bank = &gpio1->a1;
> + start = 4;
> + count = 2;
> + break;
> + }
> + for (i = start; i < start + count; i++) {
> + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
> + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
> + }
> +}
> +
> +static int exynos5_mmc_config(int peripheral, int flags)
> +{
> + struct exynos5_gpio_part1 *gpio1 =
> + (struct exynos5_gpio_part1 *)
> samsung_get_base_gpio_part1();
> + struct s5p_gpio_bank *bank, *bank_ext;
> + int i;
>
blank line here
> + switch (peripheral) {
> + case PERIPH_ID_SDMMC0:
> + bank = &gpio1->c0;
> + bank_ext = &gpio1->c1;
> + break;
> + case PERIPH_ID_SDMMC1:
> + bank = &gpio1->c1;
> + bank_ext = NULL;
> + break;
> + case PERIPH_ID_SDMMC2:
> + bank = &gpio1->c2;
> + bank_ext = &gpio1->c3;
> + break;
> + case PERIPH_ID_SDMMC3:
> + bank = &gpio1->c3;
> + bank_ext = NULL;
> + break;
> + }
> + if ((flags
Re: [U-Boot] [PATCH] powerpc/CoreNet: add tool to support pbl image build.
>-Original Message- >From: Wood Scott-B07421 >Sent: Thursday, June 07, 2012 2:19 AM >To: Xie Shaohui-B21989 >Cc: Wood Scott-B07421; u-boot@lists.denx.de; Tabi Timur-B04825 >Subject: Re: [U-Boot] [PATCH] powerpc/CoreNet: add tool to support pbl >image build. > >On 06/05/2012 09:45 PM, Xie Shaohui-B21989 wrote: >>> -Original Message- >>> From: Wood Scott-B07421 >>> Sent: Wednesday, June 06, 2012 2:14 AM >>> To: Xie Shaohui-B21989 >>> Cc: Wood Scott-B07421; u-boot@lists.denx.de; Tabi Timur-B04825 >>> Subject: Re: [U-Boot] [PATCH] powerpc/CoreNet: add tool to support >>> pbl image build. >>> >>> On 06/05/2012 12:35 AM, Xie Shaohui-B21989 wrote: >> +++ b/board/freescale/corenet_ds/config.mk >> @@ -0,0 +1,26 @@ >> +# >> + >> +#PBL preamble and RCW header >> +aa55aa55 010e0100 >> +#64 bytes RCW data for P4080, replace it when building image #for >> +P3041DS or P5020DS. >> +4c58 18185218 40464000 3c3c2000 5800 >> +6100 008b6000 >> + > > Could you have the tool source this from a separate file, rather > than require the user to replace it manually? [Xie Shaohui] Then I have to prepare a separate file and a tool... It is quite simple to replace, just copy and paste, and users may need to modify the RCW when the default one does not fit their use case, they will always have to do it manually. It's simple to do it >here. >>> >>> I disagree that copy and paste is good enough, though taking an >>> external RCW source (such as output from Timur's tool) could be a >>> future enhancement. >> >> [Xie Shaohui] OK. Suppose we got the output from Timur's tool, what >> should we do for the input if we need to change the RCW? > >You change the input to Timur's tool -- that's what it's for. It compiles >a textual description of the RCW settings into a PBL image. > >> Can Timur's >> tool do it automatically, or by some arguments provided? And even >> though, there will be two files for configuration, one is RCW output >> from Timur's tool, and another is PBI commands. This is too much for >> the tool; it has only one entry for configuration file. > >Too much for which tool, and why can't that be changed? [Xie Shaohui] The mkimage structure provides one entry to indicate the configuration file, is it OK to add a more entry just for PBL? > > Talk to Timur (when he gets back from vacation in a couple weeks) > about his RCW tool and how best to accept the output it produces. > > Why is eSPI in here? Isn't this supposed to just generically write > an image into CPC SRAM? [Xie Shaohui] No. some interfaces need to be pre-initialized before PBL start to load stuff from it, and default configurations for SPI is suitable, this tool provides a more compatible configurations. >>> >>> What do you mean by a more compatible configuration? If the default >>> is good enough to load the first few PBL commands, why is it not goot >>> enough to load the rest? >> >> [Xie Shaohui] the default configurations for SPI is too slow, it will >> take more than half minutes to finish the loading. > >Please add a comment describing what you're doing to the SPI controller >and why. Are there any situations where the faster speed you're >programming won't work? [Xie Shaohui] OK. Will add a comment in new version. The configuration for SPI is same as the one used in u-boot, so I think it's OK for PBL. Best Regards, Shaohui Xie ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 08/10] tegra20: add u-boot.t2 target
On 06/06/2012 04:00 PM, Allen Martin wrote: > On Wed, Jun 06, 2012 at 12:57:05PM -0700, Stephen Warren wrote: >> On 06/06/2012 01:53 PM, Tom Warren wrote: I'll move the SPL to 0x108000 and the normal u-boot to 0x208000 if that sounds more acceptable. >>> The current flash tools everyone is using expect to flash U-Boot to >>> 0x0108000 (on T20). This works with the non-SPL (current) upstream U-Boot >>> for Tegra, and should continue to work for any new SPL Tegra U-Boot, so >>> that people can use the same flash tools for either build. >>> >>> Note that the above statement assumes we'll still be able to build either a >>> 'normal' non-SPL build of Tegra U-Boot and a SPL build with your patchset, >>> at least in the interim while we're testing/reviewing these major changes. >> >> I assume that once a board is converted to SPL, you always use a >> matched/concatenated pair of SPL+non-SPL, i.e. never SPL on its own or >> non-SPL on its own? > > Yes, that's the intention. Although I do have plans down the road for > adding memory initialization to the SPL so I can use it for > boot/flashing when in recovery mode and there's no BCT. In the normal > case they have to be used together. How would that work; in the regular boot process, SPL would be linked to e.g. 00108000 since the boot ROM will put it into SDRAM. However, in recovery mode, code will be downloaded to the IRAM, so would have to be linked to a different address, and hence the same SPL binary couldn't be used. At that point, aren't we looking at: * Regular boot SPL, which just sets up a few PLLs and jump-starts the A9s. * Regular boot full-blown U-Boot to run on the A9s. * Some third build t run from IRAM. Or am I missing something? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 06/10] ARM: add tegra20 support to arm720t
On 06/06/2012 04:18 PM, Allen Martin wrote: > On Wed, Jun 06, 2012 at 12:17:53PM -0700, Stephen Warren wrote: >> Oh, I see. MACH_TEGRA_GENERIC means "some Tegra SoC", and CONFIG_TEGRA* >> indicate which one. Coming from my kernel background, MACH_* is a define >> for a particular board, and we do have a GENERIC Tegra board, so I got >> the wrong end of the stick. >> >> I wonder if it's worth renaming CONFIG_MACH_TEGRA_GENERIC to >> CONFIG_TEGRA. There don't appear to be any users of it currently. > > Fine by me, maybe CONFIG_TEGRA2 should go to CONFIG_TEGRA20 also to > keep with the new naming? Sounds reasonable to me. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 06/10] ARM: add tegra20 support to arm720t
On Wed, Jun 06, 2012 at 12:17:53PM -0700, Stephen Warren wrote: > Oh, I see. MACH_TEGRA_GENERIC means "some Tegra SoC", and CONFIG_TEGRA* > indicate which one. Coming from my kernel background, MACH_* is a define > for a particular board, and we do have a GENERIC Tegra board, so I got > the wrong end of the stick. > > I wonder if it's worth renaming CONFIG_MACH_TEGRA_GENERIC to > CONFIG_TEGRA. There don't appear to be any users of it currently. Fine by me, maybe CONFIG_TEGRA2 should go to CONFIG_TEGRA20 also to keep with the new naming? -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 08/10] tegra20: add u-boot.t2 target
On Wed, Jun 06, 2012 at 12:57:05PM -0700, Stephen Warren wrote: > On 06/06/2012 01:53 PM, Tom Warren wrote: > >> > >> I'll move the SPL to 0x108000 and the normal u-boot to 0x208000 if that > >> sounds more acceptable. > > The current flash tools everyone is using expect to flash U-Boot to > > 0x0108000 (on T20). This works with the non-SPL (current) upstream U-Boot > > for Tegra, and should continue to work for any new SPL Tegra U-Boot, so > > that people can use the same flash tools for either build. > > > > Note that the above statement assumes we'll still be able to build either a > > 'normal' non-SPL build of Tegra U-Boot and a SPL build with your patchset, > > at least in the interim while we're testing/reviewing these major changes. > > I assume that once a board is converted to SPL, you always use a > matched/concatenated pair of SPL+non-SPL, i.e. never SPL on its own or > non-SPL on its own? Yes, that's the intention. Although I do have plans down the road for adding memory initialization to the SPL so I can use it for boot/flashing when in recovery mode and there's no BCT. In the normal case they have to be used together. > > But that does bring up one point - boards which haven't yet converted to > SPL need to still build/link for the original 00108000 address, so the > addresses need to depend on config data. > > Either that, or just convert all boards at once? I'll need to convert all the boards. Since I removed the Cortex A9 init from the normal u-boot it will no longer work for non SPL boot. I think that's what we want anyway, I just may need some help testing some of the boards I don't have. -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH][v2] powerpc/CoreNet: add tool to support pbl image build.
On 06/06/2012 04:09 PM, Wolfgang Denk wrote: > Dear Shaohui Xie, > > In message <1338979010-950-1-git-send-email-shaohui@freescale.com> you > wrote: >> + For eSPI boot: >> +To build the eSPI boot image for P4080DS: >> +make P4080DS_SPIFLASH >> + >> +To build the eSPI boot image for P3041DS: >> +make P3041DS_SPIFLASH >> + >> +To build the eSPI boot image for P5020DS: >> +make P5020DS_SPIFLASH > > Come on, this doesn't scale. Why not simply: > > make _SPIFLASH > > ? Listing all boards here isn't the right answer, but some targets might have other orthogonal options to be specified, so the pattern wouldn't necessarily hold. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH][v2] powerpc/CoreNet: add tool to support pbl image build.
Dear Shaohui Xie, In message <1338979010-950-1-git-send-email-shaohui@freescale.com> you wrote: > Provides a tool to build boot Image for PBL(Pre boot loader) which is > used on Freescale CoreNet SoCs, PBL can be used to load some instructions > and/or data for pre-initialization. The default output image is u-boot.pbl, > for more details please refer to doc/README.pblimage. > > Signed-off-by: Shaohui Xie > --- > Makefile|5 + > board/freescale/corenet_ds/config.mk| 26 +++ > board/freescale/corenet_ds/pblimage.cfg | 60 ++ ... BTW: The subject says V2, but there is no change log. This is mandatory!! Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Our way is peace. -- Septimus, the Son Worshiper, "Bread and Circuses", stardate 4040.7. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH][v2] powerpc/CoreNet: add tool to support pbl image build.
Dear Shaohui Xie,
In message <1338979010-950-1-git-send-email-shaohui@freescale.com> you
wrote:
> Provides a tool to build boot Image for PBL(Pre boot loader) which is
> used on Freescale CoreNet SoCs, PBL can be used to load some instructions
> and/or data for pre-initialization. The default output image is u-boot.pbl,
> for more details please refer to doc/README.pblimage.
...
> --- /dev/null
> +++ b/board/freescale/corenet_ds/config.mk
> @@ -0,0 +1,26 @@
...
> +ifeq ($(CONFIG_RAMBOOT_PBL), y)
> +CONFIG_PBL_CONFIG = $(SRCTREE)/$(CONFIG_BOARDDIR)/pblimage.cfg
> +ALL-y += $(obj)u-boot.pbl
> +endif
I want to get rid if config.mk files to the extend possible - and here
I see no need for a new one.
Please dump this.
> diff --git a/board/freescale/corenet_ds/pblimage.cfg
> b/board/freescale/corenet_ds/pblimage.cfg
> new file mode 100644
> index 000..01003ce
> --- /dev/null
> +++ b/board/freescale/corenet_ds/pblimage.cfg
> @@ -0,0 +1,60 @@
...
> +#64 bytes RCW data for P4080, replace it when building image
> +#for P3041DS or P5020DS.
> +4c58 18185218
> +40464000 3c3c2000 5800 6100
> + 008b6000
> +
You don;t expect us to edit this fiule just when building for another
target? Please find a solution that works without editing source
files.
> diff --git a/common/image.c b/common/image.c
> index 202c8a1..afc7155 100644
> --- a/common/image.c
> +++ b/common/image.c
> @@ -147,6 +147,7 @@ static const table_entry_t uimage_type[] = {
> { IH_TYPE_SCRIPT, "script", "Script", },
> { IH_TYPE_STANDALONE, "standalone", "Standalone Program", },
> { IH_TYPE_UBLIMAGE, "ublimage", "Davinci UBL image",},
> + { IH_TYPE_PBLIMAGE, "pblimage", "Freescale PBL Boot Image",},
Please keep/make list sorted.
> --- /dev/null
> +++ b/doc/README.pblimage
> @@ -0,0 +1,138 @@
> +--
> +Freescale PBL(pre-boot loader) Boot Image generation using mkimage
> +--
> +
> +This document describes the U-Boot feature as it
> +is implemented for the Freescale CoreNet SoC.
Is it also implemented for other SoCs, differently? If not, then this
is redundant and should be removed.
> +The CoreNet SoC's can boot directly from eSPI FLASH, SD/MMC and
> +NAND, etc. For more details refer section 5 Pre-boot loader
> +specifications.
section 5 of which document? Provide title and URL.
> + For eSPI boot:
> + To build the eSPI boot image for P4080DS:
> + make P4080DS_SPIFLASH
> +
> + To build the eSPI boot image for P3041DS:
> + make P3041DS_SPIFLASH
> +
> + To build the eSPI boot image for P5020DS:
> + make P5020DS_SPIFLASH
Come on, this doesn't scale. Why not simply:
make _SPIFLASH
?
> +2. Command below provided a way to re-build the PBL boot image if the
> +configuration file needes to be modified while the u-boot.bin does not
> +need to be re-built.
Fix spelling and grammar.
Also, such a command should never be necessary - the "make" system
should catch any such situations automatically. If it doesn't, then
please fix this.
> +Board specific configuration file specifications:
> +
> +1. This file must present in the $(BOARDDIR) and the name should be
> + pblimage.cfg (since this is used in Makefile)
WHo knows what $(BOARDDIR) might be? s/should/must/
> diff --git a/tools/Makefile b/tools/Makefile
> index 64bcc4d..26f4927 100644
> --- a/tools/Makefile
> +++ b/tools/Makefile
> @@ -90,6 +90,7 @@ OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o
> OBJ_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes.o
> NOPED_OBJ_FILES-y += aisimage.o
> NOPED_OBJ_FILES-y += kwbimage.o
> +NOPED_OBJ_FILES-y += pblimage.o
> NOPED_OBJ_FILES-y += imximage.o
> NOPED_OBJ_FILES-y += omapimage.o
> NOPED_OBJ_FILES-y += mkenvimage.o
> @@ -203,6 +204,7 @@ $(obj)mkimage$(SFX): $(obj)aisimage.o \
> $(obj)image.o \
> $(obj)imximage.o \
> $(obj)kwbimage.o \
> + $(obj)pblimage.o \
> $(obj)md5.o \
> $(obj)mkimage.o \
> $(obj)os_support.o \
Should we make this code conditional? Most users will never need it.
Best regards,
Wolfgang Denk
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
When a woman marries again it is because she detested her first hus-
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Re: [U-Boot] [PATCH v2 08/10] tegra20: add u-boot.t2 target
On 06/06/2012 01:53 PM, Tom Warren wrote: > Allen, > >> -Original Message- >> From: Allen Martin [mailto:amar...@nvidia.com] >> Sent: Wednesday, June 06, 2012 12:37 PM >> To: Stephen Warren >> Cc: Tom Warren; s...@chromium.org; u-boot@lists.denx.de >> Subject: Re: [PATCH v2 08/10] tegra20: add u-boot.t2 target >> >> On Wed, Jun 06, 2012 at 09:48:23AM -0700, Stephen Warren wrote: >>> On 06/05/2012 03:20 PM, Allen Martin wrote: Add target for tegra20 u-boot image. This is a concatenation of tegra spl and normal u-boot binaries. >>> diff --git a/board/nvidia/seaboard/config.mk b/board/nvidia/seaboard/config.mk >>> +PAD_TO=0x00108000 >>> >>> Oh crap, does this mean that we have to start flashing the combined >>> u-boot.t2 at 0x8000 (IIRC the start address of the SPL in an earlier >>> patch) instead of 0x108000? That would cause all kinds of problems. If >>> that is the case, can we move the SPL to the existing 0x108000, and >>> bump the regular U-Boot up a bit to make space? If that isn't the >>> case, could you please explain exactly how the SPL memory layout etc. >> works for me? >>> Thanks. >> >> The addresses are arbitrary, I picked 0x8000 for the SPL to preserve the >> existing 0x108000 for the normal u-boot but it doesn't have to be that way. >> The only requirement is that the SPL needs to know the address of the normal >> u-boot at compile time because it doesn't have any smarts to look for it. >> >> I'll move the SPL to 0x108000 and the normal u-boot to 0x208000 if that >> sounds more acceptable. > The current flash tools everyone is using expect to flash U-Boot to 0x0108000 > (on T20). This works with the non-SPL (current) upstream U-Boot for Tegra, > and should continue to work for any new SPL Tegra U-Boot, so that people can > use the same flash tools for either build. > > Note that the above statement assumes we'll still be able to build either a > 'normal' non-SPL build of Tegra U-Boot and a SPL build with your patchset, at > least in the interim while we're testing/reviewing these major changes. I assume that once a board is converted to SPL, you always use a matched/concatenated pair of SPL+non-SPL, i.e. never SPL on its own or non-SPL on its own? But that does bring up one point - boards which haven't yet converted to SPL need to still build/link for the original 00108000 address, so the addresses need to depend on config data. Either that, or just convert all boards at once? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 08/10] tegra20: add u-boot.t2 target
Allen, > -Original Message- > From: Allen Martin [mailto:amar...@nvidia.com] > Sent: Wednesday, June 06, 2012 12:37 PM > To: Stephen Warren > Cc: Tom Warren; s...@chromium.org; u-boot@lists.denx.de > Subject: Re: [PATCH v2 08/10] tegra20: add u-boot.t2 target > > On Wed, Jun 06, 2012 at 09:48:23AM -0700, Stephen Warren wrote: > > On 06/05/2012 03:20 PM, Allen Martin wrote: > > > Add target for tegra20 u-boot image. This is a concatenation of > > > tegra spl and normal u-boot binaries. > > > > > diff --git a/board/nvidia/seaboard/config.mk > > > b/board/nvidia/seaboard/config.mk > > > > > +PAD_TO=0x00108000 > > > > Oh crap, does this mean that we have to start flashing the combined > > u-boot.t2 at 0x8000 (IIRC the start address of the SPL in an earlier > > patch) instead of 0x108000? That would cause all kinds of problems. If > > that is the case, can we move the SPL to the existing 0x108000, and > > bump the regular U-Boot up a bit to make space? If that isn't the > > case, could you please explain exactly how the SPL memory layout etc. > works for me? > > Thanks. > > The addresses are arbitrary, I picked 0x8000 for the SPL to preserve the > existing 0x108000 for the normal u-boot but it doesn't have to be that way. > The only requirement is that the SPL needs to know the address of the normal > u-boot at compile time because it doesn't have any smarts to look for it. > > I'll move the SPL to 0x108000 and the normal u-boot to 0x208000 if that > sounds more acceptable. The current flash tools everyone is using expect to flash U-Boot to 0x0108000 (on T20). This works with the non-SPL (current) upstream U-Boot for Tegra, and should continue to work for any new SPL Tegra U-Boot, so that people can use the same flash tools for either build. Note that the above statement assumes we'll still be able to build either a 'normal' non-SPL build of Tegra U-Boot and a SPL build with your patchset, at least in the interim while we're testing/reviewing these major changes. Thanks, Tom > > -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 09/10] tegra20: Remove CPU init code from tegra20 u-boot
On Wed, Jun 06, 2012 at 09:51:09AM -0700, Stephen Warren wrote:
> On 06/05/2012 03:20 PM, Allen Martin wrote:
> > This code is now included in the tegra20 SPL
>
> > @@ -323,34 +91,10 @@ void init_pmc_scratch(void)
> >
> > /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
> > writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20);
> > -
> > -#ifdef CONFIG_TEGRA2_LP0
> > - /* save Sdram params to PMC 2, 4, and 24 for WB0 */
> > - warmboot_save_sdram_params();
> > -#endif
> > }
>
> Is that change intended, or was it a rebase mistake?
>
> > diff --git a/arch/arm/cpu/tegra20-common/board.c
> > b/arch/arm/cpu/tegra20-common/board.c
>
> > @@ -69,6 +68,11 @@ int dram_init(void)
> > {
> > /* We do not initialise DRAM here. We just query the size */
> > gd->ram_size = query_sdram_size();
> > +
> > +#ifdef CONFIG_TEGRA2_LP0
> > + /* save Sdram params to PMC 2, 4, and 24 for WB0 */
> > + warmboot_save_sdram_params();
> > +#endif
>
> Hmmm. That's more than just removing the code that's now in the AVP
> directory. Separate patch? The patch description also doesn't say why
> this change is necessary.
This code was added since v1 of the patch series, and I had to move it
because when I fixed it so we could use the normal lowlevel_init it
gets called before the devicetree is initialized.
I rolled it into this patch, but you're probably right, it would make
more sense to be in it's own patch with a proper description.
-Allen
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Re: [U-Boot] [PATCH v2 08/10] tegra20: add u-boot.t2 target
On Wed, Jun 06, 2012 at 09:48:23AM -0700, Stephen Warren wrote: > On 06/05/2012 03:20 PM, Allen Martin wrote: > > Add target for tegra20 u-boot image. This is a concatenation of tegra > > spl and normal u-boot binaries. > > > diff --git a/board/nvidia/seaboard/config.mk > > b/board/nvidia/seaboard/config.mk > > > +PAD_TO=0x00108000 > > Oh crap, does this mean that we have to start flashing the combined > u-boot.t2 at 0x8000 (IIRC the start address of the SPL in an earlier > patch) instead of 0x108000? That would cause all kinds of problems. If > that is the case, can we move the SPL to the existing 0x108000, and bump > the regular U-Boot up a bit to make space? If that isn't the case, could > you please explain exactly how the SPL memory layout etc. works for me? > Thanks. The addresses are arbitrary, I picked 0x8000 for the SPL to preserve the existing 0x108000 for the normal u-boot but it doesn't have to be that way. The only requirement is that the SPL needs to know the address of the normal u-boot at compile time because it doesn't have any smarts to look for it. I'll move the SPL to 0x108000 and the normal u-boot to 0x208000 if that sounds more acceptable. -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 06/10] ARM: add tegra20 support to arm720t
On 06/06/2012 12:25 PM, Allen Martin wrote: > On Wed, Jun 06, 2012 at 09:39:57AM -0700, Stephen Warren wrote: >> On 06/05/2012 03:20 PM, Allen Martin wrote: >>> Add support for tegra20 arm7 boot processor. This processor is used >>> to power on the Cortex A9 and transfer control to it. >> >>> diff --git a/arch/arm/cpu/arm720t/cpu.c b/arch/arm/cpu/arm720t/cpu.c >> >>> #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) >>> /* No cleanup before linux for IntegratorAP/CM720T as yet */ >>> +#elif defined (CONFIG_MACH_TEGRA_GENERIC) >>> + /* No cleanup before linux for tegra as yet */ >>> #else >>> #error No cleanup_before_linux() defined for this CPU type >>> #endif >> >> Wouldn't CONFIG_TEGRA2 be a better define to use? Same comment throughout. > > The SPL *should* work on tegra30 with only minor changes, so just > trying to look forward. Oh, I see. MACH_TEGRA_GENERIC means "some Tegra SoC", and CONFIG_TEGRA* indicate which one. Coming from my kernel background, MACH_* is a define for a particular board, and we do have a GENERIC Tegra board, so I got the wrong end of the stick. I wonder if it's worth renaming CONFIG_MACH_TEGRA_GENERIC to CONFIG_TEGRA. There don't appear to be any users of it currently. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 07/10] tegra20: add SPL config options for seaboard
On Wed, Jun 06, 2012 at 09:44:59AM -0700, Stephen Warren wrote: > On 06/05/2012 03:20 PM, Allen Martin wrote: > > Add SPL options to tegra20 config files and enable SPL build for > > seaboard in boards.cfg > > > diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h > > > +/* include overrides for SPL build */ > > +#ifdef CONFIG_SPL_BUILD > > +#include "tegra2-spl.h" > > +#endif > > Perhaps we should add that to include/configs/tegra2-common-post.h, > which I think all Tegra config headers now include at the end. Ok. > > > diff --git a/include/configs/tegra2-common.h > > b/include/configs/tegra2-common.h > > > +/* Defines for SPL */ > > +#define CONFIG_SPL > > +#define CONFIG_SPL_NAND_SIMPLE > > +#define CONFIG_SPL_TEXT_BASE 0x8000 > > +#define CONFIG_SPL_MAX_SIZE0x00078000 > > +#define CONFIG_SYS_SPL_MALLOC_START0x0008 > > +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001 > > +#define CONFIG_SPL_STACK 0x0009fffc > > + > > +#define CONFIG_SPL_LIBCOMMON_SUPPORT > > +#define CONFIG_SPL_LIBGENERIC_SUPPORT > > +#define CONFIG_SPL_SERIAL_SUPPORT > > > +#define CONFIG_SPL_POWER_SUPPORT > > I'm not sure what that's for? Hm, I put it in for the PMU driver, but maybe that's not actually needed in the SPL. I'll take a look. > > +#define CONFIG_SPL_GPIO_SUPPORT > > I believe only Seaboard needs that, not all boards. It'd be nice if we > could just ignore the crufy SPI/GPIO switch on Seaboard too and punt > this. Does anyone actually boot Seaboard using SPI? I use NAND and Tom > uses eMMC... Well I use SPI on my Springbank, but maybe I'm in the minority :^) > > diff --git a/include/configs/tegra2-spl.h b/include/configs/tegra2-spl.h > > > + * published by the Free Software Foundation; either version 2 of > > + * the License, or (at your option) any later version. > > Being a new file, this should be GPLv2 not GPLv2+. Ok. > > > +/* remove devicetree support */ > > +#ifdef CONFIG_OF_CONTROL > > +#undef CONFIG_OF_CONTROL > > +#endif > > I don't /think/ #undef complains if the define isn't defined? I've seen compilers that do, so I was just trying to play it safe. > > Perhaps this (and the others) are better approached by not defining all > these if building SPL though - what if a particular board's SPL actually > wanted any of these? That's what I had in v1 of the patch series, but it ends up adding a lot of #ifdefs sprinkled through each board config file. I'd like to keep the SPL as small and minimal as possible such that it doesn't need a lot of board specific configuration, just unavoidable things like UART. -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 06/10] ARM: add tegra20 support to arm720t
On Wed, Jun 06, 2012 at 09:39:57AM -0700, Stephen Warren wrote:
> On 06/05/2012 03:20 PM, Allen Martin wrote:
> > Add support for tegra20 arm7 boot processor. This processor is used
> > to power on the Cortex A9 and transfer control to it.
>
> > diff --git a/arch/arm/cpu/arm720t/cpu.c b/arch/arm/cpu/arm720t/cpu.c
>
> > #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
> > /* No cleanup before linux for IntegratorAP/CM720T as yet */
> > +#elif defined (CONFIG_MACH_TEGRA_GENERIC)
> > + /* No cleanup before linux for tegra as yet */
> > #else
> > #error No cleanup_before_linux() defined for this CPU type
> > #endif
>
> Wouldn't CONFIG_TEGRA2 be a better define to use? Same comment throughout.
The SPL *should* work on tegra30 with only minor changes, so just
trying to look forward.
> > diff --git a/arch/arm/cpu/arm720t/tegra20/cpu.c
> > b/arch/arm/cpu/arm720t/tegra20/cpu.c
>
> > +/* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */
> > +int ap20_cpu_is_cortexa9(void)
> > +{
> > + u32 id = readb(NV_PA_PG_UP_BASE + PG_UP_TAG_0);
> > + return id == (PG_UP_TAG_0_PID_CPU & 0xff);
> > +}
>
> Doesn't the SPL always run on the AVP, and the regular U-Boot build
> always run on the main CPUs - I'm not sure why this runtime API would be
> needed.
I think this is just a holdover from the old code, I'll look at
purging it.
> > +void init_pllx(void)
>
> I assume a lot of the code in this file is copied from the
> armv7/tegra20/*.c files. Shouldn't this patch remove the ARMv7 versions
> since presumably it's no longer needed - doesn't the non-SPL U-Boot rely
> on the SPL U-Boot always having run first in order to start the main
> U-Boot executing?
Yes, I remove some of it in "tegra20: Remove CPU init code from
tegra20 u-boot". I'll look at rolling that patch into this one, but I
originally made it two patches to try to preserve building and booting
at every patch.
>
> If not, then shouldn't this code be in tegra20-common so it can be shared?
>
> > diff --git a/arch/arm/cpu/arm720t/tegra20/cpu.h
> > b/arch/arm/cpu/arm720t/tegra20/cpu.h
>
> Similarly, this file seems like it'd be in tegra20-common/include or
> somewhere like that.
Those defines are only used for the Cortex A9 init, so it should only
be needed from the SPL.
-Allen
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Re: [U-Boot] [PATCH] powerpc/CoreNet: add tool to support pbl image build.
On 06/05/2012 09:45 PM, Xie Shaohui-B21989 wrote: >> -Original Message- >> From: Wood Scott-B07421 >> Sent: Wednesday, June 06, 2012 2:14 AM >> To: Xie Shaohui-B21989 >> Cc: Wood Scott-B07421; u-boot@lists.denx.de; Tabi Timur-B04825 >> Subject: Re: [U-Boot] [PATCH] powerpc/CoreNet: add tool to support pbl >> image build. >> >> On 06/05/2012 12:35 AM, Xie Shaohui-B21989 wrote: > +++ b/board/freescale/corenet_ds/config.mk > @@ -0,0 +1,26 @@ > +# > + > +#PBL preamble and RCW header > +aa55aa55 010e0100 > +#64 bytes RCW data for P4080, replace it when building image #for > +P3041DS or P5020DS. > +4c58 18185218 40464000 3c3c2000 5800 > +6100 008b6000 > + Could you have the tool source this from a separate file, rather than require the user to replace it manually? >>> >>> [Xie Shaohui] Then I have to prepare a separate file and a tool... >>> It is quite simple to replace, just copy and paste, and users may need >>> to modify the RCW when the default one does not fit their use case, >>> they will always have to do it manually. It's simple to do it here. >> >> I disagree that copy and paste is good enough, though taking an external >> RCW source (such as output from Timur's tool) could be a future >> enhancement. > > [Xie Shaohui] OK. Suppose we got the output from Timur's tool, what > should we do for the input if we need to change the RCW? You change the input to Timur's tool -- that's what it's for. It compiles a textual description of the RCW settings into a PBL image. > Can Timur's > tool do it automatically, or by some arguments provided? And even > though, there will be two files for configuration, one is RCW output > from Timur's tool, and another is PBI commands. This is too much for > the tool; it has only one entry for configuration file. Too much for which tool, and why can't that be changed? Talk to Timur (when he gets back from vacation in a couple weeks) about his RCW tool and how best to accept the output it produces. Why is eSPI in here? Isn't this supposed to just generically write an image into CPC SRAM? >>> >>> [Xie Shaohui] No. some interfaces need to be pre-initialized before >>> PBL start to load stuff from it, and default configurations for SPI is >>> suitable, this tool provides a more compatible configurations. >> >> What do you mean by a more compatible configuration? If the default is >> good enough to load the first few PBL commands, why is it not goot enough >> to load the rest? > > [Xie Shaohui] the default configurations for SPI is too slow, it will > take more than half minutes to finish the loading. Please add a comment describing what you're doing to the SPI controller and why. Are there any situations where the faster speed you're programming won't work? -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 03/10] mkconfig: add support for SPL CPU
On Wed, Jun 06, 2012 at 09:20:22AM -0700, Stephen Warren wrote:
> On 06/05/2012 03:20 PM, Allen Martin wrote:
> > Add support for specifying a differnt CPU for main u-boot and SPL
>
> typo^^
Got it, thanks.
> > u-boot builds. This is done by adding an optional SPL CPU after the
> > main CPU in boards.cfg as follows:
> >
> > normal_cpu:spl_cpu
> >
> > This this case CPU will be set to "normal_cpu" during the main u-boot
> > build and "spl_cpu" during the SPL build.
>
> > diff --git a/mkconfig b/mkconfig
>
> > +tmp="${cpu#*:}"
> > +if [ "$tmp" != "$cpu" ] ; then
> > + spl_cpu=$tmp
> > + cpu="${cpu%:*}"
> > +fi
>
> Neat - I wasn't aware of those variable expansion techniques.
>
> However, this script runs under /bin/sh - are they standard sh
> constructs, or are they bash-isms? I wonder if shelling out to awk or
> cut here would be more portable?
It's bash, I'll rewrite it with awk.
-Allen
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Re: [U-Boot] [PATCH v2 02/10] tegra20: move tegra20 SoC code to arch/arm/cpu/tegra20-common
On Wed, Jun 06, 2012 at 09:16:46AM -0700, Stephen Warren wrote: > On 06/05/2012 03:20 PM, Allen Martin wrote: > > In preparation for splitting out the armv4t code from tegra20, move > > the tegra20 SoC code to arch/arm/cpu/tegra20-common. This code will > > be compiled armv4t for the arm7tdmi and armv7 for the cortex A9. > > > diff --git a/arch/arm/cpu/armv7/tegra20/Makefile > > b/arch/arm/cpu/tegra20-common/Makefile > > > # The AVP is ARMv4T architecture so we must use special compiler > > # flags for any startup files it might use. > > -CFLAGS_arch/arm/cpu/armv7/tegra2/ap20.o += -march=armv4t > > -CFLAGS_arch/arm/cpu/armv7/tegra2/clock.o += -march=armv4t > > -CFLAGS_arch/arm/cpu/armv7/tegra2/warmboot_avp.o += -march=armv4t > > +CFLAGS_arch/arm/cpu/tegra2-common/ap20.o += -march=armv4t > > +CFLAGS_arch/arm/cpu/tegra2-common/clock.o += -march=armv4t > > Don't you still need the CFLAGS override for warmboot_avp.o here too? I > assume that a later patch will just remove it, but it'd be nice if each > patch along the way built and booted OK to, so that "git bisect" works > through this series. When I first wrote the series I made sure it booted at each patch, but I didn't reconfirm with all the changes, so it's quite possible I broke that. I'll make sure I preserve that. > > -COBJS := $(COBJS-y) > > -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) > > -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) > > +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) > > +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) > > At least in this patch, I don't think SOBJS is set. Does using it here > cause build issues? I'll confirm. > > diff --git a/spl/Makefile b/spl/Makefile > > > +ifneq ($(CONFIG_TEGRA2),) > > +LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o > > +endif > > In another file in this patch, that first line was the non-inverted test: > > +ifeq ($(SOC),tegra20) > > That seems simpler. Can we use the same here? Sure. -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 01/10] tegra20: rename tegra2 -> tegra20
On Wed, Jun 06, 2012 at 09:11:01AM -0700, Stephen Warren wrote: > On 06/05/2012 03:20 PM, Allen Martin wrote: > > This is make naming consistent with the kernel and devicetree and in > > preparation of pulling out the common tegra20 code. > > > diff --git a/boards.cfg b/boards.cfg > > This misses a couple of recently added boards - whistler and trimslice. I based the series off u-boot/master, I'll rebase against u-boot-tegra/next -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] da850/omap-l138: Enable auto negotiation in RMII mode
Hi Prabhakar, Le Fri, 1 Jun 2012 19:04:37 +0530, Prabhakar Lad a écrit : > From: Rajashekhara, Sudhakar > > On DA850/OMAP-L138 it was observed that in RMII mode, > auto negotiation was not performed. This patch enables > auto negotiation in RMII mode. Without this patch, EMAC > initialization takes more time and sometimes tftp fails > in RMII mode. > > Signed-off-by: Rajashekhara, Sudhakar > Signed-off-by: Lad, Prabhakar > Signed-off-by: Hadli, Manjunath Tested-by: Eric Bénard on an AM1808 with a RMII PHY where tftp was nearly always failing. Eric ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 10/10] tegra20: Remove armv4t build flags
On 06/05/2012 03:20 PM, Allen Martin wrote: > These flags were necessary when building tegra20 as a single binary > that supported ARM7TDMI and Cortex A9. Now that the ARM7TDMI support > is split into a separate SPL, this is no longer necessary. Can we also (probably in a separate patch) remove USE_PRIVATE_LIBGCC from the makefiles/... wherever we define it for Tegra? At least for the non-SPL build; presumably the SPL build will still need it. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 09/10] tegra20: Remove CPU init code from tegra20 u-boot
On 06/05/2012 03:20 PM, Allen Martin wrote:
> This code is now included in the tegra20 SPL
> @@ -323,34 +91,10 @@ void init_pmc_scratch(void)
>
> /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
> writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20);
> -
> -#ifdef CONFIG_TEGRA2_LP0
> - /* save Sdram params to PMC 2, 4, and 24 for WB0 */
> - warmboot_save_sdram_params();
> -#endif
> }
Is that change intended, or was it a rebase mistake?
> diff --git a/arch/arm/cpu/tegra20-common/board.c
> b/arch/arm/cpu/tegra20-common/board.c
> @@ -69,6 +68,11 @@ int dram_init(void)
> {
> /* We do not initialise DRAM here. We just query the size */
> gd->ram_size = query_sdram_size();
> +
> +#ifdef CONFIG_TEGRA2_LP0
> + /* save Sdram params to PMC 2, 4, and 24 for WB0 */
> + warmboot_save_sdram_params();
> +#endif
Hmmm. That's more than just removing the code that's now in the AVP
directory. Separate patch? The patch description also doesn't say why
this change is necessary.
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Re: [U-Boot] [PATCH v2 08/10] tegra20: add u-boot.t2 target
On 06/05/2012 03:20 PM, Allen Martin wrote: > Add target for tegra20 u-boot image. This is a concatenation of tegra > spl and normal u-boot binaries. > diff --git a/board/nvidia/seaboard/config.mk b/board/nvidia/seaboard/config.mk > +PAD_TO=0x00108000 Oh crap, does this mean that we have to start flashing the combined u-boot.t2 at 0x8000 (IIRC the start address of the SPL in an earlier patch) instead of 0x108000? That would cause all kinds of problems. If that is the case, can we move the SPL to the existing 0x108000, and bump the regular U-Boot up a bit to make space? If that isn't the case, could you please explain exactly how the SPL memory layout etc. works for me? Thanks. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 07/10] tegra20: add SPL config options for seaboard
On 06/05/2012 03:20 PM, Allen Martin wrote: > Add SPL options to tegra20 config files and enable SPL build for > seaboard in boards.cfg > diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h > +/* include overrides for SPL build */ > +#ifdef CONFIG_SPL_BUILD > +#include "tegra2-spl.h" > +#endif Perhaps we should add that to include/configs/tegra2-common-post.h, which I think all Tegra config headers now include at the end. > diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h > +/* Defines for SPL */ > +#define CONFIG_SPL > +#define CONFIG_SPL_NAND_SIMPLE > +#define CONFIG_SPL_TEXT_BASE 0x8000 > +#define CONFIG_SPL_MAX_SIZE 0x00078000 > +#define CONFIG_SYS_SPL_MALLOC_START 0x0008 > +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001 > +#define CONFIG_SPL_STACK 0x0009fffc > + > +#define CONFIG_SPL_LIBCOMMON_SUPPORT > +#define CONFIG_SPL_LIBGENERIC_SUPPORT > +#define CONFIG_SPL_SERIAL_SUPPORT > +#define CONFIG_SPL_POWER_SUPPORT I'm not sure what that's for? > +#define CONFIG_SPL_GPIO_SUPPORT I believe only Seaboard needs that, not all boards. It'd be nice if we could just ignore the crufy SPI/GPIO switch on Seaboard too and punt this. Does anyone actually boot Seaboard using SPI? I use NAND and Tom uses eMMC... > diff --git a/include/configs/tegra2-spl.h b/include/configs/tegra2-spl.h > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. Being a new file, this should be GPLv2 not GPLv2+. > +/* remove devicetree support */ > +#ifdef CONFIG_OF_CONTROL > +#undef CONFIG_OF_CONTROL > +#endif I don't /think/ #undef complains if the define isn't defined? Perhaps this (and the others) are better approached by not defining all these if building SPL though - what if a particular board's SPL actually wanted any of these? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 06/10] ARM: add tegra20 support to arm720t
On 06/05/2012 03:20 PM, Allen Martin wrote:
> Add support for tegra20 arm7 boot processor. This processor is used
> to power on the Cortex A9 and transfer control to it.
> diff --git a/arch/arm/cpu/arm720t/cpu.c b/arch/arm/cpu/arm720t/cpu.c
> #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
> /* No cleanup before linux for IntegratorAP/CM720T as yet */
> +#elif defined (CONFIG_MACH_TEGRA_GENERIC)
> + /* No cleanup before linux for tegra as yet */
> #else
> #error No cleanup_before_linux() defined for this CPU type
> #endif
Wouldn't CONFIG_TEGRA2 be a better define to use? Same comment throughout.
> diff --git a/arch/arm/cpu/arm720t/tegra20/cpu.c
> b/arch/arm/cpu/arm720t/tegra20/cpu.c
> +/* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */
> +int ap20_cpu_is_cortexa9(void)
> +{
> + u32 id = readb(NV_PA_PG_UP_BASE + PG_UP_TAG_0);
> + return id == (PG_UP_TAG_0_PID_CPU & 0xff);
> +}
Doesn't the SPL always run on the AVP, and the regular U-Boot build
always run on the main CPUs - I'm not sure why this runtime API would be
needed.
> +void init_pllx(void)
I assume a lot of the code in this file is copied from the
armv7/tegra20/*.c files. Shouldn't this patch remove the ARMv7 versions
since presumably it's no longer needed - doesn't the non-SPL U-Boot rely
on the SPL U-Boot always having run first in order to start the main
U-Boot executing?
If not, then shouldn't this code be in tegra20-common so it can be shared?
> diff --git a/arch/arm/cpu/arm720t/tegra20/cpu.h
> b/arch/arm/cpu/arm720t/tegra20/cpu.h
Similarly, this file seems like it'd be in tegra20-common/include or
somewhere like that.
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Re: [U-Boot] [PATCH v2 03/10] mkconfig: add support for SPL CPU
On 06/05/2012 03:20 PM, Allen Martin wrote:
> Add support for specifying a differnt CPU for main u-boot and SPL
typo^^
> u-boot builds. This is done by adding an optional SPL CPU after the
> main CPU in boards.cfg as follows:
>
> normal_cpu:spl_cpu
>
> This this case CPU will be set to "normal_cpu" during the main u-boot
> build and "spl_cpu" during the SPL build.
> diff --git a/mkconfig b/mkconfig
> +tmp="${cpu#*:}"
> +if [ "$tmp" != "$cpu" ] ; then
> + spl_cpu=$tmp
> + cpu="${cpu%:*}"
> +fi
Neat - I wasn't aware of those variable expansion techniques.
However, this script runs under /bin/sh - are they standard sh
constructs, or are they bash-isms? I wonder if shelling out to awk or
cut here would be more portable?
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Re: [U-Boot] [PATCH v2 02/10] tegra20: move tegra20 SoC code to arch/arm/cpu/tegra20-common
On 06/05/2012 03:20 PM, Allen Martin wrote: > In preparation for splitting out the armv4t code from tegra20, move > the tegra20 SoC code to arch/arm/cpu/tegra20-common. This code will > be compiled armv4t for the arm7tdmi and armv7 for the cortex A9. > diff --git a/arch/arm/cpu/armv7/tegra20/Makefile > b/arch/arm/cpu/tegra20-common/Makefile > # The AVP is ARMv4T architecture so we must use special compiler > # flags for any startup files it might use. > -CFLAGS_arch/arm/cpu/armv7/tegra2/ap20.o += -march=armv4t > -CFLAGS_arch/arm/cpu/armv7/tegra2/clock.o += -march=armv4t > -CFLAGS_arch/arm/cpu/armv7/tegra2/warmboot_avp.o += -march=armv4t > +CFLAGS_arch/arm/cpu/tegra2-common/ap20.o += -march=armv4t > +CFLAGS_arch/arm/cpu/tegra2-common/clock.o += -march=armv4t Don't you still need the CFLAGS override for warmboot_avp.o here too? I assume that a later patch will just remove it, but it'd be nice if each patch along the way built and booted OK to, so that "git bisect" works through this series. > -COBJS:= $(COBJS-y) > -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) > -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) > +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) > +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) At least in this patch, I don't think SOBJS is set. Does using it here cause build issues? > diff --git a/spl/Makefile b/spl/Makefile > +ifneq ($(CONFIG_TEGRA2),) > +LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o > +endif In another file in this patch, that first line was the non-inverted test: +ifeq ($(SOC),tegra20) That seems simpler. Can we use the same here? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 01/10] tegra20: rename tegra2 -> tegra20
On 06/05/2012 03:20 PM, Allen Martin wrote: > This is make naming consistent with the kernel and devicetree and in > preparation of pulling out the common tegra20 code. > diff --git a/boards.cfg b/boards.cfg This misses a couple of recently added boards - whistler and trimslice. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v9 0/4] Kirkwood: add lschlv2 and lsxhl board support
> -Original Message- > From: Michael Walle [mailto:mich...@walle.cc] > Sent: 06 June 2012 12:39 > To: Joe Hershberger > Cc: Prafulla Wadaskar; u-boot@lists.denx.de > Subject: Re: [U-Boot] [PATCH v9 0/4] Kirkwood: add lschlv2 and lsxhl > board support > > > > Joe Hershberger schrieb: > > >Hi Prafulla, > > > >On Tue, Jun 5, 2012 at 4:36 PM, Michael Walle > wrote: > >> > >> Hi Prafulla, > >> > >> Am Dienstag 05 Juni 2012, 23:33:13 schrieb Michael Walle: > >>> Changes: > >>> v9: > >>> - rebase to marvell custodian tree, merged with wolfgangs master > >> [..snip..] > >> > >> > >> I had to merge your tree with wolfgangs master, because my second > net > >patch > >> depends on the latest net patches by Joe. > >> > >> So please make sure you merge wolfgangs master with your tree > before > >applying > >> these patches. u-boot-marvell.git is cloned from u-boot-arm.git, and I always sync with this before any task. And just to keep it clean for pull requests I would not like to pull any other repository in it. Copying Albert on this, who can sync u-boot.git into u-boot-arm.git if something is missing. Regards.. Prafulla . . . > > > >It seems a better way to handle this is to rebase marvell onto WD's > >master and push that to the marvell tree, allowing Michael to rebase > >his patches onto that version. It seems there should not be a merge > >here. > > that should work too. but my patcheset v9 should apply cleanly > regardless of which way you choose. > > michael > > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH][v2] powerpc/CoreNet: add tool to support pbl image build.
Provides a tool to build boot Image for PBL(Pre boot loader) which is used on Freescale CoreNet SoCs, PBL can be used to load some instructions and/or data for pre-initialization. The default output image is u-boot.pbl, for more details please refer to doc/README.pblimage. Signed-off-by: Shaohui Xie --- Makefile|5 + board/freescale/corenet_ds/config.mk| 26 +++ board/freescale/corenet_ds/pblimage.cfg | 60 ++ common/image.c |1 + doc/README.pblimage | 138 + include/image.h |1 + tools/Makefile |2 + tools/mkimage.c |5 + tools/mkimage.h |2 + tools/pblimage.c| 325 +++ tools/pblimage.h| 36 11 files changed, 601 insertions(+), 0 deletions(-) create mode 100644 board/freescale/corenet_ds/config.mk create mode 100644 board/freescale/corenet_ds/pblimage.cfg create mode 100644 doc/README.pblimage create mode 100644 tools/pblimage.c create mode 100644 tools/pblimage.h diff --git a/Makefile b/Makefile index 57ad45b..06f079f 100644 --- a/Makefile +++ b/Makefile @@ -416,6 +416,10 @@ $(obj)u-boot.kwb: $(obj)u-boot.bin $(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@ +$(obj)u-boot.pbl: $(obj)u-boot.bin + $(obj)tools/mkimage -n $(CONFIG_PBL_CONFIG) -T pblimage \ + -d $< $@ + $(obj)u-boot.sha1: $(obj)u-boot.bin $(obj)tools/ubsha1 $(obj)u-boot.bin @@ -773,6 +777,7 @@ clobber:tidy $(obj)cscope.* $(obj)*.*~ @rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL-y) @rm -f $(obj)u-boot.kwb + @rm -f $(obj)u-boot.pbl @rm -f $(obj)u-boot.imx @rm -f $(obj)u-boot.ubl @rm -f $(obj)u-boot.ais diff --git a/board/freescale/corenet_ds/config.mk b/board/freescale/corenet_ds/config.mk new file mode 100644 index 000..2a0ab9d --- /dev/null +++ b/board/freescale/corenet_ds/config.mk @@ -0,0 +1,26 @@ +# +# Copyright 2012 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +ifeq ($(CONFIG_RAMBOOT_PBL), y) +CONFIG_PBL_CONFIG = $(SRCTREE)/$(CONFIG_BOARDDIR)/pblimage.cfg +ALL-y += $(obj)u-boot.pbl +endif diff --git a/board/freescale/corenet_ds/pblimage.cfg b/board/freescale/corenet_ds/pblimage.cfg new file mode 100644 index 000..01003ce --- /dev/null +++ b/board/freescale/corenet_ds/pblimage.cfg @@ -0,0 +1,60 @@ +# +# Copyright 2012 Freescale Semiconductor, Inc. +# Written-by: Shaohui Xie +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.pblimage for more details about how-to configure +# and create PBL boot image +# + +#PBL preamble and RCW header +aa55aa55 010e0100 +#64 bytes RCW data for P4080, replace it when building image +#for P3041DS or P5020DS. +4c58 18185218 +40464000 3c3c2000 5800 6100 + 008b6000 + + +#PBI commands +#Initialize CPC1 +0901 00200400 +09138000 +091380c0 0100 +09010100 +09010104 fffb +09010f00 0800 +0901 8000 +#Configure LAW for CPC1 +09000d00 +09000d04 fff0 +09000d08 8113 +0910
Re: [U-Boot] [PATCH] tftp: fix type of block arg to store_block
Dear "Jayachandran C",
In message <1338961566-13389-1-git-send-email-jayachandr...@netlogicmicro.com>
you wrote:
> The block argument for store_block can be -1 when the tftp sequence
> number rolls over (i.e TftpBlock == 0), so the first argument to
> store_block has to be of type 'int' instead of 'unsigned'.
What makes you think so?
> -store_block (unsigned block, uchar * src, unsigned len)
> +store_block (int block, uchar * src, unsigned len)
> {
> ulong offset = block * TftpBlkSize + TftpBlockWrapOffset;
Block gets used to compute the offset into the storage area, so it
must never be negative.
I think your analysis must be flawed.
Best regards,
Wolfgang Denk
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Re: [U-Boot] [PATCH] da850/omap-l138: Enable auto negotiation in RMII mode
Hi Christian, On Tue, Jun 05, 2012 at 17:04:13, Christian Riesch wrote: > Hi, > > On Fri, Jun 1, 2012 at 3:34 PM, Prabhakar Lad wrote: > > From: Rajashekhara, Sudhakar > > > > On DA850/OMAP-L138 it was observed that in RMII mode, > > auto negotiation was not performed. This patch enables > > auto negotiation in RMII mode. Without this patch, EMAC > > initialization takes more time and sometimes tftp fails > > in RMII mode. > > > > This patch causes a warning for the ea20 board: > davinci_emac.c: In function 'davinci_emac_initialize': > davinci_emac.c:901:2: warning: passing argument 1 of > 'gen_auto_negotiate' makes integer from pointer without a cast > davinci_emac.c:355:12: note: expected 'int' but argument is of type 'u_int8_t > *' > > (found with ./MAKEALL -s davinci) > Ok I'll fix this. Thx, --Prabhakar Lad > Regards, Christian > > > Signed-off-by: Rajashekhara, Sudhakar > > Signed-off-by: Lad, Prabhakar > > Signed-off-by: Hadli, Manjunath > > --- > > drivers/net/davinci_emac.c | 5 + > > 1 files changed, 5 insertions(+), 0 deletions(-) > > > > diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c > > index fbd0f1b..9bbd625 100644 > > --- a/drivers/net/davinci_emac.c > > +++ b/drivers/net/davinci_emac.c > > @@ -895,5 +895,10 @@ int davinci_emac_initialize(void) > > miiphy_register(phy[i].name, davinci_mii_phy_read, > > davinci_mii_phy_write); > > } > > + > > +#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ > > + defined(CONFIG_MACH_DAVINCI_DA850_EVM) > > + gen_auto_negotiate(active_phy_addr); > > +#endif > > return(1); > > } > > -- > > 1.7.4.1 > > > > ___ > > U-Boot mailing list > > U-Boot@lists.denx.de > > http://lists.denx.de/mailman/listinfo/u-boot > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] problem while making kernel up
Hello scott, The issue is solved by making baud rate correction. thank you manukumar signal-networks On Fri, 2012-06-01 at 12:15 -0500, Scott Wood wrote: > On 06/01/2012 05:10 AM, Manukumar wrote: > > Hello scott. > > > > I can able make the kernel up but it hangs after probing > > serial driver as shown below: > > > > It has to boot further but its not happenig.. > > I have attached the file i should get the log as this i also mentioned > > where it hangs... > > > > what may be the problem with this how could i fix this issue. > > This is getting off topic for the U-Boot list. Plus, it looks like > you're using a Freescale-provided kernel. Please e-mail > supp...@freescale.com, or try the latest upstream kernel and get help > from linuxppc-...@lists.ozlabs.org. > > But in this case, since this is your custom board, and it works on the > evaluation board, this is something you'll need to debug yourself (or > hire someone to debug). > > Given the place where it hangs, the obvious suggestion is to make sure > the baud rate and serial input clock are correct. > > -Scott > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/7] da850/omap-l138: Add support for NAND SPL
Hi Christian,
On Tue, Jun 05, 2012 at 16:56:01, Christian Riesch wrote:
> Hi,
>
> On Fri, Jun 1, 2012 at 4:30 PM, Prabhakar Lad wrote:
> > From: Lad, Prabhakar
> >
> > This patch adds support for NAND SPL on DA850/OMAP-L138.
> >
> > Signed-off-by: Lad, Prabhakar
> > Signed-off-by: Rajashekhara, Sudhakar
> > Signed-off-by: Hadli, Manjunath
> > ---
> > arch/arm/cpu/arm926ejs/davinci/spl.c | 13 ++-
> > include/configs/da850evm.h | 39
> > +
> > 2 files changed, 41 insertions(+), 11 deletions(-)
> >
> > diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c
> > b/arch/arm/cpu/arm926ejs/davinci/spl.c
> > index be397ce..53df581 100644
> > --- a/arch/arm/cpu/arm926ejs/davinci/spl.c
> > +++ b/arch/arm/cpu/arm926ejs/davinci/spl.c
> > @@ -79,12 +79,6 @@ void board_init_f(ulong dummy)
> >
> > void board_init_r(gd_t *id, ulong dummy)
> > {
> > -#ifdef CONFIG_SPL_NAND_LOAD
> > - nand_init();
> > - puts("Nand boot...\n");
> > - nand_boot();
> > -#endif
> > -#ifdef CONFIG_SPL_SPI_LOAD
> > mem_malloc_init(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN,
> > CONFIG_SYS_MALLOC_LEN);
> >
> > @@ -95,6 +89,13 @@ void board_init_r(gd_t *id, ulong dummy)
> > serial_init(); /* serial communications setup */
> > gd->have_console = 1;
> >
>
> This breaks the build for the cam_enc_4xx board and the hawkboard.
>
> You may do this initializations only if CONFIG_SPL_LIBCOMMON_SUPPORT
> is defined. Please test your patchset with ./MAKEALL -s davinci
>
Ok I'll fix this.
Thx,
--Prabhakar Lad
> Regards, Christian
>
> > +#ifdef CONFIG_SPL_NAND_LOAD
> > + puts("Nand boot...\n");
> > + nand_init();
> > + puts("Nand Initalized...\n");
> > + nand_boot();
> > +#endif
> > +#ifdef CONFIG_SPL_SPI_LOAD
> > puts("SPI boot...\n");
> > #ifdef CONFIG_SPL_MMC_LOAD
> > spl_mmc_load();
>
> [...]
>
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Re: [U-Boot] [PATCH] da850/omap-l138: enable SPI flash in RMII mode
Hi Christian, On Tue, Jun 05, 2012 at 15:38:53, Christian Riesch wrote: > Hi, > > On Fri, Jun 1, 2012 at 3:48 PM, Prabhakar Lad wrote: > > From: Rajashekhara, Sudhakar > > > > According to DA850/OMAP-L138 schematics, GP2[6] line has to be driven > > high for RMII mode to work. In RMII mode, SPI flash becomes un-usable. > > But during testing it was found out that, driving GP2[6] low also > > enables RMII and in this configuration SPI flash is also accessible. > > How about just removing all the code that is related to GP2[6]? > There's a pull-down resistor on the board and the pin is high > impedance by default. > Yes, this patch is not required I'll drop this patch. Thx, --Prabhakar Lad > Regards, Christian > > > > > Signed-off-by: Rajashekhara, Sudhakar > > Signed-off-by: Lad, Prabhakar > > Signed-off-by: Hadli, Manjunath > > --- > > board/davinci/da8xxevm/da850evm.c | 6 +++--- > > 1 files changed, 3 insertions(+), 3 deletions(-) > > > > diff --git a/board/davinci/da8xxevm/da850evm.c > > b/board/davinci/da8xxevm/da850evm.c > > index 004d5ad..82d707f 100644 > > --- a/board/davinci/da8xxevm/da850evm.c > > +++ b/board/davinci/da8xxevm/da850evm.c > > @@ -438,10 +438,10 @@ int rmii_hw_init(void) > > CONFIG_SYS_I2C_EXPANDER_ADDR); > > } > > > > - /* Set the output as high */ > > - temp = REG(GPIO_BANK2_REG_SET_ADDR); > > + /* Set the output as low */ > > + temp = REG(GPIO_BANK2_REG_CLR_ADDR); > > temp |= (0x01 << 6); > > - REG(GPIO_BANK2_REG_SET_ADDR) = temp; > > + REG(GPIO_BANK2_REG_CLR_ADDR) = temp; > > > > /* Set the GPIO direction as output */ > > temp = REG(GPIO_BANK2_REG_DIR_ADDR); > > -- > > 1.7.4.1 > > > > ___ > > U-Boot mailing list > > U-Boot@lists.denx.de > > http://lists.denx.de/mailman/listinfo/u-boot > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/7] da850/omap-l138: Add MMC support for DA850/OMAP-L138
Hi Christian,
On Tue, Jun 05, 2012 at 15:33:07, Christian Riesch wrote:
> Hi,
>
> On Fri, Jun 1, 2012 at 4:30 PM, Prabhakar Lad wrote:
> > From: Lad, Prabhakar
> >
> > This patch adds support for MMC/SD on DA850/OMAP-L138.
> >
> > Signed-off-by: Lad, Prabhakar
> > Signed-off-by: Rajashekhara, Sudhakar
> > Signed-off-by: Hadli, Manjunath
> > ---
> > arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c | 13 ++
> > arch/arm/include/asm/arch-davinci/hardware.h | 1 +
> > arch/arm/include/asm/arch-davinci/pinmux_defs.h | 3 ++
> > board/davinci/da8xxevm/da850evm.c | 28
> > +++
> > include/configs/da850evm.h | 14 +++
> > 5 files changed, 59 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
> > b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
> > index fa07fb5..a95e419 100644
> > --- a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
> > +++ b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
> > @@ -169,3 +169,16 @@ const struct pinmux_config emifa_pins_nor[] = {
> > { pinmux(12), 1, 6 }, /* EMA_A[1] */
> > { pinmux(12), 1, 7 }, /* EMA_A[0] */
> > };
> > +
> > +/* MMC0 pin muxer settings */
> > +const struct pinmux_config mmc0_pins[] = {
> > + /* GP0[11] is required for SD to work on Rev 3 EVMs */
> > + { pinmux(0), 8, 4 }, /* GP0[11] */
>
> Please move GP0[11] to the board specific file, e.g., add it to static
> const struct pinmux_config gpio_pins[] in
> board/davinci/da8xxevm/da850evm.c. Other boards might use other (or
> no) GPIOs for this purpose...
Ok.
Thx,
--Prabhakar Lad
>
> > + { pinmux(10), 2, 0 }, /* MMCSD0_CLK */
> > + { pinmux(10), 2, 1 }, /* MMCSD0_CMD */
> > + { pinmux(10), 2, 2 }, /* MMCSD0_DAT_0 */
> > + { pinmux(10), 2, 3 }, /* MMCSD0_DAT_1 */
> > + { pinmux(10), 2, 4 }, /* MMCSD0_DAT_2 */
> > + { pinmux(10), 2, 5 }, /* MMCSD0_DAT_3 */
> > + /* DA850 supports only 4-bit mode, remaining pins are not
> > configured */
> > +};
> > diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
> > b/arch/arm/include/asm/arch-davinci/hardware.h
> > index b145c6e..f6b7a2c 100644
> > --- a/arch/arm/include/asm/arch-davinci/hardware.h
> > +++ b/arch/arm/include/asm/arch-davinci/hardware.h
> > @@ -446,6 +446,7 @@ struct davinci_pllc_regs {
> > #define DAVINCI_SPI1_CLKID (cpu_is_da830() ? 2 : ASYNC3)
> > /* Clock IDs */
> > enum davinci_clk_ids {
> > + DAVINCI_MMCSD_CLKID = 2,
> > DAVINCI_SPI0_CLKID = 2,
> > DAVINCI_UART2_CLKID = 2,
> > DAVINCI_MMC_CLKID = 2,
> > diff --git a/arch/arm/include/asm/arch-davinci/pinmux_defs.h
> > b/arch/arm/include/asm/arch-davinci/pinmux_defs.h
> > index 07aceaa..c9ac697 100644
> > --- a/arch/arm/include/asm/arch-davinci/pinmux_defs.h
> > +++ b/arch/arm/include/asm/arch-davinci/pinmux_defs.h
> > @@ -48,4 +48,7 @@ extern const struct pinmux_config emifa_pins_cs4[1];
> > extern const struct pinmux_config emifa_pins_nand[12];
> > extern const struct pinmux_config emifa_pins_nor[43];
> >
> > +/* MMC pin muxer settings */
> > +extern const struct pinmux_config mmc0_pins[7];
> > +
> > #endif
> > diff --git a/board/davinci/da8xxevm/da850evm.c
> > b/board/davinci/da8xxevm/da850evm.c
> > index 82d707f..608c652 100644
> > --- a/board/davinci/da8xxevm/da850evm.c
> > +++ b/board/davinci/da8xxevm/da850evm.c
> > @@ -36,6 +36,11 @@
> > #include
> > #include
> >
> > +#ifdef CONFIG_DAVINCI_MMC
> > +#include
> > +#include
> > +#endif
> > +
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > #ifdef CONFIG_DRIVER_TI_EMAC
> > @@ -204,6 +209,23 @@ int misc_init_r(void)
> > return 0;
> > }
> >
> > +#ifdef CONFIG_DAVINCI_MMC
> > +static struct davinci_mmc mmc_sd0 = {
> > + .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
> > + .host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC
> > */
> > + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
> > + .version = MMC_CTLR_VERSION_2,
> > +};
> > +
> > +int board_mmc_init(bd_t *bis)
> > +{
> > + mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
> > +
> > + /* Add slot-0 to mmc subsystem */
> > + return davinci_mmc_init(bis, &mmc_sd0);
> > +}
> > +#endif
> > +
> > static const struct pinmux_config gpio_pins[] = {
> > #ifdef CONFIG_USE_NOR
> > /* GP0[11] is required for NOR to work on Rev 3 EVMs */
> > @@ -236,6 +258,9 @@ const struct pinmux_resource pinmuxes[] = {
> > PINMUX_ITEM(emifa_pins_nor),
> > #endif
> > PINMUX_ITEM(gpio_pins),
> > +#ifdef CONFIG_DAVINCI_MMC
> > + PINMUX_ITEM(mmc0_pins),
> > +#endif
> > };
> >
> > const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
> > @@ -246,6 +271,9 @@ const struct lpsc_resource lpsc[] = {
> > { DAVINCI_LPSC_EMAC }, /* image download */
> > { DAVINCI_LPSC_UART2 }, /* console */
> > { DAVINCI_LPSC_GPIO },
> > +#ifdef CONFIG_DAVINCI_MMC
> > + { D
Re: [U-Boot] [PATCH 7/7] da850/omap-l138: add support for direct NOR boot mode
Hi Tom, On Tue, Jun 05, 2012 at 04:02:01, Rini, Tom wrote: > On Fri, Jun 01, 2012 at 08:00:49PM +0530, Prabhakar Lad wrote: > > From: Lad, Prabhakar > > > > This patch adds support for direct NOR boot mode on da850/omap-l138. > > > > Define the CONFIG_DIRECT_NOR_BOOT macro along with CONFIG_USE_NOR in > > the DA850/OMAP-L138 configuration file to enable this feature. > > We should be using boards.cfg to add additional build targets that will > toggle CONFIG_DIRECT_NOR_BOOT and other cases where we can't have SW that > works in conflicting cases. Ok I'll add a new entry in boards.cfg. Thx, --Prabhakar Lad > > -- > Tom > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] da850/omap-l138: Enable auto negotiation in RMII mode
Hi Tom, On Tue, Jun 05, 2012 at 03:59:08, Rini, Tom wrote: > On Fri, Jun 01, 2012 at 07:04:37PM +0530, Prabhakar Lad wrote: > > From: Rajashekhara, Sudhakar > > > > On DA850/OMAP-L138 it was observed that in RMII mode, auto negotiation > > was not performed. This patch enables auto negotiation in RMII mode. > > Without this patch, EMAC initialization takes more time and sometimes > > tftp fails in RMII mode. > > > > Signed-off-by: Rajashekhara, Sudhakar > > Signed-off-by: Lad, Prabhakar > > Signed-off-by: Hadli, Manjunath > > --- > > drivers/net/davinci_emac.c |5 + > > 1 files changed, 5 insertions(+), 0 deletions(-) > > > > diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c > > index fbd0f1b..9bbd625 100644 > > --- a/drivers/net/davinci_emac.c > > +++ b/drivers/net/davinci_emac.c > > @@ -895,5 +895,10 @@ int davinci_emac_initialize(void) > > miiphy_register(phy[i].name, davinci_mii_phy_read, > > davinci_mii_phy_write); > > } > > + > > +#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ > > + defined(CONFIG_MACH_DAVINCI_DA850_EVM) > > + gen_auto_negotiate(active_phy_addr); > > +#endif > > Why not just check on CONFIG_DRIVER_TI_EMAC_USE_RMII ? Would it be harmful > to try and re-auto negotiate on some RMII hardware that already did it? Some of the phy's might not support auto negotiation, Not sure what will be the behavior on these phy's on enabling auto negotiation. So as to avoid this case this check is added. Thx, --Prabhakar Lad > > -- > Tom > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/7] da850/omap-l138: Add MMC support for DA850/OMAP-L138
Hi Tom, On Tue, Jun 05, 2012 at 03:58:03, Rini, Tom wrote: > On Fri, Jun 01, 2012 at 08:00:43PM +0530, Prabhakar Lad wrote: > > > From: Lad, Prabhakar > > > > This patch adds support for MMC/SD on DA850/OMAP-L138. > [snip] > > +/* SD/MMC */ > > +#define CONFIG_MMC > > +#define CONFIG_DAVINCI_MMC_SD1 > > +#define CONFIG_MMC_MBLOCK > > CONFIG_MMC_MBLOCK isn't used anywhere in code, remove it please. Ok. > > > +#define CONFIG_GENERIC_MMC > > +#define CONFIG_DAVINCI_MMC > > + > > +#ifdef CONFIG_MMC > > +#define CONFIG_DOS_PARTITION > > +#define CONFIG_CMD_EXT2 > > +#define CONFIG_CMD_FAT > > +#define CONFIG_CMD_MMC > > +#endif > > I'm not a fan of #define FOO, then checking right away for #ifdef FOO. > Just add a comment about these only been needed when you have MMC support so > it's clear to folks working from this as a template for their custom board > they can remove it. Ok I'll add a comment over here. Thx, --Prabhakar Lad > > -- > Tom > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v9 0/4] Kirkwood: add lschlv2 and lsxhl board support
Joe Hershberger schrieb: >Hi Prafulla, > >On Tue, Jun 5, 2012 at 4:36 PM, Michael Walle wrote: >> >> Hi Prafulla, >> >> Am Dienstag 05 Juni 2012, 23:33:13 schrieb Michael Walle: >>> Changes: >>> v9: >>> - rebase to marvell custodian tree, merged with wolfgangs master >> [..snip..] >> >> >> I had to merge your tree with wolfgangs master, because my second net >patch >> depends on the latest net patches by Joe. >> >> So please make sure you merge wolfgangs master with your tree before >applying >> these patches. > >It seems a better way to handle this is to rebase marvell onto WD's >master and push that to the marvell tree, allowing Michael to rebase >his patches onto that version. It seems there should not be a merge >here. that should work too. but my patcheset v9 should apply cleanly regardless of which way you choose. michael ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
