Re: [U-Boot] building u-boot inside buildroot
-Original Message- From: u-boot-boun...@lists.denx.de [mailto:u-boot- boun...@lists.denx.de] On Behalf Of Karl O. Pinc Sent: 30 July 2012 08:00 To: Sabri Altunbas Cc: u-boot@lists.denx.de Subject: Re: [U-Boot] building u-boot inside buildroot On 07/29/2012 07:43:00 AM, Sabri Altunbas wrote: I installed buildroot as my embedded linux environment. For first time I can build u-boot. But if i change a c-file and try to recompile u-boot. It doesn,t work. Buildroot doesn,t notice this changing and does nothing. Can anybody give me any hints please Hi Karl May you please describe the process you followed to build the u-boot and for which board? Regards... Prafulla . . . ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] dm: net: Fixup the armada100 FEC driver
-Original Message-
From: u-boot-boun...@lists.denx.de [mailto:u-boot-
boun...@lists.denx.de] On Behalf Of Marek Vasut
Sent: 28 July 2012 01:20
To: u-boot@lists.denx.de
Cc: Marek Vasut; Joe Hershberger; u-boot...@lists.denx.de
Subject: [U-Boot] [PATCH] dm: net: Fixup the armada100 FEC driver
Apply the following questionable adjustment to silence GCC.
armada100_fec.c: In function 'armdfec_send':
armada100_fec.c:589:2: warning: dereferencing type-punned pointer will
break strict-aliasing rules [-Wstrict-aliasing]
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Joe Hershberger joe.hershber...@ni.com
---
drivers/net/armada100_fec.c |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/net/armada100_fec.c b/drivers/net/armada100_fec.c
index d318a36..ed7cf20 100644
--- a/drivers/net/armada100_fec.c
+++ b/drivers/net/armada100_fec.c
@@ -565,7 +565,7 @@ static int armdfec_send(struct eth_device *dev,
void *dataptr, int datasize)
struct tx_desc *p_txdesc = darmdfec-p_txdesc;
void *p = (void *)dataptr;
int retry = PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS;
- u32 cmd_sts;
+ u32 cmd_sts, temp;
/* Copy buffer if it's misaligned */
if ((u32)dataptr 0x07) {
@@ -586,7 +586,8 @@ static int armdfec_send(struct eth_device *dev,
void *dataptr, int datasize)
p_txdesc-byte_cnt = datasize;
/* Apply send command using high priority TX queue */
- writel((u32)p_txdesc, regs-txcdp[TXQ]);
+ temp = (u32)regs-txcdp[TXQ];
+ writel((u32)p_txdesc, temp);
writel(SDMA_CMD_TXDL | SDMA_CMD_TXDH | SDMA_CMD_ERD, regs-
sdma_cmd);
/*
--
Acked-By: Prafulla Wadaskar prafu...@marvell.com
Regards...
Prafulla . . .
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Re: [U-Boot] [PATCH] km/common: remove printfs for i2c deblocking code
-Original Message-
From: u-boot-boun...@lists.denx.de [mailto:u-boot-
boun...@lists.denx.de] On Behalf Of Gerlando Falauto
Sent: 27 July 2012 20:28
To: u-boot@lists.denx.de
Cc: Holger Brunck
Subject: [U-Boot] [PATCH] km/common: remove printfs for i2c deblocking
code
From: Holger Brunck holger.bru...@keymile.com
This code will also be used before reallocation and during this time
we
are not allowed to do these printings.
Signed-off-by: Holger Brunck holger.bru...@keymile.com
---
board/keymile/common/common.c |3 ---
1 files changed, 0 insertions(+), 3 deletions(-)
diff --git a/board/keymile/common/common.c
b/board/keymile/common/common.c
index 1013f42..a90f112 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -151,7 +151,6 @@ int i2c_make_abort(void)
sda_state = get_sda();
if (scl_state sda_state) {
ret = 0;
- printf([INFO] i2c abort after %d clocks\n, i);
break;
}
}
@@ -159,8 +158,6 @@ int i2c_make_abort(void)
if (ret == 0)
for (i = 0; i 5; i++)
i2c_write_start_seq();
- else
- printf([ERROR] i2c abort failed\n);
/* respect stop setup time */
udelay(DELAY_ABORT_SEQ);
--
Acked-By: Prafulla Wadaskar prafu...@marvell.com
Regards...
Prafulla . . .
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Re: [U-Boot] [PATCH] dm: net: Fixup the armada100 FEC driver
Dear Prafulla Wadaskar, -Original Message- From: u-boot-boun...@lists.denx.de [mailto:u-boot- boun...@lists.denx.de] On Behalf Of Marek Vasut Sent: 28 July 2012 01:20 To: u-boot@lists.denx.de Cc: Marek Vasut; Joe Hershberger; u-boot...@lists.denx.de Subject: [U-Boot] [PATCH] dm: net: Fixup the armada100 FEC driver Apply the following questionable adjustment to silence GCC. armada100_fec.c: In function 'armdfec_send': armada100_fec.c:589:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] Signed-off-by: Marek Vasut ma...@denx.de Cc: Joe Hershberger joe.hershber...@ni.com [...] Joe, can you please pick this for -next (or -master already?) ? Acked-By: Prafulla Wadaskar prafu...@marvell.com Regards... Prafulla . . . Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] dm: mips: Fix lb60 WDT control
Dear Marek Vasut, Write the TSCR register via 32bit write instead of 16bit one. The register is 32bit wide and bit 16 is being set, triggering gcc overflow error and making the code broken. [...] Dan, can you please pick these (I didn't CC you ... sigh :/ ) ? Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Cosmetic doc typo fixes to the kwbimage feature docs
-Original Message- From: u-boot-boun...@lists.denx.de [mailto:u-boot- boun...@lists.denx.de] On Behalf Of Karl O. Pinc Sent: 27 July 2012 20:23 To: u-boot@lists.denx.de Subject: Re: [U-Boot] Cosmetic doc typo fixes to the kwbimage feature docs On 07/26/2012 11:15:32 PM, Karl O. Pinc wrote: Hi, I'm looking into the kirkwood docs and found some typos. I'm not proficent in git. If there's a problem with my git-age, or anything else, please let me know. I used git send-mail to send the above and it sent 2 emails (?), of which this was the first. The actual patch was the second email and it did not show up on this list, perhaps because this was my first post and needed moderation. Should I send the patch again? (Trivial stuff, but I've another doc fix waiting and wanted to get this right first.) You may send your v2 with this fix. Please send it first you your email-id just to validate you are sending right patches (before sending on mailing list). Regards... Prafulla . . . ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 0/6] tegra: Add NAND flash support
This series adds NAND flash support to Tegra and enables it on Seaboard. Included here is a proposed device tree binding with most of the properties private to nvidia,. The binding includes information about the NAND controller as well as the connected NAND device. The Seaboard has a Hynix HY27UF4G2B. The driver supports ECC-based access and uses DMA and NAND acceleration features of the Tegra SOC to provide access at reasonable speed. Changes in v2: - Add new patch to align default buffers in nand_base - Added comment about the behaviour of the 'resp' register - Call set_bus_width_page_size() at init to report errors earlier - Change set_bus_width_page_size() to return an error when needed - Change timing structure member to u32 to match device tree - Check for supported bus width in board_nand_init() - Fix tegra nand header file to remove BIT defines - Implement a dummy nand_select_chip() instead of nand_hwcontro() - Make nand_command() display an error on an unknown command - Minor code tidy-ups in driver for style - Move cache logic into a separate dma_prepare() function - Remove CMD_TRANS_SIZE_BYTESx enum - Remove space after casts - Remove use of 'register' variables - Rename struct nand_info to struct nand_drv to avoid nand_info_t confusion - Support 4096 byte page devices, drop 1024 and 2048 - Tidy up nand_waitfor_cmd_completion() logic - Update NAND binding to add nvidia, prefix - Use s32 for device tree integer values Changes in v3: - Add reg property for unit address (should be used for chip select) - Change note in fdt binding about the need for a hardware-specific binding - Fix up typos in fdt binding, and rename the file - Update fdt binding to make everything Nvidia-specific Changes in v4: - Align buffer length to cache line size in dma_prepare() - Fix Write Page 0x0 timeout with ECC error on 4.4.1 - Fix the issue that read_byte can read at most 4 times - Get some information from Read ID data instead of from device tree - In nand_command, set NAND_CMD_RNDOUT as unsupported command - Modify eccoob layout - Move to using CONFIG_SYS_NAND_SELF_INIT - Remove DEFAULT from comment because that function is not default - Remove fdt bindings related to page structure - Remove local read_buf and write_buf functions - Remove some fields in fdt_nand structure - Rename CONFIG_TEGRA2_NAND to CONFIG_TEGRA_NAND - Rename variables my_* as our_* - Use virt_to_phys() when filling address register Jim Lin (1): tegra: nand: Add Tegra NAND driver Simon Glass (5): nand: Try to align the default buffers tegra: Add NAND support to funcmux tegra: fdt: Add NAND controller binding and definitions tegra: fdt: Add NAND definitions to fdt tegra: Enable NAND on Seaboard arch/arm/cpu/tegra20-common/funcmux.c |7 + arch/arm/dts/tegra20.dtsi |7 + arch/arm/include/asm/arch-tegra20/funcmux.h|3 + arch/arm/include/asm/arch-tegra20/tegra20.h|1 + board/nvidia/dts/tegra20-seaboard.dts | 10 + .../nand/nvidia,tegra20-nand.txt | 53 + drivers/mtd/nand/Makefile |1 + drivers/mtd/nand/nand_base.c |3 +- drivers/mtd/nand/tegra_nand.c | 1026 drivers/mtd/nand/tegra_nand.h | 257 + include/configs/seaboard.h |9 + include/configs/tegra20-common.h |2 + include/fdtdec.h |1 + include/linux/mtd/nand.h |7 +- lib/fdtdec.c |1 + 15 files changed, 1384 insertions(+), 4 deletions(-) create mode 100644 doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt create mode 100644 drivers/mtd/nand/tegra_nand.c create mode 100644 drivers/mtd/nand/tegra_nand.h -- 1.7.7.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 3/6] tegra: fdt: Add NAND controller binding and definitions
Add a NAND controller along with a bindings file for review.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Update NAND binding to add nvidia, prefix
Changes in v3:
- Add reg property for unit address (should be used for chip select)
- Change note in fdt binding about the need for a hardware-specific binding
- Fix up typos in fdt binding, and rename the file
- Update fdt binding to make everything Nvidia-specific
Changes in v4:
- Remove fdt bindings related to page structure
arch/arm/dts/tegra20.dtsi |7 +++
.../nand/nvidia,tegra20-nand.txt | 53
2 files changed, 60 insertions(+), 0 deletions(-)
create mode 100644 doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index f95be58..d936b1e 100644
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -204,4 +204,11 @@
compatible = nvidia,tegra20-kbc;
reg = 0x7000e200 0x0078;
};
+
+ nand: nand-controller@70008000 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = nvidia,tegra20-nand;
+ reg = 0x70008000 0x100;
+ };
};
diff --git a/doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt
b/doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt
new file mode 100644
index 000..86ae408
--- /dev/null
+++ b/doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt
@@ -0,0 +1,53 @@
+NAND Flash
+--
+
+(there isn't yet a generic binding in Linux, so this describes what is in
+U-Boot. There should not be Linux-specific or U-Boot specific binding, just
+a binding that describes this hardware. But agreeing a binding in Linux in
+the absence of a driver may be beyond my powers.)
+
+The device node for a NAND flash device is as follows:
+
+Required properties :
+ - compatible : Should be manufacturer,device, nand-flash
+
+This node should sit inside its controller.
+
+
+Nvidia NAND Controller
+--
+
+The device node for a NAND flash controller is as follows:
+
+Optional properties:
+
+nvidia,wp-gpios : GPIO of write-protect line, three cells in the format:
+ phandle, parameter, flags
+nvidia,nand-width : bus width of the NAND device in bits
+
+ - nvidia,nand-timing : Timing parameters for the NAND. Each is in ns.
+ Order is: MAX_TRP_TREA, TWB, Max(tCS, tCH, tALS, tALH),
+ TWHR, Max(tCS, tCH, tALS, tALH), TWH, TWP, TRH, TADL
+
+ MAX_TRP_TREA is:
+ non-EDO mode: Max(tRP, tREA) + 6ns
+ EDO mode: tRP timing
+
+The 'reg' property should provide the chip select used by the flash chip.
+
+
+Example
+---
+
+nand-controller@0x70008000 {
+ compatible = nvidia,tegra20-nand;
+ #address-cells = 1;
+ #size-cells = 0;
+ nvidia,wp-gpios = gpio 59 0; /* PH3 */
+ nvidia,nand-width = 8;
+ nvidia,timing = 26 100 20 80 20 10 12 10 70;
+ nand@0 {
+ reg = 0;
+ compatible = hynix,hy27uf4g2b, nand-flash;
+ };
+};
--
1.7.7.3
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[U-Boot] [PATCH v4 1/6] nand: Try to align the default buffers
The NAND layer needs to use cache-aligned buffers by default. Towards this
goal. align the default buffers and their members according to the minimum
DMA alignment defined for the architecture.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add new patch to align default buffers in nand_base
drivers/mtd/nand/nand_base.c |3 ++-
include/linux/mtd/nand.h |7 ---
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index bfd668f..891af1f 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -2936,7 +2936,8 @@ int nand_scan_tail(struct mtd_info *mtd)
struct nand_chip *chip = mtd-priv;
if (!(chip-options NAND_OWN_BUFFERS))
- chip-buffers = kmalloc(sizeof(*chip-buffers), GFP_KERNEL);
+ chip-buffers = memalign(ARCH_DMA_MINALIGN,
+sizeof(*chip-buffers));
if (!chip-buffers)
return -ENOMEM;
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 82704de..dc839e7 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -391,9 +391,10 @@ struct nand_ecc_ctrl {
* consecutive order.
*/
struct nand_buffers {
- uint8_t ecccalc[NAND_MAX_OOBSIZE];
- uint8_t ecccode[NAND_MAX_OOBSIZE];
- uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
+ uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
+ uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
+ uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
+ ARCH_DMA_MINALIGN)];
};
/**
--
1.7.7.3
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[U-Boot] [PATCH v4 4/6] tegra: fdt: Add NAND definitions to fdt
Add a flash node to handle the NAND, including memory timings and
page / block size information.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Update NAND binding to add nvidia, prefix
Changes in v3:
- Add reg property for unit address (should be used for chip select)
- Update fdt binding to make everything Nvidia-specific
Changes in v4:
- Remove fdt bindings related to page structure
board/nvidia/dts/tegra20-seaboard.dts | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/board/nvidia/dts/tegra20-seaboard.dts
b/board/nvidia/dts/tegra20-seaboard.dts
index 3352539..25a63a0 100644
--- a/board/nvidia/dts/tegra20-seaboard.dts
+++ b/board/nvidia/dts/tegra20-seaboard.dts
@@ -153,4 +153,14 @@
0x1f04008a;
linux,fn-keymap = 0x05040002;
};
+
+ nand-controller@70008000 {
+ nvidia,wp-gpios = gpio 59 0; /* PH3 */
+ nvidia,width = 8;
+ nvidia,timing = 26 100 20 80 20 10 12 10 70;
+ nand@0 {
+ reg = 0;
+ compatible = hynix,hy27uf4g2b, nand-flash;
+ };
+ };
};
--
1.7.7.3
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[U-Boot] [PATCH v4 2/6] tegra: Add NAND support to funcmux
Add selection of NAND flash pins to the funcmux.
Signed-off-by: Simon Glass s...@chromium.org
Acked-by: Stephen Warren swar...@nvidia.com
---
arch/arm/cpu/tegra20-common/funcmux.c |7 +++
arch/arm/include/asm/arch-tegra20/funcmux.h |3 +++
2 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/tegra20-common/funcmux.c
b/arch/arm/cpu/tegra20-common/funcmux.c
index 8cfed64..b2129ad 100644
--- a/arch/arm/cpu/tegra20-common/funcmux.c
+++ b/arch/arm/cpu/tegra20-common/funcmux.c
@@ -234,6 +234,13 @@ int funcmux_select(enum periph_id id, int config)
}
break;
+ case PERIPH_ID_NDFLASH:
+ if (config == FUNCMUX_NDFLASH_ATC) {
+ pinmux_set_func(PINGRP_ATC, PMUX_FUNC_NAND);
+ pinmux_tristate_disable(PINGRP_ATC);
+ }
+ break;
+
default:
debug(%s: invalid periph_id %d, __func__, id);
return -1;
diff --git a/arch/arm/include/asm/arch-tegra20/funcmux.h
b/arch/arm/include/asm/arch-tegra20/funcmux.h
index 258f7b6..bd511db 100644
--- a/arch/arm/include/asm/arch-tegra20/funcmux.h
+++ b/arch/arm/include/asm/arch-tegra20/funcmux.h
@@ -57,6 +57,9 @@ enum {
/* Serial Flash configs */
FUNCMUX_SPI1_GMC_GMD = 0,
+
+ /* NAND flags */
+ FUNCMUX_NDFLASH_ATC = 0,
};
/**
--
1.7.7.3
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[U-Boot] [PATCH v4 6/6] tegra: Enable NAND on Seaboard
This enables NAND support for the Seaboard. Signed-off-by: Simon Glass s...@chromium.org --- Changes in v4: - Move to using CONFIG_SYS_NAND_SELF_INIT - Rename CONFIG_TEGRA2_NAND to CONFIG_TEGRA_NAND include/configs/seaboard.h |9 + include/configs/tegra20-common.h |2 ++ 2 files changed, 11 insertions(+), 0 deletions(-) diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index afc4a85..479af1a 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -105,4 +105,13 @@ #include tegra20-common-post.h +/* NAND support */ +#define CONFIG_CMD_NAND +#define CONFIG_TEGRA_NAND + +/* Max number of NAND devices */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* Somewhat oddly, the NAND base address must be a config option */ +#define CONFIG_SYS_NAND_BASE TEGRA20_NAND_BASE #endif /* __CONFIG_H */ diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 1c0d235..c9e8b6b 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -207,4 +207,6 @@ #define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_SPL_LDSCRIPT$(CPUDIR)/tegra20/u-boot-spl.lds +#define CONFIG_SYS_NAND_SELF_INIT + #endif /* __TEGRA20_COMMON_H */ -- 1.7.7.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 5/6] tegra: nand: Add Tegra NAND driver
From: Jim Lin ji...@nvidia.com A device tree is used to configure the NAND, including memory timings and block/pages sizes. If this node is not present or is disabled, then NAND will not be initialized. Signed-off-by: Jim Lin ji...@nvidia.com Signed-off-by: Simon Glass s...@chromium.org --- Changes in v2: - Added comment about the behaviour of the 'resp' register - Call set_bus_width_page_size() at init to report errors earlier - Change set_bus_width_page_size() to return an error when needed - Change timing structure member to u32 to match device tree - Check for supported bus width in board_nand_init() - Fix tegra nand header file to remove BIT defines - Implement a dummy nand_select_chip() instead of nand_hwcontro() - Make nand_command() display an error on an unknown command - Minor code tidy-ups in driver for style - Move cache logic into a separate dma_prepare() function - Remove CMD_TRANS_SIZE_BYTESx enum - Remove space after casts - Remove use of 'register' variables - Rename struct nand_info to struct nand_drv to avoid nand_info_t confusion - Support 4096 byte page devices, drop 1024 and 2048 - Tidy up nand_waitfor_cmd_completion() logic - Update NAND binding to add nvidia, prefix - Use s32 for device tree integer values Changes in v3: - Update fdt binding to make everything Nvidia-specific Changes in v4: - Align buffer length to cache line size in dma_prepare() - Fix Write Page 0x0 timeout with ECC error on 4.4.1 - Fix the issue that read_byte can read at most 4 times - Get some information from Read ID data instead of from device tree - In nand_command, set NAND_CMD_RNDOUT as unsupported command - Modify eccoob layout - Move to using CONFIG_SYS_NAND_SELF_INIT - Remove DEFAULT from comment because that function is not default - Remove local read_buf and write_buf functions - Remove some fields in fdt_nand structure - Rename variables my_* as our_* - Use virt_to_phys() when filling address register arch/arm/include/asm/arch-tegra20/tegra20.h |1 + drivers/mtd/nand/Makefile |1 + drivers/mtd/nand/tegra_nand.c | 1026 +++ drivers/mtd/nand/tegra_nand.h | 257 +++ include/fdtdec.h|1 + lib/fdtdec.c|1 + 6 files changed, 1287 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/nand/tegra_nand.c create mode 100644 drivers/mtd/nand/tegra_nand.h diff --git a/arch/arm/include/asm/arch-tegra20/tegra20.h b/arch/arm/include/asm/arch-tegra20/tegra20.h index 6750754..b2fb50e 100644 --- a/arch/arm/include/asm/arch-tegra20/tegra20.h +++ b/arch/arm/include/asm/arch-tegra20/tegra20.h @@ -39,6 +39,7 @@ #define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200) #define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300) #define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400) +#define TEGRA20_NAND_BASE (NV_PA_APB_MISC_BASE + 0x8000) #define TEGRA20_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380) #define TEGRA20_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400) #define TEGRA20_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800) diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 29dc20e..beb99ca 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -62,6 +62,7 @@ COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o +COBJS-$(CONFIG_TEGRA_NAND) += tegra_nand.o COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o endif diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c new file mode 100644 index 000..8c1de34 --- /dev/null +++ b/drivers/mtd/nand/tegra_nand.c @@ -0,0 +1,1026 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2011 NVIDIA Corporation www.nvidia.com + * (C) Copyright 2006 Detlev Zundel, d...@denx.de + * (C) Copyright 2006 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include common.h +#include asm/io.h +#include nand.h +#include asm/arch/clk_rst.h +#include asm/arch/clock.h +#include
Re: [U-Boot] [PATCH 1/2 v2] SDHC/MMC: fix the wrong infomation after change SD card
Hi, Andy Could you give some reason why eMMC device will be so slowed down by re-initialization? I think eMMC device is initialized only once, except it invoke 'mmc_init' many times. The workaround mmc rescan works when replace the card. But if one card is removed, then use mmcfinfo: there is no card present, while the previous card information is displayed, I don't' think it make sense. = mmc rescan MMC: no card present = mmcinfo MMC: no card present Device: FSL_SDHC Manufacturer ID: 2 OEM: 544d Name: SD04G Tran Speed: 5000 Rd Block Len: 512 SD version 2.0 High Capacity: Yes Capacity: 3.7 GiB Bus Width: 4-bit Best Regards Jerry Huang -Original Message- From: Andy Fleming [mailto:aflem...@gmail.com] Sent: Saturday, July 14, 2012 5:33 AM To: Huang Changming-R66093 Cc: u-boot@lists.denx.de; Marek Vasut Subject: Re: [PATCH 1/2 v2] SDHC/MMC: fix the wrong infomation after change SD card On Wed, Jul 11, 2012 at 4:29 AM, Huang Changming-R66093 r66...@freescale.com wrote: Hi, Andy, There is not any feedback for very long time, Could it be applied to the u-boot? I'm afraid I have to reject this patch. We need to find a better solution to the two problems: 1) We want to change cards and still have mmc commands work 2) We don't want eMMC devices to be slowed down by constantly re-initializing their cards. Normally, I would err on the side of #1, but there's a simple workaround. If you replace the card, execute mmc rescan, and the card will be reinitialized. Please let me know if that workaround doesn't work. I hope, in the future, we'll have some code which makes both possible, by being able to detect that a card has been changed, but for now I think the current system is reasonably satisfactory to both cases #1 and #2. Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] USB: EHCI: Initialize multiple USB controllers at once
-Original Message- From: Marek Vasut [mailto:marek.va...@gmail.com] Sent: Friday, July 27, 2012 5:26 PM To: u-boot@lists.denx.de Cc: Jim Lin; Wolfgang Denk; Tom Warren Subject: Re: [U-Boot] [PATCH 1/1] USB: EHCI: Initialize multiple USB controllers at once Wolfgang, Is there any chance to get this feature in after Stephen explained to you? I'll poke into it. Can we not get rid of the added ifdef, eg. by setting up the controller number to 1 for those that don't define CONFIG_USB_MULTI now (everyone) I assume you want me to add these in next patch. 1 . Use CONFIG_USB_MULTI, instead of CONFIG_USB_INIT_MULTI (current patch), 2. If CONFIG_USB_MULTI is not defined, then define CONFIG_USB_MAX_CONTROLLER_COUNT as 1. and adding some wrapping goo? Don't understand what you meant. Could you provide an example? Thanks. nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2] dm: ppc: Fixup cpu.c warning in mpc8xx
Dear Marek Vasut, In message 1343429832-24194-1-git-send-email-ma...@denx.de you wrote: cpu.c: In function ‘check_CPU’: cpu.c:256:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] Signed-off-by: Marek Vasut ma...@denx.de Cc: Wolfgang Denk w...@denx.de --- arch/powerpc/cpu/mpc8xx/cpu.c |3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) NOTE: This patch is likely to break something, it is only compile tested. NOTE2: Something is seriously wrong with my damned locale again :-/ Tested on TQM855MDCBAB7-T66.102 (MPC855T at 66 MHz) and TQM860LDB0A3-T50.202 (MPC860T at 50MHz). Tested-by: Wolfgang Denk w...@denx.de Acked-by: Wolfgang Denk w...@denx.de Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Wish not to seem, but to be, the best. - Aeschylus ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2] dm: ppc: Fixup cpu.c warning in mpc8xx
Dear Marek Vasut, In message 1343429832-24194-1-git-send-email-ma...@denx.de you wrote: cpu.c: In function ‘check_CPU’: cpu.c:256:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] Signed-off-by: Marek Vasut ma...@denx.de Cc: Wolfgang Denk w...@denx.de --- arch/powerpc/cpu/mpc8xx/cpu.c |3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) Applied to next branch, thanks. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Old programmers never die, they just branch to a new address. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Pull request: u-boot-mips/master for v2012.07
Dear daniel.schwierz...@gmail.com, In message 1343426851-2415-1-git-send-email-daniel.schwierz...@gmail.com you wrote: Dear Wolfgang, please pull a small fix for v2012.07 The following changes since commit c627faf637f5fe091bdb6846a52b16983e97b262: Prepare v2012.07-rc3 (2012-07-27 08:27:18 +0200) are available in the git repository at: git://git.denx.de/u-boot-mips.git master for you to fetch changes up to 8b425b3f8e345b07ce7f0005bb0222970bd3b248: MIPS: fix renaming of inca-swap-bytes to xway-swap-bytes (2012-07-27 23:44:24 +0200) Daniel Schwierzeck (1): MIPS: fix renaming of inca-swap-bytes to xway-swap-bytes Makefile | 2 +- tools/.gitignore | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) Applied, thanks. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de A little retrospection shows that although many fine, useful software systems have been designed by committees and built as part of multipart projects, those software systems that have excited passio- nate fans are those that are the products of one or a few designing minds, great designers. Consider Unix, APL, Pascal, Modula, the Smalltalk interface, even Fortran; and contrast them with Cobol, PL/I, Algol, MVS/370, and MS-DOS. - Fred Brooks, Jr. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] dwc_ahsata vs ahci
Hi Pavel, The ahci.c is a ahci driver using pci interface, while dwc_asata is not. u-boot don't have a pure ahci driver now, thus we have to reuse some ahci parts from ahci.c in dwc_asata.c. Thanks~~ Yours Terry -Original Message- From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Stefano Babic Sent: 2012?7?29? 14:56 To: Pavel Herrmann Cc: u-boot@lists.denx.de; u-boot...@lists.denx.de Subject: Re: [U-Boot] dwc_ahsata vs ahci On 28/07/2012 15:44, Pavel Herrmann wrote: Hi, Hi Pavel, While working on the DM project, I found out that there are two implementations of AHCI drivers - one in block/ahci.c, one in block/dwc_ahsata.c ooopppss ! what is the difference between them (apart from the obvious, ahci.c exposes SCSI API, dwc_ahsata exposes SATA API)? are there any problems that would prevent me from merging them? No, there are not evident reasons ! dwc_asata was inserted to add SATA support for Freescale MX5 family, and I missed that a similar driver was already in u-boot. dwc_ahsata was ported from Freescale's u-boot, and linked only for MX5 / MX6 SOCs. I think it is a very good idea to merge the two drivers (dwc_ahsata seems an updated version of the original driver), thanks to note this ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/7] powerpc/82xx: merge mgcoge.h and mgcoge3ne.h into km82xx.h
Dear Wolgfang Denk, On 07/27/2012 07:30 PM, Wolfgang Denk wrote: Dear Gerlando Falauto, In message1343402200-32020-4-git-send-email-gerlando.fala...@keymile.com you wrote: Since mgcoge and mgcoge3ne are the only km82xx boards, there is no need to keep them as separate .h config files. Therefore, make mgcoge3ne.h and mgcoge.h converge into a single km82xx.h file. Signed-off-by: Gerlando Falautogerlando.fala...@keymile.com --- boards.cfg |4 +- include/configs/km82xx.h| 149 +++ include/configs/mgcoge.h| 93 --- include/configs/mgcoge3ne.h | 93 --- 4 files changed, 151 insertions(+), 188 deletions(-) create mode 100644 include/configs/km82xx.h delete mode 100644 include/configs/mgcoge.h delete mode 100644 include/configs/mgcoge3ne.h Can you please try creating this patch with git format-patch with options -M and -C, please? I think git should do better to recognize this rename / merge of two files. I tried this but to no avail, the resulting patch is still the same. Same for patch number 4. I guess git gets confused by the fact that we are merging two files into one. What I could do is to split this commit so that, for instance, first we rename one of the files and then (on a separate commit) we move the content of one into the other. In any case, I believe git has no notion of operations like a file being embedded into another. I think the best we could do is to put such changes into a separate commit and mark it explicitly (perhaps including a sed script in the commit message) so that they can be automated in case of a rebase. Question is, is this really worth the effort? Is there a common practice for such reworks? Thank you, Gerlando ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot-DM] dwc_ahsata vs ahci
Dear Lv Terry-R65388, Hi Pavel, The ahci.c is a ahci driver using pci interface, while dwc_asata is not. u-boot don't have a pure ahci driver now, thus we have to reuse some ahci parts from ahci.c in dwc_asata.c. Ok, I think we can unify that eventually. Thanks~~ Yours Terry -Original Message- From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Stefano Babic Sent: 2012?7?29? 14:56 To: Pavel Herrmann Cc: u-boot@lists.denx.de; u-boot...@lists.denx.de Subject: Re: [U-Boot] dwc_ahsata vs ahci On 28/07/2012 15:44, Pavel Herrmann wrote: Hi, Hi Pavel, While working on the DM project, I found out that there are two implementations of AHCI drivers - one in block/ahci.c, one in block/dwc_ahsata.c ooopppss ! what is the difference between them (apart from the obvious, ahci.c exposes SCSI API, dwc_ahsata exposes SATA API)? are there any problems that would prevent me from merging them? No, there are not evident reasons ! dwc_asata was inserted to add SATA support for Freescale MX5 family, and I missed that a similar driver was already in u-boot. dwc_ahsata was ported from Freescale's u-boot, and linked only for MX5 / MX6 SOCs. I think it is a very good idea to merge the two drivers (dwc_ahsata seems an updated version of the original driver), thanks to note this ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot-DM mailing list u-boot...@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot-dm Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] km/common: remove printfs for i2c deblocking code
Hello Gerlando, On 27.07.2012 16:58, Gerlando Falauto wrote: From: Holger Brunckholger.bru...@keymile.com This code will also be used before reallocation and during this time we are not allowed to do these printings. Signed-off-by: Holger Brunckholger.bru...@keymile.com --- board/keymile/common/common.c |3 --- 1 files changed, 0 insertions(+), 3 deletions(-) Acked-by: Heiko Schocherh...@denx.de @Prafulla: Is it OK for you, if I pick this patch up to my i2c tree? bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] powerdown can't work (mx28)
Hi: If the voltage of battery is below 3.6v, the system still can be startup, and do you think it is right? The function mx28_powerdown is meaningless. At 2012-07-26 09:31:20,alex laub...@163.com wrote: The poweroff function in kernel can work. The similar code can be found in bootlet from FSL, and it also can work . After poweroff the system, press pswitch key and the board can startup. At 2012-07-26 04:42:28,Marek Vasut marek.va...@gmail.com wrote: Dear alex, Hi: I find that mx28_powerdown function can't power down mx28, and continue to load kernel I don't know whether this issue is on your side. My board is changed frommx28evk. Was mx28_powerdown function tested? Best I think this question was here already. What do you expect that function to do? It won't do anything like ACPI powerdown you know from PC (it's not even possible on the hardware I guess). The function should probably be adjusted and some for(;;); added at the end, but that's probably it. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] dm: mips: Fix lb60 WDT control
2012/7/30 Marek Vasut ma...@denx.de: Dear Marek Vasut, Write the TSCR register via 32bit write instead of 16bit one. The register is 32bit wide and bit 16 is being set, triggering gcc overflow error and making the code broken. [...] Dan, can you please pick these (I didn't CC you ... sigh :/ ) ? Sure. I'm still waiting for some comments from Xiangfu. Best regards, Daniel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] cfi: Problem with Intel Strata 28F320 flash
Hello Gerlando, On 27.07.2012 16:11, Gerlando Falauto wrote: Hi all, On 03/09/2011 02:21 PM, Detlev Zundel wrote: Hi Heiko, Maybe a way to go ... more comments? Below a patch, which introduces a function, which checks for protection bugfixes, and if no bugfix is found the old code is executed. Just a fast RFC patch. bye, Heiko [...] Can't we introduce a field chip_quirk in flash_info_t, and upon flash enumeration check for the specific chip version and for example put a CFI_QUIRK_PROTECT in it for this chip. The core code can then check for this flag and call functions appropriately. In other words, why not introduce a generic infrastructure for handling chip quirks that may need different handling for other functions also. Cheers Detlev Have there been (since the original posting) other instances of flash parts requiring quirks (like the original one introduced by Philippe De Muyter for the Numonyx chip)? I don´t know ... Is there any ongoing activity on this or any other reason to suggest it might be necessary to introduce such generic infrastructure (like the one in linux mtd, the way I understand it)? I have no current activity on this ... If that's not the case, wouldn't Heicho's original patch in this thread (http://patchwork.ozlabs.org/patch/86063/) just be good enough for the purpose? I am here on Detlevs side, but if it is currently only one usecase here, maybe my patch is enough ... Stefan? Detlev? bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] hawkboard: Fix SPL Nand driver misconfiguration
hi Wolfgang, On Fri Jul 27, 2012 at 03:16:15PM +0530, Sughosh Ganu wrote: On Fri Jul 27, 2012 at 01:51:53PM +0530, Linu Cherian wrote: Hawkboard was using the wrong nand_read_page version for SPL image. As a side effect, the u-boot image loaded by the SPL from nand was getting corrupted. Enable CONFIG_SYS_NAND_HW_ECC_OOBFIRST to select the correct nand_read_page algorithm for SPL. Signed-off-by: Linu Cherian linucher...@gmail.com Acked-by: Sughosh Ganu urwithsugh...@gmail.com Tom, since this is a bug fix, can this go to the 2012.07 release. Did not get any response from Tom, so if it's not too late, can this patch be applied to the master for the 2012.07 release. It is a bugfix. -sughosh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] cfi: Problem with Intel Strata 28F320 flash
Hi Heiko, On Monday 30 July 2012 13:07:07 Heiko Schocher wrote: Have there been (since the original posting) other instances of flash parts requiring quirks (like the original one introduced by Philippe De Muyter for the Numonyx chip)? I don´t know ... Is there any ongoing activity on this or any other reason to suggest it might be necessary to introduce such generic infrastructure (like the one in linux mtd, the way I understand it)? I have no current activity on this ... If that's not the case, wouldn't Heicho's original patch in this thread (http://patchwork.ozlabs.org/patch/86063/) just be good enough for the purpose? I am here on Detlevs side, but if it is currently only one usecase here, maybe my patch is enough ... Stefan? Detlev? I'm just back from vacation and I'll look into this in a few days. Promise! Viele Grüße, Stefan -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: off...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/8 V7] EXYNOS5: Enable I2C support
Hi, On Tue, Jul 24, 2012 at 8:23 AM, Rajeshwari Shinde rajeshwar...@samsung.com wrote: This patch set enables I2C support for EXYNOS5. This patchset modifies the s3c24x0 I2C driver to use same for EXYNOS5. Multichannel support has been added to the s3c24x0 I2C driver. s3c24x0_i2c struct has been moved to a common place as it can used by different SOC's. Changes in V2: - Incorporated review comments from Simon Glass. - Aligned the pinmux functionality as per latest comments Changes in V3: - Incorporated review comments from Joonyoung Shim for I2C driver. Changes in V4: - Resolved build error for S3C2410. Changes in V5: - Pinmux setting moved to board file. - Multi Bus I2C offset calculation done based on EXYNOS_I2C_SPACE. - Peripheral id calculation removed from i2c driver. Changes in V6: - Incorporated review comments from Simon Glass. Changes in V7: - Incorporated review comments from Joonyoung Shim. This series looks good to me (still). Regards, Simon Rajeshwari Shinde (8): EXYNOS: CLK: Add i2c clock EXYNOS: Add I2C base address. EXYNOS5: define EXYNOS5_I2C_SPACING EXYNOS: PINMUX: Add pinmux support for I2C I2C: Move struct s3c24x0_i2c to a common place. I2C: Modify the I2C driver for EXYNOS5 I2C: Add support for Multi channel CONFIG: SMDK5250: I2C: Enable I2C arch/arm/cpu/armv7/exynos/clock.c | 33 arch/arm/cpu/armv7/exynos/pinmux.c | 52 +++ arch/arm/include/asm/arch-exynos/clk.h |1 + arch/arm/include/asm/arch-exynos/cpu.h |5 + arch/arm/include/asm/arch-exynos/periph.h |8 + arch/arm/include/asm/arch-s3c24x0/s3c24x0.h | 10 -- board/samsung/smdk5250/smdk5250.c | 30 - drivers/i2c/s3c24x0_i2c.c | 221 +- drivers/i2c/s3c24x0_i2c.h | 33 include/configs/smdk5250.h | 10 ++ 10 files changed, 315 insertions(+), 88 deletions(-) create mode 100644 drivers/i2c/s3c24x0_i2c.h -- 1.7.4.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] USB: EHCI: Initialize multiple USB controllers at once
Dear Jim Lin, -Original Message- From: Marek Vasut [mailto:marek.va...@gmail.com] Sent: Friday, July 27, 2012 5:26 PM To: u-boot@lists.denx.de Cc: Jim Lin; Wolfgang Denk; Tom Warren Subject: Re: [U-Boot] [PATCH 1/1] USB: EHCI: Initialize multiple USB controllers at once Wolfgang, Is there any chance to get this feature in after Stephen explained to you? I'll poke into it. Can we not get rid of the added ifdef, eg. by setting up the controller number to 1 for those that don't define CONFIG_USB_MULTI now (everyone) I assume you want me to add these in next patch. 1 . Use CONFIG_USB_MULTI, instead of CONFIG_USB_INIT_MULTI (current patch), 2. If CONFIG_USB_MULTI is not defined, then define CONFIG_USB_MAX_CONTROLLER_COUNT as 1. Yes, is that a problem? Aka. have this always enabled and don't treat not having multiple controllers as a special case. and adding some wrapping goo? Don't understand what you meant. Could you provide an example? Just don't treat having 1 controller as a special case, that's all I meant. Thanks. nvpublic Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/7] powerpc/82xx: merge mgcoge.h and mgcoge3ne.h into km82xx.h
Dear Gerlando Falauto, In message 50164f3a.6050...@keymile.com you wrote: boards.cfg |4 +- include/configs/km82xx.h| 149 +++ include/configs/mgcoge.h| 93 --- include/configs/mgcoge3ne.h | 93 --- 4 files changed, 151 insertions(+), 188 deletions(-) create mode 100644 include/configs/km82xx.h delete mode 100644 include/configs/mgcoge.h delete mode 100644 include/configs/mgcoge3ne.h Can you please try creating this patch with git format-patch with options -M and -C, please? I think git should do better to recognize this rename / merge of two files. I tried this but to no avail, the resulting patch is still the same. Same for patch number 4. I guess git gets confused by the fact that we are merging two files into one. No, git can handle this pretty well if you tell it what you are doing. I just retested this; the result is: --- file.1| 64 --- file.2 = file.common | 64 +++ 2 files changed, 64 insertions(+), 64 deletions(-) delete mode 100644 file.1 rename file.2 = file.common (63%) What I could do is to split this commit so that, for instance, first we rename one of the files and then (on a separate commit) we move the content of one into the other. No, this can and should be done in a single commit, for example like this: 1. run: git mv include/configs/mgcoge.h include/configs/km82xx.h 2. merge include/configs/mgcoge3ne.h into include/configs/km82xx.h 3. run: git rm include/configs/mgcoge3ne.h git format-patch -M -C will then recognize what you did. Question is, is this really worth the effort? Is there a common practice for such reworks? Yes, if possible we want that git tracks such renames / merges. And here it seems easily possible. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de You see things; and you say ``Why?'' But I dream things that never were; and I say ``Why not?'' - George Bernard Shaw _Back to Methuselah_ (1921) pt. 1, act 1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] multichannel mmc strangeness on omap
Does anyone have any experience enabling the second or third mmc
channels in u-boot on an omap3 board?
I used the feature successfully a couple of years ago on Overo, but of
course there have been many changes in the mmc code since then.
Here's what I tried for overo with the current head of tree:
diff --git a/board/overo/overo.c b/board/overo/overo.c
index f973870..51315b3 100644
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -404,6 +404,7 @@ int board_eth_init(bd_t *bis)
int board_mmc_init(bd_t *bis)
{
omap_mmc_init(0, 0, 0);
+ omap_mmc_init(2, 0, 0);
return 0;
}
#endif
The result is a hang after printing: MMC: OMAP SD/MMC 0, SD/MMC 1
After adding a few printf's, it seems that the crash/hang is occurring
when calling env_relocate_spec in env_nand.c, which of course is
completely unrelated code!
Just for grins I tried enabling the second mmc channel instead (i.e
change omap_mmc_init(2, 0, 0) to omap_mmc_init(1, 0, 0)).
This worked as expected. I also tried enabling all three, which
resulted in the same crash. So enabling the third mmc channel seems
to be the issue.
Before I start debugging I thought I would check to see if anyone else
has seen this or has any theories as to why it is happening.
Steve
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Re: [U-Boot] [PATCH] hawkboard: Fix SPL Nand driver misconfiguration
On Fri, Jul 27, 2012 at 03:16:15PM +0530, Sughosh Ganu wrote: On Fri Jul 27, 2012 at 01:51:53PM +0530, Linu Cherian wrote: Hawkboard was using the wrong nand_read_page version for SPL image. As a side effect, the u-boot image loaded by the SPL from nand was getting corrupted. Enable CONFIG_SYS_NAND_HW_ECC_OOBFIRST to select the correct nand_read_page algorithm for SPL. Signed-off-by: Linu Cherian linucher...@gmail.com Acked-by: Sughosh Ganu urwithsugh...@gmail.com Tom, since this is a bug fix, can this go to the 2012.07 release. Acked-by: Tom Rini tr...@ti.com Wolfgang, please take this for the release, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] multichannel mmc strangeness on omap
On Mon, Jul 30, 2012 at 06:36:24AM -0700, Steve Sakoman wrote:
Does anyone have any experience enabling the second or third mmc
channels in u-boot on an omap3 board?
I used the feature successfully a couple of years ago on Overo, but of
course there have been many changes in the mmc code since then.
Here's what I tried for overo with the current head of tree:
diff --git a/board/overo/overo.c b/board/overo/overo.c
index f973870..51315b3 100644
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -404,6 +404,7 @@ int board_eth_init(bd_t *bis)
int board_mmc_init(bd_t *bis)
{
omap_mmc_init(0, 0, 0);
+ omap_mmc_init(2, 0, 0);
return 0;
}
#endif
The result is a hang after printing: MMC: OMAP SD/MMC 0, SD/MMC 1
After adding a few printf's, it seems that the crash/hang is occurring
when calling env_relocate_spec in env_nand.c, which of course is
completely unrelated code!
I've spent some time scratching my head against a hang in the same spot,
on am335x. I only have seen it when booting from NAND (same image from
MMC or UART is fine). Further, it only showed up when a change was made
in another driver which isn't even entered before the hang.
--
Tom
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Re: [U-Boot] [PATCH 3/7] powerpc/82xx: merge mgcoge.h and mgcoge3ne.h into km82xx.h
On 07/30/2012 03:00 PM, Wolfgang Denk wrote:
Dear Gerlando Falauto,
In message50164f3a.6050...@keymile.com you wrote:
boards.cfg |4 +-
include/configs/km82xx.h| 149
+++
include/configs/mgcoge.h| 93 ---
include/configs/mgcoge3ne.h | 93 ---
4 files changed, 151 insertions(+), 188 deletions(-)
create mode 100644 include/configs/km82xx.h
delete mode 100644 include/configs/mgcoge.h
delete mode 100644 include/configs/mgcoge3ne.h
Can you please try creating this patch with git format-patch with
options -M and -C, please? I think git should do better to
recognize this rename / merge of two files.
I tried this but to no avail, the resulting patch is still the same.
Same for patch number 4.
I guess git gets confused by the fact that we are merging two files into
one.
No, git can handle this pretty well if you tell it what you are doing.
I just retested this; the result is:
---
file.1| 64
---
file.2 = file.common | 64
+++
2 files changed, 64 insertions(+), 64 deletions(-)
delete mode 100644 file.1
rename file.2 = file.common (63%)
What I could do is to split this commit so that, for instance,
first we rename one of the files and then (on a separate commit) we move
the content of one into the other.
No, this can and should be done in a single commit, for example like this:
1. run: git mv include/configs/mgcoge.h include/configs/km82xx.h
2. merge include/configs/mgcoge3ne.h into include/configs/km82xx.h
3. run: git rm include/configs/mgcoge3ne.h
git format-patch -M -C will then recognize what you did.
The way I understand it, such renaming information is built on the fly
while building the patch (like you're suggesting, it's a parameter to
git format-patch, not to the commit itself).
In other words, a renaming is just a remove and an add (see [1]):
--
Git has a rename command git mv, but that is just for convenience. The
effect is indistinguishable from removing the file and adding another
with different name and the same content.
--
As a matter of fact, I am able to get the renaming recognized when
committing:
---
[detached HEAD 85129b8] powerpc/82xx: 1of2 move km/km82xx-common.h
within km82xx.h
1 files changed, 148 insertions(+), 0 deletions(-)
rename include/configs/{km/km82xx-common.h = km82xx.h} (71%)
---
However, I've been struggling to get this same kind of message through
git-format-patch. No way, I don't know why. I tried with -M, -M -C,
-M10%, adding [diff]\n renames = copies to ~/.gitconfig, with both
versions below, nothing. Detected as a rename at commit time, it's a
plain delete/create commit at patch creation time.
$ git --version
git version 1.7.1
$ ~/git/bin-wrappers/git --version
git version 1.7.11.3
Could you please share what GIT version you're running?
Question is, is this really worth the effort?
Is there a common practice for such reworks?
Yes, if possible we want that git tracks such renames / merges.
And here it seems easily possible.
Could you please try applying the patch to your tree (namely 3 and 4),
and then build it again by running:
git-format-patch -M30% -C
It should get detected as a rename anyway (I mean, even if applied as a
whole delete/add).
In any case, I have no clue whether git would be able to correctly (i.e.
intelligently) apply such patch to a slightly different tree (e.g.
through cherry-pick or rebase).
So for instance, in your example above, what if file.1 (whose contents
is anyway moved into file.common, regardless of rename detection) is
slightly different?
Would the patch fail? Or worse, would it silently apply by just deleting
the new file and applying the old contents (verbatim from the patch)?
I'm strongly convinced that if we want to track such changes for what
they are (code moving) so that they can be easily re-applied, we
should mark this explicitly. Even at the cost of creating multiple
patches if necessary. Since git isn't able to figure it out by itself,
the only way I can think of doing this is splitting the commit into 3 parts:
1) preparation work, adding #include statements to the old files
2) automated code moving through a script like the following (and
including it in the commit message itself)
3) cleanup changes
powerpc/82xx: 2of3 merge mgcoge.h and mgcoge3ne.h into km82xx.h
Since mgcoge and mgcoge3ne are the only km82xx boards, there is no
need to keep them as separate .h config files.
Therefore, make mgcoge3ne.h and mgcoge.h converge into a single
km82xx.h file.
Step 2 of 3: substitute include files through the following script:
INCLUDE_STMT='#include mgcoge.h'
Re: [U-Boot] building u-boot inside buildroot
On 07/30/2012 01:28:45 AM, Prafulla Wadaskar wrote: -Original Message- From: u-boot-boun...@lists.denx.de [mailto:u-boot- boun...@lists.denx.de] On Behalf Of Karl O. Pinc Sent: 30 July 2012 08:00 To: Sabri Altunbas Cc: u-boot@lists.denx.de Subject: Re: [U-Boot] building u-boot inside buildroot On 07/29/2012 07:43:00 AM, Sabri Altunbas wrote: I installed buildroot as my embedded linux environment. For first time I can build u-boot. But if i change a c-file and try to recompile u-boot. It doesn,t work. Buildroot doesn,t notice this changing and does nothing. Can anybody give me any hints please Hi Karl May you please describe the process you followed to build the u-boot and for which board? This question is for Sabri, right? Karl k...@meme.com Free Software: You don't pay back, you pay forward. -- Robert A. Heinlein ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] dm: net: Fixup the armada100 FEC driver
Hi Marek, On Mon, Jul 30, 2012 at 1:35 AM, Marek Vasut ma...@denx.de wrote: Dear Prafulla Wadaskar, -Original Message- From: u-boot-boun...@lists.denx.de [mailto:u-boot- boun...@lists.denx.de] On Behalf Of Marek Vasut Sent: 28 July 2012 01:20 To: u-boot@lists.denx.de Cc: Marek Vasut; Joe Hershberger; u-boot...@lists.denx.de Subject: [U-Boot] [PATCH] dm: net: Fixup the armada100 FEC driver Apply the following questionable adjustment to silence GCC. armada100_fec.c: In function 'armdfec_send': armada100_fec.c:589:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] Signed-off-by: Marek Vasut ma...@denx.de Cc: Joe Hershberger joe.hershber...@ni.com [...] Joe, can you please pick this for -next (or -master already?) ? OK... I figured this was just an RFC, since it was sent to the u-boot-dm list. I'll pull it into master after release. Thanks, -Joe ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] dm: net: Fixup the armada100 FEC driver
Dear Joe Hershberger, Hi Marek, On Mon, Jul 30, 2012 at 1:35 AM, Marek Vasut ma...@denx.de wrote: Dear Prafulla Wadaskar, -Original Message- From: u-boot-boun...@lists.denx.de [mailto:u-boot- boun...@lists.denx.de] On Behalf Of Marek Vasut Sent: 28 July 2012 01:20 To: u-boot@lists.denx.de Cc: Marek Vasut; Joe Hershberger; u-boot...@lists.denx.de Subject: [U-Boot] [PATCH] dm: net: Fixup the armada100 FEC driver Apply the following questionable adjustment to silence GCC. armada100_fec.c: In function 'armdfec_send': armada100_fec.c:589:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] Signed-off-by: Marek Vasut ma...@denx.de Cc: Joe Hershberger joe.hershber...@ni.com [...] Joe, can you please pick this for -next (or -master already?) ? OK... I figured this was just an RFC, since it was sent to the u-boot-dm list. That was a bad choice to cross post it to both MLs ... and I was already told so, quite a lot. I'll pull it into master after release. Thanks, -Joe Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/7] powerpc/82xx: merge mgcoge.h and mgcoge3ne.h into km82xx.h
Dear Gerlando Falauto,
In message 5016a093.6040...@keymile.com you wrote:
The way I understand it, such renaming information is built on the fly
while building the patch (like you're suggesting, it's a parameter to
git format-patch, not to the commit itself).
Yes, and I fail to understand where your problems could be.
However, I've been struggling to get this same kind of message through
git-format-patch. No way, I don't know why. I tried with -M, -M -C,
-M10%, adding [diff]\n renames = copies to ~/.gitconfig, with both
versions below, nothing. Detected as a rename at commit time, it's a
plain delete/create commit at patch creation time.
I see this (doing it all manually for testing):
- patch -p1 /tmp/patch
- git rm include/configs/mgcoge.h include/configs/mgcoge3ne.h
- git add include/configs/km82xx.h
- git commit -s -m 'test 1'
- git format-patch -M -C --stdout HEAD^ /tmp/patch
- less /tmp/patch
From 1d9ce92a542d139b78291fb4e437e538d647d55b Mon Sep 17 00:00:00 2001
From: Wolfgang Denk w...@denx.de
Date: Mon, 30 Jul 2012 17:57:53 +0200
Subject: [PATCH] test 1
Signed-off-by: Wolfgang Denk w...@denx.de
---
include/configs/{mgcoge3ne.h = km82xx.h} | 95 ++---
include/configs/mgcoge.h | 93
2 files changed, 74 insertions(+), 114 deletions(-)
rename include/configs/{mgcoge3ne.h = km82xx.h} (55%)
delete mode 100644 include/configs/mgcoge.h
...
Oops, I forgot to git add boards.cfg here, but for this test it
makes no difference.
$ git --version
git version 1.7.1
$ ~/git/bin-wrappers/git --version
git version 1.7.11.3
Could you please share what GIT version you're running?
- git --version
git version 1.7.10.4
That's what I get from the normal Fedora 17 installation.
Could you please try applying the patch to your tree (namely 3 and 4),
and then build it again by running:
git-format-patch -M30% -C
See above...
In any case, I have no clue whether git would be able to correctly (i.e.
intelligently) apply such patch to a slightly different tree (e.g.
through cherry-pick or rebase).
So for instance, in your example above, what if file.1 (whose contents
is anyway moved into file.common, regardless of rename detection) is
slightly different?
It doesn't matter. If there are conflicts, and these can be resolved,
it works just the same.
I'm strongly convinced that if we want to track such changes for what
they are (code moving) so that they can be easily re-applied, we
should mark this explicitly. Even at the cost of creating multiple
patches if necessary. Since git isn't able to figure it out by itself,
No, on contrary. This is basicly an atomic change, and we should not
artificially split it. git should have no problems with such actions,
they are really not special in any way.
the only way I can think of doing this is splitting the commit into 3 parts:
No, please don't.
Since mgcoge and mgcoge3ne are the only km82xx boards, there is no
need to keep them as separate .h config files.
Therefore, make mgcoge3ne.h and mgcoge.h converge into a single
km82xx.h file.
Step 2 of 3: substitute include files through the following script:
INCLUDE_STMT='#include mgcoge.h'
INCLUDED=include/configs/mgcoge.h
INCLUDING=include/configs/km82xx.h
Argh No, this is not what we're going to do.
Best regards,
Wolfgang Denk
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Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
All a hacker needs is a tight PUSHJ, a loose pair of UUOs, and a warm
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[U-Boot] [PATCH 1/3] DaVinci DA8xx: tidy up clock ID definition
Tidy up the clock IDs defined for the DA8xx SOCs. With this new structure in
place, it is clear how to define new clock IDs, and how these map to the
numbers presented in the technical reference manual.
Signed-off-by: Laurence Withers lwith...@guralp.com
Cc: Prabhakar Lad prabhakar.cse...@gmail.com
---
arch/arm/include/asm/arch-davinci/hardware.h | 53 +++---
1 files changed, 39 insertions(+), 14 deletions(-)
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
b/arch/arm/include/asm/arch-davinci/hardware.h
index b145c6e..dac43bb 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -441,21 +441,46 @@ struct davinci_pllc_regs {
#define davinci_pllc1_regs ((struct davinci_pllc_regs
*)DAVINCI_PLL_CNTRL1_BASE)
#define DAVINCI_PLLC_DIV_MASK 0x1f
-#define ASYNC3 get_async3_src()
-#define PLL1_SYSCLK2 ((1 16) | 0x2)
-#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? 2 : ASYNC3)
-/* Clock IDs */
+/*
+ * A clock ID is a 32-bit number where bit 16 represents the PLL controller
+ * (clear is PLLC0, set is PLLC1) and the low 16 bits represent the divisor,
+ * counting from 1. Clock IDs may be passed to clk_get().
+ */
+
+/* flags to select PLL controller */
+#define DAVINCI_PLLC0_FLAG (0)
+#define DAVINCI_PLLC1_FLAG (1 16)
+
enum davinci_clk_ids {
- DAVINCI_SPI0_CLKID = 2,
- DAVINCI_UART2_CLKID = 2,
- DAVINCI_MMC_CLKID = 2,
- DAVINCI_MDIO_CLKID = 4,
- DAVINCI_ARM_CLKID = 6,
- DAVINCI_PLLM_CLKID = 0xff,
- DAVINCI_PLLC_CLKID = 0x100,
- DAVINCI_AUXCLK_CLKID = 0x101
+ /*
+* Clock IDs for PLL outputs. Each may be switched on/off independently,
+* and each may map to one or more peripherals.
+*/
+ DAVINCI_PLL0_SYSCLK2= DAVINCI_PLLC0_FLAG | 2,
+ DAVINCI_PLL0_SYSCLK4= DAVINCI_PLLC0_FLAG | 4,
+ DAVINCI_PLL0_SYSCLK6= DAVINCI_PLLC0_FLAG | 6,
+ DAVINCI_PLL1_SYSCLK2= DAVINCI_PLLC1_FLAG | 2,
+
+ /* map peripherals to clock IDs */
+ DAVINCI_ARM_CLKID = DAVINCI_PLL0_SYSCLK6,
+ DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4,
+ DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2,
+ DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2,
+ DAVINCI_UART2_CLKID = DAVINCI_PLL0_SYSCLK2,
+
+ /* special clock ID - output of PLL multiplier */
+ DAVINCI_PLLM_CLKID = 0x0FF,
+
+ /* special clock ID - output of PLL post divisor */
+ DAVINCI_PLLC_CLKID = 0x100,
+
+ /* special clock ID - PLL bypass */
+ DAVINCI_AUXCLK_CLKID= 0x101,
};
+#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
+ : get_async3_src())
+
int clk_get(enum davinci_clk_ids id);
/* Boot config */
@@ -570,10 +595,10 @@ static inline int cpu_is_da850(void)
return ((part_no == 0xb7d1) ? 1 : 0);
}
-static inline int get_async3_src(void)
+static inline enum davinci_clk_ids get_async3_src(void)
{
return (REG(davinci_syscfg_regs-cfgchip3) 0x10) ?
- PLL1_SYSCLK2 : 2;
+ DAVINCI_PLL1_SYSCLK2 : DAVINCI_PLL0_SYSCLK2;
}
#endif /* CONFIG_SOC_DA8XX */
--
1.7.2.5
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[U-Boot] [PATCH 3/3] DaVinci DA8xx: replace magic number for DDR speed
Replace a magic number for the DDR2/mDDR PHY clock ID with a proper
definition. In addition, don't request this clock ID on DA830 hardware,
which does not have a DDR2/mDDR PHY (or associated PLL controller).
Signed-off-by: Laurence Withers lwith...@guralp.com
Cc: Prabhakar Lad prabhakar.cse...@gmail.com
---
arch/arm/cpu/arm926ejs/davinci/cpu.c |3 ++-
arch/arm/include/asm/arch-davinci/hardware.h |2 ++
2 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c
b/arch/arm/cpu/arm926ejs/davinci/cpu.c
index 4bdb08b..b31add8 100644
--- a/arch/arm/cpu/arm926ejs/davinci/cpu.c
+++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c
@@ -122,7 +122,8 @@ int set_cpu_clk_info(void)
{
gd-bd-bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 100;
/* DDR PHY uses an x2 input clock */
- gd-bd-bi_ddr_freq = clk_get(0x10001) / 100;
+ gd-bd-bi_ddr_freq = cpu_is_da830() ? 0 :
+ (clk_get(DAVINCI_DDR_CLKID) / 100);
gd-bd-bi_dsp_freq = 0;
return 0;
}
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
b/arch/arm/include/asm/arch-davinci/hardware.h
index 0fce940..7f3dcc2 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -459,10 +459,12 @@ enum davinci_clk_ids {
DAVINCI_PLL0_SYSCLK2= DAVINCI_PLLC0_FLAG | 2,
DAVINCI_PLL0_SYSCLK4= DAVINCI_PLLC0_FLAG | 4,
DAVINCI_PLL0_SYSCLK6= DAVINCI_PLLC0_FLAG | 6,
+ DAVINCI_PLL1_SYSCLK1= DAVINCI_PLLC1_FLAG | 1,
DAVINCI_PLL1_SYSCLK2= DAVINCI_PLLC1_FLAG | 2,
/* map peripherals to clock IDs */
DAVINCI_ARM_CLKID = DAVINCI_PLL0_SYSCLK6,
+ DAVINCI_DDR_CLKID = DAVINCI_PLL1_SYSCLK1,
DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4,
DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2,
DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2,
--
1.7.2.5
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[U-Boot] [PATCH 2/3] DaVinci DA850: UART2 clock ID comes from ASYNC3
On the DA830, UART2's clock is derived from PLL controller 0 output 2.
On the DA850, it is in the ASYNC3 group, and may be switched between PLL
controller 0 or 1. Fix the definition of the ID to match.
Signed-off-by: Laurence Withers lwith...@guralp.com
Cc: Prabhakar Lad prabhakar.cse...@gmail.com
---
arch/arm/include/asm/arch-davinci/hardware.h |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
b/arch/arm/include/asm/arch-davinci/hardware.h
index dac43bb..0fce940 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -466,7 +466,6 @@ enum davinci_clk_ids {
DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4,
DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2,
DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2,
- DAVINCI_UART2_CLKID = DAVINCI_PLL0_SYSCLK2,
/* special clock ID - output of PLL multiplier */
DAVINCI_PLLM_CLKID = 0x0FF,
@@ -478,6 +477,9 @@ enum davinci_clk_ids {
DAVINCI_AUXCLK_CLKID= 0x101,
};
+#define DAVINCI_UART2_CLKID(cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
+ : get_async3_src())
+
#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
: get_async3_src())
--
1.7.2.5
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Re: [U-Boot] [PATCH] DaVinci DA8xx: fix set_cpu_clk_info()
On Sat, Jul 28, 2012 at 12:49:55PM +0530, Prabhakar Lad wrote:
Thanks for the patch. I have tested this patch, below are few comments.
[snip]
+int set_cpu_clk_info(void)
+{
+ gd-bd-bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 100;
+ /* DDR PHY uses an x2 input clock */
+ gd-bd-bi_ddr_freq = clk_get(0x10001) / 100;
Can you define a macro for this 0x10001 ?
With that change you can add my ACK:
Acked-by: Prabhakar Lad prabhakar@ti.com
Hi Prabhakar,
I have tidied up the clock IDs a little and added a constant for the DDR2
clock ID as you suggested. It made sense that this would be a separate set
of patches:
http://lists.denx.de/pipermail/u-boot/2012-July/129444.html
Bye for now,
--
Laurence Withers, lwith...@guralp.comhttp://www.guralp.com/
Direct tel:+447753988197 or tel:+44408643 Software Engineer
General support queries: supp...@guralp.com CMG-DCM CMG-EAM CMG-NAM
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Re: [U-Boot] [PATCH 3/3] DaVinci DA8xx: replace magic number for DDR speed
On Mon, Jul 30, 2012 at 04:30:15PM +, Laurence Withers wrote:
Replace a magic number for the DDR2/mDDR PHY clock ID with a proper
definition. In addition, don't request this clock ID on DA830 hardware,
which does not have a DDR2/mDDR PHY (or associated PLL controller).
Signed-off-by: Laurence Withers lwith...@guralp.com
Cc: Prabhakar Lad prabhakar.cse...@gmail.com
---
arch/arm/cpu/arm926ejs/davinci/cpu.c |3 ++-
arch/arm/include/asm/arch-davinci/hardware.h |2 ++
2 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c
b/arch/arm/cpu/arm926ejs/davinci/cpu.c
index 4bdb08b..b31add8 100644
--- a/arch/arm/cpu/arm926ejs/davinci/cpu.c
+++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c
@@ -122,7 +122,8 @@ int set_cpu_clk_info(void)
{
gd-bd-bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 100;
/* DDR PHY uses an x2 input clock */
- gd-bd-bi_ddr_freq = clk_get(0x10001) / 100;
+ gd-bd-bi_ddr_freq = cpu_is_da830() ? 0 :
+ (clk_get(DAVINCI_DDR_CLKID) / 100);
gd-bd-bi_dsp_freq = 0;
return 0;
}
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
b/arch/arm/include/asm/arch-davinci/hardware.h
index 0fce940..7f3dcc2 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -459,10 +459,12 @@ enum davinci_clk_ids {
DAVINCI_PLL0_SYSCLK2= DAVINCI_PLLC0_FLAG | 2,
DAVINCI_PLL0_SYSCLK4= DAVINCI_PLLC0_FLAG | 4,
DAVINCI_PLL0_SYSCLK6= DAVINCI_PLLC0_FLAG | 6,
+ DAVINCI_PLL1_SYSCLK1= DAVINCI_PLLC1_FLAG | 1,
DAVINCI_PLL1_SYSCLK2= DAVINCI_PLLC1_FLAG | 2,
/* map peripherals to clock IDs */
DAVINCI_ARM_CLKID = DAVINCI_PLL0_SYSCLK6,
+ DAVINCI_DDR_CLKID = DAVINCI_PLL1_SYSCLK1,
DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4,
DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2,
DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2,
--
1.7.2.5
Hi,
This patch does depend on my earlier patch to tidy up the definition of
set_cpu_clk_info() :
http://lists.denx.de/pipermail/u-boot/2012-July/129205.html
Bye for now,
--
Laurence Withers, lwith...@guralp.comhttp://www.guralp.com/
Direct tel:+447753988197 or tel:+44408643 Software Engineer
General support queries: supp...@guralp.com CMG-DCM CMG-EAM CMG-NAM
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[U-Boot] [PATCH 0/17]: Improve am33xx support
Hey all, The following series of patches improves am33xx support, and cleans up omap3/4/5 slightly. The slight cleanup to omap3/4/5 is that we can all share a single function to see if we are executing in SDRAM or not. The rest of the series cleans up the EMIF code for am33xx. While I had hoped to be able to re-use the omap4/5 code as the EMIF unit is the same block, it's simply wired up too differently to reuse the same codebase. We can however reuse the register structs so some of the commits here are about changing to use that. There's also bugfixes to the DDR2 init sequence and cleanups that will make adding DDR3 support easier. I also update the am335x_evm config to be like a normal board and support common commands and booting Linux. -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 02/17] am335x_evm: Update config for common usage
- Add default commands
- Add HUSH parser
- Make environment, malloc areas larger
- Add ATAGS and OF_LIBFDT
- Add defaults to boot ramdisk and MMC, use uEnv.txt
Signed-off-by: Tom Rini tr...@ti.com
---
include/configs/am335x_evm.h | 69 --
1 file changed, 59 insertions(+), 10 deletions(-)
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index d0fbc88..32a7441 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -17,32 +17,81 @@
#define __CONFIG_AM335X_EVM_H
#define CONFIG_AM33XX
-#define CONFIG_CMD_MEMORY /* for mtest */
-#undef CONFIG_GZIP
-#undef CONFIG_ZLIB
-#undef CONFIG_SYS_HUSH_PARSER
#undef CONFIG_CMD_NET
#include asm/arch/cpu.h
#include asm/arch/hardware.h
-#define CONFIG_ENV_SIZE0x400
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 * 1024))
+#define CONFIG_ENV_SIZE(128 10) /* 128 KiB */
+#define CONFIG_SYS_MALLOC_LEN (1024 10)
+#define CONFIG_SYS_LONGHELP/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use hush command parser */
#define CONFIG_SYS_PROMPT U-Boot#
#define CONFIG_SYS_NO_FLASH
#define MACH_TYPE_TIAM335EVM 3589/* Until the next sync */
#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/* commands to include */
+#include config_cmd_default.h
+
#define CONFIG_CMD_ASKENV
#define CONFIG_VERSION_VARIABLE
/* set to negative value for no autoboot */
#define CONFIG_BOOTDELAY 3
-#define CONFIG_SYS_AUTOLOADno
-#define CONFIG_BOOTFILEuImage
#define CONFIG_EXTRA_ENV_SETTINGS \
- verify=yes\0 \
- ramdisk_file=ramdisk.gz\0 \
+ loadaddr=0x8020\0 \
+ rdaddr=0x8100\0 \
+ bootfile=/boot/uImage\0 \
+ console=ttyO0,115200n8\0 \
+ optargs=\0 \
+ mmcdev=0\0 \
+ mmcroot=/dev/mmcblk0p2 rw\0 \
+ mmcrootfstype=ext3 rootwait\0 \
+ ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0 \
+ ramrootfstype=ext2\0 \
+ mmcargs=setenv bootargs console=${console} \
+ ${optargs} \
+ root=${mmcroot} \
+ rootfstype=${mmcrootfstype}\0 \
+ bootenv=uEnv.txt\0 \
+ loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0 \
+ importbootenv=echo Importing environment from mmc ...; \
+ env import -t $loadaddr $filesize\0 \
+ ramargs=setenv bootargs console=${console} \
+ ${optargs} \
+ root=${ramroot} \
+ rootfstype=${ramrootfstype}\0 \
+ loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0 \
+ loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0 \
+ loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0 \
+ mmcboot=echo Booting from mmc ...; \
+ run mmcargs; \
+ bootm ${loadaddr}\0 \
+ ramboot=echo Booting from ramdisk ...; \
+ run ramargs; \
+ bootm ${loadaddr}\0 \
+
+#define CONFIG_BOOTCOMMAND \
+ if mmc rescan ${mmcdev}; then \
+ echo SD/MMC found on device ${mmcdev}; \
+ if run loadbootenv; then \
+ echo Loaded environment from ${bootenv}; \
+ run importbootenv; \
+ fi; \
+ if test -n $uenvcmd; then \
+ echo Running uenvcmd ...; \
+ run uenvcmd; \
+ fi; \
+ if run loaduimage; then \
+ run mmcboot; \
+ fi; \
+ fi; \
/* Clock Defines */
#define V_OSCK 2400 /* Clock output from T2 */
--
1.7.9.5
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[U-Boot] [PATCH 01/17] omap3/omap4/omap5/am33xx: Use a common running_from_sdram function
On all OMAP3+ platforms we know that SDRAM starts at 0x8000 and we
can use 0xD000 as the end.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/omap3/board.c|4 ++--
arch/arm/cpu/armv7/omap3/sys_info.c | 12
arch/arm/include/asm/arch-omap3/sys_proto.h |1 -
arch/arm/include/asm/arch-omap4/omap.h |5 -
arch/arm/include/asm/arch-omap4/sys_proto.h |8
arch/arm/include/asm/arch-omap5/omap.h |5 -
arch/arm/include/asm/arch-omap5/sys_proto.h |8
arch/arm/include/asm/omap_common.h | 14 ++
8 files changed, 16 insertions(+), 41 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index f2e52e9..7639bdd 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -177,7 +177,7 @@ void secureworld_exit()
void try_unlock_memory()
{
int mode;
- int in_sdram = is_running_in_sdram();
+ int in_sdram = running_from_sdram();
/*
* if GP device unlock device SRAM for general use
@@ -210,7 +210,7 @@ void try_unlock_memory()
*/
void s_init(void)
{
- int in_sdram = is_running_in_sdram();
+ int in_sdram = running_from_sdram();
watchdog_init();
diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c
b/arch/arm/cpu/armv7/omap3/sys_info.c
index 3c80113..a49e84a 100644
--- a/arch/arm/cpu/armv7/omap3/sys_info.c
+++ b/arch/arm/cpu/armv7/omap3/sys_info.c
@@ -240,18 +240,6 @@ u32 is_running_in_sram(void)
return 0; /* running in FLASH or SDRAM */
}
-/
- * is_running_in_sdram() - tell if currently running in
- * SDRAM.
- ***/
-u32 is_running_in_sdram(void)
-{
- if (get_base() 4)
- return 1; /* in SDRAM */
-
- return 0; /* running in SRAM or FLASH */
-}
-
/***
* get_boot_type() - Is this an XIP type device or a stream one
* bits 4-0 specify type. Bit 5 says mem/perif
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h
b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 9e52b12..269b8cc 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -57,7 +57,6 @@ u32 get_sysboot_value(void);
u32 is_gpmc_muxed(void);
u32 get_gpmc0_type(void);
u32 get_gpmc0_width(void);
-u32 is_running_in_sdram(void);
u32 is_running_in_sram(void);
u32 is_running_in_flash(void);
u32 get_device_type(void);
diff --git a/arch/arm/include/asm/arch-omap4/omap.h
b/arch/arm/include/asm/arch-omap4/omap.h
index 03bd923..83d3813 100644
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -42,11 +42,6 @@
#define OMAP44XX_L4_WKUP_BASE 0x4A30
#define OMAP44XX_L4_PER_BASE 0x4800
-#define OMAP44XX_DRAM_ADDR_SPACE_START 0x8000
-#define OMAP44XX_DRAM_ADDR_SPACE_END 0xD000
-#define DRAM_ADDR_SPACE_START OMAP44XX_DRAM_ADDR_SPACE_START
-#define DRAM_ADDR_SPACE_ENDOMAP44XX_DRAM_ADDR_SPACE_END
-
/* CONTROL */
#define CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000)
#define CONTROL_PADCONF_CORE (OMAP44XX_L4_CORE_BASE + 0x10)
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h
b/arch/arm/include/asm/arch-omap4/sys_proto.h
index d633573..48a6550 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -67,14 +67,6 @@ void force_emif_self_refresh(void);
*/
extern struct omap_boot_parameters boot_params;
-static inline u32 running_from_sdram(void)
-{
- u32 pc;
- asm volatile (mov %0, pc : =r (pc));
- return ((pc = OMAP44XX_DRAM_ADDR_SPACE_START)
- (pc OMAP44XX_DRAM_ADDR_SPACE_END));
-}
-
static inline u8 uboot_loaded_by_spl(void)
{
/*
diff --git a/arch/arm/include/asm/arch-omap5/omap.h
b/arch/arm/include/asm/arch-omap5/omap.h
index 7f05cb5..c697e0b 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -39,11 +39,6 @@
#define OMAP54XX_L4_WKUP_BASE 0x4Ae0
#define OMAP54XX_L4_PER_BASE 0x4800
-#define OMAP54XX_DRAM_ADDR_SPACE_START 0x8000
-#define OMAP54XX_DRAM_ADDR_SPACE_END 0x
-#define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START
-#define DRAM_ADDR_SPACE_ENDOMAP54XX_DRAM_ADDR_SPACE_END
-
/* CONTROL */
#define CTRL_BASE (OMAP54XX_L4_CORE_BASE + 0x2000)
#define CONTROL_PADCONF_CORE (CTRL_BASE + 0x0800)
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h
b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 74feb90..23b02fd 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -68,14 +68,6 @@ void
[U-Boot] [PATCH 03/17] am33xx: Remove DMM_BASE define
The am33xx does not have a DMM, so don't define the base. Signed-off-by: Tom Rini tr...@ti.com --- arch/arm/include/asm/arch-am33xx/hardware.h |1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index 0ec22eb..9be679f 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -53,7 +53,6 @@ /* EMIF Base address */ #define EMIF4_0_CFG_BASE 0x4C00 #define EMIF4_1_CFG_BASE 0x4D00 -#define DMM_BASE 0x4E00 /* PLL related registers */ #define CM_PER 0x44E0 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 04/17] am33xx: Convert to using asm/emif.h to describe the EMIF
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/ddr.c | 29 ++-
arch/arm/include/asm/arch-am33xx/ddr_defs.h | 27 -
2 files changed, 15 insertions(+), 41 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index ed982c1..e592609 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -18,12 +18,13 @@ http://www.ti.com/
#include asm/arch/cpu.h
#include asm/arch/ddr_defs.h
#include asm/io.h
+#include asm/emif.h
/**
* Base address for EMIF instances
*/
-static struct emif_regs *emif_reg = {
- (struct emif_regs *)EMIF4_0_CFG_BASE};
+static struct emif_reg_struct *emif_reg = {
+ (struct emif_reg_struct *)EMIF4_0_CFG_BASE};
/**
* Base address for DDR instance
@@ -48,10 +49,10 @@ static struct ddr_cmdtctrl *ioctrl_reg = {
*/
int config_sdram(struct sdram_config *cfg)
{
- writel(cfg-sdrcr, emif_reg-sdrcr);
- writel(cfg-sdrcr2, emif_reg-sdrcr2);
- writel(cfg-refresh, emif_reg-sdrrcr);
- writel(cfg-refresh_sh, emif_reg-sdrrcsr);
+ writel(cfg-sdrcr, emif_reg-emif_sdram_config);
+ writel(cfg-sdrcr2, emif_reg-emif_lpddr2_nvm_config);
+ writel(cfg-refresh, emif_reg-emif_sdram_ref_ctrl);
+ writel(cfg-refresh_sh, emif_reg-emif_sdram_ref_ctrl_shdw);
return 0;
}
@@ -61,12 +62,12 @@ int config_sdram(struct sdram_config *cfg)
*/
int set_sdram_timings(struct sdram_timing *t)
{
- writel(t-time1, emif_reg-sdrtim1);
- writel(t-time1_sh, emif_reg-sdrtim1sr);
- writel(t-time2, emif_reg-sdrtim2);
- writel(t-time2_sh, emif_reg-sdrtim2sr);
- writel(t-time3, emif_reg-sdrtim3);
- writel(t-time3_sh, emif_reg-sdrtim3sr);
+ writel(t-time1, emif_reg-emif_sdram_tim_1);
+ writel(t-time1_sh, emif_reg-emif_sdram_tim_1_shdw);
+ writel(t-time2, emif_reg-emif_sdram_tim_2);
+ writel(t-time2_sh, emif_reg-emif_sdram_tim_2_shdw);
+ writel(t-time3, emif_reg-emif_sdram_tim_3);
+ writel(t-time3_sh, emif_reg-emif_sdram_tim_3_shdw);
return 0;
}
@@ -76,8 +77,8 @@ int set_sdram_timings(struct sdram_timing *t)
*/
int config_ddr_phy(struct ddr_phy_control *p)
{
- writel(p-reg, emif_reg-ddrphycr);
- writel(p-reg_sh, emif_reg-ddrphycsr);
+ writel(p-reg, emif_reg-emif_ddr_phy_ctrl_1);
+ writel(p-reg_sh, emif_reg-emif_ddr_phy_ctrl_1_shdw);
return 0;
}
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 388336f..c62f826 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -56,33 +56,6 @@
#define DDR_IOCTRL_VALUE 0x18B
/**
- * This structure represents the EMIF registers on AM33XX devices.
- */
-struct emif_regs {
- unsigned int sdrrev;/* offset 0x00 */
- unsigned int sdrstat; /* offset 0x04 */
- unsigned int sdrcr; /* offset 0x08 */
- unsigned int sdrcr2;/* offset 0x0C */
- unsigned int sdrrcr;/* offset 0x10 */
- unsigned int sdrrcsr; /* offset 0x14 */
- unsigned int sdrtim1; /* offset 0x18 */
- unsigned int sdrtim1sr; /* offset 0x1C */
- unsigned int sdrtim2; /* offset 0x20 */
- unsigned int sdrtim2sr; /* offset 0x24 */
- unsigned int sdrtim3; /* offset 0x28 */
- unsigned int sdrtim3sr; /* offset 0x2C */
- unsigned int res1[2];
- unsigned int sdrmcr;/* offset 0x38 */
- unsigned int sdrmcsr; /* offset 0x3C */
- unsigned int res2[8];
- unsigned int sdritr;/* offset 0x60 */
- unsigned int res3[32];
- unsigned int ddrphycr; /* offset 0xE4 */
- unsigned int ddrphycsr; /* offset 0xE8 */
- unsigned int ddrphycr2; /* offset 0xEC */
-};
-
-/**
* Encapsulates DDR PHY control and corresponding shadow registers.
*/
struct ddr_phy_control {
--
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[U-Boot] [PATCH 06/17] am33xx: Bugfix to config_sdram()
When we change SDRAM_CONFIG this triggers a refresh based on all of the
parameters that we have programmed so we must do this last.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/ddr.c |3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index e592609..c37f91b 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -49,10 +49,9 @@ static struct ddr_cmdtctrl *ioctrl_reg = {
*/
int config_sdram(struct sdram_config *cfg)
{
- writel(cfg-sdrcr, emif_reg-emif_sdram_config);
- writel(cfg-sdrcr2, emif_reg-emif_lpddr2_nvm_config);
writel(cfg-refresh, emif_reg-emif_sdram_ref_ctrl);
writel(cfg-refresh_sh, emif_reg-emif_sdram_ref_ctrl_shdw);
+ writel(cfg-sdrcr, emif_reg-emif_sdram_config);
return 0;
}
--
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[U-Boot] [PATCH 05/17] am33xx: Remove extra check in enable_ddr_clocks
We do not need to check for EMIF_GCLK and L3_GCLK being active. This was a hold-over from bringup and no longer required. Signed-off-by: Tom Rini tr...@ti.com --- arch/arm/cpu/armv7/am33xx/clock.c |5 - 1 file changed, 5 deletions(-) diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c index bbb9c13..d05780c 100644 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -255,11 +255,6 @@ void enable_emif_clocks(void) writel(PRCM_MOD_EN, cmper-emiffwclkctrl); /* Enable EMIF0 Clock */ writel(PRCM_MOD_EN, cmper-emifclkctrl); - /* Poll for emif_gclk L3_G clock are active */ - while ((readl(cmper-l3clkstctrl) (PRCM_EMIF_CLK_ACTIVITY | - PRCM_L3_GCLK_ACTIVITY)) != (PRCM_EMIF_CLK_ACTIVITY | - PRCM_L3_GCLK_ACTIVITY)) - ; /* Poll if module is functional */ while ((readl(cmper-emifclkctrl)) != PRCM_MOD_EN) ; -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 07/17] am33xx: Rework DDR2 EMIF initalization slightly
With the previous bugfix we now don't need to set two different REF_CTRL
values and instead set the final value.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/emif4.c | 17 ++---
1 file changed, 2 insertions(+), 15 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c
b/arch/arm/cpu/armv7/am33xx/emif4.c
index 2f4164d..8f7aadc 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -117,7 +117,6 @@ static void config_vtp(void)
static void config_emif_ddr2(void)
{
- int i;
int ret;
struct sdram_config cfg;
struct sdram_timing tmg;
@@ -137,31 +136,19 @@ static void config_emif_ddr2(void)
cfg.sdrcr = EMIF_SDCFG;
cfg.sdrcr2 = EMIF_SDCFG;
- cfg.refresh = 0x4650;
- cfg.refresh_sh = 0x4650;
+ cfg.refresh = EMIF_SDREF;
+ cfg.refresh_sh = EMIF_SDREF;
/* Program EMIF instance */
ret = config_ddr_phy(phyc);
if (ret 0)
printf(Couldn't configure phyc\n);
- ret = config_sdram(cfg);
- if (ret 0)
- printf(Couldn't configure SDRAM\n);
ret = set_sdram_timings(tmg);
if (ret 0)
printf(Couldn't configure timings\n);
- /* Delay */
- for (i = 0; i 5000; i++)
- ;
-
- cfg.refresh = EMIF_SDREF;
- cfg.refresh_sh = EMIF_SDREF;
- cfg.sdrcr = EMIF_SDCFG;
- cfg.sdrcr2 = EMIF_SDCFG;
-
ret = config_sdram(cfg);
if (ret 0)
printf(Couldn't configure SDRAM\n);
--
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[U-Boot] [PATCH 08/17] am33xx: Make config_cmd_ctrl / config_ddr_data take const structs
Rework the EMIF4/DDR code slightly to setup the structs that
config_cmd_ctrl and config_ddr_data take to be setup at compile time and
mark them as const. This lets us simplify the calling path slightly as
well as making it easier to deal with DDR3.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/ddr.c |4 +-
arch/arm/cpu/armv7/am33xx/emif4.c | 101 ---
arch/arm/include/asm/arch-am33xx/ddr_defs.h |4 +-
3 files changed, 48 insertions(+), 61 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index c37f91b..b4b3c01 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -85,7 +85,7 @@ int config_ddr_phy(struct ddr_phy_control *p)
/**
* Configure DDR CMD control registers
*/
-int config_cmd_ctrl(struct cmd_control *cmd)
+int config_cmd_ctrl(const struct cmd_control *cmd)
{
writel(cmd-cmd0csratio, ddr_reg[0]-cm0csratio);
writel(cmd-cmd0csforce, ddr_reg[0]-cm0csforce);
@@ -111,7 +111,7 @@ int config_cmd_ctrl(struct cmd_control *cmd)
/**
* Configure DDR DATA registers
*/
-int config_ddr_data(int macrono, struct ddr_data *data)
+int config_ddr_data(int macrono, const struct ddr_data *data)
{
writel(data-datardsratio0, ddr_reg[macrono]-dt0rdsratio0);
writel(data-datardsratio1, ddr_reg[macrono]-dt0rdsratio1);
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c
b/arch/arm/cpu/armv7/am33xx/emif4.c
index 8f7aadc..26c6a66 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -47,58 +47,47 @@ void dram_init_banksize(void)
#ifdef CONFIG_SPL_BUILD
-static void data_macro_config(int dataMacroNum)
-{
- struct ddr_data data;
-
- data.datardsratio0 = ((DDR2_RD_DQS30)|(DDR2_RD_DQS20)
- |(DDR2_RD_DQS10)|(DDR2_RD_DQS0));
- data.datardsratio1 = DDR2_RD_DQS2;
- data.datawdsratio0 = ((DDR2_WR_DQS30)|(DDR2_WR_DQS20)
- |(DDR2_WR_DQS10)|(DDR2_WR_DQS0));
- data.datawdsratio1 = DDR2_WR_DQS2;
- data.datawiratio0 = ((DDR2_PHY_WRLVL30)|(DDR2_PHY_WRLVL20)
- |(DDR2_PHY_WRLVL10)|(DDR2_PHY_WRLVL0));
- data.datawiratio1 = DDR2_PHY_WRLVL2;
- data.datagiratio0 = ((DDR2_PHY_GATELVL30)|(DDR2_PHY_GATELVL20)
- |(DDR2_PHY_GATELVL10)|(DDR2_PHY_GATELVL0));
- data.datagiratio1 = DDR2_PHY_GATELVL2;
- data.datafwsratio0 = ((DDR2_PHY_FIFO_WE30)|(DDR2_PHY_FIFO_WE20)
- |(DDR2_PHY_FIFO_WE10)|(DDR2_PHY_FIFO_WE0));
- data.datafwsratio1 = DDR2_PHY_FIFO_WE2;
- data.datawrsratio0 = ((DDR2_PHY_WR_DATA30)|(DDR2_PHY_WR_DATA20)
- |(DDR2_PHY_WR_DATA10)|(DDR2_PHY_WR_DATA0));
- data.datawrsratio1 = DDR2_PHY_WR_DATA2;
- data.datadldiff0 = PHY_DLL_LOCK_DIFF;
-
- config_ddr_data(dataMacroNum, data);
-}
-
-static void cmd_macro_config(void)
-{
- struct cmd_control cmd;
-
- cmd.cmd0csratio = DDR2_RATIO;
- cmd.cmd0csforce = CMD_FORCE;
- cmd.cmd0csdelay = CMD_DELAY;
- cmd.cmd0dldiff = DDR2_DLL_LOCK_DIFF;
- cmd.cmd0iclkout = DDR2_INVERT_CLKOUT;
-
- cmd.cmd1csratio = DDR2_RATIO;
- cmd.cmd1csforce = CMD_FORCE;
- cmd.cmd1csdelay = CMD_DELAY;
- cmd.cmd1dldiff = DDR2_DLL_LOCK_DIFF;
- cmd.cmd1iclkout = DDR2_INVERT_CLKOUT;
-
- cmd.cmd2csratio = DDR2_RATIO;
- cmd.cmd2csforce = CMD_FORCE;
- cmd.cmd2csdelay = CMD_DELAY;
- cmd.cmd2dldiff = DDR2_DLL_LOCK_DIFF;
- cmd.cmd2iclkout = DDR2_INVERT_CLKOUT;
-
- config_cmd_ctrl(cmd);
-
-}
+static const struct ddr_data ddr2_data = {
+ .datardsratio0 = ((DDR2_RD_DQS30)|(DDR2_RD_DQS20)
+ |(DDR2_RD_DQS10)|(DDR2_RD_DQS0)),
+ .datardsratio1 = DDR2_RD_DQS2,
+ .datawdsratio0 = ((DDR2_WR_DQS30)|(DDR2_WR_DQS20)
+ |(DDR2_WR_DQS10)|(DDR2_WR_DQS0)),
+ .datawdsratio1 = DDR2_WR_DQS2,
+ .datawiratio0 = ((DDR2_PHY_WRLVL30)|(DDR2_PHY_WRLVL20)
+ |(DDR2_PHY_WRLVL10)|(DDR2_PHY_WRLVL0)),
+ .datawiratio1 = DDR2_PHY_WRLVL2,
+ .datagiratio0 = ((DDR2_PHY_GATELVL30)|(DDR2_PHY_GATELVL20)
+ |(DDR2_PHY_GATELVL10)|(DDR2_PHY_GATELVL0)),
+ .datagiratio1 = DDR2_PHY_GATELVL2,
+ .datafwsratio0 = ((DDR2_PHY_FIFO_WE30)|(DDR2_PHY_FIFO_WE20)
+ |(DDR2_PHY_FIFO_WE10)|(DDR2_PHY_FIFO_WE0)),
+ .datafwsratio1 = DDR2_PHY_FIFO_WE2,
+ .datawrsratio0 = ((DDR2_PHY_WR_DATA30)|(DDR2_PHY_WR_DATA20)
+ |(DDR2_PHY_WR_DATA10)|(DDR2_PHY_WR_DATA0)),
+ .datawrsratio1 = DDR2_PHY_WR_DATA2,
+ .datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
+static const struct cmd_control ddr2_cmd_ctrl_data = {
+ .cmd0csratio = DDR2_RATIO,
+ .cmd0csforce = CMD_FORCE,
+
[U-Boot] [PATCH 09/17] am33xx: Pass to config_ddr the type of memory that is connected
We need to pass in the type of memory that is connected to the board.
The only reliable way to do this is to know what type of board we are
running on (which later will be knowable in s_init()). For now, pass in
the value of DDR2.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/board.c |3 ++-
arch/arm/cpu/armv7/am33xx/emif4.c | 38 +++
arch/arm/include/asm/arch-am33xx/ddr_defs.h |2 +-
arch/arm/include/asm/emif.h |8 +-
4 files changed, 31 insertions(+), 20 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/board.c
b/arch/arm/cpu/armv7/am33xx/board.c
index 71309a7..fd2d82b 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -26,6 +26,7 @@
#include asm/arch/common_def.h
#include asm/io.h
#include asm/omap_common.h
+#include asm/emif.h
DECLARE_GLOBAL_DATA_PTR;
@@ -97,7 +98,7 @@ void s_init(void)
preloader_console_init();
- config_ddr();
+ config_ddr(EMIF_REG_SDRAM_TYPE_DDR2);
#endif
/* Enable MMC0 */
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c
b/arch/arm/cpu/armv7/am33xx/emif4.c
index 26c6a66..9b1a80c 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -22,6 +22,7 @@
#include asm/arch/hardware.h
#include asm/arch/clock.h
#include asm/io.h
+#include asm/emif.h
DECLARE_GLOBAL_DATA_PTR;
@@ -29,7 +30,6 @@ struct ddr_regs *ddrregs = (struct ddr_regs
*)DDR_PHY_BASE_ADDR;
struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
-
int dram_init(void)
{
/* dram_init must store complete ramsize in gd-ram_size */
@@ -143,33 +143,37 @@ static void config_emif_ddr2(void)
printf(Couldn't configure SDRAM\n);
}
-void config_ddr(void)
+void config_ddr(short ddr_type)
{
struct ddr_ioctrl ioctrl;
enable_emif_clocks();
- config_vtp();
+ if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
+ config_vtp();
- config_cmd_ctrl(ddr2_cmd_ctrl_data);
+ config_cmd_ctrl(ddr2_cmd_ctrl_data);
- config_ddr_data(0, ddr2_data);
- config_ddr_data(1, ddr2_data);
+ config_ddr_data(0, ddr2_data);
+ config_ddr_data(1, ddr2_data);
- writel(PHY_RANK0_DELAY, ddrregs-dt0rdelays0);
- writel(PHY_RANK0_DELAY, ddrregs-dt1rdelays0);
+ writel(PHY_RANK0_DELAY, ddrregs-dt0rdelays0);
+ writel(PHY_RANK0_DELAY, ddrregs-dt1rdelays0);
- ioctrl.cmd1ctl = DDR_IOCTRL_VALUE;
- ioctrl.cmd2ctl = DDR_IOCTRL_VALUE;
- ioctrl.cmd3ctl = DDR_IOCTRL_VALUE;
- ioctrl.data1ctl = DDR_IOCTRL_VALUE;
- ioctrl.data2ctl = DDR_IOCTRL_VALUE;
+ ioctrl.cmd1ctl = DDR_IOCTRL_VALUE;
+ ioctrl.cmd2ctl = DDR_IOCTRL_VALUE;
+ ioctrl.cmd3ctl = DDR_IOCTRL_VALUE;
+ ioctrl.data1ctl = DDR_IOCTRL_VALUE;
+ ioctrl.data2ctl = DDR_IOCTRL_VALUE;
- config_io_ctrl(ioctrl);
+ config_io_ctrl(ioctrl);
- writel(readl(ddrctrl-ddrioctrl) 0xefff, ddrctrl-ddrioctrl);
- writel(readl(ddrctrl-ddrckectrl) | 0x0001, ddrctrl-ddrckectrl);
+ writel(readl(ddrctrl-ddrioctrl) 0xefff,
+ ddrctrl-ddrioctrl);
+ writel(readl(ddrctrl-ddrckectrl) | 0x0001,
+ ddrctrl-ddrckectrl);
- config_emif_ddr2();
+ config_emif_ddr2();
+ }
}
#endif
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 087082f..842e45f 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -232,6 +232,6 @@ struct ddr_ctrl {
unsigned int ddrckectrl;
};
-void config_ddr(void);
+void config_ddr(short ddr_type);
#endif /* _DDR_DEFS_H */
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 674c3de..ed251ec 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -19,7 +19,7 @@
#define EMIF1_BASE 0x4c00
#define EMIF2_BASE 0x4d00
-/* Registers shifts and masks */
+/* Registers shifts, masks and values */
/* EMIF_MOD_ID_REV */
#define EMIF_REG_SCHEME_SHIFT 30
@@ -46,6 +46,12 @@
/* SDRAM_CONFIG */
#define EMIF_REG_SDRAM_TYPE_SHIFT 29
#define EMIF_REG_SDRAM_TYPE_MASK (0x7 29)
+#define EMIF_REG_SDRAM_TYPE_DDR1 0
+#define EMIF_REG_SDRAM_TYPE_LPDDR1 1
+#define EMIF_REG_SDRAM_TYPE_DDR2 2
+#define EMIF_REG_SDRAM_TYPE_DDR3 3
+#define EMIF_REG_SDRAM_TYPE_LPDDR2_S4 4
+#define EMIF_REG_SDRAM_TYPE_LPDDR2_S2 5
#define
[U-Boot] [PATCH 10/17] am33xx: Move the call to ddr_pll_config, make it take the frequency
Depending on if we have DDR2 or DDR3 on the board we will need to call
ddr_pll_config with a different value. This call can be delayed
slightly to the point where we know which type of memory we have.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/clock.c|5 ++---
arch/arm/cpu/armv7/am33xx/emif4.c|2 ++
arch/arm/include/asm/arch-am33xx/sys_proto.h |1 +
3 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c
b/arch/arm/cpu/armv7/am33xx/clock.c
index d05780c..82bbba2 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -216,7 +216,7 @@ static void per_pll_config(void)
;
}
-static void ddr_pll_config(void)
+void ddr_pll_config(unsigned int ddrpll_m)
{
u32 clkmode, clksel, div_m2;
@@ -234,7 +234,7 @@ static void ddr_pll_config(void)
;
clksel = clksel (~CLK_SEL_MASK);
- clksel = clksel | ((DDRPLL_M CLK_SEL_SHIFT) | DDRPLL_N);
+ clksel = clksel | ((ddrpll_m CLK_SEL_SHIFT) | DDRPLL_N);
writel(clksel, cmwkup-clkseldpllddr);
div_m2 = div_m2 CLK_DIV_SEL;
@@ -268,7 +268,6 @@ void pll_init()
mpu_pll_config();
core_pll_config();
per_pll_config();
- ddr_pll_config();
/* Enable the required interconnect clocks */
enable_interface_clocks();
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c
b/arch/arm/cpu/armv7/am33xx/emif4.c
index 9b1a80c..12f270a 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -21,6 +21,7 @@
#include asm/arch/ddr_defs.h
#include asm/arch/hardware.h
#include asm/arch/clock.h
+#include asm/arch/sys_proto.h
#include asm/io.h
#include asm/emif.h
@@ -150,6 +151,7 @@ void config_ddr(short ddr_type)
enable_emif_clocks();
if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
+ ddr_pll_config(266);
config_vtp();
config_cmd_ctrl(ddr2_cmd_ctrl_data);
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h
b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index 6c58f1b..eef5573 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -30,4 +30,5 @@ int print_cpuinfo(void);
u32 get_device_type(void);
void setup_clocks_for_console(void);
+void ddr_pll_config(unsigned int ddrpll_M);
#endif
--
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[U-Boot] [PATCH 11/17] am33xx: Clean up unused DDR defines, prefix more with 'DDR2'
- Remove a handful of unused defines. - Prefix more values with 'DDR2' as DDR3 will require different values. Signed-off-by: Tom Rini tr...@ti.com --- arch/arm/cpu/armv7/am33xx/emif4.c | 46 +-- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 32 +++ 2 files changed, 35 insertions(+), 43 deletions(-) diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index 12f270a..684b123 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -112,22 +112,22 @@ static void config_emif_ddr2(void) struct sdram_timing tmg; struct ddr_phy_control phyc; - /*Program EMIF0 CFG Registers*/ - phyc.reg = EMIF_READ_LATENCY; - phyc.reg_sh = EMIF_READ_LATENCY; - phyc.reg2 = EMIF_READ_LATENCY; - - tmg.time1 = EMIF_TIM1; - tmg.time1_sh = EMIF_TIM1; - tmg.time2 = EMIF_TIM2; - tmg.time2_sh = EMIF_TIM2; - tmg.time3 = EMIF_TIM3; - tmg.time3_sh = EMIF_TIM3; - - cfg.sdrcr = EMIF_SDCFG; - cfg.sdrcr2 = EMIF_SDCFG; - cfg.refresh = EMIF_SDREF; - cfg.refresh_sh = EMIF_SDREF; + /* Program EMIF0 CFG Registers */ + phyc.reg = DDR2_EMIF_READ_LATENCY; + phyc.reg_sh = DDR2_EMIF_READ_LATENCY; + phyc.reg2 = DDR2_EMIF_READ_LATENCY; + + tmg.time1 = DDR2_EMIF_TIM1; + tmg.time1_sh = DDR2_EMIF_TIM1; + tmg.time2 = DDR2_EMIF_TIM2; + tmg.time2_sh = DDR2_EMIF_TIM2; + tmg.time3 = DDR2_EMIF_TIM3; + tmg.time3_sh = DDR2_EMIF_TIM3; + + cfg.sdrcr = DDR2_EMIF_SDCFG; + cfg.sdrcr2 = DDR2_EMIF_SDCFG; + cfg.refresh = DDR2_EMIF_SDREF; + cfg.refresh_sh = DDR2_EMIF_SDREF; /* Program EMIF instance */ ret = config_ddr_phy(phyc); @@ -159,14 +159,14 @@ void config_ddr(short ddr_type) config_ddr_data(0, ddr2_data); config_ddr_data(1, ddr2_data); - writel(PHY_RANK0_DELAY, ddrregs-dt0rdelays0); - writel(PHY_RANK0_DELAY, ddrregs-dt1rdelays0); + writel(DDR2_PHY_RANK0_DELAY, ddrregs-dt0rdelays0); + writel(DDR2_PHY_RANK0_DELAY, ddrregs-dt1rdelays0); - ioctrl.cmd1ctl = DDR_IOCTRL_VALUE; - ioctrl.cmd2ctl = DDR_IOCTRL_VALUE; - ioctrl.cmd3ctl = DDR_IOCTRL_VALUE; - ioctrl.data1ctl = DDR_IOCTRL_VALUE; - ioctrl.data2ctl = DDR_IOCTRL_VALUE; + ioctrl.cmd1ctl = DDR2_IOCTRL_VALUE; + ioctrl.cmd2ctl = DDR2_IOCTRL_VALUE; + ioctrl.cmd3ctl = DDR2_IOCTRL_VALUE; + ioctrl.data1ctl = DDR2_IOCTRL_VALUE; + ioctrl.data2ctl = DDR2_IOCTRL_VALUE; config_io_ctrl(ioctrl); diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 842e45f..b4735ba 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -22,38 +22,30 @@ #include asm/arch/hardware.h /* AM335X EMIF Register values */ -#define EMIF_SDMGT 0x8000 -#define EMIF_SDRAM 0x4650 -#define EMIF_PHYCFG0x2 -#define DDR_PHY_RESET (0x1 10) -#define DDR_FUNCTIONAL_MODE_EN 0x1 -#define DDR_PHY_READY (0x1 2) #define VTP_CTRL_READY (0x1 5) #define VTP_CTRL_ENABLE(0x1 6) -#define VTP_CTRL_LOCK_EN (0x1 4) #define VTP_CTRL_START_EN (0x1) -#define DDR2_RATIO 0x80 #define CMD_FORCE 0x00 #define CMD_DELAY 0x00 +#define PHY_DLL_LOCK_DIFF 0x0 -#define EMIF_READ_LATENCY 0x05 -#define EMIF_TIM1 0x0666B3D6 -#define EMIF_TIM2 0x143731DA -#define EMIF_TIM3 0x0347 -#define EMIF_SDCFG 0x43805332 -#define EMIF_SDREF 0x081a +#define DDR2_EMIF_READ_LATENCY 0x05 +#define DDR2_EMIF_TIM1 0x0666B3D6 +#define DDR2_EMIF_TIM2 0x143731DA +#define DDR2_EMIF_TIM3 0x0347 +#define DDR2_EMIF_SDCFG0x43805332 +#define DDR2_EMIF_SDREF0x081a #define DDR2_DLL_LOCK_DIFF 0x0 -#define DDR2_RD_DQS0x12 -#define DDR2_PHY_FIFO_WE 0x80 - +#define DDR2_RATIO 0x80 #define DDR2_INVERT_CLKOUT 0x00 +#define DDR2_RD_DQS0x12 #define DDR2_WR_DQS0x00 #define DDR2_PHY_WRLVL 0x00 #define DDR2_PHY_GATELVL 0x00 #define DDR2_PHY_WR_DATA 0x40 -#define PHY_RANK0_DELAY0x01 -#define PHY_DLL_LOCK_DIFF 0x0 -#define DDR_IOCTRL_VALUE 0x18B +#define DDR2_PHY_FIFO_WE 0x80 +#define DDR2_PHY_RANK0_DELAY 0x1 +#define DDR2_IOCTRL_VALUE 0x18B /** * Encapsulates DDR PHY control and corresponding shadow registers. -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de
[U-Boot] [PATCH 12/17] am335x: ddr_defs: Update EMIF parameters
From: Vaibhav Bedia vaibhav.be...@ti.com EMIF parameters are calculated based on the AC timing parameters from the SDRAM datasheet and the DDR frequency. Current values for these paramters in AM335x U-Boot code, though reliable, are not fully optimal. The most optimal settings can be derived based on the guidelines published at [1]. A pre-computed set of values with the most optimum settings for AM335x EVM and BeagleBone can be found at [2]. [1] http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips [2] http://processors.wiki.ti.com/index.php/OMAP_and_Sitara_CCS_support#AM335x Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com Signed-off-by: Tom Rini tr...@ti.com --- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index b4735ba..879c5fb 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -29,11 +29,11 @@ #define CMD_DELAY 0x00 #define PHY_DLL_LOCK_DIFF 0x0 -#define DDR2_EMIF_READ_LATENCY 0x05 -#define DDR2_EMIF_TIM1 0x0666B3D6 -#define DDR2_EMIF_TIM2 0x143731DA -#define DDR2_EMIF_TIM3 0x0347 -#define DDR2_EMIF_SDCFG0x43805332 +#define DDR2_EMIF_READ_LATENCY 0x15/* Enable Dynamic Power Down */ +#define DDR2_EMIF_TIM1 0x0666B3C9 +#define DDR2_EMIF_TIM2 0x243631CA +#define DDR2_EMIF_TIM3 0x033F +#define DDR2_EMIF_SDCFG0x41805332 #define DDR2_EMIF_SDREF0x081a #define DDR2_DLL_LOCK_DIFF 0x0 #define DDR2_RATIO 0x80 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 16/17] am33xx: Rework config_io_ctrl slightly
This function sets a number of related registers to the same value (the
registers in question all have the same field descriptions and are
related in operation). Rather than defining a struct and setting the
value repeatedly, just pass in the value.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/ddr.c | 12 ++--
arch/arm/cpu/armv7/am33xx/emif4.c | 10 +-
arch/arm/include/asm/arch-am33xx/ddr_defs.h | 13 +
3 files changed, 8 insertions(+), 27 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index 993f3da..597d62f 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -120,11 +120,11 @@ void config_ddr_data(int macrono, const struct ddr_data
*data)
writel(data-datadldiff0, ddr_reg[macrono]-dt0dldiff0);
}
-void config_io_ctrl(struct ddr_ioctrl *ioctrl)
+void config_io_ctrl(unsigned long val)
{
- writel(ioctrl-cmd1ctl, ioctrl_reg-cm0ioctl);
- writel(ioctrl-cmd2ctl, ioctrl_reg-cm1ioctl);
- writel(ioctrl-cmd3ctl, ioctrl_reg-cm2ioctl);
- writel(ioctrl-data1ctl, ioctrl_reg-dt0ioctl);
- writel(ioctrl-data2ctl, ioctrl_reg-dt1ioctl);
+ writel(val, ioctrl_reg-cm0ioctl);
+ writel(val, ioctrl_reg-cm1ioctl);
+ writel(val, ioctrl_reg-cm2ioctl);
+ writel(val, ioctrl_reg-dt0ioctl);
+ writel(val, ioctrl_reg-dt1ioctl);
}
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c
b/arch/arm/cpu/armv7/am33xx/emif4.c
index 0190ec6..3219045 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -116,8 +116,6 @@ static void config_vtp(void)
void config_ddr(short ddr_type)
{
- struct ddr_ioctrl ioctrl;
-
enable_emif_clocks();
if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
@@ -132,13 +130,7 @@ void config_ddr(short ddr_type)
writel(DDR2_PHY_RANK0_DELAY, ddrregs-dt0rdelays0);
writel(DDR2_PHY_RANK0_DELAY, ddrregs-dt1rdelays0);
- ioctrl.cmd1ctl = DDR2_IOCTRL_VALUE;
- ioctrl.cmd2ctl = DDR2_IOCTRL_VALUE;
- ioctrl.cmd3ctl = DDR2_IOCTRL_VALUE;
- ioctrl.data1ctl = DDR2_IOCTRL_VALUE;
- ioctrl.data2ctl = DDR2_IOCTRL_VALUE;
-
- config_io_ctrl(ioctrl);
+ config_io_ctrl(DDR2_IOCTRL_VALUE);
/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, ddrctrl-ddrckectrl);
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 7806e1b..ebd3077 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -174,20 +174,9 @@ struct ddr_cmdtctrl {
};
/**
- * Encapsulates DDR CMD DATA io control registers.
- */
-struct ddr_ioctrl {
- unsigned long cmd1ctl;
- unsigned long cmd2ctl;
- unsigned long cmd3ctl;
- unsigned long data1ctl;
- unsigned long data2ctl;
-};
-
-/**
* Configure DDR io control registers
*/
-void config_io_ctrl(struct ddr_ioctrl *ioctrl);
+void config_io_ctrl(unsigned long val);
struct ddr_ctrl {
unsigned int ddrioctrl;
--
1.7.9.5
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[U-Boot] [PATCH 13/17] am33xx: Document what we're doing with ddrctrl-ddrckectrl
- Remove the call to set ddrctrl-ddrioctrl as it's all zeros. - Comment what we're really setting in ddrctrl-ddrckectrl which is that we're operating in the normal mode where EMIF/PHY clock is controlled by the PHY. Signed-off-by: Tom Rini tr...@ti.com --- arch/arm/cpu/armv7/am33xx/emif4.c |6 ++ arch/arm/include/asm/arch-am33xx/ddr_defs.h |1 + 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index 684b123..e04e970 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -170,10 +170,8 @@ void config_ddr(short ddr_type) config_io_ctrl(ioctrl); - writel(readl(ddrctrl-ddrioctrl) 0xefff, - ddrctrl-ddrioctrl); - writel(readl(ddrctrl-ddrckectrl) | 0x0001, - ddrctrl-ddrckectrl); + /* Set CKE to be controlled by EMIF/DDR PHY */ + writel(DDR_CKE_CTRL_NORMAL, ddrctrl-ddrckectrl); config_emif_ddr2(); } diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 879c5fb..f755736 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -28,6 +28,7 @@ #define CMD_FORCE 0x00 #define CMD_DELAY 0x00 #define PHY_DLL_LOCK_DIFF 0x0 +#define DDR_CKE_CTRL_NORMAL0x1 #define DDR2_EMIF_READ_LATENCY 0x15/* Enable Dynamic Power Down */ #define DDR2_EMIF_TIM1 0x0666B3C9 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 15/17] am33xx: Use emif_regs struct for storing initialization values
Rather than defining our own structs to note what to use when
programming the EMIF and related re-use the emif_regs struct.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/ddr.c | 28 -
arch/arm/cpu/armv7/am33xx/emif4.c | 43 ---
arch/arm/include/asm/arch-am33xx/ddr_defs.h | 38 +++
3 files changed, 31 insertions(+), 78 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index 7ac144a..993f3da 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -42,33 +42,33 @@ static struct ddr_cmdtctrl *ioctrl_reg = {
/**
* Configure SDRAM
*/
-void config_sdram(struct sdram_config *cfg)
+void config_sdram(const struct emif_regs *regs)
{
- writel(cfg-refresh, emif_reg-emif_sdram_ref_ctrl);
- writel(cfg-refresh_sh, emif_reg-emif_sdram_ref_ctrl_shdw);
- writel(cfg-sdrcr, emif_reg-emif_sdram_config);
+ writel(regs-ref_ctrl, emif_reg-emif_sdram_ref_ctrl);
+ writel(regs-ref_ctrl, emif_reg-emif_sdram_ref_ctrl_shdw);
+ writel(regs-sdram_config, emif_reg-emif_sdram_config);
}
/**
* Set SDRAM timings
*/
-void set_sdram_timings(struct sdram_timing *t)
+void set_sdram_timings(const struct emif_regs *regs)
{
- writel(t-time1, emif_reg-emif_sdram_tim_1);
- writel(t-time1_sh, emif_reg-emif_sdram_tim_1_shdw);
- writel(t-time2, emif_reg-emif_sdram_tim_2);
- writel(t-time2_sh, emif_reg-emif_sdram_tim_2_shdw);
- writel(t-time3, emif_reg-emif_sdram_tim_3);
- writel(t-time3_sh, emif_reg-emif_sdram_tim_3_shdw);
+ writel(regs-sdram_tim1, emif_reg-emif_sdram_tim_1);
+ writel(regs-sdram_tim1, emif_reg-emif_sdram_tim_1_shdw);
+ writel(regs-sdram_tim2, emif_reg-emif_sdram_tim_2);
+ writel(regs-sdram_tim2, emif_reg-emif_sdram_tim_2_shdw);
+ writel(regs-sdram_tim3, emif_reg-emif_sdram_tim_3);
+ writel(regs-sdram_tim3, emif_reg-emif_sdram_tim_3_shdw);
}
/**
* Configure DDR PHY
*/
-void config_ddr_phy(struct ddr_phy_control *p)
+void config_ddr_phy(const struct emif_regs *regs)
{
- writel(p-reg, emif_reg-emif_ddr_phy_ctrl_1);
- writel(p-reg_sh, emif_reg-emif_ddr_phy_ctrl_1_shdw);
+ writel(regs-emif_ddr_phy_ctlr_1, emif_reg-emif_ddr_phy_ctrl_1);
+ writel(regs-emif_ddr_phy_ctlr_1, emif_reg-emif_ddr_phy_ctrl_1_shdw);
}
/**
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c
b/arch/arm/cpu/armv7/am33xx/emif4.c
index 66ab892..0190ec6 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -90,6 +90,15 @@ static const struct cmd_control ddr2_cmd_ctrl_data = {
.cmd2iclkout = DDR2_INVERT_CLKOUT,
};
+static const struct emif_regs ddr2_emif_reg_data = {
+ .sdram_config = DDR2_EMIF_SDCFG,
+ .ref_ctrl = DDR2_EMIF_SDREF,
+ .sdram_tim1 = DDR2_EMIF_TIM1,
+ .sdram_tim2 = DDR2_EMIF_TIM2,
+ .sdram_tim3 = DDR2_EMIF_TIM3,
+ .emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY,
+};
+
static void config_vtp(void)
{
writel(readl(vtpreg-vtp0ctrlreg) | VTP_CTRL_ENABLE,
@@ -105,35 +114,6 @@ static void config_vtp(void)
;
}
-static void config_emif_ddr2(void)
-{
- struct sdram_config cfg;
- struct sdram_timing tmg;
- struct ddr_phy_control phyc;
-
- /* Program EMIF0 CFG Registers */
- phyc.reg = DDR2_EMIF_READ_LATENCY;
- phyc.reg_sh = DDR2_EMIF_READ_LATENCY;
- phyc.reg2 = DDR2_EMIF_READ_LATENCY;
-
- tmg.time1 = DDR2_EMIF_TIM1;
- tmg.time1_sh = DDR2_EMIF_TIM1;
- tmg.time2 = DDR2_EMIF_TIM2;
- tmg.time2_sh = DDR2_EMIF_TIM2;
- tmg.time3 = DDR2_EMIF_TIM3;
- tmg.time3_sh = DDR2_EMIF_TIM3;
-
- cfg.sdrcr = DDR2_EMIF_SDCFG;
- cfg.sdrcr2 = DDR2_EMIF_SDCFG;
- cfg.refresh = DDR2_EMIF_SDREF;
- cfg.refresh_sh = DDR2_EMIF_SDREF;
-
- /* Program EMIF instance */
- config_ddr_phy(phyc);
- set_sdram_timings(tmg);
- config_sdram(cfg);
-}
-
void config_ddr(short ddr_type)
{
struct ddr_ioctrl ioctrl;
@@ -163,7 +143,10 @@ void config_ddr(short ddr_type)
/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, ddrctrl-ddrckectrl);
- config_emif_ddr2();
+ /* Program EMIF instance */
+ config_ddr_phy(ddr2_emif_reg_data);
+ set_sdram_timings(ddr2_emif_reg_data);
+ config_sdram(ddr2_emif_reg_data);
}
}
#endif
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 997480b..7806e1b 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -20,6 +20,7 @@
#define _DDR_DEFS_H
#include asm/arch/hardware.h
+#include asm/emif.h
/* AM335X EMIF Register values */
#define VTP_CTRL_READY (0x1 5)
[U-Boot] [PATCH 14/17] am33xx: Turn a number of 'int' functions to 'void'
A number of memory initalization functions were int and always returned
0. Further it's not feasible to be doing error checking here, so simply
turn them into void functions.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/ddr.c | 29 ++-
arch/arm/cpu/armv7/am33xx/emif4.c | 16 +++
arch/arm/include/asm/arch-am33xx/ddr_defs.h | 12 +--
3 files changed, 15 insertions(+), 42 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index b4b3c01..7ac144a 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -40,26 +40,19 @@ static struct ddr_cmdtctrl *ioctrl_reg = {
(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
/**
- * As a convention, all functions here return 0 on success
- * -1 on failure.
- */
-
-/**
* Configure SDRAM
*/
-int config_sdram(struct sdram_config *cfg)
+void config_sdram(struct sdram_config *cfg)
{
writel(cfg-refresh, emif_reg-emif_sdram_ref_ctrl);
writel(cfg-refresh_sh, emif_reg-emif_sdram_ref_ctrl_shdw);
writel(cfg-sdrcr, emif_reg-emif_sdram_config);
-
- return 0;
}
/**
* Set SDRAM timings
*/
-int set_sdram_timings(struct sdram_timing *t)
+void set_sdram_timings(struct sdram_timing *t)
{
writel(t-time1, emif_reg-emif_sdram_tim_1);
writel(t-time1_sh, emif_reg-emif_sdram_tim_1_shdw);
@@ -67,25 +60,21 @@ int set_sdram_timings(struct sdram_timing *t)
writel(t-time2_sh, emif_reg-emif_sdram_tim_2_shdw);
writel(t-time3, emif_reg-emif_sdram_tim_3);
writel(t-time3_sh, emif_reg-emif_sdram_tim_3_shdw);
-
- return 0;
}
/**
* Configure DDR PHY
*/
-int config_ddr_phy(struct ddr_phy_control *p)
+void config_ddr_phy(struct ddr_phy_control *p)
{
writel(p-reg, emif_reg-emif_ddr_phy_ctrl_1);
writel(p-reg_sh, emif_reg-emif_ddr_phy_ctrl_1_shdw);
-
- return 0;
}
/**
* Configure DDR CMD control registers
*/
-int config_cmd_ctrl(const struct cmd_control *cmd)
+void config_cmd_ctrl(const struct cmd_control *cmd)
{
writel(cmd-cmd0csratio, ddr_reg[0]-cm0csratio);
writel(cmd-cmd0csforce, ddr_reg[0]-cm0csforce);
@@ -104,14 +93,12 @@ int config_cmd_ctrl(const struct cmd_control *cmd)
writel(cmd-cmd2csdelay, ddr_reg[0]-cm2csdelay);
writel(cmd-cmd2dldiff, ddr_reg[0]-cm2dldiff);
writel(cmd-cmd2iclkout, ddr_reg[0]-cm2iclkout);
-
- return 0;
}
/**
* Configure DDR DATA registers
*/
-int config_ddr_data(int macrono, const struct ddr_data *data)
+void config_ddr_data(int macrono, const struct ddr_data *data)
{
writel(data-datardsratio0, ddr_reg[macrono]-dt0rdsratio0);
writel(data-datardsratio1, ddr_reg[macrono]-dt0rdsratio1);
@@ -131,17 +118,13 @@ int config_ddr_data(int macrono, const struct ddr_data
*data)
writel(data-datawrsratio1, ddr_reg[macrono]-dt0wrsratio1);
writel(data-datadldiff0, ddr_reg[macrono]-dt0dldiff0);
-
- return 0;
}
-int config_io_ctrl(struct ddr_ioctrl *ioctrl)
+void config_io_ctrl(struct ddr_ioctrl *ioctrl)
{
writel(ioctrl-cmd1ctl, ioctrl_reg-cm0ioctl);
writel(ioctrl-cmd2ctl, ioctrl_reg-cm1ioctl);
writel(ioctrl-cmd3ctl, ioctrl_reg-cm2ioctl);
writel(ioctrl-data1ctl, ioctrl_reg-dt0ioctl);
writel(ioctrl-data2ctl, ioctrl_reg-dt1ioctl);
-
- return 0;
}
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c
b/arch/arm/cpu/armv7/am33xx/emif4.c
index e04e970..66ab892 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -107,7 +107,6 @@ static void config_vtp(void)
static void config_emif_ddr2(void)
{
- int ret;
struct sdram_config cfg;
struct sdram_timing tmg;
struct ddr_phy_control phyc;
@@ -130,18 +129,9 @@ static void config_emif_ddr2(void)
cfg.refresh_sh = DDR2_EMIF_SDREF;
/* Program EMIF instance */
- ret = config_ddr_phy(phyc);
- if (ret 0)
- printf(Couldn't configure phyc\n);
-
-
- ret = set_sdram_timings(tmg);
- if (ret 0)
- printf(Couldn't configure timings\n);
-
- ret = config_sdram(cfg);
- if (ret 0)
- printf(Couldn't configure SDRAM\n);
+ config_ddr_phy(phyc);
+ set_sdram_timings(tmg);
+ config_sdram(cfg);
}
void config_ddr(short ddr_type)
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index f755736..997480b 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -82,17 +82,17 @@ struct sdram_config {
/**
* Configure SDRAM
*/
-int config_sdram(struct sdram_config *cfg);
+void config_sdram(struct sdram_config *cfg);
/**
* Set SDRAM timings
*/
-int set_sdram_timings(struct sdram_timing *val);
+void set_sdram_timings(struct sdram_timing *val);
[U-Boot] [PATCH 17/17] am33xx: Do not touch 'ratio1' fields
The various ratio1 fields are not documented in any of the documentation
I can find. Removing these and testing has yielded success, so remove
the code that sets them and move their locations into the reserved
fields.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/ddr.c | 11 ---
arch/arm/cpu/armv7/am33xx/emif4.c |6 --
arch/arm/include/asm/arch-am33xx/ddr_defs.h | 25 +++--
3 files changed, 7 insertions(+), 35 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index 597d62f..59ca51f 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -101,22 +101,11 @@ void config_cmd_ctrl(const struct cmd_control *cmd)
void config_ddr_data(int macrono, const struct ddr_data *data)
{
writel(data-datardsratio0, ddr_reg[macrono]-dt0rdsratio0);
- writel(data-datardsratio1, ddr_reg[macrono]-dt0rdsratio1);
-
writel(data-datawdsratio0, ddr_reg[macrono]-dt0wdsratio0);
- writel(data-datawdsratio1, ddr_reg[macrono]-dt0wdsratio1);
-
writel(data-datawiratio0, ddr_reg[macrono]-dt0wiratio0);
- writel(data-datawiratio1, ddr_reg[macrono]-dt0wiratio1);
writel(data-datagiratio0, ddr_reg[macrono]-dt0giratio0);
- writel(data-datagiratio1, ddr_reg[macrono]-dt0giratio1);
-
writel(data-datafwsratio0, ddr_reg[macrono]-dt0fwsratio0);
- writel(data-datafwsratio1, ddr_reg[macrono]-dt0fwsratio1);
-
writel(data-datawrsratio0, ddr_reg[macrono]-dt0wrsratio0);
- writel(data-datawrsratio1, ddr_reg[macrono]-dt0wrsratio1);
-
writel(data-datadldiff0, ddr_reg[macrono]-dt0dldiff0);
}
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c
b/arch/arm/cpu/armv7/am33xx/emif4.c
index 3219045..ace3d26 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -51,22 +51,16 @@ void dram_init_banksize(void)
static const struct ddr_data ddr2_data = {
.datardsratio0 = ((DDR2_RD_DQS30)|(DDR2_RD_DQS20)
|(DDR2_RD_DQS10)|(DDR2_RD_DQS0)),
- .datardsratio1 = DDR2_RD_DQS2,
.datawdsratio0 = ((DDR2_WR_DQS30)|(DDR2_WR_DQS20)
|(DDR2_WR_DQS10)|(DDR2_WR_DQS0)),
- .datawdsratio1 = DDR2_WR_DQS2,
.datawiratio0 = ((DDR2_PHY_WRLVL30)|(DDR2_PHY_WRLVL20)
|(DDR2_PHY_WRLVL10)|(DDR2_PHY_WRLVL0)),
- .datawiratio1 = DDR2_PHY_WRLVL2,
.datagiratio0 = ((DDR2_PHY_GATELVL30)|(DDR2_PHY_GATELVL20)
|(DDR2_PHY_GATELVL10)|(DDR2_PHY_GATELVL0)),
- .datagiratio1 = DDR2_PHY_GATELVL2,
.datafwsratio0 = ((DDR2_PHY_FIFO_WE30)|(DDR2_PHY_FIFO_WE20)
|(DDR2_PHY_FIFO_WE10)|(DDR2_PHY_FIFO_WE0)),
- .datafwsratio1 = DDR2_PHY_FIFO_WE2,
.datawrsratio0 = ((DDR2_PHY_WR_DATA30)|(DDR2_PHY_WR_DATA20)
|(DDR2_PHY_WR_DATA10)|(DDR2_PHY_WR_DATA0)),
- .datawrsratio1 = DDR2_PHY_WR_DATA2,
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index ebd3077..b37b161 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -88,25 +88,20 @@ struct ddr_regs {
unsigned int cm2iclkout;/* offset 0x094 */
unsigned int resv3[12];
unsigned int dt0rdsratio0; /* offset 0x0C8 */
- unsigned int dt0rdsratio1; /* offset 0x0CC */
- unsigned int resv4[3];
+ unsigned int resv4[4];
unsigned int dt0wdsratio0; /* offset 0x0DC */
- unsigned int dt0wdsratio1; /* offset 0x0E0 */
- unsigned int resv5[3];
+ unsigned int resv5[4];
unsigned int dt0wiratio0; /* offset 0x0F0 */
- unsigned int dt0wiratio1; /* offset 0x0F4 */
+ unsigned int resv6;
unsigned int dt0giratio0; /* offset 0x0FC */
- unsigned int dt0giratio1; /* offset 0x100 */
- unsigned int resv6[1];
+ unsigned int resv7[2];
unsigned int dt0fwsratio0; /* offset 0x108 */
- unsigned int dt0fwsratio1; /* offset 0x10C */
- unsigned int resv7[4];
+ unsigned int resv8[5];
unsigned int dt0wrsratio0; /* offset 0x120 */
- unsigned int dt0wrsratio1; /* offset 0x124 */
- unsigned int resv8[3];
+ unsigned int resv9[4];
unsigned int dt0rdelays0; /* offset 0x134 */
unsigned int dt0dldiff0;/* offset 0x138 */
- unsigned int resv9[39];
+ unsigned int resv10[39];
unsigned int dt1rdelays0; /* offset 0x1D8 */
};
@@ -136,17 +131,11 @@ struct cmd_control {
*/
struct ddr_data {
unsigned long datardsratio0;
- unsigned long datardsratio1;
unsigned long datawdsratio0;
- unsigned long datawdsratio1;
Re: [U-Boot] multichannel mmc strangeness on omap
On Mon, Jul 30, 2012 at 7:27 AM, Tom Rini tr...@ti.com wrote: After adding a few printf's, it seems that the crash/hang is occurring when calling env_relocate_spec in env_nand.c, which of course is completely unrelated code! I've spent some time scratching my head against a hang in the same spot, on am335x. I only have seen it when booting from NAND (same image from MMC or UART is fine). Further, it only showed up when a change was made in another driver which isn't even entered before the hang. In order to keep making progress on hardware bringup I swapped the base register pointer setup for mmc2 and mmc3 since enabling mmc2 in the board file didn't seem to cause the hang. With this change the mmc3 port hardware worked as expected. What a strange bug! I have a feeling that this is going to be a real bear to find root cause. Steve ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [u-boot-arm/next RESEND PATCH 0/3] OMAP3: igep00x0: add nand flash and SPL support
On Sat, Jul 28, 2012 at 01:19:31PM +0200, Javier Martinez Canillas wrote: IGEP-based boards can have two different flash memories, a OneNAND or a NAND device. Since u-boot still lacks of a device model to be the able to look at run-time which memory type is available on a the board, a built time config option is needed to choose which memory to use. This is a resend of a patch-set that adds both a config option for the nand memory type and SPL support to IGEP-based boards. The patch-set is composed of the following patches: [u-boot-arm/next RESEND PATCH 1/3] OMAP3: igep00x0: Add config [u-boot-arm/next RESEND PATCH 2/3] OMAP3: mem: Add Numonyx OneNAND [u-boot-arm/next RESEND PATCH 3/3] OMAP3: igep00x0: add SPL support This all looks good, barring comments from someone else, I'll pick this up Friday or so. -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Building u-boot for iMX28 and getting error in mkimage of missing command line parameter CONFIG_IMX_CONFIG
Here is my log. It stops at the done, booting kernel.I tried
setting the console to ttyAM0 and no change. I don't think its booting
as I don't see the LCD flash and no penguin. The odd this is that I
built the latest kernel for iMX and this uboot will boot it. I also
included my u-boot environment settings at the end.
Thanks,
Bills
U-Boot 2012.07-rc1-08235-g7c5f511 (Jul 26 2012 - 12:00:38)
Freescale i.MX28 family at 454 MHz
BOOT: SSP SD/MMC #0, 3V3
I2C: ready
DRAM: 128 MiB
MMC: MXS MMC: 0
In:serial
Out: serial
Err: serial
Net: FEC0, FEC1
Hit any key to stop autoboot: 0
Booting from net ...
BOOTP broadcast 1
*** Unhandled DHCP Option in OFFER/ACK: 42
*** Unhandled DHCP Option in OFFER/ACK: 44
*** Unhandled DHCP Option in OFFER/ACK: 42
*** Unhandled DHCP Option in OFFER/ACK: 44
DHCP client bound to address 192.168.0.240
Using FEC0 device
TFTP from server 192.168.0.204; our IP address is 192.168.0.240
Filename 'uImage'.
Load address: 0x4200
Loading: #
#
#
#
#
#
#
##
done
Bytes transferred = 2562232 (2718b8 hex)
## Booting kernel from Legacy Image at 4200 ...
Image Name: Linux-2.6.35.3-571-gcca29a0
Created: 2012-07-12 15:53:55 UTC
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size:2562168 Bytes = 2.4 MiB
Load Address: 40008000
Entry Point: 40008000
Verifying Checksum ... OK
Loading Kernel Image ... OK
OK
Starting kernel ...
Uncompressing Linux... done, booting the kernel.
U-boot environment settings:
U-Boot 2012.07-rc1-08235-g7c5f511 (Jul 26 2012 - 12:00:38)
Freescale i.MX28 family at 454 MHz
BOOT: SSP SD/MMC #0, 3V3
I2C: ready
DRAM: 128 MiB
MMC: MXS MMC: 0
In:serial
Out: serial
Err: serial
Net: FEC0, FEC1
Hit any key to stop autoboot: 0
MX28EVK U-Boot printenv
baudrate=115200
bootargs=console=ttyAMA0,115200n8 debug root=/dev/nfs ip=dhcp
nfsroot=192.168.0.204:/tools/rootfs,v3,tcp fec_mac=
bootcmd=run bootcmd_net
bootcmd_net=echo Booting from net ...; run netargs; dhcp ${uimage}; bootm
bootdelay=3
bootfile=uImage
console=ttyAMA0
console_fsl=console=ttyAM0console_mainline=console=ttyAMA0netargs=setenv
bootargs console=${console_mainline}root=/dev/nfs ip=dhcp
nfsroot=${serverip}:${nfsroot}
console_mainline=ttyAMA0
ethact=FEC0
ipaddr=192.168.0.19
loadaddr=0x4200
netargs=setenv bootargs console=ttyAMA0,115200
netmask=255.255.255.0
nfsroot=/tools/rootfs
serverip=192.168.0.204
stderr=serial
stdin=serial
stdout=serial
ver=U-Boot 2012.07-rc1-08235-g7c5f511 (Jul 26 2012 - 12:00:38)
Environment size: 770/16380 bytes
MX28EVK U-Boot
On 7/28/2012 3:19 PM, Fabio Estevam wrote:
On Fri, Jul 27, 2012 at 3:15 PM, Fabio Estevamfeste...@gmail.com wrote:
On Fri, Jul 27, 2012 at 12:35 PM, Billbsou...@techsi.com wrote:
Thanks. I tried that and got the same results. Are there any debug/logging
that I can use to see what's going on?
I just tried it here and 2012.07-rc3 does not boot for me too.
I was using the wrong LOADADDR for mx28, and that's the reason it did not boot.
What is the error you are seeing? Can you post your log?
Here is the log on 2012.07-rc3:
...
U-Boot 2012.07-rc3 (Jul 28 2012 - 17:08:24)
Freescale i.MX28 family at 454 MHz
BOOT: SSP SD/MMC #0, 3V3
I2C: ready
DRAM: 128 MiB
MMC: MXS MMC: 0
In:serial
Out: serial
Err: serial
Net: FEC0, FEC1
Hit any key to stop autoboot: 0
Using FEC0 device
TFTP from server 192.168.1.1; our IP address is 192.168.1.2
Filename 'uImage'.
Load address: 0x4200
Loading: #
#
#
#
#
#
#
##
done
Bytes transferred = 2358008 (23faf8 hex)
## Booting kernel from Legacy Image at 4200 ...
Image Name: Linux-3.5.0-next-20120727-4-
Created: 2012-07-28 20:06:58 UTC
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size:2357944 Bytes = 2.2 MiB
Load Address: 40008000
Entry Point: 40008000
Verifying Checksum ... OK
Loading Kernel
Re: [U-Boot] [PATCH v3 0/8] CPSW switch plus SPL net support
On Wed, Jul 25, 2012 at 02:22:15AM +0400, Ilya Yanok wrote: These patches add CPSW switch driver and enable support for it on TI AM335x based boards. This version is rebased on top of u-boot-ti/next. Also now CPSW driver uses internal controller memory for DMA descriptors so coherent allocator is no longer a requirement for this series. The second part of the series provides support for networking in SPL. These patches try to use network infrasctructure as is, without trying to cut some minimal set of it, so the resulting SPL image is quite big and only useful for boards with plenty of SRAM/OCRAM (like TI AM335x based ones). Parts 1 to 5 look good, barring comments from someone else, I'll pick those up Friday or so and you can v4 just 6/7/8. -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Building u-boot for iMX28 and getting error in mkimage of missing command line parameter CONFIG_IMX_CONFIG
On Mon, Jul 30, 2012 at 2:06 PM, Bill bsou...@techsi.com wrote:
Here is my log. It stops at the done, booting kernel.I tried setting
the console to ttyAM0 and no change. I don't think its booting as I don't
see the LCD flash and no penguin. The odd this is that I built the latest
kernel for iMX and this uboot will boot it. I also included my u-boot
Do you mean you are able to boot a mainline kernel, but not a 2.6.35 kernel?
environment settings at the end.
U-boot environment settings:
U-Boot 2012.07-rc1-08235-g7c5f511 (Jul 26 2012 - 12:00:38)
Freescale i.MX28 family at 454 MHz
BOOT: SSP SD/MMC #0, 3V3
I2C: ready
DRAM: 128 MiB
MMC: MXS MMC: 0
In:serial
Out: serial
Err: serial
Net: FEC0, FEC1
Hit any key to stop autoboot: 0
MX28EVK U-Boot printenv
baudrate=115200
bootargs=console=ttyAMA0,115200n8 debug root=/dev/nfs ip=dhcp
Please change it to ttyAM0.
nfsroot=192.168.0.204:/tools/rootfs,v3,tcp fec_mac=
bootcmd=run bootcmd_net
bootcmd_net=echo Booting from net ...; run netargs; dhcp ${uimage}; bootm
bootdelay=3
bootfile=uImage
console=ttyAMA0
If you boot a 2.6.35 you need to use ttyAM0.
console_fsl=console=ttyAM0console_mainline=console=ttyAMA0netargs=setenv
This line seems to be without any spaces. Are you sure this is correct?
Make sure your kernel command line passes ttyAM0 instead of ttyAMA0 if
you want to boot a 2.6.35 kernel.
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Re: [U-Boot] [PATCH 3/3] DaVinci DA8xx: replace magic number for DDR speed
On Mon, Jul 30, 2012 at 04:34:39PM +, Laurence Withers wrote:
On Mon, Jul 30, 2012 at 04:30:15PM +, Laurence Withers wrote:
Replace a magic number for the DDR2/mDDR PHY clock ID with a proper
definition. In addition, don't request this clock ID on DA830 hardware,
which does not have a DDR2/mDDR PHY (or associated PLL controller).
Signed-off-by: Laurence Withers lwith...@guralp.com
Cc: Prabhakar Lad prabhakar.cse...@gmail.com
---
arch/arm/cpu/arm926ejs/davinci/cpu.c |3 ++-
arch/arm/include/asm/arch-davinci/hardware.h |2 ++
2 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c
b/arch/arm/cpu/arm926ejs/davinci/cpu.c
index 4bdb08b..b31add8 100644
--- a/arch/arm/cpu/arm926ejs/davinci/cpu.c
+++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c
@@ -122,7 +122,8 @@ int set_cpu_clk_info(void)
{
gd-bd-bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 100;
/* DDR PHY uses an x2 input clock */
- gd-bd-bi_ddr_freq = clk_get(0x10001) / 100;
+ gd-bd-bi_ddr_freq = cpu_is_da830() ? 0 :
+ (clk_get(DAVINCI_DDR_CLKID) / 100);
gd-bd-bi_dsp_freq = 0;
return 0;
}
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
b/arch/arm/include/asm/arch-davinci/hardware.h
index 0fce940..7f3dcc2 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -459,10 +459,12 @@ enum davinci_clk_ids {
DAVINCI_PLL0_SYSCLK2= DAVINCI_PLLC0_FLAG | 2,
DAVINCI_PLL0_SYSCLK4= DAVINCI_PLLC0_FLAG | 4,
DAVINCI_PLL0_SYSCLK6= DAVINCI_PLLC0_FLAG | 6,
+ DAVINCI_PLL1_SYSCLK1= DAVINCI_PLLC1_FLAG | 1,
DAVINCI_PLL1_SYSCLK2= DAVINCI_PLLC1_FLAG | 2,
/* map peripherals to clock IDs */
DAVINCI_ARM_CLKID = DAVINCI_PLL0_SYSCLK6,
+ DAVINCI_DDR_CLKID = DAVINCI_PLL1_SYSCLK1,
DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4,
DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2,
DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2,
--
1.7.2.5
Hi,
This patch does depend on my earlier patch to tidy up the definition of
set_cpu_clk_info() :
http://lists.denx.de/pipermail/u-boot/2012-July/129205.html
Can you please post everything as a series of 4 patches so that we don't
add and then replace the magic value with the enum? Other than that,
I'm happy with the series and will apply the updated series on Friday or
so, thanks!
--
Tom
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Re: [U-Boot] [PATCH v4 0/6] tegra: Add NAND flash support
Simon, -Original Message- From: Simon Glass [mailto:s...@chromium.org] Sent: Sunday, July 29, 2012 11:53 PM To: U-Boot Mailing List Cc: Tom Warren; Stephen Warren; Scott Wood; Simon Glass Subject: [PATCH v4 0/6] tegra: Add NAND flash support This series adds NAND flash support to Tegra and enables it on Seaboard. Included here is a proposed device tree binding with most of the properties private to nvidia,. The binding includes information about the NAND controller as well as the connected NAND device. The Seaboard has a Hynix HY27UF4G2B. The driver supports ECC-based access and uses DMA and NAND acceleration features of the Tegra SOC to provide access at reasonable speed. Applied to u-boot-tegra/master AOK. ./MAKEALL -s tegra20 AOK. Able to erase/read/write NAND on my Seaboard AOK. Tested-by: Tom Warren twar...@nvidia.com Thanks, I'll upload a new u-boot-tegra/master and /next with this change later once I see some ACKs. Tom -- nvpublic Changes in v2: - Add new patch to align default buffers in nand_base - Added comment about the behaviour of the 'resp' register - Call set_bus_width_page_size() at init to report errors earlier - Change set_bus_width_page_size() to return an error when needed - Change timing structure member to u32 to match device tree - Check for supported bus width in board_nand_init() - Fix tegra nand header file to remove BIT defines - Implement a dummy nand_select_chip() instead of nand_hwcontro() - Make nand_command() display an error on an unknown command - Minor code tidy-ups in driver for style - Move cache logic into a separate dma_prepare() function - Remove CMD_TRANS_SIZE_BYTESx enum - Remove space after casts - Remove use of 'register' variables - Rename struct nand_info to struct nand_drv to avoid nand_info_t confusion - Support 4096 byte page devices, drop 1024 and 2048 - Tidy up nand_waitfor_cmd_completion() logic - Update NAND binding to add nvidia, prefix - Use s32 for device tree integer values Changes in v3: - Add reg property for unit address (should be used for chip select) - Change note in fdt binding about the need for a hardware-specific binding - Fix up typos in fdt binding, and rename the file - Update fdt binding to make everything Nvidia-specific Changes in v4: - Align buffer length to cache line size in dma_prepare() - Fix Write Page 0x0 timeout with ECC error on 4.4.1 - Fix the issue that read_byte can read at most 4 times - Get some information from Read ID data instead of from device tree - In nand_command, set NAND_CMD_RNDOUT as unsupported command - Modify eccoob layout - Move to using CONFIG_SYS_NAND_SELF_INIT - Remove DEFAULT from comment because that function is not default - Remove fdt bindings related to page structure - Remove local read_buf and write_buf functions - Remove some fields in fdt_nand structure - Rename CONFIG_TEGRA2_NAND to CONFIG_TEGRA_NAND - Rename variables my_* as our_* - Use virt_to_phys() when filling address register Jim Lin (1): tegra: nand: Add Tegra NAND driver Simon Glass (5): nand: Try to align the default buffers tegra: Add NAND support to funcmux tegra: fdt: Add NAND controller binding and definitions tegra: fdt: Add NAND definitions to fdt tegra: Enable NAND on Seaboard arch/arm/cpu/tegra20-common/funcmux.c |7 + arch/arm/dts/tegra20.dtsi |7 + arch/arm/include/asm/arch-tegra20/funcmux.h|3 + arch/arm/include/asm/arch-tegra20/tegra20.h|1 + board/nvidia/dts/tegra20-seaboard.dts | 10 + .../nand/nvidia,tegra20-nand.txt | 53 + drivers/mtd/nand/Makefile |1 + drivers/mtd/nand/nand_base.c |3 +- drivers/mtd/nand/tegra_nand.c | 1026 drivers/mtd/nand/tegra_nand.h | 257 + include/configs/seaboard.h |9 + include/configs/tegra20-common.h |2 + include/fdtdec.h |1 + include/linux/mtd/nand.h |7 +- lib/fdtdec.c |1 + 15 files changed, 1384 insertions(+), 4 deletions(-) create mode 100644 doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt create mode 100644 drivers/mtd/nand/tegra_nand.c create mode 100644 drivers/mtd/nand/tegra_nand.h -- 1.7.7.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 0/6] tegra: Add NAND flash support
On 07/30/2012 12:53 AM, Simon Glass wrote: This series adds NAND flash support to Tegra and enables it on Seaboard. Included here is a proposed device tree binding with most of the properties private to nvidia,. The binding includes information about the NAND controller as well as the connected NAND device. The Seaboard has a Hynix HY27UF4G2B. The driver supports ECC-based access and uses DMA and NAND acceleration features of the Tegra SOC to provide access at reasonable speed. Along with a couple of patches that I'll post momentarily, this works for me on Harmony, so: Tested-by: Stephen Warren swar...@wwwdotorg.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] tegra: enable NAND on Harmony
From: Stephen Warren swar...@nvidia.com
Signed-off-by: Stephen Warren swar...@nvidia.com
---
board/nvidia/dts/tegra20-harmony.dts | 10 ++
include/configs/harmony.h|9 -
2 files changed, 18 insertions(+), 1 deletions(-)
diff --git a/board/nvidia/dts/tegra20-harmony.dts
b/board/nvidia/dts/tegra20-harmony.dts
index c351954..ca5facb 100644
--- a/board/nvidia/dts/tegra20-harmony.dts
+++ b/board/nvidia/dts/tegra20-harmony.dts
@@ -54,4 +54,14 @@
usb@c5004000 {
status = disabled;
};
+
+ nand-controller@70008000 {
+ nvidia,wp-gpios = gpio 23 0; /* PC7 */
+ nvidia,width = 8;
+ nvidia,timing = 26 100 20 80 20 10 12 10 70;
+ nand@0 {
+ reg = 0;
+ compatible = hynix,hy27uf4g2b, nand-flash;
+ };
+ };
};
diff --git a/include/configs/harmony.h b/include/configs/harmony.h
index d0555c1..85059b9 100644
--- a/include/configs/harmony.h
+++ b/include/configs/harmony.h
@@ -62,8 +62,15 @@
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_TEGRA_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE TEGRA20_NAND_BASE
+
/* Environment not stored */
-#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sector size */
/* USB Host support */
#define CONFIG_USB_EHCI
--
1.7.0.4
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[U-Boot] [PATCH] env_nand: align NAND buffers
From: Stephen Warren swar...@nvidia.com
This allows cache flush/invalidate operations to succeed on the buffers.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
common/env_nand.c | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/common/env_nand.c b/common/env_nand.c
index e8daec9..e635472 100644
--- a/common/env_nand.c
+++ b/common/env_nand.c
@@ -226,7 +226,7 @@ int saveenv(void)
int saveenv(void)
{
int ret = 0;
- env_t env_new;
+ ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, sizeof(env_t));
ssize_t len;
char*res;
nand_erase_options_t nand_erase_options;
@@ -238,20 +238,20 @@ int saveenv(void)
if (CONFIG_ENV_RANGE CONFIG_ENV_SIZE)
return 1;
- res = (char *)env_new.data;
+ res = (char *)env_new-data;
len = hexport_r(env_htab, '\0', res, ENV_SIZE, 0, NULL);
if (len 0) {
error(Cannot export environment: errno = %d\n, errno);
return 1;
}
- env_new.crc = crc32(0, env_new.data, ENV_SIZE);
+ env_new-crc = crc32(0, env_new-data, ENV_SIZE);
puts(Erasing Nand...\n);
if (nand_erase_opts(nand_info[0], nand_erase_options))
return 1;
puts(Writing to Nand... );
- if (writeenv(CONFIG_ENV_OFFSET, (u_char *)env_new)) {
+ if (writeenv(CONFIG_ENV_OFFSET, (u_char *)env_new)) {
puts(FAILED!\n);
return 1;
}
@@ -398,7 +398,7 @@ void env_relocate_spec(void)
{
#if !defined(ENV_IS_EMBEDDED)
int ret;
- char buf[CONFIG_ENV_SIZE];
+ ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
#if defined(CONFIG_ENV_OFFSET_OOB)
ret = get_nand_env_oob(nand_info[0], nand_env_oob_offset);
--
1.7.0.4
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Re: [U-Boot] [PATCH v4 0/6] tegra: Add NAND flash support
Stephen, -Original Message- From: Stephen Warren [mailto:swar...@wwwdotorg.org] Sent: Monday, July 30, 2012 10:34 AM To: Simon Glass Cc: U-Boot Mailing List; Tom Warren; Scott Wood Subject: Re: [PATCH v4 0/6] tegra: Add NAND flash support On 07/30/2012 12:53 AM, Simon Glass wrote: This series adds NAND flash support to Tegra and enables it on Seaboard. Included here is a proposed device tree binding with most of the properties private to nvidia,. The binding includes information about the NAND controller as well as the connected NAND device. The Seaboard has a Hynix HY27UF4G2B. The driver supports ECC-based access and uses DMA and NAND acceleration features of the Tegra SOC to provide access at reasonable speed. Along with a couple of patches that I'll post momentarily, this works for me on Harmony, so: Tested-by: Stephen Warren swar...@wwwdotorg.org Your two patches (Harmony NAND and env_nand) have been applied to u-boot-tegra/next (along w/Simon's NAND patchset, obviously), and pushed to denx.de. I'll apply them to u-boot-tegra/master when they're ACK'd along w/Simon's NAND work. Thanks, Tom -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/7] powerpc/82xx: merge mgcoge.h and mgcoge3ne.h into km82xx.h
On 07/30/2012 06:07 PM, Wolfgang Denk wrote:
Dear Gerlando Falauto,
In message5016a093.6040...@keymile.com you wrote:
The way I understand it, such renaming information is built on the fly
while building the patch (like you're suggesting, it's a parameter to
git format-patch, not to the commit itself).
Yes, and I fail to understand where your problems could be.
However, I've been struggling to get this same kind of message through
git-format-patch. No way, I don't know why. I tried with -M, -M -C,
-M10%, adding [diff]\n renames = copies to ~/.gitconfig, with both
versions below, nothing. Detected as a rename at commit time, it's a
plain delete/create commit at patch creation time.
I see this (doing it all manually for testing):
- patch -p1/tmp/patch
- git rm include/configs/mgcoge.h include/configs/mgcoge3ne.h
- git add include/configs/km82xx.h
- git commit -s -m 'test 1'
- git format-patch -M -C --stdout HEAD^/tmp/patch
- less /tmp/patch
From 1d9ce92a542d139b78291fb4e437e538d647d55b Mon Sep 17 00:00:00 2001
From: Wolfgang Denkw...@denx.de
Date: Mon, 30 Jul 2012 17:57:53 +0200
Subject: [PATCH] test 1
Signed-off-by: Wolfgang Denkw...@denx.de
---
include/configs/{mgcoge3ne.h = km82xx.h} | 95
++---
include/configs/mgcoge.h | 93
2 files changed, 74 insertions(+), 114 deletions(-)
rename include/configs/{mgcoge3ne.h = km82xx.h} (55%)
delete mode 100644 include/configs/mgcoge.h
...
Oops, I forgot to git add boards.cfg here, but for this test it
makes no difference.
It turns out it's a bug/limitation of git 1.7.1.
I upgraded to 1.7.10.4 and 1.7.11.3 and now I get the same results as
you do (rename detected). See new patch as a follow-up.
[...]
In any case, I have no clue whether git would be able to correctly (i.e.
intelligently) apply such patch to a slightly different tree (e.g.
through cherry-pick or rebase).
So for instance, in your example above, what if file.1 (whose contents
is anyway moved into file.common, regardless of rename detection) is
slightly different?
It doesn't matter. If there are conflicts, and these can be resolved,
it works just the same.
I'm strongly convinced that if we want to track such changes for what
they are (code moving) so that they can be easily re-applied, we
should mark this explicitly. Even at the cost of creating multiple
patches if necessary. Since git isn't able to figure it out by itself,
No, on contrary. This is basicly an atomic change, and we should not
artificially split it. git should have no problems with such actions,
they are really not special in any way.
Renaming, I understand. But merging/splitting files, I guess they should
be treated differently (i.e., as such!) IMHO, if we want repeatability
and resilience to small changes.
But git doesn't (yet?) do that, and I think it should be worked around
some other way.
the only way I can think of doing this is splitting the commit into 3 parts:
No, please don't.
Since mgcoge and mgcoge3ne are the only km82xx boards, there is no
need to keep them as separate .h config files.
Therefore, make mgcoge3ne.h and mgcoge.h converge into a single
km82xx.h file.
Step 2 of 3: substitute include files through the following script:
INCLUDE_STMT='#include mgcoge.h'
INCLUDED=include/configs/mgcoge.h
INCLUDING=include/configs/km82xx.h
Argh No, this is not what we're going to do.
Alright, your call.
Thanks for your patience.
Gerlando
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[U-Boot] [PATCH v2 3/7] powerpc/82xx: merge mgcoge.h and mgcoge3ne.h into km82xx.h
Since mgcoge and mgcoge3ne are the only km82xx boards, there is no need
to keep them as separate .h config files.
Therefore, make mgcoge3ne.h and mgcoge.h converge into a single km82xx.h
file.
Signed-off-by: Gerlando Falauto gerlando.fala...@keymile.com
---
Changes from v1:
switched to git v1.7.11.3, used git format-patch -M -C
---
boards.cfg| 4 +-
include/configs/{mgcoge3ne.h = km82xx.h} | 58 ++-
include/configs/mgcoge.h | 93 ---
3 files changed, 59 insertions(+), 96 deletions(-)
rename include/configs/{mgcoge3ne.h = km82xx.h} (66%)
delete mode 100644 include/configs/mgcoge.h
diff --git a/boards.cfg b/boards.cfg
index 2d36d83..1af87c0 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -577,8 +577,8 @@ PQ2FADS-ZU_66MHz powerpc mpc8260
mpc8260ads freesca
PQ2FADS-ZU_66MHz_lowboot powerpc mpc8260 mpc8260ads
freescale -
MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=6600,SYS_TEXT_BASE=0xFF80
PQ2FADS-ZU_lowboot powerpc mpc8260 mpc8260ads
freescale -
MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF80
VoVPN-GW_66MHz powerpc mpc8260 vovpn-gw
funkwerk - VoVPN-GW:CLKIN_66MHz
-mgcoge powerpc mpc8260 km82xx
keymile
-mgcoge3nepowerpc mpc8260 km82xx
keymile
+mgcoge powerpc mpc8260 km82xx
keymile- km82xx:MGCOGE
+mgcoge3nepowerpc mpc8260 km82xx
keymile- km82xx:MGCOGE3NE
SCM powerpc mpc8260 -
siemens
TQM8255_AA powerpc mpc8260 tqm8260 tqc
- TQM8260:MPC8255,300MHz
TQM8260_AA powerpc mpc8260 tqm8260 tqc
- TQM8260:MPC8260,200MHz
diff --git a/include/configs/mgcoge3ne.h b/include/configs/km82xx.h
similarity index 66%
rename from include/configs/mgcoge3ne.h
rename to include/configs/km82xx.h
index 7ab03a0..5d62f4b 100644
--- a/include/configs/mgcoge3ne.h
+++ b/include/configs/km82xx.h
@@ -30,11 +30,21 @@
*/
#define CONFIG_MPC8247
-#define CONFIG_MGCOGE3NE
+/* MGCOGE */
+#if defined(CONFIG_MGCOGE)
+#define CONFIG_HOSTNAMEmgcoge
+#define CONFIG_KM_BOARD_EXTRA_ENV
+
+/* MGCOGE3NE */
+#elif defined(CONFIG_MGCOGE3NE)
#define CONFIG_HOSTNAMEmgcoge3ne
#define CONFIG_KM_82XX
#define CONFIG_KM_BOARD_EXTRA_ENV bobcatreset=true\0
+#else
+#error (Board unsupported)
+#endif
+
#defineCONFIG_SYS_TEXT_BASE0xFE00
/* include common defines/options for all Keymile boards */
@@ -46,6 +56,51 @@
#define CONFIG_SYS_FLASH_SIZE 32
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
+
+/* MGCOGE */
+#if defined(CONFIG_MGCOGE)
+#define CONFIG_SYS_MAX_FLASH_BANKS 3
+/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT 512
+
+#define CONFIG_SYS_FLASH_BASE_10x5000
+#define CONFIG_SYS_FLASH_SIZE_132
+#define CONFIG_SYS_FLASH_BASE_20x5200
+#define CONFIG_SYS_FLASH_SIZE_232
+
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
+ CONFIG_SYS_FLASH_BASE_1, \
+ CONFIG_SYS_FLASH_BASE_2 }
+#define MTDIDS_DEFAULT nor3=app
+
+/*
+ * Bank 1 - 60x bus SDRAM
+ */
+#define SDRAM_MAX_SIZE 0x0800 /* max. 128 MB */
+#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 20) /* less than 256 MB */
+
+/* SDRAM initialization values
+*/
+
+#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) \
+ ORxS_SDAM_MSK) |\
+ ORxS_BPD_8 |\
+ ORxS_ROWST_PBI0_A7 |\
+ ORxS_NUMR_13)
+
+#define CONFIG_SYS_PSDMR ( \
+ PSDMR_SDAM_A14_IS_A5|\
+ PSDMR_BSMA_A14_A16 |\
+ PSDMR_SDA10_PBI0_A9 |\
+ PSDMR_RFRC_5_CLK|\
+ PSDMR_PRETOACT_2W |\
+ PSDMR_ACTTORW_2W|\
+ PSDMR_LDOTOPRE_1C |\
+ PSDMR_WRC_1C|\
+ PSDMR_CL_2)
+
+/* MGCOGE3NE */
+#elif defined(CONFIG_MGCOGE3NE)
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
#define CONFIG_SYS_MAX_FLASH_SECT 1024/*
* max num of sects on one
@@ -86,6 +141,7 @@
Re: [U-Boot] [PATCH] hawkboard: Fix SPL Nand driver misconfiguration
Dear Linu Cherian, In message 1343377313-30301-1-git-send-email-linucher...@gmail.com you wrote: Hawkboard was using the wrong nand_read_page version for SPL image. As a side effect, the u-boot image loaded by the SPL from nand was getting corrupted. Enable CONFIG_SYS_NAND_HW_ECC_OOBFIRST to select the correct nand_read_page algorithm for SPL. Signed-off-by: Linu Cherian linucher...@gmail.com --- include/configs/hawkboard.h |1 + 1 files changed, 1 insertions(+), 0 deletions(-) Applied, thanks. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de On the subject of C program indentation: In My Egotistical Opinion, most people's C programs should be indented six feet downward and covered with dirt. - Blair P. Houghton ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/7] powerpc/82xx: move km/km82xx-common.h within km82xx.h
On 07/27/2012 07:31 PM, Wolfgang Denk wrote:
Dear Gerlando Falauto,
In message1343402200-32020-5-git-send-email-gerlando.fala...@keymile.com you
wrote:
The only file including km82xx-common.h is km82xx.h.
So there is no need to have it as a separate file.
Signed-off-by: Gerlando Falautogerlando.fala...@keymile.com
---
include/configs/km/km82xx-common.h | 317
include/configs/km82xx.h | 290 -
2 files changed, 289 insertions(+), 318 deletions(-)
delete mode 100644 include/configs/km/km82xx-common.h
Please also try with -M -C and see if this changes anything.
For this one patch I can't get git to detect renames.
I tried with git 1.7.1, 1.7.10.4, 1.7.11.3:
- git commit --amend
[xxx f9981ff] powerpc/82xx: move km/km82xx-common.h within km82xx.h
1 files changed, 124 insertions(+), 4 deletions(-)
rename include/configs/{km/km82xx-common.h = km82xx.h} (75%)
Notice how git commit DOES detect the rename, but the following
format-patch does NOT:
- git format-patch -M -C --stdout -1
From f9981ff849562c9d466d9429e0ec9a510a0d4b3c Mon Sep 17 00:00:00 2001
From: Gerlando Falauto gerlando.fala...@keymile.com
Date: Tue, 10 Jul 2012 18:13:27 +0200
Subject: [PATCH] ...
...
---
include/configs/km/km82xx-common.h | 317
include/configs/km82xx.h | 290
-
2 files changed, 289 insertions(+), 318 deletions(-)
delete mode 100644 include/configs/km/km82xx-common.h
...
#endif /* __CONFIG_H */
--
1.7.10.4
I guess the reason behind this is that km82xx.h is already existing.
Again, git can somehow track renames (i.e. one file's gone, another
one's brand new), but it does not detect merging of files.
As a matter of fact, if I rename the target file, i.e.:
- git mv include/configs/km82xx.h include/configs/km82xx-tmp.h
- git commit --amend
[xxx 49c85c3] powerpc/82xx: move km/km82xx-common.h within km82xx.h
2 files changed, 124 insertions(+), 153 deletions(-)
rename include/configs/{km/km82xx-common.h = km82xx-tmp.h} (75%)
delete mode 100644 include/configs/km82xx.h
- ~/bin/git format-patch -M -C -1 --stdout
From 49c85c351f65330746836bf90a06443a6b095b1e Mon Sep 17 00:00:00 2001
From: Gerlando Falauto gerlando.fala...@keymile.com
Date: Tue, 10 Jul 2012 18:13:27 +0200
Subject: [PATCH] ...
...
---
.../configs/{km/km82xx-common.h = km82xx-tmp.h} | 128
-
include/configs/km82xx.h | 149
2 files changed, 124 insertions(+), 153 deletions(-)
rename include/configs/{km/km82xx-common.h = km82xx-tmp.h} (75%)
delete mode 100644 include/configs/km82xx.h
diff --git a/include/configs/km/km82xx-common.h
b/include/configs/km82xx-tmp.h
similarity index 75%
rename from include/configs/km/km82xx-common.h
rename to include/configs/km82xx-tmp.h
index 2c763bb..9bfb8df 100644
THEN, AND ONLY THEN, do I get a rename detected.
And we would need an extra patch to rename it back...
Anyway, I believe the above patch, if applied to a tree with a slightly
different (let's say updated) km82xx.h, would fail upon the deletion of
km82xx.h, but would apply cleanly on km82xx-common.h (introducing
outdated chunks of km82xx.h though). Is that what we really want?
Thanks,
Gerlando
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Re: [U-Boot] Building u-boot for iMX28 and getting error in mkimage of missing command line parameter CONFIG_IMX_CONFIG
Progress! I switched all the references from ttyAMA0... to ttyAM0. Also changed netargs too. Now it starts to boot linux but hangs right after the line of: mxs_cpu_init: cpufreq init finished. In regards to your question, yes it was booting the mainline kernel. Here is the latest output from the boot. U-Boot 2012.07-rc1-08235-g7c5f511 (Jul 26 2012 - 12:00:38) Freescale i.MX28 family at 454 MHz BOOT: SSP SD/MMC #0, 3V3 I2C: ready DRAM: 128 MiB MMC: MXS MMC: 0 In:serial Out: serial Err: serial Net: FEC0, FEC1 Hit any key to stop autoboot: 0 Booting from net ... BOOTP broadcast 1 *** Unhandled DHCP Option in OFFER/ACK: 42 *** Unhandled DHCP Option in OFFER/ACK: 44 *** Unhandled DHCP Option in OFFER/ACK: 42 *** Unhandled DHCP Option in OFFER/ACK: 44 DHCP client bound to address 192.168.0.240 Using FEC0 device TFTP from server 192.168.0.204; our IP address is 192.168.0.240 Filename 'uImage'. Load address: 0x4200 Loading: # # # # # # # ## done Bytes transferred = 2562232 (2718b8 hex) ## Booting kernel from Legacy Image at 4200 ... Image Name: Linux-2.6.35.3-571-gcca29a0 Created: 2012-07-12 15:53:55 UTC Image Type: ARM Linux Kernel Image (uncompressed) Data Size:2562168 Bytes = 2.4 MiB Load Address: 40008000 Entry Point: 40008000 Verifying Checksum ... OK Loading Kernel Image ... OK OK Starting kernel ... Uncompressing Linux... done, booting the kernel. Linux version 2.6.35.3-571-gcca29a0 (blsousan@ubuntu) (gcc version 4.4.4 (4.4.4_09.06.2010) ) #1 PREEMPT Thu Jul 12 08:53:51 PDT 2012 CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177 CPU: VIVT data cache, VIVT instruction cache Machine: Freescale MX28EVK board Memory policy: ECC disabled, Data cache writeback Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512 Kernel command line: console=ttyAM0,115200 PID hash table entries: 512 (order: -1, 2048 bytes) Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) Memory: 128MB = 128MB total Memory: 124316k/124316k available, 6756k reserved, 0K highmem Virtual kernel memory layout: vector : 0x - 0x1000 ( 4 kB) fixmap : 0xfff0 - 0xfffe ( 896 kB) DMA : 0xfde0 - 0xffe0 ( 32 MB) vmalloc : 0xc880 - 0xf000 ( 632 MB) lowmem : 0xc000 - 0xc800 ( 128 MB) modules : 0xbf00 - 0xc000 ( 16 MB) .init : 0xc0008000 - 0xc003 ( 160 kB) .text : 0xc003 - 0xc04f7000 (4892 kB) .data : 0xc04f8000 - 0xc0535960 ( 247 kB) SLUB: Genslabs=11, HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 Hierarchical RCU implementation. RCU-based detection of stalled CPUs is disabled. Verbose stalled-CPUs detection is disabled. NR_IRQS:288 Console: colour dummy device 80x30 console [ttyAM0] enabled Calibrating delay loop... 226.09 BogoMIPS (lpj=1130496) pid_max: default: 32768 minimum: 301 Security Framework initialized SELinux: Initializing. Mount-cache hash table entries: 512 CPU: Testing write buffer coherency: ok regulator: core version 0.5 NET: Registered protocol family 16 regulator: vddd: 800 -- 1575 mV at 1500 mV fast normal regulator: vdddbo: 800 -- 1575 mV fast normal regulator: vdda: 1500 -- 2275 mV at 1800 mV fast normal vddio = 338, val=10 regulator: vddio: 2880 -- 3680 mV at 3380 mV fast normal regulator: overall_current: fast normal regulator: vbus5v: regulator: mxs-duart-1: fast normal regulator: mxs-bl-1: fast normal regulator: mxs-i2c-1: fast normal regulator: mmc_ssp-1: fast normal regulator: mmc_ssp-2: fast normal regulator: charger-1: fast normal regulator: power-test-1: fast normal regulator: cpufreq-1: fast normal i.MX IRAM pool: 124 KB@0xc882 usb DR wakeup device is registered IMX usb wakeup probe audit: cannot initialize inotify handle bio: create slab bio-0 at 0 SCSI subsystem initialized Freescale USB OTG Driver loaded, $Revision: 1.55 $ usbcore: registered new interface driver usbfs usbcore: registered new interface driver hub usbcore: registered new device driver usb Advanced Linux Sound Architecture Driver Version 1.0.23. Switching to clocksource mxs clock source NET: Registered protocol family 2 IP route cache hash table entries: 1024 (order: 0, 4096 bytes) TCP established hash table entries: 4096 (order: 3, 32768 bytes) TCP bind hash table
Re: [U-Boot] [PATCH 4/7] powerpc/82xx: move km/km82xx-common.h within km82xx.h
Dear Gerlando, In message 5016d241.4030...@keymile.com you wrote: Please also try with -M -C and see if this changes anything. For this one patch I can't get git to detect renames. Neither can I. Thanks for trying, though. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de How many Unix hacks does it take to change a light bulb? Let's see, can you use a shell script for that or does it need a C program? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [STATUS] v2012.07 released, Merge Window is OPEN
Hello all, U-Boot v2012.07 has been released and is available from the git repository and the FTP server. The Merge Window for the next release (v2012.10) is open until Sat Aug 18, 2012, 23:59:59 CEST = 19 days remaining. Release v2012.10 is scheduled in 77 days — on October 15, 2012. A little statistics [1] - changes since release v2012.04: Processed 775 csets from 115 developers 14 employers found A total of 55134 lines added, 11790 removed (delta 43344) Developers with the most changesets Joe Hershberger 90 (11.6%) Fabio Estevam 56 (7.2%) Marek Vasut 42 (5.4%) Stephen Warren 35 (4.5%) SRICHARAN R 29 (3.7%) Tom Rini25 (3.2%) Mike Frysinger 22 (2.8%) Simon Glass 22 (2.8%) Vipin Kumar 21 (2.7%) Anatolij Gustschin 19 (2.5%) ... Developers with the most changed lines Donghwa Lee 9433 (15.7%) Mike Frysinger3200 (5.3%) Joe Hershberger 2929 (4.9%) Nobuhiro Iwamatsu 2412 (4.0%) Yen Lin 2098 (3.5%) Stefano Babic 2090 (3.5%) Stefan Roese 2001 (3.3%) Lukasz Majewski 1954 (3.3%) Marek Vasut 1815 (3.0%) Macpaul Lin 1690 (2.8%) ... Developers with the most lines removed Tom Rini 831 (7.0%) Jaehoon Chung 353 (3.0%) Enric Balletbò i Serra262 (2.2%) Amit Virdi 104 (0.9%) York Sun51 (0.4%) Timur Tabi 51 (0.4%) Andreas Bießmann 43 (0.4%) Wolfgang Denk 22 (0.2%) Simon Guinot13 (0.1%) Thomas Chou 6 (0.1%) ... Developers with the most signoffs (total 372) Tom Warren 80 (21.5%) Stefan Roese46 (12.4%) Kyungmin Park 32 (8.6%) Amit Virdi 31 (8.3%) Andy Fleming16 (4.3%) Kim Phillips14 (3.8%) Simon Glass 14 (3.8%) Valentin Longchamp 13 (3.5%) Minkyu Kang 11 (3.0%) Anatolij Gustschin 10 (2.7%) ... Developers with the most reviews (total 2) Joe Hershberger 2 (100.0%) Developers with the most test credits (total 25) Anatolij Gustschin 3 (12.0%) Tom Rini 3 (12.0%) Wolfgang Denk2 (8.0%) Gary Thomas 2 (8.0%) Pali Rohár 2 (8.0%) Stephen Warren 2 (8.0%) Simon Glass 1 (4.0%) Holger Brunck1 (4.0%) Jaehoon Chung1 (4.0%) Simon Guinot 1 (4.0%) ... Developers who gave the most tested-by credits (total 25) Anatolij Gustschin 3 (12.0%) Luka Perkov 3 (12.0%) SRICHARAN R 2 (8.0%) Tetsuyuki Kobayashi 2 (8.0%) u-b...@lakedaemon.net2 (8.0%) Grazvydas Ignotas2 (8.0%) Timo Ketola 2 (8.0%) Stephen Warren 1 (4.0%) amar...@nvidia.com 1 (4.0%) Tom Warren 1 (4.0%) ... Developers with the most report credits (total 12) Isabelle Gros3 (25.0%) Jerome Angeloni 3 (25.0%) Pali Rohár 1 (8.3%) Marek Vasut 1 (8.3%) Deepak Sikri 1 (8.3%) David Jander 1 (8.3%) Armando Visconti 1 (8.3%) Michael Walle1 (8.3%) Developers who gave the most report credits (total 12) Nishanth Menon 6 (50.0%) Shiraz Hashim2 (16.7%) Anatolij Gustschin 1 (8.3%) Mike Frysinger 1 (8.3%) Joe Hershberger 1 (8.3%) Stefano Babic1 (8.3%) Top changeset contributors by employer (Unknown) 321 (41.4%) Freescale 102 (13.2%) DENX Software Engineering 92 (11.9%) Texas Instruments 83 (10.7%) NVidia 51 (6.6%) Samsung 44 (5.7%) ST Microelectronics 41 (5.3%) Renesas Technology 13 (1.7%) Boundary Devices12 (1.5%) CompuLab 7 (0.9%) ... Top lines changed by employer (Unknown) 21667 (36.1%) Samsung 13488 (22.5%) DENX Software Engineering 6788 (11.3%) NVidia4584 (7.6%) Freescale 4044 (6.7%) Texas Instruments 3424 (5.7%) Renesas Technology2803 (4.7%) ST Microelectronics 1752 (2.9%) Atmel 719 (1.2%) Boundary Devices 426 (0.7%) ... Employers with the most signoffs (total 372) NVidia 80 (21.5%) (Unknown) 64 (17.2%) DENX Software Engineering 60 (16.1%) Freescale 59 (15.9%) Samsung 57 (15.3%) ST Microelectronics 35 (9.4%) Texas Instruments 10 (2.7%) CompuLab 5 (1.3%) Marvell
[U-Boot] [PATCH 18/17] am33xx: Correct and clean up ddr_regs struct
The ddr_regs struct was incorrectly offset after the dt0wiratio0 entry.
Correct this by documenting a missing register that will be used at some
point in the future (when write leveling is supported). Further, the
cmdNcs{force,delay} fields are undocumented and we have been setting
them to zero, remove. Next, setting of the
'DATAn_REG_PHY_USE_RANK0_DELAYS field belongs with the rest of the
ddr_data entries, so program it there. Finally, comment on how we are
configuring the DATA1 registers that correspond to the DATA0 (dt0)
registers defined in the struct.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/ddr.c |7 +
arch/arm/cpu/armv7/am33xx/emif4.c | 10 +---
arch/arm/include/asm/arch-am33xx/ddr_defs.h | 37 +--
3 files changed, 20 insertions(+), 34 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index 59ca51f..bceed81 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -77,20 +77,14 @@ void config_ddr_phy(const struct emif_regs *regs)
void config_cmd_ctrl(const struct cmd_control *cmd)
{
writel(cmd-cmd0csratio, ddr_reg[0]-cm0csratio);
- writel(cmd-cmd0csforce, ddr_reg[0]-cm0csforce);
- writel(cmd-cmd0csdelay, ddr_reg[0]-cm0csdelay);
writel(cmd-cmd0dldiff, ddr_reg[0]-cm0dldiff);
writel(cmd-cmd0iclkout, ddr_reg[0]-cm0iclkout);
writel(cmd-cmd1csratio, ddr_reg[0]-cm1csratio);
- writel(cmd-cmd1csforce, ddr_reg[0]-cm1csforce);
- writel(cmd-cmd1csdelay, ddr_reg[0]-cm1csdelay);
writel(cmd-cmd1dldiff, ddr_reg[0]-cm1dldiff);
writel(cmd-cmd1iclkout, ddr_reg[0]-cm1iclkout);
writel(cmd-cmd2csratio, ddr_reg[0]-cm2csratio);
- writel(cmd-cmd2csforce, ddr_reg[0]-cm2csforce);
- writel(cmd-cmd2csdelay, ddr_reg[0]-cm2csdelay);
writel(cmd-cmd2dldiff, ddr_reg[0]-cm2dldiff);
writel(cmd-cmd2iclkout, ddr_reg[0]-cm2iclkout);
}
@@ -106,6 +100,7 @@ void config_ddr_data(int macrono, const struct ddr_data
*data)
writel(data-datagiratio0, ddr_reg[macrono]-dt0giratio0);
writel(data-datafwsratio0, ddr_reg[macrono]-dt0fwsratio0);
writel(data-datawrsratio0, ddr_reg[macrono]-dt0wrsratio0);
+ writel(data-datauserank0delay, ddr_reg[macrono]-dt0rdelays0);
writel(data-datadldiff0, ddr_reg[macrono]-dt0dldiff0);
}
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c
b/arch/arm/cpu/armv7/am33xx/emif4.c
index ace3d26..3bb91d3 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -61,25 +61,20 @@ static const struct ddr_data ddr2_data = {
|(DDR2_PHY_FIFO_WE10)|(DDR2_PHY_FIFO_WE0)),
.datawrsratio0 = ((DDR2_PHY_WR_DATA30)|(DDR2_PHY_WR_DATA20)
|(DDR2_PHY_WR_DATA10)|(DDR2_PHY_WR_DATA0)),
+ .datauserank0delay = DDR2_PHY_RANK0_DELAY,
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
static const struct cmd_control ddr2_cmd_ctrl_data = {
.cmd0csratio = DDR2_RATIO,
- .cmd0csforce = CMD_FORCE,
- .cmd0csdelay = CMD_DELAY,
.cmd0dldiff = DDR2_DLL_LOCK_DIFF,
.cmd0iclkout = DDR2_INVERT_CLKOUT,
.cmd1csratio = DDR2_RATIO,
- .cmd1csforce = CMD_FORCE,
- .cmd1csdelay = CMD_DELAY,
.cmd1dldiff = DDR2_DLL_LOCK_DIFF,
.cmd1iclkout = DDR2_INVERT_CLKOUT,
.cmd2csratio = DDR2_RATIO,
- .cmd2csforce = CMD_FORCE,
- .cmd2csdelay = CMD_DELAY,
.cmd2dldiff = DDR2_DLL_LOCK_DIFF,
.cmd2iclkout = DDR2_INVERT_CLKOUT,
};
@@ -121,9 +116,6 @@ void config_ddr(short ddr_type)
config_ddr_data(0, ddr2_data);
config_ddr_data(1, ddr2_data);
- writel(DDR2_PHY_RANK0_DELAY, ddrregs-dt0rdelays0);
- writel(DDR2_PHY_RANK0_DELAY, ddrregs-dt1rdelays0);
-
config_io_ctrl(DDR2_IOCTRL_VALUE);
/* Set CKE to be controlled by EMIF/DDR PHY */
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index b37b161..0526863 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -26,8 +26,6 @@
#define VTP_CTRL_READY (0x1 5)
#define VTP_CTRL_ENABLE(0x1 6)
#define VTP_CTRL_START_EN (0x1)
-#define CMD_FORCE 0x00
-#define CMD_DELAY 0x00
#define PHY_DLL_LOCK_DIFF 0x0
#define DDR_CKE_CTRL_NORMAL0x1
@@ -66,43 +64,43 @@ void config_ddr_phy(const struct emif_regs *regs);
/**
* This structure represents the DDR registers on AM33XX devices.
+ * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that
+ * correspond to DATA1 registers defined here.
*/
struct ddr_regs {
unsigned int resv0[7];
unsigned int cm0csratio;/* offset 0x01C */
- unsigned int cm0csforce;/* offset
[U-Boot] usb_test_unit_ready called every block read - performance
While tuning ext2load, we found that usb_test_unit_ready was being called every block read. We compared the usb block storage to the scsi block storage cmd_scsi.c, and found that the scsi device was only calling its scsi_setup_test_unit_ready() during scsi_can. It appears that usb_test_unit_ready() really only needs to be called once during usb_stor_scan(), via usb_stor_get_info(). Is there a particular reason usb_test_unit_ready is called for every block read, or do you think its ok to only call during usb_stor_scan()? We're finding this speeds up ext2load quite a bit. Regards, Jim -- *James H Shimer* Motorola Mobility T3-12-HH72 900 Chelmsford Street Lowell MA 08151 978-614-3550 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] pull request for u-boot-tegra/master
Albert,
Please pull u-boot-tegra/master into ARM master. Thanks!
The following changes since commit f8f09dd40423b7f9ea0f0b810a8f5da9cd580a17:
Benoît Thébaudeau (1):
ARM1136: Fix cache range checks
are available in the git repository at:
git://git.denx.de/u-boot-tegra master
Allen Martin (15):
tegra20: rename tegra2 - tegra20
tegra20: move tegra20 SoC code to arch/arm/cpu/tegra20-common
tegra20: rename CONFIG_MACH_TEGRA_GENERIC
tegra20: tec: add tegra20-common-post.h
tegra20: make board mkdir commands unconditional
mkconfig: add support for SPL CPU
ARM: Fix arm720t SPL build
tegra20: remove timer_init from SPL build
ARM: add tegra20 support to arm720t
tegra20: add u-boot-*-tegra.bin targets
tegra20: move SDRAM param save to later in boot
tegra20: enable SPL for tegra20 boards
arm: enable libgcc build for SPL
spl: fix SPL build of private libgcc
tegra20: Remove armv4t build flags
MAINTAINERS| 18 ++--
Makefile | 26
arch/arm/cpu/arm720t/cpu.c |2 +
arch/arm/cpu/arm720t/interrupts.c |5 +
arch/arm/cpu/arm720t/start.S | 19 +++-
.../cpu/{armv7/tegra2 = arm720t/tegra20}/Makefile | 28 +---
.../arch-tegra2 = cpu/arm720t/tegra20}/board.h| 11 +-
.../{armv7/tegra2 = arm720t/tegra20}/config.mk| 12 --
.../{armv7/tegra2/ap20.c = arm720t/tegra20/cpu.c} | 148 ++--
.../ap20.h = cpu/arm720t/tegra20/cpu.h} | 15 +--
arch/arm/cpu/arm720t/tegra20/spl.c | 132 +
arch/arm/cpu/armv7/start.S |2 -
arch/arm/cpu/armv7/{tegra2 = tegra20}/Makefile| 15 +--
.../cpu/armv7/{tegra2 = tegra20}/cmd_enterrcm.c |4 +-
arch/arm/cpu/armv7/{tegra2 = tegra20}/config.mk | 12 --
arch/arm/cpu/armv7/{tegra2 = tegra20}/usb.c |2 +-
.../cpu/{armv7/tegra2 = tegra20-common}/Makefile | 29 ++---
arch/arm/cpu/tegra20-common/ap20.c | 131 +
.../cpu/{armv7/tegra2 = tegra20-common}/board.c | 39 ++
.../cpu/{armv7/tegra2 = tegra20-common}/clock.c | 10 +-
.../cpu/{armv7/tegra2 = tegra20-common}/crypto.c |0
.../cpu/{armv7/tegra2 = tegra20-common}/crypto.h |0
.../arm/cpu/{armv7/tegra2 = tegra20-common}/emc.c |2 +-
.../cpu/{armv7/tegra2 = tegra20-common}/funcmux.c |2 +-
.../tegra2 = tegra20-common}/lowlevel_init.S |0
.../cpu/{armv7/tegra2 = tegra20-common}/pinmux.c |4 +-
.../arm/cpu/{armv7/tegra2 = tegra20-common}/pmu.c |2 +-
.../{armv7/tegra2 = tegra20-common}/sys_info.c|2 +-
.../cpu/{armv7/tegra2 = tegra20-common}/timer.c |2 +-
.../{armv7/tegra2 = tegra20-common}/warmboot.c| 18 ++--
.../tegra2 = tegra20-common}/warmboot_avp.c |4 +-
.../tegra2 = tegra20-common}/warmboot_avp.h |0
.../asm/{arch-tegra2 = arch-tegra20}/ap20.h |4 +-
.../asm/{arch-tegra2 = arch-tegra20}/apb_misc.h |0
.../asm/{arch-tegra2 = arch-tegra20}/board.h |0
.../asm/{arch-tegra2 = arch-tegra20}/clk_rst.h|0
.../asm/{arch-tegra2 = arch-tegra20}/clock.h |0
.../asm/{arch-tegra2 = arch-tegra20}/emc.h|0
.../asm/{arch-tegra2 = arch-tegra20}/flow.h |0
.../asm/{arch-tegra2 = arch-tegra20}/funcmux.h|2 +-
.../asm/{arch-tegra2 = arch-tegra20}/fuse.h |0
.../asm/{arch-tegra2 = arch-tegra20}/gp_padctrl.h |2 +-
.../asm/{arch-tegra2 = arch-tegra20}/gpio.h |2 +-
arch/arm/include/asm/arch-tegra20/hardware.h | 29
.../asm/{arch-tegra2 = arch-tegra20}/mmc.h|8 +-
.../asm/{arch-tegra2 = arch-tegra20}/pinmux.h |0
.../asm/{arch-tegra2 = arch-tegra20}/pmc.h|0
.../asm/{arch-tegra2 = arch-tegra20}/pmu.h|0
.../asm/{arch-tegra2 = arch-tegra20}/scu.h|0
.../{arch-tegra2 = arch-tegra20}/sdram_param.h|0
.../asm/{arch-tegra2 = arch-tegra20}/sys_proto.h |4 +-
.../tegra2.h = arch-tegra20/tegra20.h}| 18 ++--
.../asm/{arch-tegra2 = arch-tegra20}/tegra_i2c.h |2 +-
.../asm/{arch-tegra2 = arch-tegra20}/tegra_spi.h |4 +-
.../asm/{arch-tegra2 = arch-tegra20}/timer.h |6 +-
.../uart-spi-switch.h |0
.../asm/{arch-tegra2 = arch-tegra20}/uart.h |0
.../asm/{arch-tegra2 = arch-tegra20}/usb.h|0
.../asm/{arch-tegra2 = arch-tegra20}/warmboot.h |0
arch/arm/lib/Makefile |2 +-
board/avionic-design/common/tamonten.c |4 +-
.../dts/{tegra2-medcom.dts = tegra20-medcom.dts} |0
.../dts/{tegra2-plutux.dts = tegra20-plutux.dts} |0
.../dts/{tegra2-tec.dts = tegra20-tec.dts}|0
board/avionic-design/medcom/Makefile |2 -
Re: [U-Boot] [PATCH] tegra: enable NAND on Harmony
On Mon, Jul 30, 2012 at 6:37 PM, Stephen Warren swar...@wwwdotorg.org wrote:
From: Stephen Warren swar...@nvidia.com
Signed-off-by: Stephen Warren swar...@nvidia.com
Acked-by: Simon Glass s...@chromium.org
(nice to have a commit message though)
---
board/nvidia/dts/tegra20-harmony.dts | 10 ++
include/configs/harmony.h|9 -
2 files changed, 18 insertions(+), 1 deletions(-)
diff --git a/board/nvidia/dts/tegra20-harmony.dts
b/board/nvidia/dts/tegra20-harmony.dts
index c351954..ca5facb 100644
--- a/board/nvidia/dts/tegra20-harmony.dts
+++ b/board/nvidia/dts/tegra20-harmony.dts
@@ -54,4 +54,14 @@
usb@c5004000 {
status = disabled;
};
+
+ nand-controller@70008000 {
+ nvidia,wp-gpios = gpio 23 0; /* PC7 */
+ nvidia,width = 8;
+ nvidia,timing = 26 100 20 80 20 10 12 10 70;
+ nand@0 {
+ reg = 0;
+ compatible = hynix,hy27uf4g2b, nand-flash;
+ };
+ };
};
diff --git a/include/configs/harmony.h b/include/configs/harmony.h
index d0555c1..85059b9 100644
--- a/include/configs/harmony.h
+++ b/include/configs/harmony.h
@@ -62,8 +62,15 @@
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_TEGRA_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE TEGRA20_NAND_BASE
+
/* Environment not stored */
-#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sector size */
/* USB Host support */
#define CONFIG_USB_EHCI
--
1.7.0.4
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Re: [U-Boot] [PATCH] env_nand: align NAND buffers
On Mon, Jul 30, 2012 at 6:38 PM, Stephen Warren swar...@wwwdotorg.org wrote:
From: Stephen Warren swar...@nvidia.com
This allows cache flush/invalidate operations to succeed on the buffers.
Signed-off-by: Stephen Warren swar...@nvidia.com
Acked-by: Simon Glass s...@chromium.org
---
common/env_nand.c | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/common/env_nand.c b/common/env_nand.c
index e8daec9..e635472 100644
--- a/common/env_nand.c
+++ b/common/env_nand.c
@@ -226,7 +226,7 @@ int saveenv(void)
int saveenv(void)
{
int ret = 0;
- env_t env_new;
+ ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, sizeof(env_t));
I think this should b
ssize_t len;
char*res;
nand_erase_options_t nand_erase_options;
@@ -238,20 +238,20 @@ int saveenv(void)
if (CONFIG_ENV_RANGE CONFIG_ENV_SIZE)
return 1;
- res = (char *)env_new.data;
+ res = (char *)env_new-data;
len = hexport_r(env_htab, '\0', res, ENV_SIZE, 0, NULL);
if (len 0) {
error(Cannot export environment: errno = %d\n, errno);
return 1;
}
- env_new.crc = crc32(0, env_new.data, ENV_SIZE);
+ env_new-crc = crc32(0, env_new-data, ENV_SIZE);
puts(Erasing Nand...\n);
if (nand_erase_opts(nand_info[0], nand_erase_options))
return 1;
puts(Writing to Nand... );
- if (writeenv(CONFIG_ENV_OFFSET, (u_char *)env_new)) {
+ if (writeenv(CONFIG_ENV_OFFSET, (u_char *)env_new)) {
puts(FAILED!\n);
return 1;
}
@@ -398,7 +398,7 @@ void env_relocate_spec(void)
{
#if !defined(ENV_IS_EMBEDDED)
int ret;
- char buf[CONFIG_ENV_SIZE];
+ ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
#if defined(CONFIG_ENV_OFFSET_OOB)
ret = get_nand_env_oob(nand_info[0], nand_env_oob_offset);
--
1.7.0.4
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[U-Boot] [PATCH] lsxl: support power switch
This patch restores the Linkstation's original behaviour when powering off.
Once the (soft) power switch is turned off, linux will reboot and the
bootloader turns off HDD and USB power. Then it loops as long as the switch
is in the off position, before continuing the boot process again.
Additionally, this patch fixes the board function set_led(LED_OFF).
Signed-off-by: Michael Walle mich...@walle.cc
Cc: Prafulla Wadaskar prafu...@marvell.com
---
board/buffalo/lsxl/lsxl.c | 22 +-
1 files changed, 21 insertions(+), 1 deletions(-)
diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c
index fe15511..b3f31d6 100644
--- a/board/buffalo/lsxl/lsxl.c
+++ b/board/buffalo/lsxl/lsxl.c
@@ -158,7 +158,7 @@ static void set_led(int state)
{
switch (state) {
case LED_OFF:
- __set_led(0, 0, 0, 0, 0, 0);
+ __set_led(0, 0, 0, 1, 1, 1);
break;
case LED_ALARM_ON:
__set_led(0, 0, 0, 0, 1, 1);
@@ -192,6 +192,25 @@ int board_init(void)
}
#ifdef CONFIG_MISC_INIT_R
+static void check_power_switch(void)
+{
+ if (kw_gpio_get_value(GPIO_POWER_SWITCH)) {
+ /* turn off HDD and USB power */
+ kw_gpio_set_value(GPIO_HDD_POWER, 0);
+ kw_gpio_set_value(GPIO_USB_VBUS, 0);
+ set_led(LED_OFF);
+
+ /* loop until released */
+ while (kw_gpio_get_value(GPIO_POWER_SWITCH))
+ ;
+
+ /* turn power on again */
+ kw_gpio_set_value(GPIO_HDD_POWER, 1);
+ kw_gpio_set_value(GPIO_USB_VBUS, 1);
+ set_led(LED_POWER_BLINKING);
+ }
+}
+
void check_enetaddr(void)
{
uchar enetaddr[6];
@@ -261,6 +280,7 @@ static void check_push_button(void)
int misc_init_r(void)
{
+ check_power_switch();
check_enetaddr();
check_push_button();
--
1.7.2.5
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[U-Boot] [PATCH 1/3] mmc: detect boot sectors using EXT_CSD_BOOT_MULT too
From: Stephen Warren swar...@nvidia.com Some eMMC devices contain boot partitions, but do not set the PART_SUPPORT bit in EXT_CSD_PARTITIONING_SUPPORT. Allow partition selection on such devices, by enabling partition switching when EXT_CSD_BOOT_MULT is set. Note that the Linux kernel enables access to boot partitions solely based on the value of EXT_CSD_BOOT_MULT; EXT_CSD_PARTITIONING_SUPPORT only influences access to general partitions. eMMC devices affected by this issue exist on various NVIDIA Tegra platforms (and presumably many others too), such as Harmony (plug-in eMMC), Seaboard, Springbank, and Whistler (plug-in eMMC). Signed-off-by: Stephen Warren swar...@nvidia.com --- drivers/mmc/mmc.c |3 ++- include/mmc.h |1 + 2 files changed, 3 insertions(+), 1 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index aebe578..3b08953 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1157,7 +1157,8 @@ int mmc_startup(struct mmc *mmc) } /* store the partition info of emmc */ - if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] PART_SUPPORT) + if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] PART_SUPPORT) || + ext_csd[EXT_CSD_BOOT_MULT]) mmc-part_config = ext_csd[EXT_CSD_PART_CONF]; } diff --git a/include/mmc.h b/include/mmc.h index 2305986..89df83c 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -159,6 +159,7 @@ #define EXT_CSD_CARD_TYPE 196 /* RO */ #define EXT_CSD_SEC_CNT212 /* RO, 4 bytes */ #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ +#define EXT_CSD_BOOT_MULT 226 /* RO */ /* * EXT_CSD field definitions -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] mmc: detect boot sectors using EXT_CSD_BOOT_MULT too
From: Stephen Warren swar...@nvidia.com Some eMMC devices contain boot partitions, but do not set the PART_SUPPORT bit in EXT_CSD_PARTITIONING_SUPPORT. Allow partition selection on such devices, by enabling partition switching when EXT_CSD_BOOT_MULT is set. Note that the Linux kernel enables access to boot partitions solely based on the value of EXT_CSD_BOOT_MULT; EXT_CSD_PARTITIONING_SUPPORT only influences access to general partitions. eMMC devices affected by this issue exist on various NVIDIA Tegra platforms (and presumably many others too), such as Harmony (plug-in eMMC), Seaboard, Springbank, and Whistler (plug-in eMMC). Signed-off-by: Stephen Warren swar...@nvidia.com --- drivers/mmc/mmc.c |3 ++- include/mmc.h |1 + 2 files changed, 3 insertions(+), 1 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index aebe578..3b08953 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1157,7 +1157,8 @@ int mmc_startup(struct mmc *mmc) } /* store the partition info of emmc */ - if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] PART_SUPPORT) + if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] PART_SUPPORT) || + ext_csd[EXT_CSD_BOOT_MULT]) mmc-part_config = ext_csd[EXT_CSD_PART_CONF]; } diff --git a/include/mmc.h b/include/mmc.h index 2305986..89df83c 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -159,6 +159,7 @@ #define EXT_CSD_CARD_TYPE 196 /* RO */ #define EXT_CSD_SEC_CNT212 /* RO, 4 bytes */ #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ +#define EXT_CSD_BOOT_MULT 226 /* RO */ /* * EXT_CSD field definitions -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3] env_mmc: allow environment to be in an eMMC partition
From: Stephen Warren swar...@nvidia.com
eMMC devices may have hardware-level partitions: 2 boot partitions,
up to 4 general partitions, plus the user area. This change introduces
optional config variable CONFIG_SYS_MMC_ENV_PART to indicate which
partition the environment should be stored in: 0=user, 1=boot0, 2=boot1,
4..7=general0..3. This allows the environment to be kept out of the user
area, which simplifies the management of OS-/user-level (MBR/GPT)
partitions within the user area.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
common/env_mmc.c | 64 +++--
1 files changed, 56 insertions(+), 8 deletions(-)
diff --git a/common/env_mmc.c b/common/env_mmc.c
index be2f2be..a2ff90b 100644
--- a/common/env_mmc.c
+++ b/common/env_mmc.c
@@ -75,9 +75,28 @@ static int init_mmc_for_env(struct mmc *mmc)
return -1;
}
+#ifdef CONFIG_SYS_MMC_ENV_PART
+ if (CONFIG_SYS_MMC_ENV_PART != mmc-part_num) {
+ if (mmc_switch_part(CONFIG_SYS_MMC_ENV_DEV,
+ CONFIG_SYS_MMC_ENV_PART)) {
+ puts(MMC partition switch failed\n);
+ return -1;
+ }
+ }
+#endif
+
return 0;
}
+static void fini_mmc_for_env(struct mmc *mmc)
+{
+#ifdef CONFIG_SYS_MMC_ENV_PART
+ if (CONFIG_SYS_MMC_ENV_PART != mmc-part_num)
+ mmc_switch_part(CONFIG_SYS_MMC_ENV_DEV,
+ mmc-part_num);
+#endif
+}
+
#ifdef CONFIG_CMD_SAVEENV
static inline int write_env(struct mmc *mmc, unsigned long size,
unsigned long offset, const void *buffer)
@@ -100,26 +119,38 @@ int saveenv(void)
char*res;
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
u32 offset;
+ int ret;
- if (init_mmc_for_env(mmc) || mmc_get_env_addr(mmc, offset))
+ if (init_mmc_for_env(mmc))
return 1;
+ if (mmc_get_env_addr(mmc, offset)) {
+ ret = 1;
+ goto fini;
+ }
+
res = (char *)env_new-data;
len = hexport_r(env_htab, '\0', res, ENV_SIZE, 0, NULL);
if (len 0) {
error(Cannot export environment: errno = %d\n, errno);
- return 1;
+ ret = 1;
+ goto fini;
}
env_new-crc = crc32(0, env_new-data[0], ENV_SIZE);
printf(Writing to MMC(%d)... , CONFIG_SYS_MMC_ENV_DEV);
if (write_env(mmc, CONFIG_ENV_SIZE, offset, (u_char *)env_new)) {
puts(failed\n);
- return 1;
+ ret = 1;
+ goto fini;
}
puts(done\n);
- return 0;
+ ret = 0;
+
+fini:
+ fini_mmc_for_env(mmc);
+ return ret;
}
#endif /* CONFIG_CMD_SAVEENV */
@@ -143,13 +174,30 @@ void env_relocate_spec(void)
ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
u32 offset;
+ int ret;
- if (init_mmc_for_env(mmc) || mmc_get_env_addr(mmc, offset))
- return set_default_env(NULL);
+ if (init_mmc_for_env(mmc)) {
+ ret = 1;
+ goto err;
+ }
- if (read_env(mmc, CONFIG_ENV_SIZE, offset, buf))
- return set_default_env(NULL);
+ if (mmc_get_env_addr(mmc, offset)) {
+ ret = 1;
+ goto fini;
+ }
+
+ if (read_env(mmc, CONFIG_ENV_SIZE, offset, buf)) {
+ ret = 1;
+ goto fini;
+ }
env_import(buf, 1);
+ ret = 0;
+
+fini:
+ fini_mmc_for_env(mmc);
+err:
+ if (ret)
+ set_default_env(NULL);
#endif
}
--
1.7.0.4
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[U-Boot] [PATCH 3/3] tegra: put eMMC environment into the boot sectors
From: Stephen Warren swar...@nvidia.com When I set up Tegra's config files to put the environment into eMMC, I assumed that CONFIG_ENV_OFFSET was a linearized address relative to the start of the eMMC device, and spanning HW partitions boot0, boot1, general* and the user area in order. However, it turns out that the offset is actually relative to the beginning of the user area. Hence, the environment block ended up in a different location to expected and documented. Set CONFIG_SYS_MMC_ENV_PART=2 (boot1) to solve this, and adjust CONFIG_ENV_OFFSET to be relative to the start of boot1, not the entire eMMC. Signed-off-by: Stephen Warren swar...@nvidia.com --- include/configs/paz00.h|3 ++- include/configs/seaboard.h |3 ++- include/configs/ventana.h |3 ++- include/configs/whistler.h |3 ++- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/include/configs/paz00.h b/include/configs/paz00.h index 0eb9f3b..99b8753 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -51,8 +51,9 @@ /* Environment in eMMC, at the end of 2nd boot sector */ #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_OFFSET ((2 * 1024 * 1024) - CONFIG_ENV_SIZE) +#define CONFIG_ENV_OFFSET ((1024 * 1024) - CONFIG_ENV_SIZE) #define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 /* USB Host support */ #define CONFIG_USB_EHCI diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 479af1a..6996502 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -77,8 +77,9 @@ /* Environment in eMMC, at the end of 2nd boot sector */ #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_OFFSET ((2 * 512 * 1024) - CONFIG_ENV_SIZE) +#define CONFIG_ENV_OFFSET ((512 * 1024) - CONFIG_ENV_SIZE) #define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 /* USB Host support */ #define CONFIG_USB_EHCI diff --git a/include/configs/ventana.h b/include/configs/ventana.h index 25ec2eb..f5e1bf8 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -58,8 +58,9 @@ /* Environment in eMMC, at the end of 2nd boot sector */ #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_OFFSET ((2 * 1024 * 1024) - CONFIG_ENV_SIZE) +#define CONFIG_ENV_OFFSET ((1024 * 1024) - CONFIG_ENV_SIZE) #define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 /* USB Host support */ #define CONFIG_USB_EHCI diff --git a/include/configs/whistler.h b/include/configs/whistler.h index b747d0e..3235718 100644 --- a/include/configs/whistler.h +++ b/include/configs/whistler.h @@ -72,8 +72,9 @@ * particular card is standard practice as far as I know. */ #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_OFFSET ((2 * 512 * 1024) - CONFIG_ENV_SIZE) +#define CONFIG_ENV_OFFSET ((512 * 1024) - CONFIG_ENV_SIZE) #define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 /* USB Host support */ #define CONFIG_USB_EHCI -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Building u-boot for iMX28 and getting error in mkimage of missing command line parameter CONFIG_IMX_CONFIG
On Mon, Jul 30, 2012 at 3:53 PM, Bill bsou...@techsi.com wrote: Progress! I switched all the references from ttyAMA0... to ttyAM0. Also changed netargs too. Now it starts to boot linux but hangs right after the line of: mxs_cpu_init: cpufreq init finished. Please remove cpufreq from your kernel config. You can use this patch: https://github.com/Freescale/meta-fsl-arm/blob/denzil/recipes-kernel/linux/linux-imx-2.6.35.3/mx28-removecpufreq.patch Regards, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] net: Improve the speed of netconsole
Hi Mike,
On Wed, Jul 25, 2012 at 1:49 PM, Mike Frysinger vap...@gentoo.org wrote:
On Tuesday 24 July 2012 16:11:15 Joe Hershberger wrote:
--- a/drivers/net/netconsole.c
+++ b/drivers/net/netconsole.c
@@ -131,8 +131,17 @@ static void nc_send_packet(const char *buf, int len)
}
if (eth-state != ETH_STATE_ACTIVE) {
- if (eth_init(gd-bd) 0)
- return;
+#ifdef CONFIG_NETCONSOLE_PERSIST_ETH
+ if (net_loop_last_protocol != NETCONS) {
+#endif
+ if (eth_init(gd-bd) 0)
+ return;
+#ifdef CONFIG_NETCONSOLE_PERSIST_ETH
+ net_loop_last_protocol = NETCONS;
+ } else {
+ eth_init_state_only(gd-bd);
+ }
+#endif
seems to me these pre/post clauses should really get refactored someway. the
ifdef noise is significant here.
I agree.
so in the header, something like:
static inline int eth_reinit_protocol(int protocol)
{
#ifdef CONFIG_NETCONSOLE_PERSIST_ETH
return protocol != NETCONS;
#else
return 1;
#endif
}
static inline void eth_set_last_protocol(int protocol)
{
#ifdef CONFIG_NETCONSOLE_PERSIST_ETH
net_loop_last_protocol = protocol;
#endif
}
#ifdef CONFIG_NETCONSOLE_PERSIST_ETH
extern enum proto_t net_loop_last_protocol;
#else
# define net_loop_last_protocol -1
#endif
then the source becomes the more manageable:
if (eth_reinit_protocol(net_loop_last_protocol)) {
if (eth_init(gd-bd) 0)
return;
eth_set_last_protocol(NETCONS);
} else
eth_init_state_only(gd-bd);
Much nicer. With static inline it should compile to the same thing.
--- a/net/eth.c
+++ b/net/eth.c
+#ifdef CONFIG_NETCONSOLE_PERSIST_ETH
+int eth_init_state_only(bd_t *bis)
+{
+ eth_current-state = ETH_STATE_ACTIVE;
+
+ return 0;
+}
+
+void eth_halt_state_only(void)
+{
+ eth_current-state = ETH_STATE_PASSIVE;
+}
+#endif
these *really* should be static inlines in the global header. they're so dirt
simple, the overhead of the function call is probably much higher than the
single memory store.
I can do that, but I don't think it will save anything. Since
eth_current is static, I would have to change it to eth_get_dev(), and
we're back to a function call. Thoughts?
Thanks,
-Joe
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Re: [U-Boot] [PATCH] env_nand: align NAND buffers
Dear Simon Glass, In message CAPnjgZ2gJLhmZyXB1DW=83GBdf1QNv_=q+qfprawczx4yq7...@mail.gmail.com you wrote: - env_t env_new; + ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, sizeof(env_t)); I think this should b Should be ... ??? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Be wiser than other people if you can, but do not tell them so. -- Philip Earl of Chesterfield ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] env_nand: align NAND buffers
Hi Wolfgang, On Mon, Jul 30, 2012 at 10:10 PM, Wolfgang Denk w...@denx.de wrote: Dear Simon Glass, In message CAPnjgZ2gJLhmZyXB1DW=83GBdf1QNv_=q+qfprawczx4yq7...@mail.gmail.com you wrote: - env_t env_new; + ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, sizeof(env_t)); I think this should b Should be ... ??? Sorry, I started a comment, but thought better of it. It looks fine to me. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Be wiser than other people if you can, but do not tell them so. -- Philip Earl of Chesterfield Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RESEND] [PATCH 0/2] kirkwood: Generalise dns325 support, include dns320
I submitted this a while ago[0], it would be nice to see it included
if possible. It generalises the DNS325 support so that it can be used
for both the DNS320 and DNS325.
Luka Perkov stated I have no more questions regarding this patch, not
sure if this counts as an ACK. The patch here is ~same, just rebased.
Somewhat related, I have tried using tools/kwboot to boot both NASes.
The DNS325 boots fine, however the DNS320 reports:-
Sending boot message. Please reboot the target...|
Sending boot image...
0 % [+xmodem: Bad message
UART-boot works with kwuartboot, although only when it is killed and
restarted. If I work out anything interesting will follow it up in
a separate thread.
Any feedback appreciated!
[0] http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/130234/focus=130575
Jamie Lentin (2):
kirkwood: Rename dns325 to dnskw
kirkwood: Add support for the D-Link DNS-320
MAINTAINERS|4 +
board/d-link/{dns325 = dnskw}/Makefile|2 +-
board/d-link/{dns325/dns325.c = dnskw/dnskw.c}| 18 +-
board/d-link/{dns325/dns325.h = dnskw/dnskw.h}| 30 ++-
board/d-link/dnskw/kwbimage.dns320.cfg | 207
.../kwbimage.cfg = dnskw/kwbimage.dns325.cfg} |0
boards.cfg |3 +-
include/configs/{dns325.h = dnskw.h} | 21 +-
8 files changed, 261 insertions(+), 24 deletions(-)
rename board/d-link/{dns325 = dnskw}/Makefile (98%)
rename board/d-link/{dns325/dns325.c = dnskw/dnskw.c} (90%)
rename board/d-link/{dns325/dns325.h = dnskw/dnskw.h} (65%)
create mode 100644 board/d-link/dnskw/kwbimage.dns320.cfg
rename board/d-link/{dns325/kwbimage.cfg = dnskw/kwbimage.dns325.cfg} (100%)
rename include/configs/{dns325.h = dnskw.h} (89%)
--
1.7.10.4
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[U-Boot] [PATCH 2/2] kirkwood: Add support for the D-Link DNS-320
Extend dnskw to support the D-Link DNS-320 ShareCenter NAS also. For more information on this NAS, see:- http://jamie.lentin.co.uk/devices/dlink-dns320 http://dns323.kood.org/dns-320 http://sharecenter.dlink.com/products/DNS-320 Signed-off-by: Jamie Lentin j...@lentin.co.uk Cc: prafu...@marvell.com Cc: albert.u.b...@aribaud.net --- MAINTAINERS|4 + board/d-link/dnskw/dnskw.c |8 +- board/d-link/dnskw/dnskw.h |6 + board/d-link/dnskw/kwbimage.dns320.cfg | 207 boards.cfg |1 + include/configs/dnskw.h| 10 ++ 6 files changed, 232 insertions(+), 4 deletions(-) create mode 100644 board/d-link/dnskw/kwbimage.dns320.cfg diff --git a/MAINTAINERS b/MAINTAINERS index fd0c65c..92ede1f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -673,6 +673,10 @@ Igor Grinberg grinb...@compulab.co.il cm-t35 ARM ARMV7 (OMAP3xx Soc) +Jamie Lentin j...@lentin.co.uk + + dns320 ARM926EJS (Kirkwood SoC) + Stefan Herbrechtsmeier ste...@code.herbrechtsmeier.net dns325 ARM926EJS (Kirkwood SoC) diff --git a/board/d-link/dnskw/dnskw.c b/board/d-link/dnskw/dnskw.c index d29735c..cd6bfe9 100644 --- a/board/d-link/dnskw/dnskw.c +++ b/board/d-link/dnskw/dnskw.c @@ -58,8 +58,8 @@ int board_early_init_f(void) MPP10_UART0_TXD, MPP11_UART0_RXD, MPP12_SD_CLK, - MPP13_SD_CMD, - MPP14_SD_D0, + MPP13_UART1_TXD,/* Custom ...*/ + MPP14_UART1_RXD,/* ... controller */ MPP15_SD_D1, MPP16_SD_D2, MPP17_SD_D3, @@ -74,13 +74,13 @@ int board_early_init_f(void) MPP26_GPIO, /* power led */ MPP27_GPIO, /* sata0(right) error led */ MPP28_GPIO, /* sata1(left) error led */ - MPP29_GPIO, /* usb error led */ + MPP29_GPIO, /* usb error led (dns-325) */ MPP30_GPIO, MPP31_GPIO, MPP32_GPIO, MPP33_GPIO, MPP34_GPIO, /* power key */ - MPP35_GPIO, + MPP35_GPIO, /* usb error led (dns-320) */ MPP36_GPIO, MPP37_GPIO, MPP38_GPIO, diff --git a/board/d-link/dnskw/dnskw.h b/board/d-link/dnskw/dnskw.h index 4b11cb6..8886050 100644 --- a/board/d-link/dnskw/dnskw.h +++ b/board/d-link/dnskw/dnskw.h @@ -43,6 +43,12 @@ #define DNSKW_OE_VAL_HIGH 0x0800 /* disable leds */ #endif /* CONFIG_BOARD_IS_DNS325 */ +/* DNS-320 specific configuration */ +#ifdef CONFIG_BOARD_IS_DNS320 +#define DNSKW_OE_VAL_LOW 0x3800 /* disable leds */ +#define DNSKW_OE_VAL_HIGH 0x0808 /* disable leds */ +#endif /* CONFIG_BOARD_IS_DNS320 */ + /* PHY related */ #define MV88E1116_MAC_CTRL_REG 21 #define MV88E1116_PGADR_REG22 diff --git a/board/d-link/dnskw/kwbimage.dns320.cfg b/board/d-link/dnskw/kwbimage.dns320.cfg new file mode 100644 index 000..5fb4052 --- /dev/null +++ b/board/d-link/dnskw/kwbimage.dns320.cfg @@ -0,0 +1,207 @@ +# +# Copyright (C) 2012 +# Jamie Lentin j...@lentin.co.uk +# +# Based on dns325 support: +# Copyright (C) 2011 +# Stefan Herbrechtsmeier ste...@code.herbrechtsmeier.net +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=3 @ 200MHz +DATA 0xFFD01400 0x43000618 # DDR Configuration register +# bit13-0: 0x618 DDR2 clks refresh rate +# bit23-14: 0 required +# bit24:1 enable exit self refresh mode on DDR access +# bit25:1 required +#
[U-Boot] [PATCH 1/2] kirkwood: Rename dns325 to dnskw
So we can re-use DNS-325 configuration for the DNS-320 without things getting
confusing, rename all common parts from dns325 to dnskw, and use a config
option to configure DNS-325 specifics.
Signed-off-by: Jamie Lentin j...@lentin.co.uk
Cc: prafu...@marvell.com
Cc: albert.u.b...@aribaud.net
---
board/d-link/{dns325 = dnskw}/Makefile|2 +-
board/d-link/{dns325/dns325.c = dnskw/dnskw.c}| 10
board/d-link/{dns325/dns325.h = dnskw/dnskw.h}| 24
.../kwbimage.cfg = dnskw/kwbimage.dns325.cfg} |0
boards.cfg |2 +-
include/configs/{dns325.h = dnskw.h} | 11 ++---
6 files changed, 29 insertions(+), 20 deletions(-)
rename board/d-link/{dns325 = dnskw}/Makefile (98%)
rename board/d-link/{dns325/dns325.c = dnskw/dnskw.c} (94%)
rename board/d-link/{dns325/dns325.h = dnskw/dnskw.h} (73%)
rename board/d-link/{dns325/kwbimage.cfg = dnskw/kwbimage.dns325.cfg} (100%)
rename include/configs/{dns325.h = dnskw.h} (95%)
diff --git a/board/d-link/dns325/Makefile b/board/d-link/dnskw/Makefile
similarity index 98%
rename from board/d-link/dns325/Makefile
rename to board/d-link/dnskw/Makefile
index 35da21a..174127e 100644
--- a/board/d-link/dns325/Makefile
+++ b/board/d-link/dnskw/Makefile
@@ -30,7 +30,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(BOARD).o
-COBJS := dns325.o
+COBJS := dnskw.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/d-link/dns325/dns325.c b/board/d-link/dnskw/dnskw.c
similarity index 94%
rename from board/d-link/dns325/dns325.c
rename to board/d-link/dnskw/dnskw.c
index 11260fe..d29735c 100644
--- a/board/d-link/dns325/dns325.c
+++ b/board/d-link/dnskw/dnskw.c
@@ -33,15 +33,15 @@
#include asm/arch/kirkwood.h
#include asm/arch/mpp.h
#include asm/arch/gpio.h
-#include dns325.h
+#include dnskw.h
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
/* Gpio configuration */
- kw_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH,
- DNS325_OE_LOW, DNS325_OE_HIGH);
+ kw_config_gpio(DNSKW_OE_VAL_LOW, DNSKW_OE_VAL_HIGH,
+ DNSKW_OE_LOW, DNSKW_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
u32 kwmpp_config[] = {
@@ -99,9 +99,9 @@ int board_early_init_f(void)
};
kirkwood_mpp_conf(kwmpp_config, NULL);
- kw_gpio_set_blink(DNS325_GPIO_LED_POWER , 1);
+ kw_gpio_set_blink(DNSKW_GPIO_LED_POWER , 1);
- kw_gpio_set_value(DNS325_GPIO_SATA0_EN , 1);
+ kw_gpio_set_value(DNSKW_GPIO_SATA0_EN , 1);
return 0;
}
diff --git a/board/d-link/dns325/dns325.h b/board/d-link/dnskw/dnskw.h
similarity index 73%
rename from board/d-link/dns325/dns325.h
rename to board/d-link/dnskw/dnskw.h
index 7859cea..4b11cb6 100644
--- a/board/d-link/dns325/dns325.h
+++ b/board/d-link/dnskw/dnskw.h
@@ -26,18 +26,22 @@
* MA 02110-1301 USA
*/
-#ifndef __DNS325_H
-#define __DNS325_H
+#ifndef __DNSKW_H
+#define __DNSKW_H
/* GPIO configuration */
-#define DNS325_OE_LOW 0x
-#define DNS325_OE_HIGH 0x00039604
-#define DNS325_OE_VAL_LOW 0x3800 /* disable leds */
-#define DNS325_OE_VAL_HIGH 0x0800 /* disable leds */
+#define DNSKW_OE_LOW 0x
+#define DNSKW_OE_HIGH 0x00039604
-#define DNS325_GPIO_LED_POWER 26
-#define DNS325_GPIO_SATA0_EN 39
-#define DNS325_GPIO_SATA1_EN 40
+#define DNSKW_GPIO_LED_POWER 26
+#define DNSKW_GPIO_SATA0_EN39
+#define DNSKW_GPIO_SATA1_EN40
+
+/* DNS-325 specific configuration */
+#ifdef CONFIG_BOARD_IS_DNS325
+#define DNSKW_OE_VAL_LOW 0x3800 /* disable leds */
+#define DNSKW_OE_VAL_HIGH 0x0800 /* disable leds */
+#endif /* CONFIG_BOARD_IS_DNS325 */
/* PHY related */
#define MV88E1116_MAC_CTRL_REG 21
@@ -45,4 +49,4 @@
#define MV88E1116_RGMII_TXTM_CTRL (1 4)
#define MV88E1116_RGMII_RXTM_CTRL (1 5)
-#endif /* __DNS325_H */
+#endif /* __DNSKW_H */
diff --git a/board/d-link/dns325/kwbimage.cfg
b/board/d-link/dnskw/kwbimage.dns325.cfg
similarity index 100%
rename from board/d-link/dns325/kwbimage.cfg
rename to board/d-link/dnskw/kwbimage.dns325.cfg
diff --git a/boards.cfg b/boards.cfg
index 2d36d83..8b8bb45 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -139,7 +139,7 @@ hawkboard_uart arm arm926ejs
da8xxevmdavinci
enbw_cmc arm arm926ejs enbw_cmcenbw
davinci
calimain arm arm926ejs calimain
omicrondavinci
pogo_e02 arm arm926ejs -
cloudengines kirkwood
-dns325 arm arm926ejs -
Re: [U-Boot] [PATCH v4 5/6] tegra: nand: Add Tegra NAND driver
On 07/30/2012 01:53 AM, Simon Glass wrote: From: Jim Lin ji...@nvidia.com A device tree is used to configure the NAND, including memory timings and block/pages sizes. If this node is not present or is disabled, then NAND will not be initialized. Signed-off-by: Jim Lin ji...@nvidia.com Signed-off-by: Simon Glass s...@chromium.org Acked-by: Scott Wood scottw...@freescale.com -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/5] ehci-hcd: Boost transfer speed
Dear Benoît Thébaudeau, [...] Can you explain where this gain would come from? In both cases, the data in USB transfers would be organized in the same way, and it would be accessed in memory also in the same way (regarding bursts). The only difference would be the fetch time of a little bit more qTDs, which is extremely fast and insignificant compared to the transfer time of the payload, which remains unchanged. You are right, the speed different will be minimal, only the memory usage will be lower. If your point is only the memory gain, I agree. With your suggestion, there are roughly 25% less qTDs used in the (max wMaxPacketSize)-aligned but not page-aligned case since the number of qTDs is about (total transfer size) / 5 instead of (total transfer size) / 4. But this is still small compared to usual heap sizes (at least on the kind of hardware I use). Ok, I see the point. I understand it's not really a bug, just an improvement. Maybe we can do a subsequent patch on top of these from Benoit and see how it fares? Moreover, in your use case, if you are e.g. using FAT, on the one hand, the buffers in fat.c are never aligned to more than the DMA min alignment, and on the other hand, if you can align your user buffers to 512 bytes, you can also align them directly to 4 kB. The user buffer is aligned to 4kB, but this doesn't matter as a file load from a storage device (ex. fatload) can be segmented in partial USB transfers. This can lead to any block aligned buffer for a partial transfer. What do you mean by partial USB transfers? As seen from EHCI users like the MSC driver (usb_storage.c), USB transfers either succeed or fail, but they cannot be segmented. Segmented -- like multiple transfers being issues with small payload? You can not put these together at the USB-level, since it's the issuing code that has to be fixed. On its side, the MSC driver will only segment the FAT layer requests if they are larger than 65535 blocks, so still not what you describe. As to the FAT stack, it will only read whole clusters while accessing file payload, and the most usual cluster sizes are by default a multiple of 4 kiB (see http://support.microsoft.com/kb/140365). 512b is minimum and it's quite often used. So I don't see segmentation anywhere, and for usual cluster sizes, the EHCI buffer alignment is fully determined by the applicative buffer alignment and the file position corresponding to the beginning of the applicative buffer. But there are indeed some unusual use cases (e.g. smaller clusters) for which only a block-aligned buffer will reach EHCI despite a page-aligned applicative buffer. I don't quite get this one. My suggestion would be to truncate the xfr_bytes with the max wMaxPacketSize (1024) and for the qtd_count use: if ((uint32_t)buffer 1023)/* wMaxPacketSize unaligned */ qtd_count += DIV_ROUND_UP(((uint32_t)buffer 4095) + length, (QT_BUFFER_CNT - 1) * 4096); else/* wMaxPacketSize aligned */ qtd_count += DIV_ROUND_UP(((uint32_t)buffer 4095) + length, QT_BUFFER_CNT * 4096); This allows 50% of unaligned block data (512) to be transferred with min qTDs. That would also require a realignment-to-page stage. This is specific code for specific buffer alignment from the upper layers. We could also skip the realignment to page and always keep the same qTD transfer size except for the last one, by adding as many packets as possible for the buffer alignment. What you mean by realignment-to-page stage? I mean that the alignment of the transfer to 1024 instead of 4096 can make the first qTD transfer larger than the following ones, which guarantees that the following qTD transfers are page-aligned, even if the first one was only aligned to 1024. For the 1024-aligned case, this results in the change that you suggest, but it also changes things for the unaligned case, which makes this part of the code inaccurate. See below. But I still don't see a significant reason to complicate code to do that. I don't understand where you expect to complicate the code. You limit the size of one transfer (xfr_bytes) to (QT_BUFFER_CNT - 1) * 4kB for unaligned buffers. But you only need to limit it to a multiple of the maximal possible wMaxPacketSize (1kB) to make sure that you always send full packages. I only suggest to replace the causeless 4kB alignment with a reasonable 1kB alignment and adapte the qtd_count caluclation. int xfr_bytes = min(left_length, (QT_BUFFER_CNT * 4096 - ((uint32_t)buf_ptr
Re: [U-Boot] [PATCH v4 4/6] tegra: fdt: Add NAND definitions to fdt
On 07/30/2012 01:53 AM, Simon Glass wrote:
Add a flash node to handle the NAND, including memory timings and
page / block size information.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Update NAND binding to add nvidia, prefix
Changes in v3:
- Add reg property for unit address (should be used for chip select)
- Update fdt binding to make everything Nvidia-specific
Changes in v4:
- Remove fdt bindings related to page structure
board/nvidia/dts/tegra20-seaboard.dts | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/board/nvidia/dts/tegra20-seaboard.dts
b/board/nvidia/dts/tegra20-seaboard.dts
index 3352539..25a63a0 100644
--- a/board/nvidia/dts/tegra20-seaboard.dts
+++ b/board/nvidia/dts/tegra20-seaboard.dts
@@ -153,4 +153,14 @@
0x1f04008a;
linux,fn-keymap = 0x05040002;
};
+
+ nand-controller@70008000 {
+ nvidia,wp-gpios = gpio 59 0; /* PH3 */
+ nvidia,width = 8;
+ nvidia,timing = 26 100 20 80 20 10 12 10 70;
+ nand@0 {
+ reg = 0;
+ compatible = hynix,hy27uf4g2b, nand-flash;
+ };
+ };
Are #address-cells, #size-cells, and reg on the controller node provided
by an /include/?
-Scott
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Re: [U-Boot] usb_test_unit_ready called every block read - performance
Dear Jim Shimer, While tuning ext2load, we found that usb_test_unit_ready was being called every block read. We compared the usb block storage to the scsi block storage cmd_scsi.c, and found that the scsi device was only calling its scsi_setup_test_unit_ready() during scsi_can. It appears that usb_test_unit_ready() really only needs to be called once during usb_stor_scan(), via usb_stor_get_info(). Is there a particular reason usb_test_unit_ready is called for every block read, or do you think its ok to only call during usb_stor_scan()? We're finding this speeds up ext2load quite a bit. Could it be because the USB is actually quite slower than SCSI and the device might get congested? It seems the code was there ever since (I can't seem to find the origin of it) and we might actually want to try if this doesn't break some usb 1.x things. Regards, Jim Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
