[U-Boot] [PATCH 8/9 V2] EXYNOS: Add clock for I2S
This patch adds clock support for I2S
Signed-off-by: R. Chandrasekar
Signed-off-by: Rajeshwari Shinde
---
Changes in V2:
- None
arch/arm/cpu/armv7/exynos/clock.c| 119 ++
arch/arm/include/asm/arch-exynos/clk.h |3 +
arch/arm/include/asm/arch-exynos/clock.h | 29 +++
3 files changed, 151 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 44dff2b..691f6d4 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -26,6 +26,16 @@
#include
#include
+/* Epll Clock division values to achive different frequency output */
+static struct st_epll_con_val epll_div[] = {
+ { 19200, 0, 48, 3, 1, 0 },
+ { 18000, 0, 45, 3, 1, 0 },
+ { 73728000, 1, 73, 3, 3, 47710 },
+ { 67737600, 1, 90, 4, 3, 20762 },
+ { 49152000, 0, 49, 3, 3, 9961 },
+ { 45158400, 0, 45, 3, 3, 10381 },
+ { 180633600, 0, 45, 3, 1, 10381 }
+};
/* exynos4: return pll clock frequency */
static unsigned long exynos4_get_pll_clk(int pllreg)
{
@@ -848,6 +858,92 @@ static int exynos5_spi_set_clock_rate(enum periph_id
periph_id,
return 0;
}
+int exynos5_clock_epll_set_rate(unsigned long rate)
+{
+ unsigned int epll_con, epll_con_k;
+ unsigned int i;
+ unsigned int lockcnt;
+ unsigned int start;
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+
+ epll_con = readl(&clk->epll_con0);
+ epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK <<
+ EPLL_CON0_LOCK_DET_EN_SHIFT) |
+ EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT |
+ EPLL_CON0_PDIV_MASK << EPLL_CON0_PDIV_SHIFT |
+ EPLL_CON0_SDIV_MASK << EPLL_CON0_SDIV_SHIFT);
+
+ for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
+ if (epll_div[i].freq_out == rate)
+ break;
+ }
+
+ if (i == ARRAY_SIZE(epll_div))
+ return -1;
+
+ epll_con_k = epll_div[i].k_dsm << 0;
+ epll_con |= epll_div[i].en_lock_det << EPLL_CON0_LOCK_DET_EN_SHIFT;
+ epll_con |= epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT;
+ epll_con |= epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT;
+ epll_con |= epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
+
+ /*
+* Required period ( in cycles) to genarate a stable clock output.
+* The maximum clock time can be up to 3000 * PDIV cycles of PLLs
+* frequency input (as per spec)
+*/
+ lockcnt = 3000 * epll_div[i].p_div;
+
+ writel(lockcnt, &clk->epll_lock);
+ writel(epll_con, &clk->epll_con0);
+ writel(epll_con_k, &clk->epll_con1);
+
+ start = get_timer(0);
+
+while (!(readl(&clk->epll_con0) &
+ (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) {
+ if (get_timer(start) > TIMEOUT_EPLL_LOCK) {
+ debug("%s: Timeout waiting for EPLL lock\n", __func__);
+ return -1;
+ }
+ }
+ return 0;
+}
+
+void exynos5_clock_select_i2s_clk_source(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+
+ clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK,
+ (CLK_SRC_SCLK_EPLL));
+}
+
+int exynos5_clock_set_i2s_clk_prescaler(unsigned int src_frq,
+ unsigned int dst_frq)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned int div;
+
+ if ((dst_frq == 0) || (src_frq == 0)) {
+ debug("%s: Invalid requency input for prescaler\n", __func__);
+ debug("src frq = %d des frq = %d ", src_frq, dst_frq);
+ return -1;
+ }
+
+ div = (src_frq / dst_frq);
+ if (div > AUDIO_1_RATIO_MASK) {
+ debug("%s: Frequency ratio is out of range\n", __func__);
+ debug("src frq = %d des frq = %d ", src_frq, dst_frq);
+ return -1;
+ }
+ clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK,
+ (div & AUDIO_1_RATIO_MASK));
+ return 0;
+}
+
unsigned long get_pll_clk(int pllreg)
{
if (cpu_is_exynos5())
@@ -927,3 +1023,26 @@ int spi_set_clock_rate(enum periph_id periph_id, unsigned
int rate)
else
return 0;
}
+
+int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq)
+{
+
+ if (cpu_is_exynos5())
+ return exynos5_clock_set_i2s_clk_prescaler(src_frq, dst_frq);
+ else
+ return 0;
+}
+
+void clock_select_i2s_clk_source(void)
+{
+ if (cpu_is_exynos5())
+ exynos5_clock_select_i2s_clk_source();
+}
+
+int clock_epll_set_rate(unsigned long rate)
+{
+ if (cpu_is_exynos5())
+ return exynos5_clock_epll_set
[U-Boot] [PATCH 7/9 V2] EXYNOS: Add I2S base address
This patch adds base address for I2S Signed-off-by: Rajeshwari Shinde --- Changes in V2: - None arch/arm/include/asm/arch-exynos/cpu.h |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index 252a5b3..f32e778 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -55,6 +55,7 @@ #define EXYNOS4_PWMTIMER_BASE 0x139D #define EXYNOS4_MODEM_BASE 0x13A0 #define EXYNOS4_USBPHY_CONTROL 0x10020704 +#define EXYNOS4_I2S_BASE 0xE210 #define EXYNOS4_GPIO_PART4_BASEDEVICE_NOT_AVAILABLE #define EXYNOS4_DP_BASEDEVICE_NOT_AVAILABLE @@ -84,6 +85,7 @@ #define EXYNOS5_UART_BASE 0x12C0 #define EXYNOS5_I2C_BASE 0x12C6 #define EXYNOS5_SPI_BASE 0x12D2 +#define EXYNOS5_I2S_BASE 0x12D6 #define EXYNOS5_PWMTIMER_BASE 0x12DD #define EXYNOS5_SPI_ISP_BASE 0x131A #define EXYNOS5_GPIO_PART2_BASE0x1340 @@ -160,6 +162,7 @@ SAMSUNG_BASE(dp, DP_BASE) SAMSUNG_BASE(sysreg, SYSREG_BASE) SAMSUNG_BASE(fimd, FIMD_BASE) SAMSUNG_BASE(i2c, I2C_BASE) +SAMSUNG_BASE(i2s, I2S_BASE) SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE) SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE) SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE) -- 1.7.4.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 9/9 V2] SMDK5250: Enable Sound
This patch enables sound support for EXYNOS5 Signed-off-by: Rajeshwari Shinde --- Changes in V2: - corrected the commit message. include/configs/smdk5250.h |8 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 29b7ac6..1463137 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -237,6 +237,14 @@ #define CONFIG_ENV_SPI_MAX_HZ 5000 #endif +/* Sound */ +#define CONFIG_CMD_SOUND +#ifdef CONFIG_CMD_SOUND +#define CONFIG_SOUND +#define CONFIG_I2S +#define CONFIG_SOUND_WM8994 +#endif + /* Enable devicetree support */ #define CONFIG_OF_LIBFDT -- 1.7.4.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 6/9 V2] EXYNOS: Add pinmux for I2S
This patch adds pinmux support for I2S1
Signed-off-by: Rajeshwari Shinde
---
Changes in V2:
- made exynos_i2s_config pinmux function static.
arch/arm/cpu/armv7/exynos/pinmux.c| 12
arch/arm/include/asm/arch-exynos/periph.h |1 +
2 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
b/arch/arm/cpu/armv7/exynos/pinmux.c
index 13f75e0..ed82bc3 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -273,6 +273,15 @@ void exynos5_spi_config(int peripheral)
}
}
+static void exynos5_i2s_config(int peripheral)
+{
+ int i;
+ struct exynos5_gpio_part1 *gpio1 =
+ (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+ for (i = 0; i < 5; i++)
+ s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
+}
+
static int exynos5_pinmux_config(int peripheral, int flags)
{
switch (peripheral) {
@@ -307,6 +316,9 @@ static int exynos5_pinmux_config(int peripheral, int flags)
case PERIPH_ID_SPI4:
exynos5_spi_config(peripheral);
break;
+ case PERIPH_ID_I2S1:
+ exynos5_i2s_config(peripheral);
+ break;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return -1;
diff --git a/arch/arm/include/asm/arch-exynos/periph.h
b/arch/arm/include/asm/arch-exynos/periph.h
index dafc3f3..404e5db 100644
--- a/arch/arm/include/asm/arch-exynos/periph.h
+++ b/arch/arm/include/asm/arch-exynos/periph.h
@@ -38,6 +38,7 @@ enum periph_id {
PERIPH_ID_I2C5,
PERIPH_ID_I2C6,
PERIPH_ID_I2C7,
+ PERIPH_ID_I2S1,
PERIPH_ID_SDMMC0,
PERIPH_ID_SDMMC1,
PERIPH_ID_SDMMC2,
--
1.7.4.4
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[U-Boot] [PATCH 4/9 V2] EXYNOS: Add I2S registers
This patch add I2S registers Signed-off-by: R. Chandrasekar Signed-off-by: Rajeshwari Shinde --- Changes in V2: - None arch/arm/include/asm/arch-exynos/i2s-regs.h | 66 +++ 1 files changed, 66 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-exynos/i2s-regs.h diff --git a/arch/arm/include/asm/arch-exynos/i2s-regs.h b/arch/arm/include/asm/arch-exynos/i2s-regs.h new file mode 100644 index 000..2326ca0 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/i2s-regs.h @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * R. Chandrasekar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __I2S_REGS_H__ +#define __I2S_REGS_H__ + +#define CON_TXFIFO_FULL(1 << 8) +#define CON_TXCH_PAUSE (1 << 4) +#define CON_ACTIVE (1 << 0) + +#define MOD_BLCP_SHIFT 24 +#define MOD_BLCP_16BIT (0 << MOD_BLCP_SHIFT) +#define MOD_BLCP_8BIT (1 << MOD_BLCP_SHIFT) +#define MOD_BLCP_24BIT (2 << MOD_BLCP_SHIFT) +#define MOD_BLCP_MASK (3 << MOD_BLCP_SHIFT) + +#define MOD_BLC_16BIT (0 << 13) +#define MOD_BLC_8BIT (1 << 13) +#define MOD_BLC_24BIT (2 << 13) +#define MOD_BLC_MASK (3 << 13) + +#define MOD_SLAVE (1 << 11) +#define MOD_MASK (3 << 8) +#define MOD_LR_LLOW(0 << 7) +#define MOD_LR_RLOW(1 << 7) +#define MOD_SDF_IIS(0 << 5) +#define MOD_SDF_MSB(1 << 5) +#define MOD_SDF_LSB(2 << 5) +#define MOD_SDF_MASK (3 << 5) +#define MOD_RCLK_256FS (0 << 3) +#define MOD_RCLK_512FS (1 << 3) +#define MOD_RCLK_384FS (2 << 3) +#define MOD_RCLK_768FS (3 << 3) +#define MOD_RCLK_MASK (3 << 3) +#define MOD_BCLK_32FS (0 << 1) +#define MOD_BCLK_48FS (1 << 1) +#define MOD_BCLK_16FS (2 << 1) +#define MOD_BCLK_24FS (3 << 1) +#define MOD_BCLK_MASK (3 << 1) + +#define MOD_CDCLKCON (1 << 12) + +#define FIC_TXFLUSH(1 << 15) +#define FIC_RXFLUSH(1 << 7) + +#endif /* __I2S_REGS_H__ */ -- 1.7.4.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/9 V2] EXYNOS: Add parameters required by I2S
This patch adds the audio parameters required by the I2S to play the predefined audio data. Signed-off-by: Rajeshwari Shinde --- Changes in V2: - None arch/arm/include/asm/arch-exynos/sound.h | 44 ++ 1 files changed, 44 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-exynos/sound.h diff --git a/arch/arm/include/asm/arch-exynos/sound.h b/arch/arm/include/asm/arch-exynos/sound.h new file mode 100644 index 000..d25d4f2 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/sound.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Rajeshwari Shinde + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef __SOUND_ARCH_H__ +#define __SOUND_ARCH_H__ + +/* I2S values */ +#define I2S_PLL_CLK19200 +#define I2S_SAMPLING_RATE 48000 +#define I2S_BITS_PER_SAMPLE16 +#define I2S_CHANNELS 2 +#define I2S_RFS256 +#define I2S_BFS32 + +/* I2C values */ +#define AUDIO_I2C_BUS 1 +#define AUDIO_I2C_REG 0x34 + +/* Audio Codec */ +#define AUDIO_CODEC"wm8994" + +#define AUDIO_COMPAT 1 +#endif -- 1.7.4.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/9 V2] Sound: Add command for audio playback
This patch adds command to test audio playback.
sound init - Initialises the audio subsystem (i2s and wm8994 codec)
sound play - Plays predefined the audio data.
Signed-off-by: Rajeshwari Shinde
---
Changes in V2:
- None
common/Makefile|1 +
common/cmd_sound.c | 90
2 files changed, 91 insertions(+), 0 deletions(-)
create mode 100644 common/cmd_sound.c
diff --git a/common/Makefile b/common/Makefile
index 483eb4d..a21cac9 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -73,6 +73,7 @@ COBJS-$(CONFIG_CMD_CONSOLE) += cmd_console.o
COBJS-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o
COBJS-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o
COBJS-$(CONFIG_CMD_DATE) += cmd_date.o
+COBJS-$(CONFIG_CMD_SOUND) += cmd_sound.o
ifdef CONFIG_4xx
COBJS-$(CONFIG_CMD_SETGETDCR) += cmd_dcr.o
endif
diff --git a/common/cmd_sound.c b/common/cmd_sound.c
new file mode 100644
index 000..9684435
--- /dev/null
+++ b/common/cmd_sound.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Rajeshwari Shinde
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+
+/* globaldata */
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Initilaise sound subsystem */
+static int do_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ int ret;
+
+ ret = sound_init();
+ if (ret) {
+ printf("Initialise Audio driver failed\n");
+ return CMD_RET_FAILURE;
+ }
+
+ return 0;
+}
+
+/* play sound from buffer */
+static int do_play(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ int ret = 0;
+
+ ret = sound_play();
+ if (ret) {
+ printf("play failed");
+ return CMD_RET_FAILURE;
+ }
+
+ return 0;
+}
+
+static cmd_tbl_t cmd_sound_sub[] = {
+ U_BOOT_CMD_MKENT(init, 0, 1, do_init, "", ""),
+ U_BOOT_CMD_MKENT(play, 2, 1, do_play, "", ""),
+};
+
+/* process sound command */
+static int do_sound(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ cmd_tbl_t *c;
+
+ if (argc < 1)
+ return CMD_RET_USAGE;
+
+ /* Strip off leading 'sound' command argument */
+ argc--;
+ argv++;
+
+ c = find_cmd_tbl(argv[0], &cmd_sound_sub[0], ARRAY_SIZE(cmd_sound_sub));
+
+ if (c)
+ return c->cmd(cmdtp, flag, argc, argv);
+ else
+ return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+ sound, 3, 1, do_sound,
+ "sound sub-system",
+ "init - initialise the sound driver\n"
+ "sound play - play predefind sound\n"
+);
--
1.7.4.4
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[U-Boot] [PATCH 1/9 V2] SOUND: Add I2S driver
This patch adds driver for I2S interface specific to samsung.
Signed-off-by: R. Chandrasekar
Signed-off-by: Rajeshwari Shinde
---
Changes in V2:
- renamed i2s.c to samsung-i2s.c.
Makefile|1 +
drivers/sound/Makefile | 47 ++
drivers/sound/samsung-i2s.c | 358 +++
drivers/sound/sound.c | 220 ++
include/i2s.h | 127 +++
include/sound.h | 62
6 files changed, 815 insertions(+), 0 deletions(-)
create mode 100644 drivers/sound/Makefile
create mode 100644 drivers/sound/samsung-i2s.c
create mode 100644 drivers/sound/sound.c
create mode 100644 include/i2s.h
create mode 100644 include/sound.h
diff --git a/Makefile b/Makefile
index f6471e2..fc929e8e 100644
--- a/Makefile
+++ b/Makefile
@@ -288,6 +288,7 @@ LIBS += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
endif
LIBS += drivers/rtc/librtc.o
LIBS += drivers/serial/libserial.o
+LIBS += drivers/sound/libsound.o
ifeq ($(CONFIG_GENERIC_LPC_TPM),y)
LIBS += drivers/tpm/libtpm.o
endif
diff --git a/drivers/sound/Makefile b/drivers/sound/Makefile
new file mode 100644
index 000..18ad2c9
--- /dev/null
+++ b/drivers/sound/Makefile
@@ -0,0 +1,47 @@
+#
+# Copyright (C) 2012 Samsung Electronics
+# R. Chandrasekar
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB:= $(obj)libsound.o
+
+COBJS-$(CONFIG_SOUND) += sound.o
+COBJS-$(CONFIG_I2S)+= samsung-i2s.o
+
+COBJS := $(COBJS-y)
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+all: $(LIB)
+
+$(LIB):$(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/drivers/sound/samsung-i2s.c b/drivers/sound/samsung-i2s.c
new file mode 100644
index 000..9485980
--- /dev/null
+++ b/drivers/sound/samsung-i2s.c
@@ -0,0 +1,358 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * R. Chandrasekar
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define FIC_TX2COUNT(x)(((x) >> 24) & 0xf)
+#define FIC_TX1COUNT(x)(((x) >> 16) & 0xf)
+#define FIC_TXCOUNT(x) (((x) >> 8) & 0xf)
+#define FIC_RXCOUNT(x) (((x) >> 0) & 0xf)
+#define FICS_TXCOUNT(x)(((x) >> 8) & 0x7f)
+
+#define TIMEOUT_I2S_TX 100 /* i2s transfer timeout */
+
+/*
+ * Sets the frame size for I2S LR clock
+ *
+ * @param i2s_reg i2s regiter address
+ * @param rfs Frame Size
+ */
+static void i2s_set_lr_framesize(struct i2s_reg *i2s_reg, unsigned int rfs)
+{
+ unsigned int mod = readl(&i2s_reg->mod);
+
+ mod &= ~MOD_RCLK_MASK;
+
+ switch (rfs) {
+ case 768:
+ mod |= MOD_RCLK_768FS;
+ break;
+ case 512:
+ mod |= MOD_RCLK_512FS;
+ break;
+ case 384:
+ mod |= MOD_RCLK_384FS;
+ break;
+ default:
+ mod |= MOD_RCLK_256FS;
+ break;
+ }
+
+ writel(mod, &i2s_reg->mod);
+}
+
+/*
+ * Sets the i2s transfer control
+ *
+ * @param i2s_reg i2s regiter address
+ * @param on 1 enable tx , 0 disable tx transfer
+ */
+static void i2s_txctrl(str
[U-Boot] [PATCH 2/9 V2] SOUND: Add WM8994 codec
This pastc adds driver for audio codec WM8994
Signed-off-by: R. Chandrasekar
Signed-off-by: Rajeshwari Shinde
---
Changes in V2:
- None
drivers/sound/Makefile |1 +
drivers/sound/wm8994.c | 781 ++
drivers/sound/wm8994.h | 87 +
drivers/sound/wm8994_registers.h | 299 +++
4 files changed, 1168 insertions(+), 0 deletions(-)
create mode 100644 drivers/sound/wm8994.c
create mode 100644 drivers/sound/wm8994.h
create mode 100644 drivers/sound/wm8994_registers.h
diff --git a/drivers/sound/Makefile b/drivers/sound/Makefile
index 18ad2c9..8fdffb1 100644
--- a/drivers/sound/Makefile
+++ b/drivers/sound/Makefile
@@ -27,6 +27,7 @@ LIB := $(obj)libsound.o
COBJS-$(CONFIG_SOUND) += sound.o
COBJS-$(CONFIG_I2S)+= samsung-i2s.o
+COBJS-$(CONFIG_SOUND_WM8994) += wm8994.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/sound/wm8994.c b/drivers/sound/wm8994.c
new file mode 100644
index 000..21604f1
--- /dev/null
+++ b/drivers/sound/wm8994.c
@@ -0,0 +1,781 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * R. Chandrasekar
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#define DEBUG
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "wm8994.h"
+#include "wm8994_registers.h"
+
+/* defines for wm8994 system clock selection */
+#define SEL_MCLK1 0x00
+#define SEL_MCLK2 0x08
+#define SEL_FLL1 0x10
+#define SEL_FLL2 0x18
+
+/* fll config to configure fll */
+struct wm8994_fll_config {
+ int src;/* Source */
+ int in; /* Input frequency in Hz */
+ int out;/* output frequency in Hz */
+};
+
+/* codec private data */
+struct wm8994_priv {
+ enum wm8994_type type; /* codec type of wolfson */
+ int revision; /* Revision */
+ int sysclk[WM8994_MAX_AIF]; /* System clock freqency in Hz */
+ int mclk[WM8994_MAX_AIF]; /* master clock frequency in Hz */
+ int aifclk[WM8994_MAX_AIF]; /* audio interfce clock in Hz */
+ struct wm8994_fll_config fll[2]; /* fll config to configure fll */
+};
+
+/* wm 8994 supported sampling rate vlaues */
+static unsigned int src_rate[] = {
+8000, 11025, 12000, 16000, 22050, 24000,
+32000, 44100, 48000, 88200, 96000
+};
+
+/* op clock divisions */
+static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
+
+/* lr clock framsize ratio */
+static int fs_ratios[] = {
+ 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
+};
+
+/* bit clock divisions */
+static int bclk_divs[] = {
+ 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
+ 640, 880, 960, 1280, 1760, 1920
+};
+
+/* Global */
+struct wm8994_priv g_wm8994_info;
+unsigned int g_wm8994_i2c_dev_addr;
+
+/*
+ * Initialise I2C for wm 8994
+ *
+ * @param bus no i2c bus number in which wm8994 is connected
+ */
+static void wm8994_i2c_init(int bus_no)
+{
+ i2c_set_bus_num(bus_no);
+}
+
+/*
+ * Writes value to a device register through i2c
+ *
+ * @param reg reg number to be write
+ * @param data data to be writen to the above registor
+ *
+ * @return int value 1 for change, 0 for no change or negative error code.
+ */
+static int wm8994_i2c_write(unsigned int reg, unsigned short data)
+{
+ unsigned char val[2];
+
+ val[0] = (unsigned char)((data >> 8) & 0xff);
+ val[1] = (unsigned char)(data & 0xff);
+ debug("Write Addr : 0x%04X, Data : 0x%04X\n", reg, data);
+
+ return i2c_write(g_wm8994_i2c_dev_addr, reg, 2, val, 2);
+}
+
+/*
+ * Read a value from a device register through i2c
+ *
+ * @param reg reg number to be read
+ * @param data address of read data to be stored
+ *
+ * @return int value 0 for success, -1 in case of error.
+ */
+static unsigned int wm8994_i2c_read(unsigned int reg , unsigned short *data)
+{
+ unsigned char val[2];
+ int ret;
+
+ ret = i2c_read(g_wm8994_i2c_dev_addr, reg, 2, val, 2);
+ if (ret != 0) {
+ debug("%s: Error while reading register %#04x\n",
+
[U-Boot] [PATCH 0/9 V2] EXYNOS5: Add Audio support
This patchset adds the audio support for EXYNOS5. This patchset plays a predefined beep sound. This patchset is based on the following patches: "[U-Boot] [PATCH 1/7 V4] EXYNOS5: Add pinmux support for SPI" "[U-Boot] [PATCH 4/7 V3] EXYNOS5: Add base address for SPI" "[U-Boot] [PATCH 3/7 V3] EXYNOS: Add clock for SPI" Changes in V2: - renamed i2s.c to samsung-i2s.c. - made exynos_i2s_config pinmux function static. - corrected the commit message for "Enable sound" patch. Rajeshwari Shinde (9): SOUND: Add I2S driver SOUND: Add WM8994 codec Sound: Add command for audio playback EXYNOS: Add I2S registers EXYNOS: Add parameters required by I2S EXYNOS: Add pinmux for I2S EXYNOS: Add I2S base address EXYNOS: Add clock for I2S SMDK5250: Enable Sound Makefile|1 + arch/arm/cpu/armv7/exynos/clock.c | 119 arch/arm/cpu/armv7/exynos/pinmux.c | 12 + arch/arm/include/asm/arch-exynos/clk.h |3 + arch/arm/include/asm/arch-exynos/clock.h| 29 + arch/arm/include/asm/arch-exynos/cpu.h |3 + arch/arm/include/asm/arch-exynos/i2s-regs.h | 66 +++ arch/arm/include/asm/arch-exynos/periph.h |1 + arch/arm/include/asm/arch-exynos/sound.h| 44 ++ common/Makefile |1 + common/cmd_sound.c | 90 +++ drivers/sound/Makefile | 48 ++ drivers/sound/samsung-i2s.c | 358 drivers/sound/sound.c | 220 drivers/sound/wm8994.c | 781 +++ drivers/sound/wm8994.h | 87 +++ drivers/sound/wm8994_registers.h| 299 ++ include/configs/smdk5250.h |8 + include/i2s.h | 127 + include/sound.h | 62 +++ 20 files changed, 2359 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-exynos/i2s-regs.h create mode 100644 arch/arm/include/asm/arch-exynos/sound.h create mode 100644 common/cmd_sound.c create mode 100644 drivers/sound/Makefile create mode 100644 drivers/sound/samsung-i2s.c create mode 100644 drivers/sound/sound.c create mode 100644 drivers/sound/wm8994.c create mode 100644 drivers/sound/wm8994.h create mode 100644 drivers/sound/wm8994_registers.h create mode 100644 include/i2s.h create mode 100644 include/sound.h -- 1.7.4.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 16/18] da850_am18xxevm: Add README.da850_am18xxevm
On Tue, Aug 21, 2012 at 9:46 PM, Prabhakar Lad wrote: > On Tuesday 21 August 2012 09:04 PM, Tom Rini wrote: >> On 08/20/2012 10:09 PM, Prabhakar Lad wrote: >>> Hi Tom, >>> >>> Thanks for the patch. >>> >>> On Monday 20 August 2012 10:15 PM, Tom Rini wrote: Add a board-specific README that documents how to write u-boot.ais to the SPI found on this board. Changes-series: 2 - Add Signed-off-by: Tom Rini --- board/davinci/da8xxevm/README.da850_am18xxevm | 53 + 1 file changed, 53 insertions(+) create mode 100644 board/davinci/da8xxevm/README.da850_am18xxevm diff --git a/board/davinci/da8xxevm/README.da850_am18xxevm b/board/davinci/da8xxevm/README.da850_am18xxevm new file mode 100644 index 000..382b718 --- /dev/null +++ b/board/davinci/da8xxevm/README.da850_am18xxevm @@ -0,0 +1,53 @@ +Summary +=== +The README is for the boot procedure used for the LogicPD AM1808 EVM. + +The board is booted in three stages. The initial bootloader which executes +upon reset is the Rom Boot Loader(RBL) which sits in the internal ROM. The +RBL initialises the memory and the SPI controller and reads the AIS image +starting at block 0. This image can contain both the SPL and U-Boot +binaries. + +AIS is an image format defined by TI for the images that are to be +loaded to memory by the RBL. The image is divided into a series of +sections and the image's entry point is specified. Each section comes +with meta data like the target address the section is to be copied to +and the size of the section, which is used by the RBL to load the +image. At the end of the image the RBL jumps to the image entry +point. + +The secondary stage bootloader(spl) which is loaded by the RBL then loads +the u-boot from a predefined location in SPI to DDR and jumps to the u-boot +entry point. + + +Compilation +=== +To build a SPI-bootable image, run 'make da850_am18xxevm'. This will build +the u-boot.ais file that needs to be written to SPI flash. + + +Flashing the images to Nand +=== +The AIS image can be written to SPI flash using the following commands. +Assuming that the network is configured and enabled and the u-boot.ais file +is tftp'able. + +U-Boot > sf probe 0 +U-Boot > sf erase 0 +32 +U-Boot > tftp u-boot.ais +U-Boot > sf write c070 0 $filesize + >>> Is this procedure to be done in Nand boot mode ? >> >> This board, as far as I know (which isn't much) doesn't use NAND, just >> SPI. The USE_NAND section of da850evm.h doesn't seem reachable today at >> least. >> > But the title for above says 'Flashing the images to Nand' ? It should > be SPI. You are correct, thanks. -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 16/18] da850_am18xxevm: Add README.da850_am18xxevm
On Tuesday 21 August 2012 09:04 PM, Tom Rini wrote: > On 08/20/2012 10:09 PM, Prabhakar Lad wrote: >> Hi Tom, >> >> Thanks for the patch. >> >> On Monday 20 August 2012 10:15 PM, Tom Rini wrote: >>> Add a board-specific README that documents how to write u-boot.ais to >>> the SPI found on this board. >>> >>> Changes-series: 2 >>> - Add >>> >>> Signed-off-by: Tom Rini >>> --- >>> >>> board/davinci/da8xxevm/README.da850_am18xxevm | 53 >>> + >>> 1 file changed, 53 insertions(+) >>> create mode 100644 board/davinci/da8xxevm/README.da850_am18xxevm >>> >>> diff --git a/board/davinci/da8xxevm/README.da850_am18xxevm >>> b/board/davinci/da8xxevm/README.da850_am18xxevm >>> new file mode 100644 >>> index 000..382b718 >>> --- /dev/null >>> +++ b/board/davinci/da8xxevm/README.da850_am18xxevm >>> @@ -0,0 +1,53 @@ >>> +Summary >>> +=== >>> +The README is for the boot procedure used for the LogicPD AM1808 EVM. >>> + >>> +The board is booted in three stages. The initial bootloader which executes >>> +upon reset is the Rom Boot Loader(RBL) which sits in the internal ROM. The >>> +RBL initialises the memory and the SPI controller and reads the AIS image >>> +starting at block 0. This image can contain both the SPL and U-Boot >>> +binaries. >>> + >>> +AIS is an image format defined by TI for the images that are to be >>> +loaded to memory by the RBL. The image is divided into a series of >>> +sections and the image's entry point is specified. Each section comes >>> +with meta data like the target address the section is to be copied to >>> +and the size of the section, which is used by the RBL to load the >>> +image. At the end of the image the RBL jumps to the image entry >>> +point. >>> + >>> +The secondary stage bootloader(spl) which is loaded by the RBL then loads >>> +the u-boot from a predefined location in SPI to DDR and jumps to the u-boot >>> +entry point. >>> + >>> + >>> +Compilation >>> +=== >>> +To build a SPI-bootable image, run 'make da850_am18xxevm'. This will build >>> +the u-boot.ais file that needs to be written to SPI flash. >>> + >>> + >>> +Flashing the images to Nand >>> +=== >>> +The AIS image can be written to SPI flash using the following commands. >>> +Assuming that the network is configured and enabled and the u-boot.ais file >>> +is tftp'able. >>> + >>> +U-Boot > sf probe 0 >>> +U-Boot > sf erase 0 +32 >>> +U-Boot > tftp u-boot.ais >>> +U-Boot > sf write c070 0 $filesize >>> + >> Is this procedure to be done in Nand boot mode ? > > This board, as far as I know (which isn't much) doesn't use NAND, just > SPI. The USE_NAND section of da850evm.h doesn't seem reachable today at > least. > But the title for above says 'Flashing the images to Nand' ? It should be SPI. Thx, --Prabhakar ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm:at91-boards: remove console_init_f where unnecessary
Hi Andreas,
On 8/17/2012 0:01, Andreas Bießmann wrote:
A lot of at91 boards have the console_init_f in board_init. This is useless
cause it was called before by generic code in lib/board.c.
Signed-off-by: Andreas Bießmann
cc: Jens Scharsig
cc: Stelian Pop
cc: Sedji Gaouaou
cc: Albin Tonnerre
cc: Eric Benard
---
board/BuS/eb_cpux9k2/cpux9k2.c |2 --
board/BuS/vl_ma2sc/vl_ma2sc.c |3 ---
board/atmel/at91sam9261ek/at91sam9261ek.c |3 ---
board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c |3 ---
board/atmel/at91sam9rlek/at91sam9rlek.c |3 ---
board/calao/sbc35_a9g20/sbc35_a9g20.c |3 ---
board/calao/tny_a9260/tny_a9260.c |3 ---
board/eukrea/cpuat91/cpuat91.c |2 --
8 files changed, 22 deletions(-)
diff --git a/board/BuS/eb_cpux9k2/cpux9k2.c b/board/BuS/eb_cpux9k2/cpux9k2.c
index 54f9b64..776226f 100644
--- a/board/BuS/eb_cpux9k2/cpux9k2.c
+++ b/board/BuS/eb_cpux9k2/cpux9k2.c
@@ -59,8 +59,6 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
- /* Enable Ctrlc */
- console_init_f();
/* Correct IRDA resistor problem / Set PA23_TXD in Output */
writel(ATMEL_PMX_AA_TXD2, &pio->pioa.oer);
diff --git a/board/BuS/vl_ma2sc/vl_ma2sc.c b/board/BuS/vl_ma2sc/vl_ma2sc.c
index 62ed6fb..84b2060 100644
--- a/board/BuS/vl_ma2sc/vl_ma2sc.c
+++ b/board/BuS/vl_ma2sc/vl_ma2sc.c
@@ -244,9 +244,6 @@ int board_init(void)
writel(pin, &pio->piod.odr);
writel(pin, &pio->piod.owdr);
- /* Enable Ctrlc */
- console_init_f();
-
gd->bd->bi_arch_number = MACH_TYPE_VL_MA2SC;
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c
b/board/atmel/at91sam9261ek/at91sam9261ek.c
index 47ab839..d30a1ee 100644
--- a/board/atmel/at91sam9261ek/at91sam9261ek.c
+++ b/board/atmel/at91sam9261ek/at91sam9261ek.c
@@ -242,9 +242,6 @@ void lcd_show_board_info(void)
int board_init(void)
{
- /* Enable Ctrlc */
- console_init_f();
-
Tested on at91sam9g10ek board. It works well without this.
Tested-by: voice.s...@atmel.com
#ifdef CONFIG_AT91SAM9G10EK
/* arch number of AT91SAM9G10EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK;
diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
index 5a04274..d02312c 100644
--- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
@@ -258,9 +258,6 @@ int board_early_init_f(void)
int board_init(void)
{
- /* Enable Ctrlc */
- console_init_f();
-
Tested on at91sam9m10g45ek board. It works well without this.
Tested-by: voice.s...@atmel.com
/* arch number of AT91SAM9M10G45EK-Board */
#ifdef CONFIG_AT91SAM9M10G45EK
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c
b/board/atmel/at91sam9rlek/at91sam9rlek.c
index ef0ddd7..e92ec6e 100644
--- a/board/atmel/at91sam9rlek/at91sam9rlek.c
+++ b/board/atmel/at91sam9rlek/at91sam9rlek.c
@@ -192,9 +192,6 @@ int board_early_init_f(void)
int board_init(void)
{
- /* Enable Ctrlc */
- console_init_f();
-
/* arch number of AT91SAM9RLEK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
/* adress of boot parameters */
diff --git a/board/calao/sbc35_a9g20/sbc35_a9g20.c
b/board/calao/sbc35_a9g20/sbc35_a9g20.c
index b6c8791..d3b3684 100644
--- a/board/calao/sbc35_a9g20/sbc35_a9g20.c
+++ b/board/calao/sbc35_a9g20/sbc35_a9g20.c
@@ -149,9 +149,6 @@ static void sbc35_a9g20_macb_hw_init(void)
int board_init(void)
{
- /* Enable Ctrlc */
- console_init_f();
-
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
diff --git a/board/calao/tny_a9260/tny_a9260.c
b/board/calao/tny_a9260/tny_a9260.c
index 31074d0..86e7e65 100644
--- a/board/calao/tny_a9260/tny_a9260.c
+++ b/board/calao/tny_a9260/tny_a9260.c
@@ -83,9 +83,6 @@ static void tny_a9260_nand_hw_init(void)
int board_init(void)
{
- /* Enable Ctrlc */
- console_init_f();
-
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
diff --git a/board/eukrea/cpuat91/cpuat91.c b/board/eukrea/cpuat91/cpuat91.c
index f654f87..c74c3fc 100644
--- a/board/eukrea/cpuat91/cpuat91.c
+++ b/board/eukrea/cpuat91/cpuat91.c
@@ -43,8 +43,6 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
- /* Enable Ctrlc */
- console_init_f();
/* arch number of CPUAT91-Board */
gd->bd->bi_arch_number = MACH_TYPE_CPUAT91;
/* adress of boot parameters */
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Re: [U-Boot] [PATCH 6/9] EXYNOS: Add pinmux for I2S
Hi Chander,
On Tue, Aug 21, 2012 at 3:26 PM, Chander Kashyap
wrote:
> hi,
>
> On 14 August 2012 11:15, Rajeshwari Shinde wrote:
>> This patch adds pinmux support for I2S1
>>
>> Signed-off-by: Rajeshwari Shinde
>> ---
>> arch/arm/cpu/armv7/exynos/pinmux.c| 12
>> arch/arm/include/asm/arch-exynos/periph.h |1 +
>> 2 files changed, 13 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
>> b/arch/arm/cpu/armv7/exynos/pinmux.c
>> index 13f75e0..ba25f6c 100644
>> --- a/arch/arm/cpu/armv7/exynos/pinmux.c
>> +++ b/arch/arm/cpu/armv7/exynos/pinmux.c
>> @@ -273,6 +273,15 @@ void exynos5_spi_config(int peripheral)
>> }
>> }
>>
>
>> +void exynos5_i2s_config(int peripheral)
> make it static.
- Ok
>> +{
>> + int i;
>> + struct exynos5_gpio_part1 *gpio1 =
>> + (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
>> + for (i = 0; i < 5; i++)
>> + s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
>> +}
>> +
>> static int exynos5_pinmux_config(int peripheral, int flags)
>> {
>> switch (peripheral) {
>> @@ -307,6 +316,9 @@ static int exynos5_pinmux_config(int peripheral, int
>> flags)
>> case PERIPH_ID_SPI4:
>> exynos5_spi_config(peripheral);
>> break;
>> + case PERIPH_ID_I2S1:
>> + exynos5_i2s_config(peripheral);
>> + break;
>> default:
>> debug("%s: invalid peripheral %d", __func__, peripheral);
>> return -1;
>> diff --git a/arch/arm/include/asm/arch-exynos/periph.h
>> b/arch/arm/include/asm/arch-exynos/periph.h
>> index dafc3f3..404e5db 100644
>> --- a/arch/arm/include/asm/arch-exynos/periph.h
>> +++ b/arch/arm/include/asm/arch-exynos/periph.h
>> @@ -38,6 +38,7 @@ enum periph_id {
>> PERIPH_ID_I2C5,
>> PERIPH_ID_I2C6,
>> PERIPH_ID_I2C7,
>> + PERIPH_ID_I2S1,
>> PERIPH_ID_SDMMC0,
>> PERIPH_ID_SDMMC1,
>> PERIPH_ID_SDMMC2,
>> --
>> 1.7.4.4
>>
>
>
>
> --
> with warm regards,
> Chander Kashyap
> ___
> U-Boot mailing list
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> http://lists.denx.de/mailman/listinfo/u-boot
Regards,
Rajeshwari Shinde.
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Re: [U-Boot] [PATCH 9/9] EXYNOS5: Enable Sound
Hi Chander, Thank you for comments. On Tue, Aug 21, 2012 at 3:22 PM, Chander Kashyap wrote: > hi Rajeshwari, > > On 14 August 2012 11:15, Rajeshwari Shinde wrote: >> This patch enables sound support for EXYNOS5 > Enable sound for exynos5 based smdk5250 not exynos5. - ok >> >> Signed-off-by: Rajeshwari Shinde >> --- >> include/configs/smdk5250.h |8 >> 1 files changed, 8 insertions(+), 0 deletions(-) >> >> diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h >> index 4b9093c..fae1c0c 100644 >> --- a/include/configs/smdk5250.h >> +++ b/include/configs/smdk5250.h >> @@ -242,6 +242,14 @@ >> #define CONFIG_ENV_SPI_MAX_HZ 5000 >> #endif >> >> +/* Sound */ >> +#define CONFIG_CMD_SOUND >> +#ifdef CONFIG_CMD_SOUND >> +#define CONFIG_SOUND >> +#define CONFIG_I2S >> +#define CONFIG_SOUND_WM8994 >> +#endif >> + >> /* Enable devicetree support */ >> #define CONFIG_OF_LIBFDT >> >> -- >> 1.7.4.4 >> > > > > -- > with warm regards, > Chander Kashyap > ___ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot Regards, Rajeshwari Shinde ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/7 V4] SPI: Add SPI Driver for EXYNOS.
Hi Joonyoung, Thank you for testing. Regards, Rajeshwari Shinde On Mon, Aug 20, 2012 at 12:15 PM, Joonyoung Shim wrote: > Hi, > > 2012/8/2 Rajeshwari Shinde : >> This patch adds SPI driver for EXYNOS. >> >> Signed-off-by: Simon Glass >> Signed-off-by: Padmavathi Venna >> Signed-off-by: Gabe Black >> Signed-off-by: Rajeshwari Shinde >> --- >> Changes in V2: >> - None. >> Changes in V3: >> - Removed SPI_SLAVE flag. >> Changes in V4: >> - Rebased on Mainline u-boot.git. >> - Removed variable bus_count and DECLARE_GLOBAL_DATA_PTR; >> - Function spi_flush_fifo made static. >> arch/arm/include/asm/arch-exynos/spi.h | 78 +++ >> drivers/spi/Makefile |1 + >> drivers/spi/exynos_spi.c | 364 >> >> 3 files changed, 443 insertions(+), 0 deletions(-) >> create mode 100644 arch/arm/include/asm/arch-exynos/spi.h >> create mode 100644 drivers/spi/exynos_spi.c >> > > I tested this driver is working at the exynos5250 > > Tested-by: jy0922.s...@samsung.com > > > -- > - Joonyoung Shim > ___ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/9] SOUND: Add I2S driver
Hi, On Sat, Aug 18, 2012 at 12:23 AM, Mike Frysinger wrote: > On Friday 17 August 2012 08:48:59 Andrew Dyer wrote: >> The code in the i2s.c file is still full of samsung soc specific stuff, so >> I think the filename is misleading. Something like samsung-i2s.c would be >> more appropriate. > > +1 Ok will do so and resend the patches. > -mike Regards, Rajeshwari Shinde. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 3/5] at91: atmel_nand: Update driver to support Programmable Multibit ECC controller
Hi, Scott On 8/22/2012 4:39 AM, Scott Wood wrote: On 08/21/2012 05:37 AM, Josh Wu wrote: Hi, Andreas On 8/17/2012 5:24 PM, Andreas Bießmann wrote: can you please add some README entry describing these new config parameters? Namely CONFIG_ATMEL_NAND_HW_PMECC, CONFIG_PMECC_CAP, CONFIG_PMECC_SECTOR_SIZE (can't this be derived from some already available NAND information?) and CONFIG_PMECC_INDEX_TABLE_OFFSET. OK, I will add a README file to explain all the parameters. this CONFIG_PMECC_SECTOR_SIZE means how many bytes to generate out PMECC code. It only can be 512 and 1024. So for a nand chip whose page size is 2048, if CONFIG_PMECC_SECTOR_SIZE is set as 512, then PMECC will generate PMECC code for each 512 bytes. I think it cannot be derived from nand information. I think I am not make me clear in previous email. let me try again :) For the PMECC hardware, it support to read/write one data page of nand in one step. The size of the data page should be multiple(max is 8) of PMECC sector. The PMECC sector can only be 512 or 1024. So the PMECC can read/write max 8192 bytes (max data page size: 8 x 1024) in one step. And generate the ecc bytes (8 x 4) for this page if the error correct capability is 2 bits. But the internal thing is those ecc bytes is split into 8 parts and each part is for corresponding sector. So this is basically nand->ecc.size? I don't think nand->ecc.size is the CONFIG_PMECC_SECTOR_SIZE. Since for my understanding, the ecc.size is the data bytes per ecc step. In my code, PMECC can read/write one page in one step. So I set nand->ecc.size to the page size. While this can't be directly read from the chip, usually there's a convention for a given type of NAND chip on a given controller. Do you really need to support both 512 and 1024 for any single chip? hmm. So maybe I can set default PMECC sector size to 512 if nand flash page is smaller than 4096 (8x512) bytes. And set it to 1024 only when nand flash page is larger than 4096. But in other side, if CONFIG_PMECC_SECTOR_SIZE is defined, then driver will use it. Why do you set nand->ecc.size to mtd->writesize if that isn't the actual ECC chunk size? As mentioned in above, the ecc.size is the data bytes per ecc step. In PMECC code, PMECC can read/write one page in one step. So I set nand->ecc.size to the page size not the actual inside ECC chunk size: CONFIG_PMECC_SECTOR_SIZE -Scott Thanks. Best Regards, Josh Wu ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/5] MX28: DMA: Prolong the DMA timeout
Load from SPI flash can create a long DMA chain, which can take long
time to transfer. Change the DMA timeout to roughly 10s to prevent
such long chains misreporting errors.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Otavio Salvador
Cc: Stefano Babic
---
drivers/dma/apbh_dma.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
index ca5a32f..37a941c 100644
--- a/drivers/dma/apbh_dma.c
+++ b/drivers/dma/apbh_dma.c
@@ -526,7 +526,7 @@ static int mxs_dma_wait_complete(uint32_t timeout, unsigned
int chan)
*/
int mxs_dma_go(int chan)
{
- uint32_t timeout = 1;
+ uint32_t timeout = 1000;
int ret;
LIST_HEAD(tmp_desc_list);
--
1.7.10.4
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[U-Boot] [PATCH 5/5] MX28: m28evk: Enable SPI DMA
Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Otavio Salvador Cc: Stefano Babic --- include/configs/m28evk.h |1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 2b16d69..4e9758f 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -245,6 +245,7 @@ #ifdef CONFIG_CMD_SPI #defineCONFIG_HARD_SPI #defineCONFIG_MXS_SPI +#defineCONFIG_MXS_SPI_DMA_ENABLE #defineCONFIG_SPI_HALF_DUPLEX #defineCONFIG_DEFAULT_SPI_BUS 2 #defineCONFIG_DEFAULT_SPI_MODE SPI_MODE_0 -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/5] MX28: m28evk: Align SSP clock speed
Align the SSP clock speed with oscilator to achieve higher transfer stability. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Otavio Salvador Cc: Stefano Babic --- board/denx/m28evk/m28evk.c |4 ++-- include/configs/m28evk.h |4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/board/denx/m28evk/m28evk.c b/board/denx/m28evk/m28evk.c index 74da3ea..255c139 100644 --- a/board/denx/m28evk/m28evk.c +++ b/board/denx/m28evk/m28evk.c @@ -49,8 +49,8 @@ int board_early_init_f(void) /* SSP0 clock at 96MHz */ mx28_set_sspclk(MXC_SSPCLK0, 96000, 0); - /* SSP2 clock at 96MHz */ - mx28_set_sspclk(MXC_SSPCLK2, 96000, 0); + /* SSP2 clock at 160MHz */ + mx28_set_sspclk(MXC_SSPCLK2, 16, 0); #ifdef CONFIG_CMD_USB mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT); diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index b3ac316..2b16d69 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -255,11 +255,11 @@ #defineCONFIG_SPI_FLASH_STMICRO #defineCONFIG_SF_DEFAULT_CS2 #defineCONFIG_SF_DEFAULT_MODE SPI_MODE_0 -#defineCONFIG_SF_DEFAULT_SPEED 2400 +#defineCONFIG_SF_DEFAULT_SPEED 4000 #defineCONFIG_ENV_SPI_CS 0 #defineCONFIG_ENV_SPI_BUS 2 -#defineCONFIG_ENV_SPI_MAX_HZ 2400 +#defineCONFIG_ENV_SPI_MAX_HZ 4000 #defineCONFIG_ENV_SPI_MODE SPI_MODE_0 #endif #endif -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/5] MX28: SPI: Supercharge the SPI driver
This change implements DMA chaining into SPI driver. This allows
the transfers to go much faster, while also fixing SF issues.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Otavio Salvador
Cc: Stefano Babic
---
drivers/spi/mxs_spi.c | 96 +
1 file changed, 65 insertions(+), 31 deletions(-)
diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
index a037c13..fef4302 100644
--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
@@ -56,7 +56,6 @@ struct mxs_spi_slave {
uint32_tmax_khz;
uint32_tmode;
struct mxs_ssp_regs *regs;
- struct mxs_dma_desc *desc;
};
static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
@@ -84,7 +83,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned
int cs,
uint32_t addr;
struct mxs_ssp_regs *ssp_regs;
int reg;
- struct mxs_dma_desc *desc;
if (!spi_cs_is_valid(bus, cs)) {
printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
@@ -95,10 +93,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned
int cs,
if (!mxs_slave)
return NULL;
- desc = mxs_dma_desc_alloc();
- if (!desc)
- goto err_desc;
-
if (mxs_dma_init_channel(bus))
goto err_init;
@@ -109,7 +103,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus,
unsigned int cs,
mxs_slave->max_khz = max_hz / 1000;
mxs_slave->mode = mode;
mxs_slave->regs = (struct mxs_ssp_regs *)addr;
- mxs_slave->desc = desc;
ssp_regs = mxs_slave->regs;
reg = readl(&ssp_regs->hw_ssp_ctrl0);
@@ -120,8 +113,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus,
unsigned int cs,
return &mxs_slave->slave;
err_init:
- mxs_dma_desc_free(desc);
-err_desc:
free(mxs_slave);
return NULL;
}
@@ -129,7 +120,6 @@ err_desc:
void spi_free_slave(struct spi_slave *slave)
{
struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
- mxs_dma_desc_free(mxs_slave->desc);
free(mxs_slave);
}
@@ -228,19 +218,24 @@ static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
char *data, int length, int write, unsigned long flags)
{
- struct mxs_dma_desc *desc = slave->desc;
+ const int xfer_max_sz = 0xff00;
+ const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1;
struct mxs_ssp_regs *ssp_regs = slave->regs;
- uint32_t ctrl0 = SSP_CTRL0_DATA_XFER;
+ struct mxs_dma_desc *dp;
+ uint32_t ctrl0;
uint32_t cache_data_count;
int dmach;
+ int tl;
+
+ ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);
+
+ memset(desc, 0, sizeof(struct mxs_dma_desc) * desc_count);
- memset(desc, 0, sizeof(struct mxs_dma_desc));
- desc->address = (dma_addr_t)desc;
+ ctrl0 = readl(&ssp_regs->hw_ssp_ctrl0);
+ ctrl0 |= SSP_CTRL0_DATA_XFER;
if (flags & SPI_XFER_BEGIN)
ctrl0 |= SSP_CTRL0_LOCK_CS;
- if (flags & SPI_XFER_END)
- ctrl0 |= SSP_CTRL0_IGNORE_CRC;
if (!write)
ctrl0 |= SSP_CTRL0_READ;
@@ -251,27 +246,66 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
else
cache_data_count = length;
- if (!write) {
- slave->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
- slave->desc->cmd.address = (dma_addr_t)data;
- } else {
- slave->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
- slave->desc->cmd.address = (dma_addr_t)data;
-
+ if (write)
/* Flush data to DRAM so DMA can pick them up */
flush_dcache_range((uint32_t)data,
(uint32_t)(data + cache_data_count));
- }
- slave->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
- (length << MXS_DMA_DESC_BYTES_OFFSET) |
- (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
- MXS_DMA_DESC_WAIT4END;
+ dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus;
- slave->desc->cmd.pio_words[0] = ctrl0;
+ dp = desc;
+ while (length) {
+ dp->address = (dma_addr_t)dp;
+ dp->cmd.address = (dma_addr_t)data;
+
+ /*
+* This is correct, even though it does indeed look insane.
+* I hereby have to, wholeheartedly, thank Freescale Inc.,
+* for always inventing insane hardware and keeping me busy
+* and employed ;-)
+*/
+ if (write)
+ dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
+ else
+ dp->cmd.data = MXS_DMA_DE
[U-Boot] [PATCH 1/5] MX28: DMA: Align the struct mxs_dma_desc
Align this structure to DMA alignment size.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Otavio Salvador
Cc: Stefano Babic
---
arch/arm/include/asm/arch-mxs/dma.h |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-mxs/dma.h
b/arch/arm/include/asm/arch-mxs/dma.h
index 4a1820b..a0a0ea5 100644
--- a/arch/arm/include/asm/arch-mxs/dma.h
+++ b/arch/arm/include/asm/arch-mxs/dma.h
@@ -27,6 +27,7 @@
#define __DMA_H__
#include
+#include
#ifndefCONFIG_ARCH_DMA_PIO_WORDS
#defineDMA_PIO_WORDS 15
@@ -109,7 +110,7 @@ struct mxs_dma_desc {
dma_addr_t address;
void*buffer;
struct list_headnode;
-};
+} __aligned(MXS_DMA_ALIGNMENT);
/**
* MXS DMA channel
--
1.7.10.4
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Re: [U-Boot] [PATCH 1/4] spiflash: at25: using common spi flash operation
Hi Andreas, On 8/21/2012 19:26, Andreas Bießmann wrote: Dear Bo Shen, On 20.08.2012 08:32, Bo Shen wrote: Using common spi flash operation function to replace private operation funtion This patch is based on http://patchwork.ozlabs.org/patch/177896/ which has been merged by Mike frysinger Mike, do you think this is a fix? Should it go into 2012.10? Will you take it? Signed-off-by: Bo Shen --- drivers/mtd/spi/atmel.c | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi/atmel.c b/drivers/mtd/spi/atmel.c index 89ebe9d..006f6d5 100644 --- a/drivers/mtd/spi/atmel.c +++ b/drivers/mtd/spi/atmel.c @@ -518,13 +518,19 @@ struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode) asf->flash.erase = dataflash_erase_p2; } + asf->flash.page_size = page_size; + asf->flash.sector_size = page_size; break; case DF_FAMILY_AT26F: case DF_FAMILY_AT26DF: asf->flash.read = spi_flash_cmd_read_fast; - asf->flash.write = dataflash_write_p2; - asf->flash.erase = dataflash_erase_p2; + asf->flash.write = spi_flash_cmd_write_multi; + asf->flash.erase = spi_flash_cmd_erase; + asf->flash.page_size = page_size; + asf->flash.sector_size = 4096; why do you take fixed value for sector size here? The fixed number fit for both AT25 and AT26 serials. So, I take it. Actually, we can calculate it as: asf->flash.sector_size = page_size * params->pages_per_block * params->blocks_per_sector So, may I need to change it? + /* clear SPRL# bit for locked flash */ + spi_flash_cmd_write_status(&asf->flash, 0); break; default: @@ -532,7 +538,6 @@ struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode) goto err; } - asf->flash.sector_size = page_size; asf->flash.size = page_size * params->pages_per_block * params->blocks_per_sector * params->nr_sectors; And here you correlate number of sectors with page size ... but we may have page_size != sector_size for some at26 devices, aren't we? This is from old driver and this line is moved away. For at26 devices, it is used the fixed number 4096 for sector size. Please take following as a reference. - case DF_FAMILY_AT26F: case DF_FAMILY_AT26DF: asf->flash.read = spi_flash_cmd_read_fast; - asf->flash.write = dataflash_write_p2; - asf->flash.erase = dataflash_erase_p2; + asf->flash.write = spi_flash_cmd_write_multi; + asf->flash.erase = spi_flash_cmd_erase; + asf->flash.page_size = page_size; + asf->flash.sector_size = 4096; - Best regards Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] rmobile: Add README
From: Nobuhiro Iwamatsu This add README of Renesas RMOBILE. Based doc/README.omap3. Signed-off-by: Nobuhiro Iwamatsu --- V2: Added more compiler infomation. doc/README.rmobile | 65 1 file changed, 65 insertions(+) create mode 100644 doc/README.rmobile diff --git a/doc/README.rmobile b/doc/README.rmobile new file mode 100644 index 000..7ec63f1 --- /dev/null +++ b/doc/README.rmobile @@ -0,0 +1,65 @@ +Summary +=== + +This README is about U-Boot support for Renesas's ARM Cortex-A9 based RMOBILE[1] +family of SoCs. Renesas's RMOBILE SoC family contains an ARM Cortex-A9. + +Currently the following boards are supported: + +* KMC KZM-A9-GT [2] + +* Atmark-Techno Armadillo-800-EVA [3] + +Toolchain += + +ARM Cortex-A9 support ARM v7 instruction set (-march=armv7a). +But currently we compile with -march=armv5 to allow more compilers to work. +(For U-Boot code this has no performance impact.) +Because there was no compiler which is supporting armv7a not much before. +Currently, ELDK[4], Linaro[5], CodeSourcey[6] and Emdebian[7] supports -march=armv7a +and you can get. + +Build += + +* KZM-A9-GT + +make kzm9g_config +make + +* Armadillo-800-EVA + +make armadillo-800eva_config +make + +Links += + +[1] Renesas RMOBILE: + +http://am.renesas.com/products/soc/assp/mobile/r_mobile/index.jsp + +[2] KZM-A9-GT + +http://www.kmckk.co.jp/kzma9-gt/index.html + +[3] Armadillo-800-EVA + +http://armadillo.atmark-techno.com/armadillo-800-EVA + +[4] ELDK + +http://www.denx.de/wiki/view/ELDK-5/WebHome#Section_1.6. + +[5] Linaro + +http://www.linaro.org/downloads/ + +[6] CodeSourcey + +http://www.mentor.com/embedded-software/codesourcery + +[7] Emdebian + +http://www.emdebian.org/crosstools.html -- 1.7.10 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6] arm: rmobile: Add support Renesas SH73A0
Renesas SH73A0 is CPU with Cortex-A9.
This supports the basic register definition and GPIO.
Signed-off-by: Nobuhiro Iwamatsu
Signed-off-by: Nobuhiro Iwamatsu
---
V6: Changed Makefile that using config.
Removed unnecessary ifdefs.
V5: Remove dead code.
V4: Revert ICCICR.
V3: Set COBJS one object per line, and sort the list.
Remove ICCICR and ICCPMR.
Remove white space.
v2: Remove white space.
Code which can be communalized was moved to lowlevel_init.
arch/arm/cpu/armv7/rmobile/Makefile | 14 +-
arch/arm/cpu/armv7/rmobile/board.c | 31 ++
arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c| 48 ++
arch/arm/cpu/armv7/rmobile/cpu_info.c | 36 +-
arch/arm/cpu/armv7/rmobile/lowlevel_init.S | 95
arch/arm/include/asm/arch-rmobile/rmobile.h |4 +
arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h | 553 +++
arch/arm/include/asm/arch-rmobile/sh73a0.h | 281
arch/arm/include/asm/arch-rmobile/sys_proto.h | 29 ++
9 files changed, 1067 insertions(+), 24 deletions(-)
create mode 100644 arch/arm/cpu/armv7/rmobile/board.c
create mode 100644 arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c
create mode 100644 arch/arm/cpu/armv7/rmobile/lowlevel_init.S
create mode 100644 arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h
create mode 100644 arch/arm/include/asm/arch-rmobile/sh73a0.h
create mode 100644 arch/arm/include/asm/arch-rmobile/sys_proto.h
diff --git a/arch/arm/cpu/armv7/rmobile/Makefile
b/arch/arm/cpu/armv7/rmobile/Makefile
index e7eb90f..77eca4b 100644
--- a/arch/arm/cpu/armv7/rmobile/Makefile
+++ b/arch/arm/cpu/armv7/rmobile/Makefile
@@ -25,11 +25,17 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).o
-COBJS += cpu_info.o
-COBJS += timer.o
+SOBJS = lowlevel_init.o
+COBJS-y += cpu_info.o
+COBJS-y += timer.o
-SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y))
+COBJS-$(CONFIG_DISPLAY_BOARDINFO) += board.o
+COBJS-$(CONFIG_SH73A0) += cpu_info-sh73a0.o
+
+COBJS := $(COBJS-y)
+SRCS:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
START := $(addprefix $(obj),$(START))
all: $(obj).depend $(LIB)
diff --git a/arch/arm/cpu/armv7/rmobile/board.c
b/arch/arm/cpu/armv7/rmobile/board.c
new file mode 100644
index 000..2622590
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/board.c
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include
+#include
+#include
+
+int checkboard(void)
+{
+ printf("Board: %s\n", sysinfo.board_string);
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c
b/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c
new file mode 100644
index 000..3086dd8
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include
+#include
+
+u32 rmobile_get_cpu_type(void)
+{
+ u32 id;
+ u32 type;
+ struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
+
+ id = readl(hpb->cccr);
+ type = (id >> 8) & 0xFF;
+
+ return type;
+}
+
+u32 get_cpu_rev(void)
+{
+ u32 id;
+ u32 rev;
+
[U-Boot] [PATCH v3] arm: rmobile: Add support TMU base timer function
Some rmobile SoC has TMU base timer function. This supports TMU.
Signed-off-by: Nobuhiro Iwamatsu
Signed-off-by: Nobuhiro Iwamatsu
---
V3: Merged arch/sh/lib/time.c
Need patches
* sh: tmu: Removed arch/sh/include/asm/clk.h
* sh: tmu: Changed switch statement to shift operation
* sh: tmu: Changed TMU driver using array of structures
V2: Set COBJS one object per line, and sort the list.
arch/arm/cpu/armv7/rmobile/Makefile |3 ++-
include/sh_tmu.h|2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/rmobile/Makefile
b/arch/arm/cpu/armv7/rmobile/Makefile
index a522872..dd0aede 100644
--- a/arch/arm/cpu/armv7/rmobile/Makefile
+++ b/arch/arm/cpu/armv7/rmobile/Makefile
@@ -27,11 +27,12 @@ LIB = $(obj)lib$(SOC).o
SOBJS = lowlevel_init.o
COBJS-y += cpu_info.o
-COBJS-y += timer.o
COBJS-$(CONFIG_DISPLAY_BOARDINFO) += board.o
+COBJS-$(CONFIG_GLOBAL_TIMER) += timer.o
COBJS-$(CONFIG_SH73A0) += cpu_info-sh73a0.o
COBJS-$(CONFIG_SH73A0) += pfc-sh73a0.o
+COBJS-$(CONFIG_TMU_TIMER) += $(TOPDIR)/arch/sh/lib/time.o
COBJS := $(COBJS-y)
SRCS:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/include/sh_tmu.h b/include/sh_tmu.h
index a55d141..96c589d 100644
--- a/include/sh_tmu.h
+++ b/include/sh_tmu.h
@@ -47,7 +47,7 @@ struct tmu_regs {
};
#endif /* CONFIG_SH3 */
-#if defined(CONFIG_SH4) || defined(CONFIG_SH4A)
+#if defined(CONFIG_SH4) || defined(CONFIG_SH4A) || defined(CONFIG_RMOBILE)
struct tmu_regs {
u32 reserved;
u8 tstr;
--
1.7.10
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Re: [U-Boot] [PATCH v2] integrator: break out common config
On Sat, Aug 4, 2012 at 5:21 PM, Linus Walleij wrote: > The configuration that is common for all Integrator boards may > just as well be stored in a common include file as per pattern > from other boards. This eases maintenance quite a bit. > > Signed-off-by: Linus Walleij > --- > ChangeLog v1->v2: > - Rebase to latest U-Boot master as requested by Albert ARIBAUD > in message 20120729112319.5581b420@lilith Ping on this! Yours, Linus Walleij ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 13/13] mxc nand: Add support for i.MX5
On 08/21/2012 04:04 PM, Benoît Thébaudeau wrote: > diff --git u-boot-imx-88e73dd.orig/nand_spl/nand_boot_fsl_nfc.c > u-boot-imx-88e73dd/nand_spl/nand_boot_fsl_nfc.c > index a40c998..1096727 100644 > --- u-boot-imx-88e73dd.orig/nand_spl/nand_boot_fsl_nfc.c > +++ u-boot-imx-88e73dd/nand_spl/nand_boot_fsl_nfc.c > @@ -30,64 +30,117 @@ > #include > #include > > +#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) > static struct fsl_nfc_regs *const nfc = (void *)NFC_BASE_ADDR; > +#elif defined(MXC_NFC_V3_2) > +static struct fsl_nfc_regs *const nfc = (void *)NFC_BASE_ADDR_AXI; > +static struct fsl_nfc_ip_regs *const nfc_ip = (void *)NFC_BASE_ADDR; > +#endif Please migrate to the new SPL. > + tmp = (readnfc(&nfc_ip->config2) & ~(NFC_V3_CONFIG2_SPAS_MASK | > + NFC_V3_CONFIG2_EDC_MASK | NFC_V3_CONFIG2_PS_MASK)) | > + NFC_V3_CONFIG2_SPAS(CONFIG_SYS_NAND_SPARE_SIZE / 2) | > + NFC_V3_CONFIG2_INT_MSK | NFC_V3_CONFIG2_ECC_EN | > + NFC_V3_CONFIG2_ONE_CYCLE; CONFIG_SYS_NAND_SPARE_SIZE needs to go in the README. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 2/2] mx35 timer: Switch to 32-kHz source
Switch the mx35 timer driver to the 32-kHz clock source to avoid calling
mxc_get_clock() again and again, and to be consistent with the timer drivers of
other i.MX SoCs.
Signed-off-by: Benoît Thébaudeau
Cc: Stefano Babic
---
Changes for v2:
- Fix multiline comment style.
- Use default SoC input clock frequency definitions instead of duplicating
frequency definitions in all board files.
.../arch/arm/cpu/arm1136/mx35/timer.c | 44
1 file changed, 27 insertions(+), 17 deletions(-)
diff --git u-boot-imx-88e73dd.orig/arch/arm/cpu/arm1136/mx35/timer.c
u-boot-imx-88e73dd/arch/arm/cpu/arm1136/mx35/timer.c
index 642..9680b7f 100644
--- u-boot-imx-88e73dd.orig/arch/arm/cpu/arm1136/mx35/timer.c
+++ u-boot-imx-88e73dd/arch/arm/cpu/arm1136/mx35/timer.c
@@ -27,6 +27,7 @@
#include
#include
#include
+#include
#include
DECLARE_GLOBAL_DATA_PTR;
@@ -37,43 +38,52 @@ DECLARE_GLOBAL_DATA_PTR;
/* General purpose timers bitfields */
#define GPTCR_SWR (1<<15)/* Software reset */
#define GPTCR_FRR (1<<9) /* Freerun / restart */
-#define GPTCR_CLKSOURCE_32 (0x100<<6)/* Clock source */
-#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */
+#define GPTCR_CLKSOURCE_32 (4<<6)/* Clock source */
#define GPTCR_TEN (1)/* Timer enable */
-#defineTIMER_FREQ_HZ mxc_get_clock(MXC_IPG_CLK)
-
+/*
+ * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
+ * "tick" is internal timer period
+ */
+/* ~0.4% error - measured with stop-watch on 100s boot-delay */
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
- do_div(tick, TIMER_FREQ_HZ);
+ do_div(tick, MXC_CLK32);
return tick;
}
-static inline unsigned long long us_to_tick(unsigned long long usec)
+static inline unsigned long long us_to_tick(unsigned long long us)
{
- usec *= TIMER_FREQ_HZ;
- do_div(usec, 100);
+ us = us * MXC_CLK32 + 99;
+ do_div(us, 100);
- return usec;
+ return us;
}
+/*
+ * nothing really to do with interrupts, just starts up a counter.
+ * The 32KHz 32-bit timer overruns in 134217 seconds
+ */
int timer_init(void)
{
int i;
struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
+ struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR;
/* setup GP Timer 1 */
writel(GPTCR_SWR, &gpt->ctrl);
- for (i = 0; i < 100; i++)
- writel(0, &gpt->ctrl); /* We have no udelay by now */
- writel(0, &gpt->pre);
- /* Freerun Mode, PERCLK1 input */
- writel(readl(&gpt->ctrl) |
- GPTCR_CLKSOURCE_IPG | GPTCR_TEN,
- &gpt->ctrl);
+ writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1);
+
+ for (i = 0; i < 100; i++)
+ writel(0, &gpt->ctrl); /* We have no udelay by now */
+ writel(0, &gpt->pre); /* prescaler = 1 */
+ /* Freerun Mode, 32KHz input */
+ writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
+ &gpt->ctrl);
+ writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl);
return 0;
}
@@ -132,5 +142,5 @@ void __udelay(unsigned long usec)
*/
ulong get_tbclk(void)
{
- return TIMER_FREQ_HZ;
+ return MXC_CLK32;
}
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[U-Boot] [PATCH v2 1/2] mx35: Define default SoC input clock frequencies
Define default SoC input clock frequencies for i.MX35 in order to get rid of
duplicated definitions.
Signed-off-by: Benoît Thébaudeau
Cc: Stefano Babic
---
This patch depends on http://patchwork.ozlabs.org/patch/177437/ .
Changes for v2:
- New patch.
.../arch/arm/cpu/arm1136/mx35/generic.c| 43
.../arch/arm/cpu/arm1136/mx35/timer.c |2 +-
.../arch/arm/include/asm/arch-mx35/clock.h | 14 +++
.../include/configs/flea3.h|1 -
.../include/configs/mx35pdk.h |1 -
5 files changed, 31 insertions(+), 30 deletions(-)
diff --git u-boot-imx-88e73dd.orig/arch/arm/cpu/arm1136/mx35/generic.c
u-boot-imx-88e73dd/arch/arm/cpu/arm1136/mx35/generic.c
index 8f61069..04c8341 100644
--- u-boot-imx-88e73dd.orig/arch/arm/cpu/arm1136/mx35/generic.c
+++ u-boot-imx-88e73dd/arch/arm/cpu/arm1136/mx35/generic.c
@@ -149,9 +149,7 @@ static u32 get_mcu_main_clk(void)
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
- fi *=
- decode_pll(readl(&ccm->mpctl),
- CONFIG_MX35_HCLK_FREQ);
+ fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK);
return fi / (arm_div * fd);
}
@@ -193,12 +191,10 @@ u32 imx_get_uartclk(void)
(struct ccm_regs *)IMX_CCM_BASE;
u32 pdr4 = readl(&ccm->pdr4);
- if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) {
+ if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U)
freq = get_mcu_main_clk();
- } else {
- freq = decode_pll(readl(&ccm->ppctl),
- CONFIG_MX35_HCLK_FREQ);
- }
+ else
+ freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
freq /= CCM_GET_DIVIDER(pdr4,
MXC_CCM_PDR4_UART_PODF_MASK,
MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;
@@ -253,12 +249,10 @@ unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
break;
case USB_CLK:
usb_podf = (reg4 >> 22) & 0x3F;
- if (reg4 & 0x200) {
+ if (reg4 & 0x200)
pll = get_mcu_main_clk();
- } else {
- pll = decode_pll(readl(&ccm->ppctl),
- CONFIG_MX35_HCLK_FREQ);
- }
+ else
+ pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
ret_val = pll / (usb_podf + 1);
break;
@@ -285,15 +279,14 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
clk_sel = mpdr3 & (1 << 14);
pdf = (mpdr4 >> 10) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
- decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
- (pdf + 1);
+ decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
break;
case SSI1_BAUD:
pre_pdf = (mpdr2 >> 24) & 0x7;
pdf = mpdr2 & 0x3F;
clk_sel = mpdr2 & (1 << 6);
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
- decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
+ decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
((pre_pdf + 1) * (pdf + 1));
break;
case SSI2_BAUD:
@@ -301,15 +294,14 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
pdf = (mpdr2 >> 8) & 0x3F;
clk_sel = mpdr2 & (1 << 6);
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
- decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
+ decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
((pre_pdf + 1) * (pdf + 1));
break;
case CSI_BAUD:
clk_sel = mpdr2 & (1 << 7);
pdf = (mpdr2 >> 16) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
- decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
- (pdf + 1);
+ decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
break;
case MSHC_CLK:
pre_pdf = readl(&ccm->pdr1);
@@ -317,36 +309,33 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
pdf = (pre_pdf >> 22) & 0x3F;
pre_pdf = (pre_pdf >> 28) & 0x7;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
- decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
+ decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
((pre_pdf + 1) * (pdf + 1));
break;
case ESDHC1_CLK:
[U-Boot] [PATCH] mx31: Define default SoC input clock frequencies
Define default SoC input clock frequencies for i.MX31 in order to get rid of
duplicated definitions.
Signed-off-by: Benoît Thébaudeau
Cc: Stefano Babic
Cc: Fabio Estevam
Cc: Wolfgang Denk
Cc: Helmut Raiger
---
.../arch/arm/cpu/arm1136/mx31/generic.c|4 ++--
.../arch/arm/cpu/arm1136/mx31/timer.c | 16
.../arch/arm/include/asm/arch-mx31/clock.h | 14 ++
.../include/configs/imx31_litekit.h|1 -
.../include/configs/imx31_phycore.h|1 -
.../include/configs/mx31ads.h |2 --
.../include/configs/mx31pdk.h |2 --
.../include/configs/qong.h |2 --
.../include/configs/tt01.h |2 --
9 files changed, 24 insertions(+), 20 deletions(-)
diff --git u-boot-imx-88e73dd.orig/arch/arm/cpu/arm1136/mx31/generic.c
u-boot-imx-88e73dd/arch/arm/cpu/arm1136/mx31/generic.c
index 8873fb7..7b53437 100644
--- u-boot-imx-88e73dd.orig/arch/arm/cpu/arm1136/mx31/generic.c
+++ u-boot-imx-88e73dd/arch/arm/cpu/arm1136/mx31/generic.c
@@ -47,9 +47,9 @@ static u32 mx31_get_mpl_dpdgck_clk(void)
u32 infreq;
if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
- infreq = CONFIG_MX31_CLK32 * 1024;
+ infreq = MXC_CLK32 * 1024;
else
- infreq = CONFIG_MX31_HCLK_FREQ;
+ infreq = MXC_HCLK;
return mx31_decode_pll(readl(CCM_MPCTL), infreq);
}
diff --git u-boot-imx-88e73dd.orig/arch/arm/cpu/arm1136/mx31/timer.c
u-boot-imx-88e73dd/arch/arm/cpu/arm1136/mx31/timer.c
index 72081a8..36266da 100644
--- u-boot-imx-88e73dd.orig/arch/arm/cpu/arm1136/mx31/timer.c
+++ u-boot-imx-88e73dd/arch/arm/cpu/arm1136/mx31/timer.c
@@ -23,6 +23,7 @@
#include
#include
+#include
#include
#include
#include
@@ -53,28 +54,27 @@ DECLARE_GLOBAL_DATA_PTR;
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
- do_div(tick, CONFIG_MX31_CLK32);
+ do_div(tick, MXC_CLK32);
return tick;
}
static inline unsigned long long time_to_tick(unsigned long long time)
{
- time *= CONFIG_MX31_CLK32;
+ time *= MXC_CLK32;
do_div(time, CONFIG_SYS_HZ);
return time;
}
static inline unsigned long long us_to_tick(unsigned long long us)
{
- us = us * CONFIG_MX31_CLK32 + 99;
+ us = us * MXC_CLK32 + 99;
do_div(us, 100);
return us;
}
#else
/* ~2% error */
-#define TICK_PER_TIME ((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) \
- / CONFIG_SYS_HZ)
-#define US_PER_TICK(100 / CONFIG_MX31_CLK32)
+#define TICK_PER_TIME ((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
+#define US_PER_TICK(100 / MXC_CLK32)
static inline unsigned long long tick_to_time(unsigned long long tick)
{
@@ -128,7 +128,7 @@ ulong get_timer_masked(void)
{
/*
* get_ticks() returns a long long (64 bit), it wraps in
-* 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+* 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
* 5 * 10^6 days - long enough.
*/
@@ -159,7 +159,7 @@ void __udelay(unsigned long usec)
*/
ulong get_tbclk(void)
{
- return CONFIG_MX31_CLK32;
+ return MXC_CLK32;
}
void reset_cpu(ulong addr)
diff --git u-boot-imx-88e73dd.orig/arch/arm/include/asm/arch-mx31/clock.h
u-boot-imx-88e73dd/arch/arm/include/asm/arch-mx31/clock.h
index 852c19c..9468b45 100644
--- u-boot-imx-88e73dd.orig/arch/arm/include/asm/arch-mx31/clock.h
+++ u-boot-imx-88e73dd/arch/arm/include/asm/arch-mx31/clock.h
@@ -24,6 +24,20 @@
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H
+#include
+
+#ifdef CONFIG_MX31_HCLK_FREQ
+#define MXC_HCLK CONFIG_MX31_HCLK_FREQ
+#else
+#define MXC_HCLK 2600
+#endif
+
+#ifdef CONFIG_MX31_CLK32
+#define MXC_CLK32 CONFIG_MX31_CLK32
+#else
+#define MXC_CLK32 32768
+#endif
+
enum mxc_clock {
MXC_ARM_CLK,
MXC_IPG_CLK,
diff --git u-boot-imx-88e73dd.orig/include/configs/imx31_litekit.h
u-boot-imx-88e73dd/include/configs/imx31_litekit.h
index a340e97..4af6c4b 100644
--- u-boot-imx-88e73dd.orig/include/configs/imx31_litekit.h
+++ u-boot-imx-88e73dd/include/configs/imx31_litekit.h
@@ -33,7 +33,6 @@
/* High Level Configuration Options */
#define CONFIG_ARM1136 1/* This is an arm1136 CPU core */
#define CONFIG_MX311/* in a mx31 */
-#define CONFIG_MX31_HCLK_FREQ 2600
#define CONFIG_MX31_CLK32 32000
#define CONFIG_DISPLAY_CPUINFO
diff --git u-boot-imx-88e73dd.orig/include/configs/imx31_phycore.h
u-boot-imx-88e73dd/include/configs/imx31_phycore.h
index a412cf6..bf763f6 100644
--- u-boot-imx-88e73dd.orig/include/configs/imx31_phycore.h
+++ u-boot-imx-88e73d
[U-Boot] [PATCH] mx25: Define default SoC input clock frequencies
Define default SoC input clock frequencies for i.MX25 in order to get rid of
duplicated definitions.
Signed-off-by: Benoît Thébaudeau
Cc: Stefano Babic
Cc: Fabio Estevam
Cc: Matthias Weisser
---
.../arch/arm/cpu/arm926ejs/mx25/generic.c |2 +-
.../arch/arm/cpu/arm926ejs/mx25/timer.c| 16
.../arch/arm/include/asm/arch-mx25/clock.h | 14 ++
.../include/configs/mx25pdk.h |1 -
.../include/configs/zmx25.h|1 -
5 files changed, 23 insertions(+), 11 deletions(-)
diff --git u-boot-imx-88e73dd.orig/arch/arm/cpu/arm926ejs/mx25/generic.c
u-boot-imx-88e73dd/arch/arm/cpu/arm926ejs/mx25/generic.c
index a412a8f..90e584a 100644
--- u-boot-imx-88e73dd.orig/arch/arm/cpu/arm926ejs/mx25/generic.c
+++ u-boot-imx-88e73dd/arch/arm/cpu/arm926ejs/mx25/generic.c
@@ -64,7 +64,7 @@ static unsigned int imx_decode_pll(unsigned int pll, unsigned
int f_ref)
static ulong imx_get_mpllclk(void)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
- ulong fref = 2400;
+ ulong fref = MXC_HCLK;
return imx_decode_pll(readl(&ccm->mpctl), fref);
}
diff --git u-boot-imx-88e73dd.orig/arch/arm/cpu/arm926ejs/mx25/timer.c
u-boot-imx-88e73dd/arch/arm/cpu/arm926ejs/mx25/timer.c
index 1cfd02b..4dc4041 100644
--- u-boot-imx-88e73dd.orig/arch/arm/cpu/arm926ejs/mx25/timer.c
+++ u-boot-imx-88e73dd/arch/arm/cpu/arm926ejs/mx25/timer.c
@@ -40,6 +40,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -55,28 +56,27 @@ DECLARE_GLOBAL_DATA_PTR;
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
- do_div(tick, CONFIG_MX25_CLK32);
+ do_div(tick, MXC_CLK32);
return tick;
}
static inline unsigned long long time_to_tick(unsigned long long time)
{
- time *= CONFIG_MX25_CLK32;
+ time *= MXC_CLK32;
do_div(time, CONFIG_SYS_HZ);
return time;
}
static inline unsigned long long us_to_tick(unsigned long long us)
{
- us = us * CONFIG_MX25_CLK32 + 99;
+ us = us * MXC_CLK32 + 99;
do_div(us, 100);
return us;
}
#else
/* ~2% error */
-#define TICK_PER_TIME ((CONFIG_MX25_CLK32 + CONFIG_SYS_HZ / 2) / \
- CONFIG_SYS_HZ)
-#define US_PER_TICK(100 / CONFIG_MX25_CLK32)
+#define TICK_PER_TIME ((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
+#define US_PER_TICK(100 / MXC_CLK32)
static inline unsigned long long tick_to_time(unsigned long long tick)
{
@@ -144,7 +144,7 @@ ulong get_timer_masked(void)
{
/*
* get_ticks() returns a long long (64 bit), it wraps in
-* 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+* 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
* 5 * 10^6 days - long enough.
*/
@@ -177,6 +177,6 @@ ulong get_tbclk(void)
{
ulong tbclk;
- tbclk = CONFIG_MX25_CLK32;
+ tbclk = MXC_CLK32;
return tbclk;
}
diff --git u-boot-imx-88e73dd.orig/arch/arm/include/asm/arch-mx25/clock.h
u-boot-imx-88e73dd/arch/arm/include/asm/arch-mx25/clock.h
index 0f47eaf..a313b80 100644
--- u-boot-imx-88e73dd.orig/arch/arm/include/asm/arch-mx25/clock.h
+++ u-boot-imx-88e73dd/arch/arm/include/asm/arch-mx25/clock.h
@@ -26,6 +26,20 @@
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H
+#include
+
+#ifdef CONFIG_MX25_HCLK_FREQ
+#define MXC_HCLK CONFIG_MX25_HCLK_FREQ
+#else
+#define MXC_HCLK 2400
+#endif
+
+#ifdef CONFIG_MX25_CLK32
+#define MXC_CLK32 CONFIG_MX25_CLK32
+#else
+#define MXC_CLK32 32768
+#endif
+
enum mxc_clock {
MXC_CSI_CLK,
MXC_EPIT_CLK,
diff --git u-boot-imx-88e73dd.orig/include/configs/mx25pdk.h
u-boot-imx-88e73dd/include/configs/mx25pdk.h
index efca287..21fc96b 100644
--- u-boot-imx-88e73dd.orig/include/configs/mx25pdk.h
+++ u-boot-imx-88e73dd/include/configs/mx25pdk.h
@@ -17,7 +17,6 @@
/* High Level Configuration Options */
-#define CONFIG_MX25_CLK32 32768 /* OSC32K frequency */
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_TEXT_BASE 0x8120
diff --git u-boot-imx-88e73dd.orig/include/configs/zmx25.h
u-boot-imx-88e73dd/include/configs/zmx25.h
index c9f737d..56060f1 100644
--- u-boot-imx-88e73dd.orig/include/configs/zmx25.h
+++ u-boot-imx-88e73dd/include/configs/zmx25.h
@@ -28,7 +28,6 @@
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_MX25
-#define CONFIG_MX25_CLK32 32768 /* OSC32K frequency */
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_TEXT_BASE 0xA000
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 13/13] mxc nand: Add support for i.MX5
Signed-off-by: Benoît Thébaudeau
Cc: Scott Wood
Cc: Stefano Babic
---
Changes for v2:
- Fix warning for unused tmp variable in board_nand_init() for NFC V1.
.../arch/arm/include/asm/arch-mx5/imx-regs.h |9 +
.../drivers/mtd/nand/mxc_nand.c| 219 +++-
.../include/fsl_nfc.h | 149 -
.../nand_spl/nand_boot_fsl_nfc.c | 114 +++---
4 files changed, 365 insertions(+), 126 deletions(-)
diff --git u-boot-imx-88e73dd.orig/arch/arm/include/asm/arch-mx5/imx-regs.h
u-boot-imx-88e73dd/arch/arm/include/asm/arch-mx5/imx-regs.h
index c53465f..ca73dea 100644
--- u-boot-imx-88e73dd.orig/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ u-boot-imx-88e73dd/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -232,6 +232,15 @@
#define CS0_32M_CS1_32M_CS2_32M_CS3_32M3
/*
+ * SRC register definitions
+ */
+#if defined(CONFIG_MX51)
+#define SRC_SBMR_NF16B (1 << 2)
+#elif defined(CONFIG_MX53)
+#define SRC_SBMR_NF16B (1 << 13)
+#endif
+
+/*
* CSPI register definitions
*/
#define MXC_ECSPI
diff --git u-boot-imx-88e73dd.orig/drivers/mtd/nand/mxc_nand.c
u-boot-imx-88e73dd/drivers/mtd/nand/mxc_nand.c
index cf2a7b0..cead757 100644
--- u-boot-imx-88e73dd.orig/drivers/mtd/nand/mxc_nand.c
+++ u-boot-imx-88e73dd/drivers/mtd/nand/mxc_nand.c
@@ -22,7 +22,8 @@
#include
#include
#include
-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35)
+#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \
+ defined(CONFIG_MX51) || defined(CONFIG_MX53)
#include
#endif
#include
@@ -36,6 +37,9 @@ struct mxc_nand_host {
struct nand_chip*nand;
struct fsl_nfc_regs __iomem *regs;
+#ifdef MXC_NFC_V3_2
+ struct fsl_nfc_ip_regs __iomem *ip_regs;
+#endif
int spare_only;
int status_request;
int pagesize_2k;
@@ -77,7 +81,7 @@ static struct nand_ecclayout nand_hw_eccoob2k = {
.oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} },
};
#endif
-#elif defined(MXC_NFC_V2_1)
+#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
#ifndef CONFIG_SYS_NAND_LARGEPAGE
static struct nand_ecclayout nand_hw_eccoob = {
.eccbytes = 9,
@@ -130,6 +134,16 @@ static int is_16bit_nand(void)
else
return 0;
}
+#elif defined(CONFIG_MX51) || defined(CONFIG_MX53)
+static int is_16bit_nand(void)
+{
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+
+ if (readl(&src->sbmr) & SRC_SBMR_NF16B)
+ return 1;
+ else
+ return 0;
+}
#else
#warning "8/16 bit NAND autodetection not supported"
static int is_16bit_nand(void)
@@ -150,7 +164,7 @@ static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t
*source, size_t size
/*
* This function polls the NANDFC to wait for the basic operation to
- * complete by checking the INT bit of config2 register.
+ * complete by checking the INT bit.
*/
static void wait_op_done(struct mxc_nand_host *host, int max_retries,
uint16_t param)
@@ -158,10 +172,17 @@ static void wait_op_done(struct mxc_nand_host *host, int
max_retries,
uint32_t tmp;
while (max_retries-- > 0) {
- if (readw(&host->regs->config2) & NFC_INT) {
- tmp = readw(&host->regs->config2);
- tmp &= ~NFC_INT;
- writew(tmp, &host->regs->config2);
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
+ tmp = readnfc(&host->regs->config2);
+ if (tmp & NFC_V1_V2_CONFIG2_INT) {
+ tmp &= ~NFC_V1_V2_CONFIG2_INT;
+ writenfc(tmp, &host->regs->config2);
+#elif defined(MXC_NFC_V3_2)
+ tmp = readnfc(&host->ip_regs->ipc);
+ if (tmp & NFC_V3_IPC_INT) {
+ tmp &= ~NFC_V3_IPC_INT;
+ writenfc(tmp, &host->ip_regs->ipc);
+#endif
break;
}
udelay(1);
@@ -180,8 +201,8 @@ static void send_cmd(struct mxc_nand_host *host, uint16_t
cmd)
{
MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
- writew(cmd, &host->regs->flash_cmd);
- writew(NFC_CMD, &host->regs->config2);
+ writenfc(cmd, &host->regs->flash_cmd);
+ writenfc(NFC_CMD, &host->regs->operation);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, cmd);
@@ -196,8 +217,8 @@ static void send_addr(struct mxc_nand_host *host, uint16_t
addr)
{
MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
- writew(addr, &host->regs->flash_addr);
- writew(NFC_ADDR, &host->regs->config2);
+ writenfc(addr, &host->regs->flash_addr);
+ writenfc(NFC_ADDR, &host->regs->operation);
/* Wait f
Re: [U-Boot] [PATCH 1/2] pxa: Add some stuff to examine cpu model and rev
Dear Łukasz Dałek, > Signed-off-by: Łukasz Dałek > --- > arch/arm/cpu/pxa/cpuinfo.c | 11 +-- > arch/arm/include/asm/arch-pxa/pxa.h | 13 + > 2 files changed, 22 insertions(+), 2 deletions(-) Acked-by: Marek Vasut I'll push this through the PXA tree. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch v3 1/2] net: introduce transparent driver private in ueth_data
Dear Lucas Stach,
> Avoid clutter in ueth_data. Individual drivers should not mess
> with structures belonging to the core like this.
>
> Signed-off-by: Lucas Stach
> ---
> drivers/usb/eth/smsc95xx.c | 48
> -- include/usb_ether.h
> | 8 ++--
> 2 Dateien geändert, 36 Zeilen hinzugefügt(+), 20 Zeilen entfernt(-)
You might want to configure your locale ... otherwise, awesome :)
> diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c
> index c62a8c1..4bf2a16 100644
> --- a/drivers/usb/eth/smsc95xx.c
> +++ b/drivers/usb/eth/smsc95xx.c
> @@ -25,6 +25,7 @@
> #include
> #include
> #include "usb_ether.h"
> +#include "malloc.h"
>
> /* SMSC LAN95xx based USB 2.0 Ethernet Devices */
>
> @@ -146,6 +147,12 @@
> /* local vars */
> static int curr_eth_dev; /* index for name of next device detected */
>
> +/* driver private */
> +struct smsc95xx_private {
> + size_t rx_urb_size; /* maximum USB URB size */
> + u32 mac_cr; /* MAC control register value */
> + int have_hwaddr; /* 1 if we have a hardware MAC address */
> +};
>
> /*
> * Smsc95xx infrastructure commands
> @@ -377,6 +384,7 @@ static int smsc95xx_init_mac_address(struct eth_device
> *eth, static int smsc95xx_write_hwaddr(struct eth_device *eth)
> {
> struct ueth_data *dev = (struct ueth_data *)eth->priv;
> + struct smsc95xx_private *priv = dev->dev_priv;
> u32 addr_lo = __get_unaligned_le32(ð->enetaddr[0]);
> u32 addr_hi = __get_unaligned_le16(ð->enetaddr[4]);
> int ret;
> @@ -392,7 +400,7 @@ static int smsc95xx_write_hwaddr(struct eth_device
> *eth) return ret;
>
> debug("MAC %pM\n", eth->enetaddr);
> - dev->have_hwaddr = 1;
> + priv->have_hwaddr = 1;
> return 0;
> }
>
> @@ -425,19 +433,22 @@ static int smsc95xx_set_csums(struct ueth_data *dev,
>
> static void smsc95xx_set_multicast(struct ueth_data *dev)
> {
> + struct smsc95xx_private *priv = dev->dev_priv;
> +
> /* No multicast in u-boot */
> - dev->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
> + priv->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
> }
>
> /* starts the TX path */
> static void smsc95xx_start_tx_path(struct ueth_data *dev)
> {
> + struct smsc95xx_private *priv = dev->dev_priv;
> u32 reg_val;
>
> /* Enable Tx at MAC */
> - dev->mac_cr |= MAC_CR_TXEN_;
> + priv->mac_cr |= MAC_CR_TXEN_;
>
> - smsc95xx_write_reg(dev, MAC_CR, dev->mac_cr);
> + smsc95xx_write_reg(dev, MAC_CR, priv->mac_cr);
>
> /* Enable Tx at SCSRs */
> reg_val = TX_CFG_ON_;
> @@ -447,8 +458,10 @@ static void smsc95xx_start_tx_path(struct ueth_data
> *dev) /* Starts the Receive path */
> static void smsc95xx_start_rx_path(struct ueth_data *dev)
> {
> - dev->mac_cr |= MAC_CR_RXEN_;
> - smsc95xx_write_reg(dev, MAC_CR, dev->mac_cr);
> + struct smsc95xx_private *priv = dev->dev_priv;
> +
> + priv->mac_cr |= MAC_CR_RXEN_;
> + smsc95xx_write_reg(dev, MAC_CR, priv->mac_cr);
> }
>
> /*
> @@ -462,6 +475,7 @@ static int smsc95xx_init(struct eth_device *eth, bd_t
> *bd) u32 burst_cap;
> int timeout;
> struct ueth_data *dev = (struct ueth_data *)eth->priv;
> + struct smsc95xx_private *priv = (struct smsc95xx_private *)dev-
>dev_priv;
> #define TIMEOUT_RESOLUTION 50/* ms */
> int link_detected;
>
> @@ -504,9 +518,9 @@ static int smsc95xx_init(struct eth_device *eth, bd_t
> *bd) debug("timeout waiting for PHY Reset\n");
> return -1;
> }
> - if (!dev->have_hwaddr && smsc95xx_init_mac_address(eth, dev) == 0)
> - dev->have_hwaddr = 1;
> - if (!dev->have_hwaddr) {
> + if (!priv->have_hwaddr && smsc95xx_init_mac_address(eth, dev) == 0)
> + priv->have_hwaddr = 1;
> + if (!priv->have_hwaddr) {
> puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n");
> return -1;
> }
> @@ -532,16 +546,16 @@ static int smsc95xx_init(struct eth_device *eth, bd_t
> *bd) #ifdef TURBO_MODE
> if (dev->pusb_dev->speed == USB_SPEED_HIGH) {
> burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
> - dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
> + priv->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
> } else {
> burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
> - dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
> + priv->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
> }
> #else
> burst_cap = 0;
> - dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
> + priv->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
> #endif
> - debug("rx_urb_size=%ld\n", (ulong)dev->rx_urb_size);
> + debug("rx_urb_size=%ld\n", (ulong)priv->rx_urb_size);
>
> ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap);
> if (ret < 0)
> @@ -606,7 +620,7 @@ static int smsc95xx_init(struct eth_d
Re: [U-Boot] [PATCH v2 3/5] at91: atmel_nand: Update driver to support Programmable Multibit ECC controller
On 08/21/2012 05:37 AM, Josh Wu wrote: > Hi, Andreas > > On 8/17/2012 5:24 PM, Andreas Bießmann wrote: >> can you please add some README entry describing these new config >> parameters? >> Namely CONFIG_ATMEL_NAND_HW_PMECC, CONFIG_PMECC_CAP, >> CONFIG_PMECC_SECTOR_SIZE (can't this be derived from some already >> available NAND information?) and CONFIG_PMECC_INDEX_TABLE_OFFSET. > > OK, I will add a README file to explain all the parameters. > this CONFIG_PMECC_SECTOR_SIZE means how many bytes to generate out PMECC > code. It only can be 512 and 1024. > So for a nand chip whose page size is 2048, if CONFIG_PMECC_SECTOR_SIZE > is set as 512, then PMECC will generate PMECC code for each 512 bytes. > > I think it cannot be derived from nand information. So this is basically nand->ecc.size? While this can't be directly read from the chip, usually there's a convention for a given type of NAND chip on a given controller. Do you really need to support both 512 and 1024 for any single chip? Why do you set nand->ecc.size to mtd->writesize if that isn't the actual ECC chunk size? -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 5/5] tegra20: add USB ULPI init code
This adds the required code to set up a ULPI USB port. It is
mostly a port of the Linux ULPI setup code with some tweaks
added for more correctness, discovered along the way of
debugging this.
To use this both CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT
have to be set in the board configuration file.
v2:
- move all controller init stuff in the respective functions to
make them self contained
- let board define ULPI_REF_CLK to account for the possibility
that some ULPI phys need a other ref clk than 24MHz
- don't touch ULPI regs directly, use ULPI framework functions
- don't hide error messages under debug()
Signed-off-by: Lucas Stach
---
arch/arm/cpu/armv7/tegra20/usb.c| 154 +++-
arch/arm/include/asm/arch-tegra20/usb.h | 29 --
2 Dateien geändert, 155 Zeilen hinzugefügt(+), 28 Zeilen entfernt(-)
diff --git a/arch/arm/cpu/armv7/tegra20/usb.c b/arch/arm/cpu/armv7/tegra20/usb.c
index 77966e5..351300b 100644
--- a/arch/arm/cpu/armv7/tegra20/usb.c
+++ b/arch/arm/cpu/armv7/tegra20/usb.c
@@ -32,9 +32,17 @@
#include
#include
#include
+#include
#include
#include
+#ifdef CONFIG_USB_ULPI
+ #ifndef CONFIG_USB_ULPI_VIEWPORT
+ #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \
+ define CONFIG_USB_ULPI_VIEWPORT"
+ #endif
+#endif
+
enum {
USB_PORTS_MAX = 4,/* Maximum ports we allow */
};
@@ -68,11 +76,13 @@ enum dr_mode {
struct fdt_usb {
struct usb_ctlr *reg; /* address of registers in physical memory */
unsigned utmi:1;/* 1 if port has external tranceiver, else 0 */
+ unsigned ulpi:1;/* 1 if port has external ULPI transceiver */
unsigned enabled:1; /* 1 to enable, 0 to disable */
unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */
enum dr_mode dr_mode; /* dual role mode */
enum periph_id periph_id;/* peripheral id */
struct fdt_gpio_state vbus_gpio;/* GPIO for vbus enable */
+ struct fdt_gpio_state phy_reset_gpio; /* GPIO to reset ULPI phy */
};
static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */
@@ -187,8 +197,8 @@ static void usbf_reset_controller(struct fdt_usb *config,
*/
}
-/* set up the USB controller with the parameters provided */
-static int init_usb_controller(struct fdt_usb *config,
+/* set up the UTMI USB controller with the parameters provided */
+static int init_utmi_usb_controller(struct fdt_usb *config,
struct usb_ctlr *usbctlr, const u32 timing[])
{
u32 val;
@@ -297,16 +307,109 @@ static int init_usb_controller(struct fdt_usb *config,
if (!loop_count)
return -1;
- return 0;
-}
+ /* Disable ICUSB FS/LS transceiver */
+ clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
+
+ /* Select UTMI parallel interface */
+ clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
+ PTS_UTMI << PTS_SHIFT);
+ clrbits_le32(&usbctlr->port_sc1, STS);
-static void power_up_port(struct usb_ctlr *usbctlr)
-{
/* Deassert power down state */
clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN);
clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN |
UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
+
+ return 0;
+}
+
+/* set up the ULPI USB controller with the parameters provided */
+static int init_ulpi_usb_controller(struct fdt_usb *config,
+ struct usb_ctlr *usbctlr)
+{
+#ifdef CONFIG_USB_ULPI
+/* if board file does not set a ULPI reference frequency we default to 24MHz */
+#ifndef ULPI_REF_CLK
+#define ULPI_REF_CLK 2400
+#endif
+ u32 val;
+ int loop_count;
+ struct ulpi_viewport ulpi_vp;
+
+ /* set up ULPI reference clock on pllp_out4 */
+ clock_enable(PERIPH_ID_DEV2_OUT);
+ clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, ULPI_REF_CLK);
+
+ /* reset ULPI phy */
+ if (fdt_gpio_isvalid(&config->phy_reset_gpio)) {
+ fdtdec_setup_gpio(&config->phy_reset_gpio);
+ gpio_direction_output(config->phy_reset_gpio.gpio, 0);
+ mdelay(5);
+ gpio_set_value(config->phy_reset_gpio.gpio, 1);
+ }
+
+ /* Reset the usb controller */
+ clock_enable(config->periph_id);
+ usbf_reset_controller(config, usbctlr);
+
+ /* enable pinmux bypass */
+ setbits_le32(&usbctlr->ulpi_timing_ctrl_0,
+ ULPI_CLKOUT_PINMUX_BYP |
ULPI_OUTPUT_PINMUX_BYP);
+
+ /* Select ULPI parallel interface */
+ clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT);
+
+ /* enable ULPI transceiver */
+ setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);
+
+ /* configure ULPI tr
[U-Boot] [PATCH v2 0/5] Tegra 2 USB ULPI series
With this series we are able to initialize USB controllers using an external ULPI phy AKA USB2 on Tegra 2 devices. This was tested to work on a Toradex Colibri T20 board, where USB2 is used to access the ASIX ethernet chipset. Testing was done with "tegra20: usb: rework set_host_mode" [1] applied. I did not spot any regressions on the UTMI ports. v2 incorporates all the review feedback I've got so far, including now trying harder to enable VBus in all configurations. Patch 3 is already in u-boot-usb and only provided as the ULPI init code now depends on it. Igor could you please take a look at Patch 4? Patchset is based on top of u-boot-tegra/next [1] http://lists.denx.de/pipermail/u-boot/2012-August/130177.html Lucas Stach (5): tegra20: complete periph_id enum tegra20: add clock_set_pllout function usb: fix ulpi_set_vbus prototype usb: ulpi: add indicator configuration function tegra20: add USB ULPI init code arch/arm/cpu/armv7/tegra20/usb.c| 154 +++- arch/arm/cpu/tegra20-common/clock.c | 39 +++ arch/arm/cpu/tegra20-common/warmboot_avp.c | 2 +- arch/arm/include/asm/arch-tegra20/clk_rst.h | 11 +- arch/arm/include/asm/arch-tegra20/clock.h | 25 + arch/arm/include/asm/arch-tegra20/usb.h | 29 +- drivers/usb/ulpi/ulpi.c | 26 - include/usb/ulpi.h | 13 ++- 8 Dateien geändert, 262 Zeilen hinzugefügt(+), 37 Zeilen entfernt(-) -- 1.7.11.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 2/5] tegra20: add clock_set_pllout function
Common practice on Tegra 2 boards is to use the pllp_out4 FO
to generate the ULPI reference clock. For this to work we have
to override the default hardware generated output divider.
This function adds a clean way to do so.
v2:
- check if pllout is valid
Signed-off-by: Lucas Stach
---
arch/arm/cpu/tegra20-common/clock.c | 38 +
arch/arm/cpu/tegra20-common/warmboot_avp.c | 2 +-
arch/arm/include/asm/arch-tegra20/clk_rst.h | 11 +++--
arch/arm/include/asm/arch-tegra20/clock.h | 19 +++
4 Dateien geändert, 67 Zeilen hinzugefügt(+), 3 Zeilen entfernt(-)
diff --git a/arch/arm/cpu/tegra20-common/clock.c
b/arch/arm/cpu/tegra20-common/clock.c
index d9bb851..6ebddf8 100644
--- a/arch/arm/cpu/tegra20-common/clock.c
+++ b/arch/arm/cpu/tegra20-common/clock.c
@@ -396,6 +396,16 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
NONE(CRAM2),
};
+/* number of clock outputs of a PLL */
+static const u8 pll_num_clkouts[] = {
+ 1, /* PLLC */
+ 1, /* PLLM */
+ 4, /* PLLP */
+ 1, /* PLLA */
+ 0, /* PLLU */
+ 0, /* PLLD */
+};
+
/*
* Get the oscillator frequency, from the corresponding hardware configuration
* field.
@@ -604,6 +614,34 @@ unsigned long clock_get_periph_rate(enum periph_id
periph_id,
(readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
}
+int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned
rate)
+{
+ struct clk_pll *pll = get_pll(clkid);
+ int data = 0, div = 0, offset = 0;
+
+ if (!clock_id_is_pll(clkid))
+ return -1;
+
+ if (pllout + 1 > pll_num_clkouts[clkid])
+ return -1;
+
+ div = clk_get_divider(8, pll_rate[clkid], rate);
+
+ if (div < 0)
+ return -1;
+
+ /* out2 and out4 are in the high part of the register */
+ if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
+ offset = 16;
+
+ data = (div << PLL_OUT_RATIO_SHIFT) |
+ PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
+ clrsetbits_le32(&pll->pll_out[pllout >> 1],
+ PLL_OUT_RATIO_MASK << offset, data << offset);
+
+ return 0;
+}
+
/**
* Find the best available 7.1 format divisor given a parent clock rate and
* required child clock rate. This function assumes that a second-stage
diff --git a/arch/arm/cpu/tegra20-common/warmboot_avp.c
b/arch/arm/cpu/tegra20-common/warmboot_avp.c
index cd01908..f6c71cb 100644
--- a/arch/arm/cpu/tegra20-common/warmboot_avp.c
+++ b/arch/arm/cpu/tegra20-common/warmboot_avp.c
@@ -214,7 +214,7 @@ void wb_start(void)
reg = PLLM_OUT1_RSTN_RESET_DISABLE | PLLM_OUT1_CLKEN_ENABLE |
PLLM_OUT1_RATIO_VAL_8;
- writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out);
+ writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out[0]);
reg = SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 | SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 |
SCLK_SWAKE_RUN_SRC_PLLM_OUT1 | SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 |
diff --git a/arch/arm/include/asm/arch-tegra20/clk_rst.h
b/arch/arm/include/asm/arch-tegra20/clk_rst.h
index 8c3be91..7b548c2 100644
--- a/arch/arm/include/asm/arch-tegra20/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra20/clk_rst.h
@@ -27,8 +27,7 @@
/* PLL registers - there are several PLLs in the clock controller */
struct clk_pll {
uint pll_base; /* the control register */
- uint pll_out; /* output control */
- uint reserved;
+ uint pll_out[2];/* output control */
uint pll_misc; /* other misc things */
};
@@ -112,6 +111,14 @@ struct clk_rst_ctlr {
#define PLL_DIVM_SHIFT 0
#define PLL_DIVM_MASK (0x1f << PLL_DIVM_SHIFT)
+/* CLK_RST_CONTROLLER_PLLx_OUTx_0 */
+#define PLL_OUT_RSTN (1 << 0)
+#define PLL_OUT_CLKEN (1 << 1)
+#define PLL_OUT_OVRRIDE(1 << 2)
+
+#define PLL_OUT_RATIO_SHIFT8
+#define PLL_OUT_RATIO_MASK (0xffU << PLL_OUT_RATIO_SHIFT)
+
/* CLK_RST_CONTROLLER_PLLx_MISC_0 */
#define PLL_CPCON_SHIFT8
#define PLL_CPCON_MASK (15U << PLL_CPCON_SHIFT)
diff --git a/arch/arm/include/asm/arch-tegra20/clock.h
b/arch/arm/include/asm/arch-tegra20/clock.h
index 20db9e6..dfef51e 100644
--- a/arch/arm/include/asm/arch-tegra20/clock.h
+++ b/arch/arm/include/asm/arch-tegra20/clock.h
@@ -186,6 +186,13 @@ enum periph_id {
PERIPH_ID_NONE = -1,
};
+enum pll_out_id {
+ PLL_OUT1,
+ PLL_OUT2,
+ PLL_OUT3,
+ PLL_OUT4
+};
+
/* Converts a clock number to a clock register: 0=L, 1=H, 2=U */
#define PERIPH_REG(id) ((id) >> 5)
@@ -218,6 +225,18 @@ unsigned long clock_start_pll(enum clock_id id, u32 divm,
u32 divn,
u32 divp, u32 cpcon, u32 lfcon);
/**
+ * Set PLL output frequency
+ *
+ * @param clkidclock id
+ * @param pllout pll output id (
+ * @param rate
[U-Boot] [PATCH v2 4/5] usb: ulpi: add indicator configuration function
Allows for easy configuration of the VBUS indicator related ULPI
config bits.
Also move the external indicator setup from ulpi_set_vbus() to
the new function.
Signed-off-by: Lucas Stach
---
drivers/usb/ulpi/ulpi.c | 26 ++
include/usb/ulpi.h | 13 +++--
2 Dateien geändert, 33 Zeilen hinzugefügt(+), 6 Zeilen entfernt(-)
diff --git a/drivers/usb/ulpi/ulpi.c b/drivers/usb/ulpi/ulpi.c
index dde2585..f358bde 100644
--- a/drivers/usb/ulpi/ulpi.c
+++ b/drivers/usb/ulpi/ulpi.c
@@ -106,20 +106,38 @@ int ulpi_select_transceiver(struct ulpi_viewport
*ulpi_vp, unsigned speed)
return ulpi_write(ulpi_vp, &ulpi->function_ctrl, val);
}
-int ulpi_set_vbus(struct ulpi_viewport *ulpi_vp, int on, int ext_power,
- int ext_ind)
+int ulpi_set_vbus(struct ulpi_viewport *ulpi_vp, int on, int ext_power)
{
u32 flags = ULPI_OTG_DRVVBUS;
u8 *reg = on ? &ulpi->otg_ctrl_set : &ulpi->otg_ctrl_clear;
if (ext_power)
flags |= ULPI_OTG_DRVVBUS_EXT;
- if (ext_ind)
- flags |= ULPI_OTG_EXTVBUSIND;
return ulpi_write(ulpi_vp, reg, flags);
}
+int ulpi_set_vbus_indicator(struct ulpi_viewport *ulpi_vp, int external,
+ int passthu, int complement)
+{
+ u8 *reg;
+ int ret;
+
+ reg = external ? &ulpi->otg_ctrl_set : &ulpi->otg_ctrl_clear;
+ if ((ret = ulpi_write(ulpi_vp, reg, ULPI_OTG_EXTVBUSIND)))
+ return ret;
+
+ reg = passthu ? &ulpi->iface_ctrl_set : &ulpi->iface_ctrl_clear;
+ if ((ret = ulpi_write(ulpi_vp, reg, ULPI_IFACE_PASSTHRU)))
+ return ret;
+
+ reg = complement ? &ulpi->iface_ctrl_set : &ulpi->iface_ctrl_clear;
+ if ((ret = ulpi_write(ulpi_vp, reg, ULPI_IFACE_EXTVBUS_COMPLEMENT)))
+ return ret;
+
+ return 0;
+}
+
int ulpi_set_pd(struct ulpi_viewport *ulpi_vp, int enable)
{
u32 val = ULPI_OTG_DP_PULLDOWN | ULPI_OTG_DM_PULLDOWN;
diff --git a/include/usb/ulpi.h b/include/usb/ulpi.h
index 9a75c24..99166c4 100644
--- a/include/usb/ulpi.h
+++ b/include/usb/ulpi.h
@@ -61,8 +61,17 @@ int ulpi_select_transceiver(struct ulpi_viewport *ulpi_vp,
unsigned speed);
*
* returns 0 on success, ULPI_ERROR on failure.
*/
-int ulpi_set_vbus(struct ulpi_viewport *ulpi_vp,
- int on, int ext_power, int ext_ind);
+int ulpi_set_vbus(struct ulpi_viewport *ulpi_vp, int on, int ext_power);
+
+/*
+ * Configure VBUS indicator
+ * @external - external VBUS over-current indicator is used
+ * @passthru - disables ANDing of internal VBUS comparator
+ *with external VBUS input
+ * @complement - inverts the external VBUS input
+ */
+int ulpi_set_vbus_indicator(struct ulpi_viewport *ulpi_vp, int external,
+ int passthru, int complement);
/*
* Enable/disable pull-down resistors on D+ and D- USB lines.
--
1.7.11.4
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[U-Boot] [PATCH v2 1/5] tegra20: complete periph_id enum
Most Tegra boards output the ULPI reference clock on pad DEV2.
Complete the periph_id enum so that we are able to enable this
clock output circuit.
Signed-off-by: Lucas Stach
Acked-by: Stephen Warren
Acked-by: Simon Glass
---
arch/arm/cpu/tegra20-common/clock.c | 1 +
arch/arm/include/asm/arch-tegra20/clock.h | 6 ++
2 Dateien geändert, 7 Zeilen hinzugefügt(+)
diff --git a/arch/arm/cpu/tegra20-common/clock.c
b/arch/arm/cpu/tegra20-common/clock.c
index 2403874..d9bb851 100644
--- a/arch/arm/cpu/tegra20-common/clock.c
+++ b/arch/arm/cpu/tegra20-common/clock.c
@@ -502,6 +502,7 @@ static int clock_periph_id_isvalid(enum periph_id id)
case PERIPH_ID_RESERVED81:
case PERIPH_ID_RESERVED82:
case PERIPH_ID_RESERVED83:
+ case PERIPH_ID_RESERVED91:
printf("Peripheral id %d is reserved\n", id);
break;
default:
diff --git a/arch/arm/include/asm/arch-tegra20/clock.h
b/arch/arm/include/asm/arch-tegra20/clock.h
index ff83bbf..20db9e6 100644
--- a/arch/arm/include/asm/arch-tegra20/clock.h
+++ b/arch/arm/include/asm/arch-tegra20/clock.h
@@ -175,6 +175,12 @@ enum periph_id {
/* 88 */
PERIPH_ID_CRAM2,
+ PERIPH_ID_SYNC_CLK_DOUBLER,
+ PERIPH_ID_CLK_M_DOUBLER,
+ PERIPH_ID_RESERVED91,
+ PERIPH_ID_SUS_OUT,
+ PERIPH_ID_DEV2_OUT,
+ PERIPH_ID_DEV1_OUT,
PERIPH_ID_COUNT,
PERIPH_ID_NONE = -1,
--
1.7.11.4
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[U-Boot] [PATCH v2 3/5] usb: fix ulpi_set_vbus prototype
Match the name of the header prototype with the actual implementation. Signed-off-by: Lucas Stach --- include/usb/ulpi.h | 2 +- 1 Datei geändert, 1 Zeile hinzugefügt(+), 1 Zeile entfernt(-) diff --git a/include/usb/ulpi.h b/include/usb/ulpi.h index 4a23fd2..9a75c24 100644 --- a/include/usb/ulpi.h +++ b/include/usb/ulpi.h @@ -61,7 +61,7 @@ int ulpi_select_transceiver(struct ulpi_viewport *ulpi_vp, unsigned speed); * * returns 0 on success, ULPI_ERROR on failure. */ -int ulpi_enable_vbus(struct ulpi_viewport *ulpi_vp, +int ulpi_set_vbus(struct ulpi_viewport *ulpi_vp, int on, int ext_power, int ext_ind); /* -- 1.7.11.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 2/3] mx51evk: Use IMX_GPIO_NR macro
From: Fabio Estevam Use IMX_GPIO_NR macro. Signed-off-by: Fabio Estevam --- Changes since v1: - Remove unnecessary comment board/freescale/mx51evk/mx51evk.c |6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 97c8a2c..651b506 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -39,9 +39,9 @@ #include #include -#define MX51EVK_LCD_3V3(3 * 32 + 9)/* GPIO4_9 */ -#define MX51EVK_LCD_5V (3 * 32 + 10) /* GPIO4_10 */ -#define MX51EVK_LCD_BACKLIGHT (2 * 32 + 4)/* GPIO3_4 */ +#define MX51EVK_LCD_3V3IMX_GPIO_NR(4, 9) +#define MX51EVK_LCD_5V IMX_GPIO_NR(4, 10) +#define MX51EVK_LCD_BACKLIGHT IMX_GPIO_NR(3, 4) DECLARE_GLOBAL_DATA_PTR; -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/3] mx53loco: Use IMX_GPIO_NR macro
From: Fabio Estevam Use IMX_GPIO_NR macro. Signed-off-by: Fabio Estevam --- Changes since v1: - Remove unnecessary comment board/freescale/mx53loco/mx53loco.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index 7cfb3f4..3a39c3e 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -42,7 +42,7 @@ #include #include -#define MX53LOCO_LCD_POWER (2 * 32 + 24) /* GPIO3_24 */ +#define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24) DECLARE_GLOBAL_DATA_PTR; -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 3/3] mx53ard: Use IMX_GPIO_NR macro
From: Fabio Estevam Use IMX_GPIO_NR macro. Signed-off-by: Fabio Estevam --- Changes since v1: - Remove unnecessary comment board/freescale/mx53ard/mx53ard.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c index 2d21584..688cff1 100644 --- a/board/freescale/mx53ard/mx53ard.c +++ b/board/freescale/mx53ard/mx53ard.c @@ -33,7 +33,7 @@ #include #include -#define ETHERNET_INT (1 * 32 + 31) /* GPIO2_31 */ +#define ETHERNET_INT IMX_GPIO_NR(2, 31) DECLARE_GLOBAL_DATA_PTR; -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] mx53loco: Use IMX_GPIO_NR macro
On 8/21/2012 10:26 AM, Fabio Estevam wrote: Use IMX_GPIO_NR macro. Signed-off-by: Fabio Estevam --- board/freescale/mx53loco/mx53loco.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index 7cfb3f4..3a39c3e 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -42,7 +42,7 @@ #include #include -#define MX53LOCO_LCD_POWER (2 * 32 + 24) /* GPIO3_24 */ +#define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24) /* GPIO3_24 */ DECLARE_GLOBAL_DATA_PTR; I'd kill the now redundant comment as well. But I don't mind if you don't. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Support for USB Ethernet adapter
So, this adapter is based on ASIX chip http://www.asix.com.tw/products.php?op=pItemdetail&PItemID=109;74;109 Could you provide me some instruction how to make it working? Best regards Daniel W dniu 20.08.2012 15:44, Marek Vasut pisze: Dear Daniel Ścisłowski, Dear Mr Marek Vasut, CCing U-boot mailing list. Please keep it. I would be grateful if you could tell me if U-Boot (currently I use 2012.07) supports USB-Ethernet adapter Yes, it does support adapter based on ASIX chips and SMSC 95xx chips. from MosChip Semiconductors MCS7830. Check the chipset or try it. If not, is it possible to write driver for that device? Yes it is. It's not hard either. Yours sincerely Daniel Ścisłowski Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] tegra20: rework UART GPIO handling
On Mon, Aug 20, 2012 at 8:48 AM, Stephen Warren wrote:
> On 08/19/2012 12:15 PM, Lucas Stach wrote:
>> Rename board provided gpio_config_uart() to
>> gpio_early_init_uart() as it does the same thing as the equally
>> called function provided by the uart-switch code. This allows
>> to simply call this function in early board init whether or not
>> we are building with CONFIG_UART_SWITCH defined.
>>
>> Also provide a weak symbol for this function, to avoid the
>> need to provide this function for boards that don't need any
>> fixup.
>>
>> This patch supersedes the earlier posted
>> "tegra: convert gpio_config_uart to weak symbol".
>> Build tested with MAKEALL -s tegra20
>>
>> Signed-off-by: Lucas Stach
Acked-by: Simon Glass
>
> I think this seems reasonable. However, a couple others should comment,
> so I'm CCing them and quoting the whole patch.
>
> Simon Glass should comment because he created the UART switch code.
This change seems reasonable to me.
> Allen Martin should comment, since it looks like both SPL and non-SPL
> end up calling gpio_early_init_uart(); is that duplication correct or
> problematic?
OK so far as seaboard goes, but could perhaps do with a tidy up at some point.
Regards,
Simon
>
>> ---
>> arch/arm/cpu/arm720t/tegra20/board.h | 2 +-
>> arch/arm/cpu/arm720t/tegra20/spl.c | 4
>> board/avionic-design/common/tamonten.c | 7 ---
>> board/compal/paz00/paz00.c | 7 ---
>> board/compulab/trimslice/trimslice.c | 7 ---
>> board/nvidia/common/board.c| 10 ++
>> board/nvidia/harmony/harmony.c | 7 ---
>> board/nvidia/seaboard/seaboard.c | 2 +-
>> board/nvidia/whistler/whistler.c | 7 ---
>> 9 Dateien geändert, 8 Zeilen hinzugefügt(+), 45 Zeilen entfernt(-)
>>
>> diff --git a/arch/arm/cpu/arm720t/tegra20/board.h
>> b/arch/arm/cpu/arm720t/tegra20/board.h
>> index 61b91c0..260767d 100644
>> --- a/arch/arm/cpu/arm720t/tegra20/board.h
>> +++ b/arch/arm/cpu/arm720t/tegra20/board.h
>> @@ -22,4 +22,4 @@
>> */
>>
>> void board_init_uart_f(void);
>> -void gpio_config_uart(void);
>> +void gpio_early_init_uart(void);
>> diff --git a/arch/arm/cpu/arm720t/tegra20/spl.c
>> b/arch/arm/cpu/arm720t/tegra20/spl.c
>> index da723ef..183a2e1 100644
>> --- a/arch/arm/cpu/arm720t/tegra20/spl.c
>> +++ b/arch/arm/cpu/arm720t/tegra20/spl.c
>> @@ -65,11 +65,7 @@ void board_init_f(ulong dummy)
>> board_init_uart_f();
>>
>> /* Initialize periph GPIOs */
>> -#ifdef CONFIG_SPI_UART_SWITCH
>> gpio_early_init_uart();
>> -#else
>> - gpio_config_uart();
>> -#endif
>>
>> /*
>>* We call relocate_code() with relocation target same as the
>> diff --git a/board/avionic-design/common/tamonten.c
>> b/board/avionic-design/common/tamonten.c
>> index a0a4d1d..f5e6f6d 100644
>> --- a/board/avionic-design/common/tamonten.c
>> +++ b/board/avionic-design/common/tamonten.c
>> @@ -41,13 +41,6 @@
>> #include
>> #endif
>>
>> -/*
>> - * Routine: gpio_config_uart
>> - * Description: Does nothing on Tamonten - no conflict w/SPI.
>> - */
>> -void gpio_config_uart(void)
>> -{
>> -}
>>
>> #ifdef CONFIG_BOARD_EARLY_INIT_F
>> void gpio_early_init(void)
>> diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c
>> index cd684f2..59cf41b 100644
>> --- a/board/compal/paz00/paz00.c
>> +++ b/board/compal/paz00/paz00.c
>> @@ -24,13 +24,6 @@
>> #include
>> #endif
>>
>> -/*
>> - * Routine: gpio_config_uart
>> - * Description: Does nothing on Paz00 - no conflict w/SPI.
>> - */
>> -void gpio_config_uart(void)
>> -{
>> -}
>>
>> #ifdef CONFIG_TEGRA_MMC
>> /*
>> diff --git a/board/compulab/trimslice/trimslice.c
>> b/board/compulab/trimslice/trimslice.c
>> index 5dae15b..f6de19e 100644
>> --- a/board/compulab/trimslice/trimslice.c
>> +++ b/board/compulab/trimslice/trimslice.c
>> @@ -34,13 +34,6 @@
>> #include
>> #endif
>>
>> -/*
>> - * Routine: gpio_config_uart
>> - * Description: Does nothing on TrimSlice - no UART-related GPIOs.
>> - */
>> -void gpio_config_uart(void)
>> -{
>> -}
>>
>> void pin_mux_spi(void)
>> {
>> diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
>> index 7ab2040..78e136a 100644
>> --- a/board/nvidia/common/board.c
>> +++ b/board/nvidia/common/board.c
>> @@ -72,6 +72,11 @@ void __pin_mux_spi(void)
>>
>> void pin_mux_spi(void) __attribute__((weak, alias("__pin_mux_spi")));
>>
>> +void __gpio_early_init_uart(void)
>> +{
>> +}
>> +
>> +void gpio_early_init_uart(void) __attribute__((weak,
>> alias("__gpio_early_init_uart")));
>> /*
>> * Routine: power_det_init
>> * Description: turn off power detects
>> @@ -156,11 +161,8 @@ int board_early_init_f(void)
>>
>> /* Initialize periph GPIOs */
>> gpio_early_init();
>> -#ifdef CONFIG_SPI_UART_SWITCH
>> gpio_early_init_uart();
>> -#else
>> - gpio_config_uart();
>> -#endif
>> +
>> return 0;
>> }
>> #endif /* EARLY_INIT */
>> diff --git a/board/nvidia/harmony/harmony.c b/board
Re: [U-Boot] [PATCH 1/3] tegra20: complete periph_id enum
On Sun, Aug 19, 2012 at 9:08 AM, Lucas Stach wrote:
> Most Tegra boards output the ULPI reference clock on pad DEV2.
>
> Complete the periph_id enum so that we are able to enable this
> clock output circuit.
>
> Signed-off-by: Lucas Stach
Acked-by: Simon Glass
> ---
> arch/arm/cpu/tegra20-common/clock.c | 1 +
> arch/arm/include/asm/arch-tegra20/clock.h | 6 ++
> 2 Dateien geändert, 7 Zeilen hinzugefügt(+)
>
> diff --git a/arch/arm/cpu/tegra20-common/clock.c
> b/arch/arm/cpu/tegra20-common/clock.c
> index 2403874..d9bb851 100644
> --- a/arch/arm/cpu/tegra20-common/clock.c
> +++ b/arch/arm/cpu/tegra20-common/clock.c
> @@ -502,6 +502,7 @@ static int clock_periph_id_isvalid(enum periph_id id)
> case PERIPH_ID_RESERVED81:
> case PERIPH_ID_RESERVED82:
> case PERIPH_ID_RESERVED83:
> + case PERIPH_ID_RESERVED91:
> printf("Peripheral id %d is reserved\n", id);
> break;
> default:
> diff --git a/arch/arm/include/asm/arch-tegra20/clock.h
> b/arch/arm/include/asm/arch-tegra20/clock.h
> index ff83bbf..20db9e6 100644
> --- a/arch/arm/include/asm/arch-tegra20/clock.h
> +++ b/arch/arm/include/asm/arch-tegra20/clock.h
> @@ -175,6 +175,12 @@ enum periph_id {
>
> /* 88 */
> PERIPH_ID_CRAM2,
> + PERIPH_ID_SYNC_CLK_DOUBLER,
> + PERIPH_ID_CLK_M_DOUBLER,
> + PERIPH_ID_RESERVED91,
> + PERIPH_ID_SUS_OUT,
> + PERIPH_ID_DEV2_OUT,
> + PERIPH_ID_DEV1_OUT,
>
> PERIPH_ID_COUNT,
> PERIPH_ID_NONE = -1,
> --
> 1.7.11.2
>
> ___
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> http://lists.denx.de/mailman/listinfo/u-boot
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Re: [U-Boot] [PATCH 2/4] spi: atmel: add WDRBT bit to avoid receive overrun
On Tuesday 21 August 2012 07:11:18 Andreas Bießmann wrote: > On 20.08.2012 08:32, Bo Shen wrote: > > The atmel at91sam9x5 series spi has feature to avoid receive overren > > > > Using the patch to enable it > > > > Signed-off-by: Bo Shen > > Acked-by: Andreas Bießmann > > Mike, will you take this patch? for SoC drivers, sometimes i'll help review, but i'd expect it to be merged through the respective architecture tree. i've only been sheriffing the spi core changes. -mike signature.asc Description: This is a digitally signed message part. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] spiflash: at25: using common spi flash operation
On Tuesday 21 August 2012 07:26:27 Andreas Bießmann wrote: > On 20.08.2012 08:32, Bo Shen wrote: > > Using common spi flash operation function to replace private operation > > funtion > > > > This patch is based on http://patchwork.ozlabs.org/patch/177896/ > > which has been merged by Mike frysinger > > Mike, do you think this is a fix? Should it go into 2012.10? Will you > take it? i'll take care of merging the changes to drivers/mtd/spi/*, but always happy to see people help to review the changes :). especially with the atmel driver as their dataflashes have the unique command set :(. -mike signature.asc Description: This is a digitally signed message part. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch v3 2/2] net: asix: add support for AX88772B
On Tuesday 21 August 2012 09:23:13 Lucas Stach wrote: > + struct ueth_data *dev = (struct ueth_data *)eth->priv; > + struct asix_private *priv = (struct asix_private *)dev->dev_priv; not that it's harmful, but priv is void*, so the casts aren't needed > + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, ee_buf, 2); > + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN); since you don't use both buffers at the same time, just declare one that is big enough to work for either code path. so looks like you could throw away ee_buf here. -mike signature.asc Description: This is a digitally signed message part. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch v3 1/2] net: introduce transparent driver private in ueth_data
On Tuesday 21 August 2012 09:23:12 Lucas Stach wrote: > Avoid clutter in ueth_data. Individual drivers should not mess > with structures belonging to the core like this. nice work -mike signature.asc Description: This is a digitally signed message part. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 1/1] mx31/mx35/mx51/mx53/mx6: add watchdog
On 8/20/2012 11:11 PM, Stefano Babic wrote:
On 21/08/2012 01:03, Troy Kisky wrote:
diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h
b/arch/arm/include/asm/arch-mx31/imx-regs.h
index bba37ac..594d613 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -68,17 +68,6 @@ struct cspi_regs {
u32 test;
};
-#define WDOG_BASE 0x53FDC000
-
+#define WDOG1_BASE_ADDR0x53FDC000
+#define CONFIG_IMX_WATCHDOG/* cpu_reset implemented in watchdog */
/*
* GPIO
*/
diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h
b/arch/arm/include/asm/arch-mx35/imx-regs.h
index b18b984..45b331f 100644
--- a/arch/arm/include/asm/arch-mx35/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx35/imx-regs.h
@@ -76,7 +76,8 @@
#define GPIO2_BASE_ADDR 0x53FD
#define SDMA_BASE_ADDR0x53FD4000
#define RTC_BASE_ADDR 0x53FD8000
-#define WDOG_BASE_ADDR 0x53FDC000
+#define WDOG1_BASE_ADDR0x53FDC000
+#define CONFIG_IMX_WATCHDOG/* cpu_reset implemented in watchdog */
#define PWM_BASE_ADDR 0x53FE
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h
b/arch/arm/include/asm/arch-mx5/imx-regs.h
index c53465f..caac574 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -78,6 +78,7 @@
#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009)
#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
+#define CONFIG_IMX_WATCHDOG/* cpu_reset implemented in watchdog */
#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
#define GPT1_BASE_ADDR(AIPS1_BASE_ADDR + 0x000A)
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index dacb9ea..0f59567 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -115,6 +115,7 @@
#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
+#define CONFIG_IMX_WATCHDOG/* cpu_reset implemented in watchdog */
#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4)
#define ANATOP_BASE_ADDR(AIPS1_OFF_BASE_ADDR + 0x48000)
#define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000)
I have only an issue with your patch. You move the reset_cpu (good idea
so we can factorize it) inside imx_watchdog.c, but then it depends on
CONFIG_IMX_WATCHDOG. If it is not set, the file is not compiled and
there is no reset_cpu. This constraints all boards to activate it, but
this is not what we want.
Best regards,
Stefano
So, you are saying CONFIG_ options don't belong in imx-regs.h, or
you didn't notice I stuck it there, or both???
Troy
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[U-Boot] [PATCH 2/3] mx51evk: Use IMX_GPIO_NR macro
Use IMX_GPIO_NR macro. Signed-off-by: Fabio Estevam --- board/freescale/mx51evk/mx51evk.c |6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 97c8a2c..651b506 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -39,9 +39,9 @@ #include #include -#define MX51EVK_LCD_3V3(3 * 32 + 9)/* GPIO4_9 */ -#define MX51EVK_LCD_5V (3 * 32 + 10) /* GPIO4_10 */ -#define MX51EVK_LCD_BACKLIGHT (2 * 32 + 4)/* GPIO3_4 */ +#define MX51EVK_LCD_3V3IMX_GPIO_NR(4, 9) /* GPIO4_9 */ +#define MX51EVK_LCD_5V IMX_GPIO_NR(4, 10) /* GPIO4_10 */ +#define MX51EVK_LCD_BACKLIGHT IMX_GPIO_NR(3, 4) /* GPIO3_4 */ DECLARE_GLOBAL_DATA_PTR; -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] mx53loco: Use IMX_GPIO_NR macro
Use IMX_GPIO_NR macro. Signed-off-by: Fabio Estevam --- board/freescale/mx53loco/mx53loco.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index 7cfb3f4..3a39c3e 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -42,7 +42,7 @@ #include #include -#define MX53LOCO_LCD_POWER (2 * 32 + 24) /* GPIO3_24 */ +#define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24) /* GPIO3_24 */ DECLARE_GLOBAL_DATA_PTR; -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/3] mx53ard: Use IMX_GPIO_NR macro
Use IMX_GPIO_NR macro. Signed-off-by: Fabio Estevam --- board/freescale/mx53ard/mx53ard.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c index 2d21584..688cff1 100644 --- a/board/freescale/mx53ard/mx53ard.c +++ b/board/freescale/mx53ard/mx53ard.c @@ -33,7 +33,7 @@ #include #include -#define ETHERNET_INT (1 * 32 + 31) /* GPIO2_31 */ +#define ETHERNET_INT IMX_GPIO_NR(2, 31) /* GPIO2_31 */ DECLARE_GLOBAL_DATA_PTR; -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/7] dm: Add skeleton support for cores and drivers
From: Pavel Herrmann
Signed-off-by: Pavel Herrmann
Signed-off-by: Marek Vasut
---
Makefile|2 +
common/dm/Makefile | 40 +
common/dm/core.c| 150
common/dm/driver.c | 404 +++
common/dm/lists.c | 138 +++
common/dm/root.c| 103 +++
common/dm/tree.c| 164 ++
common/dm/tree.h| 31
include/dm/core_numbering.h | 33
include/dm/manager.h| 57 ++
include/dm/options.h| 46 +
include/dm/structures.h | 154 +
12 files changed, 1322 insertions(+)
create mode 100644 common/dm/Makefile
create mode 100644 common/dm/core.c
create mode 100644 common/dm/driver.c
create mode 100644 common/dm/lists.c
create mode 100644 common/dm/root.c
create mode 100644 common/dm/tree.c
create mode 100644 common/dm/tree.h
create mode 100644 include/dm/core_numbering.h
create mode 100644 include/dm/manager.h
create mode 100644 include/dm/options.h
create mode 100644 include/dm/structures.h
diff --git a/Makefile b/Makefile
index 67c89ca..0e008b1 100644
--- a/Makefile
+++ b/Makefile
@@ -301,6 +301,8 @@ LIBS-y += api/libapi.o
LIBS-y += post/libpost.o
LIBS-y += test/libtest.o
+LIBS-$(CONFIG_DM) += common/dm/libdm.o
+
ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
endif
diff --git a/common/dm/Makefile b/common/dm/Makefile
new file mode 100644
index 000..6510021
--- /dev/null
+++ b/common/dm/Makefile
@@ -0,0 +1,40 @@
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB:= $(obj)libdm.o
+
+COBJS := core.o driver.o lists.o tree.o root.o
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+all: $(LIB)
+
+$(LIB):$(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/common/dm/core.c b/common/dm/core.c
new file mode 100644
index 000..4a183d8
--- /dev/null
+++ b/common/dm/core.c
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2012
+ * Pavel Herrmann
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+
+/**
+ * core_get_count() - Return number of registered children with core
+ * @id:ID of the core
+ *
+ * Count the number of members registered with this core and return
+ * the value. Negative value is returned in case of failure.
+ */
+int core_get_count(enum core_id id)
+{
+ struct core_instance *core;
+ struct u_boot_core *core_ops;
+
+ core = get_core_instance(id);
+ if (!core)
+ return -ENOMEM;
+
+ core_ops = get_core_by_id(id);
+ if (!core_ops)
+ return -ENOENT;
+
+ return core_ops->get_count(core);
+}
+
+/**
+ * core_get_child() - Return n-th child of core
+ * @id:ID of the core
+ * @index: Position of the child in core's list
+ *
+ * Return the instance pointer of a child at the given index or
+ * return NULL on error.
+ */
+struct instance *core_get_child(enum core_id id, int index)
+{
+ struct core_instance *core;
+ struct u_boot_core *core_o
[U-Boot] [PATCH 6/7] dm: add dummy demo driver and core
From: Pavel Herrmann
Signed-off-by: Pavel Herrmann
---
Makefile|1 +
drivers/demo/Makefile | 42
drivers/demo/core.c | 236 +++
drivers/demo/demo.c | 67
include/dm/core_numbering.h |1 +
include/dm/demo.h | 37 +++
6 files changed, 384 insertions(+)
create mode 100644 drivers/demo/Makefile
create mode 100644 drivers/demo/core.c
create mode 100644 drivers/demo/demo.c
create mode 100644 include/dm/demo.h
diff --git a/Makefile b/Makefile
index 0e008b1..ba74696 100644
--- a/Makefile
+++ b/Makefile
@@ -302,6 +302,7 @@ LIBS-y += post/libpost.o
LIBS-y += test/libtest.o
LIBS-$(CONFIG_DM) += common/dm/libdm.o
+LIBS-$(CONFIG_DM) += drivers/demo/libdemo.o
ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
diff --git a/drivers/demo/Makefile b/drivers/demo/Makefile
new file mode 100644
index 000..192bd7d
--- /dev/null
+++ b/drivers/demo/Makefile
@@ -0,0 +1,42 @@
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB:= $(obj)libdemo.o
+
+COBJS-y += demo.o core.o
+
+COBJS := $(COBJS-y)
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+all: $(LIB)
+
+$(LIB):$(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/drivers/demo/core.c b/drivers/demo/core.c
new file mode 100644
index 000..1e6684b
--- /dev/null
+++ b/drivers/demo/core.c
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2012
+ * Pavel Herrmann
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+
+struct demo_core_entry {
+ struct list_headlist;
+ struct instance *instance;
+ struct demo_ops *ops;
+};
+
+static struct demo_ops *get_ops(struct instance *inst)
+{
+ struct core_instance *core = NULL;
+ struct demo_core_entry *tmp;
+
+ if (!inst)
+ return NULL;
+
+ core = get_core_instance(CORE_DEMO);
+ if (!core)
+ /* something has gone terribly wrong here...*/
+ return NULL;
+
+ list_for_each_entry(tmp, &core->succ, list) {
+ if (tmp->instance == inst)
+ return tmp->ops;
+ }
+
+ return NULL;
+}
+
+static int demo_core_get_count(struct core_instance *core)
+{
+ struct demo_core_entry *tmp;
+ int i = 0;
+
+ list_for_each_entry(tmp, &core->succ, list)
+ i++;
+
+ return i;
+}
+
+static struct instance *demo_core_get_child(struct core_instance *core, int
idx)
+{
+ struct demo_core_entry *tmp;
+ int i = 0;
+
+ list_for_each_entry(tmp, &core->succ, list) {
+ if (i == idx)
+ return tmp->instance;
+ i++;
+ }
+
+ return NULL;
+}
+
+static int demo_core_bind(struct core_instance *core, struct instance *dev,
+ void *ops, void *data)
+{
+ struct demo_core_entry *entry;
+
+ if (data || !ops)
+ return -EINVAL;
+
+ entry = malloc(sizeof(*entry));
+ if (!en
[U-Boot] [PATCH 7/7] dm: Add "dm dump" command
Dumps the content of system tree
Signed-off-by: Marek Vasut
---
common/dm/Makefile |2 +-
common/dm/debug.c | 106
include/dm/debug.h | 33
3 files changed, 140 insertions(+), 1 deletion(-)
create mode 100644 common/dm/debug.c
create mode 100644 include/dm/debug.h
diff --git a/common/dm/Makefile b/common/dm/Makefile
index 6510021..2096c6b 100644
--- a/common/dm/Makefile
+++ b/common/dm/Makefile
@@ -21,7 +21,7 @@ include $(TOPDIR)/config.mk
LIB:= $(obj)libdm.o
-COBJS := core.o driver.o lists.o tree.o root.o
+COBJS := core.o debug.o driver.o lists.o tree.o root.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/common/dm/debug.c b/common/dm/debug.c
new file mode 100644
index 000..da669b7
--- /dev/null
+++ b/common/dm/debug.c
@@ -0,0 +1,106 @@
+/*
+ * (C) Copyright 2012
+ * Marek Vasut
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+static int display_succ(struct instance *in, char *buf)
+{
+ int len;
+ int ip = 0;
+ char local[16];
+ struct driver_instance *pos, *n, *prev = NULL, *outer;
+
+ outer = container_of(in, struct driver_instance, i);
+ printf("%s- %s @ 0x%p", buf, in->info->name, in);
+ if (outer->flags & DRIVER_FLAG_ACTIVATED)
+ puts(" - activated");
+ puts("\n");
+
+ if (list_empty(&in->succ))
+ return 0;
+
+ len = strlen(buf);
+ strncpy(local, buf, sizeof(local));
+ snprintf(local + len, 2, "|");
+ if (len && local[len - 1] == '`')
+ local[len - 1] = ' ';
+
+ list_for_each_entry_safe(pos, n, &in->succ, list) {
+ if (ip++)
+ display_succ(&prev->i, local);
+ prev = pos;
+ }
+
+ snprintf(local + len, 2, "`");
+ display_succ(&prev->i, local);
+
+ return 0;
+}
+
+int dm_dump_all()
+{
+ struct instance *root;
+ root = get_root_instance();
+ printf("ROOT 0x%p\n", root);
+ return dm_dump(root);
+}
+
+int dm_dump(struct instance *dev)
+{
+ if (!dev)
+ return -EINVAL;
+ return display_succ(dev, "");
+}
+
+static int do_dm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct instance *root;
+
+ if (argc != 2)
+ return -EINVAL;
+ if (!strncmp(argv[1], "dump", 4))
+ return dm_dump_all();
+
+ if (!strncmp(argv[1], "remove", 6)) {
+ root = get_root_instance();
+ return driver_remove(root);
+ }
+
+ if (!strncmp(argv[1], "unbind", 6)) {
+ root = get_root_instance();
+ return driver_unbind(root);
+ }
+
+ return -EINVAL;
+}
+
+U_BOOT_CMD(
+ dm, 2, 1, do_dm,
+ "Driver model ops",
+ "\n"
+);
diff --git a/include/dm/debug.h b/include/dm/debug.h
new file mode 100644
index 000..df86113
--- /dev/null
+++ b/include/dm/debug.h
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2012
+ * Pavel Herrmann
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef _DM_DEBUG_H_
+#define _DM_DEBUG_H_ 1
+
+#include
+
+int dm_dump_all(void);
+int dm_dump(struct instance *i);
+
+#endif
--
1.7.10.4
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[U-Boot] [PATCH 5/7] dm: gpio: Add draft GPIO core and convert sandbox to use it
Signed-off-by: Marek Vasut
---
arch/sandbox/lib/board.c|6 +
drivers/gpio/Makefile |2 +
drivers/gpio/core.c | 365 +++
drivers/gpio/sandbox.c | 58 ++-
include/asm-generic/gpio.h | 19 +++
include/configs/sandbox.h |2 +
include/dm/core_numbering.h |1 +
7 files changed, 447 insertions(+), 6 deletions(-)
create mode 100644 drivers/gpio/core.c
diff --git a/arch/sandbox/lib/board.c b/arch/sandbox/lib/board.c
index b6b3768..c79cc62 100644
--- a/arch/sandbox/lib/board.c
+++ b/arch/sandbox/lib/board.c
@@ -239,6 +239,11 @@ void board_init_r(gd_t *id, ulong dest_addr)
.name = "demo_drv",
.platform_data = NULL
};
+ static const struct driver_info gs_info = {
+ .name = "gpio_sandbox",
+ .platform_data = NULL
+ };
+
struct instance *root = get_root_instance();
struct instance *demo1, *demo2, *demo3;
demo1 = driver_bind(root, &info);
@@ -248,6 +253,7 @@ void board_init_r(gd_t *id, ulong dest_addr)
demo2 = driver_bind(demo1, &info);
demo3 = driver_bind(demo2, &info);
driver_bind(demo2, &info);
+ driver_bind(root, &gs_info);
demo_hello(demo2);
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 4b99b85..1d3aa02 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -25,6 +25,8 @@ include $(TOPDIR)/config.mk
LIB:= $(obj)libgpio.o
+COBJS-$(CONFIG_DM) += core.o
+
COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o
COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
COBJS-$(CONFIG_MARVELL_GPIO) += mvgpio.o
diff --git a/drivers/gpio/core.c b/drivers/gpio/core.c
new file mode 100644
index 000..8fd83b5
--- /dev/null
+++ b/drivers/gpio/core.c
@@ -0,0 +1,365 @@
+#include
+#include
+#include
+#include
+#include
+
+/*
+ * The idea here is to have GPIOs numbered like this from user point of view:
+ *
+ * 32 24 2316 15 0
+ * [ GPIO block ID ] [ GPIO chip ID ] [ GPIO ID within the GPIO chip ]
+ *
+ */
+
+#define GPIO_TO_BLOCK_ID(x)(((x) >> 24) & 0xff)
+#define GPIO_TO_CHIP_ID(x) (((x) >> 16) & 0xff)
+#define GPIO_TO_CHIP_OFFSET(x) ((x) & 0x)
+
+struct gpio_core_entry {
+ struct list_headlist;
+ struct instance *instance;
+ struct dm_gpio_ops *ops;
+ int id;
+};
+
+/**
+ * gpio_to_entry() - Convert GPIO number to entry in the list
+ * gpio: The numeric representation of the GPIO
+ *
+ * Convert the GPIO number to an entry in the list of GPIOs
+ * or GPIO blocks registered with the GPIO controller. Returns
+ * entry on success, NULL on error.
+ */
+static struct gpio_core_entry *gpio_to_entry(unsigned gpio)
+{
+ uint8_t block = GPIO_TO_BLOCK_ID(gpio);
+ uint8_t chip = GPIO_TO_CHIP_ID(gpio);
+ uint8_t offset = GPIO_TO_CHIP_OFFSET(gpio);
+ struct core_instance *core = get_core_instance(CORE_GPIO);
+ struct gpio_core_entry *tmp, *ret = NULL;
+
+ list_for_each_entry(tmp, &core->succ, list) {
+ if (tmp->id != block)
+ continue;
+ if (tmp->ops->base != chip)
+ continue;
+ if (tmp->ops->ngpio < offset)
+ return NULL;
+ else {
+ ret = tmp;
+ break;
+ }
+ }
+
+ if (ret)
+ driver_activate(ret->instance);
+
+ return ret;
+}
+
+/**
+ * gpio_request() - [COMPAT] Request GPIO
+ * gpio: GPIO number
+ * label: Name for the requested GPIO
+ *
+ * This function implements the API that's compatible with current
+ * GPIO API used in U-Boot. The request is forwarded to particular
+ * GPIO driver. Returns 0 on success, negative value on error.
+ */
+int gpio_request(unsigned gpio, const char *label)
+{
+ struct gpio_core_entry *e = gpio_to_entry(gpio);
+ if (!e)
+ return -EINVAL;
+
+ return e->ops->gpio_request(gpio, label);
+}
+
+/**
+ * gpio_free() - [COMPAT] Relinquish GPIO
+ * gpio: GPIO number
+ *
+ * This function implements the API that's compatible with current
+ * GPIO API used in U-Boot. The request is forwarded to particular
+ * GPIO driver. Returns 0 on success, negative value on error.
+ */
+int gpio_free(unsigned gpio)
+{
+ struct gpio_core_entry *e = gpio_to_entry(gpio);
+ if (!e)
+ return -EINVAL;
+
+ return e->ops->gpio_free(gpio);
+}
+
+/**
+ * gpio_direction_input() - [COMPAT] Set GPIO direction to input
+ * gpio: GPIO number
+ *
+ * This function implements the API that's compatible with current
+ * GPIO API used in U-Boot. The request is forwarded to particular
+ * GPIO driver. Returns 0 on success, negative value on error.
+ */
+int gpio_direction_input
[U-Boot] [PATCH 2/7] dm: sandbox: Add necessary linker sections
Add linker sections necessary for driver model operation.
Signed-off-by: Marek Vasut
---
arch/sandbox/cpu/u-boot.lds | 35 ---
1 file changed, 32 insertions(+), 3 deletions(-)
diff --git a/arch/sandbox/cpu/u-boot.lds b/arch/sandbox/cpu/u-boot.lds
index 9960138..d83ee66 100644
--- a/arch/sandbox/cpu/u-boot.lds
+++ b/arch/sandbox/cpu/u-boot.lds
@@ -24,9 +24,38 @@
SECTIONS
{
- __u_boot_cmd_start = .;
- _u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_cmd : {
+ __u_boot_cmd_start = .;
+ *(SORT(.u_boot_cmd.*))
+ __u_boot_cmd_end = .;
+ }
+
+ .u_boot_driver : {
+ __u_boot_driver_start = .;
+ __u_boot_driver_generic_start = .;
+ *(SORT(.u_boot_driver.generic.*))
+ __u_boot_driver_generic_end = .;
+
+ /*
+* PCI and USB drivers have special needs,
+* hence the separate lists
+*/
+ __u_boot_driver_pci_start = .;
+ *(SORT(.u_boot_driver.pci.*))
+ __u_boot_driver_pci_end = .;
+
+ __u_boot_driver_usb_start = .;
+ *(SORT(.u_boot_driver.usb.*))
+ __u_boot_driver_usb_end = .;
+
+ __u_boot_driver_end = .;
+ }
+
+ .u_boot_core : {
+ __u_boot_core_start = .;
+ *(SORT(.u_boot_core.*))
+ __u_boot_core_end = .;
+ }
__u_boot_sandbox_option_start = .;
_u_boot_sandbox_getopt : { *(.u_boot_sandbox_getopt) }
--
1.7.10.4
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[U-Boot] [PATCH 4/7] dm: REMOVE: sandbox binding experiment
Signed-off-by: Marek Vasut
---
arch/sandbox/lib/board.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/sandbox/lib/board.c b/arch/sandbox/lib/board.c
index c173bf9..b6b3768 100644
--- a/arch/sandbox/lib/board.c
+++ b/arch/sandbox/lib/board.c
@@ -47,6 +47,8 @@
#include
+#include
+
DECLARE_GLOBAL_DATA_PTR;
static gd_t gd_mem;
@@ -232,6 +234,23 @@ void board_init_r(gd_t *id, ulong dest_addr)
mem_malloc_init((ulong)gd->ram_buf + gd->ram_size - TOTAL_MALLOC_LEN,
TOTAL_MALLOC_LEN);
+ dm_init();
+ static const struct driver_info info = {
+ .name = "demo_drv",
+ .platform_data = NULL
+ };
+ struct instance *root = get_root_instance();
+ struct instance *demo1, *demo2, *demo3;
+ demo1 = driver_bind(root, &info);
+ driver_bind(root, &info);
+ driver_bind(demo1, &info);
+ driver_bind(demo1, &info);
+ demo2 = driver_bind(demo1, &info);
+ demo3 = driver_bind(demo2, &info);
+ driver_bind(demo2, &info);
+
+ demo_hello(demo2);
+
/* initialize environment */
env_relocate();
--
1.7.10.4
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[U-Boot] [PATCH 0/7] [RFC] Driver model, take 1
I'm submitting hereby the initial code for the driver model. This is a RFC patch, please give it a spin and scream :-) The GPIO api should now use the new approach on the sandbox target. There's also "dm" command, that allows dumping the driver tree. Marek Vasut (5): dm: sandbox: Add necessary linker sections dm: sandbox: Add necessary GD sections dm: REMOVE: sandbox binding experiment dm: gpio: Add draft GPIO core and convert sandbox to use it dm: Add "dm dump" command Pavel Herrmann (2): dm: Add skeleton support for cores and drivers dm: add dummy demo driver and core Makefile |3 + arch/sandbox/cpu/u-boot.lds| 35 ++- arch/sandbox/include/asm/global_data.h |9 + arch/sandbox/lib/board.c | 25 ++ common/dm/Makefile | 40 common/dm/core.c | 150 common/dm/debug.c | 106 + common/dm/driver.c | 404 common/dm/lists.c | 138 +++ common/dm/root.c | 103 common/dm/tree.c | 164 + common/dm/tree.h | 31 +++ drivers/demo/Makefile | 42 drivers/demo/core.c| 236 +++ drivers/demo/demo.c| 67 ++ drivers/gpio/Makefile |2 + drivers/gpio/core.c| 365 + drivers/gpio/sandbox.c | 58 - include/asm-generic/gpio.h | 19 ++ include/configs/sandbox.h |2 + include/dm/core_numbering.h| 35 +++ include/dm/debug.h | 33 +++ include/dm/demo.h | 37 +++ include/dm/manager.h | 57 + include/dm/options.h | 46 include/dm/structures.h| 154 26 files changed, 2352 insertions(+), 9 deletions(-) create mode 100644 common/dm/Makefile create mode 100644 common/dm/core.c create mode 100644 common/dm/debug.c create mode 100644 common/dm/driver.c create mode 100644 common/dm/lists.c create mode 100644 common/dm/root.c create mode 100644 common/dm/tree.c create mode 100644 common/dm/tree.h create mode 100644 drivers/demo/Makefile create mode 100644 drivers/demo/core.c create mode 100644 drivers/demo/demo.c create mode 100644 drivers/gpio/core.c create mode 100644 include/dm/core_numbering.h create mode 100644 include/dm/debug.h create mode 100644 include/dm/demo.h create mode 100644 include/dm/manager.h create mode 100644 include/dm/options.h create mode 100644 include/dm/structures.h -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/7] dm: sandbox: Add necessary GD sections
Add GD sections necessary for driver model operation.
Signed-off-by: Marek Vasut
---
arch/sandbox/include/asm/global_data.h |9 +
1 file changed, 9 insertions(+)
diff --git a/arch/sandbox/include/asm/global_data.h
b/arch/sandbox/include/asm/global_data.h
index 581fd2f..77c7508 100644
--- a/arch/sandbox/include/asm/global_data.h
+++ b/arch/sandbox/include/asm/global_data.h
@@ -25,6 +25,9 @@
#ifndef__ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
+
+#include
+
/*
* The following data structure is placed in some memory wich is
* available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
@@ -43,6 +46,12 @@ typedef struct global_data {
unsigned long fb_base;/* base address of frame buffer */
u8 *ram_buf; /* emulated RAM buffer */
phys_size_t ram_size; /* RAM size */
+
+#ifdef CONFIG_DM
+ struct instance *dm_root; /* Root instance for Driver Model */
+ struct list_head core_root; /* Head of core tree */
+#endif
+
const void *fdt_blob; /* Our device tree, NULL if none */
void**jt; /* jump table */
charenv_buf[32];/* buffer for getenv() before reloc. */
--
1.7.10.4
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Re: [U-Boot] [PATCH v2 16/18] da850_am18xxevm: Add README.da850_am18xxevm
On 08/20/2012 10:09 PM, Prabhakar Lad wrote: > Hi Tom, > > Thanks for the patch. > > On Monday 20 August 2012 10:15 PM, Tom Rini wrote: >> Add a board-specific README that documents how to write u-boot.ais to >> the SPI found on this board. >> >> Changes-series: 2 >> - Add >> >> Signed-off-by: Tom Rini >> --- >> >> board/davinci/da8xxevm/README.da850_am18xxevm | 53 >> + >> 1 file changed, 53 insertions(+) >> create mode 100644 board/davinci/da8xxevm/README.da850_am18xxevm >> >> diff --git a/board/davinci/da8xxevm/README.da850_am18xxevm >> b/board/davinci/da8xxevm/README.da850_am18xxevm >> new file mode 100644 >> index 000..382b718 >> --- /dev/null >> +++ b/board/davinci/da8xxevm/README.da850_am18xxevm >> @@ -0,0 +1,53 @@ >> +Summary >> +=== >> +The README is for the boot procedure used for the LogicPD AM1808 EVM. >> + >> +The board is booted in three stages. The initial bootloader which executes >> +upon reset is the Rom Boot Loader(RBL) which sits in the internal ROM. The >> +RBL initialises the memory and the SPI controller and reads the AIS image >> +starting at block 0. This image can contain both the SPL and U-Boot >> +binaries. >> + >> +AIS is an image format defined by TI for the images that are to be >> +loaded to memory by the RBL. The image is divided into a series of >> +sections and the image's entry point is specified. Each section comes >> +with meta data like the target address the section is to be copied to >> +and the size of the section, which is used by the RBL to load the >> +image. At the end of the image the RBL jumps to the image entry >> +point. >> + >> +The secondary stage bootloader(spl) which is loaded by the RBL then loads >> +the u-boot from a predefined location in SPI to DDR and jumps to the u-boot >> +entry point. >> + >> + >> +Compilation >> +=== >> +To build a SPI-bootable image, run 'make da850_am18xxevm'. This will build >> +the u-boot.ais file that needs to be written to SPI flash. >> + >> + >> +Flashing the images to Nand >> +=== >> +The AIS image can be written to SPI flash using the following commands. >> +Assuming that the network is configured and enabled and the u-boot.ais file >> +is tftp'able. >> + >> +U-Boot > sf probe 0 >> +U-Boot > sf erase 0 +32 >> +U-Boot > tftp u-boot.ais >> +U-Boot > sf write c070 0 $filesize >> + > Is this procedure to be done in Nand boot mode ? This board, as far as I know (which isn't much) doesn't use NAND, just SPI. The USE_NAND section of da850evm.h doesn't seem reachable today at least. -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/2] PXA25x: USB ethernet driver
Dear Łukasz Dałek, > I've moved cpu revision detection to arch/arm/cpu/pxa as you suggest. > Cleaned ethernet driver. Soon I would also send patches for > drivers/usb/gadget/ether.c to work correctly with this pxa driver. I didn't sleep today ... I'll review it tomorrow. > Łukasz Dałek (2): > pxa: Add some stuff to examine cpu model and rev > pxa25x: Add USB ethernet gadget > > arch/arm/cpu/pxa/cpuinfo.c | 11 +- > arch/arm/include/asm/arch-pxa/pxa.h | 13 + > drivers/usb/gadget/Makefile |1 + > drivers/usb/gadget/pxa25x_udc.c | 2059 > +++ drivers/usb/gadget/pxa25x_udc.h | > 168 +++ > 5 files changed, 2250 insertions(+), 2 deletions(-) > create mode 100644 drivers/usb/gadget/pxa25x_udc.c > create mode 100644 drivers/usb/gadget/pxa25x_udc.h Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Configure U-boot to output to LCD on imx28evk board
On Tue, Aug 21, 2012 at 11:35 AM, Bill wrote: > Thanks. I'm a bit fuzzy on Linux graphics. So you mention that this is > possible - but what criteria? > Does this mean all I need to do is configure U-boot? Or you mention that > there is no mxs framebuffer support. Is there a way around this in u-boot? > Or can I add a patch for mxs framebuffer support in U-boot? Yes, you need to create a patch to add mxs framebuffer support in U-boot. You can look at the linux kernel as a reference (drivers/video/mxsfb.c) and port it into U-boot. There are other i.mx processors (mx31, mx51, mx53) that do support framebuffer in U-boot. You can look at drivers/video/mxc_ipuv3_fb.c in U-boot for a reference for mx51/mx53 implementation. The LCD controller on mxs is different so that is why you will need to create a new driver for it. Regards, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Configure U-boot to output to LCD on imx28evk board
Thanks. I'm a bit fuzzy on Linux graphics. So you mention that this is possible - but what criteria? Does this mean all I need to do is configure U-boot? Or you mention that there is no mxs framebuffer support. Is there a way around this in u-boot? Or can I add a patch for mxs framebuffer support in U-boot? On 8/21/2012 9:25 AM, Fabio Estevam wrote: Hi Bill, On Tue, Aug 21, 2012 at 11:20 AM, Bill wrote: All, Is it possible to configure u-boot output (console) to the LCD on the imx28evk board? I see in the u-boot configuration options switches for LCD support: CONFIG_LCD. However, I don't see an LCD display that matches the one on the imx28evk? Yes, this is possible, but currently there is no mxs framebuffer support in U-boot. Regards, Fabio Estevam -- William (Bill) L. Sousan, Ph.D. (w) 402.331.4977 ext. 4002 bsou...@techsi.com Technical Support Inc. 11253 John Galt Blvd Omaha, NE 68137 www.techsi.com 8(a) SDB Certified, ISO 9001:2008 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Configure U-boot to output to LCD on imx28evk board
Hi Bill, On Tue, Aug 21, 2012 at 11:20 AM, Bill wrote: > All, > > Is it possible to configure u-boot output (console) to the LCD on the > imx28evk board? I see in the u-boot configuration options switches for LCD > support: CONFIG_LCD. However, I don't see an LCD display that matches the > one on the imx28evk? Yes, this is possible, but currently there is no mxs framebuffer support in U-boot. Regards, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Configure U-boot to output to LCD on imx28evk board
All, Is it possible to configure u-boot output (console) to the LCD on the imx28evk board? I see in the u-boot configuration options switches for LCD support: CONFIG_LCD. However, I don't see an LCD display that matches the one on the imx28evk? Thanks, Bill ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] pxa: Add some stuff to examine cpu model and rev
Signed-off-by: Łukasz Dałek
---
arch/arm/cpu/pxa/cpuinfo.c | 11 +--
arch/arm/include/asm/arch-pxa/pxa.h | 13 +
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/pxa/cpuinfo.c b/arch/arm/cpu/pxa/cpuinfo.c
index f1cdd40..bab6340 100644
--- a/arch/arm/cpu/pxa/cpuinfo.c
+++ b/arch/arm/cpu/pxa/cpuinfo.c
@@ -24,9 +24,11 @@
#include
#include
-#defineCPU_MASK_PXA_REVID 0x00f
+#defineCPU_MASK_PXA_PRODID 0x03f0
+#defineCPU_MASK_PXA_REVID 0x000f
+
+#defineCPU_MASK_PRODREV(CPU_MASK_PXA_PRODID |
CPU_MASK_PXA_REVID)
-#defineCPU_MASK_PXA_PRODID 0x3f0
#defineCPU_VALUE_PXA25X0x100
#defineCPU_VALUE_PXA27X0x110
@@ -51,6 +53,11 @@ int cpu_is_pxa27x(void)
return id == CPU_VALUE_PXA27X;
}
+uint32_t pxa_get_cpu_revision(void)
+{
+ return pxa_get_cpuid() & CPU_MASK_PRODREV;
+}
+
#ifdef CONFIG_DISPLAY_CPUINFO
static const char *pxa25x_get_revision(void)
{
diff --git a/arch/arm/include/asm/arch-pxa/pxa.h
b/arch/arm/include/asm/arch-pxa/pxa.h
index 49c6552..b67d8f2 100644
--- a/arch/arm/include/asm/arch-pxa/pxa.h
+++ b/arch/arm/include/asm/arch-pxa/pxa.h
@@ -22,8 +22,21 @@
#ifndef__PXA_H__
#define__PXA_H__
+#define PXA255_A0 0x0106
+#define PXA250_C0 0x0105
+#define PXA250_B2 0x0104
+#define PXA250_B1 0x0103
+#define PXA250_B0 0x0102
+#define PXA250_A1 0x0101
+#define PXA250_A0 0x0100
+#define PXA210_C0 0x0125
+#define PXA210_B2 0x0124
+#define PXA210_B1 0x0123
+#define PXA210_B0 0x0122
+
int cpu_is_pxa25x(void);
int cpu_is_pxa27x(void);
+uint32_t pxa_get_cpu_revision(void);
void pxa2xx_dram_init(void);
#endif /* __PXA_H__ */
--
1.7.8.6
___
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U-Boot@lists.denx.de
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[U-Boot] [PATCH 0/2] PXA25x: USB ethernet driver
I've moved cpu revision detection to arch/arm/cpu/pxa as you suggest. Cleaned ethernet driver. Soon I would also send patches for drivers/usb/gadget/ether.c to work correctly with this pxa driver. Łukasz Dałek (2): pxa: Add some stuff to examine cpu model and rev pxa25x: Add USB ethernet gadget arch/arm/cpu/pxa/cpuinfo.c | 11 +- arch/arm/include/asm/arch-pxa/pxa.h | 13 + drivers/usb/gadget/Makefile |1 + drivers/usb/gadget/pxa25x_udc.c | 2059 +++ drivers/usb/gadget/pxa25x_udc.h | 168 +++ 5 files changed, 2250 insertions(+), 2 deletions(-) create mode 100644 drivers/usb/gadget/pxa25x_udc.c create mode 100644 drivers/usb/gadget/pxa25x_udc.h -- 1.7.8.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/5] Add fsl_iim driver
On 21/08/2012 14:56, Benoît Thébaudeau wrote: > Hi Stefano, > Hi, >> The address depends on the SOC, and is not a board configuration >> option. >> Should we not use IIM_BASE_ADDR ? > > CONFIG_SYS_FSL_IIM_ADDR is supposed to be a board configuration option, just > like CONFIG_SYS_I2C_BASE. Ok, but the reason for CONFIG_SYS_I2C_BASE is that a SOC have multiple I2C controller, but u-boot supports only one of them (up now). Setting CONFIG_SYS_I2C_BASE we implicitely tell u-boot which controller is active. There is not multiple iim in the SOCs. For this reason I thought it is not a configuration option. > This makes things easier since on MPC this address > comes from a struct (&((immap_t *) CONFIG_SYS_IMMR)->iim). Or we could define > a > FSL_IIM_BASE_ADDR in all supported register definition files, but that would > mean including conditionally these files in fsl_iim.c. I understood the point. Ok, let's see which is the Anatolji's opinion for the PowerPC side. If he thinks it is ok, we can leave it with CONFIG_SYS_FSL_IIM_ADDR. Regards, Stefano -- = DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch v3 2/2] net: asix: add support for AX88772B
There are multiple changes needed to make AX88772B work:
1. add vendor and product ID (trivial)
2. We need to read out the MAC address from the EEPROM and write
it into the NodeID register manually.
3. The packet length check has to be adjusted, as all ASIX chips
only use 11 bits to indicate the length. AX88772B uses the other
bits to indicate unrelated things, which cause the check to fail.
This fix is based on a fix for the Linux kernel by Marek Vasut.
Linux upstream commit: bca0beb9363f8487ac902931a50eb00180a2d14a
4. AX88772B provides several bulk endpoints. Only the first
IN/OUT endpoints work in the default configuration. So stop
enumeration after we found them to avoid overwriting the
endpoint config with a non-working one.
This was tested to work on a Colibri T20 board.
Patch is based on u-boot-net/next.
v2:
- split out eeprom mac load into separate function
- add flags to driver to get a clean way to enable workarounds
or special functions
v3:
- remove useless memsets
- use MAC printing macro
- while touching the asix_dongles array constify it
- provide a write_hwaddr() function for all chipsets that
support this.
- unify MAC handling in one function
Signed-off-by: Lucas Stach
const
---
drivers/usb/eth/asix.c | 137 +
1 Datei geändert, 104 Zeilen hinzugefügt(+), 33 Zeilen entfernt(-)
diff --git a/drivers/usb/eth/asix.c b/drivers/usb/eth/asix.c
index 8fb7fc8..7d9e9a2 100644
--- a/drivers/usb/eth/asix.c
+++ b/drivers/usb/eth/asix.c
@@ -23,6 +23,7 @@
#include
#include
#include "usb_ether.h"
+#include "malloc.h"
/* ASIX AX8817X based USB 2.0 Ethernet Devices */
@@ -31,10 +32,12 @@
#define AX_CMD_READ_MII_REG0x07
#define AX_CMD_WRITE_MII_REG 0x08
#define AX_CMD_SET_HW_MII 0x0a
+#define AX_CMD_READ_EEPROM 0x0b
#define AX_CMD_READ_RX_CTL 0x0f
#define AX_CMD_WRITE_RX_CTL0x10
#define AX_CMD_WRITE_IPG0 0x12
#define AX_CMD_READ_NODE_ID0x13
+#define AX_CMD_WRITE_NODE_ID 0x14
#define AX_CMD_READ_PHY_ID 0x19
#define AX_CMD_WRITE_MEDIUM_MODE 0x1b
#define AX_CMD_WRITE_GPIOS 0x1f
@@ -97,9 +100,21 @@
#define AX_RX_URB_SIZE 2048
#define PHY_CONNECT_TIMEOUT 5000
+/* asix_flags defines */
+#define FLAG_NONE 0
+#define FLAG_TYPE_AX88172 (1U << 0)
+#define FLAG_TYPE_AX88772 (1U << 1)
+#define FLAG_TYPE_AX88772B (1U << 2)
+#define FLAG_EEPROM_MAC(1U << 3) /* initial mac address in
eeprom */
+
/* local vars */
static int curr_eth_dev; /* index for name of next device detected */
+/* driver private */
+struct asix_private {
+ int flags;
+};
+
/*
* Asix infrastructure commands
*/
@@ -284,6 +299,21 @@ static int asix_write_gpio(struct ueth_data *dev, u16
value, int sleep)
return ret;
}
+static int asix_write_hwaddr(struct eth_device *eth)
+{
+ struct ueth_data *dev = (struct ueth_data *)eth->priv;
+ int ret;
+ ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN);
+
+ memcpy(buf, eth->enetaddr, ETH_ALEN);
+
+ ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, buf);
+ if (ret < 0)
+ debug("Failed to set MAC address: %02x\n", ret);
+
+ return ret;
+}
+
/*
* mii commands
*/
@@ -310,13 +340,41 @@ static int mii_nway_restart(struct ueth_data *dev)
return r;
}
+static int asix_init_mac(struct eth_device *eth)
+{
+ struct ueth_data *dev = (struct ueth_data *)eth->priv;
+ struct asix_private *priv = (struct asix_private *)dev->dev_priv;
+ int i;
+ ALLOC_CACHE_ALIGN_BUFFER(unsigned char, ee_buf, 2);
+ ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN);
+
+ if (priv->flags & FLAG_EEPROM_MAC) {
+ for (i = 0; i < (ETH_ALEN >> 1); i++) {
+ if (asix_read_cmd(dev, AX_CMD_READ_EEPROM,
+ 0x04 + i, 0, 2, ee_buf) < 0) {
+ debug("Failed to read SROM address 04h.\n");
+ return -1;
+ }
+ memcpy((eth->enetaddr + i * 2), ee_buf, 2);
+ asix_write_hwaddr(eth);
+ }
+ } else {
+ if (asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN,
buf) < 0) {
+ debug("Failed to read MAC address.\n");
+ return -1;
+ }
+ memcpy(eth->enetaddr, buf, ETH_ALEN);
+ }
+
+ return 0;
+}
+
/*
* Asix callbacks
*/
static int asix_init(struct eth_device *eth, bd_t *bd)
{
int embd_phy;
- ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN);
u16 rx_ctl;
struct ueth_data*dev = (struct ueth_data *)eth->priv;
int timeout = 0;
@@ -360,16 +418,8 @@ static int asix_init(struct eth_device *eth, bd_t *bd)
[U-Boot] [Patch v3 1/2] net: introduce transparent driver private in ueth_data
Avoid clutter in ueth_data. Individual drivers should not mess
with structures belonging to the core like this.
Signed-off-by: Lucas Stach
---
drivers/usb/eth/smsc95xx.c | 48 --
include/usb_ether.h| 8 ++--
2 Dateien geändert, 36 Zeilen hinzugefügt(+), 20 Zeilen entfernt(-)
diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c
index c62a8c1..4bf2a16 100644
--- a/drivers/usb/eth/smsc95xx.c
+++ b/drivers/usb/eth/smsc95xx.c
@@ -25,6 +25,7 @@
#include
#include
#include "usb_ether.h"
+#include "malloc.h"
/* SMSC LAN95xx based USB 2.0 Ethernet Devices */
@@ -146,6 +147,12 @@
/* local vars */
static int curr_eth_dev; /* index for name of next device detected */
+/* driver private */
+struct smsc95xx_private {
+ size_t rx_urb_size; /* maximum USB URB size */
+ u32 mac_cr; /* MAC control register value */
+ int have_hwaddr; /* 1 if we have a hardware MAC address */
+};
/*
* Smsc95xx infrastructure commands
@@ -377,6 +384,7 @@ static int smsc95xx_init_mac_address(struct eth_device *eth,
static int smsc95xx_write_hwaddr(struct eth_device *eth)
{
struct ueth_data *dev = (struct ueth_data *)eth->priv;
+ struct smsc95xx_private *priv = dev->dev_priv;
u32 addr_lo = __get_unaligned_le32(ð->enetaddr[0]);
u32 addr_hi = __get_unaligned_le16(ð->enetaddr[4]);
int ret;
@@ -392,7 +400,7 @@ static int smsc95xx_write_hwaddr(struct eth_device *eth)
return ret;
debug("MAC %pM\n", eth->enetaddr);
- dev->have_hwaddr = 1;
+ priv->have_hwaddr = 1;
return 0;
}
@@ -425,19 +433,22 @@ static int smsc95xx_set_csums(struct ueth_data *dev,
static void smsc95xx_set_multicast(struct ueth_data *dev)
{
+ struct smsc95xx_private *priv = dev->dev_priv;
+
/* No multicast in u-boot */
- dev->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
+ priv->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
}
/* starts the TX path */
static void smsc95xx_start_tx_path(struct ueth_data *dev)
{
+ struct smsc95xx_private *priv = dev->dev_priv;
u32 reg_val;
/* Enable Tx at MAC */
- dev->mac_cr |= MAC_CR_TXEN_;
+ priv->mac_cr |= MAC_CR_TXEN_;
- smsc95xx_write_reg(dev, MAC_CR, dev->mac_cr);
+ smsc95xx_write_reg(dev, MAC_CR, priv->mac_cr);
/* Enable Tx at SCSRs */
reg_val = TX_CFG_ON_;
@@ -447,8 +458,10 @@ static void smsc95xx_start_tx_path(struct ueth_data *dev)
/* Starts the Receive path */
static void smsc95xx_start_rx_path(struct ueth_data *dev)
{
- dev->mac_cr |= MAC_CR_RXEN_;
- smsc95xx_write_reg(dev, MAC_CR, dev->mac_cr);
+ struct smsc95xx_private *priv = dev->dev_priv;
+
+ priv->mac_cr |= MAC_CR_RXEN_;
+ smsc95xx_write_reg(dev, MAC_CR, priv->mac_cr);
}
/*
@@ -462,6 +475,7 @@ static int smsc95xx_init(struct eth_device *eth, bd_t *bd)
u32 burst_cap;
int timeout;
struct ueth_data *dev = (struct ueth_data *)eth->priv;
+ struct smsc95xx_private *priv = (struct smsc95xx_private
*)dev->dev_priv;
#define TIMEOUT_RESOLUTION 50 /* ms */
int link_detected;
@@ -504,9 +518,9 @@ static int smsc95xx_init(struct eth_device *eth, bd_t *bd)
debug("timeout waiting for PHY Reset\n");
return -1;
}
- if (!dev->have_hwaddr && smsc95xx_init_mac_address(eth, dev) == 0)
- dev->have_hwaddr = 1;
- if (!dev->have_hwaddr) {
+ if (!priv->have_hwaddr && smsc95xx_init_mac_address(eth, dev) == 0)
+ priv->have_hwaddr = 1;
+ if (!priv->have_hwaddr) {
puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n");
return -1;
}
@@ -532,16 +546,16 @@ static int smsc95xx_init(struct eth_device *eth, bd_t *bd)
#ifdef TURBO_MODE
if (dev->pusb_dev->speed == USB_SPEED_HIGH) {
burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
- dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
+ priv->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
} else {
burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
- dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
+ priv->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
}
#else
burst_cap = 0;
- dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
+ priv->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
#endif
- debug("rx_urb_size=%ld\n", (ulong)dev->rx_urb_size);
+ debug("rx_urb_size=%ld\n", (ulong)priv->rx_urb_size);
ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap);
if (ret < 0)
@@ -606,7 +620,7 @@ static int smsc95xx_init(struct eth_device *eth, bd_t *bd)
if (ret < 0)
return ret;
- ret = smsc95xx_read_reg(dev, MAC_CR, &dev->mac_cr);
+ ret = smsc95xx_read_reg(dev, MAC_CR,
Re: [U-Boot] Seeking ARM development platform suggestions
On 08/21/2012 01:28:51 AM, Jorgen Lundman wrote: > At the moment though, my Mele is doing nothing (just waiting for wip > to > mature). I believe latest XBMC can play SD content. Current lack of > audio > support is a concern. I'm interested in using some of the Mele boxes instead of video cards with xdmx to get multihead video. Seems cheaper(ish), cooler and less noisy. Haven't tried it. Karl Free Software: "You don't pay back, you pay forward." -- Robert A. Heinlein ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Seeking ARM development platform suggestions
Hi Stefan, On 08/21/2012 05:30 PM, Stefan Roese wrote: [snip] >>> The general "mood" of the embedded dev community seems to be, to me, to move >>> away from these Companies, as the promised source releases has not been >>> sufficient. The current interest seems to be AM.logic's dualcore board. >>> (http://ao2.it/en/blog/2012/08/10/amlogic-aml8726-mx-linux-kernel-code-released) >> >> Seems to be more tablet oriented - can't find any 'media players' based on >> this > > There seem to be plenty. Check here for an overview: > > http://www.j1nx.nl/xbmc-amlogic-8726-m-pivos-xios-an-initial-investigation/ Thanks for the link. Looks like it uses the same GPU (Mali 400) as the AllWinner A10 The Geniatech Enjoy TV series looks pretty good, particularly the ATV1000: http://geniatech.com/pa/atv1000.asp I can get an ATV1000 for ~AU$135 with: - 800MHz Cortex A9 (not sure if it's the dual-core AML8726-MX or the single core AML8726-M1) - A remote - 2x external USB - A nicer looking case (going by the photos) - No SATA connection - Better FOSS support (?) I can get a Mele A2000 for ~AU$100 with: - 1GHz Cortex A8 Allwinner A10 - No Remote - 3x External USB - A not so nice looking case - SATA - Worse FOSS support (?) Oh the agony :( Considering it will probably be turned into a disk-less Linux workstation in a couple of years, I'm leaning towards the ATV1000 (no need for SATA) Thoughts? Regards, Graeme ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] mx35: Clean up lowlevel_init
Hi Stefano, Fabio, > On 20/08/2012 22:25, Fabio Estevam wrote: > > Hi Stefano, > > > > On Mon, Aug 20, 2012 at 4:42 PM, stefano babic > > wrote: > > > >> With the flea3 I have made some clean-up, making the > >> lowLevel_init.S > >> essential. Same changes were not reported back to the mx35pdk. I > >> am > >> going also to put in a common place the functions to setup the DDR > >> controller ( board_setup_sdram_bank() in the flea3 directory). > >> This > >> should allow to factorize some other code, reducing the > >> lowlevel_init.S. > > > > Maybe even better would be to convert the init from lowlevel_init.S > > into C code, like was done on mx31. > > > > It is much easier to debug/maintain C code then assemby. > > Yes, agree. > > Regards, > Stefano Yes, but we must also not forget the size constraints for SPLs. Best regards, Benoît ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/5] Add fsl_iim driver
Hi Stefano,
> > Add a fsl_iim driver common to i.MX and MPC.
> >
> > Signed-off-by: Benoît Thébaudeau
> > Cc: Wolfgang Denk
> > Cc: Stefano Babic
> > ---
> > .../drivers/misc/Makefile |1 +
> > /dev/null => u-boot-4d3c95f/drivers/misc/fsl_iim.c | 318
> >
> > 2 files changed, 319 insertions(+)
> > create mode 100644 u-boot-4d3c95f/drivers/misc/fsl_iim.c
> >
> > diff --git u-boot-4d3c95f.orig/drivers/misc/Makefile
> > u-boot-4d3c95f/drivers/misc/Makefile
> > index 271463c..31b8db8 100644
> > --- u-boot-4d3c95f.orig/drivers/misc/Makefile
> > +++ u-boot-4d3c95f/drivers/misc/Makefile
> > @@ -27,6 +27,7 @@ LIB := $(obj)libmisc.o
> >
> > COBJS-$(CONFIG_ALI152X) += ali512x.o
> > COBJS-$(CONFIG_DS4510) += ds4510.o
> > +COBJS-$(CONFIG_FSL_IIM) += fsl_iim.o
> > COBJS-$(CONFIG_FSL_LAW) += fsl_law.o
> > COBJS-$(CONFIG_GPIO_LED) += gpio_led.o
> > COBJS-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
> > diff --git u-boot-4d3c95f/drivers/misc/fsl_iim.c
> > u-boot-4d3c95f/drivers/misc/fsl_iim.c
> > new file mode 100644
> > index 000..1a3d5fc
> > --- /dev/null
> > +++ u-boot-4d3c95f/drivers/misc/fsl_iim.c
> > @@ -0,0 +1,318 @@
> > +/*
> > + * (C) Copyright 2009-2012 ADVANSEE
> > + * Benoît Thébaudeau
> > + *
> > + * Based on the mpc512x iim code:
> > + * Copyright 2008 Silicon Turnkey Express, Inc.
> > + * Martha Marx
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public
> > License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +/* FSL IIM-specific constants */
> > +#define STAT_BUSY 0x80
> > +#define STAT_PRGD 0x02
> > +#define STAT_SNSD 0x01
> > +
> > +#define STATM_PRGD_M 0x02
> > +#define STATM_SNSD_M 0x01
> > +
> > +#define ERR_PRGE 0x80
> > +#define ERR_WPE0x40
> > +#define ERR_OPE0x20
> > +#define ERR_RPE0x10
> > +#define ERR_WLRE 0x08
> > +#define ERR_SNSE 0x04
> > +#define ERR_PARITYE0x02
> > +
> > +#define EMASK_PRGE_M 0x80
> > +#define EMASK_WPE_M0x40
> > +#define EMASK_OPE_M0x20
> > +#define EMASK_RPE_M0x10
> > +#define EMASK_WLRE_M 0x08
> > +#define EMASK_SNSE_M 0x04
> > +#define EMASK_PARITYE_M0x02
> > +
> > +#define FCTL_DPC 0x80
> > +#define FCTL_PRG_LENGTH_MASK 0x70
> > +#define FCTL_ESNS_N0x08
> > +#define FCTL_ESNS_00x04
> > +#define FCTL_ESNS_10x02
> > +#define FCTL_PRG 0x01
> > +
> > +#define UA_A_BANK_MASK 0x38
> > +#define UA_A_ROWH_MASK 0x07
> > +
> > +#define LA_A_ROWL_MASK 0xf8
> > +#define LA_A_BIT_MASK 0x07
> > +
> > +#define PREV_PROD_REV_MASK 0xf8
> > +#define PREV_PROD_VT_MASK 0x07
> > +
> > +/* Select the correct accessors depending on endianness */
> > +#if __BYTE_ORDER == __LITTLE_ENDIAN
> > +#define iim_read32 in_le32
> > +#define iim_write32out_le32
> > +#define iim_clrsetbits32 clrsetbits_le32
> > +#define iim_clrbits32 clrbits_le32
> > +#define iim_setbits32 setbits_le32
> > +#elif __BYTE_ORDER == __BIG_ENDIAN
> > +#define iim_read32 in_be32
> > +#define iim_write32out_be32
> > +#define iim_clrsetbits32 clrsetbits_be32
> > +#define iim_clrbits32 clrbits_be32
> > +#define iim_setbits32 setbits_be32
> > +#else
> > +#error "Endianess is not defined: please fix to continue"
> > +#endif
> > +
> > +/* IIM control registers */
> > +struct fsl_iim {
> > + u32 stat;
> > + u32 statm;
> > + u32 err;
> > + u32 emask;
> > + u32 fctl;
> > + u32 ua;
> > + u32 la;
> > + u32 sdat;
> > + u32 prev;
> > + u32 srev;
> > + u32 prg_p;
> > + u32 scs[0x1f5];
> > + struct {
> > + u32 row[0x100];
> > + } bank[8];
> > +};
> > +
> > +int fuse_read_bit(u32 bank, u32 row, u32 bit, u32 *val)
> > +{
> > + int ret;
> > +
> > + if (bit >=
Re: [U-Boot] [PATCH] MX28: SPI: Limit the DMA transfer length
Dear Marek Vasut, > The upper limit for DMA transfer length on MX28 is 0x4000 bytes, > otherwise the DMA refuses to operate. > > Signed-off-by: Marek Vasut > Cc: Fabio Estevam > Cc: Otavio Salvador > Cc: Stefano Babic Hang on, I'll have a better patch Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] spiflash: at25: using common spi flash operation
Dear Bo Shen, On 20.08.2012 08:32, Bo Shen wrote: > Using common spi flash operation function to replace private operation > funtion > > This patch is based on http://patchwork.ozlabs.org/patch/177896/ > which has been merged by Mike frysinger Mike, do you think this is a fix? Should it go into 2012.10? Will you take it? > Signed-off-by: Bo Shen > --- > drivers/mtd/spi/atmel.c | 11 --- > 1 file changed, 8 insertions(+), 3 deletions(-) > > diff --git a/drivers/mtd/spi/atmel.c b/drivers/mtd/spi/atmel.c > index 89ebe9d..006f6d5 100644 > --- a/drivers/mtd/spi/atmel.c > +++ b/drivers/mtd/spi/atmel.c > @@ -518,13 +518,19 @@ struct spi_flash *spi_flash_probe_atmel(struct > spi_slave *spi, u8 *idcode) > asf->flash.erase = dataflash_erase_p2; > } > > + asf->flash.page_size = page_size; > + asf->flash.sector_size = page_size; > break; > > case DF_FAMILY_AT26F: > case DF_FAMILY_AT26DF: > asf->flash.read = spi_flash_cmd_read_fast; > - asf->flash.write = dataflash_write_p2; > - asf->flash.erase = dataflash_erase_p2; > + asf->flash.write = spi_flash_cmd_write_multi; > + asf->flash.erase = spi_flash_cmd_erase; > + asf->flash.page_size = page_size; > + asf->flash.sector_size = 4096; why do you take fixed value for sector size here? > + /* clear SPRL# bit for locked flash */ > + spi_flash_cmd_write_status(&asf->flash, 0); > break; > > default: > @@ -532,7 +538,6 @@ struct spi_flash *spi_flash_probe_atmel(struct spi_slave > *spi, u8 *idcode) > goto err; > } > > - asf->flash.sector_size = page_size; > asf->flash.size = page_size * params->pages_per_block > * params->blocks_per_sector > * params->nr_sectors; And here you correlate number of sectors with page size ... but we may have page_size != sector_size for some at26 devices, aren't we? Best regards Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/4] spi: atmel: add WDRBT bit to avoid receive overrun
Dear Bo Shen, On 20.08.2012 08:32, Bo Shen wrote: > The atmel at91sam9x5 series spi has feature to avoid receive overren > > Using the patch to enable it > > Signed-off-by: Bo Shen Acked-by: Andreas Bießmann Mike, will you take this patch? Best regards Andreas Bießmann > --- > drivers/spi/atmel_spi.c |3 +++ > drivers/spi/atmel_spi.h |1 + > 2 files changed, 4 insertions(+) > > diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c > index 83ef8e8..c7a51f7 100644 > --- a/drivers/spi/atmel_spi.c > +++ b/drivers/spi/atmel_spi.c > @@ -92,6 +92,9 @@ struct spi_slave *spi_setup_slave(unsigned int bus, > unsigned int cs, > as->slave.cs = cs; > as->regs = regs; > as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS > +#if defined(CONFIG_AT91SAM9X5) > + | ATMEL_SPI_MR_WDRBT > +#endif > | ATMEL_SPI_MR_PCS(~(1 << cs) & 0xf); > spi_writel(as, CSR(cs), csrx); > > diff --git a/drivers/spi/atmel_spi.h b/drivers/spi/atmel_spi.h > index 8b69a6d..057de9a 100644 > --- a/drivers/spi/atmel_spi.h > +++ b/drivers/spi/atmel_spi.h > @@ -26,6 +26,7 @@ > #define ATMEL_SPI_MR_PCSDEC (1 << 2) > #define ATMEL_SPI_MR_FDIV(1 << 3) > #define ATMEL_SPI_MR_MODFDIS (1 << 4) > +#define ATMEL_SPI_MR_WDRBT (1 << 5) > #define ATMEL_SPI_MR_LLB (1 << 7) > #define ATMEL_SPI_MR_PCS(x) (((x) & 15) << 16) > #define ATMEL_SPI_MR_DLYBCS(x) ((x) << 24) > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] atmel: at91sam9x5: fix name error for spi
Dear Bo Shen, On 20.08.2012 08:32, Bo Shen wrote: > Fix the name error > > Signed-off-by: Bo Shen > --- applied to u-boot-atmel/master, thanks! Best regards Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Take over the maintainer for sam9g10 and sam9m10g45
Dear Bo Shen, On 20.08.2012 11:01, Bo Shen wrote: > As the maintainer for at91sam9g10ek and at91sam9m10g45ek can not reach > any more. > > So I wish to take over the maintainer for sam9g10 and sam9m10g45 > > Signed-off-by: Bo Shen > --- applied to u-boot-atmel/master, thanks! Best regards Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 4/5] at91: 9x5: change SMC config timing that both works for PMECC & non-PMECC.
Dear Josh Wu, On 16.08.2012 07:05, Josh Wu wrote: > Signed-off-by: Josh Wu > --- > board/atmel/at91sam9x5ek/at91sam9x5ek.c | 12 ++-- > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c > b/board/atmel/at91sam9x5ek/at91sam9x5ek.c > index 17db0fd..8dc24ab 100644 > --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c > +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c > @@ -63,13 +63,13 @@ static void at91sam9x5ek_nand_hw_init(void) > writel(csa, &matrix->ebicsa); > > /* Configure SMC CS3 for NAND/SmartMedia */ > - writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | > - AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), > + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | > + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), > &smc->cs[3].setup); > - writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) | > - AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4), > + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | > + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6), > &smc->cs[3].pulse); > - writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), > + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6), > &smc->cs[3].cycle); > writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | > AT91_SMC_MODE_EXNW_DISABLE | > @@ -78,7 +78,7 @@ static void at91sam9x5ek_nand_hw_init(void) > #else /* CONFIG_SYS_NAND_DBW_8 */ > AT91_SMC_MODE_DBW_8 | > #endif > - AT91_SMC_MODE_TDF_CYCLE(3), > + AT91_SMC_MODE_TDF_CYCLE(1), > &smc->cs[3].mode); > > writel(1 << ATMEL_ID_PIOCD, &pmc->pcer); > are these changes required to get it working? As I understand your changes make the timing harder, which will result in less different NAND devices will be supported. The timing may be exactly the best for the currently used one, but maybe some change the device in future to a slightly slower one. Maybe I'm wrong so tell me please. But if not then I would like to have a Tested-by from one who owns this board (Bo?) Best regards Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 3/5] at91: atmel_nand: Update driver to support Programmable Multibit ECC controller
Hi, Andreas
On 8/17/2012 5:24 PM, Andreas Bießmann wrote:
Dear Josh Wu,
On 16.08.2012 07:05, Josh Wu wrote:
The Programmable Multibit ECC (PMECC) controller is a programmable binary
BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. This controller
can be used to support both SLC and MLC NAND Flash devices. It supports to
generate ECC to correct 2, 4, 8, 12 or 24 bits of error per sector of data.
To use PMECC in this driver, the user needs to set the PMECC correction
capability, the sector size and ROM lookup table offsets in board config file.
This driver is ported from Linux kernel atmel_nand PMECC patch. The main
difference
is in this version it uses registers structure access hardware instead of using
macros.
It is tested in 9x5 serial boards.
Signed-off-by: Josh Wu
---
Changes since v1:
Change 'ecc' array's type from u32 to u8 in structure pmecc_regs (u32 ecc[11]
-> u8 ecc[44]). That will make PMECC write correctly.
enable 4k-page nand flash pmecc support.
fix coding style errors and warnings.
changed lookup table variable name which sounds correct.
drivers/mtd/nand/atmel_nand.c | 654 -
drivers/mtd/nand/atmel_nand_ecc.h | 111 +++
2 files changed, 763 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 9dc003e..784370c 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -5,6 +5,9 @@
*
* (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
*
+ * Add Programmable Multibit ECC support for various AT91 SoC
+ * (C) Copyright 2012 ATMEL, Hong Xu
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -41,6 +44,648 @@
#include "atmel_nand_ecc.h" /* Hardware ECC registers */
+static int chip_nr;
+
+#ifdef CONFIG_ATMEL_NAND_HW_PMECC
+
+struct atmel_nand_host {
+ struct pmecc_regs __iomem *pmecc;
+ struct pmecc_errloc_regs __iomem *pmerrloc;
+ void __iomem*pmecc_rom_base;
+
+ u8 pmecc_corr_cap;
+ u16 pmecc_sector_size;
+ u32 pmecc_index_table_offset;
+
+ int pmecc_bytes_per_sector;
+ int pmecc_sector_number;
+ int pmecc_degree; /* Degree of remainders */
+ int pmecc_cw_len; /* Length of codeword */
+
+ /* lookup table for alpha_to and index_of */
+ void __iomem*pmecc_alpha_to;
+ void __iomem*pmecc_index_of;
+
+ /* data for pmecc computation */
+ int16_t pmecc_smu[(CONFIG_PMECC_CAP + 2) * (2 * CONFIG_PMECC_CAP + 1)];
+ int16_t pmecc_partial_syn[2 * CONFIG_PMECC_CAP + 1];
+ int16_t pmecc_si[2 * CONFIG_PMECC_CAP + 1];
+ int16_t pmecc_lmu[CONFIG_PMECC_CAP + 1]; /* polynomal order */
+ int pmecc_mu[CONFIG_PMECC_CAP + 1];
+ int pmecc_dmu[CONFIG_PMECC_CAP + 1];
+ int pmecc_delta[CONFIG_PMECC_CAP + 1];
can you please add some README entry describing these new config parameters?
Namely CONFIG_ATMEL_NAND_HW_PMECC, CONFIG_PMECC_CAP,
CONFIG_PMECC_SECTOR_SIZE (can't this be derived from some already
available NAND information?) and CONFIG_PMECC_INDEX_TABLE_OFFSET.
OK, I will add a README file to explain all the parameters.
this CONFIG_PMECC_SECTOR_SIZE means how many bytes to generate out PMECC
code. It only can be 512 and 1024.
So for a nand chip whose page size is 2048, if CONFIG_PMECC_SECTOR_SIZE
is set as 512, then PMECC will generate PMECC code for each 512 bytes.
I think it cannot be derived from nand information.
+};
+
+static struct atmel_nand_host pmecc_host;
+static struct nand_ecclayout atmel_pmecc_oobinfo;
+
+/*
+ * Return number of ecc bytes per sector according to sector size and
+ * correction capability
+ *
+ * Following table shows what at91 PMECC supported:
+ * Correction Capability Sector_512_bytesSector_1024_bytes
+ * = =
+ *2-bits 4-bytes 4-bytes
+ *4-bits 7-bytes 7-bytes
+ *8-bits13-bytes 14-bytes
+ * 12-bits20-bytes 21-bytes
+ * 24-bits39-bytes 42-bytes
+ */
+static int pmecc_get_ecc_bytes(int cap, int sector_size)
+{
+ int m = 12 + sector_size / 512;
+ return (m * cap + 7) / 8;
+}
+
+static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
+ int oobsize, int ecc_len)
+{
+ int i;
+
+ layout->eccbytes = ecc_len;
+
+ /* ECC will occupy the last ecc_len bytes continuously */
+ for (i = 0; i < ecc_len; i++)
+ layout->eccpos[i] = oobsize - ecc_len + i;
+
+ layout->oobfree[0].offset = 2;
+ layout->oobfree[0].length =
+ oob
Re: [U-Boot] [PATCH 3/5] Add fuse API and commands
Hi Stefano,
> > This can be useful for fuse-like hardware, OTP SoC options, etc.
> >
> > Signed-off-by: Benoît Thébaudeau
> > Cc: Wolfgang Denk
> > Cc: Stefano Babic
> > ---
>
> CC to Anatolji, he knows very well the MPC5121 that has currently
> support of fuses.
>
> > {u-boot-4d3c95f.orig => u-boot-4d3c95f}/README |1 +
> > .../common/Makefile|1 +
> > /dev/null => u-boot-4d3c95f/common/cmd_fuse.c | 182
> >
> > .../include/config_cmd_all.h |1 +
> > /dev/null => u-boot-4d3c95f/include/fuse.h | 49 ++
> > 5 files changed, 234 insertions(+)
> > create mode 100644 u-boot-4d3c95f/common/cmd_fuse.c
> > create mode 100644 u-boot-4d3c95f/include/fuse.h
> >
> > diff --git u-boot-4d3c95f.orig/README u-boot-4d3c95f/README
> > index fb9d904..c40fd34 100644
> > --- u-boot-4d3c95f.orig/README
> > +++ u-boot-4d3c95f/README
> > @@ -780,6 +780,7 @@ The following options need to be configured:
> > CONFIG_CMD_FDOS * Dos diskette Support
> > CONFIG_CMD_FLASH flinfo, erase, protect
> > CONFIG_CMD_FPGA FPGA device initialization support
> > + CONFIG_CMD_FUSE Device fuse support
> > CONFIG_CMD_GO * the 'go' command (exec code)
> > CONFIG_CMD_GREPENV * search environment
> > CONFIG_CMD_HWFLOW * RTS/CTS hw flow control
>
> Agree in this split: we have a general fuse command and each SOC /
> SOC
> family can add its own implementation.
>
> > +static int do_fuse(cmd_tbl_t *cmdtp, int flag, int argc, char
> > *const argv[])
> > +{
> > + u32 bank, row, bit, cnt, val;
> > + int ret, i;
> > +
> > + if (argc < 4 || strtou32(argv[2], 0, &bank) ||
> > + strtou32(argv[3], 0, &row))
> > + return CMD_RET_USAGE;
> > +
> > + if (!strcmp(argv[1], "read.bit")) {
> > + if (argc != 5 || strtou32(argv[4], 0, &bit))
> > + return CMD_RET_USAGE;
> > +
> > + printf("Reading bank %u row 0x%.8x bit %u: ", bank, row, bit);
> > + ret = fuse_read_bit(bank, row, bit, &val);
> > + if (ret)
> > + goto err;
> > +
> > + printf("%u\n", val);
> > + } else if (!strcmp(argv[1], "read.row")) {
> > + if (argc == 4)
> > + cnt = 1;
> > + else if (argc != 5 || strtou32(argv[4], 0, &cnt))
> > + return CMD_RET_USAGE;
> > +
> > + printf("Reading bank %u:\n", bank);
> > + for (i = 0; i < cnt; i++, row++) {
> > + if (!(i % 4))
> > + printf("\nRow 0x%.8x:", row);
> > +
> > + ret = fuse_read_row(bank, row, &val);
> > + if (ret)
> > + goto err;
> > +
> > + printf(" %.8x", val);
> > + }
> > + putc('\n');
> > + } else if (!strcmp(argv[1], "sense.bit")) {
> > + if (argc != 5 || strtou32(argv[4], 0, &bit))
> > + return CMD_RET_USAGE;
> > +
> > + printf("Sensing bank %u row 0x%.8x bit %u: ", bank, row, bit);
>
> Each command sends this output to the console. I am thinking about if
> instead of printf() we shoud use debug()
It's only a preamble to the result string. It's useful as feedback to the user
to confirm addresses and values (hex or not, etc.). There is also this kind of
indication for some existing commands, like md that confirms addresses. IMHO,
it's better as printf() than as debug(), all the more fuse stuff is sensible.
> > +U_BOOT_CMD(
> > + fuse, CONFIG_SYS_MAXARGS, 0, do_fuse,
> > + "Fuse sub-system",
> > +"read.bit- read a fuse bit\n"
> > + "fuse read.row [] - read 1 or 'cnt' fuse
> > rows,\n"
> > + "starting at 'row'\n"
> > + "fuse sense.bit- sense a fuse bit\n"
> > + "fuse sense.row [] - sense 1 or 'cnt' fuse
> > rows,\n"
> > + "starting at 'row'\n"
> > + "fuse prog.bit- program a fuse bit
> > (PERMANENT)\n"
> > + "fuse prog.row[...] - program 1
> > or\n"
> > + "several fuse rows, starting at 'row' (PERMANENT)\n"
> > + "fuse ovride.bit - override a fuse
> > bit\n"
> > + "fuse ovride.row[...] - override 1
> > or\n"
> > + "several fuse rows, starting at 'row'"
> > +);
>
> General question: why do we need the "bit" interface ? I have thought
> it
> is enough the read row / prog row interface (even if there is a bit
> programming).
For prog, it corresponds to the hardware API (at least on FSL IIM). It is also a
matter of safety. Fuse operations are sensible, irreversible and operate on
single bits, so it is less error prone for users to concentrate on the bit that
they want to program.
For read/sense/override, it is mostly for API consistency with prog.
For all these commands, this is also useful to easily automate accesses to fuse
bits from command
Re: [U-Boot] [PATCH 6/9] EXYNOS: Add pinmux for I2S
hi,
On 14 August 2012 11:15, Rajeshwari Shinde wrote:
> This patch adds pinmux support for I2S1
>
> Signed-off-by: Rajeshwari Shinde
> ---
> arch/arm/cpu/armv7/exynos/pinmux.c| 12
> arch/arm/include/asm/arch-exynos/periph.h |1 +
> 2 files changed, 13 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
> b/arch/arm/cpu/armv7/exynos/pinmux.c
> index 13f75e0..ba25f6c 100644
> --- a/arch/arm/cpu/armv7/exynos/pinmux.c
> +++ b/arch/arm/cpu/armv7/exynos/pinmux.c
> @@ -273,6 +273,15 @@ void exynos5_spi_config(int peripheral)
> }
> }
>
> +void exynos5_i2s_config(int peripheral)
make it static.
> +{
> + int i;
> + struct exynos5_gpio_part1 *gpio1 =
> + (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
> + for (i = 0; i < 5; i++)
> + s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
> +}
> +
> static int exynos5_pinmux_config(int peripheral, int flags)
> {
> switch (peripheral) {
> @@ -307,6 +316,9 @@ static int exynos5_pinmux_config(int peripheral, int
> flags)
> case PERIPH_ID_SPI4:
> exynos5_spi_config(peripheral);
> break;
> + case PERIPH_ID_I2S1:
> + exynos5_i2s_config(peripheral);
> + break;
> default:
> debug("%s: invalid peripheral %d", __func__, peripheral);
> return -1;
> diff --git a/arch/arm/include/asm/arch-exynos/periph.h
> b/arch/arm/include/asm/arch-exynos/periph.h
> index dafc3f3..404e5db 100644
> --- a/arch/arm/include/asm/arch-exynos/periph.h
> +++ b/arch/arm/include/asm/arch-exynos/periph.h
> @@ -38,6 +38,7 @@ enum periph_id {
> PERIPH_ID_I2C5,
> PERIPH_ID_I2C6,
> PERIPH_ID_I2C7,
> + PERIPH_ID_I2S1,
> PERIPH_ID_SDMMC0,
> PERIPH_ID_SDMMC1,
> PERIPH_ID_SDMMC2,
> --
> 1.7.4.4
>
--
with warm regards,
Chander Kashyap
___
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Re: [U-Boot] [PATCH 9/9] EXYNOS5: Enable Sound
hi Rajeshwari, On 14 August 2012 11:15, Rajeshwari Shinde wrote: > This patch enables sound support for EXYNOS5 Enable sound for exynos5 based smdk5250 not exynos5. > > Signed-off-by: Rajeshwari Shinde > --- > include/configs/smdk5250.h |8 > 1 files changed, 8 insertions(+), 0 deletions(-) > > diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h > index 4b9093c..fae1c0c 100644 > --- a/include/configs/smdk5250.h > +++ b/include/configs/smdk5250.h > @@ -242,6 +242,14 @@ > #define CONFIG_ENV_SPI_MAX_HZ 5000 > #endif > > +/* Sound */ > +#define CONFIG_CMD_SOUND > +#ifdef CONFIG_CMD_SOUND > +#define CONFIG_SOUND > +#define CONFIG_I2S > +#define CONFIG_SOUND_WM8994 > +#endif > + > /* Enable devicetree support */ > #define CONFIG_OF_LIBFDT > > -- > 1.7.4.4 > -- with warm regards, Chander Kashyap ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] powerpc/85xx: clear out TLB on boot
On 08/21/2012 04:40 AM, Scott Wood wrote: Instead of just shooting down the entry that covers CCSR, clear out every TLB entry that isn't the one that we're executing out of. Signed-off-by: Scott Wood --- v3: Don't skip the "last TLB entry" check when skipping a TLB entry in the invalidation loop. Sorry about the rapid updates -- this should be the last one for this patch unless someone notices a problem. Prabhakar, can you test that this doesn't break debugging? Verified debugging on P1010RDB with NOR, NAND boot and SPI boot. No debug is breaking Thanks, Prabhakar ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] MX28: SPI: Limit the DMA transfer length
The upper limit for DMA transfer length on MX28 is 0x4000 bytes,
otherwise the DMA refuses to operate.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Otavio Salvador
Cc: Stefano Babic
---
drivers/spi/mxs_spi.c | 31 ++-
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
index a037c13..fb6a167 100644
--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
@@ -287,9 +287,9 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
- struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
- struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
- int len = bitlen / 8;
+ struct mxs_spi_slave *sslave = to_mxs_slave(slave);
+ struct mxs_ssp_regs *regs = sslave->regs;
+ int len = bitlen / 8, tl, ret;
char dummy;
int write = 0;
char *data = NULL;
@@ -335,11 +335,24 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
dma = 0;
}
- if (!dma || (len < MXSSSP_SMALL_TRANSFER)) {
- writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
- return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags);
- } else {
- writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
- return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags);
+ while (len) {
+ if (!dma || (len < MXSSSP_SMALL_TRANSFER)) {
+ tl = len;
+ writel(SSP_CTRL1_DMA_ENABLE, ®s->hw_ssp_ctrl1_clr);
+ ret = mxs_spi_xfer_pio(sslave, data, tl, write, flags);
+ } else {
+ /* 0x4000 bytes is the limit for DMA burst. */
+ tl = min(len, 0x4000);
+ writel(SSP_CTRL1_DMA_ENABLE, ®s->hw_ssp_ctrl1_set);
+ ret = mxs_spi_xfer_dma(sslave, data, tl, write, flags);
+ }
+
+ if (ret)
+ return ret;
+
+ data += tl;
+ len -= tl;
}
+
+ return ret;
}
--
1.7.10.4
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Re: [U-Boot] [PATCH 5/5] mpc iim: Switch to common fsl_iim
On 14/08/2012 14:53, Benoît Thébaudeau wrote:
> Signed-off-by: Benoît Thébaudeau
> Cc: Wolfgang Denk
> Cc: Stefano Babic
> ---
> .../arch/powerpc/cpu/mpc512x/Makefile |1 -
> .../arch/powerpc/cpu/mpc512x/iim.c => /dev/null| 394
>
> .../board/davedenx/aria/aria.c |2 +-
> .../board/esd/mecp5123/mecp5123.c |2 +-
> .../board/freescale/mpc5121ads/mpc5121ads.c|2 +-
> .../board/pdm360ng/pdm360ng.c |2 +-
> .../include/configs/aria.h |2 +-
> .../include/configs/mecp5123.h |2 +-
> .../include/configs/mpc5121ads.h |2 +-
> 9 files changed, 7 insertions(+), 402 deletions(-)
> delete mode 100644 u-boot-4d3c95f.orig/arch/powerpc/cpu/mpc512x/iim.c
>
> diff --git u-boot-4d3c95f.orig/arch/powerpc/cpu/mpc512x/Makefile
> u-boot-4d3c95f/arch/powerpc/cpu/mpc512x/Makefile
> index b53232f..4f4c9ec 100644
> --- u-boot-4d3c95f.orig/arch/powerpc/cpu/mpc512x/Makefile
> +++ u-boot-4d3c95f/arch/powerpc/cpu/mpc512x/Makefile
> @@ -38,7 +38,6 @@ COBJS-y += serial.o
> COBJS-y += speed.o
> COBJS-$(CONFIG_FSL_DIU_FB) += diu.o
> COBJS-$(CONFIG_CMD_IDE) += ide.o
> -COBJS-$(CONFIG_IIM) += iim.o
> COBJS-$(CONFIG_PCI) += pci.o
>
> # Stub implementations of cache management functions for USB
> diff --git u-boot-4d3c95f.orig/arch/powerpc/cpu/mpc512x/iim.c
> u-boot-4d3c95f.orig/arch/powerpc/cpu/mpc512x/iim.c
> deleted file mode 100644
> index abec8f6..000
> --- u-boot-4d3c95f.orig/arch/powerpc/cpu/mpc512x/iim.c
> +++ /dev/null
> @@ -1,394 +0,0 @@
> -/*
> - * Copyright 2008 Silicon Turnkey Express, Inc.
> - * Martha Marx
> - *
> - * ADS5121 IIM (Fusebox) Interface
> - *
> - * See file CREDITS for list of people who contributed to this
> - * project.
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of
> - * the License, or (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> - * MA 02111-1307 USA
> - */
> -
> -#include
> -#include
> -#include
> -
> -#ifdef CONFIG_CMD_FUSE
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -static char cur_bank = '1';
> -
> -char *iim_err_msg(u32 err)
> -{
> - static char *IIM_errs[] = {
> - "Parity Error in cache",
> - "Explicit Sense Cycle Error",
> - "Write to Locked Register Error",
> - "Read Protect Error",
> - "Override Protect Error",
> - "Write Protect Error"};
> -
> - int i;
> -
> - if (!err)
> - return "";
> - for (i = 1; i < 8; i++)
> - if (err & (1 << i))
> - printf("IIM - %s\n", IIM_errs[i-1]);
> - return "";
> -}
> -
> -int in_range(int n, int min, int max, char *err, char *usg)
> -{
> - if (n > max || n < min) {
> - printf(err);
> - printf("Usage:\n%s\n", usg);
> - return 0;
> - }
> - return 1;
> -}
> -
> -int ads5121_fuse_read(int bank, int fstart, int num)
> -{
> - iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
> - u32 *iim_fb, dummy;
> - int f, ctr;
> -
> - out_be32(&iim->err, in_be32(&iim->err));
> - if (bank == 0)
> - iim_fb = (u32 *)&(iim->fbac0);
> - else
> - iim_fb = (u32 *)&(iim->fbac1);
> -/* try a read to see if Read Protect is set */
> - dummy = in_be32(&iim_fb[0]);
> - if (in_be32(&iim->err) & IIM_ERR_RPE) {
> - printf("\tRead protect fuse is set\n");
> - out_be32(&iim->err, IIM_ERR_RPE);
> - return 0;
> - }
> - printf("Reading Bank %d cache\n", bank);
> - for (f = fstart, ctr = 0; num > 0; ctr++, num--, f++) {
> - if (ctr % 4 == 0)
> - printf("F%2d:", f);
> - printf("\t%#04x", (u8)(iim_fb[f]));
> - if (ctr % 4 == 3)
> - printf("\n");
> - }
> - if (ctr % 4 != 0)
> - printf("\n");
> -}
> -
> -int ads5121_fuse_override(int bank, int f, u8 val)
> -{
> - iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
> - u32 *iim_fb;
> - u32 iim_stat;
> - int i;
> -
> - out_be32(&iim->err, in_be32(&iim->err));
> - if (bank == 0)
> - iim_fb = (u32 *)&(iim->fbac0);
> - else
> - iim_fb = (u32 *)&(iim->fbac1);
> -/* try a read to see if Read Protect is set */
Re: [U-Boot] [PATCH 4/5] Add fsl_iim driver
On 14/08/2012 14:52, Benoît Thébaudeau wrote:
> Add a fsl_iim driver common to i.MX and MPC.
>
> Signed-off-by: Benoît Thébaudeau
> Cc: Wolfgang Denk
> Cc: Stefano Babic
> ---
> .../drivers/misc/Makefile |1 +
> /dev/null => u-boot-4d3c95f/drivers/misc/fsl_iim.c | 318
>
> 2 files changed, 319 insertions(+)
> create mode 100644 u-boot-4d3c95f/drivers/misc/fsl_iim.c
>
> diff --git u-boot-4d3c95f.orig/drivers/misc/Makefile
> u-boot-4d3c95f/drivers/misc/Makefile
> index 271463c..31b8db8 100644
> --- u-boot-4d3c95f.orig/drivers/misc/Makefile
> +++ u-boot-4d3c95f/drivers/misc/Makefile
> @@ -27,6 +27,7 @@ LIB := $(obj)libmisc.o
>
> COBJS-$(CONFIG_ALI152X) += ali512x.o
> COBJS-$(CONFIG_DS4510) += ds4510.o
> +COBJS-$(CONFIG_FSL_IIM) += fsl_iim.o
> COBJS-$(CONFIG_FSL_LAW) += fsl_law.o
> COBJS-$(CONFIG_GPIO_LED) += gpio_led.o
> COBJS-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
> diff --git u-boot-4d3c95f/drivers/misc/fsl_iim.c
> u-boot-4d3c95f/drivers/misc/fsl_iim.c
> new file mode 100644
> index 000..1a3d5fc
> --- /dev/null
> +++ u-boot-4d3c95f/drivers/misc/fsl_iim.c
> @@ -0,0 +1,318 @@
> +/*
> + * (C) Copyright 2009-2012 ADVANSEE
> + * Benoît Thébaudeau
> + *
> + * Based on the mpc512x iim code:
> + * Copyright 2008 Silicon Turnkey Express, Inc.
> + * Martha Marx
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +/* FSL IIM-specific constants */
> +#define STAT_BUSY0x80
> +#define STAT_PRGD0x02
> +#define STAT_SNSD0x01
> +
> +#define STATM_PRGD_M 0x02
> +#define STATM_SNSD_M 0x01
> +
> +#define ERR_PRGE 0x80
> +#define ERR_WPE 0x40
> +#define ERR_OPE 0x20
> +#define ERR_RPE 0x10
> +#define ERR_WLRE 0x08
> +#define ERR_SNSE 0x04
> +#define ERR_PARITYE 0x02
> +
> +#define EMASK_PRGE_M 0x80
> +#define EMASK_WPE_M 0x40
> +#define EMASK_OPE_M 0x20
> +#define EMASK_RPE_M 0x10
> +#define EMASK_WLRE_M 0x08
> +#define EMASK_SNSE_M 0x04
> +#define EMASK_PARITYE_M 0x02
> +
> +#define FCTL_DPC 0x80
> +#define FCTL_PRG_LENGTH_MASK 0x70
> +#define FCTL_ESNS_N 0x08
> +#define FCTL_ESNS_0 0x04
> +#define FCTL_ESNS_1 0x02
> +#define FCTL_PRG 0x01
> +
> +#define UA_A_BANK_MASK 0x38
> +#define UA_A_ROWH_MASK 0x07
> +
> +#define LA_A_ROWL_MASK 0xf8
> +#define LA_A_BIT_MASK0x07
> +
> +#define PREV_PROD_REV_MASK 0xf8
> +#define PREV_PROD_VT_MASK0x07
> +
> +/* Select the correct accessors depending on endianness */
> +#if __BYTE_ORDER == __LITTLE_ENDIAN
> +#define iim_read32 in_le32
> +#define iim_write32 out_le32
> +#define iim_clrsetbits32 clrsetbits_le32
> +#define iim_clrbits32clrbits_le32
> +#define iim_setbits32setbits_le32
> +#elif __BYTE_ORDER == __BIG_ENDIAN
> +#define iim_read32 in_be32
> +#define iim_write32 out_be32
> +#define iim_clrsetbits32 clrsetbits_be32
> +#define iim_clrbits32clrbits_be32
> +#define iim_setbits32setbits_be32
> +#else
> +#error "Endianess is not defined: please fix to continue"
> +#endif
> +
> +/* IIM control registers */
> +struct fsl_iim {
> + u32 stat;
> + u32 statm;
> + u32 err;
> + u32 emask;
> + u32 fctl;
> + u32 ua;
> + u32 la;
> + u32 sdat;
> + u32 prev;
> + u32 srev;
> + u32 prg_p;
> + u32 scs[0x1f5];
> + struct {
> + u32 row[0x100];
> + } bank[8];
> +};
> +
> +int fuse_read_bit(u32 bank, u32 row, u32 bit, u32 *val)
> +{
> + int ret;
> +
> + if (bit >= 8) {
> + puts("fsl_iim fuse read: Invalid argument\n");
> + return -EINVAL;
> + }
> +
> + ret = fuse_read_row(bank, row, val);
> + if (ret)
> + return ret;
> +
> + *val = !!(*val & 1 << bit);
> + return 0;
> +}
> +
> +i
Re: [U-Boot] [PATCH 3/5] Add fuse API and commands
On 14/08/2012 14:52, Benoît Thébaudeau wrote:
> This can be useful for fuse-like hardware, OTP SoC options, etc.
>
> Signed-off-by: Benoît Thébaudeau
> Cc: Wolfgang Denk
> Cc: Stefano Babic
> ---
CC to Anatolji, he knows very well the MPC5121 that has currently
support of fuses.
> {u-boot-4d3c95f.orig => u-boot-4d3c95f}/README |1 +
> .../common/Makefile|1 +
> /dev/null => u-boot-4d3c95f/common/cmd_fuse.c | 182
>
> .../include/config_cmd_all.h |1 +
> /dev/null => u-boot-4d3c95f/include/fuse.h | 49 ++
> 5 files changed, 234 insertions(+)
> create mode 100644 u-boot-4d3c95f/common/cmd_fuse.c
> create mode 100644 u-boot-4d3c95f/include/fuse.h
>
> diff --git u-boot-4d3c95f.orig/README u-boot-4d3c95f/README
> index fb9d904..c40fd34 100644
> --- u-boot-4d3c95f.orig/README
> +++ u-boot-4d3c95f/README
> @@ -780,6 +780,7 @@ The following options need to be configured:
> CONFIG_CMD_FDOS * Dos diskette Support
> CONFIG_CMD_FLASH flinfo, erase, protect
> CONFIG_CMD_FPGA FPGA device initialization support
> + CONFIG_CMD_FUSE Device fuse support
> CONFIG_CMD_GO * the 'go' command (exec code)
> CONFIG_CMD_GREPENV * search environment
> CONFIG_CMD_HWFLOW * RTS/CTS hw flow control
Agree in this split: we have a general fuse command and each SOC / SOC
family can add its own implementation.
> +static int do_fuse(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
> +{
> + u32 bank, row, bit, cnt, val;
> + int ret, i;
> +
> + if (argc < 4 || strtou32(argv[2], 0, &bank) ||
> + strtou32(argv[3], 0, &row))
> + return CMD_RET_USAGE;
> +
> + if (!strcmp(argv[1], "read.bit")) {
> + if (argc != 5 || strtou32(argv[4], 0, &bit))
> + return CMD_RET_USAGE;
> +
> + printf("Reading bank %u row 0x%.8x bit %u: ", bank, row, bit);
> + ret = fuse_read_bit(bank, row, bit, &val);
> + if (ret)
> + goto err;
> +
> + printf("%u\n", val);
> + } else if (!strcmp(argv[1], "read.row")) {
> + if (argc == 4)
> + cnt = 1;
> + else if (argc != 5 || strtou32(argv[4], 0, &cnt))
> + return CMD_RET_USAGE;
> +
> + printf("Reading bank %u:\n", bank);
> + for (i = 0; i < cnt; i++, row++) {
> + if (!(i % 4))
> + printf("\nRow 0x%.8x:", row);
> +
> + ret = fuse_read_row(bank, row, &val);
> + if (ret)
> + goto err;
> +
> + printf(" %.8x", val);
> + }
> + putc('\n');
> + } else if (!strcmp(argv[1], "sense.bit")) {
> + if (argc != 5 || strtou32(argv[4], 0, &bit))
> + return CMD_RET_USAGE;
> +
> + printf("Sensing bank %u row 0x%.8x bit %u: ", bank, row, bit);
Each command sends this output to the console. I am thinking about if
instead of printf() we shoud use debug()
> +U_BOOT_CMD(
> + fuse, CONFIG_SYS_MAXARGS, 0, do_fuse,
> + "Fuse sub-system",
> + "read.bit- read a fuse bit\n"
> + "fuse read.row [] - read 1 or 'cnt' fuse rows,\n"
> + "starting at 'row'\n"
> + "fuse sense.bit- sense a fuse bit\n"
> + "fuse sense.row [] - sense 1 or 'cnt' fuse rows,\n"
> + "starting at 'row'\n"
> + "fuse prog.bit- program a fuse bit (PERMANENT)\n"
> + "fuse prog.row[...] - program 1 or\n"
> + "several fuse rows, starting at 'row' (PERMANENT)\n"
> + "fuse ovride.bit - override a fuse bit\n"
> + "fuse ovride.row[...] - override 1 or\n"
> + "several fuse rows, starting at 'row'"
> +);
General question: why do we need the "bit" interface ? I have thought it
is enough the read row / prog row interface (even if there is a bit
programming).
Best regards,
Stefano Babic
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Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
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Re: [U-Boot] [PATCH 3/3] tegra20: add USB ULPI init code
On 08/20/12 21:27, Stephen Warren wrote:
> On 08/20/2012 06:41 AM, Lucas Stach wrote:
>> Hello Igor,
>>
>> thanks for your review. Comments inline.
>>
>> Am Montag, den 20.08.2012, 15:07 +0300 schrieb Igor Grinberg:
>>> Hi Lucas,
>>>
>>> On 08/19/12 19:08, Lucas Stach wrote:
This adds the required code to set up a ULPI USB port. It is
mostly a port of the Linux ULPI setup code with some tweaks
added for more correctness, discovered along the way of
debugging this.
>
if (config->utmi) {
+ if (init_utmi_usb_controller(config, usbctlr, timing)) {
+ debug("tegrausb: Cannot init port\n");
>>>
>>> This also looks like an error...
>>> So why debug()?
>>>
+ return -1;
+ }
+
/* Disable ICUSB FS/LS transceiver */
clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
@@ -345,6 +434,24 @@ static int add_port(struct fdt_usb *config, const u32
timing[])
clrbits_le32(&usbctlr->port_sc1, STS);
power_up_port(usbctlr);
}
+
+ if (config->ulpi) {
+#ifdef CONFIG_USB_ULPI
+ /* set up 24MHz ULPI reference clock on pllp_out4 */
+ clock_enable(PERIPH_ID_DEV2_OUT);
+ clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, 2400);
>>>
>>> Wouldn't it be clearer if:
>>> 1) you put the above inside the init_ulpi_usb_controller() function
>>> 2) Provide a !CONFIG_USB_ULPI implementation of the same function
>>>technically having only the code under #else below inside.
>>>
>> Actually I'm not really sure what to do about this. Although I've not
>> seen any Tegra boards with a other ULPI reference freq used, maybe we
>> should just move the clock setup into board code or add a device tree
>> entry to tell the ref frequency.
>>
>> Stephen, Tom, any ideas?
>
> Moving all the initialization into init_utmi_usb_controller() and
> init_ulpi_usb_controller() sounds reasonable to me.
Agreed completely.
>
> I imagine that the reference frequency is somewhat driven by the
> requirements of USB itself and/or the ULPI interface. I think it's fine
> to just hard-code that in the USB driver for now; we can easily enhance
> the driver to make it configurable from either DT or U-Boot config file
> in the future if we need.
Well, it can also be both the controller and the ULPI PHY,
but I agree, you can hard code it for now or make something like:
#define DEFAULT_ULPI_REF_CLK 2400
#ifndef ULPI_REF_CLK
#define ULPI_REF_CLK DEFAULT_ULPI_REF_CLK
#endif
and use the ULPI_REF_CLK where appropriate.
--
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Re: [U-Boot] [PATCH 3/3] tegra20: add USB ULPI init code
On 08/20/12 15:41, Lucas Stach wrote:
> Hello Igor,
>
> thanks for your review. Comments inline.
>
> Am Montag, den 20.08.2012, 15:07 +0300 schrieb Igor Grinberg:
>> Hi Lucas,
>>
>> On 08/19/12 19:08, Lucas Stach wrote:
>>> This adds the required code to set up a ULPI USB port. It is
>>> mostly a port of the Linux ULPI setup code with some tweaks
>>> added for more correctness, discovered along the way of
>>> debugging this.
>>
>> Can you share which tweaks for correctness are there?
>>
> Linux code does not actually check if the phy clock comes up correctly,
> it just waits 100ms and hopes it is there. Also we explicitly select the
> ULPI interface, although it also works without this, as ULPI seems to be
> the default state for USB2.
Ok. Thanks.
>
>>>
>>> To use this both CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT
>>> have to be set in the board configuration file.
>>>
>>> Signed-off-by: Lucas Stach
>>> ---
>>> arch/arm/cpu/armv7/tegra20/usb.c| 131
>>> +---
>>> arch/arm/include/asm/arch-tegra20/usb.h | 29 +--
>>> 2 Dateien geändert, 145 Zeilen hinzugefügt(+), 15 Zeilen entfernt(-)
>>>
>>> diff --git a/arch/arm/cpu/armv7/tegra20/usb.c
>>> b/arch/arm/cpu/armv7/tegra20/usb.c
>>> index 77966e5..2ae1244 100644
>>> --- a/arch/arm/cpu/armv7/tegra20/usb.c
>>> +++ b/arch/arm/cpu/armv7/tegra20/usb.c
>>> @@ -32,9 +32,17 @@
>>> #include
>>> #include
>>> #include
>>> +#include
>>> #include
>>> #include
>>>
>>> +#ifdef CONFIG_USB_ULPI
>>> + #ifndef CONFIG_USB_ULPI_VIEWPORT
>>> + #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \
>>> + define CONFIG_USB_ULPI_VIEWPORT"
>>
>> there is a mix of tabs and spaces in the above line, please make it only tabs
>
> This was actually intentional to align the two lines exactly.
I see. Well, in U-Boot we have had huge threads discussing
how the alignment should be done and the conclusion was that only
tabs should be used (even if it means that the starting letters
will not be one below the other).
Now in the above particular case, you can place a tab between the
"#error" and the message - this will assure the wanted alignment
of both lines.
>
>>> + #endif
>>> +#endif
>>> +
>>> enum {
>>> USB_PORTS_MAX = 4,/* Maximum ports we allow */
>>> };
>>> @@ -68,11 +76,13 @@ enum dr_mode {
>>> struct fdt_usb {
>>> struct usb_ctlr *reg; /* address of registers in physical memory */
>>> unsigned utmi:1;/* 1 if port has external tranceiver, else 0 */
>>> + unsigned ulpi:1;/* 1 if port has external ULPI transceiver */
>>> unsigned enabled:1; /* 1 to enable, 0 to disable */
>>> unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */
>>> enum dr_mode dr_mode; /* dual role mode */
>>> enum periph_id periph_id;/* peripheral id */
>>> struct fdt_gpio_state vbus_gpio;/* GPIO for vbus enable */
>>> + struct fdt_gpio_state phy_reset_gpio; /* GPIO to reset ULPI phy */
>>> };
>>>
>>> static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */
>>> @@ -187,8 +197,8 @@ static void usbf_reset_controller(struct fdt_usb
>>> *config,
>>> */
>>> }
>>>
>>> -/* set up the USB controller with the parameters provided */
>>> -static int init_usb_controller(struct fdt_usb *config,
>>> +/* set up the UTMI USB controller with the parameters provided */
>>> +static int init_utmi_usb_controller(struct fdt_usb *config,
>>> struct usb_ctlr *usbctlr, const u32 timing[])
>>> {
>>> u32 val;
>>> @@ -300,6 +310,83 @@ static int init_usb_controller(struct fdt_usb *config,
>>> return 0;
>>> }
>>>
>>> +#ifdef CONFIG_USB_ULPI
>>> +/* set up the ULPI USB controller with the parameters provided */
>>> +static int init_ulpi_usb_controller(struct fdt_usb *config,
>>> +struct usb_ctlr *usbctlr)
>>> +{
>>> + u32 val;
>>> + int loop_count;
>>> + struct ulpi_regs *ulpi_reg = (struct ulpi_regs *)0;
>>> + struct ulpi_viewport ulpi_vp;
>>> +
>>> + /* reset ULPI phy */
>>> + if (fdt_gpio_isvalid(&config->phy_reset_gpio)) {
>>> + fdtdec_setup_gpio(&config->phy_reset_gpio);
>>> + gpio_direction_output(config->phy_reset_gpio.gpio, 0);
>>> + mdelay(5);
>>> + gpio_set_value(config->phy_reset_gpio.gpio, 1);
>>> + }
>>> +
>>> + /* Reset the usb controller */
>>> + clock_enable(config->periph_id);
>>> + usbf_reset_controller(config, usbctlr);
>>> +
>>> + /* enable pinmux bypass */
>>> + setbits_le32(&usbctlr->ulpi_timing_ctrl_0,
>>> +ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP);
>>> +
>>> + /* Select ULPI parallel interface */
>>> + clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT);
>>> +
>>> + /* enable ULPI transceiver */
>>> + setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);
>>> +
>>> + /* configure ULPI transceiver timings */
>>> + val = 0
Re: [U-Boot] Seeking ARM development platform suggestions
Hi Graeme, On 08/21/2012 05:12 AM, Graeme Russ wrote: >> 2) >> I have a Mele A2000 >> (http://www.cnx-software.com/2012/04/04/mele-a2000-android-2-3-media-player-powered-by-allwinner-a10/) > > This looks promising at ~ AU$100 with USB, SD/MMC, VGA, HDMI, SATA, > Ethernet, WiFi, Sound w/ Optical Out > >> which fancier in the Android department (JB4.1 available) and have Linux >> images, but needs extra dongle for serial. Could "just about" be a >> mediaplayer for locally attached media (maybe) but once you add network play >> and a greater selection of codecs, it moves into "not ready to be a full >> mediaplayer". > > How far off would it be? If I put a really trimmed down Linux xmbc, do > you think it could handle it? > >> Also not in mainline u-boot, but the u-boot available is less hacky. > > I've seen some comments on a few review sites mentioning U-Boot > >> Neither run XBMC enough to be useful. > > Oh :( - just how far off do you think? See Jorgen's mail on this. I also followed this XBMC thread closely, as I'm looking for a low-power ARM box to replace my Atom based HTPC running XBMC. Fortunately I waited with buying an AllWinner device. My interest is now also moving to AMLogic now (see below). >> The general "mood" of the embedded dev community seems to be, to me, to move >> away from these Companies, as the promised source releases has not been >> sufficient. The current interest seems to be AM.logic's dualcore board. >> (http://ao2.it/en/blog/2012/08/10/amlogic-aml8726-mx-linux-kernel-code-released) > > Seems to be more tablet oriented - can't find any 'media players' based on > this There seem to be plenty. Check here for an overview: http://www.j1nx.nl/xbmc-amlogic-8726-m-pivos-xios-an-initial-investigation/ Cheers, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] WARNING: Caches not enabled on openrd based board
> -Original Message- > From: u-boot-boun...@lists.denx.de [mailto:u-boot- > boun...@lists.denx.de] On Behalf Of Alex Zeffertt > Sent: 17 August 2012 16:47 > To: u-boot@lists.denx.de > Subject: [U-Boot] WARNING: Caches not enabled on openrd based board > > Hi U-Booters, > > I get the following warning when I boot our openrd based board: > > > U-Boot 2012.07 (Aug 17 2012 - 10:45:29) > > OpenRD-Base > > > > SoC: Kirkwood 88F6281_A1 > > DRAM: 128 MiB > > WARNING: Caches not enabled > > NAND: 512 MiB > > I am running the latest code from git with a small number of changes > to make it work with our hardware. > (In particular we have had to rewrite > board/Marvell/openrd/kwbimage.cfg.) > > My question is: does the warning about caches affect only U-Boot (in > which case I don't mind) or will it also affect Linux? At least for Kirkwood, cache is forced disabled to keep peripheral drives small and simple. I don't think it affects Linux. Regards... Prafulla . . . ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
