Re: [U-Boot] [PATCH 2/2] pxa: fix memory coherency problem after relocation
Hi Marek, On Sat, 22 Jun 2013 04:29:56 +0200, Marek Vasut wrote: > Albert, do you want me to pick these or will you? Pick them and PR me. > Best regards, > Marek Vasut Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] pxa: fix memory coherency problem after relocation
Dear Mike Dunn, > On the xscale, the icache must be invalidated and the write buffers drained > after writing code over the data bus, even if the caches are disabled. > Tested on the pxa270. > > Signed-off-by: Mike Dunn > --- > arch/arm/lib/relocate.S |9 + > 1 files changed, 9 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S > index 4446da9..eedf314 100644 > --- a/arch/arm/lib/relocate.S > +++ b/arch/arm/lib/relocate.S > @@ -92,6 +92,15 @@ fixnext: > > relocate_done: > > +#ifdef __XSCALE__ > + /* > + * On xscale, icache must be invalidated and write buffers drained, > + * even with cache disabled - 4.2.7 of xscale core developer's manual > + */ > + mcr p15, 0, r0, c7, c7, 0 /* invalidate icache */ > + mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ > +#endif > + > /* ARMv4- don't know bx lr but the assembler fails to see that */ > > #ifdef __ARM_ARCH_4__ Acked-by: Marek Vasut Albert, do you want me to pick these or will you? Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] pxa: use -mcpu=xscale compiler option
Dear Mike Dunn, > Pass '-mcpu=xscale' to the compiler instead of march and mtune. This will > cause gcc to define the __XSCALE__ macro. > > Signed-off-by: Mike Dunn > --- > arch/arm/cpu/pxa/config.mk |2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/arch/arm/cpu/pxa/config.mk b/arch/arm/cpu/pxa/config.mk > index 0bbe295..ea55859 100644 > --- a/arch/arm/cpu/pxa/config.mk > +++ b/arch/arm/cpu/pxa/config.mk > @@ -24,7 +24,7 @@ > > PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float > > -PLATFORM_CPPFLAGS += -march=armv5te -mtune=xscale > +PLATFORM_CPPFLAGS += -mcpu=xscale > # > = > # > # Supply options according to compiler version Acked-by: Marek Vasut Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] dfu, nand: before write a buffer to nand, erase the nand sectors
On 06/21/2013 12:09:18 AM, Heiko Schocher wrote:
diff --git a/drivers/mtd/nand/nand_util.c
b/drivers/mtd/nand/nand_util.c
index d81972c..2778f7f 100644
--- a/drivers/mtd/nand/nand_util.c
+++ b/drivers/mtd/nand/nand_util.c
@@ -120,6 +120,10 @@ int nand_erase_opts(nand_info_t *meminfo, const
nand_erase_options_t *opts)
WATCHDOG_RESET();
+ if (opts->lim && (erase.addr > (opts->offset +
opts->lim))) {
Should be >=
-Scott
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Re: [U-Boot] [U-Boot, v2] powerpc/mpc85xx:Disable Debug TLB entry before init_tlbs
On 06/21/2013 03:38:48 PM, Andy Fleming wrote: On Thu, Jun 13, 2013 at 10:14:00AM +0530, Prabhakar Kushwaha wrote: > init_tlbs() initialize all the TLB entries required for the system. > > So disable DEBUG TLB entry before TLB entries initialization. > > Signed-off-by: Prabhakar Kushwaha Applied, with fixes. > diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c > index f4403c2..340b063 100644 > --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c > +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c > @@ -180,5 +180,9 @@ void cpu_init_early_f(void) > >invalidate_tlb(1); > > +#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_SPL_BUILD) > + disable_tlb(CONFIG_SYS_PPC_E500_DEBUG_TLB); > +#endif Had to add CONFIG_NAND_SPL here, as well, just for future reference Why exclude all SPLs? Only minimal SPLs skip creating the debug TLB. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request: u-boot-arm/master
Hello Tom,
The following changes since commit
847e6693ccb529bf8346db62876f38f0c4e04ade:
arm: pxa: config option for PXA270 turbo mode (2013-06-12 22:24:12
+0200)
are available in the git repository at:
git://git.denx.de/u-boot-arm master
for you to fetch changes up to fbf87b1823dd5ebc2a384711ea2c677543019ece:
arm: optimize relocate_code routine (2013-06-21 23:05:50 +0200)
Akshay Saraswat (2):
Exynos5: clock: Update the equation to calculate PLL output
frequency Exynos: uart: s5p: enabling the uart tx/rx fifo
Albert ARIBAUD (8):
Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'
Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
arm: ensure u-boot only uses relative relocations
remove all references to .dynsym
arm: generalize lib/bss.c into lib/sections.c
arm: make __image_copy_{start, end} compiler-generated
arm: make __rel_dyn_{start, end} compiler-generated
arm: optimize relocate_code routine
Amar (9):
FDT: Add compatible string for DWMMC
EXYNOS5: FDT: Add DWMMC device node data
DWMMC: Initialise dwmci and resolve EMMC read write issues
EXYNOS5: DWMMC: Added FDT support for DWMMC
EXYNOS5: DWMMC: Initialise the local variable to avoid unwanted
results. SMDK5250: Initialise and Enable DWMMC, support FDT and non-FDT
MMC: APIs to support resize of EMMC boot partition
SMDK5250: Enable EMMC booting
COMMON: MMC: Command to support EMMC booting and to resize EMMC
boot partition
Arkadiusz Wlodarczyk (1):
arm:trats: change auto-booting to boot kernel with separate
device tree blob
Dan Murphy (5):
arm: omap: Add check for fdtfile in the findfdt macro
arm: omap5_uevm: Correct the console sys prompt for 5432
arm: dra7xx: Update the EXTRA_ENV_SETTINGS
arm: omap4: panda: Add reading of the board revision
arm: omap4: panda: Fix checkpatch on panda file
Heiko Schocher (3):
arm, am33xx: move rtc32k_enable() to common place
arm, am335x: make mpu pll config configurable
arm, am33xx: move uart soft reset code to common place
Inderpal Singh (3):
exynos: move tzpc_init to armv7/exynos
exynos: update tzpc to make it common for exynos4 and exynos5
exynos: Update origen and smdkv310 to use common tzpc_init
Naveen Krishna Chatradhi (2):
power: exynos-tmu: fix warnings and clean up code
power: exynos-tmu: use the mux_addr bit fields in tmu_control
register
Rajeshwari Shinde (3):
SF: Add driver for Gigabyte device GD25LQ and GD25Q64B
SMDK5250: Enable SPI Gigabyte device.
MMC: DWMMC: Fix FIFO_DEPTH calculation
Simon Guinot (3):
net2big_v2: initialize I2C fan at startup
LaCie/common: add support for the CPLD GPIO bus
net2big_v2: initialize LEDs at startup
Makefile | 7 +
arch/arm/config.mk | 5 +
arch/arm/cpu/arm920t/ep93xx/u-boot.lds | 6 +-
arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds | 5 -
arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds| 5 -
arch/arm/cpu/armv7/am33xx/board.c | 40 ++
arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 9 +-
arch/arm/cpu/armv7/exynos/Makefile | 2 +-
arch/arm/cpu/armv7/exynos/clock.c | 10 +-
.../arm/cpu/armv7/exynos/tzpc.c| 25 +-
arch/arm/cpu/armv7/s5p-common/Makefile | 2 +
arch/arm/cpu/ixp/u-boot.lds| 20 +-
arch/arm/cpu/u-boot-spl.lds| 6 +-
arch/arm/cpu/u-boot.lds| 21 +-
arch/arm/dts/exynos5250.dtsi | 33 ++
arch/arm/include/asm/arch-am33xx/sys_proto.h | 4 +
arch/arm/include/asm/arch-exynos/cpu.h | 4 +
arch/arm/include/asm/arch-exynos/dwmmc.h | 11 +-
arch/arm/include/asm/arch-exynos/tmu.h | 58 ++-
arch/arm/include/asm/arch-exynos/tzpc.h| 20 +
arch/arm/lib/Makefile | 2 +-
arch/arm/lib/relocate.S| 61 +--
arch/arm/lib/{bss.c => sections.c} | 8 +-
board/LaCie/common/cpld-gpio-bus.c | 50 +++
board/LaCie/common/cpld-gpio-bus.h | 24 ++
board/LaCie/net2big_v2/Makefile| 3 +
board/LaCie/net2big_v2/net2big_v2.c| 154 +++-
board/LaCie/net2big_v2/net2big_v2.h| 5 +
board/actux1/u-boot.lds| 20 +-
board/actux2/u-boot.lds| 20 +-
board/actux3/u-boot.lds| 20 +-
board/ait/cam_enc_4xx/u-boot-spl.lds | 5 -
board/davinci/da8xxevm/u-boot-spl-da850evm.lds | 5 -
board/davinci/da8xxevm/u-boot-spl-hawk.lds | 1 -
board/dvlhost/u-boot.lds
Re: [U-Boot] [U-Boot, v2] powerpc/mpc85xx:Disable Debug TLB entry before init_tlbs
On 06/21/2013 04:05:37 PM, Fleming Andy-AFLEMING wrote: On Jun 21, 2013, at 3:59 PM, Scott Wood wrote: > On 06/21/2013 03:38:48 PM, Andy Fleming wrote: >> On Thu, Jun 13, 2013 at 10:14:00AM +0530, Prabhakar Kushwaha wrote: >> > init_tlbs() initialize all the TLB entries required for the system. >> > >> > So disable DEBUG TLB entry before TLB entries initialization. >> > >> > Signed-off-by: Prabhakar Kushwaha >> Applied, with fixes. >> > diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c >> > index f4403c2..340b063 100644 >> > --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c >> > +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c >> > @@ -180,5 +180,9 @@ void cpu_init_early_f(void) >> > >> > invalidate_tlb(1); >> > >> > +#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_SPL_BUILD) >> > + disable_tlb(CONFIG_SYS_PPC_E500_DEBUG_TLB); >> > +#endif >> Had to add CONFIG_NAND_SPL here, as well, just for future reference > > Why exclude all SPLs? Only minimal SPLs skip creating the debug TLB. The definition of disable_tlb() is excluded when NAND_SPL is defined. I'm talking about new-SPL, not NAND_SPL. My comment is about the original patch (I made the comment before internally), not your edit to it. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 0/6] Optimize ARM relocation
On Tue, 11 Jun 2013 14:17:29 +0200, Albert ARIBAUD
wrote:
> This series optimizes relocation by ensuring ARM
> binaries only use one type of relocation record,
> R_ARM_RELATIVE., then optimizing relocation code
> accordingly.
>
> 1. A Makefile rule is added that checks that no
> other relocation record types are generated except
> R_ARM_RELATIVE; build fails if this is the case.
>
> 2. All references to dymsym are removed, as this
> table is not used for R_ARM_RELATIVE relocations.
>
> 3. arch/arm/lib/bss.c is replaced by a more generic
> arch/arm/lib/sections.c where all section symbols will
> be defined.
>
> 4. __image_copy_start and __image_copy_end symbols
> are moved from linker scripts to arch/arm/lib/sections.c
>
> 5. __rel_dyn_start and __rel_dyn_end are moved from
> linker scripts into arch/arm/lib/sections.c
>
> 6. relocate_code is optimized based on the fact that
> symbol references are now always valid even before
> relcation, and that only R_ARM_RELATIVE relocations
> will be met.
>
> Changes in v3:
> - fix commit message typo (of -> if)
> - fix commit message typo (breaks -> break)
>
> Changes in v2:
> - use $< instead of $(obj)u-boot
> - new in V2: remove all dynsym references
> - various comment fixes
>
> Albert ARIBAUD (6):
> arm: ensure u-boot only uses relative relocations
> remove all references to .dynsym
> arm: generalize lib/bss.c into lib/sections.c
> arm: make __image_copy_{start,end} compiler-generated
> arm: make __rel_dyn_{start,end} compiler-generated
> arm: optimize relocate_code routine
>
> Makefile |7 +++
> arch/arm/config.mk |5 ++
> arch/arm/cpu/arm920t/ep93xx/u-boot.lds |6 ++-
> arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds |5 --
> arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds|5 --
> arch/arm/cpu/ixp/u-boot.lds| 20 +---
> arch/arm/cpu/u-boot-spl.lds|6 +--
> arch/arm/cpu/u-boot.lds| 21 +---
> arch/arm/lib/Makefile |2 +-
> arch/arm/lib/relocate.S| 61
> ++--
> arch/arm/lib/{bss.c => sections.c} |8 +++-
> board/actux1/u-boot.lds| 20 +---
> board/actux2/u-boot.lds| 20 +---
> board/actux3/u-boot.lds| 20 +---
> board/ait/cam_enc_4xx/u-boot-spl.lds |5 --
> board/davinci/da8xxevm/u-boot-spl-da850evm.lds |5 --
> board/davinci/da8xxevm/u-boot-spl-hawk.lds |1 -
> board/dvlhost/u-boot.lds | 20 +---
> board/freescale/mx31ads/u-boot.lds | 20 +---
> board/vpac270/u-boot-spl.lds |6 +--
> include/asm-generic/sections.h |3 --
> 21 files changed, 139 insertions(+), 127 deletions(-)
> rename arch/arm/lib/{bss.c => sections.c} (79%)
>
Applied to u-boot-arm/master.
Amicalement,
--
Albert.
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Re: [U-Boot] [U-Boot, v2] powerpc/mpc85xx:Disable Debug TLB entry before init_tlbs
On Jun 21, 2013, at 3:59 PM, Scott Wood wrote: > On 06/21/2013 03:38:48 PM, Andy Fleming wrote: >> On Thu, Jun 13, 2013 at 10:14:00AM +0530, Prabhakar Kushwaha wrote: >> > init_tlbs() initialize all the TLB entries required for the system. >> > >> > So disable DEBUG TLB entry before TLB entries initialization. >> > >> > Signed-off-by: Prabhakar Kushwaha >> Applied, with fixes. >> > diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c >> > b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c >> > index f4403c2..340b063 100644 >> > --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c >> > +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c >> > @@ -180,5 +180,9 @@ void cpu_init_early_f(void) >> > >> >invalidate_tlb(1); >> > >> > +#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_SPL_BUILD) >> > + disable_tlb(CONFIG_SYS_PPC_E500_DEBUG_TLB); >> > +#endif >> Had to add CONFIG_NAND_SPL here, as well, just for future reference > > Why exclude all SPLs? Only minimal SPLs skip creating the debug TLB. The definition of disable_tlb() is excluded when NAND_SPL is defined. It may be that the error lies the other way around, but this fixed my build problem. Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 2/8, v2] powerpc/mpc85xx: modify the functionality clear_bss and aligning the end address of the BSS
On Fri, Jun 07, 2013 at 05:25:16PM +0800, ying.zh...@freescale.com wrote: > From: Ying Zhang > > There will clear the BSS in the function clear_bss(), the reset address of > the BSS started from the __bss_start, and increased by four-byte increments, > finally stoped depending on the address is equal to the _bss_end. If the end > address __bss_end is not alignment to 4byte, it will be an infinite loop. > > 1. The reset action stoped depending on the reset address is greater > than or equal the end address of the BSS. > 2. The end address of the BSS should be 4byte aligned. Because the reset unit > is 4 Bytes. > > This patch is on top of the patch "powerpc/mpc85xx: support application > without resetvec segment in the linker script". > > Signed-off-by: Ying Zhang Applied, thanks! Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Please pull u-boot-mpc85xx.git
The following changes since commit 7315cfd9e1922ee1c3c5f016e5a3b16199122172: NET: Fix system hanging if NET device is not installed (2013-06-19 08:32:44 -0400) are available in the git repository at: git://www.denx.de/git/u-boot-mpc85xx.git master for you to fetch changes up to 5707233880090f785c33df32c04549ea1aeef61e: powerpc/85xx: Add P1023RDB board support (2013-06-20 17:08:53 -0500) Andy Fleming (2): 85xx: Change clock-frequency compatible to 2.0 85xx: Change case of MPC85XX_PORBMSR_ROMLOC_SHIFT Axel Lin (1): powerpc: mpc85xx/mpc86xx: Fix off-by-one boundary checking with ARRAY_SIZE Chris Packham (1): powerpc/CoreNet: Allow pbl images to take u-boot images != 512K Chunhe Lan (1): powerpc/85xx: Add P1023RDB board support Fabio Estevam (1): powerpc: Use lower case for the core names Liu Gang (6): powerpc/doc: Update the README.srio-pcie-boot-corenet powerpc/boot: Change the macro of Boot from SRIO and PCIE master module powerpc/b4860qds: Enable master module for boot from SRIO and PCIE powerpc/b4860qds: Slave module for boot from SRIO and PCIE powerpc/t4qds: Enable master module for Boot from SRIO and PCIE powerpc/t4qds: Slave module for boot from SRIO and PCIE Mingkai Hu (2): powerpc/mpc85xx: explicit cast the SDRAM size to type phys_size_t fsl_ifc: add support for different IFC bank count Prabhakar Kushwaha (9): powerpc/mpc85xx:No NOR boot, do not compile IFC errata A003399 powerpc/mpc85xx: new SPL support for IFC NAND board/p1010rdb:Add NAND boot support using new SPL format board/bsc9131rdb:Add NAND boot support using new SPL format board/bsc9132qds:Add NAND boot support using new SPL format powerpc/mpc85xx:Fix "boot page TLB" entry size for NAND SPL board/b4860qds: Relax NOR flash teadc timing parameter board/p1010rdb: Fix PCIe TLB creation on CONFIG_PCI define powerpc/mpc85xx:Disable Debug TLB entry before init_tlbs Priyanka Jain (3): board/bsc9131rdb: Add targets for Sysclk 100MHz board/bsc9131rdb: Add DSP side tlb and laws board/bsc9131rdb: Update default boot environment settings Scott Wood (1): powerpc/mpc85xx: work around erratum A-006593 Ying Zhang (4): powerpc/mpc85xx: support application without resetvec segment in the linker script powerpc/mpc85xx: modify the functionality clear_bss and aligning the end address of the BSS common/Makefile: Add new symbol CONFIG_SPL_ENV_SUPPORT for environment in SPL Makefile: move the common makefile line to public area York Sun (2): powerpc/BSC9132: Add IFC bank count powerpc/pixis: Fix pixis help message README | 27 ++ arch/powerpc/cpu/mpc85xx/Makefile |1 + arch/powerpc/cpu/mpc85xx/cmd_errata.c |3 + arch/powerpc/cpu/mpc85xx/cpu.c | 10 +- arch/powerpc/cpu/mpc85xx/cpu_init.c|5 +- arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 10 +- arch/powerpc/cpu/mpc85xx/fdt.c |2 +- arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c |4 +- arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c |4 +- arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c |2 +- arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c |2 +- arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c |2 +- arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c |2 +- arch/powerpc/cpu/mpc85xx/p1010_serdes.c|4 +- arch/powerpc/cpu/mpc85xx/p1021_serdes.c|2 +- arch/powerpc/cpu/mpc85xx/p1022_serdes.c|4 +- arch/powerpc/cpu/mpc85xx/p1023_serdes.c|2 +- arch/powerpc/cpu/mpc85xx/p2020_serdes.c|2 +- arch/powerpc/cpu/mpc85xx/p2041_serdes.c|2 +- arch/powerpc/cpu/mpc85xx/p3041_serdes.c|2 +- arch/powerpc/cpu/mpc85xx/p4080_serdes.c|2 +- arch/powerpc/cpu/mpc85xx/p5020_serdes.c|2 +- arch/powerpc/cpu/mpc85xx/p5040_serdes.c|2 +- arch/powerpc/cpu/mpc85xx/start.S |2 +- arch/powerpc/cpu/mpc85xx/t1040_serdes.c|2 +- arch/powerpc/cpu/mpc85xx/u-boot-spl.lds| 18 +- arch/powerpc/cpu/mpc85xx/u-boot.lds|8 + arch/powerpc/cpu/mpc86xx/cpu.c |2 +- arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c |4 +- arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c |4 +- arch/powerpc/cpu/mpc8xxx/fsl_ifc.c | 60 ++- arch/powerpc/cpu/mpc8xxx/srio.c|4 +- arch/powerpc/include/asm/config_mpc85xx.h | 13 +- arch/powerpc/include/asm/fsl_ifc.h | 95 +++-- arch/powerpc/include/asm/fsl_law.h |5 + arch/powerpc/include/asm/immap_85xx.h
Re: [U-Boot] [U-Boot,v4] powerpc/85xx: Add P1023RDB board support
On Fri, Jun 14, 2013 at 04:21:48PM +0800, Chunhe Lan wrote: > P1023RDB Specification: > --- > Memory subsystem: >512MB DDR3 (Fixed DDR on board) >64MB NOR flash >128MB NAND flash > > Ethernet: >eTSEC1: Connected to Atheros AR8035 GETH PHY >eTSEC2: Connected to Atheros AR8035 GETH PHY > > PCIe: >Three mini-PCIe slots > > USB: >Two USB2.0 Type A ports > > I2C: >AT24C08 8K Board EEPROM (8 bit address) > > Signed-off-by: Chunhe Lan > Cc: Scott Wood Applied, thanks! Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] powerpc: mpc85xx/mpc86xx: Fix off-by-one boundary checking with ARRAY_SIZE
On Sun, May 26, 2013 at 03:00:30PM +0800, Axel Lin wrote: > If a variable is used as array subscript, it's valid value range is > 0 ... ARRAY_SIZE -1. > > Signed-off-by: Axel Lin Applied, thanks! Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,v2] powerpc/pixis: Fix pixis help message
On Fri, May 31, 2013 at 08:48:04AM -0700, York Sun wrote: > "pixis_reset help" command prints the message without a new line "\n", > which makes the prompt on the same line. > > Signed-off-by: York Sun Applied, thanks! Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 4/6] Makefile: move the common makefile line to public area
On Mon, May 20, 2013 at 02:07:26PM +0800, ying.zh...@freescale.com wrote: > From: Ying Zhang > > Move the common makefile line shared by the SPL and non-SPL to the public > area, > so that we can avoid excessive SPL symbols. Some of them will be used by the > SPL later. > > This patch is on top of the patch "common/Makefile: Add new symbol > CONFIG_SPL_ENV_SUPPORT for environment in SPL". > > Signed-off-by: Ying Zhang > Acked-by: Tom Rini > Acked-by: Tom Rini Applied, thanks! Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 3/6] common/Makefile: Add new symbol CONFIG_SPL_ENV_SUPPORT for environment in SPL
On Mon, May 20, 2013 at 02:07:25PM +0800, ying.zh...@freescale.com wrote: > From: Ying Zhang > > There will need the environment in SPL for reasons other than network > support (in particular, hwconfig contains info for how to set up DDR). > > Add a new symbol CONFIG_SPL_ENV_SUPPORT to replace CONFIG_SPL_NET_SUPPORT > for environment in common/Makefile. > > Signed-off-by: Ying Zhang > Reviewed-by: Tom Rini Applied, thanks! Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 1/6] powerpc/mpc85xx: support application without resetvec segment in the linker script
On Mon, May 20, 2013 at 02:07:23PM +0800, ying.zh...@freescale.com wrote: > From: Ying Zhang > > For SD/SPI 2-stage bootloader, the On-Chip Rom code loads the SPL into L2 > SRAM, > then jump to it to begin execution. After that, the SPL loads the final uboot > image into DDR, then jump to it to begin execution. The segment .resetvec in > the SPL and in final U-boot is useless. > > So, add new symbols CONFIG_SYS_MPC85XX_NO_RESETVEC for this application. > If CONFIG_SYS_MPC85XX_NO_RESETVEC is set, the segment .resetvec is excluded > and the segment .bootpg is placed in the previous 4K of the segment .text. > > Signed-off-by: Ying Zhang Applied, thanks! Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] board/p1010rdb: Fix PCIe TLB creation on CONFIG_PCI define
On Fri, May 17, 2013 at 02:22:34PM +0530, Prabhakar Kushwaha wrote: > PCIe TLB should be created with CONFIG_PCI defined > > Signed-off-by: Prabhakar Kushwaha Applied, thanks! Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 2/6, v2] powerpc/boot: Change the macro of Boot from SRIO and PCIE master module
On Tue, May 07, 2013 at 04:30:46PM +0800, Liu Gang wrote: > Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable > the master module of Boot from SRIO and PCIE on a platform. But this > is not a silicon feature, it's just a specific booting mode based on > the SRIO and PCIE interfaces. So it's inappropriate to put the macro > into the file arch/powerpc/include/asm/config_mpc85xx.h. > > Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to > "CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from > arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros > in configuration header file of each board which can support the > master module of Boot from SRIO and PCIE. > > Signed-off-by: Liu Gang Applied, thanks! Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 5/6, v2] powerpc/t4qds: Enable master module for Boot from SRIO and PCIE
On Tue, May 07, 2013 at 04:30:49PM +0800, Liu Gang wrote: > T4 can support the feature of Boot from SRIO/PCIE, and the macro > "CONFIG_SRIO_PCIE_BOOT_MASTER" will enable the master module of this feature > when building the u-boot image. > > You can get some description about this macro in README file, and for more > information about the feature of Boot from SRIO/PCIE, please refer to the > document doc/README.srio-pcie-boot-corenet. > > Signed-off-by: Liu Gang Applied, thanks! Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2] fsl_ifc: add support for different IFC bank count
On Thu, May 16, 2013 at 10:18:13AM +0800, Mingkai Hu wrote: > From: Mingkai Hu > > Calculate reserved fields according to IFC bank count > > 1. Move csor_ext register behind csor register and fix res offset > 2. Move ifc bank count to config_mpc85xx.h to support 8 bank count > 3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile >error on some devices that does not have IFC controller. > > Signed-off-by: Mingkai Hu Applied, thanks! Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] board/b4860qds: Relax NOR flash teadc timing parameter
On Fri, May 17, 2013 at 01:40:52PM +0530, Prabhakar Kushwaha wrote: > Relax parameters to give address latching more time to setup. > > Signed-off-by: Prabhakar Kushwaha Applied, thanks! Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] powerpc/mpc85xx: work around erratum A-006593
On Wed, May 15, 2013 at 05:50:13PM -0500, Scott Wood wrote: > Erratum A-006593 is "Atomic store may report failure but still allow > the store data to be visible". > > The workaround is: "Set CoreNet Platform Cache register CPCHDBCR0 bit > 21 to 1'b1. This may have a small impact on synthetic write bandwidth > benchmarks but should have a negligible impact on real code." > > Signed-off-by: Scott Wood Applied, thanks! Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 1/6, v2] powerpc/doc: Update the README.srio-pcie-boot-corenet
On Tue, May 07, 2013 at 04:30:45PM +0800, Liu Gang wrote: > 1. Misalignment will be found in the doc/README.srio-pcie-boot-corenet >file when the tabs are set to 8 characters. And the standard for >u-boot should be 8 character tabs! So this issue should be amended. > > 2. Add a NOTE for the ENV parameters of the Slave. > > Signed-off-by: Liu Gang Applied, thanks! Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 3/6, v2] powerpc/b4860qds: Enable master module for boot from SRIO and PCIE
On Tue, May 07, 2013 at 04:30:47PM +0800, Liu Gang wrote: > B4860QDS can support the feature of Boot from SRIO/PCIE, and the macro > "CONFIG_SRIO_PCIE_BOOT_MASTER" will enable the master module of this feature > when building the u-boot image. > > You can get some description about this macro in README file, and for more > information about the feature of Boot from SRIO/PCIE, please refer to the > document doc/README.srio-pcie-boot-corenet. > > Signed-off-by: Liu Gang Applied, thanks! Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] powerpc/mpc85xx:Fix "boot page TLB" entry size for NAND SPL
On Tue, May 07, 2013 at 11:19:55AM +0530, Prabhakar Kushwaha wrote: > e500v2 processor does not support 8K page size TLB entries. > > So create new TLB entry only during NAND SPL boot. > > Signed-off-by: Prabhakar Kushwaha Applied, thanks! Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 4/6, v2] powerpc/b4860qds: Slave module for boot from SRIO and PCIE
On Tue, May 07, 2013 at 04:30:48PM +0800, Liu Gang wrote: > When a b4860qds board boots from SRIO or PCIE, it needs to finish these > processes: > 1. Set all the cores in holdoff status. > 2. Set the boot location to one PCIE or SRIO interface by RCW. > 3. Set a specific TLB entry for the boot process. > 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. > 5. Set a specific TLB entry in order to fetch ucode and ENV from > master. > 6. Set a LAW entry with the TargetID one of the PCIE ports for > ucode and ENV. > 7. Slave's u-boot image should be generated specifically by > make _SRIO_PCIE_BOOT_config. > This will set SYS_TEXT_BASE=0xFFF8 and other configurations. > > For more information about the feature of Boot from SRIO/PCIE, please > refer to the document doc/README.srio-pcie-boot-corenet. > > Signed-off-by: Liu Gang Applied, thanks! Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] powerpc: Use lower case for the core names
On Sun, Apr 21, 2013 at 01:11:02PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam
>
> Freescale documentation presents the PowerPC core names in lower case, such as
> "e300", "e500", "e600", etc.
>
> Change the upper case occurrences into lower case so that the core names
> reported in U-boot can match the ones from the documentation.
>
> While at it also fix a checkpatch error:
>
> ERROR: space prohibited before that close parenthesis ')'
> #53: FILE: arch/powerpc/cpu/mpc86xx/cpu.c:81:
> + printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0 );
>
> Reported-by: Heinz Wrobel
> Signed-off-by: Fabio Estevam
Applied, thanks!
Andy
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Re: [U-Boot] powerpc/BSC9132: Add IFC bank count
On Thu, Apr 18, 2013 at 07:31:01PM -0700, York Sun wrote: > BSC9132 has 3 IFC banks. > > Signed-off-by: York Sun Applied, thanks! Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 3/5, v5] board/p1010rdb:Add NAND boot support using new SPL format
On Tue, Apr 16, 2013 at 01:28:12PM +0530, Prabhakar Kushwaha wrote: > - defines contants > - Add spl_minimal.c to initialise DDR > - update TLB entries as per NAND boot > - remove nand_spl support for P1010RDB > > Signed-off-by: Prabhakar Kushwaha Applied, thanks! Fixed typos in commit message Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 4/5, v5] board/bsc9131rdb:Add NAND boot support using new SPL format
On Tue, Apr 16, 2013 at 01:28:25PM +0530, Prabhakar Kushwaha wrote: > - Add NAND boot target >- defines contants >- Add spl_minimal.c to initialise DDR >- update TLB entries as per NAND boot > > Signed-off-by: Prabhakar Kushwaha Applied, thanks! Fixed typo Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 5/5, v5] board/bsc9132qds:Add NAND boot support using new SPL format
On Tue, Apr 16, 2013 at 01:28:40PM +0530, Prabhakar Kushwaha wrote: > - Add NAND boot target >- defines contants >- Add spl_minimal.c to initialise DDR >- update TLB, LAW entries as per NAND boot > > Signed-off-by: Prabhakar Kushwaha Applied, thanks! Fixed typo. Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 2/5, v5] powerpc/mpc85xx: new SPL support for IFC NAND
On Tue, Apr 16, 2013 at 01:27:59PM +0530, Prabhakar Kushwaha wrote:
> Linker script is not able find start.o binary. So add its absolute path in
> u-boot-spl.lds. This change is similar to u-boot-nand.lds
>
> common/Makefile: Avoid compiling unnecssary files
>
> fsl_ifc_spl.c : It is is responsible for reading u-boot binary from
> NAND flash and copying into DDR. It also transfer cotrol from NAND SPL
> to u-boot image present in DDR.
>
> Signed-off-by: Prabhakar Kushwaha
Fixed typo and applied, thanks. Also changed a few instances of 15
to 0xf.
Andy
>
> ---
> Changes for v2: Sending as it is
> Changes for v3: Fix tools/checkpatch errors
> Changes for v4: Sending as it is
> Changes for v5: Rebased
>
> arch/powerpc/cpu/mpc85xx/u-boot-spl.lds |2 +-
> board/freescale/common/Makefile | 10 ++
> drivers/mtd/nand/Makefile |1 +
> drivers/mtd/nand/fsl_ifc_spl.c | 258
> +++
> 4 files changed, 270 insertions(+), 1 deletion(-)
> create mode 100644 drivers/mtd/nand/fsl_ifc_spl.c
>
> diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
> b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
> index f2b7bff..cf6fa7c 100644
> --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
> +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
> @@ -60,7 +60,7 @@ SECTIONS
> #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
> .bootpg ADDR(.text) + 0x1000 :
> {
> - start.o (.bootpg)
> + arch/powerpc/cpu/mpc85xx/start.o (.bootpg)
> }
> #define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
> #elif defined(CONFIG_FSL_ELBC)
> diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
> index 75725b4..a4d521c 100644
> --- a/board/freescale/common/Makefile
> +++ b/board/freescale/common/Makefile
> @@ -29,6 +29,15 @@ endif
>
> LIB = $(obj)libfreescale.o
>
> +MINIMAL=
> +
> +ifdef CONFIG_SPL_BUILD
> +ifdef CONFIG_SPL_INIT_MINIMAL
> +MINIMAL=y
> +endif
> +endif
> +
> +ifndef MINIMAL
> COBJS-$(CONFIG_FSL_CADMUS) += cadmus.o
> COBJS-$(CONFIG_FSL_VIA) += cds_via.o
> COBJS-$(CONFIG_FMAN_ENET)+= fman.o
> @@ -62,6 +71,7 @@ SUBLIB-$(CONFIG_P3041DS)+= p_corenet/libp_corenet.o
> SUBLIB-$(CONFIG_P4080DS) += p_corenet/libp_corenet.o
> SUBLIB-$(CONFIG_P5020DS) += p_corenet/libp_corenet.o
> SUBLIB-$(CONFIG_P5040DS) += p_corenet/libp_corenet.o
> +endif
>
> SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
> OBJS := $(addprefix $(obj),$(COBJS-y))
> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
> index 35769c5..dd1df4a 100644
> --- a/drivers/mtd/nand/Makefile
> +++ b/drivers/mtd/nand/Makefile
> @@ -81,6 +81,7 @@ COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
> else # minimal SPL drivers
>
> COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o
> +COBJS-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o
> COBJS-$(CONFIG_NAND_MXC) += mxc_nand_spl.o
>
> endif # drivers
> diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c
> new file mode 100644
> index 000..adfe7b1
> --- /dev/null
> +++ b/drivers/mtd/nand/fsl_ifc_spl.c
> @@ -0,0 +1,258 @@
> +/*
> + * NAND boot for Freescale Integrated Flash Controller, NAND FCM
> + *
> + * Copyright 2011 Freescale Semiconductor, Inc.
> + * Author: Dipen Dudhat
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +
> +static inline int is_blank(uchar *addr, int page_size)
> +{
> + int i;
> +
> + for (i = 0; i < page_size; i++) {
> + if (__raw_readb(&addr[i]) != 0xff)
> + return 0;
> + }
> +
> + /*
> + * For the SPL, don't worry about uncorrectable errors
> + * where the main area is all FFs but shouldn't be.
> + */
> + return 1;
> +}
> +
> +/* returns nonzero if entire page is blank */
> +static inline int check_read_ecc(uchar *buf, u32 *eccstat,
> + unsigned int bufnum, int page_size)
> +{
> + u32 reg = eccstat[bufnum / 4];
> + int errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
> +
> + if (errors == 15) { /* uncorrectable */
> + /* Blank pages fail hw ECC checks */
> + if (is_blank(buf, page_size))
> +
Re: [U-Boot] [U-Boot, 1/5, v5] powerpc/mpc85xx:No NOR boot, do not compile IFC errata A003399
On Tue, Apr 16, 2013 at 01:27:44PM +0530, Prabhakar Kushwaha wrote: > IFC errata A003399 is valid for IFC NOR boot i.e.if no on-board NOR flash or > no NOR boot, do not compile its workaround. > > Signed-off-by: Prabhakar Kushwaha Applied, thanks! Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] board/bsc9131rdb: Add DSP side tlb and laws
On Thu, Apr 04, 2013 at 09:31:54AM +0530, Priyanka Jain wrote: > BSC9131RDB is a Freescale Reference Design Board for > BSC9131 SoC which is a integrated device that contains > one powerpc e500v2 core and one DSP starcore. > > To support DSP starcore > -Creating LAW and TLB for DSP-CCSR space. > -Creating LAW for DSP-core subsystem M2 memory > > Signed-off-by: Priyanka Jain > Signed-off-by: Poonam Aggrwal > Signed-off-by: Prabhakar Kushwaha Applied, thanks! Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] board/bsc9131rdb: Update default boot environment settings
On Thu, Apr 04, 2013 at 02:40:32PM +0530, Priyanka Jain wrote: > BSC9131RDB has 1GB DDR. > Out of this, only 880MB is passed on to Linux via bootm_size. > Remaining > -16MB is reserved for PowerPC-DSP shared control area > -128MB is reserved for DSP private area. > > Also 256MB, out of this 880MB is required for data communication between > PowerPC and DSP core. > For this bootargs are modified to pass parameter to create 1 hugetlb > page of 256MB via default_hugepagesz, hugepagesz and hugepages > > Signed-off-by: Priyanka Jain Applied, thanks! Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] powerpc/mpc85xx: explicit cast the SDRAM size to type phys_size_t
On Fri, Apr 12, 2013 at 03:56:28PM +0800, Mingkai Hu wrote: > To avoid sign extension problem, use explicit casting to cast > the SDRAM size to type phys_size_t, or else, if the SDRAM size > is 2G(0x8000), it will be extended to 0x8000 > when phys_size_t is type 'unsigned long long'. > > Signed-off-by: Mingkai Hu Applied, thanks! Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] board/bsc9131rdb: Add targets for Sysclk 100MHz
On Mon, Apr 01, 2013 at 12:12:45PM +0530, Priyanka Jain wrote: > BSC9131RDB supports Sysclk > -66MHz if jumper J16 is close (default state) > -100MHz if jumper J16 is open > > Add targets > -BSC9131RDB_NAND_SYSCLK100 : for NAND boot at Sysclk 100MHz > -BSC9131RDB_SPIFLASH_SYSCLK100: for SPI boot at Sysclk 100MHz > > Signed-off-by: Ramneek Mehresh > Signed-off-by: Priyanka Jain > > --- Applied, thanks! Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2] powerpc/mpc85xx:Disable Debug TLB entry before init_tlbs
On Thu, Jun 13, 2013 at 10:14:00AM +0530, Prabhakar Kushwaha wrote: > init_tlbs() initialize all the TLB entries required for the system. > > So disable DEBUG TLB entry before TLB entries initialization. > > Signed-off-by: Prabhakar Kushwaha Applied, with fixes. > diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c > b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c > index f4403c2..340b063 100644 > --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c > +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c > @@ -180,5 +180,9 @@ void cpu_init_early_f(void) > > invalidate_tlb(1); > > +#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_SPL_BUILD) > + disable_tlb(CONFIG_SYS_PPC_E500_DEBUG_TLB); > +#endif Had to add CONFIG_NAND_SPL here, as well, just for future reference ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 6/6, v2] powerpc/t4qds: Slave module for boot from SRIO and PCIE
On Tue, May 07, 2013 at 04:30:50PM +0800, Liu Gang wrote: > When a T4 board boots from SRIO or PCIE, it needs to finish these processes: > 1. Set all the cores in holdoff status. > 2. Set the boot location to one PCIE or SRIO interface by RCW. > 3. Set a specific TLB entry for the boot process. > 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. > 5. Set a specific TLB entry in order to fetch ucode and ENV from > master. > 6. Set a LAW entry with the TargetID one of the PCIE ports for > ucode and ENV. > 7. Slave's u-boot image should be generated specifically by > make _SRIO_PCIE_BOOT_config. > This will set SYS_TEXT_BASE=0xFFF8 and other configurations. > > For more information about the feature of Boot from SRIO/PCIE, please > refer to the document doc/README.srio-pcie-boot-corenet. > > Signed-off-by: Liu Gang Applied with fixes for build errors. I think this was just an issue of this patch arriving before the T4 consolidation patch, but please be careful. > diff --git a/boards.cfg b/boards.cfg > index 61acc3f..354738e 100644 > --- a/boards.cfg > +++ b/boards.cfg > @@ -896,6 +896,7 @@ stxssa_4Mpowerpc mpc85xx > stxssa stx > T4240QDS powerpc mpc85xx t4qds > freescale > T4240QDS_SDCARD powerpc mpc85xx t4qds > freescale - T4240QDS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF8 > T4240QDS_SPIFLASHpowerpc mpc85xx t4qds > freescale - T4240QDS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8 > +T4240QDS_SRIO_PCIE_BOOT powerpc mpc85xx t4qds > freescale - > T4240QDS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF8 Had to fix this line so it included PPC_T4240, for future reference Thanks, Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] powerpc/CoreNet: Allow pbl images to take u-boot images != 512K
On Mon, May 27, 2013 at 10:51:46AM +1200, Chris Packham wrote:
> From: Chris Packham
>
> Instead of assuming that SYS_TEXT_BASE is 0xFFF8 calculate the initial
> pbl command offset by subtracting the image size from the top of the
> 24-bit address range. Also increase the size of the memory buffer to
> accommodate a larger output image.
>
> Signed-off-by: Chris Packham
I've applied this (thanks), but I'll note it had a warning about unused
variable "size". Because it was unused. Please build-test any patches,
and ensure they are free of warnings.
> + * The PBL can load up to 64 bytes at a time, so we split the U-Boot
> + * image into 64 byte chunks. PBL needs a command for each piece, of
> + * the form "81xx", where "xx" is the offset. Calculate the
> + * start offset by subtracting the size of the u-boot image from the
> + * top of the allowable 24-bit range.
> + */
> +static void init_next_pbl_cmd(FILE *fp_uboot)
> +{
> + struct stat st;
> + int fd = fileno(fp_uboot);
> + size_t size;
This was the variable, for future reference.
> +
> + if (fstat(fd, &st) == -1) {
> + printf("Error: Could not determine u-boot image size. %s\n",
> + strerror(errno));
> + exit(EXIT_FAILURE);
> + }
> +
> + next_pbl_cmd = 0x8200 - st.st_size;
> +}
Andy
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Re: [U-Boot] [U-Boot,v2] powerpc/85xx: Add TWR-P10xx board support
On Thu, Apr 25, 2013 at 03:51:11PM +0800, Xie Xiaobo wrote: > TWR-P1025 Specification: > --- > Memory subsystem: >512MB DDR3 (on board DDR) >64Mbyte 16bit NOR flash >One microSD Card slot > > Ethernet: >eTSEC1: Connected to Atheros AR8035 GETH PHY >eTSEC3: Connected to Atheros AR8035 GETH PHY > > UART: >Two UARTs are routed to the FDTI dual USB to RS232 convertor > > USB: Two USB2.0 Type A ports > > I2C: >AT24C01B 1K Board EEPROM (8 bit address) > > QUICC Engine: >Connected to DP83849i PHY supply two 10/100M ethernet ports >QE UART for RS485 or RS232 > > PCIE: >One mini-PCIE slot > > Signed-off-by: Michael Johnston > Signed-off-by: Xie Xiaobo [...] > diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h > new file mode 100644 > index 000..d18c8f4 > --- /dev/null > +++ b/include/configs/p1_twr.h [...] > + > +#define CONFIG_MP > + > +#define CONFIG_FSL_ELBC > +#define CONFIG_PCI > +#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ > +#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ > +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ > +#define CONFIG_FSL_PCIE_RESET/* need PCIe reset errata */ > +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ Why is CONFIG_PCI_INDIRECT_BRIDGE not set? Without it, the PCI code is not building, which raises the question of how you build-tested this code... Please rebase, build-test, and fix any errors before resubmitting. Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/11] MIPS: bootm updates
Hello Daniel, sorry for being late with my questions. Daniel Schwierzeck wrote on 2013-06-09: > MIPS: bootm: refactor initialisation of kernel cmdline > MIPS: bootm: refactor initialisation of kernel environment > MIPS: bootm: make initialisation of Linux environment optional > MIPS: bootm: add support for generic relocation of init ramdisks > MIPS: bootm: automatically initialise kernel cmdline variable 'mem' > MIPS: bootm: automatically initialise kernel cmdline variables 'rd_start' > and 'rd_size' These patches changing the style, how parameters are given to the kernel (using cmdline instead of environment). Can you explain a little, why this is necessary? Please give some references to the corresponding kernel changes or discussions, if possible. And how about backward compatibility? Will it still be possible to boot older kernels? When you automatically add the variable 'mem', will it still be possible to override the memory size by manually adding it to the bootargs? Best Regards, Thomas ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC] [UBOOT] [PATCH 0/4] DWC back port from Linux kernel
On Fri, Jun 21, 2013 at 01:27:41PM -0500, Dan Murphy wrote: > This patch series has been generated in an effort to get comments on > the implementation of the dwc code within the uBoot. > > The first patch is the one of major concern as this patch will make an > attempt to commonize the usb headers so that there is re-use and prepare > the usb headers for future usb code back ports from the linux kernel. > > This code will compile for omap5 and omap4 but fails for am335x. > Before I invest anymore time in this I would like to understand if there are > any comments on the overall implemenation. A few minor, I hope, comments to make review easier. While in the final commit we would squash these into two commits, I'd like to suggest: commit 1: Import vanilla kernel files A/B/C commit 2: U-Boot adaptation of files A/B/C commit 3: Import vanilla kernel dwc3 driver commit 4: U-Boot adaptation of dwc3 driver Also, note that we don't need the last kernel commit ID to change the file, but the kernel commit ID you backported the whole thing from. In other words, you can just grab everything from v3.10-rc6 and use that ID in the commit messages. Oh, and doing things in the above split will make it easier for you to re-sync with v3.10 when it comes out and so forth. Thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Modifying the Device tree fields
On 06/21/2013 12:26:33 PM, Kamaraj P wrote:
Hello All,
In my device tree blob, i would like to add some interrupt to the
protected-source list dynamically in the u-boot before launching the
linux
kernel.
mpic: pic@4 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x4 0x4>;
compatible = "chrp,open-pic";
device_type = "open-pic";
protected-sources = <
16
>
In the above DTS file, i would like to add the other interrupts to
the
protected-sources dynamically.
If you use the pic-no-reset property, you don't need protected-sources
at all, unless you specifically want the error checking aspect of it.
I hope we need to use the device fdt APIs. Could you please any
pointers
or reference for how to use those APIs in the u-boot ?
fdt_appendprop looks like a good choice if you still want to do this.
-Scott
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Re: [U-Boot] Modifying the Device tree fields
On Fri, Jun 21, 2013 at 10:56:33PM +0530, Kamaraj P wrote:
> Hello All,
>
> In my device tree blob, i would like to add some interrupt to the
> protected-source list dynamically in the u-boot before launching the linux
> kernel.
>
> mpic: pic@4 {
> interrupt-controller;
> #address-cells = <0>;
> #interrupt-cells = <2>;
> reg = <0x4 0x4>;
> compatible = "chrp,open-pic";
> device_type = "open-pic";
> protected-sources = <
> 16
> >
>
> In the above DTS file, i would like to add the other interrupts to the
> protected-sources dynamically.
> I hope we need to use the device fdt APIs. Could you please any pointers
> or reference for how to use those APIs in the u-boot ?
If you can do it with the fdt command, you can then work out what the C
API versions would look like.
--
Tom
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Re: [U-Boot] AM335x: enabling datacache in SPL slows down system?
On Fri, Jun 21, 2013 at 08:46:47PM +0200, Jeroen Hofstee wrote: > Hello Wolfgang, > > On 06/21/2013 07:33 AM, Wolfgang Denk wrote: > >We observed the very same issue with the verry first prototype > >implementation of Falcon mode on an AM3517 based board. [..] > For the am3517 the only thing needed is to add SRAM > to the known memory. See [1], that should change the > cache misses (which likely cause the extra delays) to > actual caches. U-boot only adds the detected memory > and since U-boot is running from DRAM and SPL is not, > the difference seems obvious. This would be my guess as folks have done functional but not mainlineable changes in this direction, as well as DMA, before. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] AM335x: enabling datacache in SPL slows down system?
Hello Wolfgang, On 06/21/2013 07:33 AM, Wolfgang Denk wrote: We observed the very same issue with the verry first prototype implementation of Falcon mode on an AM3517 based board. [..] For the am3517 the only thing needed is to add SRAM to the known memory. See [1], that should change the cache misses (which likely cause the extra delays) to actual caches. U-boot only adds the detected memory and since U-boot is running from DRAM and SPL is not, the difference seems obvious. Regards, Jeroen [1] http://lists.denx.de/pipermail/u-boot/2013-June/156949.html ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Modifying the Device tree fields
Hello All,
In my device tree blob, i would like to add some interrupt to the
protected-source list dynamically in the u-boot before launching the linux
kernel.
mpic: pic@4 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x4 0x4>;
compatible = "chrp,open-pic";
device_type = "open-pic";
protected-sources = <
16
>
In the above DTS file, i would like to add the other interrupts to the
protected-sources dynamically.
I hope we need to use the device fdt APIs. Could you please any pointers
or reference for how to use those APIs in the u-boot ?
Thanks,
Kamaraj
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Re: [U-Boot] [PATCH v2 6/7] ARM: extend non-secure switch to also go into HYP mode
Hello, On Thu, Jun 13, 2013 at 2:01 PM, Andre Przywara wrote: > For the KVM and XEN hypervisors to be usable, we need to enter the > kernel in HYP mode. Now that we already are in non-secure state, > HYP mode switching is within short reach. > > While doing the non-secure switch, we have to enable the HVC > instruction and setup the HYP mode HVBAR (while still secure). > > The actual switch is done by dropping back from a HYP mode handler > without actually leaving HYP mode, so we introduce a new handler > routine in our new secure exception vector table. > > In the assembly switching routine we save and restore the banked LR > and SP registers around the hypercall to do the actual HYP mode > switch. > > The C routine first checks whether we are in HYP mode already and > also whether the virtualization extensions are available. It also > checks whether the HYP mode switch was finally successful. > The bootm command part only adds and adjusts some error reporting. > > Signed-off-by: Andre Przywara > --- > arch/arm/cpu/armv7/nonsec_virt.S | 31 --- > arch/arm/include/asm/armv7.h | 7 +-- > arch/arm/lib/bootm.c | 14 ++ > arch/arm/lib/virt-v7.c | 27 ++- > 4 files changed, 65 insertions(+), 14 deletions(-) > > diff --git a/arch/arm/cpu/armv7/nonsec_virt.S > b/arch/arm/cpu/armv7/nonsec_virt.S > index 919f6e9..950da6f 100644 > --- a/arch/arm/cpu/armv7/nonsec_virt.S > +++ b/arch/arm/cpu/armv7/nonsec_virt.S > @@ -1,5 +1,5 @@ > /* > - * code for switching cores into non-secure state > + * code for switching cores into non-secure state and into HYP mode > * > * Copyright (c) 2013 Andre Przywara > * > @@ -26,14 +26,14 @@ > #include > #include > > -/* the vector table for secure state */ > +/* the vector table for secure state and HYP mode */ > _secure_vectors: > .word 0 /* reset */ > .word 0 /* undef */ > adr pc, _secure_monitor > .word 0 > .word 0 > - .word 0 > + adr pc, _hyp_trap > .word 0 > .word 0 > .word 0 /* pad */ > @@ -50,10 +50,23 @@ _secure_monitor: > bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET > bits > orr r1, r1, #0x31 @ enable NS, AW, FW bits > > + mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 > + and r0, r0, #CPUID_ARM_VIRT_MASK@ mask virtualization bits > + cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT) > + orreq r1, r1, #0x100 @ allow HVC instruction > + > mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit > set) > > + mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value > + mcreq p15, 4, r0, c12, c0, 0 @ write HVBAR > + > movspc, lr @ return to non-secure SVC > > +_hyp_trap: > + .byte 0x00, 0xe3, 0x0e, 0xe1@ mrs lr, elr_hyp > + mov pc, lr @ do no switch modes, but > + @ return to caller > + > /* > * Secondary CPUs start here and call the code for the core specific parts > * of the non-secure and HYP mode transition. The GIC distributor specific > @@ -69,6 +82,7 @@ _smp_pen: > mcr p15, 0, r1, c12, c0, 0 @ set VBAR > > bl _nonsec_init > + bl _hyp_init > If I get it right, _nonsec_init stores the GICC address. Adding _hyp_init here overwrites r3. In effect the following lines do something on the stack (sp). > > ldr r1, [r3, #0x0c] @ read GICD acknowledge > str r1, [r3, #0x10] @ write GICD EOI > can you add these 0x0c and 0x10 constants to gic.h. > @@ -145,3 +159,14 @@ _nonsec_init: > str r1, [r2]@ allow private interrupts > > bx lr > + > +.globl _hyp_init > +_hyp_init: > + mov r2, lr > + mov r3, sp @ save SVC copy of LR and > SP > + isb > + .byte 0x70, 0x00, 0x40, 0xe1@ hvc #0 > + mov sp, r3 > + mov lr, r2 @ fix HYP mode banked LR > and SP > + > + bx lr > diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h > index 04545b9..8c3a85e 100644 > --- a/arch/arm/include/asm/armv7.h > +++ b/arch/arm/include/asm/armv7.h > @@ -89,15 +89,18 @@ void v7_outer_cache_inval_range(u32 start, u32 end); > > #ifdef CONFIG_ARMV7_VIRT > > -#define HYP_ERR_NO_SEC_EXT 2 > +#define HYP_ERR_ALREADY_HYP_MODE 1 > +#define HYP_ERR_NO_VIRT_EXT2 > #define HYP_ERR_NO_GIC_ADDRESS 3 > #define HYP_ERR_GIC_ADDRESS_ABOVE_4GB 4 > +#define HYP_ERR_NOT_HYP_MODE 5 > > -int armv7_switch_nonsec(void); > +int armv7_switch_hyp(void); > > /* defined in cpu/armv7/nonsec_virt.S */ > void _nonsec_init(void); > void
[U-Boot] [RFC] [UBOOT] [PATCH 3/4] omap5: usb: Add usb otg clocks and enable
Add and enable the USB OTG clocks.
Signed-off-by: Dan Murphy
---
arch/arm/cpu/armv7/omap5/hw_data.c | 14 ++
arch/arm/cpu/armv7/omap5/prcm-regs.c |1 +
arch/arm/include/asm/arch-omap5/clocks.h |4
arch/arm/include/asm/omap_common.h |1 +
common/cmd_usb.c |6 +-
include/configs/omap5_common.h |9 +
6 files changed, 34 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index 604fa42..8feceb5 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -394,6 +394,20 @@ void enable_basic_clocks(void)
OPTFCLKEN_SCRM_PER_MASK);
setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
OPTFCLKEN_SCRM_CORE_MASK);
+
+/* TODO wrap this with USB defines */
+ /* Setting OCP2SCP1 register */
+ setbits_le32((*prcm)->cm_l3init_ocp2scp1_clkctrl,
+ MODULE_CLKCTRL_MODULEMODE_HW_AUTO);
+
+ /* Select USB OTG SS clock */
+ setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
+ (MODULE_CLKCTRL_MODULEMODE_HW_AUTO |
+OPTFCLKEN_USB_OTG_SS_FCLK_MASK));
+
+ /* Setting l3init register */
+ setbits_le32((*prcm)->cm_l3init_clkstctrl,
OPTFCLKEN_USB_OTG_SS_FCLK_MASK);
+
}
void enable_basic_uboot_clocks(void)
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c
b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index e9f6a32..3638095 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -708,6 +708,7 @@ struct prcm_regs const omap5_es2_prcm = {
.cm_l3init_p1500_clkctrl = 0x4a009678,
.cm_l3init_fsusb_clkctrl = 0x4a0096d0,
.cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
+ .cm_l3init_usb_otg_ss_clkctrl = 0x4a0096f0,
/* l4 wkup regs */
.cm_abe_pll_ref_clksel = 0x4ae0610c,
diff --git a/arch/arm/include/asm/arch-omap5/clocks.h
b/arch/arm/include/asm/arch-omap5/clocks.h
index 68afa76..c1eb7d9 100644
--- a/arch/arm/include/asm/arch-omap5/clocks.h
+++ b/arch/arm/include/asm/arch-omap5/clocks.h
@@ -174,6 +174,10 @@
/* CM_L3INIT_USBPHY_CLKCTRL */
#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8
+/* CM_L3INIT_USB_OTG_SS_CLKCTRL */
+#define OPTFCLKEN_USB_OTG_SS_FCLK_SHIFT8
+#define OPTFCLKEN_USB_OTG_SS_FCLK_MASK (1 << 8)
+
/* CM_MPU_MPU_CLKCTRL */
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24)
diff --git a/arch/arm/include/asm/omap_common.h
b/arch/arm/include/asm/omap_common.h
index baeef4e..ea962d5 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -241,6 +241,7 @@ struct prcm_regs {
u32 cm_l3init_p1500_clkctrl;
u32 cm_l3init_fsusb_clkctrl;
u32 cm_l3init_ocp2scp1_clkctrl;
+ u32 cm_l3init_usb_otg_ss_clkctrl;
/* cm2.l4per */
u32 cm_l4per_clkstctrl;
diff --git a/common/cmd_usb.c b/common/cmd_usb.c
index 70e803b..816fb23 100644
--- a/common/cmd_usb.c
+++ b/common/cmd_usb.c
@@ -31,6 +31,7 @@
#include
#include
#include
+#include
#ifdef CONFIG_USB_STORAGE
static int usb_stor_curr_dev = -1; /* current device */
@@ -160,6 +161,7 @@ static void usb_display_string(struct usb_device *dev, int
index)
static void usb_display_desc(struct usb_device *dev)
{
+#if 0
if (dev->descriptor.bDescriptorType == USB_DT_DEVICE) {
printf("%d: %s, USB Revision %x.%x\n", dev->devnum,
usb_get_class_desc(dev->config.if_desc[0].desc.bInterfaceClass),
@@ -189,7 +191,7 @@ static void usb_display_desc(struct usb_device *dev)
(dev->descriptor.bcdDevice>>8) & 0xff,
dev->descriptor.bcdDevice & 0xff);
}
-
+#endif
}
static void usb_display_conf_desc(struct usb_config_descriptor *config,
@@ -350,10 +352,12 @@ static void usb_show_tree_graph(struct usb_device *dev,
char *pre)
pre[index++] = ' ';
pre[index++] = has_child ? '|' : ' ';
pre[index] = 0;
+#if 0
printf(" %s (%s, %dmA)\n", usb_get_class_desc(
dev->config.if_desc[0].desc.bInterfaceClass),
portspeed(dev->speed),
dev->config.desc.bMaxPower * 2);
+#endif
if (strlen(dev->mf) || strlen(dev->prod) || strlen(dev->serial))
printf(" %s %s %s %s\n", pre, dev->mf, dev->prod, dev->serial);
printf(" %s\n", pre);
diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h
index deb5e9f..ecb4a70 100644
--- a/include/configs/omap5_common.h
+++ b/include/configs/omap5_common.h
@@ -104,6 +104,15 @@
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+/* USB */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_DWC3
+#define CONFIG_
[U-Boot] [RFC] [UBOOT] [PATCH 4/4] Makefile: Add the libdwc3 to the main Makefile
Add the libdwc3 to the Makefile so that drivers/usb/dwc3 is included in the build Signed-off-by: Dan Murphy --- Makefile |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/Makefile b/Makefile index ef154aa..e0a15cf 100644 --- a/Makefile +++ b/Makefile @@ -327,6 +327,7 @@ LIBS-y += drivers/usb/gadget/libusb_gadget.o LIBS-y += drivers/usb/host/libusb_host.o LIBS-y += drivers/usb/musb/libusb_musb.o LIBS-y += drivers/usb/musb-new/libusb_musb-new.o +LIBS-y += drivers/usb/dwc3/libusb_dwc3.o LIBS-y += drivers/usb/phy/libusb_phy.o LIBS-y += drivers/usb/ulpi/libusb_ulpi.o LIBS-y += drivers/video/libvideo.o -- 1.7.5.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC] [UBOOT] [PATCH 0/4] DWC back port from Linux kernel
This patch series has been generated in an effort to get comments on the implementation of the dwc code within the uBoot. The first patch is the one of major concern as this patch will make an attempt to commonize the usb headers so that there is re-use and prepare the usb headers for future usb code back ports from the linux kernel. This code will compile for omap5 and omap4 but fails for am335x. Before I invest anymore time in this I would like to understand if there are any comments on the overall implemenation. Makefile |1 + arch/arm/cpu/armv7/omap5/hw_data.c | 14 + arch/arm/cpu/armv7/omap5/prcm-regs.c |1 + arch/arm/include/asm/arch-omap5/clocks.h |4 + arch/arm/include/asm/omap_common.h |1 + common/cmd_usb.c |6 +- drivers/usb/dwc3/Makefile| 53 + drivers/usb/dwc3/core.c | 847 + drivers/usb/dwc3/core.h | 974 +++ drivers/usb/dwc3/dwc3-omap.c | 505 ++ drivers/usb/dwc3/dwc3-omap.h | 41 + drivers/usb/dwc3/dwc3-uboot.c| 384 drivers/usb/dwc3/ep0.c | 1085 drivers/usb/dwc3/gadget.c| 2806 ++ drivers/usb/dwc3/gadget.h| 196 +++ drivers/usb/dwc3/host.c | 107 ++ drivers/usb/dwc3/io.h| 81 + drivers/usb/host/Makefile|2 + drivers/usb/musb-new/musb_host.h |1 + drivers/usb/musb-new/usb-compat.h| 30 - include/configs/omap5_common.h |9 + include/linux/usb/gadget.h | 184 ++- include/linux/usb/linux-compat.h | 234 +++ include/linux/usb/usb-compat.h | 1957 + include/linux/usb/usb-mod-devicetable.h | 131 ++ include/usb.h| 119 +-- include/usb/lin_gadget_compat.h | 29 +- 27 files changed, 9590 insertions(+), 212 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/7] cleanup in the 'ifm AC14xx' board support
On Wed, Jun 05, 2013 at 14:51 +0200, Gerhard Sittig wrote: > > this change set adjusts the configuration of the 'ifm AC14xx' board > to get closer to mainline philosophy and slightly improves builtin > diagnostics and robustness after setup failure > > > changes in v2: > - address a potential NULL pointer dereference in the diagnostics > code path as well (previously unhandled in mainline) > - split the previous convoluted v1 patch into a series of > individual patches, each addressing one specific issue, > to aid in the review process Are there any other concerns that I shall address? Any feedback beyond what was mentioned before? virtually yours Gerhard Sittig -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: off...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] nand: Don't call adjust_size_for_badblocks for erase
On 06/20/2013 11:19:19 PM, Heiko Schocher wrote: Hello Scott, Am 20.06.2013 19:52, schrieb Scott Wood: > adjust_size_for_badblocks reduces the the operation size to account nitpicking: please only one "the". Thanks, I'll fix when applying. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2] drivers:power:max77686: add function to set voltage and mode
Dear Piotr Wilczek,
On 21 May 2013 21:54, Piotr Wilczek wrote:
> This patch add new functions to pmic max77686 to set voltage and mode.
>
> Signed-off-by: Piotr Wilczek
> Signed-off-by: Kyungmin Park
> CC: Minkyu Kang
> CC: Rajeshwari Shinde
>
> Acked-by: Rajeshwari Shinde
> ---
> Changes in v2:
> - changed printf to debug
>
> drivers/power/pmic/pmic_max77686.c | 186
>
> include/power/max77686_pmic.h | 11 +++
> 2 files changed, 197 insertions(+)
>
> diff --git a/drivers/power/pmic/pmic_max77686.c
> b/drivers/power/pmic/pmic_max77686.c
> index 7fcb4c0..dabd6b6 100644
> --- a/drivers/power/pmic/pmic_max77686.c
> +++ b/drivers/power/pmic/pmic_max77686.c
> @@ -30,6 +30,192 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> +static const char max77686_buck_addr[] = {
> + 0xff, 0x10, 0x12, 0x1c, 0x26, 0x30, 0x32, 0x34, 0x36, 0x38
> +};
> +
> +static unsigned int max77686_ldo_volt2hex(int ldo, ulong uV)
> +{
> + unsigned int hex = 0;
> + const unsigned int max_hex = 0x3f;
>
Is it constant? then please define it.
+
> + switch (ldo) {
> + case 1:
> + case 2:
> + case 6:
> + case 7:
> + case 8:
> + case 15:
> + hex = (uV - 80) / 25000;
> + break;
> + default:
> + hex = (uV - 80) / 5;
> + }
> +
> + if (0 <= hex && hex <= max_hex)
>
I think, hex >= 0 looks more comfortable.
> + return hex;
> +
> + debug("%s: %ld is wrong voltage value for LDO%d\n", __func__, uV,
> ldo);
> + return 0;
> +}
> +
> +int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV)
> +{
> + unsigned int val, ret, hex, adr, mask;
> +
> + if (ldo < 1 && 26 < ldo) {
>
ditto.
> + printf("%s: %d is wrong ldo number\n", __func__, ldo);
> + return -1;
> + }
> +
> + adr = MAX77686_REG_PMIC_LDO1CTRL1 + ldo - 1;
> + mask = 0x3f;
> + hex = max77686_ldo_volt2hex(ldo, uV);
> +
> + if (!hex)
> + return -1;
> +
> + ret = pmic_reg_read(p, adr, &val);
>
I think.. if you got error while read the register then please return error
without writing.
+ val &= ~mask;
> + val |= hex;
> + ret |= pmic_reg_write(p, adr, val);
>
+
> + return ret;
> +}
> +
> +int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode)
> +{
> + unsigned int val, ret, mask, adr, mode;
> +
> + if (ldo < 1 && 26 < ldo) {
> + printf("%s: %d is wrong ldo number\n", __func__, ldo);
> + return -1;
> + }
> +
> + adr = MAX77686_REG_PMIC_LDO1CTRL1 + ldo - 1;
> +
> + /* mask */
> + mask = 0xc0;
>
Is it constant? then please define it.
> +
> + /* mode */
> + if (opmode == OPMODE_OFF) {
> + mode = 0x00;
> + } else if (opmode == OPMODE_STANDBY) {
> + switch (ldo) {
> + case 2:
> + case 6:
> + case 7:
> + case 8:
> + case 10:
> + case 11:
> + case 12:
> + case 14:
> + case 15:
> + case 16:
> + mode = 0x40;
+ break;
> + default:
> + mode = 0xff;
> + }
> + } else if (opmode == OPMODE_LPM) {
> + mode = 0x80;
> + } else if (opmode == OPMODE_ON) {
> + mode = 0xc0;
> + } else {
> + mode = 0xff;
> + }
>
switch case?
What means 0x40 and 0x80, 0xc0?
There are so many magic values in this patch.
I'll not mentioned about it anymore.
Please fix it globally.
> +
> + if (mode == 0xff) {
> + printf("%s: %d is not supported on LDO%d\n",
> + __func__, opmode, ldo);
> + return -1;
> + }
> +
> + ret = pmic_reg_read(p, adr, &val);
>
ditto.
> + val &= ~mask;
> + val |= mode;
> + ret |= pmic_reg_write(p, adr, val);
> +
> + return ret;
> +}
> +
> +int max77686_set_buck_mode(struct pmic *p, int buck, char opmode)
> +{
> + unsigned int val, ret, mask, adr, size, mode;
> +
> + size = sizeof(max77686_buck_addr) / sizeof(*max77686_buck_addr);
>
ARRAY_SIZE()?
> + if (buck >= size) {
> + printf("%s: %d is wrong buck number\n", __func__, buck);
> + return -1;
> + }
> +
> + adr = max77686_buck_addr[buck];
> +
> + /* mask */
> + switch (buck) {
> + case 2:
> + case 3:
> + case 4:
> + mask = 0x30;
> + break;
> + default:
> + mask = 0x03;
> + }
> +
> + /* mode */
> + if (opmode == OPMODE_OFF) {
> + mode = 0x00;
> + } else if (opmode == OPMODE_STANDBY) {
> + switch (buck) {
> + case 1:
> + m
Re: [U-Boot] [PATCH v5 1/3] ARM: Tegra: FDT: Add USB EHCI function for T30/T114
On 06/21/2013 05:05 AM, Jim Lin wrote: > Add DT node for USB EHCI function. > Add support for T30-Cardhu, T30-Beaver, T114-Dalmore boards. > Changes in v5: > - Move changes on fdtdec.h and fdtdec.c to patch 2/3 > - Modify PHY type to hsic for USB2 port HSIC is an odd choice; ULPI is much more common. Still, this isn't a big deal; this is simply a default value, so any board that enables USB2 can simply set the property to "ulpi" if needed. Missing from the changelog is the fact you fixed the VBUS GPIO values for Cardhu and Beaver to be correct. I'll try to test and do a final review of this soon. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] pxa: use -mcpu=xscale compiler option
Pass '-mcpu=xscale' to the compiler instead of march and mtune. This will cause gcc to define the __XSCALE__ macro. Signed-off-by: Mike Dunn --- arch/arm/cpu/pxa/config.mk |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/cpu/pxa/config.mk b/arch/arm/cpu/pxa/config.mk index 0bbe295..ea55859 100644 --- a/arch/arm/cpu/pxa/config.mk +++ b/arch/arm/cpu/pxa/config.mk @@ -24,7 +24,7 @@ PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float -PLATFORM_CPPFLAGS += -march=armv5te -mtune=xscale +PLATFORM_CPPFLAGS += -mcpu=xscale # = # # Supply options according to compiler version -- 1.7.8.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] pxa: fix memory coherency problem after relocation
On the xscale, the icache must be invalidated and the write buffers drained after writing code over the data bus, even if the caches are disabled. Tested on the pxa270. Signed-off-by: Mike Dunn --- arch/arm/lib/relocate.S |9 + 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S index 4446da9..eedf314 100644 --- a/arch/arm/lib/relocate.S +++ b/arch/arm/lib/relocate.S @@ -92,6 +92,15 @@ fixnext: relocate_done: +#ifdef __XSCALE__ + /* +* On xscale, icache must be invalidated and write buffers drained, +* even with cache disabled - 4.2.7 of xscale core developer's manual +*/ + mcr p15, 0, r0, c7, c7, 0 /* invalidate icache */ + mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ +#endif + /* ARMv4- don't know bx lr but the assembler fails to see that */ #ifdef __ARM_ARCH_4__ -- 1.7.8.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/2] pxa: fix memory coherency problem after relocation
These patches fix a memory coherency problem that sometimes occurs on xscale after code relocation. The first patch changes the options passed to the compiler so that the __XSCALE__ macro is defined. This is used in the second patch to limit the change to xscale cores, where the necessary cache operations are performed before jumping to the relocated code. Whether other cores need a similiar operation after code relocation remains an open question. Thanks Albert. Mike Dunn (2): pxa: use -mcpu=xscale compiler option pxa: fix memory coherency problem after relocation arch/arm/cpu/pxa/config.mk |2 +- arch/arm/lib/relocate.S|9 + 2 files changed, 10 insertions(+), 1 deletions(-) -- 1.7.8.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4 V5] S5P: Serial: Add fdt support to driver
Dear Rajeshwari Shinde,
On 17 May 2013 20:03, Rajeshwari Shinde wrote:
> This patch adds FDT support to the serial s5p driver.
> At present disabling the serial console (from the device tree) crashes
> U-Boot. Add checks for this case, so that execution can continue without
> a serial console.
> It also enables the serial_s5p driver recognize the silent_console option.
>
> Signed-off-by: Abhilash Kesavan
> Signed-off-by: Gabe Black
> Signed-off-by: Simon Glass
> Signed-off-by: Rajeshwari Shinde
> ---
> Changes in V2:
> - None
> Changes in V3:
> - Moved driver config structure to data section.
> - Changed silent_console to silent-console.
> - Did put a check for base address before doing fdt decoding.
> Changes in V4:
> - None
> Changes in V5:
> - None
> drivers/serial/serial_s5p.c | 78
> +++
> 1 files changed, 78 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
> index 3c41242..55ef2bf 100644
> --- a/drivers/serial/serial_s5p.c
> +++ b/drivers/serial/serial_s5p.c
> @@ -24,16 +24,28 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> +/* Information about a serial port */
> +struct fdt_serial {
> + u32 base_addr; /* address of registers in physical memory */
> + u8 port_id; /* uart port number */
> + u8 enabled; /* 1 if enabled, 0 if disabled */
> +} config __attribute__ ((section(".data")));
> +
> static inline struct s5p_uart *s5p_get_base_uart(int dev_index)
> {
> +#ifdef CONFIG_OF_CONTROL
> + return (struct s5p_uart *)(config.base_addr);
> +#else
> u32 offset = dev_index * sizeof(struct s5p_uart);
> return (struct s5p_uart *)(samsung_get_base_uart() + offset);
> +#endif
> }
>
> /*
> @@ -69,6 +81,9 @@ void serial_setbrg_dev(const int dev_index)
> u32 baudrate = gd->baudrate;
> u32 val;
>
> + if (!config.enabled)
> + return;
> +
> val = uclk / baudrate;
>
> writel(val / 16 - 1, &uart->ubrdiv);
> @@ -87,6 +102,16 @@ int serial_init_dev(const int dev_index)
> {
> struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
>
> +#if defined(CONFIG_SILENT_CONSOLE) && \
> + defined(CONFIG_OF_CONTROL) && \
> + !defined(CONFIG_SPL_BUILD)
> + if (fdtdec_get_config_int(gd->fdt_blob, "silent_console", 0))
> + gd->flags |= GD_FLG_SILENT;
> +#endif
> +
> + if (!config.enabled)
> + return 0;
> +
> /* reset and enable FIFOs, set triggers to the maximum */
> writel(0, &uart->ufcon);
> writel(0, &uart->umcon);
> @@ -129,6 +154,9 @@ int serial_getc_dev(const int dev_index)
> {
> struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
>
> + if (!config.enabled)
> + return 0;
> +
> /* wait for character to arrive */
> while (!(readl(&uart->utrstat) & 0x1)) {
> if (serial_err_check(dev_index, 0))
> @@ -145,6 +173,9 @@ void serial_putc_dev(const char c, const int dev_index)
> {
> struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
>
> + if (!config.enabled)
> + return;
> +
> /* wait for room in the tx FIFO */
> while (!(readl(&uart->utrstat) & 0x2)) {
> if (serial_err_check(dev_index, 1))
> @@ -165,6 +196,9 @@ int serial_tstc_dev(const int dev_index)
> {
> struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
>
> + if (!config.enabled)
> + return 0;
> +
> return (int)(readl(&uart->utrstat) & 0x1);
> }
>
> @@ -207,8 +241,51 @@ DECLARE_S5P_SERIAL_FUNCTIONS(3);
> struct serial_device s5p_serial3_device =
> INIT_S5P_SERIAL_STRUCTURE(3, "s5pser3");
>
> +#ifdef CONFIG_OF_CONTROL
> +int fdtdec_decode_console(int *index, struct fdt_serial *uart)
> +{
> + const void *blob = gd->fdt_blob;
> + int node;
> +
> + node = fdt_path_offset(blob, "console");
> + if (node < 0)
> + return node;
> +
> + uart->base_addr = fdtdec_get_addr(blob, node, "reg");
> + if (uart->base_addr == FDT_ADDR_T_NONE)
> + return -FDT_ERR_NOTFOUND;
> +
> + uart->port_id = fdtdec_get_int(blob, node, "id", -1);
> + uart->enabled = fdtdec_get_is_enabled(blob, node);
> +
> + return 0;
> +}
> +#endif
> +
> __weak struct serial_device *default_serial_console(void)
> {
> +#ifdef CONFIG_OF_CONTROL
> + int index = 0;
> +
> + if ((!config.base_addr) && (fdtdec_decode_console(&index,
> &config))) {
> + debug("Cannot decode default console node\n");
> + return NULL;
> + }
> +
> + if (config.port_id == 0)
> + return &s5p_serial0_device;
> + else if (config.port_id == 1)
> + return &s5p_serial1_device
Re: [U-Boot] [PATCH 00/10] PXE support updates
Hi Rob, On Sun, Jun 16, 2013 at 9:29 PM, Joe Hershberger wrote: > Hi Rob, > > On Sun, Jun 16, 2013 at 10:24 AM, Rob Herring wrote: >> On Tue, May 14, 2013 at 3:32 PM, Joe Hershberger >> wrote: >>> Hi Rob, >>> >>> On Tue, May 14, 2013 at 2:48 PM, Rob Herring wrote: On Sun, Dec 2, 2012 at 9:00 PM, Rob Herring wrote: > From: Rob Herring > > This is a series of various enhancements and fixes for u-boot pxe support. > These patches are a result of testing with server side tools like Cobbler > and ubuntu MAAS. > > Rob > > Rob Herring (10): > pxe: Use ethact setting for pxe > pxe: make string parameters const > pxe: fix handling of different localboot values > bootz: un-staticize do_bootz > pxe: use bootz instead of bootm when enabled > pxe: always display a menu when present > pxe: simplify menu display and selection > pxe: add support for ontimeout token > pxe: add support for per arch and SoC default paths > pxe: add ipappend support > > common/cmd_bootm.c |2 +- > common/cmd_pxe.c | 210 > > include/command.h |2 + > 3 files changed, 132 insertions(+), 82 deletions(-) Is someone going to pick these patches up? The single comment by Wolfgang I've addressed. >>> >>> Yes... I'll pick these up... apologies for the delays. >> >> When can I expect to see these land? > > I've got these patches in my local repo and I'm build testing them. > > I'll likely send a PR by the end of today or tomorrow. > > -Joe I ran into some build failures on some boards from some of the patches so I'm working on fixing them. -Joe ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATH v5 13/14] sf: Remove spi_flash_cmd_poll_bit()
There is no other call other than spi_flash_cmd_wait_ready(),
hence removed spi_flash_cmd_poll_bit and use the poll status code
spi_flash_cmd_wait_ready() itself.
Signed-off-by: Jagannadha Sutradharudu Teki
Reviewed-by: Simon Glass
---
Changes for v5:
- none
Changes for v4:
- none
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/spi_flash.c | 11 +++
drivers/mtd/spi/spi_flash_internal.h | 4
2 files changed, 3 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 0ed2295..cca02d1 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -194,13 +194,14 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash, u32
offset,
return ret;
}
-int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout,
- u8 cmd, u8 poll_bit)
+int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
{
struct spi_slave *spi = flash->spi;
unsigned long timebase;
int ret;
u8 status;
+ u8 poll_bit = STATUS_WIP;
+ u8 cmd = CMD_READ_STATUS;
ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
if (ret) {
@@ -231,12 +232,6 @@ int spi_flash_cmd_poll_bit(struct spi_flash *flash,
unsigned long timeout,
return -1;
}
-int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
-{
- return spi_flash_cmd_poll_bit(flash, timeout,
- CMD_READ_STATUS, STATUS_WIP);
-}
-
int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len)
{
u32 erase_size;
diff --git a/drivers/mtd/spi/spi_flash_internal.h
b/drivers/mtd/spi/spi_flash_internal.h
index e613ef3..e9b85bf 100644
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -107,10 +107,6 @@ int spi_flash_bank_config(struct spi_flash *flash, u8
idcode0);
int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
size_t cmd_len, void *data, size_t data_len);
-/* Send a command to the device and wait for some bit to clear itself. */
-int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout,
- u8 cmd, u8 poll_bit);
-
/*
* Send the read status command to the device and wait for the wip
* (write-in-progress) bit to clear itself.
--
1.8.3
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[U-Boot] [PATH v5 04/14] sf: Update sf to support all sizes of flashes
Updated the spi_flash framework to handle all sizes of flashes
using bank/extd addr reg facility
The current implementation in spi_flash supports 3-byte address mode
due to this up to 16Mbytes amount of flash is able to access for those
flashes which has an actual size of > 16MB.
As most of the flashes introduces a bank/extd address registers
for accessing the flashes in 16Mbytes of banks if the flash size
is > 16Mbytes, this new scheme will add the bank selection feature
for performing write/erase operations on all flashes.
Signed-off-by: Jagannadha Sutradharudu Teki
Reviewed-by: Simon Glass
---
Changes for v5:
- none
Changes for v4:
- none
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/spi_flash.c | 39 ++-
1 file changed, 26 insertions(+), 13 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 64b57ec..7f1ef17 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -74,11 +74,9 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32
offset,
unsigned long page_addr, byte_addr, page_size;
size_t chunk_len, actual;
int ret;
- u8 cmd[4];
+ u8 cmd[4], bank_sel;
page_size = flash->page_size;
- page_addr = offset / page_size;
- byte_addr = offset % page_size;
ret = spi_claim_bus(flash->spi);
if (ret) {
@@ -88,6 +86,16 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32
offset,
cmd[0] = CMD_PAGE_PROGRAM;
for (actual = 0; actual < len; actual += chunk_len) {
+ bank_sel = offset / SPI_FLASH_16MB_BOUN;
+
+ ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
+ if (ret) {
+ debug("SF: fail to set bank%d\n", bank_sel);
+ return ret;
+ }
+
+ page_addr = offset / page_size;
+ byte_addr = offset % page_size;
chunk_len = min(len - actual, page_size - byte_addr);
if (flash->spi->max_write_size)
@@ -117,11 +125,7 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32
offset,
if (ret)
break;
- byte_addr += chunk_len;
- if (byte_addr == page_size) {
- page_addr++;
- byte_addr = 0;
- }
+ offset += chunk_len;
}
spi_release_bus(flash->spi);
@@ -204,9 +208,9 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash,
unsigned long timeout)
int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len)
{
- u32 end, erase_size;
+ u32 erase_size;
int ret;
- u8 cmd[4];
+ u8 cmd[4], bank_sel;
erase_size = flash->sector_size;
if (offset % erase_size || len % erase_size) {
@@ -224,11 +228,17 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u32
offset, size_t len)
cmd[0] = CMD_ERASE_4K;
else
cmd[0] = CMD_ERASE_64K;
- end = offset + len;
- while (offset < end) {
+ while (len) {
+ bank_sel = offset / SPI_FLASH_16MB_BOUN;
+
+ ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
+ if (ret) {
+ debug("SF: fail to set bank%d\n", bank_sel);
+ return ret;
+ }
+
spi_flash_addr(offset, cmd);
- offset += erase_size;
debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
cmd[2], cmd[3], offset);
@@ -244,6 +254,9 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u32
offset, size_t len)
ret = spi_flash_cmd_wait_ready(flash,
SPI_FLASH_PAGE_ERASE_TIMEOUT);
if (ret)
goto out;
+
+ offset += erase_size;
+ len -= erase_size;
}
out:
--
1.8.3
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[U-Boot] [PATH v5 03/14] sf: Read flash bank addr register at probe time
Read the flash bank addr register to get the state of bank in
a perticular flash. and also bank write happens only when there is
a change in bank selection from user.
bank read only valid for flashes which has > 16Mbytes those are
opearted in 3-byte addr mode, each bank occupies 16Mytes.
Suppose if the flash has 64Mbytes size consists of 4 banks like
bank0, bank1, bank2 and bank3.
Signed-off-by: Jagannadha Sutradharudu Teki
Reviewed-by: Simon Glass
---
Changes for v5:
- bank_read_cmd <= bank_cmd[0]
- bank_write_cmd <= bank_cmd[1]
Changes for v4:
- Added spi_flash_bank_config
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/spi_flash.c | 27 +++
drivers/mtd/spi/spi_flash_internal.h | 2 ++
include/spi_flash.h | 2 ++
3 files changed, 31 insertions(+)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 7e19953..64b57ec 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -283,6 +283,12 @@ int spi_flash_cmd_bankaddr_write(struct spi_flash *flash,
u8 bank_sel)
u8 cmd;
int ret;
+ if (flash->bank_curr == bank_sel) {
+ debug("SF: not require to enable bank%d\n", bank_sel);
+ return 0;
+ }
+
+ cmd = flash->bank_write_cmd;
ret = spi_flash_cmd_write_enable(flash);
if (ret < 0) {
debug("SF: enabling write failed\n");
@@ -294,6 +300,7 @@ int spi_flash_cmd_bankaddr_write(struct spi_flash *flash,
u8 bank_sel)
debug("SF: fail to write bank addr register\n");
return ret;
}
+ flash->bank_curr = bank_sel;
ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
if (ret < 0) {
@@ -306,6 +313,9 @@ int spi_flash_cmd_bankaddr_write(struct spi_flash *flash,
u8 bank_sel)
int spi_flash_bank_config(struct spi_flash *flash, u8 idcode0)
{
+ u8 cmd;
+ u8 curr_bank = 0;
+
/* discover bank cmds */
switch (idcode0) {
case SPI_FLASH_SPANSION_IDCODE0:
@@ -322,6 +332,18 @@ int spi_flash_bank_config(struct spi_flash *flash, u8
idcode0)
return -1;
}
+ /* read the bank reg - on which bank the flash is in currently */
+ cmd = flash->bank_read_cmd;
+ if (flash->size > SPI_FLASH_16MB_BOUN) {
+ if (spi_flash_read_common(flash, &cmd, 1, &curr_bank, 1)) {
+ debug("SF: fail to read bank addr register\n");
+ return -1;
+ }
+ flash->bank_curr = curr_bank;
+ } else {
+ flash->bank_curr = curr_bank;
+ }
+
return 0;
}
@@ -469,6 +491,11 @@ struct spi_flash *spi_flash_probe(unsigned int bus,
unsigned int cs,
goto err_manufacturer_probe;
}
+ /* Configure the BAR - disover bank cmds and read current bank */
+ ret = spi_flash_bank_config(flash, *idp);
+ if (ret < 0)
+ goto err_manufacturer_probe;
+
#ifdef CONFIG_OF_CONTROL
if (spi_flash_decode_fdt(gd->fdt_blob, flash)) {
debug("SF: FDT decode error\n");
diff --git a/drivers/mtd/spi/spi_flash_internal.h
b/drivers/mtd/spi/spi_flash_internal.h
index db6c444..00ed1ee 100644
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -28,6 +28,8 @@
#define CMD_ERASE_64K 0xd8
#define CMD_ERASE_CHIP 0xc7
+#define SPI_FLASH_16MB_BOUN0x100
+
/* Manufacture ID's */
#define SPI_FLASH_SPANSION_IDCODE0 0x01
#define SPI_FLASH_STMICRO_IDCODE0 0x20
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 38587c2..91b43ee 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -42,6 +42,8 @@ struct spi_flash {
u8 bank_read_cmd;
/* Bank write cmd */
u8 bank_write_cmd;
+ /* Current flash bank */
+ u8 bank_curr;
void *memory_map; /* Address of read-only SPI flash access */
int (*read)(struct spi_flash *flash, u32 offset,
--
1.8.3
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[U-Boot] [PATH v5 11/14] sf: stmicro: Add support for N25Q1024A
Add support for Numonyx N25Q1024A SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki
---
Changes for v5:
- none
Changes for v4:
- none
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/stmicro.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c
index cac1013..ef4b911 100644
--- a/drivers/mtd/spi/stmicro.c
+++ b/drivers/mtd/spi/stmicro.c
@@ -158,6 +158,12 @@ static const struct stmicro_spi_flash_params
stmicro_spi_flash_table[] = {
.nr_sectors = 2048,
.name = "N25Q1024",
},
+ {
+ .id = 0xbb21,
+ .pages_per_sector = 256,
+ .nr_sectors = 2048,
+ .name = "N25Q1024A",
+ },
};
struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode)
--
1.8.3
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[U-Boot] [PATH v5 14/14] sf: Add flag status register polling support
Flag status register polling is required for micron 512Mb flash
devices onwards, for performing erase/program operations.
Like polling for WIP(Write-In-Progress) bit in read status register,
spi_flash_cmd_wait_ready will poll for PEC(Program-Erase-Control)
bit in flag status register.
Signed-off-by: Jagannadha Sutradharudu Teki
Reviewed-by: Simon Glass
---
Changes for v5:
- move flag_status assignment to stmicro driver
Changes for v4:
- Remove STMICRO config, discover poll_cmd at probe
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/spi_flash.c | 16
drivers/mtd/spi/spi_flash_internal.h | 2 ++
drivers/mtd/spi/stmicro.c| 4
include/spi_flash.h | 3 +++
4 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index cca02d1..6ce82c1 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -200,12 +200,19 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash,
unsigned long timeout)
unsigned long timebase;
int ret;
u8 status;
+ u8 check_status = 0x0;
u8 poll_bit = STATUS_WIP;
- u8 cmd = CMD_READ_STATUS;
+ u8 cmd = flash->poll_cmd;
+
+ if (cmd == CMD_FLAG_STATUS) {
+ poll_bit = STATUS_PEC;
+ check_status = poll_bit;
+ }
ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
if (ret) {
- debug("SF: Failed to send command %02x: %d\n", cmd, ret);
+ debug("SF: fail to read %s status register\n",
+ cmd == CMD_READ_STATUS ? "read" : "flag");
return ret;
}
@@ -217,14 +224,14 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash,
unsigned long timeout)
if (ret)
return -1;
- if ((status & poll_bit) == 0)
+ if ((status & poll_bit) == check_status)
break;
} while (get_timer(timebase) < timeout);
spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
- if ((status & poll_bit) == 0)
+ if ((status & poll_bit) == check_status)
return 0;
/* Timed out */
@@ -584,6 +591,7 @@ void *spi_flash_do_alloc(int offset, int size, struct
spi_slave *spi,
/* Set up some basic fields - caller will sort out sizes */
flash->spi = spi;
flash->name = name;
+ flash->poll_cmd = CMD_READ_STATUS;
flash->read = spi_flash_cmd_read_fast;
flash->write = spi_flash_cmd_write_multi;
diff --git a/drivers/mtd/spi/spi_flash_internal.h
b/drivers/mtd/spi/spi_flash_internal.h
index e9b85bf..8147f27 100644
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -22,6 +22,7 @@
#define CMD_PAGE_PROGRAM 0x02
#define CMD_WRITE_DISABLE 0x04
#define CMD_READ_STATUS0x05
+#define CMD_FLAG_STATUS0x70
#define CMD_WRITE_ENABLE 0x06
#define CMD_ERASE_4K 0x20
#define CMD_ERASE_32K 0x52
@@ -45,6 +46,7 @@
/* Common status */
#define STATUS_WIP 0x01
+#define STATUS_PEC 0x80
/* Send a single-byte command to the device and read the response */
int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c
index ef4b911..7e41ee1 100644
--- a/drivers/mtd/spi/stmicro.c
+++ b/drivers/mtd/spi/stmicro.c
@@ -210,5 +210,9 @@ struct spi_flash *spi_flash_probe_stmicro(struct spi_slave
*spi, u8 * idcode)
flash->sector_size = 256 * params->pages_per_sector;
flash->size = flash->sector_size * params->nr_sectors;
+ /* for >= 512MiB flashes, use flag status instead of read_status */
+ if (flash->size >= 0x400)
+ flash->poll_cmd = CMD_FLAG_STATUS;
+
return flash;
}
diff --git a/include/spi_flash.h b/include/spi_flash.h
index e22d698..e80785f 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -46,6 +46,9 @@ struct spi_flash {
/* Current flash bank */
u8 bank_curr;
#endif
+ /* Poll cmd - for flash erase/program */
+ u8 poll_cmd;
+
void *memory_map; /* Address of read-only SPI flash access */
int (*read)(struct spi_flash *flash, u32 offset,
size_t len, void *buf);
--
1.8.3
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[U-Boot] [PATH v5 09/14] sf: stmicro: Add support for N25Q512A
Add support for Numonyx N25Q512A SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki
---
Changes for v5:
- none
Changes for v4:
- none
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/stmicro.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c
index e9adfa5..bf61a37 100644
--- a/drivers/mtd/spi/stmicro.c
+++ b/drivers/mtd/spi/stmicro.c
@@ -146,6 +146,12 @@ static const struct stmicro_spi_flash_params
stmicro_spi_flash_table[] = {
.nr_sectors = 1024,
.name = "N25Q512",
},
+ {
+ .id = 0xbb20,
+ .pages_per_sector = 256,
+ .nr_sectors = 1024,
+ .name = "N25Q512A",
+ },
};
struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode)
--
1.8.3
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[U-Boot] [PATH v5 07/14] sf: Use spi_flash_addr() in write call
Use the existing spi_flash_addr() for 3-byte addressing
cmd filling in write call.
Signed-off-by: Jagannadha Sutradharudu Teki
Reviewed-by: Simon Glass
---
Changes for v5:
- none
Changes for v4:
- none
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/spi_flash.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index f05f8f4..0ed2295 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -71,7 +71,7 @@ int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd,
size_t cmd_len,
int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset,
size_t len, const void *buf)
{
- unsigned long page_addr, byte_addr, page_size;
+ unsigned long byte_addr, page_size;
size_t chunk_len, actual;
int ret;
u8 cmd[4];
@@ -97,16 +97,13 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32
offset,
return ret;
}
#endif
- page_addr = offset / page_size;
byte_addr = offset % page_size;
chunk_len = min(len - actual, page_size - byte_addr);
if (flash->spi->max_write_size)
chunk_len = min(chunk_len, flash->spi->max_write_size);
- cmd[1] = page_addr >> 8;
- cmd[2] = page_addr;
- cmd[3] = byte_addr;
+ spi_flash_addr(offset, cmd);
debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len =
%zu\n",
buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
--
1.8.3
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Re: [U-Boot] [PATCH 1/4 V5] EXYNOS5: FDT: Add compatible strings for Serial
Dear Rajeshwari Shinde,
On 17 May 2013 20:03, Rajeshwari Shinde wrote:
> Add required compatible information for s5p serial driver
>
> Signed-off-by: Abhilash Kesavan
> Signed-off-by: Rajeshwari Shinde
> Acked-by: Simon Glass
> ---
> Changes in V2:
> - Changed the compatible string to "samsung,exynos4210-uart"
> Changes in V3:
> - Rebased on latest u-boot-samsung
> Changes in V4:
> - Rebased on latest u-boot-samsung
> - Changed to COMPAT_SAMSUNG_EXYNOS5_SERIAL to
> COMPAT_SAMSUNG_EXYNOS_SERIAL
> Changes in V5:
> - None
> include/fdtdec.h |1 +
> lib/fdtdec.c |1 +
> 2 files changed, 2 insertions(+), 0 deletions(-)
>
> diff --git a/include/fdtdec.h b/include/fdtdec.h
> index 844991e..7f78dbc 100644
> --- a/include/fdtdec.h
> +++ b/include/fdtdec.h
> @@ -92,6 +92,7 @@ enum fdt_compat_id {
> COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */
> COMPAT_GENERIC_SPI_FLASH, /* Generic SPI Flash chip */
> COMPAT_MAXIM_98095_CODEC, /* MAX98095 Codec */
> + COMPAT_SAMSUNG_EXYNOS_SERIAL, /* Exynos UART */
>
Why don't you gather with SAMSUNG stuffs?
>
> COMPAT_COUNT,
> };
> diff --git a/lib/fdtdec.c b/lib/fdtdec.c
> index 403babd..b141211 100644
> --- a/lib/fdtdec.c
> +++ b/lib/fdtdec.c
> @@ -65,6 +65,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
> COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686_pmic"),
> COMPAT(GENERIC_SPI_FLASH, "spi-flash"),
> COMPAT(MAXIM_98095_CODEC, "maxim,max98095-codec"),
> + COMPAT(SAMSUNG_EXYNOS_SERIAL, "samsung,exynos4210-uart"),
>
ditto.
> };
>
> const char *fdtdec_get_compatible(enum fdt_compat_id id)
> --
> 1.7.4.4
>
> ___
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> http://lists.denx.de/mailman/listinfo/u-boot
>
Thanks,
Minkyu Kang.
--
from. prom.
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[U-Boot] [PATH v5 01/14] sf: Add bank address register writing support
This patch provides support to program a flash bank address
register.
extended/bank address register contains an information to access
the 4th byte addressing in 3-byte address mode.
reff' the spec for more details about bank addr register
in Page-63, Table 8.16
http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf
Signed-off-by: Jagannadha Sutradharudu Teki
Reviewed-by: Simon Glass
---
Changes for v5:
- none
Changes for v4:
- remove bank cmds
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/spi_flash.c | 26 ++
drivers/mtd/spi/spi_flash_internal.h | 3 +++
2 files changed, 29 insertions(+)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 0e38f59..9ddd070 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -278,6 +278,32 @@ int spi_flash_cmd_write_status(struct spi_flash *flash, u8
sr)
return 0;
}
+int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
+{
+ u8 cmd;
+ int ret;
+
+ ret = spi_flash_cmd_write_enable(flash);
+ if (ret < 0) {
+ debug("SF: enabling write failed\n");
+ return ret;
+ }
+
+ ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &bank_sel, 1);
+ if (ret) {
+ debug("SF: fail to write bank addr register\n");
+ return ret;
+ }
+
+ ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+ if (ret < 0) {
+ debug("SF: write bank addr register timed out\n");
+ return ret;
+ }
+
+ return 0;
+}
+
#ifdef CONFIG_OF_CONTROL
int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
{
diff --git a/drivers/mtd/spi/spi_flash_internal.h
b/drivers/mtd/spi/spi_flash_internal.h
index 141cfa8..772fef6 100644
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -77,6 +77,9 @@ static inline int spi_flash_cmd_write_disable(struct
spi_flash *flash)
/* Program the status register. */
int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
+/* Program the bank address register */
+int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel);
+
/*
* Same as spi_flash_cmd_read() except it also claims/releases the SPI
* bus. Used as common part of the ->read() operation.
--
1.8.3
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[U-Boot] [PATH v5 06/14] sf: Add bank addr code in CONFIG_SPI_FLASH_BAR
Defined bank addr code on CONFIG_SPI_FLASH_BAR macro, to reduce the
size for existing boards which has < 16Mbytes SPI flashes.
It's upto user which has provision to use the bank addr code for
flashes which has > 16Mbytes.
Signed-off-by: Jagannadha Sutradharudu Teki
Reviewed-by: Simon Glass
---
Changes for v5:
- none
Changes for v4:
- rebase of 02/14
Changes for v3:
- none
Changes for v2:
- none
README | 5 +
drivers/mtd/spi/spi_flash.c | 23 +--
drivers/mtd/spi/spi_flash_internal.h | 12
include/spi_flash.h | 3 ++-
4 files changed, 32 insertions(+), 11 deletions(-)
diff --git a/README b/README
index ac1ec44..3df1b86 100644
--- a/README
+++ b/README
@@ -2509,6 +2509,11 @@ CBFS (Coreboot Filesystem) support
Define this option to include a destructive SPI flash
test ('sf test').
+ CONFIG_SPI_FLASH_BARBan/Extended Addr Reg
+
+ Define this option to use the Bank addr/Extended addr
+ support on SPI flashes which has size > 16Mbytes.
+
- SystemACE Support:
CONFIG_SYSTEMACE
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 562f6ad..f05f8f4 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -74,7 +74,7 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32
offset,
unsigned long page_addr, byte_addr, page_size;
size_t chunk_len, actual;
int ret;
- u8 cmd[4], bank_sel;
+ u8 cmd[4];
page_size = flash->page_size;
@@ -86,6 +86,9 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32
offset,
cmd[0] = CMD_PAGE_PROGRAM;
for (actual = 0; actual < len; actual += chunk_len) {
+#ifdef CONFIG_SPI_FLASH_BAR
+ u8 bank_sel;
+
bank_sel = offset / SPI_FLASH_16MB_BOUN;
ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
@@ -93,7 +96,7 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32
offset,
debug("SF: fail to set bank%d\n", bank_sel);
return ret;
}
-
+#endif
page_addr = offset / page_size;
byte_addr = offset % page_size;
chunk_len = min(len - actual, page_size - byte_addr);
@@ -148,7 +151,7 @@ int spi_flash_read_common(struct spi_flash *flash, const u8
*cmd,
int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
- u8 cmd[5], bank_sel;
+ u8 cmd[5], bank_sel = 0;
u32 remain_len, read_len;
int ret = -1;
@@ -162,6 +165,7 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash, u32
offset,
cmd[4] = 0x00;
while (len) {
+#ifdef CONFIG_SPI_FLASH_BAR
bank_sel = offset / SPI_FLASH_16MB_BOUN;
ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
@@ -169,7 +173,7 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash, u32
offset,
debug("SF: fail to set bank%d\n", bank_sel);
return ret;
}
-
+#endif
remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1) - offset);
if (len < remain_len)
read_len = len;
@@ -240,7 +244,7 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u32
offset, size_t len)
{
u32 erase_size;
int ret;
- u8 cmd[4], bank_sel;
+ u8 cmd[4];
erase_size = flash->sector_size;
if (offset % erase_size || len % erase_size) {
@@ -260,6 +264,9 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u32
offset, size_t len)
cmd[0] = CMD_ERASE_64K;
while (len) {
+#ifdef CONFIG_SPI_FLASH_BAR
+ u8 bank_sel;
+
bank_sel = offset / SPI_FLASH_16MB_BOUN;
ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
@@ -267,7 +274,7 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u32
offset, size_t len)
debug("SF: fail to set bank%d\n", bank_sel);
return ret;
}
-
+#endif
spi_flash_addr(offset, cmd);
debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
@@ -321,6 +328,7 @@ int spi_flash_cmd_write_status(struct spi_flash *flash, u8
sr)
return 0;
}
+#ifdef CONFIG_SPI_FLASH_BAR
int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
{
u8 cmd;
@@ -389,6 +397,7 @@ int spi_flash_bank_config(struct spi_flash *flash, u8
idcode0)
return 0;
}
+#endif
#ifdef CONFIG_OF_CONTROL
int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
@@ -534,10 +543,12 @@ struct spi_flash *spi_flash_probe(unsigned int bus,
unsigned int cs,
goto err_manufacturer_probe;
}
+#ifdef CONFIG_SPI_F
[U-Boot] [PATH v5 02/14] sf: Discover the bank addr commands
Bank/Extended addr commands are specific to particular
flash vendor so discover them based on the idocode0.
Assign the discovered bank commands to spi_flash members
so-that the bank read/write will use their specific operations.
Signed-off-by: Jagannadha Sutradharudu Teki
---
Changes for v5:
- bank_read_cmd <= bank_cmd[0]
- bank_write_cmd <= bank_cmd[1]
Changes for v4:
- none
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/spi_flash.c | 21 +
drivers/mtd/spi/spi_flash_internal.h | 14 ++
include/spi_flash.h | 4
3 files changed, 39 insertions(+)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 9ddd070..7e19953 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -304,6 +304,27 @@ int spi_flash_cmd_bankaddr_write(struct spi_flash *flash,
u8 bank_sel)
return 0;
}
+int spi_flash_bank_config(struct spi_flash *flash, u8 idcode0)
+{
+ /* discover bank cmds */
+ switch (idcode0) {
+ case SPI_FLASH_SPANSION_IDCODE0:
+ flash->bank_read_cmd = CMD_BANKADDR_BRRD;
+ flash->bank_write_cmd = CMD_BANKADDR_BRWR;
+ break;
+ case SPI_FLASH_STMICRO_IDCODE0:
+ case SPI_FLASH_WINBOND_IDCODE0:
+ flash->bank_read_cmd = CMD_EXTNADDR_RDEAR;
+ flash->bank_write_cmd = CMD_EXTNADDR_WREAR;
+ break;
+ default:
+ printf("SF: Unsupported bank commands %02x\n", idcode0);
+ return -1;
+ }
+
+ return 0;
+}
+
#ifdef CONFIG_OF_CONTROL
int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
{
diff --git a/drivers/mtd/spi/spi_flash_internal.h
b/drivers/mtd/spi/spi_flash_internal.h
index 772fef6..db6c444 100644
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -28,6 +28,17 @@
#define CMD_ERASE_64K 0xd8
#define CMD_ERASE_CHIP 0xc7
+/* Manufacture ID's */
+#define SPI_FLASH_SPANSION_IDCODE0 0x01
+#define SPI_FLASH_STMICRO_IDCODE0 0x20
+#define SPI_FLASH_WINBOND_IDCODE0 0xef
+
+/* Bank addr access commands */
+#define CMD_BANKADDR_BRWR 0x17
+#define CMD_BANKADDR_BRRD 0x16
+#define CMD_EXTNADDR_WREAR 0xC5
+#define CMD_EXTNADDR_RDEAR 0xC8
+
/* Common status */
#define STATUS_WIP 0x01
@@ -80,6 +91,9 @@ int spi_flash_cmd_write_status(struct spi_flash *flash, u8
sr);
/* Program the bank address register */
int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel);
+/* Configure the BAR - discover the bank cmds */
+int spi_flash_bank_config(struct spi_flash *flash, u8 idcode0);
+
/*
* Same as spi_flash_cmd_read() except it also claims/releases the SPI
* bus. Used as common part of the ->read() operation.
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 3b6a44e..38587c2 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -38,6 +38,10 @@ struct spi_flash {
u32 page_size;
/* Erase (sector) size */
u32 sector_size;
+ /* Bank read cmd */
+ u8 bank_read_cmd;
+ /* Bank write cmd */
+ u8 bank_write_cmd;
void *memory_map; /* Address of read-only SPI flash access */
int (*read)(struct spi_flash *flash, u32 offset,
--
1.8.3
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[U-Boot] [PATH v5 08/14] sf: stmicro: Add support for N25Q512
Add support for Numonyx N25Q512 SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki
---
Changes for v5:
- none
Changes for v4:
- none
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/stmicro.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c
index 2a9972b..e9adfa5 100644
--- a/drivers/mtd/spi/stmicro.c
+++ b/drivers/mtd/spi/stmicro.c
@@ -140,6 +140,12 @@ static const struct stmicro_spi_flash_params
stmicro_spi_flash_table[] = {
.nr_sectors = 512,
.name = "N25Q256A",
},
+ {
+ .id = 0xba20,
+ .pages_per_sector = 256,
+ .nr_sectors = 1024,
+ .name = "N25Q512",
+ },
};
struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode)
--
1.8.3
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[U-Boot] [PATH v5 05/14] sf: Update sf read to support all sizes of flashes
This patch updated the spi_flash read func to support all
sizes of flashes using bank reg addr facility.
The same support has been added in below patch for erase/write
spi_flash functions:
"sf: Support all sizes of flashes using bank addr reg facility"
(sha1: c956f600cbb0943d0afe1004cdb503f4fcd8f415)
With these new updates on sf framework, the flashes which has < 16MB
are not effected as per as performance is concern and but the
u-boot.bin size incrased ~460 bytes.
sf update(for first 16MBytes), Changes before:
U-Boot> sf update 0x100 0x0 0x100
- N25Q256
16777216 bytes written, 0 bytes skipped in 199.72s, speed 86480 B/s
- W25Q128BV
16777216 bytes written, 0 bytes skipped in 351.739s, speed 48913 B/s
- S25FL256S_64K
16777216 bytes written, 0 bytes skipped in 65.659s, speed 262144 B/s
sf update(for first 16MBytes), Changes before:
U-Boot> sf update 0x100 0x0 0x100
- N25Q256
16777216 bytes written, 0 bytes skipped in 198.953s, speed 86480 B/s
- W25Q128BV
16777216 bytes written, 0 bytes skipped in 350.90s, speed 49200 B/s
- S25FL256S_64K
16777216 bytes written, 0 bytes skipped in 66.521s, speed 262144 B/s
Signed-off-by: Jagannadha Sutradharudu Teki
Reviewed-by: Simon Glass
---
Changes for v5:
- none
Changes for v4:
- none
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/spi_flash.c | 36 +---
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 7f1ef17..562f6ad 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -148,7 +148,9 @@ int spi_flash_read_common(struct spi_flash *flash, const u8
*cmd,
int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
- u8 cmd[5];
+ u8 cmd[5], bank_sel;
+ u32 remain_len, read_len;
+ int ret = -1;
/* Handle memory-mapped SPI */
if (flash->memory_map) {
@@ -157,10 +159,38 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash, u32
offset,
}
cmd[0] = CMD_READ_ARRAY_FAST;
- spi_flash_addr(offset, cmd);
cmd[4] = 0x00;
- return spi_flash_read_common(flash, cmd, sizeof(cmd), data, len);
+ while (len) {
+ bank_sel = offset / SPI_FLASH_16MB_BOUN;
+
+ ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
+ if (ret) {
+ debug("SF: fail to set bank%d\n", bank_sel);
+ return ret;
+ }
+
+ remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1) - offset);
+ if (len < remain_len)
+ read_len = len;
+ else
+ read_len = remain_len;
+
+ spi_flash_addr(offset, cmd);
+
+ ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
+ data, read_len);
+ if (ret < 0) {
+ debug("SF: read failed\n");
+ break;
+ }
+
+ offset += read_len;
+ len -= read_len;
+ data += read_len;
+ }
+
+ return ret;
}
int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout,
--
1.8.3
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[U-Boot] [PATH v5 00/14] sf: Update sf framework to support all sizes of flashes
This is a v5 patch series with some modifications on previous series with same head "sf: Update sf framework to support all sizes of flashes" The current implementation in sf supports 3-byte address mode due to this up to 16MB amount of flash is able to access for those flashes which has an actual size of > 16MB. This series of patches is more detailed/meatured changes w.r.t the current sf framework in addition to changes related to support all sizes using bank/exnt register addr accessing support. With these new updates on sf framework, the flashes which has < 16MB are not effected as per as performance is concern and but the u-boot.bin size incrased ~460 bytes. sf update(for first 16MBytes), Changes before: U-Boot> sf update 0x100 0x0 0x100 - N25Q256 16777216 bytes written, 0 bytes skipped in 199.72s, speed 86480 B/s - W25Q128BV 16777216 bytes written, 0 bytes skipped in 351.739s, speed 48913 B/s - S25FL256S_64K 16777216 bytes written, 0 bytes skipped in 65.659s, speed 262144 B/s sf update(for first 16MBytes), Changes after: U-Boot> sf update 0x100 0x0 0x100 - N25Q256 16777216 bytes written, 0 bytes skipped in 198.953s, speed 86480 B/s - W25Q128BV 16777216 bytes written, 0 bytes skipped in 350.90s, speed 49200 B/s - S25FL256S_64K 16777216 bytes written, 0 bytes skipped in 66.521s, speed 262144 B/s The main aim of these changes is to not effect the current framework and at the same time to support the > 16Mbyte flashes, becuase of this I involved few flash vendor people in CC [thought that they may/mayn't be a mailing list members] to know their views. REQUEST FOR ALL SPI CODE CONTRIBUTORS/USERS, PLEASE TEST THESE CHANGES W.R.T YOUR HW IF POSSIBLE. Please let me know for any issues/concerns/questions. -- Thanks, Jagan. Jagannadha Sutradharudu Teki (14): sf: Add bank address register writing support sf: Discover the bank addr commands sf: Read flash bank addr register at probe time sf: Update sf to support all sizes of flashes sf: Update sf read to support all sizes of flashes sf: Add bank addr code in CONFIG_SPI_FLASH_BAR sf: Use spi_flash_addr() in write call sf: stmicro: Add support for N25Q512 sf: stmicro: Add support for N25Q512A sf: stmicro: Add support for N25Q1024 sf: stmicro: Add support for N25Q1024A sf: spansion: Add support for S25FL512S_64K sf: Remove spi_flash_cmd_poll_bit() sf: Add flag status register polling support README | 5 + drivers/mtd/spi/spansion.c | 7 ++ drivers/mtd/spi/spi_flash.c | 186 +-- drivers/mtd/spi/spi_flash_internal.h | 29 +- drivers/mtd/spi/stmicro.c| 28 ++ include/spi_flash.h | 10 ++ 6 files changed, 232 insertions(+), 33 deletions(-) -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATH v5 12/14] sf: spansion: Add support for S25FL512S_64K
Add support for Spansion S25FL512S_64K SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki
---
Changes for v5:
- none
Changes for v4:
- none
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/spansion.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c
index dad4fbb..3ec2151 100644
--- a/drivers/mtd/spi/spansion.c
+++ b/drivers/mtd/spi/spansion.c
@@ -110,6 +110,13 @@ static const struct spansion_spi_flash_params
spansion_spi_flash_table[] = {
.nr_sectors = 512,
.name = "S25FL256S_64K",
},
+ {
+ .idcode1 = 0x0220,
+ .idcode2 = 0x4d01,
+ .pages_per_sector = 256,
+ .nr_sectors = 1024,
+ .name = "S25FL512S_64K",
+ },
};
struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode)
--
1.8.3
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[U-Boot] [PATH v5 10/14] sf: stmicro: Add support for N25Q1024
Add support for Numonyx N25Q1024 SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki
---
Changes for v5:
- none
Changes for v4:
- none
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/stmicro.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c
index bf61a37..cac1013 100644
--- a/drivers/mtd/spi/stmicro.c
+++ b/drivers/mtd/spi/stmicro.c
@@ -152,6 +152,12 @@ static const struct stmicro_spi_flash_params
stmicro_spi_flash_table[] = {
.nr_sectors = 1024,
.name = "N25Q512A",
},
+ {
+ .id = 0xba21,
+ .pages_per_sector = 256,
+ .nr_sectors = 2048,
+ .name = "N25Q1024",
+ },
};
struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode)
--
1.8.3
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[U-Boot] [PATCH v3 2/4] sf: Place the sf calls in proper order
From: Jagannadha Sutradharudu Teki
Placed the sf calls in proper order - erase/write/read
Signed-off-by: Jagannadha Sutradharudu Teki
---
Changes for v3:
-
Changes for v2:
-
drivers/mtd/spi/spi_flash.c | 184 ++--
1 file changed, 92 insertions(+), 92 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 03cecef..a329850 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -68,6 +68,51 @@ int spi_flash_cmd_write(struct spi_slave *spi, const u8
*cmd, size_t cmd_len,
return spi_flash_read_write(spi, cmd, cmd_len, data, NULL, data_len);
}
+int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
+{
+ struct spi_slave *spi = flash->spi;
+ unsigned long timebase;
+ int ret;
+ u8 status;
+ u8 check_status = 0x0;
+ u8 poll_bit = STATUS_WIP;
+ u8 cmd = flash->poll_cmd;
+
+ if (cmd == CMD_FLAG_STATUS) {
+ poll_bit = STATUS_PEC;
+ check_status = poll_bit;
+ }
+
+ ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
+ if (ret) {
+ debug("SF: fail to read %s status register\n",
+ cmd == CMD_READ_STATUS ? "read" : "flag");
+ return ret;
+ }
+
+ timebase = get_timer(0);
+ do {
+ WATCHDOG_RESET();
+
+ ret = spi_xfer(spi, 8, NULL, &status, 0);
+ if (ret)
+ return -1;
+
+ if ((status & poll_bit) == check_status)
+ break;
+
+ } while (get_timer(timebase) < timeout);
+
+ spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
+
+ if ((status & poll_bit) == check_status)
+ return 0;
+
+ /* Timed out */
+ debug("SF: time out!\n");
+ return -1;
+}
+
int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
size_t cmd_len, const void *buf, size_t buf_len)
{
@@ -109,6 +154,53 @@ int spi_flash_write_common(struct spi_flash *flash, const
u8 *cmd,
return ret;
}
+int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len)
+{
+ u32 erase_size;
+ u8 cmd[4];
+ int ret = -1;
+
+ erase_size = flash->sector_size;
+ if (offset % erase_size || len % erase_size) {
+ debug("SF: Erase offset/length not multiple of erase size\n");
+ return -1;
+ }
+
+ if (erase_size == 4096)
+ cmd[0] = CMD_ERASE_4K;
+ else
+ cmd[0] = CMD_ERASE_64K;
+
+ while (len) {
+#ifdef CONFIG_SPI_FLASH_BAR
+ u8 bank_sel;
+
+ bank_sel = offset / SPI_FLASH_16MB_BOUN;
+
+ ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
+ if (ret) {
+ debug("SF: fail to set bank%d\n", bank_sel);
+ return ret;
+ }
+#endif
+ spi_flash_addr(offset, cmd);
+
+ debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
+ cmd[2], cmd[3], offset);
+
+ ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
+ if (ret < 0) {
+ debug("SF: erase failed\n");
+ break;
+ }
+
+ offset += erase_size;
+ len -= erase_size;
+ }
+
+ return ret;
+}
+
int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset,
size_t len, const void *buf)
{
@@ -218,98 +310,6 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash, u32
offset,
return ret;
}
-int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
-{
- struct spi_slave *spi = flash->spi;
- unsigned long timebase;
- int ret;
- u8 status;
- u8 check_status = 0x0;
- u8 poll_bit = STATUS_WIP;
- u8 cmd = flash->poll_cmd;
-
- if (cmd == CMD_FLAG_STATUS) {
- poll_bit = STATUS_PEC;
- check_status = poll_bit;
- }
-
- ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
- if (ret) {
- debug("SF: fail to read %s status register\n",
- cmd == CMD_READ_STATUS ? "read" : "flag");
- return ret;
- }
-
- timebase = get_timer(0);
- do {
- WATCHDOG_RESET();
-
- ret = spi_xfer(spi, 8, NULL, &status, 0);
- if (ret)
- return -1;
-
- if ((status & poll_bit) == check_status)
- break;
-
- } while (get_timer(timebase) < timeout);
-
- spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
-
- if ((status & poll_bit) == check_status)
- return 0;
-
- /* Timed out */
- debug("SF: time out!\n");
- return -1;
-}
-
-int spi_flash_cmd_erase(struct spi_fla
[U-Boot] [PATCH v3 1/4] sf: Unify spi_flash write code
Move common flash write code into spi_flash_write_common().
Signed-off-by: Jagannadha Sutradharudu Teki
Acked-by: Simon Glass
---
Changes for v3:
- Used proper comments on spi_flash_write_common
Changes for v2:
-
drivers/mtd/spi/spi_flash.c | 120 ---
drivers/mtd/spi/spi_flash_internal.h | 10 +++
2 files changed, 63 insertions(+), 67 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 6ce82c1..03cecef 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -68,15 +68,15 @@ int spi_flash_cmd_write(struct spi_slave *spi, const u8
*cmd, size_t cmd_len,
return spi_flash_read_write(spi, cmd, cmd_len, data, NULL, data_len);
}
-int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset,
- size_t len, const void *buf)
+int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
+ size_t cmd_len, const void *buf, size_t buf_len)
{
- unsigned long byte_addr, page_size;
- size_t chunk_len, actual;
+ struct spi_slave *spi = flash->spi;
+ unsigned long timeout = SPI_FLASH_PROG_TIMEOUT;
int ret;
- u8 cmd[4];
- page_size = flash->page_size;
+ if (buf == NULL)
+ timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
ret = spi_claim_bus(flash->spi);
if (ret) {
@@ -84,6 +84,41 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32
offset,
return ret;
}
+ ret = spi_flash_cmd_write_enable(flash);
+ if (ret < 0) {
+ debug("SF: enabling write failed\n");
+ return ret;
+ }
+
+ ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len);
+ if (ret < 0) {
+ debug("SF: write cmd failed\n");
+ return ret;
+ }
+
+ ret = spi_flash_cmd_wait_ready(flash, timeout);
+ if (ret < 0) {
+ debug("SF: write %s timed out\n",
+ timeout == SPI_FLASH_PROG_TIMEOUT ?
+ "program" : "page erase");
+ return ret;
+ }
+
+ spi_release_bus(spi);
+
+ return ret;
+}
+
+int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset,
+ size_t len, const void *buf)
+{
+ unsigned long byte_addr, page_size;
+ size_t chunk_len, actual;
+ u8 cmd[4];
+ int ret = -1;
+
+ page_size = flash->page_size;
+
cmd[0] = CMD_PAGE_PROGRAM;
for (actual = 0; actual < len; actual += chunk_len) {
#ifdef CONFIG_SPI_FLASH_BAR
@@ -108,27 +143,16 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash,
u32 offset,
debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len =
%zu\n",
buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
- ret = spi_flash_cmd_write_enable(flash);
- if (ret < 0) {
- debug("SF: enabling write failed\n");
- break;
- }
-
- ret = spi_flash_cmd_write(flash->spi, cmd, 4,
- buf + actual, chunk_len);
+ ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
+ buf + actual, chunk_len);
if (ret < 0) {
debug("SF: write failed\n");
break;
}
- ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
- if (ret)
- break;
-
offset += chunk_len;
}
- spi_release_bus(flash->spi);
return ret;
}
@@ -242,8 +266,8 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash,
unsigned long timeout)
int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len)
{
u32 erase_size;
- int ret;
u8 cmd[4];
+ int ret = -1;
erase_size = flash->sector_size;
if (offset % erase_size || len % erase_size) {
@@ -251,12 +275,6 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u32
offset, size_t len)
return -1;
}
- ret = spi_claim_bus(flash->spi);
- if (ret) {
- debug("SF: Unable to claim SPI bus\n");
- return ret;
- }
-
if (erase_size == 4096)
cmd[0] = CMD_ERASE_4K;
else
@@ -279,24 +297,16 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u32
offset, size_t len)
debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
cmd[2], cmd[3], offset);
- ret = spi_flash_cmd_write_enable(flash);
- if (ret)
- goto out;
-
- ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), NULL,
0);
- if (ret)
- goto out;
-
- ret = spi_flash_cmd_wait_ready(flash,
[U-Boot] [PATCH v3 4/4] sf: Warn to use BAR for > 16MiB flashes
From: Jagannadha Sutradharudu Teki
Warning for > 16MiB flashes to #define CONFIG_SPI_FLASH_BAR
Signed-off-by: Jagannadha Sutradharudu Teki
---
Changes for v3:
-
Changes for v2:
-
drivers/mtd/spi/spi_flash.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 51142d8..a468208 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -557,6 +557,12 @@ struct spi_flash *spi_flash_probe(unsigned int bus,
unsigned int cs,
if (flash->memory_map)
printf(", mapped at %p", flash->memory_map);
puts("\n");
+#ifndef CONFIG_SPI_FLASH_BAR
+ if (flash->size > SPI_FLASH_16MB_BOUN) {
+ puts("SF: Warning - Only lower 16MiB accessible,");
+ puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
+ }
+#endif
spi_release_bus(spi);
--
1.8.3
___
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[U-Boot] [PATCH v3 3/4] sf: Add debug messages on spi_flash_read_common
- Added debug's on spi_flash_read_common()
- Added space
Signed-off-by: Jagannadha Sutradharudu Teki
---
Changes for v3:
-
Changes for v2:
-
drivers/mtd/spi/spi_flash.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index a329850..51142d8 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -254,8 +254,18 @@ int spi_flash_read_common(struct spi_flash *flash, const
u8 *cmd,
struct spi_slave *spi = flash->spi;
int ret;
- spi_claim_bus(spi);
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ debug("SF: unable to claim SPI bus\n");
+ return ret;
+ }
+
ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
+ if (ret < 0) {
+ debug("SF: read cmd failed\n");
+ return ret;
+ }
+
spi_release_bus(spi);
return ret;
--
1.8.3
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Re: [U-Boot] [PATCH] ARM: OMAP: GPIO: Fix valid range and enable usage of all GPIOs on OMAP5
Hi Axel, On 21/06/13 13:54, Axel Lin wrote: > The omap_gpio driver is used by AM33XX, OMAP3/4, OMAP54XX and DRA7XX SoCs. > These SoCs have different gpio count but currently omap_gpio driver uses hard > coded 192 which is wrong. > > This patch fixes this issue by: > 1. Move define of OMAP_MAX_GPIO to all arch/arm/include/asm/arch-omap*/gpio.h. > 2. Update gpio bank settings and enable GPIO modules 7 & 8 clocks for OMAP5. > > Thanks for Lubomir Popov to provide valuable comments to fix this issue. > > Signed-off-by: Axel Lin > --- > This patch supersedes below patches: > > [PATCH v3 1/2] gpio: omap_gpio: Fix valid gpio range for AM33XX [1] > [PATCH v3 2/2] gpio: omap_gpio: Fix valid GPIO range for OMAP5 [2] > [PATCH 1/2] OMAP5: Fix gpio_bank_54xx setting [3] > [PATCH 2/2] OMAP: gpio: Introduce get_omap_gpio_count() function to get gpio > count [4] > Applied and tested on a custom OMAP5430 board with some GPIOs from banks 7 & 8. Works OK. Tested-by: Lubomir Popov ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 2/3] ARM: Tegra: USB: EHCI: Add support for Tegra30/Tegra114
Tegra30 and Tegra114 are compatible except PLL parameters.
Tested on Tegra30 Cardhu, and Tegra114 Dalmore
platforms. All works well.
Signed-off-by: Jim Lin
---
Changes in v2:
- Move common definitions into arch-tegra/usb.h and
chip specific definitions into arch-tegraXX(X)/usb.h
- In ehci-tegra.c, add PLL parameters for Tegra30 and Tegra114.
- In ehci-tegra.c, use the port pointed by "nvidia,has-legacy-mode"
to know whether we do special handling on Port Reset.
- Remove some irrelevant whitespace changes.
- Use if-else, instead of goto in ehci-tegra.c
init_utmi_usb_controller().
- Use original coding for PTS_MASK in ehci-tegra.c
init_utmi_usb_controller().
Reason is that these bits are read-only on Tegra20.
Don't need special handling between USB1 and USB3 ports.
- Use if-else, instead of goto in ehci-tegra.c board_usb_init().
Changes in v3:
- None
Changes in v4:
- In board.c, add inclusion of asm/arch-tegra/usb.h for build warning.
- In ehci-tegra.c, modify board_usb_init to find usb nodes with compatible ID
in table fdt_usb_controllers and use matched feature flags later.
- In ehci-tegra.c, removing is_T30_compatible and is_T114_compatible variables
due to above change.
- In ehci-tegra.c, change variable port_clear_csc to port_addr_clear_csc.
- In pinmux-config-cardhu.h, chnage GMI_AD13 pinmux state to be OUTPUT
in order to be driven HIGH for Beaver board.
Changes in v5:
- Modify fdtdec.h and fdtdec.c.
- In ehci-tegra.c, use "u32 has_hostpc:1;" for alignment concern.
- Remove previous change of "pinmux-config-cardhu.h".
arch/arm/include/asm/arch-tegra/clk_rst.h | 10 +
arch/arm/include/asm/arch-tegra/usb.h | 182 -
arch/arm/include/asm/arch-tegra114/usb.h | 156 +++
arch/arm/include/asm/arch-tegra20/usb.h | 155 +++
arch/arm/include/asm/arch-tegra30/usb.h | 168
board/nvidia/common/board.c |1 +
drivers/usb/host/ehci-tegra.c | 300 +
include/fdtdec.h |2 +
lib/fdtdec.c |2 +
9 files changed, 803 insertions(+), 173 deletions(-)
create mode 100644 arch/arm/include/asm/arch-tegra114/usb.h
create mode 100644 arch/arm/include/asm/arch-tegra20/usb.h
create mode 100644 arch/arm/include/asm/arch-tegra30/usb.h
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h
b/arch/arm/include/asm/arch-tegra/clk_rst.h
index c754ec7..9b8de9c 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -225,6 +225,16 @@ enum {
IN_408_OUT_9_6_DIVISOR = 83,
};
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */
+#define PLLU_POWERDOWN (1 << 16)
+#define PLL_ENABLE_POWERDOWN (1 << 14)
+#define PLL_ACTIVE_POWERDOWN (1 << 12)
+
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 */
+#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN(1 << 4)
+#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN(1 << 2)
+#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN(1 << 0)
+
/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
#define OSC_XOBP_SHIFT 1
#define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT)
diff --git a/arch/arm/include/asm/arch-tegra/usb.h
b/arch/arm/include/asm/arch-tegra/usb.h
index ef6c089..cefe0d2 100644
--- a/arch/arm/include/asm/arch-tegra/usb.h
+++ b/arch/arm/include/asm/arch-tegra/usb.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2013 NVIDIA Corporation
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -22,120 +23,6 @@
#ifndef _TEGRA_USB_H_
#define _TEGRA_USB_H_
-
-/* USB Controller (USBx_CONTROLLER_) regs */
-struct usb_ctlr {
- /* 0x000 */
- uint id;
- uint reserved0;
- uint host;
- uint device;
-
- /* 0x010 */
- uint txbuf;
- uint rxbuf;
- uint reserved1[2];
-
- /* 0x020 */
- uint reserved2[56];
-
- /* 0x100 */
- u16 cap_length;
- u16 hci_version;
- uint hcs_params;
- uint hcc_params;
- uint reserved3[5];
-
- /* 0x120 */
- uint dci_version;
- uint dcc_params;
- uint reserved4[6];
-
- /* 0x140 */
- uint usb_cmd;
- uint usb_sts;
- uint usb_intr;
- uint frindex;
-
- /* 0x150 */
- uint reserved5;
- uint periodic_list_base;
- uint async_list_addr;
- uint async_tt_sts;
-
- /* 0x160 */
- uint burst_size;
- uint tx_fill_tuning;
- uint reserved6; /* is this port_sc1 on some controllers? */
- uint icusb_ctrl;
-
- /* 0x170 */
- uint ulpi_viewport;
- uint reserved7;
- uint endpt_nak;
- uint endpt_nak_enable;
-
- /* 0x180 */
- uint reserved;
- uint port_sc1;
- uint reserved8[6];
-
- /* 0x1a0 */
- uint reserved9;
- uint otgsc;
- uint usb_mode;
- uint endpt_setup
[U-Boot] [PATCH v5 1/3] ARM: Tegra: FDT: Add USB EHCI function for T30/T114
Add DT node for USB EHCI function.
Add support for T30-Cardhu, T30-Beaver, T114-Dalmore boards.
Signed-off-by: Jim Lin
---
Changes in v2:
- Remove PLL parameters from dt file
Changes in v3:
- Change VBus GPIO from H.05 to DD.04 for Beaver board.
Changes in v4:
- Change Beaver VBus GPIO to H.05 and value to 0 for polarity to be High.
I don't have Beaver board. So this needs somebody to help test.
Thanks.
- Change Cardhu VBus GPIO value from 3 to 1 because only bit 0 is meaningful.
Changes in v5:
- Move changes on fdtdec.h and fdtdec.c to patch 2/3
- Modify PHY type to hsic for USB2 port
arch/arm/dts/tegra114.dtsi| 27 +++
arch/arm/dts/tegra30.dtsi | 27 +++
board/nvidia/dts/tegra114-dalmore.dts |7 +++
board/nvidia/dts/tegra30-beaver.dts |6 ++
board/nvidia/dts/tegra30-cardhu.dts |6 ++
5 files changed, 73 insertions(+), 0 deletions(-)
diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi
index f86d18d..626cc3c 100644
--- a/arch/arm/dts/tegra114.dtsi
+++ b/arch/arm/dts/tegra114.dtsi
@@ -216,4 +216,31 @@
clocks = <&tegra_car 15>;
status = "disable";
};
+
+ usb@7d00 {
+ compatible = "nvidia,tegra114-ehci";
+ reg = <0x7d00 0x4000>;
+ interrupts = <52>;
+ phy_type = "utmi";
+ clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */
+ status = "disabled";
+ };
+
+ usb@7d004000 {
+ compatible = "nvidia,tegra114-ehci";
+ reg = <0x7d004000 0x4000>;
+ interrupts = <53>;
+ phy_type = "hsic";
+ clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
+ status = "disabled";
+ };
+
+ usb@7d008000 {
+ compatible = "nvidia,tegra114-ehci";
+ reg = <0x7d008000 0x4000>;
+ interrupts = <129>;
+ phy_type = "utmi";
+ clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */
+ status = "disabled";
+ };
};
diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi
index ccf154f..fee1c36 100644
--- a/arch/arm/dts/tegra30.dtsi
+++ b/arch/arm/dts/tegra30.dtsi
@@ -216,4 +216,31 @@
clocks = <&tegra_car 15>;
status = "disabled";
};
+
+ usb@7d00 {
+ compatible = "nvidia,tegra30-ehci";
+ reg = <0x7d00 0x4000>;
+ interrupts = <52>;
+ phy_type = "utmi";
+ clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */
+ status = "disabled";
+ };
+
+ usb@7d004000 {
+ compatible = "nvidia,tegra30-ehci";
+ reg = <0x7d004000 0x4000>;
+ interrupts = <53>;
+ phy_type = "hsic";
+ clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
+ status = "disabled";
+ };
+
+ usb@7d008000 {
+ compatible = "nvidia,tegra30-ehci";
+ reg = <0x7d008000 0x4000>;
+ interrupts = <129>;
+ phy_type = "utmi";
+ clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */
+ status = "disabled";
+ };
};
diff --git a/board/nvidia/dts/tegra114-dalmore.dts
b/board/nvidia/dts/tegra114-dalmore.dts
index 86e9459..435c01e 100644
--- a/board/nvidia/dts/tegra114-dalmore.dts
+++ b/board/nvidia/dts/tegra114-dalmore.dts
@@ -14,6 +14,7 @@
i2c4 = "/i2c@7000c700";
sdhci0 = "/sdhci@78000600";
sdhci1 = "/sdhci@78000400";
+ usb0 = "/usb@7d008000";
};
memory {
@@ -61,4 +62,10 @@
bus-width = <8>;
status = "okay";
};
+
+ usb@7d008000 {
+ /* SPDIF_IN: USB_VBUS_EN1 */
+ nvidia,vbus-gpio = <&gpio 86 0>;
+ status = "okay";
+ };
};
diff --git a/board/nvidia/dts/tegra30-beaver.dts
b/board/nvidia/dts/tegra30-beaver.dts
index 836169f..a7cc93e 100644
--- a/board/nvidia/dts/tegra30-beaver.dts
+++ b/board/nvidia/dts/tegra30-beaver.dts
@@ -14,6 +14,7 @@
i2c4 = "/i2c@7000c700";
sdhci0 = "/sdhci@78000600";
sdhci1 = "/sdhci@7800";
+ usb0 = "/usb@7d008000";
};
memory {
@@ -68,4 +69,9 @@
status = "okay";
bus-width = <8>;
};
+
+ usb@7d008000 {
+ nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */
+ status = "okay";
+ };
};
diff --git a/board/nvidia/dts/tegra30-cardhu.dts
b/board/nvidia/dts/tegra30-cardhu.dts
index 4d22b48..ea2cf76 100644
--- a/board/nvidia/dts/tegra30-cardhu.dts
+++ b/board/nvidia/dts/tegra30-cardhu.dts
@@ -14,6 +14,7 @@
i2c4 = "/i2c@7000c700";
sdhci0 = "/sdhci@
[U-Boot] [PATCH v5 3/3] Tegra: Config: Enable Tegra30/Tegra114 USB function
Add USB EHCI, storage and network support. Tested on Tegra30 Cardhu, and Tegra114 Dalmore platforms. All works well. Signed-off-by: Jim Lin --- Changes in v2: - Add support for Beaver board. Changes in v3: - None Changes in v4: - None Changes in v5: - None include/configs/beaver.h | 14 ++ include/configs/cardhu.h | 14 ++ include/configs/dalmore.h | 14 ++ include/configs/tegra114-common.h |3 +++ include/configs/tegra30-common.h |3 +++ 5 files changed, 48 insertions(+), 0 deletions(-) diff --git a/include/configs/beaver.h b/include/configs/beaver.h index 058da4f..165de13 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -71,6 +71,20 @@ #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH_SIZE (4 << 20) +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index 6a99175..fd46083 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -70,6 +70,20 @@ #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH_SIZE (4 << 20) +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index 7b68f7c..2723843 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -75,6 +75,20 @@ #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH_SIZE (4 << 20) +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 721b29c..44e98e5 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -77,4 +77,7 @@ /* Total I2C ports on Tegra114 */ #define TEGRA_I2C_NUM_CONTROLLERS 5 +/* For USB EHCI controller */ +#define CONFIG_EHCI_IS_TDI + #endif /* _TEGRA114_COMMON_H_ */ diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index ed36e11..7ea36be 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -90,4 +90,7 @@ /* Total I2C ports on Tegra30 */ #define TEGRA_I2C_NUM_CONTROLLERS 5 +/* For USB EHCI controller */ +#define CONFIG_EHCI_IS_TDI + #endif /* _TEGRA30_COMMON_H_ */ -- 1.7.7 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 1/3] arm: spl: Fix SPL booting for OMAP3
Hi Stefan, On Fri, 21 Jun 2013 12:42:46 +0200, Stefan Roese wrote: > Fix a problem with a re-assignment of r8 in the SPL version. > > This patch now moves the call to s_init() to a later stage, right before > calling board_init_f(). And makes sure that r8 is correctly initialized > before s_init() is called. r8 now is only written in crt0.S. > > This error was detected on the SPL port for the Compulab CM-T35 board > (OMAP3530). > > Signed-off-by: Stefan Roese > Cc: Tom Rini > Acked-by: Albert ARIBAUD > --- > v4: > - Corrected commit text to reflect changed patch > > v3: > - Some code shuffling in crt0.S as requested by Albert > > v2: > - Change handling/initializing of r8 as suggested by Albert. > It should only be written in crt0.S. > > Tom, while working on this version one question came up: > Is lowlevel_init() (file arch/arm/cpu/armv7/omap3/lowlevel_init.S) > needed any more? It calls cpy_clk_code() to copy some clk init > code into SRAM. But I fail to see if and where this code is really > executed from SRAM. Maybe I missed something. Perhaps you could > shed some light into this. > > Thanks, Stefan > > arch/arm/cpu/armv7/omap3/board.c | 2 -- > arch/arm/cpu/armv7/omap3/lowlevel_init.S | 3 +-- > arch/arm/lib/crt0.S | 5 + > 3 files changed, 6 insertions(+), 4 deletions(-) > > diff --git a/arch/arm/cpu/armv7/omap3/board.c > b/arch/arm/cpu/armv7/omap3/board.c > index b72fadc..8f41dcd 100644 > --- a/arch/arm/cpu/armv7/omap3/board.c > +++ b/arch/arm/cpu/armv7/omap3/board.c > @@ -256,8 +256,6 @@ void s_init(void) > #endif > > #ifdef CONFIG_SPL_BUILD > - gd = &gdata; > - > preloader_console_init(); > > timer_init(); > diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S > b/arch/arm/cpu/armv7/omap3/lowlevel_init.S > index eacfef8..8539093 100644 > --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S > +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S > @@ -226,8 +226,7 @@ ENTRY(lowlevel_init) > #endif /* NAND Boot */ > mov lr, ip /* restore link reg */ > ldr ip, [sp]/* restore save ip */ > - /* tail-call s_init to setup pll, mux, memory */ > - b s_init > + mov pc, lr > > ENDPROC(lowlevel_init) > > diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S > index a5bffb8..9bd7c24 100644 > --- a/arch/arm/lib/crt0.S > +++ b/arch/arm/lib/crt0.S > @@ -83,9 +83,14 @@ ENTRY(_main) > ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) > #endif > bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ > +#if defined(CONFIG_SPL_BUILD) > + ldr r8, =gdata /* SPL assigns r8 directly to &gdata */ > + bl s_init /* s_init() needs GD to be setup */ > +#else > sub sp, #GD_SIZE/* allocate one GD above SP */ > bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ > mov r8, sp /* GD is above SP */ > +#endif > mov r0, #0 > bl board_init_f > Acked-by: Albert ARIBAUD Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] ARM: OMAP: GPIO: Fix valid range and enable usage of all GPIOs on OMAP5
The omap_gpio driver is used by AM33XX, OMAP3/4, OMAP54XX and DRA7XX SoCs.
These SoCs have different gpio count but currently omap_gpio driver uses hard
coded 192 which is wrong.
This patch fixes this issue by:
1. Move define of OMAP_MAX_GPIO to all arch/arm/include/asm/arch-omap*/gpio.h.
2. Update gpio bank settings and enable GPIO modules 7 & 8 clocks for OMAP5.
Thanks for Lubomir Popov to provide valuable comments to fix this issue.
Signed-off-by: Axel Lin
---
This patch supersedes below patches:
[PATCH v3 1/2] gpio: omap_gpio: Fix valid gpio range for AM33XX [1]
[PATCH v3 2/2] gpio: omap_gpio: Fix valid GPIO range for OMAP5 [2]
[PATCH 1/2] OMAP5: Fix gpio_bank_54xx setting [3]
[PATCH 2/2] OMAP: gpio: Introduce get_omap_gpio_count() function to get gpio
count [4]
[1] http://lists.denx.de/pipermail/u-boot/2013-June/156980.html
[2] http://lists.denx.de/pipermail/u-boot/2013-June/156981.html
[3] http://lists.denx.de/pipermail/u-boot/2013-June/156984.html
[4] http://lists.denx.de/pipermail/u-boot/2013-June/156985.html
Regards,
Axel
arch/arm/cpu/armv7/omap5/hw_data.c | 2 ++
arch/arm/cpu/armv7/omap5/hwinit.c | 4 +++-
arch/arm/include/asm/arch-am33xx/gpio.h | 2 ++
arch/arm/include/asm/arch-omap3/gpio.h | 2 ++
arch/arm/include/asm/arch-omap4/gpio.h | 2 ++
arch/arm/include/asm/arch-omap5/gpio.h | 4
drivers/gpio/omap_gpio.c| 2 +-
7 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index 56cf1f8..07b1108 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -412,6 +412,8 @@ void enable_basic_clocks(void)
(*prcm)->cm_l4per_gpio4_clkctrl,
(*prcm)->cm_l4per_gpio5_clkctrl,
(*prcm)->cm_l4per_gpio6_clkctrl,
+ (*prcm)->cm_l4per_gpio7_clkctrl,
+ (*prcm)->cm_l4per_gpio8_clkctrl,
0
};
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c
b/arch/arm/cpu/armv7/omap5/hwinit.c
index daf124e..11ba36b 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -43,13 +43,15 @@ DECLARE_GLOBAL_DATA_PTR;
u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
-static struct gpio_bank gpio_bank_54xx[6] = {
+static struct gpio_bank gpio_bank_54xx[8] = {
{ (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
+ { (void *)OMAP54XX_GPIO7_BASE, METHOD_GPIO_24XX },
+ { (void *)OMAP54XX_GPIO8_BASE, METHOD_GPIO_24XX },
};
const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
diff --git a/arch/arm/include/asm/arch-am33xx/gpio.h
b/arch/arm/include/asm/arch-am33xx/gpio.h
index 1a211e9..8346979 100644
--- a/arch/arm/include/asm/arch-am33xx/gpio.h
+++ b/arch/arm/include/asm/arch-am33xx/gpio.h
@@ -21,6 +21,8 @@
#include
+#define OMAP_MAX_GPIO 128
+
#define AM33XX_GPIO0_BASE 0x44E07000
#define AM33XX_GPIO1_BASE 0x4804C000
#define AM33XX_GPIO2_BASE 0x481AC000
diff --git a/arch/arm/include/asm/arch-omap3/gpio.h
b/arch/arm/include/asm/arch-omap3/gpio.h
index 8bba3b0..d72f5e5 100644
--- a/arch/arm/include/asm/arch-omap3/gpio.h
+++ b/arch/arm/include/asm/arch-omap3/gpio.h
@@ -40,6 +40,8 @@
#include
+#define OMAP_MAX_GPIO 192
+
#define OMAP34XX_GPIO1_BASE0x4831
#define OMAP34XX_GPIO2_BASE0x4905
#define OMAP34XX_GPIO3_BASE0x49052000
diff --git a/arch/arm/include/asm/arch-omap4/gpio.h
b/arch/arm/include/asm/arch-omap4/gpio.h
index 26f19d1..fdf65ed 100644
--- a/arch/arm/include/asm/arch-omap4/gpio.h
+++ b/arch/arm/include/asm/arch-omap4/gpio.h
@@ -40,6 +40,8 @@
#include
+#define OMAP_MAX_GPIO 192
+
#define OMAP44XX_GPIO1_BASE0x4A31
#define OMAP44XX_GPIO2_BASE0x48055000
#define OMAP44XX_GPIO3_BASE0x48057000
diff --git a/arch/arm/include/asm/arch-omap5/gpio.h
b/arch/arm/include/asm/arch-omap5/gpio.h
index c14dff0..7c82f90 100644
--- a/arch/arm/include/asm/arch-omap5/gpio.h
+++ b/arch/arm/include/asm/arch-omap5/gpio.h
@@ -40,11 +40,15 @@
#include
+#define OMAP_MAX_GPIO 256
+
#define OMAP54XX_GPIO1_BASE0x4Ae1
#define OMAP54XX_GPIO2_BASE0x48055000
#define OMAP54XX_GPIO3_BASE0x48057000
#define OMAP54XX_GPIO4_BASE0x48059000
#define OMAP54XX_GPIO5_BASE0x4805B000
#define OMAP54XX_GPIO6_BASE0x4805D000
+#define OMAP54XX_GPIO7_BASE0x48051000
+#define OMAP54XX_GPIO8_BASE0x48053000
#endif /* _GPIO_OMAP5_H */
diff --git a/drivers/gpio/omap_gpio.c b/d
[U-Boot] [PATCH v4 1/3] arm: spl: Fix SPL booting for OMAP3
Fix a problem with a re-assignment of r8 in the SPL version. This patch now moves the call to s_init() to a later stage, right before calling board_init_f(). And makes sure that r8 is correctly initialized before s_init() is called. r8 now is only written in crt0.S. This error was detected on the SPL port for the Compulab CM-T35 board (OMAP3530). Signed-off-by: Stefan Roese Cc: Tom Rini Acked-by: Albert ARIBAUD --- v4: - Corrected commit text to reflect changed patch v3: - Some code shuffling in crt0.S as requested by Albert v2: - Change handling/initializing of r8 as suggested by Albert. It should only be written in crt0.S. Tom, while working on this version one question came up: Is lowlevel_init() (file arch/arm/cpu/armv7/omap3/lowlevel_init.S) needed any more? It calls cpy_clk_code() to copy some clk init code into SRAM. But I fail to see if and where this code is really executed from SRAM. Maybe I missed something. Perhaps you could shed some light into this. Thanks, Stefan arch/arm/cpu/armv7/omap3/board.c | 2 -- arch/arm/cpu/armv7/omap3/lowlevel_init.S | 3 +-- arch/arm/lib/crt0.S | 5 + 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index b72fadc..8f41dcd 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -256,8 +256,6 @@ void s_init(void) #endif #ifdef CONFIG_SPL_BUILD - gd = &gdata; - preloader_console_init(); timer_init(); diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index eacfef8..8539093 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -226,8 +226,7 @@ ENTRY(lowlevel_init) #endif /* NAND Boot */ mov lr, ip /* restore link reg */ ldr ip, [sp]/* restore save ip */ - /* tail-call s_init to setup pll, mux, memory */ - b s_init + mov pc, lr ENDPROC(lowlevel_init) diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index a5bffb8..9bd7c24 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -83,9 +83,14 @@ ENTRY(_main) ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) #endif bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ +#if defined(CONFIG_SPL_BUILD) + ldr r8, =gdata /* SPL assigns r8 directly to &gdata */ + bl s_init /* s_init() needs GD to be setup */ +#else sub sp, #GD_SIZE/* allocate one GD above SP */ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ mov r8, sp /* GD is above SP */ +#endif mov r0, #0 bl board_init_f -- 1.8.2.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/3] arm: spl: Fix SPL booting for OMAP3
On 21.06.2013 12:30, Albert ARIBAUD wrote: >> SPL already has GD set to the correct location (in s_init), we mustn't >> move it around now since some data (clocks etc) is already present. > > Actually the commit message is not accurate any more, as it states > s_init should keep setting gd -- sorry for missing this so far, maybe > Tom can fix the message while applying? Argh! I had the commit message changed in v2 but forgot it in v3. Will send v4 shortly. Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/3] arm: spl: Fix SPL booting for OMAP3
Hi Stefan, On Fri, 21 Jun 2013 11:10:10 +0200, Stefan Roese wrote: > SPL already has GD set to the correct location (in s_init), we mustn't > move it around now since some data (clocks etc) is already present. Actually the commit message is not accurate any more, as it states s_init should keep setting gd -- sorry for missing this so far, maybe Tom can fix the message while applying? Otherwise: Acked-by: Albert ARIBAUD Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 8/8] powerpc/p1022ds: boot from spi flash with SPL
From: Andy Fleming [mailto:aflem...@gmail.com] Sent: Thursday, June 20, 2013 12:37 AM To: Zhang Ying-B40530; jagannadha.sutradharudu-t...@xilinx.com Cc: U-Boot list; Wood Scott-B07421; Xie Xiaobo-R63061; Zhang Ying-B40530 Subject: Re: [PATCH 8/8] powerpc/p1022ds: boot from spi flash with SPL On Fri, Jun 7, 2013 at 4:25 AM, mailto:ying.zh...@freescale.com>> wrote: From: Ying Zhang mailto:b40...@freescale.com>> Support to boot from spi flash. This patch is on top of the patch: powerpc/p1022ds: boot from SD Card with SPL Signed-off-by: Ying Zhang mailto:b40...@freescale.com>> --- board/freescale/p1022ds/spl.c | 12 +- drivers/mtd/spi/Makefile |1 + drivers/mtd/spi/fsl_espi_spl.c | 79 drivers/mtd/spi/spi_flash.c|2 + include/configs/P1022DS.h | 36 +++ These should probably be divided into two patches. One to add the capability (in drivers/mtd), and one to enable the capability (in the p1022-specific files). I'd like jagan's ack before applying this, but if you split this patch, and he agrees, I'd be happy to take this in through my tree. [Zhang Ying] This should be no problem. It will be modified with other review comment in the next version(v6). Now the most important is the patch "[PATCH 07/10 v5] powerpc/p1022ds: boot from SD Card with SPL", Please review as soon as possible, I had waiting long. Thanks. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] OMAP: gpio: Introduce get_omap_gpio_count() function to get gpio count
Axel,
Why do you introduce a function when this stuff is constant and known
to the compiler? Just put a #define in every header. You are now
uselessly inflating code...
Regards,
Lubo
On 21/06/13 11:50, Axel Lin wrote:
> Now the omap_gpio driver is used by AM33XX, OMAP3/4, OMAP54XX and DRA7XX SoCs.
> These SoCs have various gpio count. Thus introduce get_omap_gpio_count()
> function to get correct gpio count.
>
> Signed-off-by: Axel Lin
> ---
> arch/arm/cpu/armv7/am33xx/board.c | 5 +
> arch/arm/cpu/armv7/omap3/board.c | 5 +
> arch/arm/cpu/armv7/omap4/hwinit.c | 5 +
> arch/arm/cpu/armv7/omap5/hwinit.c | 5 +
> arch/arm/include/asm/omap_gpio.h | 1 +
> drivers/gpio/omap_gpio.c | 2 +-
> 6 files changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/cpu/armv7/am33xx/board.c
> b/arch/arm/cpu/armv7/am33xx/board.c
> index 885fb2d..405d649 100644
> --- a/arch/arm/cpu/armv7/am33xx/board.c
> +++ b/arch/arm/cpu/armv7/am33xx/board.c
> @@ -51,6 +51,11 @@ static const struct gpio_bank gpio_bank_am33xx[4] = {
>
> const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
>
> +unsigned int get_omap_gpio_count(void)
> +{
> + return ARRAY_SIZE(gpio_bank_am33xx) * 32;
> +}
> +
> #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
> int cpu_mmc_init(bd_t *bis)
> {
> diff --git a/arch/arm/cpu/armv7/omap3/board.c
> b/arch/arm/cpu/armv7/omap3/board.c
> index b72fadc..950b13f 100644
> --- a/arch/arm/cpu/armv7/omap3/board.c
> +++ b/arch/arm/cpu/armv7/omap3/board.c
> @@ -65,6 +65,11 @@ static const struct gpio_bank gpio_bank_34xx[6] = {
>
> const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
>
> +unsigned int get_omap_gpio_count(void)
> +{
> + return ARRAY_SIZE(gpio_bank_34xx) * 32;
> +}
> +
> #ifdef CONFIG_SPL_BUILD
> /*
> * We use static variables because global data is not ready yet.
> diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c
> b/arch/arm/cpu/armv7/omap4/hwinit.c
> index 81f5a48..3212980 100644
> --- a/arch/arm/cpu/armv7/omap4/hwinit.c
> +++ b/arch/arm/cpu/armv7/omap4/hwinit.c
> @@ -51,6 +51,11 @@ static const struct gpio_bank gpio_bank_44xx[6] = {
>
> const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
>
> +unsigned int get_omap_gpio_count(void)
> +{
> + return ARRAY_SIZE(gpio_bank_44xx) * 32;
> +}
> +
> #ifdef CONFIG_SPL_BUILD
> /*
> * Some tuning of IOs for optimal power and performance
> diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c
> b/arch/arm/cpu/armv7/omap5/hwinit.c
> index 11ba36b..58c77e7 100644
> --- a/arch/arm/cpu/armv7/omap5/hwinit.c
> +++ b/arch/arm/cpu/armv7/omap5/hwinit.c
> @@ -56,6 +56,11 @@ static struct gpio_bank gpio_bank_54xx[8] = {
>
> const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
>
> +unsigned int get_omap_gpio_count(void)
> +{
> + return ARRAY_SIZE(gpio_bank_54xx) * 32;
> +}
> +
> #ifdef CONFIG_SPL_BUILD
> /* LPDDR2 specific IO settings */
> static void io_settings_lpddr2(void)
> diff --git a/arch/arm/include/asm/omap_gpio.h
> b/arch/arm/include/asm/omap_gpio.h
> index 1ebfa86..5e25707 100644
> --- a/arch/arm/include/asm/omap_gpio.h
> +++ b/arch/arm/include/asm/omap_gpio.h
> @@ -46,6 +46,7 @@ struct gpio_bank {
> };
>
> extern const struct gpio_bank *const omap_gpio_bank;
> +extern unsigned int get_omap_gpio_count(void);
>
> #define METHOD_GPIO_24XX 4
>
> diff --git a/drivers/gpio/omap_gpio.c b/drivers/gpio/omap_gpio.c
> index a30d7f0..1088803 100644
> --- a/drivers/gpio/omap_gpio.c
> +++ b/drivers/gpio/omap_gpio.c
> @@ -55,7 +55,7 @@ static inline int get_gpio_index(int gpio)
>
> int gpio_is_valid(int gpio)
> {
> - return (gpio >= 0) && (gpio < 192);
> + return (gpio >= 0) && (gpio < get_omap_gpio_count());
> }
>
> static int check_gpio(int gpio)
>
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Re: [U-Boot] [PATCH v2] gpio: omap_gpio: Fix valid gpio range for AM33XX
Hi Heiko, Axel, On 21/06/13 11:44, Heiko Schocher wrote: > Hello Lubomir, > > Am 21.06.2013 09:44, schrieb Lubomir Popov: >> One more thing that perhaps seems more reasonable in general: >> >> These OMAP_MAX_GPIO defines could go into the corresponding .../arch-omap*.h >> files, where the base addresses are defined, and the number of GPIOs is >> implicitly obvious. And we shall have no ugly #ifdefs in the GPIO driver. > > This sounds good. I vote for doing it this way ... Sure, but for things to work on the OMAP5 SoCs, the GPIO modules 7 & 8 clocks have to be enabled as well, otherwise we get a Data Abort exception. This requires one more fix in arch/arm/cpu/armv7/omap5/hw_data.c: (*prcm)->cm_l4per_gpio7_clkctrl, (*prcm)->cm_l4per_gpio8_clkctrl, have to be added to the clk_modules_hw_auto_essential[] array. I'm not mentioning here that, in order to test this in U-Boot, the pads that are intended to be used as GPIO have to be properly configured (the GPIO mux mode selected). For me the easiest way to do this was by again defining CONFIG_SYS_ENABLE_PADS_ALL (which is being descoped) because my board mux file has quite a lot of pads set to GPIO in the non_essential array. I have some additional concerns as well: on the different SoCs we have different GPIOs that are input-only or output-only, and this is currently not handled by the driver in any way. We have just to hope that users are educated enough... Unfortunately my experience tells me that very few people care to read these thousands of pages long tech docs :( . Anyway, I guess we shall have to leave this as is for now... I would suggest that Axel withdraws V3 and makes a V4 (and, please, cleanly based on master branch, not incremental), where: 1. The OMAP_MAX_GPIO defines are moved to all arch/arm/include/asm/arch-omap*/gpio.h files, and 2. The fix to arch/arm/cpu/armv7/omap5/hw_data.c is made - this affects OMAP54XX and DRA7XX. Or perhaps an entirely new patch subject (that is, new V1 patch), so that no confusion happens - we have actually shifted the scope a bit with these additional fixes. Something like ARM: OMAP: GPIO: Fix valid range and enable usage of all GPIOs on OMAP5 Otherwise, functionally tested on a custom OMAP5430 board with some GPIOs > 191, works OK (with all discussed fixes applied manually). Shall give my "Tested-by:" when I apply the final version as a patch and test again. > > bye, > Heiko > Regards, Lubo ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Not able to boot using zImage
Hi Tom,
Thanks for your quick reply.
2013/6/20 Tom Rini
> On Thu, Jun 20, 2013 at 12:27:02PM +0200, Enric Balletbo Serra wrote:
>
> > Hi all,
> >
> > I've some problems trying to boot a zImage with following command after
> > load the zImage and the fdt file on memory:
> >
> > U-Boot > fdt addr ${dtbaddr}; fdt resize; bootz ${loadaddr} - ${dtbaddr}
> [snip]
> > The same commands using the uImage instead of zImage works without
> > problems. Is expected to work ? Any clue before diving into the problem ?
>
> Same kernel tree? And you're setting bootargs before you do any of the
> above?
>
>
Yes, same kernel tree and I set the bootargs before. But I think it was my
bad, it's not an u-boot problem as I tested on beaglebone and works.
The difference between the two cases I tested are the address. The one that
doesn't work using zImage and works with uImage is
dtbaddr=0x8160
loadaddr=0x8000
If I change the addresses like the used in beaglebone, then works
dtbaddr=0x8020
loadaddr=0x80F8
I need to check exactly what is thge problem with these addresses. Anyway
it's not an u-boot problem. Thanks for the support.
Best regards,
Enric
--
> Tom
>
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[U-Boot] [PATCH v3 1/3] arm: spl: Fix SPL booting for OMAP3
SPL already has GD set to the correct location (in s_init), we mustn't move it around now since some data (clocks etc) is already present. This error was detected on the SPL port for the Compulab CM-T35 board (OMAP3530). Signed-off-by: Stefan Roese Cc: Tom Rini Cc: Albert ARIBAUD --- v3: - Some code shuffling in crt0.S as requested by Albert v2: - Change handling/initializing of r8 as suggested by Albert. It should only be written in crt0.S. Tom, while working on this version one question came up: Is lowlevel_init() (file arch/arm/cpu/armv7/omap3/lowlevel_init.S) needed any more? It calls cpy_clk_code() to copy some clk init code into SRAM. But I fail to see if and where this code is really executed from SRAM. Maybe I missed something. Perhaps you could shed some light into this. Thanks, Stefan arch/arm/cpu/armv7/omap3/board.c | 2 -- arch/arm/cpu/armv7/omap3/lowlevel_init.S | 3 +-- arch/arm/lib/crt0.S | 5 + 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index b72fadc..8f41dcd 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -256,8 +256,6 @@ void s_init(void) #endif #ifdef CONFIG_SPL_BUILD - gd = &gdata; - preloader_console_init(); timer_init(); diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index eacfef8..8539093 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -226,8 +226,7 @@ ENTRY(lowlevel_init) #endif /* NAND Boot */ mov lr, ip /* restore link reg */ ldr ip, [sp]/* restore save ip */ - /* tail-call s_init to setup pll, mux, memory */ - b s_init + mov pc, lr ENDPROC(lowlevel_init) diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index a5bffb8..9bd7c24 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -83,9 +83,14 @@ ENTRY(_main) ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) #endif bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ +#if defined(CONFIG_SPL_BUILD) + ldr r8, =gdata /* SPL assigns r8 directly to &gdata */ + bl s_init /* s_init() needs GD to be setup */ +#else sub sp, #GD_SIZE/* allocate one GD above SP */ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ mov r8, sp /* GD is above SP */ +#endif mov r0, #0 bl board_init_f -- 1.8.2.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/3] arm: spl: Fix SPL booting for OMAP3
Hi Stefan, On Fri, 21 Jun 2013 04:13:17 +0200, Stefan Roese wrote: > Fix a problem with a re-assignment of r8 in the SPL version. > > This patch now moves the call to s_init() to a later stage, right before > calling board_init_f(). And makes sure that r8 is correctly initialized > before s_init() is called. r8 now is only written in crt0.S. > > This error was detected on the SPL port for the Compulab CM-T35 board > (OMAP3530). > > Signed-off-by: Stefan Roese > Cc: Tom Rini > Cc: Albert ARIBAUD > --- > v2: > - Change handling/initializing of r8 as suggested by Albert. > It should only be written in crt0.S. > > Tom, while working on this version one question came up: > Is lowlevel_init() (file arch/arm/cpu/armv7/omap3/lowlevel_init.S) > needed any more? It calls cpy_clk_code() to copy some clk init > code into SRAM. But I fail to see if and where this code is really > executed from SRAM. Maybe I missed something. Perhaps you could > shed some light into this. > > Thanks, Stefan > > arch/arm/cpu/armv7/omap3/board.c | 2 -- > arch/arm/cpu/armv7/omap3/lowlevel_init.S | 3 +-- > arch/arm/lib/crt0.S | 7 ++- > 3 files changed, 7 insertions(+), 5 deletions(-) > > diff --git a/arch/arm/cpu/armv7/omap3/board.c > b/arch/arm/cpu/armv7/omap3/board.c > index b72fadc..8f41dcd 100644 > --- a/arch/arm/cpu/armv7/omap3/board.c > +++ b/arch/arm/cpu/armv7/omap3/board.c > @@ -256,8 +256,6 @@ void s_init(void) > #endif > > #ifdef CONFIG_SPL_BUILD > - gd = &gdata; > - > preloader_console_init(); > > timer_init(); > diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S > b/arch/arm/cpu/armv7/omap3/lowlevel_init.S > index eacfef8..8539093 100644 > --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S > +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S > @@ -226,8 +226,7 @@ ENTRY(lowlevel_init) > #endif /* NAND Boot */ > mov lr, ip /* restore link reg */ > ldr ip, [sp]/* restore save ip */ > - /* tail-call s_init to setup pll, mux, memory */ > - b s_init > + mov pc, lr > > ENDPROC(lowlevel_init) > > diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S > index a5bffb8..0f8d9f5 100644 > --- a/arch/arm/lib/crt0.S > +++ b/arch/arm/lib/crt0.S > @@ -85,8 +85,13 @@ ENTRY(_main) > bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ Actually, this... > sub sp, #GD_SIZE/* allocate one GD above SP */ > bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ ... should also be moved under the #else clause below -- no need to eat up valuable stack space when GD is in gdata. > - mov r8, sp /* GD is above SP */ Also, this... > mov r0, #0 ... should remain just before the call to board_init_f which needs it. Otherwise you run the (non-null) risk that r0 be non-zero on return from s_init and then this non-zero value be passed to board_init_f. > +#if defined(CONFIG_SPL_BUILD) > + ldr r8, =gdata /* SPL assigns r8 directly to &gdata */ > + bl s_init /* s_init() needs GD to be setup */ > +#else > + mov r8, sp /* GD is above SP */ > +#endif > bl board_init_f > > #if ! defined(CONFIG_SPL_BUILD) Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] OMAP: gpio: Introduce get_omap_gpio_count() function to get gpio count
Now the omap_gpio driver is used by AM33XX, OMAP3/4, OMAP54XX and DRA7XX SoCs.
These SoCs have various gpio count. Thus introduce get_omap_gpio_count()
function to get correct gpio count.
Signed-off-by: Axel Lin
---
arch/arm/cpu/armv7/am33xx/board.c | 5 +
arch/arm/cpu/armv7/omap3/board.c | 5 +
arch/arm/cpu/armv7/omap4/hwinit.c | 5 +
arch/arm/cpu/armv7/omap5/hwinit.c | 5 +
arch/arm/include/asm/omap_gpio.h | 1 +
drivers/gpio/omap_gpio.c | 2 +-
6 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/am33xx/board.c
b/arch/arm/cpu/armv7/am33xx/board.c
index 885fb2d..405d649 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -51,6 +51,11 @@ static const struct gpio_bank gpio_bank_am33xx[4] = {
const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
+unsigned int get_omap_gpio_count(void)
+{
+ return ARRAY_SIZE(gpio_bank_am33xx) * 32;
+}
+
#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
int cpu_mmc_init(bd_t *bis)
{
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index b72fadc..950b13f 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -65,6 +65,11 @@ static const struct gpio_bank gpio_bank_34xx[6] = {
const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
+unsigned int get_omap_gpio_count(void)
+{
+ return ARRAY_SIZE(gpio_bank_34xx) * 32;
+}
+
#ifdef CONFIG_SPL_BUILD
/*
* We use static variables because global data is not ready yet.
diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c
b/arch/arm/cpu/armv7/omap4/hwinit.c
index 81f5a48..3212980 100644
--- a/arch/arm/cpu/armv7/omap4/hwinit.c
+++ b/arch/arm/cpu/armv7/omap4/hwinit.c
@@ -51,6 +51,11 @@ static const struct gpio_bank gpio_bank_44xx[6] = {
const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
+unsigned int get_omap_gpio_count(void)
+{
+ return ARRAY_SIZE(gpio_bank_44xx) * 32;
+}
+
#ifdef CONFIG_SPL_BUILD
/*
* Some tuning of IOs for optimal power and performance
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c
b/arch/arm/cpu/armv7/omap5/hwinit.c
index 11ba36b..58c77e7 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -56,6 +56,11 @@ static struct gpio_bank gpio_bank_54xx[8] = {
const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
+unsigned int get_omap_gpio_count(void)
+{
+ return ARRAY_SIZE(gpio_bank_54xx) * 32;
+}
+
#ifdef CONFIG_SPL_BUILD
/* LPDDR2 specific IO settings */
static void io_settings_lpddr2(void)
diff --git a/arch/arm/include/asm/omap_gpio.h b/arch/arm/include/asm/omap_gpio.h
index 1ebfa86..5e25707 100644
--- a/arch/arm/include/asm/omap_gpio.h
+++ b/arch/arm/include/asm/omap_gpio.h
@@ -46,6 +46,7 @@ struct gpio_bank {
};
extern const struct gpio_bank *const omap_gpio_bank;
+extern unsigned int get_omap_gpio_count(void);
#define METHOD_GPIO_24XX 4
diff --git a/drivers/gpio/omap_gpio.c b/drivers/gpio/omap_gpio.c
index a30d7f0..1088803 100644
--- a/drivers/gpio/omap_gpio.c
+++ b/drivers/gpio/omap_gpio.c
@@ -55,7 +55,7 @@ static inline int get_gpio_index(int gpio)
int gpio_is_valid(int gpio)
{
- return (gpio >= 0) && (gpio < 192);
+ return (gpio >= 0) && (gpio < get_omap_gpio_count());
}
static int check_gpio(int gpio)
--
1.8.1.2
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[U-Boot] [PATCH 1/2] OMAP5: Fix gpio_bank_54xx setting
OMAP54XX and DRA7XX SoCs have 8 banks per 32 GPIOs, that is, 256 in total.
Fix the gpio bank setting.
Signed-off-by: Axel Lin
---
arch/arm/cpu/armv7/omap5/hwinit.c | 4 +++-
arch/arm/include/asm/arch-omap5/gpio.h | 2 ++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c
b/arch/arm/cpu/armv7/omap5/hwinit.c
index daf124e..11ba36b 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -43,13 +43,15 @@ DECLARE_GLOBAL_DATA_PTR;
u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
-static struct gpio_bank gpio_bank_54xx[6] = {
+static struct gpio_bank gpio_bank_54xx[8] = {
{ (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
+ { (void *)OMAP54XX_GPIO7_BASE, METHOD_GPIO_24XX },
+ { (void *)OMAP54XX_GPIO8_BASE, METHOD_GPIO_24XX },
};
const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
diff --git a/arch/arm/include/asm/arch-omap5/gpio.h
b/arch/arm/include/asm/arch-omap5/gpio.h
index c14dff0..f507a35 100644
--- a/arch/arm/include/asm/arch-omap5/gpio.h
+++ b/arch/arm/include/asm/arch-omap5/gpio.h
@@ -46,5 +46,7 @@
#define OMAP54XX_GPIO4_BASE0x48059000
#define OMAP54XX_GPIO5_BASE0x4805B000
#define OMAP54XX_GPIO6_BASE0x4805D000
+#define OMAP54XX_GPIO7_BASE0x48051000
+#define OMAP54XX_GPIO8_BASE0x48053000
#endif /* _GPIO_OMAP5_H */
--
1.8.1.2
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Re: [U-Boot] [PATCH v2] gpio: omap_gpio: Fix valid gpio range for AM33XX
2013/6/21 Heiko Schocher : > Hello Lubomir, > > Am 21.06.2013 09:44, schrieb Lubomir Popov: >> One more thing that perhaps seems more reasonable in general: >> >> These OMAP_MAX_GPIO defines could go into the corresponding .../arch-omap*.h >> files, where the base addresses are defined, and the number of GPIOs is >> implicitly obvious. And we shall have no ugly #ifdefs in the GPIO driver. > > This sounds good. I vote for doing it this way ... I'm sending patches base on this idea now... Thanks, Axel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
