Re: [U-Boot] Some custodian changes
On Thu, Aug 8, 2013 at 9:09 PM, Tom Rini tr...@ti.com wrote: Hey all, I want to announce a few custodian changes. Andy Fleming is stepping down from both his PowerPC and MMC custodianships to go off and do something non-technical and fun for a while. I want to thank him for all his time and wish him the best! All the very best Andy Fleming. Taking over for Andy for mpc85xx and mpc86xx will be York Sun, and taking over for MMC will be Pantelis Antoniou. Welcome aboard guys! Congrats..Welcome on board..York Sun and Pantelis Antoniou. -- Thanks, Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] microblaze: Call spi_init function
On 08-08-2013 19:03, Jagannadha Sutradharudu Teki wrote: From: Michal Simek mon...@monstr.eu Initialization spi. Signed-off-by: Michal Simek mon...@monstr.eu Acked-by: Stephan Linz l...@li-pro.net Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com --- Changes for v2: - rebase to current tree. arch/microblaze/lib/board.c | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c index 8267191..f7182f2 100644 --- a/arch/microblaze/lib/board.c +++ b/arch/microblaze/lib/board.c @@ -16,6 +16,7 @@ #include stdio_dev.h #include serial.h #include net.h +#include spi.h #include linux/compiler.h #include asm/processor.h #include asm/microblaze_intc.h @@ -147,6 +148,10 @@ void board_init_f(ulong not_used) } #endif +#ifdef CONFIG_SPI + spi_init(); +#endif + /* relocate environment function pointers etc. */ env_relocate(); Applied to u-boot-spi/master -- Thanks, Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/3] spi: Add zynq spi controller
On 07-08-2013 01:17, Jagannadha Sutradharudu Teki wrote: This is a v2 for previous series with same cover head. This small series patchset will add suuport for zynq spi controller, tested on sst flash. -- Thanks, Jagan. Jagannadha Sutradharudu Teki (3): spi: Add zynq spi controller driver sf: sst: Add support for SST25WF080 zynq: Enable CONFIG_ZYNQ_SPI arch/arm/include/asm/arch-zynq/hardware.h | 2 + drivers/mtd/spi/sst.c | 6 + drivers/spi/Makefile | 1 + drivers/spi/zynq_spi.c| 280 ++ include/configs/zynq.h| 9 + 5 files changed, 298 insertions(+) create mode 100644 drivers/spi/zynq_spi.c Applied to u-boot-spi/master -- Thanks, Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] arm: sama5d3: fix smc cs related registers offset
the smc cs related registers start at 0x600 and loop with 5 registers
so the reserved register should be in at91_smc structure while no in
at91_cs structure. So fix it
Signed-off-by: Bo Shen voice.s...@atmel.com
---
arch/arm/include/asm/arch-at91/sama5d3_smc.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-at91/sama5d3_smc.h
b/arch/arm/include/asm/arch-at91/sama5d3_smc.h
index c060894..6caa9b6 100644
--- a/arch/arm/include/asm/arch-at91/sama5d3_smc.h
+++ b/arch/arm/include/asm/arch-at91/sama5d3_smc.h
@@ -17,7 +17,6 @@
#define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x60C)
#else
struct at91_cs {
- u32 reserved[96];
u32 setup; /* 0x600 SMC Setup Register */
u32 pulse; /* 0x604 SMC Pulse Register */
u32 cycle; /* 0x608 SMC Cycle Register */
@@ -26,6 +25,7 @@ struct at91_cs {
};
struct at91_smc {
+ u32 reserved[384];
struct at91_cs cs[4];
};
#endif /* __ASSEMBLY__ */
--
1.7.9.5
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[U-Boot] [PATCH] arm: sama5d3: remove unused define
The CONFIG_MAX_NAND_CHIPS never used, remove it No where define LCD_TEST_PATTERN, so no need undefine Signed-off-by: Bo Shen voice.s...@atmel.com --- include/configs/sama5d3xek.h |2 -- 1 file changed, 2 deletions(-) diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index 10697d6..cceb38b 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -56,7 +56,6 @@ #define LCD_BPPLCD_COLOR16 #define LCD_OUTPUT_BPP 24 #define CONFIG_LCD_LOGO -#undef LCD_TEST_PATTERN #define CONFIG_LCD_INFO #define CONFIG_LCD_INFO_BELOW_LOGO #define CONFIG_SYS_WHITE_ON_BLACK @@ -112,7 +111,6 @@ #define CONFIG_CMD_NAND #ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_MAX_CHIPS 1 #define CONFIG_NAND_ATMEL #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] spi: Add support SH Queued SPI driver
Hi,
On 08-08-2013 15:02, Nobuhiro Iwamatsu wrote:
This patch adds a driver for Renesas SoC's Queued SPI bus.
This supports with 8 bits per transfer to use with SPI flash.
Signed-off-by: Kouei Abe kouei.abe...@renesas.com
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
v2: Change SH QSPI to SH QSPI (Queued SPI).
Remove magic number.
drivers/spi/Makefile | 1 +
drivers/spi/sh_qspi.c | 232 ++
drivers/spi/sh_qspi.h | 52 +++
Please move the structure decelerations on to sh_qspi.c
FYI: I am trying to prepare the spi driver code to more readable
header file inclusion
Register bit masks
MISC macro definitions
controller reg structure
controller private slave structure
inline func defination
spi_xfer_sub()
spi_setup_slave_sub
spi_cs_is_valid
spi_cs_activate
spi_cs_deactivate
spi_init
spi_setup_slave
{
spi_setup_slave_sub()
}
spi_free_slave
spi_claim_bus
spi_release_bus
spi_xfer code
{
spi_xfer_sub()
}
I am just trying to do the above format atleast from the drivers which
are pushing now onwards.
Please see the reff driver
http://git.denx.de/?p=u-boot/u-boot-spi.git;a=commitdiff;h=1465d055f9d7a81edacf30c9d20a1b51dfcbfa8d
Let me know your views.
3 files changed, 285 insertions(+)
create mode 100644 drivers/spi/sh_qspi.c
create mode 100644 drivers/spi/sh_qspi.h
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 019132e..f71c089 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -33,6 +33,7 @@ COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
+COBJS-$(CONFIG_SH_QSPI) += sh_qspi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c
new file mode 100644
index 000..25ce60a
--- /dev/null
+++ b/drivers/spi/sh_qspi.c
@@ -0,0 +1,232 @@
+/*
+ * drivers/spi/sh_qspi.c
Not required, i guess.
+ * SH QSPI (Queued SPI) driver
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include common.h
+#include malloc.h
+#include spi.h
+#include asm/io.h
+#include sh_qspi.h
+
+static void sh_qspi_writeb(unsigned char data, unsigned char *reg)
+{
+ writeb(data, reg);
+}
+
+static void sh_qspi_writew(unsigned short data, unsigned short *reg)
+{
+ writew(data, reg);
+}
+
+static void sh_qspi_writel(unsigned long data, unsigned long *reg)
+{
+ writel(data, reg);
+}
+
+static unsigned char sh_qspi_readb(unsigned char *reg)
+{
+ return readb(reg);
+}
+
+static unsigned short sh_qspi_readw(unsigned short *reg)
+{
+ return readw(reg);
+}
+
+void spi_init(void)
+{
+}
Can you use read* and write* directly instead of sh_qspi_write*
sh_qspi_read*
Do you have any specific reason for using these?
+
+/* SPCR */
+#define SPCR_MSTR 0x08
+#define SPCR_SPE 0x40
+/* SPSR */
+#define SPSR_SPRFF 0x80
+#define SPSR_SPTEF 0x20
+/* SPPCR */
+#define SPPCR_IO3FV 0x04
+#define SPPCR_IO2FV 0x02
+#define SPPCR_IO1FV 0x01
+/* SPBDCR */
+#define SPBDCR_RXBC0 (1 0)
+/* SPCMD */
+#define SPCMD_SCKDEN (1 15)
+#define SPCMD_SLNDEN (1 14)
+#define SPCMD_SPNDEN (1 13)
+#define SPCMD_SSLKP (1 7)
+#define SPCMD_BRDV0 (1 2)
+#define SPCMD_INIT1 \
+ (SPCMD_SCKDEN|SPCMD_SLNDEN|SPCMD_SPNDEN|SPCMD_SSLKP|SPCMD_BRDV0)
+#define SPCMD_INIT2 (SPCMD_SPNDEN|SPCMD_SSLKP|SPCMD_BRDV0)
+/* SPBFCR */
+#define SPBFCR_TXRST (1 7)
+#define SPBFCR_RXRST (1 6)
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct sh_qspi *ss;
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
+ ss = spi_alloc_slave(struct sh_qspi, bus, cs);
+ if (!ss)
+ return NULL;
+
+ ss-regs = (struct sh_qspi_regs *)CONFIG_SH_QSPI_BASE;
+
+ /* QSPI initialize */
+ sh_qspi_writeb(SPCR_MSTR, ss-regs-spcr);
+ sh_qspi_writeb(0x00, ss-regs-sslp);
+ sh_qspi_writeb(SPPCR_IO3FV|SPPCR_IO2FV, ss-regs-sppcr);
+
+ /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
+ sh_qspi_writeb(0x01, ss-regs-spbr);
+
+ sh_qspi_writeb(0x00, ss-regs-spdcr);
+ sh_qspi_writeb(0x00, ss-regs-spckd);
+ sh_qspi_writeb(0x00, ss-regs-sslnd);
+ sh_qspi_writeb(0x00, ss-regs-spnd);
+ sh_qspi_writew(SPCMD_INIT1, ss-regs-spcmd0);
+ sh_qspi_writew(SPCMD_INIT2, ss-regs-spcmd0);
+ sh_qspi_writeb(SPBFCR_TXRST|SPBFCR_RXRST, ss-regs-spbfcr);
+ sh_qspi_writeb(0x00, ss-regs-spbfcr);
+ sh_qspi_writeb(0x00, ss-regs-spscr);
+ sh_qspi_writeb(SPCR_SPE|SPCR_MSTR, ss-regs-spcr);
+
+ return
[U-Boot] : Suggestions for SPI driver pusher
Hi,
FYI: I am trying to prepare the spi driver code to more readable.
As each spi driver has a common set of calls.
header file inclusion
Register bit masks
MISC macro definitions
controller reg structure
controller private slave structure
inline func defination
spi_xfer_sub()
spi_setup_slave_sub
spi_cs_is_valid
spi_cs_activate
spi_cs_deactivate
spi_init
spi_setup_slave
{
spi_setup_slave_sub()
}
spi_free_slave
spi_claim_bus
spi_release_bus
spi_xfer code
{
spi_xfer_sub()
}
I am just trying to do the above format at-least from the drivers which
are pushing now onwards.
Please see the reff driver
http://git.denx.de/?p=u-boot/u-boot-spi.git;a=commitdiff;h=1465d055f9d7a81edacf30c9d20a1b51dfcbfa8d
Let me know your views.
--
Thanks,
Jagan.
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[U-Boot] [PATCH v1 4/4] powerpc/ppc4xx: Fix dlvision-10g reset gpio
From: Dirk Eibach dirk.eib...@gdsys.cc Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc --- include/configs/dlvision-10g.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h index a03c462..68e5246 100644 --- a/include/configs/dlvision-10g.h +++ b/include/configs/dlvision-10g.h @@ -18,7 +18,7 @@ * Include common defines/options for all AMCC eval boards */ #define CONFIG_HOSTNAMEdlvsion-10g -#define CONFIG_IDENT_STRING dlvision-10g 0.04 +#define CONFIG_IDENT_STRING dlvision-10g 0.05 #include amcc-common.h #define CONFIG_BOARD_EARLY_INIT_F @@ -131,7 +131,7 @@ #define CONFIG_SYS_LATCH0_RESET0x #define CONFIG_SYS_LATCH0_BOOT 0x -#define CONFIG_SYS_LATCH1_RESET0xffcf +#define CONFIG_SYS_LATCH1_RESET0xffbf #define CONFIG_SYS_LATCH1_BOOT 0x #define CONFIG_SYS_FPGA_NO_RFL_HI -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1 3/4] powerpc/ppc4xx: Do full iocon PHY initialization in software
From: Dirk Eibach dirk.eib...@gdsys.cc
Up to this point some PHY initialization was done from the FPGA
and some from u-boot.
From now all initialization is done from u-boot.
To keep this maintainable a PHY setup machine was implemented that can
execute commands from initialization arrays.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
board/gdsys/405ep/iocon.c | 220 --
1 file changed, 172 insertions(+), 48 deletions(-)
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
index 664b1e1..7a98e41 100644
--- a/board/gdsys/405ep/iocon.c
+++ b/board/gdsys/405ep/iocon.c
@@ -99,7 +99,6 @@ unsigned int mclink_fpgacount;
struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
static int setup_88e1518(const char *bus, unsigned char addr);
-static int verify_88e1518(const char *bus, unsigned char addr);
int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
{
@@ -405,11 +404,7 @@ int last_stage_init(void)
if ((mux_ch == 1) !ch0_rgmii2_present)
continue;
- if (!verify_88e1518(bb_miiphy_buses[0].name, mux_ch)) {
- printf(Fixup 88e1518 erratum on %s phy %u\n,
- bb_miiphy_buses[0].name, mux_ch);
- setup_88e1518(bb_miiphy_buses[0].name, mux_ch);
- }
+ setup_88e1518(bb_miiphy_buses[0].name, mux_ch);
}
}
@@ -434,11 +429,7 @@ int last_stage_init(void)
if (feature_carrier_speed == CARRIER_SPEED_1G) {
miiphy_register(bb_miiphy_buses[k].name,
bb_miiphy_read, bb_miiphy_write);
- if (!verify_88e1518(bb_miiphy_buses[k].name, 0)) {
- printf(Fixup 88e1518 erratum on %s\n,
- bb_miiphy_buses[k].name);
- setup_88e1518(bb_miiphy_buses[k].name, 0);
- }
+ setup_88e1518(bb_miiphy_buses[k].name, 0);
}
}
@@ -652,56 +643,189 @@ struct bb_miiphy_bus bb_miiphy_buses[] = {
int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
sizeof(bb_miiphy_buses[0]);
+enum {
+ MIICMD_SET,
+ MIICMD_MODIFY,
+ MIICMD_VERIFY_VALUE,
+ MIICMD_WAIT_FOR_VALUE,
+};
+
+struct mii_setupcmd {
+ u8 token;
+ u8 reg;
+ u16 data;
+ u16 mask;
+ u32 timeout;
+};
+
/*
- * Workaround for erratum mentioned in 88E1518 release notes
+ * verify we are talking to a 88e1518
*/
+struct mii_setupcmd verify_88e1518[] = {
+ { MIICMD_SET, 22, 0x },
+ { MIICMD_VERIFY_VALUE, 2, 0x0141, 0x },
+ { MIICMD_VERIFY_VALUE, 3, 0x0dd0, 0xfff0 },
+};
-static int verify_88e1518(const char *bus, unsigned char addr)
-{
- u16 phy_id1, phy_id2;
-
- if (miiphy_read(bus, addr, 2, phy_id1) ||
- miiphy_read(bus, addr, 3, phy_id2)) {
- printf(Error reading from the PHY addr=%02x\n, addr);
- return -EIO;
- }
+/*
+ * workaround for erratum mentioned in 88E1518 release notes
+ */
+struct mii_setupcmd fixup_88e1518[] = {
+ { MIICMD_SET, 22, 0x00ff },
+ { MIICMD_SET, 17, 0x214b },
+ { MIICMD_SET, 16, 0x2144 },
+ { MIICMD_SET, 17, 0x0c28 },
+ { MIICMD_SET, 16, 0x2146 },
+ { MIICMD_SET, 17, 0xb233 },
+ { MIICMD_SET, 16, 0x214d },
+ { MIICMD_SET, 17, 0xcc0c },
+ { MIICMD_SET, 16, 0x2159 },
+ { MIICMD_SET, 22, 0x00fb },
+ { MIICMD_SET, 7, 0xc00d },
+ { MIICMD_SET, 22, 0x },
+};
- if ((phy_id1 != 0x0141) || ((phy_id2 0xfff0) != 0x0dd0))
- return -EINVAL;
+/*
+ * default initialization:
+ * - set RGMII receive timing to receive clock transition when data stable
+ * - set RGMII transmit timing to transmit clock internally delayed
+ * - set RGMII output impedance target to 78,8 Ohm
+ * - run output impedance calibration
+ * - set autonegotiation advertise to 1000FD only
+ */
+struct mii_setupcmd default_88e1518[] = {
+ { MIICMD_SET, 22, 0x0002 },
+ { MIICMD_MODIFY, 21, 0x0030, 0x0030 },
+ { MIICMD_MODIFY, 25, 0x, 0x0003 },
+ { MIICMD_MODIFY, 24, 0x8000, 0x8000 },
+ { MIICMD_WAIT_FOR_VALUE, 24, 0x4000, 0x4000, 2000 },
+ { MIICMD_SET, 22, 0x },
+ { MIICMD_MODIFY, 4, 0x, 0x01e0 },
+ { MIICMD_MODIFY, 9, 0x0200, 0x0300 },
+};
- return 0;
-}
+/*
+ * turn off CLK125 for PHY daughterboard
+ */
+struct mii_setupcmd ch1fix_88e1518[] = {
+ { MIICMD_SET, 22, 0x0002 },
+ { MIICMD_MODIFY, 16, 0x0006, 0x0006 },
+ { MIICMD_SET, 22, 0x },
+};
-struct regfix_88e1518 {
- u8 reg;
- u16 data;
-} regfix_88e1518[] = {
- { 22, 0x00ff },
- { 17, 0x214b },
- { 16, 0x2144 },
- {
[U-Boot] [PATCH v1 2/4] powerpc/ppc4xx: Add support for iocon-2
From: Dirk Eibach dirk.eib...@gdsys.cc
Add a new iocon flavor with a second communiction port per channel.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
board/gdsys/405ep/iocon.c | 36 +---
1 file changed, 25 insertions(+), 11 deletions(-)
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
index f6502b3..664b1e1 100644
--- a/board/gdsys/405ep/iocon.c
+++ b/board/gdsys/405ep/iocon.c
@@ -30,6 +30,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+#define MAX_MUX_CHANNELS 2
+
enum {
UNITTYPE_MAIN_SERVER = 0,
UNITTYPE_MAIN_USER = 1,
@@ -163,7 +165,7 @@ int checkboard(void)
return 0;
}
-static void print_fpga_info(unsigned int fpga)
+static void print_fpga_info(unsigned int fpga, bool rgmii2_present)
{
u16 versions;
u16 fpga_version;
@@ -260,6 +262,8 @@ static void print_fpga_info(unsigned int fpga)
hardware_version);
break;
}
+ if (rgmii2_present)
+ printf( RGMII2,);
}
if (unit_type == UNITTYPE_VIDEO_USER) {
@@ -362,14 +366,19 @@ int last_stage_init(void)
{
int slaves;
unsigned int k;
+ unsigned int mux_ch;
unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
int legacy = get_fpga_state(0) FPGA_STATE_PLATFORM;
u16 fpga_features;
int feature_carrier_speed = fpga_features (14);
+ bool ch0_rgmii2_present = false;
FPGA_GET_REG(0, fpga_features, fpga_features);
- print_fpga_info(0);
+ if (!legacy)
+ ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
+
+ print_fpga_info(0, ch0_rgmii2_present);
osd_probe(0);
/* wait for FPGA done */
@@ -392,10 +401,15 @@ int last_stage_init(void)
if (!legacy (feature_carrier_speed == CARRIER_SPEED_1G)) {
miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
bb_miiphy_write);
- if (!verify_88e1518(bb_miiphy_buses[0].name, 0)) {
- printf(Fixup 88e1518 erratum on %s\n,
- bb_miiphy_buses[0].name);
- setup_88e1518(bb_miiphy_buses[0].name, 0);
+ for (mux_ch = 0; mux_ch MAX_MUX_CHANNELS; ++mux_ch) {
+ if ((mux_ch == 1) !ch0_rgmii2_present)
+ continue;
+
+ if (!verify_88e1518(bb_miiphy_buses[0].name, mux_ch)) {
+ printf(Fixup 88e1518 erratum on %s phy %u\n,
+ bb_miiphy_buses[0].name, mux_ch);
+ setup_88e1518(bb_miiphy_buses[0].name, mux_ch);
+ }
}
}
@@ -415,7 +429,7 @@ int last_stage_init(void)
FPGA_GET_REG(k, fpga_features, fpga_features);
feature_carrier_speed = fpga_features (14);
- print_fpga_info(k);
+ print_fpga_info(k, false);
osd_probe(k);
if (feature_carrier_speed == CARRIER_SPEED_1G) {
miiphy_register(bb_miiphy_buses[k].name,
@@ -590,7 +604,7 @@ static int mii_delay(struct bb_miiphy_bus *bus)
struct bb_miiphy_bus bb_miiphy_buses[] = {
{
- .name = trans1,
+ .name = board0,
.init = mii_dummy_init,
.mdio_active = mii_mdio_active,
.mdio_tristate = mii_mdio_tristate,
@@ -601,7 +615,7 @@ struct bb_miiphy_bus bb_miiphy_buses[] = {
.priv = fpga_mii[0],
},
{
- .name = trans2,
+ .name = board1,
.init = mii_dummy_init,
.mdio_active = mii_mdio_active,
.mdio_tristate = mii_mdio_tristate,
@@ -612,7 +626,7 @@ struct bb_miiphy_bus bb_miiphy_buses[] = {
.priv = fpga_mii[1],
},
{
- .name = trans3,
+ .name = board2,
.init = mii_dummy_init,
.mdio_active = mii_mdio_active,
.mdio_tristate = mii_mdio_tristate,
@@ -623,7 +637,7 @@ struct bb_miiphy_bus bb_miiphy_buses[] = {
.priv = fpga_mii[2],
},
{
- .name = trans4,
+ .name = board3,
.init = mii_dummy_init,
.mdio_active = mii_mdio_active,
.mdio_tristate = mii_mdio_tristate,
--
1.8.3
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[U-Boot] [PATCH v1 0/4] Fixes on gdsys boards and some new functionality
From: Dirk Eibach dirk.eib...@gdsys.cc Since I will be on parental leave soon, Reinhard will probably take over maintaining this series at some point. Dirk Eibach (4): powerpc/ppc4xx: Add support for iocon fiber powerpc/ppc4xx: Add support for iocon-2 powerpc/ppc4xx: Do full iocon PHY initialization in software powerpc/ppc4xx: Fix dlvision-10g reset gpio board/gdsys/405ep/iocon.c | 278 - include/configs/dlvision-10g.h | 4 +- 2 files changed, 224 insertions(+), 58 deletions(-) -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1 1/4] powerpc/ppc4xx: Add support for iocon fiber
From: Dirk Eibach dirk.eib...@gdsys.cc
Add a new iocon flavor with fiber instead of copper connectivity.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
board/gdsys/405ep/iocon.c | 44
1 file changed, 36 insertions(+), 8 deletions(-)
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
index 9f84fb1..f6502b3 100644
--- a/board/gdsys/405ep/iocon.c
+++ b/board/gdsys/405ep/iocon.c
@@ -44,6 +44,8 @@ enum {
HWVER_120 = 3,
HWVER_200 = 4,
HWVER_210 = 5,
+ HWVER_220 = 6,
+ HWVER_230 = 7,
};
enum {
@@ -74,6 +76,11 @@ enum {
};
enum {
+ CARRIER_SPEED_1G = 0,
+ CARRIER_SPEED_2_5G = 1,
+};
+
+enum {
MCFPGA_DONE = 1 0,
MCFPGA_INIT_N = 1 1,
MCFPGA_PROGRAM_N = 1 2,
@@ -168,8 +175,10 @@ static void print_fpga_info(unsigned int fpga)
unsigned feature_audio;
unsigned feature_sysclock;
unsigned feature_ramconfig;
+ unsigned feature_carrier_speed;
unsigned feature_carriers;
unsigned feature_video_channels;
+
int legacy = get_fpga_state(0) FPGA_STATE_PLATFORM;
FPGA_GET_REG(0, versions, versions);
@@ -182,6 +191,7 @@ static void print_fpga_info(unsigned int fpga)
feature_audio = (fpga_features 0x0600) 9;
feature_sysclock = (fpga_features 0x0180) 7;
feature_ramconfig = (fpga_features 0x0060) 5;
+ feature_carrier_speed = fpga_features (14);
feature_carriers = (fpga_features 0x000c) 2;
feature_video_channels = fpga_features 0x0003;
@@ -237,6 +247,14 @@ static void print_fpga_info(unsigned int fpga)
printf( HW-Ver 2.10,);
break;
+ case HWVER_220:
+ printf( HW-Ver 2.20,);
+ break;
+
+ case HWVER_230:
+ printf( HW-Ver 2.30,);
+ break;
+
default:
printf( HW-Ver %d(not supported),,
hardware_version);
@@ -334,7 +352,8 @@ static void print_fpga_info(unsigned int fpga)
break;
}
- printf(, %d carrier(s), feature_carriers);
+ printf(, %d carrier(s) %s, feature_carriers,
+ feature_carrier_speed ? 2.5Gbit/s : 1Gbit/s);
printf(, %d video channel(s)\n, feature_video_channels);
}
@@ -345,6 +364,10 @@ int last_stage_init(void)
unsigned int k;
unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
int legacy = get_fpga_state(0) FPGA_STATE_PLATFORM;
+ u16 fpga_features;
+ int feature_carrier_speed = fpga_features (14);
+
+ FPGA_GET_REG(0, fpga_features, fpga_features);
print_fpga_info(0);
osd_probe(0);
@@ -366,7 +389,7 @@ int last_stage_init(void)
}
}
- if (!legacy) {
+ if (!legacy (feature_carrier_speed == CARRIER_SPEED_1G)) {
miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
bb_miiphy_write);
if (!verify_88e1518(bb_miiphy_buses[0].name, 0)) {
@@ -389,14 +412,19 @@ int last_stage_init(void)
mclink_fpgacount = slaves;
for (k = 1; k = slaves; ++k) {
+ FPGA_GET_REG(k, fpga_features, fpga_features);
+ feature_carrier_speed = fpga_features (14);
+
print_fpga_info(k);
osd_probe(k);
- miiphy_register(bb_miiphy_buses[k].name,
- bb_miiphy_read, bb_miiphy_write);
- if (!verify_88e1518(bb_miiphy_buses[k].name, 0)) {
- printf(Fixup 88e1518 erratum on %s\n,
- bb_miiphy_buses[k].name);
- setup_88e1518(bb_miiphy_buses[k].name, 0);
+ if (feature_carrier_speed == CARRIER_SPEED_1G) {
+ miiphy_register(bb_miiphy_buses[k].name,
+ bb_miiphy_read, bb_miiphy_write);
+ if (!verify_88e1518(bb_miiphy_buses[k].name, 0)) {
+ printf(Fixup 88e1518 erratum on %s\n,
+ bb_miiphy_buses[k].name);
+ setup_88e1518(bb_miiphy_buses[k].name, 0);
+ }
}
}
--
1.8.3
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Re: [U-Boot] [PATCH RESEND 2/5] arm:goni:dfu Add support for DFU at GONI target
On 08/06/2013 07:50 PM, Mateusz Zalega wrote:
From: Arkadiusz Wlodarczyk a.wlodarc...@samsung.com
Proper adjustment for supporting DFU at GONI target has been made.
The s5p_goni.h file has been updated. Moreover the code for low level
USB initialization has been added to GONI board code.
The malloc pool has been enlarged in order to support larger buffer
sizes needed by DFU implementation.
Signed-off-by: Arkadiusz Wlodarczyk a.wlodarc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Signed-off-by: Mateusz Zalega m.zal...@samsung.com
Tested-by: Arkadiusz Wlodarczyk a.wlodarc...@samsung.com
Tested-by: Mateusz Zalega m.zal...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
---
board/samsung/goni/goni.c | 7 +++
include/configs/s5p_goni.h | 22 --
2 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c
index c05801d..c605bf5 100644
--- a/board/samsung/goni/goni.c
+++ b/board/samsung/goni/goni.c
@@ -139,4 +139,11 @@ struct s3c_plat_otg_data s5pc110_otg_data = {
.regs_otg = S5PC110_OTG_BASE,
.usb_phy_ctrl = S5PC110_USB_PHY_CONTROL,
};
+
+void board_usb_init(void)
+{
+ debug(USB_udc_probe\n);
+ s3c_udc_probe(s5pc110_otg_data);
+}
+
#endif
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index 6d88874..192acaa 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -38,7 +38,7 @@
* Size of malloc() pool
* 1MB = 0x10, 0x10 = 1024 * 1024
*/
-#define CONFIG_SYS_MALLOC_LEN(CONFIG_ENV_SIZE + (1 20))
+#define CONFIG_SYS_MALLOC_LEN(CONFIG_ENV_SIZE + (16 20))
/*
* select serial console configuration
*/
@@ -70,6 +70,17 @@
#define CONFIG_CMD_ONENAND
#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_MMC
+#define CONFIG_CMD_DFU
+
+/* USB Composite download gadget - g_dnl */
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_MMC
+
+/* USB Samsung's IDs */
+#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
+#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
+#define CONFIG_G_DNL_MANUFACTURER Samsung
#define CONFIG_BOOTDELAY 1
#define CONFIG_ZERO_BOOTDELAY_CHECK
@@ -89,6 +100,10 @@
,60m(qboot)\
,-(UBI)\0
+#define CONFIG_DFU_ALT \
+ u-boot mmc 80 400; \
If we can use 0x800, i want to use the 0x800 instead of 0x400.
Best Regards,
Jaehoon Chung
+ uImage fat 0 2\0 \
+
#define NORMAL_MTDPARTS_DEFAULT MTDPARTS_DEFAULT
#define CONFIG_BOOTCOMMAND run mmcboot
@@ -159,7 +174,9 @@
bootblock=9\0 \
ubiblock=8\0 \
ubi=enabled\0 \
- opts=always_resume=1
+ opts=always_resume=1\0 \
+ dfu_alt_info= CONFIG_DFU_ALT
+
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
@@ -228,5 +245,6 @@
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_S3C_UDC_OTG
#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
#endif /* __CONFIG_H */
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Re: [U-Boot] [PATCH RESEND 4/5] trats: new USB hardware init interface
On 08/06/2013 07:50 PM, Mateusz Zalega wrote:
This commit changes name of an existing initialization function to
board_usb_init(), so that such functions could be reached by every
USB driver and command (ie. do_dfu()).
Signed-off-by: Mateusz Zalega m.zal...@samsung.com
---
board/samsung/trats/trats.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index c8698f3..f8d4b0c 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -26,6 +26,7 @@
#include power/max8997_muic.h
#include power/battery.h
#include power/max17042_fg.h
+#include usb.h
#include usb_mass_storage.h
#include setup.h
@@ -488,10 +489,11 @@ struct s3c_plat_otg_data s5pc210_otg_data = {
.usb_flags = PHY0_SLEEP,
};
-void board_usb_init(void)
+int board_usb_init(enum board_usb_init_type what_to_init)
{
debug(USB_udc_probe\n);
s3c_udc_probe(s5pc210_otg_data);
+ return 0;
Always return 0?
}
#endif
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Re: [U-Boot] [PATCH v3 0/5] ARM: at91: atmel_nand: check ONFI ecc minimum requirement
Hi, Any feedback for those patch series? Best Regards, Josh Wu On 7/3/2013 11:11 AM, Josh Wu wrote: In this patch series, first we make the nand driver can dynamic change sector size and ecc correct bits. Then we enable ONFI ecc parameters check. v2 -- v3: use dev_err/info(host-dev) instead of dev_err/info(NULL). use MTDDEBUG instead of pr_debug(). v1 -- v2: Fixes according to Scoot Wood's suggestion - add a new patch which make all driver can use dev_err, dev_info, dev_dbg. - replace all printk to dev_err or dev_info. - fix pmecc data allocate error handler. - fix the pmecc ecc requirement selection, should use = instead of use . Josh Wu (5): ARM: at91: atmel_nand: pmecc driver will select the galois table by sector size ARM: at91: sama5d3: remove unused definition about PMECC alpha table offset linux/compat.h: move dev_err, dev_info and dev_dbg from usb driver to compat.h mtd: atmel_nand: alloc memory instead of use static array for pmecc data ARM: at91: atmel_nand: add code to check the ONFI parameter ECC requirement arch/arm/include/asm/arch-at91/at91sam9x5.h |6 + arch/arm/include/asm/arch-at91/sama5d3.h|2 - doc/README.atmel_pmecc | 14 -- drivers/mtd/nand/atmel_nand.c | 197 +-- drivers/usb/musb-new/linux-compat.h | 16 --- include/configs/at91sam9x5ek.h |1 - include/configs/sama5d3xek.h|1 - include/linux/compat.h |8 ++ 8 files changed, 201 insertions(+), 44 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] arm: omap3: fix SRAM copy and execution sequence
Fix size calculation in copy of go_to_speed into SRAM.
Use SRAM_CLK_CODE in call to SRAM-based go_to_speed.
Signed-off-by: Albert ARIBAUD albert.u.b...@aribaud.net
---
arch/arm/cpu/armv7/omap3/clock.c | 6 ++
arch/arm/cpu/armv7/omap3/lowlevel_init.S | 8 +++-
2 files changed, 5 insertions(+), 9 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
index 3acbc9c..70c2595 100644
--- a/arch/arm/cpu/armv7/omap3/clock.c
+++ b/arch/arm/cpu/armv7/omap3/clock.c
@@ -183,8 +183,7 @@ static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
* if running from flash, jump to small relocated code
* area in SRAM.
*/
- f_lock_pll = (void *) ((u32) _end_vect - (u32) _start +
- SRAM_VECT_CODE);
+ f_lock_pll = (void *) (SRAM_CLK_CODE);
p0 = readl(prcm_base-clken_pll);
sr32(p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
@@ -401,8 +400,7 @@ static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
* if running from flash, jump to small relocated code
* area in SRAM.
*/
- f_lock_pll = (void *) ((u32) _end_vect - (u32) _start +
- SRAM_VECT_CODE);
+ f_lock_pll = (void *) (SRAM_CLK_CODE);
p0 = readl(prcm_base-clken_pll);
sr32(p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
index bdf74ea..3b0d342 100644
--- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
@@ -69,15 +69,13 @@ ENDPROC(do_omap3_emu_romcode_call)
*/
ENTRY(cpy_clk_code)
/* Copy DPLL code into SRAM */
- adr r0, go_to_speed /* get addr of clock setting code */
- mov r2, #384/* r2 size to copy (div by 32 bytes) */
- mov r1, r1 /* r1 - dest address (passed in) */
- add r2, r2, r0 /* r2 - source end address */
+ adr r0, go_to_speed /* copy from start of go_to_speed... */
+ adr r2, lowlevel_init /* ... up to start of low_level_init */
next2:
ldmia r0!, {r3 - r10} /* copy from source address [r0] */
stmia r1!, {r3 - r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
- bne next2
+ blo next2
mov pc, lr /* back to caller */
ENDPROC(cpy_clk_code)
--
1.8.1.2
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Re: [U-Boot] [PATCH v2 05/12] spi: add Faraday FTSPI010 SPI controller support
On Fri, Aug 9, 2013 at 6:17 AM, Kuo-Jung Su dant...@gmail.com wrote:
Hi Jagan:
Thanks for the comments, but the [spi bus controller: ftssp010]
has been scheduled after the [Faraday A36x platform support] get approved.
In this way, the entire patch itself looks much better clean.
Best Wishes
Dante Su
2013/8/8 Jagan Teki jagannadh.t...@gmail.com:
Hi Kuo-Jung Su,
Please fix the comments I sent on v4.
http://patchwork.ozlabs.org/patch/242023/
Feel free to ask for any quires.
Thanks,
Jagan.
On Thu, Apr 18, 2013 at 2:55 PM, Kuo-Jung Su dant...@gmail.com wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday FTSSP010 is a multi-function controller
which supports I2S/SPI/SSP/AC97/SPDIF.
This patch simpily implements the SPI mode only.
BTW the DMA and CS/Clock control logic has been
altered since revision 1.19.0. So this patch
would 1st detects the revision id of the underlying
chip, and then switch to the corresponding control
routines.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
drivers/spi/Makefile |1 +
drivers/spi/ftssp010_spi.c | 337
drivers/spi/ftssp010_spi.h | 86 +++
3 files changed, 424 insertions(+)
create mode 100644 drivers/spi/ftssp010_spi.c
create mode 100644 drivers/spi/ftssp010_spi.h
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d08609e..947d60e 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
COBJS-$(CONFIG_CF_SPI) += cf_spi.o
COBJS-$(CONFIG_CF_QSPI) += cf_qspi.o
COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
+COBJS-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o
COBJS-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
COBJS-$(CONFIG_ICH_SPI) += ich.o
COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
diff --git a/drivers/spi/ftssp010_spi.c b/drivers/spi/ftssp010_spi.c
new file mode 100644
index 000..4247c8c
--- /dev/null
+++ b/drivers/spi/ftssp010_spi.c
@@ -0,0 +1,337 @@
+/*
+ * Faraday Multi-function Controller - SPI Mode
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su dant...@faraday-tech.com
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for
details.
+ */
+
+#include common.h
+#include asm/io.h
+#include spi.h
+#include malloc.h
+
+#include ftssp010_spi.h
+
+struct ftssp010_chip {
+ void*iobase;
+ uint32_t fifo;
+ uint32_t rev;
+ uint32_t div;
+ uint32_t mode;
+
+ struct {
+ uint32_t iobase;
+ uint32_t pin;
+ } gpio;
+};
+
+static struct ftssp010_chip chip_list[] = {
+#if defined(CONFIG_FTSSP010_BASE) || defined(CONFIG_FTSSP010_BASE0)
+ {
+ .iobase = (void *)CONFIG_FTSSP010_BASE,
+#ifdef CONFIG_FTSSP010_GPIO_BASE
+ .gpio = { CONFIG_FTSSP010_GPIO_BASE,
CONFIG_FTSSP010_GPIO_PIN },
+#endif
+ },
+#endif
+#ifdef CONFIG_FTSSP010_BASE1
+ { .iobase = (void *)CONFIG_FTSSP010_BASE1, },
+#endif
+#ifdef CONFIG_FTSSP010_BASE2
+ { .iobase = (void *)CONFIG_FTSSP010_BASE2, },
+#endif
+#ifdef CONFIG_FTSSP010_BASE3
+ { .iobase = (void *)CONFIG_FTSSP010_BASE3, },
+#endif
+};
+
+/* Register access macros */
+#define SPI_READ(r)le32_to_cpu(readl(r))
+#define SPI_WRITE(v, r)writel(cpu_to_le32(v), r)
+#define SPI_SETBITS(m, r) setbits_le32(r, m)
+#define SPI_CLRBITS(m, r) clrbits_le32(r, m)
+
+#ifdef CONFIG_FTSSP010_GPIO_BASE
+#define SPI_GPIO_READ(p, r)\
+ le32_to_cpu(readl((p)-gpio.iobase + (r)))
+#define SPI_GPIO_WRITE(p, v, r)\
+ writel(cpu_to_le32(v), (p)-gpio.iobase + (r))
+#define SPI_GPIO_SETBITS(p, m, r) \
+ setbits_le32((p)-gpio.iobase + (r), m)
+#define SPI_GPIO_CLRBITS(p, m, r) \
+ clrbits_le32((p)-gpio.iobase + (r), m)
+#endif /* #ifdef CONFIG_FTSSP010_GPIO_BASE */
+
+static int ftssp010_spi_work_transfer_v1_19(struct ftssp010_chip *chip,
+ const void *tx_buf, void *rx_buf, int len, uint flags)
+{
+ struct ftssp010_regs *regs = chip-iobase;
+ const uint8_t *txb = tx_buf;
+ uint8_t *rxb = rx_buf;
+
+ while (len 0) {
+ int i, depth = min(chip-fifo 2, len);
+ uint32_t xmsk = 0;
+
+ if (tx_buf) {
+ for (i = 0; i depth; ++i) {
+ while (!(SPI_READ(regs-sr) SR_TFNF))
+ ;
+ SPI_WRITE(*txb++, regs-dr);
+ }
+ xmsk |= CR2_TXEN | CR2_TXDOE;
+ if ((SPI_READ(regs-cr[2]) xmsk) != xmsk)
+ SPI_SETBITS(xmsk, regs-cr[2]);
+ }
+ if (rx_buf) {
+
[U-Boot] [PATCH][v2] powerpc/common/vsc3316: remove const from vsc3316_config parameter define
Since the parameters need to be modified according to different Serdes
protocols at runtime, the const will block this. Also remove const from
arrays define used by vsc3316_config.
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
changes for V2:
1. changed subject;
2. fix broken on B4xxx boards;
board/freescale/b4860qds/b4860qds_crossbar_con.h | 12 ++--
board/freescale/common/vsc3316_3308.c| 2 +-
board/freescale/common/vsc3316_3308.h| 2 +-
board/freescale/t4qds/t4qds.c| 8
4 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h
b/board/freescale/b4860qds/b4860qds_crossbar_con.h
index 6e64745..db0cf28 100644
--- a/board/freescale/b4860qds/b4860qds_crossbar_con.h
+++ b/board/freescale/b4860qds/b4860qds_crossbar_con.h
@@ -13,10 +13,10 @@
static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10},
{5, 11}, {4, 5}, {2, 6}, {12, 9} };
-static const int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
+static int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-static const int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
+static int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
{7, 8}, {9, 0}, {2, 14}, {12, 15},
{-1, -1}, {-1, -1} };
@@ -25,7 +25,7 @@ static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7},
{0, 1},
{-1, -1}, {-1, -1} };
#ifdef CONFIG_PPC_B4420
-static const int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
+static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
#endif
@@ -35,10 +35,10 @@ static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12,
12}, {-1, -1},
static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9},
{11, 11}, {5, 10}, {6, 3}, {9, 12} };
-static const int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9},
+static int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-static const int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1},
+static int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1},
{7, 8}, {1, 9}, {14, 3}, {15, 12},
{-1, -1}, {-1, -1} };
@@ -47,7 +47,7 @@ static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15},
{0, 1},
{-1, -1}, {-1, -1} };
#ifdef CONFIG_PPC_B4420
-static const int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
+static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
#endif
diff --git a/board/freescale/common/vsc3316_3308.c
b/board/freescale/common/vsc3316_3308.c
index 8a3dc33..97a25e8 100644
--- a/board/freescale/common/vsc3316_3308.c
+++ b/board/freescale/common/vsc3316_3308.c
@@ -31,7 +31,7 @@ int vsc_if_enable(unsigned int vsc_addr)
return i2c_write(vsc_addr, INTERFACE_MODE_REG, 1, data, 1);
}
-int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
unsigned int num_con)
{
unsigned int i;
diff --git a/board/freescale/common/vsc3316_3308.h
b/board/freescale/common/vsc3316_3308.h
index 4003fcd..2a49187 100644
--- a/board/freescale/common/vsc3316_3308.h
+++ b/board/freescale/common/vsc3316_3308.h
@@ -12,7 +12,7 @@
#include errno.h
int vsc_if_enable(unsigned int vsc_addr);
-int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
unsigned int num_con);
int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],
unsigned int num_con);
diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c
index aa6a217..2dade85 100644
--- a/board/freescale/t4qds/t4qds.c
+++ b/board/freescale/t4qds/t4qds.c
@@ -26,16 +26,16 @@
DECLARE_GLOBAL_DATA_PTR;
-static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
+static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
{8, 8}, {9, 9}, {14, 14}, {15, 15} };
-static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
+static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
{10, 10}, {11, 11}, {12, 12}, {13, 13} };
-static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
+static int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
Re: [U-Boot] : Suggestions for SPI driver pusher
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 08/09/2013 04:48 AM, Jagan Teki wrote:
Hi,
FYI: I am trying to prepare the spi driver code to more readable.
As each spi driver has a common set of calls.
header file inclusion Register bit masks
MISC macro definitions
controller reg structure
controller private slave structure
inline func defination
spi_xfer_sub()
spi_setup_slave_sub
spi_cs_is_valid
spi_cs_activate
spi_cs_deactivate
spi_init
spi_setup_slave { spi_setup_slave_sub() }
spi_free_slave
spi_claim_bus
spi_release_bus
spi_xfer code { spi_xfer_sub() }
I am just trying to do the above format at-least from the drivers
which are pushing now onwards.
Please see the reff driver
http://git.denx.de/?p=u-boot/u-boot-spi.git;a=commitdiff;h=1465d055f9d7a81edacf30c9d20a1b51dfcbfa8d
Sounds
like a good idea to me.
- --
Tom
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Version: GnuPG v1.4.11 (GNU/Linux)
Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/
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Re: [U-Boot] Pull request: u-boot-nds32
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 08/08/2013 03:04 PM, ub...@andestech.com wrote: Hi Tom, Please pull the following patch from u-boot-nds32 into your tree. Thanks! The following changes since commit d05bfd0586ccebe96e31976459c8ef45ec65e109: Merge branch 'master' of git://git.denx.de/u-boot-i2c (2013-08-06 09:49:06 -0400) are available in the git repository at: git://git.denx.de/u-boot-nds32.git master Andes (1): nds32: Change of NDS32 Custodian ken kuo (2): nds32: introduce DMA allocation API nds32: fix the missing COBJS-y change MAINTAINERS |2 +- arch/nds32/include/asm/dma-mapping.h | 33 + board/AndesTech/adp-ag102/Makefile |2 +- 3 files changed, 35 insertions(+), 2 deletions(-) create mode 100644 arch/nds32/include/asm/dma-mapping.h Applied to u-boot/master, thanks! - -- Tom -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQIcBAEBAgAGBQJSBNwkAAoJENk4IS6UOR1WQrcP/3OY51BxZKS90i46D4vRFH/Z 9/MS5+EioB4y06cj8ipjoy7rdk2VyVTNIbWCwICa3h1k2lRD35jN+Asra6OxKOnW aPFHDz5JsuyutHehkvds27XF5WnZ06cgdITbelPBJ5DBTn7/z5exaEAZZSEHRZ+D 2B39HDMT9gJuiAE/70iMJg5bh54+z/iQgP1zYTTF8lV2ZosEjjGNK7CWOeju/uI+ H1fYsuF9COP7G6/MTm8fSJ/J2DBnA/+wGLmwBvJTVZUc/U0YdwEzotTk3VbEha7G n7bBbQsX0FtPo8Bn0U2qDugtHkuYthqZe0qaYIKqxEdvvwfK+dNBmwkOMj2wKJkj wFJDJQuySCgzclbqM8O2zIAX1391TkOm9UUj7XDtnds6AQB9ohhjLeSPG6SyFSvz BXoga52t7tQRpa8+HKtmkmBMCKg5fkOyy2iIIeU32lcTJFQ35fZIVq6CNsYPKZzP 9D+L96ZlpayoPwisfCgLSin5anPNAyXbZp0AfVvlPCzNGroit9WtXRnN8UkAtG0Q fTnfIQeA6b8F2XYhW0V3QY9bauu0sEzQtKYpbWSpE69ojQTOGIIE40Wkpv11ZJVC UhjDY+QsHqtVkNj0rgheYqbpVFSw6Cu8c5dhNLWTKg+MqD5DutetGsS3wOVWj1R2 R3LMo5aeRe378F1Q7fgs =45p0 -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v8 RESEND 1/2] NET: Add net_busy_flag if CONFIG_USB_KEYBOARD is defined
This flag is to make console aware that NET transfer is running or not. Signed-off-by: Jim Lin ji...@nvidia.com --- Changes in v2: 1. Change configuration name from CONFIG_CTRLC_POLL_MS to CONFIG_CTRLC_POLL_S. 2. New code will be executed only when CONFIG_CTRLC_POLL_S is defined in configuration header file. 3. Add description in README.console. Changes in v3: 1. Move changes to common/usb_kbd.c and doc/README.usb 2. Rename config setting to CONFIG_USBKB_TESTC_PERIOD. 3. Remove slow response on USB-keyboard input when TFTP boot is not running. Changes in v4: 1. Remove changes in doc/README.usb, common/usb_kbd.c and CONFIG_USBKB_TESTC_PERIOD 2. Modify net/net.c Changes in v5: 1. Change variable name to ctrlc_t_start. 2. Use two calls of get_timer(0) to get time gap. Changes in v6: 1. In common/usb_kbd.c, check net_busy_flag to determine whether we poll USB keyboard status. 2. In include/usb.h, add external variable declaration net_busy_flag Changes in v7: 1. Add CONFIG_USB_KEYBOARD Changes in v8: 1. net/net.c, add __maybe_unused for variable net_busy_flag. net/net.c | 11 +++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/net/net.c b/net/net.c index df94789..65daaa0 100644 --- a/net/net.c +++ b/net/net.c @@ -207,6 +207,8 @@ static int net_check_prereq(enum proto_t protocol); static int NetTryCount; +int __maybe_unused net_busy_flag; + /**/ static int on_bootfile(const char *name, const char *value, enum env_op op, @@ -341,6 +343,9 @@ int NetLoop(enum proto_t protocol) eth_init_state_only(bd); restart: +#ifdef CONFIG_USB_KEYBOARD + net_busy_flag = 0; +#endif net_set_state(NETLOOP_CONTINUE); /* @@ -453,6 +458,9 @@ restart: status_led_set(STATUS_LED_RED, STATUS_LED_ON); #endif /* CONFIG_SYS_FAULT_ECHO_LINK_DOWN, ... */ #endif /* CONFIG_MII, ... */ +#ifdef CONFIG_USB_KEYBOARD + net_busy_flag = 1; +#endif /* * Main packet reception loop. Loop receiving packets until @@ -558,6 +566,9 @@ restart: } done: +#ifdef CONFIG_USB_KEYBOARD + net_busy_flag = 0; +#endif #ifdef CONFIG_CMD_TFTPPUT /* Clear out the handlers */ net_set_udp_handler(NULL); -- 1.7.7 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v8 RESEND 2/2] console: usb: kbd: To improve TFTP booting performance
TFTP booting is slow when a USB keyboard is installed and
stdin has usbkbd added.
This fix is to change Ctrl-C polling for USB keyboard to every second
when NET transfer is running.
Signed-off-by: Jim Lin ji...@nvidia.com
---
Changes in v2:
1. Change configuration name from CONFIG_CTRLC_POLL_MS to CONFIG_CTRLC_POLL_S.
2. New code will be executed only when CONFIG_CTRLC_POLL_S is defined in
configuration header file.
3. Add description in README.console.
Changes in v3:
1. Move changes to common/usb_kbd.c and doc/README.usb
2. Rename config setting to CONFIG_USBKB_TESTC_PERIOD.
3. Remove slow response on USB-keyboard input when TFTP boot is not running.
Changes in v4:
1. Remove changes in doc/README.usb, common/usb_kbd.c and
CONFIG_USBKB_TESTC_PERIOD
2. Modify net/net.c
Changes in v5:
1. Change variable name to ctrlc_t_start.
2. Use two calls of get_timer(0) to get time gap.
Changes in v6:
1. In common/usb_kbd.c, check net_busy_flag to determine whether we poll
USB keyboard status.
2. In include/usb.h, add external variable declaration net_busy_flag
Changes in v7:
1. In common/usb_kbd.c and include/usb.h, add #ifdef CONFIG_CMD_NET.
2. In common/usb_kbd.c, modify code to get correct time gap.
Changes in v8:
1. Add __maybe_unused for variable kbd_testc_tms.
common/usb_kbd.c | 13 +
include/usb.h|2 +-
2 files changed, 14 insertions(+), 1 deletions(-)
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index 3174b5e..4e7b304 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -121,6 +121,9 @@ struct usb_kbd_pdata {
uint8_t flags;
};
+/* The period of time between two calls of usb_kbd_testc(). */
+static unsigned long __maybe_unused kbd_testc_tms;
+
/* Generic keyboard event polling. */
void usb_kbd_generic_poll(void)
{
@@ -366,6 +369,16 @@ static int usb_kbd_testc(void)
struct usb_device *usb_kbd_dev;
struct usb_kbd_pdata *data;
+#ifdef CONFIG_CMD_NET
+ /*
+* If net_busy_flag is 1, NET transfer is running,
+* then we check key-pressed every second (first check may be
+* less than 1 second) to improve TFTP booting performance.
+*/
+ if (net_busy_flag (get_timer(kbd_testc_tms) CONFIG_SYS_HZ))
+ return 0;
+ kbd_testc_tms = get_timer(0);
+#endif
dev = stdio_get_by_name(DEVNAME);
usb_kbd_dev = (struct usb_device *)dev-priv;
data = usb_kbd_dev-privptr;
diff --git a/include/usb.h b/include/usb.h
index d7b082d..5c95bf5 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -206,7 +206,7 @@ int usb_host_eth_scan(int mode);
int drv_usb_kbd_init(void);
int usb_kbd_deregister(void);
-
+extern int __maybe_unused net_busy_flag;
#endif
/* routines */
int usb_init(void); /* initialize the USB Controller */
--
1.7.7
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Re: [U-Boot] U-Boot mini-summit at ELCE 2013 in Edinburgh - call for participation!
On Thu, Aug 08, 2013 at 11:24:58AM +0200, Wolfgang Denk wrote: Hello all, I think we should bring the upcoming U-Boot mini-summit in Edinburgh back to attention - it's still more than two months, so no reason to panic yet, but as we all know, time flies like an arrow... In message m2ehf8ofw5@lamuella.denx.de Detlev Zundel wrote: Hi fellow U-Boot developers, people meeting us at our booth at the Embedded World trade show in N??rnberg this year may already have heard rumours about it but now it is official - there will be an U-Boot mini-summit at the Emdedd Linux Conference Europe in Edinburgh, UK [1]. Thanks to the wonderful people at the Linux Foundation, we will have some space in the afternoon of thursday 24th that we can use to present and discuss topics of interest for the immediate future of the project. Currently we believe that it makes sense to plan for 4-5 short talks in the range of 20-30 minutes with following QA. The audience will very likely be tech level and the presentations are thus allowed to have indecent technical content :) Of course everybody is invited to suggest a presentation, but an informal poll turned up these topics of interest: - Driver model - Kconfig - Patman tutorial - U-Boot configuration through device tree - Falcon boot for everybody - DFU - Android fastboot The organization of the mini-summit is up to our discretion and thus somewhat less formal than the regular ELCE tracks, but we would like to encourage people to also submit U-Boot related talks through the regular CFP[2] if they are of wide interest. Having agreed on our schedule, we will be able to get it included in the official conference schedule and thus hopefully get a broader visibility. To make this work we should finalize our schedule around the end of the official CFP which is July 21st, but of course the sooner, the better. Please inform us if you would like to attend in order to get an idea of the expected presence. If neccessary we will have to look for a larger place early on. Next to the official program I'm sure that we will be able to find a place in the evening to taste local culinary specialities (in solid and liquid form), so be sure to book your return flight no sooner than friday evening ;) Thanks Detlev [1] http://events.linuxfoundation.org/events/embedded-linux-conference-europe [2] http://events.linuxfoundation.org/events/embedded-linux-conference-europe/cfp The deadline for the CFP has expired - did any of you actually submit a presentation? In any case, if you intend do give a presentation, could you please ASAP send a short summary (title and abstract) to at least Tom, Detlev and me, optionally also to the mailing list (recommended) ? I'll be giving a presentation called Redundant booting with U-Boot (or: Welcome to the redundancy theatre playhouse) that will cover the redundancy features we've had practically for forever (but are now enabled more often in stock configs) as well as some ideas I've had kicking around my head for a while and now have to go and implement. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 0/3] Add TI816X EVM support
On Fri, Jul 26, 2013 at 03:42:49PM +0200, TENART Antoine wrote: Hi, Since the merge window is open, any comment / news on the serie ? Things look good and I shall pick it up soon for u-boot-ti/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH RESEND 4/5] trats: new USB hardware init interface
On 08/09/13 11:30, Jaehoon Chung wrote:
+int board_usb_init(enum board_usb_init_type what_to_init)
{
debug(USB_udc_probe\n);
s3c_udc_probe(s5pc210_otg_data);
+return 0;
Always return 0?
}
You're right, it could pass return value from s3c_udc_probe.
Thanks,
--
Mateusz Zalega
Samsung RD Institute Poland (SRPOL) | Kernel and System Framework group
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Re: [U-Boot] [PATCH v2 00/10] sf: Add support for extended/quad read and write commands
On Thu, Aug 08, 2013 at 01:39:33AM +0530, Jagannadha Sutradharudu Teki wrote: This is v2 series for past read/write instruction support. this series also includes zynq qspi driver patch set for knowing usage of these extended/quad read and write commnads. [snip] REQUEST FOR ALL SPI CODE CONTRIBUTORS/USERS, PLEASE TEST THESE CHANGES W.R.T YOUR HW IF POSSIBLE. What is this against? A git am of the series vs master fails on the first patch. Perhaps a test branch in the u-boot-spi repo would help? I can make sure that am335x_evm is OK still, thanks. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 4/8] ARM: add C function to switch to non-secure state
The core specific part of the work is done in the assembly routine
in nonsec_virt.S, introduced with the previous patch, but for the full
glory we need to setup the GIC distributor interface once for the
whole system, which is done in C here.
The routine is placed in arch/arm/cpu/armv7 to allow easy access from
other ARMv7 boards.
We check the availability of the security extensions first.
Since we need a safe way to access the GIC, we use the PERIPHBASE
registers on Cortex-A15 and A7 CPUs and do some sanity checks.
Boards not implementing the CBAR can override this value via a
configuration file variable.
Then we actually do the GIC enablement:
a) enable the GIC distributor, both for non-secure and secure state
(GICD_CTLR[1:0] = 11b)
b) allow all interrupts to be handled from non-secure state
(GICD_IGROUPRn = 0x)
The core specific GIC setup is then done in the assembly routine.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/cpu/armv7/Makefile | 1 +
arch/arm/cpu/armv7/virt-v7.c | 121 +++
arch/arm/include/asm/armv7.h | 3 ++
3 files changed, 125 insertions(+)
create mode 100644 arch/arm/cpu/armv7/virt-v7.c
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 11a8ad5..5813e87 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -38,6 +38,7 @@ endif
ifneq ($(CONFIG_ARMV7_NONSEC),)
SOBJS += nonsec_virt.o
+COBJS += virt-v7.o
endif
SRCS := $(START:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
new file mode 100644
index 000..689023f
--- /dev/null
+++ b/arch/arm/cpu/armv7/virt-v7.c
@@ -0,0 +1,121 @@
+/*
+ * (C) Copyright 2013
+ * Andre Przywara, Linaro
+ *
+ * Routines to transition ARMv7 processors from secure into non-secure state
+ * needed to enable ARMv7 virtualization for current hypervisors
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/armv7.h
+#include asm/gic.h
+#include asm/io.h
+
+unsigned long gic_dist_addr;
+
+static unsigned int read_id_pfr1(void)
+{
+ unsigned int reg;
+
+ asm(mrc p15, 0, %0, c0, c1, 1\n : =r(reg));
+ return reg;
+}
+
+static unsigned long get_gicd_base_address(void)
+{
+#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
+ return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET;
+#else
+ unsigned midr;
+ unsigned periphbase;
+
+ /* check whether we are an Cortex-A15 or A7.
+* The actual HYP switch should work with all CPUs supporting
+* the virtualization extension, but we need the GIC address,
+* which we know only for sure for those two CPUs.
+*/
+ asm(mrc p15, 0, %0, c0, c0, 0\n : =r(midr));
+ switch (midr MIDR_PRIMARY_PART_MASK) {
+ case MIDR_CORTEX_A9_R0P1:
+ case MIDR_CORTEX_A15_R0P0:
+ case MIDR_CORTEX_A7_R0P0:
+ break;
+ default:
+ printf(nonsec: could not determine GIC address.\n);
+ return -1;
+ }
+
+ /* get the GIC base address from the CBAR register */
+ asm(mrc p15, 4, %0, c15, c0, 0\n : =r (periphbase));
+
+ /* the PERIPHBASE can be mapped above 4 GB (lower 8 bits used to
+* encode this). Bail out here since we cannot access this without
+* enabling paging.
+*/
+ if ((periphbase 0xff) != 0) {
+ printf(nonsec: PERIPHBASE is above 4 GB, no access.\n);
+ return -1;
+ }
+
+ return (periphbase CBAR_MASK) + GIC_DIST_OFFSET;
+#endif
+}
+
+int armv7_switch_nonsec(void)
+{
+ unsigned int reg;
+ unsigned itlinesnr, i;
+
+ /* check whether the CPU supports the security extensions */
+ reg = read_id_pfr1();
+ if ((reg 0xF0) == 0) {
+ printf(nonsec: Security extensions not implemented.\n);
+ return -1;
+ }
+
+ /* the SCR register will be set directly in the monitor mode handler,
+* according to the spec one should not tinker with it in secure state
+* in SVC mode. Do not try to read it once in non-secure state,
+* any access to it will trap.
+*/
+
+
[U-Boot] [PATCH v4 5/8] ARM: trigger non-secure state switch during bootm execution
To actually trigger the non-secure switch we just implemented, call
the switching routine from within the bootm command implementation.
This way we automatically enable this feature without further user
intervention.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/lib/bootm.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 0325d08..6470eac 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -34,6 +34,10 @@
#include asm/bootm.h
#include linux/compiler.h
+#ifdef CONFIG_ARMV7_NONSEC
+#include asm/armv7.h
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
static struct tag *params;
@@ -193,6 +197,14 @@ static void setup_end_tag(bd_t *bd)
__weak void setup_board_tags(struct tag **in_params) {}
+static void do_nonsec_virt_switch(void)
+{
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+ if (armv7_switch_nonsec() == 0)
+ debug(entered non-secure state\n);
+#endif
+}
+
/* Subcommand: PREP */
static void boot_prep_linux(bootm_headers_t *images)
{
@@ -229,6 +241,7 @@ static void boot_prep_linux(bootm_headers_t *images)
printf(FDT and ATAGS support not compiled in - hanging\n);
hang();
}
+ do_nonsec_virt_switch();
}
/* Subcommand: GO */
--
1.7.12.1
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[U-Boot] [PATCH v4 3/8] ARM: add assembly routine to switch to non-secure state
While actually switching to non-secure state is one thing, another part of this process is to make sure that we still have full access to the interrupt controller (GIC). The GIC is fully aware of secure vs. non-secure state, some registers are banked, others may be configured to be accessible from secure state only. To be as generic as possible, we get the GIC memory mapped address based on the PERIPHBASE value in the CBAR register. Since this register is not architecturally defined, we check the MIDR before to be from an A15 or A7. For CPUs not having the CBAR or boards with wrong information herein we allow providing the base address as a configuration variable. Now that we know the GIC address, we: a) allow private interrupts to be delivered to the core (GICD_IGROUPR0 = 0x) b) enable the CPU interface (GICC_CTLR[0] = 1) c) set the priority filter to allow non-secure interrupts (GICC_PMR = 0xFF) Also we allow access to all coprocessor interfaces from non-secure state by writing the appropriate bits in the NSACR register. The generic timer base frequency register is only accessible from secure state, so we have to program it now. Actually this should be done from primary firmware before, but some boards seems to omit this, so if needed we do this here with a board specific value. The Versatile Express board does not need this, so we remove the frequency from the configuration file here. After having switched to non-secure state, we also enable the non-secure GIC CPU interface, since this register is banked. Since we need to call this routine also directly from the smp_pen later (where we don't have any stack), we can only use caller saved registers r0-r3 and r12 to not mess with the compiler. Signed-off-by: Andre Przywara andre.przyw...@linaro.org --- arch/arm/cpu/armv7/nonsec_virt.S| 86 + arch/arm/include/asm/armv7.h| 21 + arch/arm/include/asm/gic.h | 17 include/configs/vexpress_ca15_tc2.h | 2 - 4 files changed, 124 insertions(+), 2 deletions(-) create mode 100644 arch/arm/include/asm/gic.h diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index dbe5c0f..81384df 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -23,6 +23,11 @@ */ #include config.h +#include linux/linkage.h +#include asm/gic.h +#include asm/armv7.h + +.arch_extension sec /* the vector table for secure state */ _monitor_vectors: @@ -53,3 +58,84 @@ _secure_monitor: movspc, lr @ return to non-secure SVC +/* + * Switch a core to non-secure state. + * + * 1. initialize the GIC per-core interface + * 2. allow coprocessor access in non-secure modes + * 3. switch the cpu mode (by calling smc #0) + * + * Called from smp_pen by secondary cores and directly by the BSP. + * Do not assume that the stack is available and only use registers + * r0-r3 and r12. + * + * PERIPHBASE is used to get the GIC address. This could be 40 bits long, + * though, but we check this in C before calling this function. + */ +ENTRY(_nonsec_init) +#ifdef CONFIG_ARM_GIC_BASE_ADDRESS + ldr r2, =CONFIG_ARM_GIC_BASE_ADDRESS +#else + mrc p15, 4, r2, c15, c0, 0 @ read CBAR + bfc r2, #0, #15 @ clear reserved bits +#endif + add r3, r2, #GIC_DIST_OFFSET@ GIC dist i/f offset + mvn r1, #0 @ all bits to 1 + str r1, [r3, #GICD_IGROUPRn]@ allow private interrupts + + mrc p15, 0, r0, c0, c0, 0 @ read MIDR + ldr r1, =MIDR_PRIMARY_PART_MASK + and r0, r0, r1 @ mask out variant and revision + + ldr r1, =MIDR_CORTEX_A7_R0P0 MIDR_PRIMARY_PART_MASK + cmp r0, r1 @ check for Cortex-A7 + + ldr r1, =MIDR_CORTEX_A15_R0P0 MIDR_PRIMARY_PART_MASK + cmpne r0, r1 @ check for Cortex-A15 + + movne r1, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9 + moveq r1, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7 + add r3, r2, r1 @ r3 = GIC CPU i/f addr + + mov r1, #1 @ set GICC_CTLR[enable] + str r1, [r3, #GICC_CTLR]@ and clear all other bits + mov r1, #0xff + str r1, [r3, #GICC_PMR] @ set priority mask register + + movwr1, #0x3fff + movtr1, #0x0006 + mcr p15, 0, r1, c1, c1, 2 @ NSACR = all copros to non-sec + +/* The CNTFRQ register of the generic timer needs to be + * programmed in secure state. Some primary bootloaders / firmware + * omit this, so if the frequency is provided in the configuration, + * we do this here instead. + * But first check if we have the generic timer. + */ +#ifdef CONFIG_SYS_CLK_FREQ + mrc p15,
[U-Boot] [PATCH v4 6/8] ARM: add SMP support for non-secure switch
Currently the non-secure switch is only done for the boot processor.
To enable full SMP support, we have to switch all secondary cores
into non-secure state also.
So we add an entry point for secondary CPUs coming out of low-power
state and make sure we put them into WFI again after having switched
to non-secure state.
For this we acknowledge and EOI the wake-up IPI, then go into WFI.
Once being kicked out of it later, we sanity check that the start
address has actually been changed (since another attempt to switch
to non-secure would block the core) and jump to the new address.
The actual CPU kick is done by sending an inter-processor interrupt
via the GIC to all CPU interfaces except the requesting processor.
The secondary cores will then setup their respective GIC CPU
interface.
While this approach is pretty universal across several ARMv7 boards,
we make this function weak in case someone needs to tweak this for
a specific board.
The way of setting the secondary's start address is board specific,
so each supported board should implement smp_set_boot_cpu_addr().
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/cpu/armv7/nonsec_virt.S | 22 ++
arch/arm/cpu/armv7/virt-v7.c | 16 +++-
arch/arm/include/asm/armv7.h | 1 +
arch/arm/include/asm/gic.h | 2 ++
include/common.h | 2 ++
5 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index 81384df..a88fa6b 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -59,6 +59,28 @@ _secure_monitor:
movspc, lr @ return to non-secure SVC
/*
+ * Secondary CPUs start here and call the code for the core specific parts
+ * of the non-secure and HYP mode transition. The GIC distributor specific
+ * code has already been executed by a C function before.
+ * Then they go back to wfi and wait to be woken up by the kernel again.
+ */
+ENTRY(_smp_pen)
+ mrs r0, cpsr
+ orr r0, r0, #0xc0
+ msr cpsr, r0@ disable interrupts
+ ldr r1, =_start
+ mcr p15, 0, r1, c12, c0, 0 @ set VBAR
+
+ bl _nonsec_init
+
+ ldr r1, [r0, #GICC_IAR] @ acknowledge IPI
+ str r1, [r0, #GICC_EOIR]@ signal end of interrupt
+
+ adr r0, _smp_pen@ do not use this address again
+ b smp_waitloop@ wait for IPIs, board specific
+ENDPROC(_smp_pen)
+
+/*
* Switch a core to non-secure state.
*
* 1. initialize the GIC per-core interface
diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
index 689023f..50f0a3a 100644
--- a/arch/arm/cpu/armv7/virt-v7.c
+++ b/arch/arm/cpu/armv7/virt-v7.c
@@ -79,6 +79,17 @@ static unsigned long get_gicd_base_address(void)
#endif
}
+static void kick_secondary_cpus_gic(unsigned long gicdaddr)
+{
+ /* kick all CPUs (except this one) by writing to GICD_SGIR */
+ writel(1U 24, gicdaddr + GICD_SGIR);
+}
+
+void __weak smp_kick_all_cpus(void)
+{
+ kick_secondary_cpus_gic(gic_dist_addr);
+}
+
int armv7_switch_nonsec(void)
{
unsigned int reg;
@@ -114,7 +125,10 @@ int armv7_switch_nonsec(void)
for (i = 0; i = itlinesnr; i++)
writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
- /* call the non-sec switching code on this CPU */
+ smp_set_core_boot_addr((unsigned long)_smp_pen, -1);
+ smp_kick_all_cpus();
+
+ /* call the non-sec switching code on this CPU also */
_nonsec_init();
return 0;
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index 10ced11..06657fe 100644
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -98,6 +98,7 @@ int armv7_switch_nonsec(void);
/* defined in assembly file */
unsigned int _nonsec_init(void);
+void _smp_pen(void);
#endif /* CONFIG_ARMV7_NONSEC */
#endif /* ! __ASSEMBLY__ */
diff --git a/arch/arm/include/asm/gic.h b/arch/arm/include/asm/gic.h
index c2b1e28..a0891cc 100644
--- a/arch/arm/include/asm/gic.h
+++ b/arch/arm/include/asm/gic.h
@@ -13,5 +13,7 @@
#define GIC_CPU_OFFSET_A15 0x2000
#define GICC_CTLR 0x
#define GICC_PMR 0x0004
+#define GICC_IAR 0x000C
+#define GICC_EOIR 0x0010
#endif
diff --git a/include/common.h b/include/common.h
index e5220cf..05b30d7 100644
--- a/include/common.h
+++ b/include/common.h
@@ -642,6 +642,8 @@ void ft_pci_setup(void *blob, bd_t *bd);
#endif
#endif
+void smp_set_core_boot_addr(unsigned long addr, int corenr);
+void smp_kick_all_cpus(void);
/* $(CPU)/serial.c */
intserial_init (void);
--
1.7.12.1
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[U-Boot] [PATCH v4 2/8] ARM: add secure monitor handler to switch to non-secure state
A prerequisite for using virtualization is to be in HYP mode, which requires the CPU to be in non-secure state first. Add a new file in arch/arm/cpu/armv7 to hold a monitor handler routine which switches the CPU to non-secure state by setting the NS and associated bits. According to the ARM architecture reference manual this should not be done in SVC mode, so we have to setup a SMC handler for this. We create a new vector table to avoid interference with other boards. The MVBAR register will be programmed later just before the smc call. Signed-off-by: Andre Przywara andre.przyw...@linaro.org --- arch/arm/cpu/armv7/Makefile | 4 +++ arch/arm/cpu/armv7/nonsec_virt.S | 55 2 files changed, 59 insertions(+) create mode 100644 arch/arm/cpu/armv7/nonsec_virt.S diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 7a8c2d0..11a8ad5 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -36,6 +36,10 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONF SOBJS += lowlevel_init.o endif +ifneq ($(CONFIG_ARMV7_NONSEC),) +SOBJS += nonsec_virt.o +endif + SRCS := $(START:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) START := $(addprefix $(obj),$(START)) diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S new file mode 100644 index 000..dbe5c0f --- /dev/null +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -0,0 +1,55 @@ +/* + * code for switching cores into non-secure state + * + * Copyright (c) 2013 Andre Przywara andre.przyw...@linaro.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include config.h + +/* the vector table for secure state */ +_monitor_vectors: + .word 0 /* reset */ + .word 0 /* undef */ + adr pc, _secure_monitor + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 /* pad */ + +/* + * secure monitor handler + * U-boot calls this software interrupt in start.S + * This is executed on a smc instruction, we use a smc #0 to switch + * to non-secure state. + * We use only r0 and r1 here, due to constraints in the caller. + */ + .align 5 +_secure_monitor: + mrc p15, 0, r1, c1, c1, 0 @ read SCR + bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits + orr r1, r1, #0x31 @ enable NS, AW, FW bits + + mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set) + + movspc, lr @ return to non-secure SVC + -- 1.7.12.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 1/8] ARM: prepare armv7.h to be included from assembly source
armv7.h contains some useful constants, but also C prototypes. To include it also in assembly files, protect the non-assembly part appropriately. Signed-off-by: Andre Przywara andre.przyw...@linaro.org --- arch/arm/include/asm/armv7.h | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index a73630b..20caa7c 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -23,7 +23,6 @@ */ #ifndef ARMV7_H #define ARMV7_H -#include linux/types.h /* Cortex-A9 revisions */ #define MIDR_CORTEX_A9_R0P10x410FC091 @@ -57,6 +56,9 @@ #define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3 #define ARMV7_CLIDR_CTYPE_UNIFIED 4 +#ifndef __ASSEMBLY__ +#include linux/types.h + /* * CP15 Barrier instructions * Please note that we have separate barrier instructions in ARMv7 @@ -74,4 +76,6 @@ void v7_outer_cache_inval_all(void); void v7_outer_cache_flush_range(u32 start, u32 end); void v7_outer_cache_inval_range(u32 start, u32 end); +#endif /* ! __ASSEMBLY__ */ + #endif -- 1.7.12.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 0/8] ARMv7: Add HYP mode switching support
(for GIT URL and Changelog see below) ARM CPUs with the virtualization extension have a new mode called HYP mode, which allows hypervisors to safely control and monitor guests. The current hypervisor implementations (KVM and Xen) require the kernel to be entered in that HYP mode. This patch series introduces a configuration variable CONFIG_ARMV7_VIRT which enables code to switch all cores into HYP mode. This is done automatically during execution of the bootm command. The process of switching into HYP mode requires the CPU to be in secure state initially when entering u-boot, it will then setup some register and switch to non-secure state. This requires the GIC to be programmed properly first. Explanations about the details are in the commit messages of the respective patches. The patches are structured like this: 1/8: prepare header file 2/8: add monitor handler (assembly) 3/8: add per CPU non-secure switch routine (assembly) 4/8: add system wide non-secure setup (C) 5/8: trigger non-secure switch during bootm command 6/8: add generic SMP functionality 7/8: add HYP mode switching 8/8: board specific code for ARM Versatile Express TC2 Since up to patch 6/8 this code works on non-virtualization capable CPUs also and there has been a request, there is now a second configuration variable CONFIG_ARMV7_NONSEC, which omits the final HYP mode switch and just goes into non-secure SVC state. You can specify either (or none) of them, the code cares about the dependency. The code aims to be as generic as possible, though currently it has only been tested on the Versatile Express TC-2 board. The last patch thus enables the feature for that board and should serve as an example for supporting other boards. For convenience there is a GIT tree which you can pull these patches from (hypmode_v4 branch): git://git.linaro.org/people/aprzywara/u-boot.git Changes RFC..v1 * not a dedicated command anymore, code run by bootm friends * protecting code with #ifdefs to avoid unnecessary inclusion and accidental crashing (when accessing restricted registers) * moving prototypes to header file to meet checkpatch recommendation * adding comment as proposed by Christoffer Changes v1..v2 mostly style and code layout changes * restructure assembly code to live in a new file and not start.S * split smp, nonsec_init and hyp_init to be separate functions * used named constants from common header files * split C function to be more readable * extend comments to be more precise and elaborate * add provision to override GIC base address (needed for Arndale?) * add configuration variable to enable VExpress specific SMP code * use writel/readl for MMIO GIC accesses * remove superfluous isb instructions * more minor fixes Changes v2..v3 * fix clobbering of GICC address actually spoiling the stack * do CNTFRQ setup in assembly per core (and not only once per SoC) * moving the new code files into arch/arm/cpu/armv7 * add config variable for doing non-secure switch only * use actual HYP and secure instructions mnemonics instead of the encoded byte sequence. This requires more recent compilers. * make the identification of the CPU core more robust and saner * use enum for error codes and rename them * lots of smaller layout and style fixes Changes v3..v4 * mask reserved bits in CBAR register * move the VExpress board specific SMP code into the board directory * embed error reporting in the respective functions and getting rid of the error code enum at all (by popular demand ;-) * minor style fixes Please review and comment! Contributions and comments to support other boards are welcome. Andre Przywara (8): ARM: prepare armv7.h to be included from assembly source ARM: add secure monitor handler to switch to non-secure state ARM: add assembly routine to switch to non-secure state ARM: add C function to switch to non-secure state ARM: trigger non-secure state switch during bootm execution ARM: add SMP support for non-secure switch ARM: extend non-secure switch to also go into HYP mode ARM: VExpress: enable ARMv7 virt support for VExpress A15 arch/arm/cpu/armv7/Makefile | 5 + arch/arm/cpu/armv7/nonsec_virt.S| 196 arch/arm/cpu/armv7/virt-v7.c| 172 arch/arm/include/asm/armv7.h| 33 +- arch/arm/include/asm/gic.h | 19 arch/arm/lib/bootm.c| 18 +++ board/armltd/vexpress/Makefile | 7 +- board/armltd/vexpress/vexpress_common.c | 13 +++ board/armltd/vexpress/vexpress_smp.S| 36 ++ include/common.h| 2 + include/configs/vexpress_ca15_tc2.h | 4 +- 11 files changed, 501 insertions(+), 4 deletions(-) create mode 100644 arch/arm/cpu/armv7/nonsec_virt.S create mode 100644 arch/arm/cpu/armv7/virt-v7.c create mode 100644 arch/arm/include/asm/gic.h create mode 100644 board/armltd/vexpress/vexpress_smp.S -- 1.7.12.1
[U-Boot] [PATCH v4 8/8] ARM: VExpress: enable ARMv7 virt support for VExpress A15
To enable hypervisors utilizing the ARMv7 virtualization extension
on the Versatile Express board with the A15 core tile, we add the
required configuration variable.
Also we define the board specific functions to do the SMP bringup:
smp_set_cpu_boot_addr() to set the start address for secondary cores
and smp_waitloop() to wait for IPIs and jump to the start address.
This also serves as an example for what to do when adding support for
new boards.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
board/armltd/vexpress/Makefile | 7 +--
board/armltd/vexpress/vexpress_common.c | 13
board/armltd/vexpress/vexpress_smp.S| 36 +
include/configs/vexpress_ca15_tc2.h | 4
4 files changed, 58 insertions(+), 2 deletions(-)
create mode 100644 board/armltd/vexpress/vexpress_smp.S
diff --git a/board/armltd/vexpress/Makefile b/board/armltd/vexpress/Makefile
index 6719f3d..282ef6d 100644
--- a/board/armltd/vexpress/Makefile
+++ b/board/armltd/vexpress/Makefile
@@ -26,9 +26,12 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(BOARD).o
COBJS := vexpress_common.o
+ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),)
+SOBJS := vexpress_smp.o
+endif
-SRCS := $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
+SRCS := $(COBJS:.o=.c) $(SOBJS:.o=.S)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
$(LIB):$(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
diff --git a/board/armltd/vexpress/vexpress_common.c
b/board/armltd/vexpress/vexpress_common.c
index 2c54869..66b810d 100644
--- a/board/armltd/vexpress/vexpress_common.c
+++ b/board/armltd/vexpress/vexpress_common.c
@@ -272,3 +272,16 @@ ulong get_tbclk(void)
{
return (ulong)CONFIG_SYS_HZ;
}
+
+/* Setting the address at which secondary cores start from.
+ * Versatile Express uses one address for all cores, so ignore corenr
+ */
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+ /* The SYSFLAGS register on VExpress needs to be cleared first
+* by writing to the next address, since any writes to the address
+* at offset 0 will only be ORed in
+*/
+ writel(~0, CONFIG_SYSFLAGS_ADDR + 4);
+ writel(addr, CONFIG_SYSFLAGS_ADDR);
+}
diff --git a/board/armltd/vexpress/vexpress_smp.S
b/board/armltd/vexpress/vexpress_smp.S
new file mode 100644
index 000..41be2e7
--- /dev/null
+++ b/board/armltd/vexpress/vexpress_smp.S
@@ -0,0 +1,36 @@
+/*
+ * code for redirecting secondary cores to their start address
+ *
+ * Copyright (c) 2013 Andre Przywara andre.przyw...@linaro.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include config.h
+#include linux/linkage.h
+
+/* void _smp_waitloop(unsigned previous_address); */
+ENTRY(smp_waitloop)
+ wfi
+ ldr r1, =CONFIG_SYSFLAGS_ADDR @ load start address
+ ldr r1, [r1]
+ cmp r0, r1 @ make sure we dont execute this code
+ beq smp_waitloop@ again (due to a spurious wakeup)
+ mov pc, r1
+ENDPROC(smp_waitloop)
diff --git a/include/configs/vexpress_ca15_tc2.h
b/include/configs/vexpress_ca15_tc2.h
index 4f425ac..14aa78e 100644
--- a/include/configs/vexpress_ca15_tc2.h
+++ b/include/configs/vexpress_ca15_tc2.h
@@ -31,4 +31,8 @@
#include vexpress_common.h
#define CONFIG_BOOTP_VCI_STRING U-boot.armv7.vexpress_ca15x2_tc2
+#define CONFIG_SYSFLAGS_ADDR 0x1c010030
+
+#define CONFIG_ARMV7_VIRT
+
#endif
--
1.7.12.1
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[U-Boot] [PATCH v4 7/8] ARM: extend non-secure switch to also go into HYP mode
For the KVM and XEN hypervisors to be usable, we need to enter the kernel in HYP mode. Now that we already are in non-secure state, HYP mode switching is within short reach. While doing the non-secure switch, we have to enable the HVC instruction and setup the HYP mode HVBAR (while still secure). The actual switch is done by dropping back from a HYP mode handler without actually leaving HYP mode, so we introduce a new handler routine in our new secure exception vector table. In the assembly switching routine we save and restore the banked LR and SP registers around the hypercall to do the actual HYP mode switch. The C routine first checks whether we are in HYP mode already and also whether the virtualization extensions are available. It also checks whether the HYP mode switch was finally successful. The bootm command part only adds and adjusts some error reporting. Signed-off-by: Andre Przywara andre.przyw...@linaro.org --- arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/cpu/armv7/nonsec_virt.S | 43 +++- arch/arm/cpu/armv7/virt-v7.c | 37 ++ arch/arm/include/asm/armv7.h | 6 -- arch/arm/lib/bootm.c | 7 ++- 5 files changed, 86 insertions(+), 9 deletions(-) diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 5813e87..c20df3d 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -36,7 +36,7 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONF SOBJS += lowlevel_init.o endif -ifneq ($(CONFIG_ARMV7_NONSEC),) +ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),) SOBJS += nonsec_virt.o COBJS += virt-v7.o endif diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index a88fa6b..fb1651d 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -1,5 +1,5 @@ /* - * code for switching cores into non-secure state + * code for switching cores into non-secure state and into HYP mode * * Copyright (c) 2013 Andre Przywara andre.przyw...@linaro.org * @@ -28,15 +28,16 @@ #include asm/armv7.h .arch_extension sec +.arch_extension virt -/* the vector table for secure state */ +/* the vector table for secure state and HYP mode */ _monitor_vectors: .word 0 /* reset */ .word 0 /* undef */ adr pc, _secure_monitor .word 0 .word 0 - .word 0 + adr pc, _hyp_trap .word 0 .word 0 .word 0 /* pad */ @@ -54,10 +55,27 @@ _secure_monitor: bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits orr r1, r1, #0x31 @ enable NS, AW, FW bits +#ifdef CONFIG_ARMV7_VIRT + mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 + and r0, r0, #CPUID_ARM_VIRT_MASK@ mask virtualization bits + cmp r0, #(1 CPUID_ARM_VIRT_SHIFT) + orreq r1, r1, #0x100 @ allow HVC instruction +#endif + mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set) +#ifdef CONFIG_ARMV7_VIRT + mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value + mcreq p15, 4, r0, c12, c0, 0 @ write HVBAR +#endif + movspc, lr @ return to non-secure SVC +_hyp_trap: + mrs lr, elr_hyp @ for older asm: .byte 0x00, 0xe3, 0x0e, 0xe1 + mov pc, lr @ do no switch modes, but + @ return to caller + /* * Secondary CPUs start here and call the code for the core specific parts * of the non-secure and HYP mode transition. The GIC distributor specific @@ -72,9 +90,13 @@ ENTRY(_smp_pen) mcr p15, 0, r1, c12, c0, 0 @ set VBAR bl _nonsec_init + mov r12, r0 @ save GICC address +#ifdef CONFIG_ARMV7_VIRT + bl _switch_to_hyp +#endif - ldr r1, [r0, #GICC_IAR] @ acknowledge IPI - str r1, [r0, #GICC_EOIR]@ signal end of interrupt + ldr r1, [r12, #GICC_IAR]@ acknowledge IPI + str r1, [r12, #GICC_EOIR] @ signal end of interrupt adr r0, _smp_pen@ do not use this address again b smp_waitloop@ wait for IPIs, board specific @@ -161,3 +183,14 @@ ENTRY(_nonsec_init) bx lr ENDPROC(_nonsec_init) + +ENTRY(_switch_to_hyp) + mov r0, lr + mov r1, sp @ save SVC copy of LR and SP + isb + hvc #0 @ for older asm: .byte 0x70, 0x00, 0x40, 0xe1 + mov sp, r1 + mov lr, r0 @ restore SVC copy of LR and SP + + bx lr +ENDPROC(_switch_to_hyp) diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index 50f0a3a..4dc8c45
[U-Boot] [PATCH v2 2/9] am33xx: Stop using PHYS_DRAM_1 define
We defined PHYS_DRAM_1 to 0x8000 (start of DRAM) and then used this
for CONFIG_SYS_SDRAM_BASE. But then we kept on referencing PHYS_DRAM_1
in other places. Change to directly setting CONFIG_SYS_DRAM_BASE and
then using that name in code.
Signed-off-by: Tom Rini tr...@ti.com
---
board/isee/igep0033/board.c |2 +-
board/phytec/pcm051/board.c |2 +-
board/ti/am335x/board.c |2 +-
board/ti/ti814x/evm.c|2 +-
include/configs/igep0033.h |3 +--
include/configs/pcm051.h |5 ++---
include/configs/ti814x_evm.h |5 ++---
7 files changed, 9 insertions(+), 12 deletions(-)
diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
index c0f0c0d..7a66e33 100644
--- a/board/isee/igep0033/board.c
+++ b/board/isee/igep0033/board.c
@@ -119,7 +119,7 @@ void s_init(void)
*/
int board_init(void)
{
- gd-bd-bi_boot_params = PHYS_DRAM_1 + 0x100;
+ gd-bd-bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gpmc_init();
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index 6291d03..77202f7 100644
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -135,7 +135,7 @@ int board_init(void)
{
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- gd-bd-bi_boot_params = PHYS_DRAM_1 + 0x100;
+ gd-bd-bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 728afc2..88663ea 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -371,7 +371,7 @@ int board_init(void)
STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 };
#endif
- gd-bd-bi_boot_params = PHYS_DRAM_1 + 0x100;
+ gd-bd-bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gpmc_init();
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
index c469645..26d2f9b 100644
--- a/board/ti/ti814x/evm.c
+++ b/board/ti/ti814x/evm.c
@@ -161,7 +161,7 @@ void s_init(void)
*/
int board_init(void)
{
- gd-bd-bi_boot_params = PHYS_DRAM_1 + 0x100;
+ gd-bd-bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
diff --git a/include/configs/igep0033.h b/include/configs/igep0033.h
index c8480dc..2b9e8ab 100644
--- a/include/configs/igep0033.h
+++ b/include/configs/igep0033.h
@@ -131,10 +131,9 @@
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
-#define PHYS_DRAM_10x8000 /* DRAM Bank #1 */
#define CONFIG_MAX_RAM_BANK_SIZE (1024 20)/* 1GB */
-#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
+#define CONFIG_SYS_SDRAM_BASE 0x8000
#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
GENERATED_GBL_DATA_SIZE)
/* Platform/Board specific defs */
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
index fe8350f..044a857 100644
--- a/include/configs/pcm051.h
+++ b/include/configs/pcm051.h
@@ -122,7 +122,7 @@
* memtest works on 8 MB in DRAM after skipping 32MB from
* start addr of ram disk
*/
-#define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64 * 1024 * 1024))
+#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + (64 20))
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \
+ (8 * 1024 * 1024))
@@ -146,10 +146,9 @@
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
-#define PHYS_DRAM_10x8000 /* DRAM Bank #1 */
#define CONFIG_MAX_RAM_BANK_SIZE (1024 19)/* 512MiB */
-#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
+#define CONFIG_SYS_SDRAM_BASE 0x8000
#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
GENERATED_GBL_DATA_SIZE)
/* Platform/Board specific defs */
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
index b036e1b..91485e2 100644
--- a/include/configs/ti814x_evm.h
+++ b/include/configs/ti814x_evm.h
@@ -116,7 +116,7 @@
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE
-#define CONFIG_SYS_MEMTEST_START PHYS_DRAM_1
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \
+ PHYS_DRAM_1_SIZE - (8 12))
@@ -136,11 +136,10 @@
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* 1 banks of DRAM */
-#define PHYS_DRAM_10x8000 /* DRAM Bank #1 */
#define PHYS_DRAM_1_SIZE 0x2000 /* 512MB */
#define CONFIG_MAX_RAM_BANK_SIZE (1024 20)/* 1024MB */
-#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
+#define CONFIG_SYS_SDRAM_BASE 0x8000
#define
[U-Boot] [PATCH v2 3/9] am335x_evm: Use default baud rate table
Signed-off-by: Tom Rini tr...@ti.com
---
include/configs/am335x_evm.h |2 --
1 file changed, 2 deletions(-)
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index e32066d..7d755f1 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -314,8 +314,6 @@
#define CONFIG_OMAP_GPIO
#define CONFIG_BAUDRATE115200
-#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \
-4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
/* CPU */
#define CONFIG_ARCH_CPU_INIT
--
1.7.9.5
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[U-Boot] [PATCH v2 0/9] Introduce common config file for TI ARMv7 platforms
Hey all, The following series cleans up am335x a bit, and then uses that to introduce a common config file that can be used on all of the ARMv7 platforms from TI. This series converts am335x_evm, omap5_uevm and dra7xx_evm to use the new structure. There is room for further cleanup and consolidation but as they are invasive patches I don't want to hold these for too long. This is on top of u-boot-arm/master. The changes since v1 are to address Dan's comments, add links to the TI site for where to find docs for the SoC family and drop the first patch about V_OSCK after Heiko and Lars comments. Acked/Tested-bys are added for otherwise unchanged parts. -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 8/9] TI:armv7: Enable CONFIG_CMD_SPI
Add the generic poke the SPI bus command, with the SPI related defines. Acked-by: Dan Murphy dmur...@ti.com Signed-off-by: Tom Rini tr...@ti.com --- include/configs/ti_armv7_common.h |1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 893a08e..0eaa59b 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -75,6 +75,7 @@ /* McSPI IP block */ #define CONFIG_SPI #define CONFIG_OMAP3_SPI +#define CONFIG_CMD_SPI /* GPIO block */ #define CONFIG_OMAP_GPIO -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 9/9] TI:armv7: Enable CONFIG_CMD_GPIO
Add the generic poke a GPIO command, with the GPIO related defines. Acked-by: Dan Murphy dmur...@ti.com Signed-off-by: Tom Rini tr...@ti.com --- include/configs/ti_armv7_common.h |1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 0eaa59b..a49a37c 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -79,6 +79,7 @@ /* GPIO block */ #define CONFIG_OMAP_GPIO +#define CONFIG_CMD_GPIO /* * GPMC NAND block. We support 1 device and the physical address to -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 7/9] TI:omap5/dra7xx: Convert to ti_armv7_common.h
Update omap5_common.h to use ti_armv7_common.h, and in turn update dra7xx_evm.h and omap5_uevm.h slightly. The biggest changes here are that IP blocks which exist on the platform, and had clocks enabled, now have the drivers being built as well. Signed-off-by: Tom Rini tr...@ti.com --- Changes in v2: - Address Dan Murphy's comments - Add link to OMAP5432 docs --- include/configs/dra7xx_evm.h | 11 +-- include/configs/omap5_common.h | 191 ++-- include/configs/omap5_uevm.h |8 +- 3 files changed, 34 insertions(+), 176 deletions(-) diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 51be73d..58786ff 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -12,21 +12,18 @@ #ifndef __CONFIG_DRA7XX_EVM_H #define __CONFIG_DRA7XX_EVM_H -/* High Level Configuration Options */ -#define CONFIG_DRA7XX /* in a TI DRA7XX core */ -#define CONFIG_ENV_IS_NOWHERE /* For now. */ - -#include configs/omap5_common.h +#define CONFIG_DRA7XX -#define CONFIG_SYS_PROMPT DRA752 EVM # +#define CONFIG_ENV_IS_NOWHERE /* For now. */ +#define CONSOLEDEV ttyO0 #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_COM1UART1_BASE #define CONFIG_BAUDRATE115200 #define CONFIG_SYS_OMAP_ABE_SYSCK -#define CONSOLEDEV ttyO0 +#include configs/omap5_common.h /* CPSW Ethernet */ #define CONFIG_CMD_NET diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h index 7dd56cf..8e82fed 100644 --- a/include/configs/omap5_common.h +++ b/include/configs/omap5_common.h @@ -9,111 +9,59 @@ * TI OMAP5 AND DRA7XX common configuration settings * * SPDX-License-Identifier:GPL-2.0+ + * + * For more details, please see the technical documents listed at + * http://www.ti.com/product/omap5432 */ #ifndef __CONFIG_OMAP5_COMMON_H #define __CONFIG_OMAP5_COMMON_H -/* - * High Level Configuration Options - */ -#define CONFIG_OMAP/* in a TI OMAP core */ -#define CONFIG_OMAP54XX/* which is a 54XX */ -#define CONFIG_OMAP_GPIO - -/* Get CPU defs */ -#include asm/arch/cpu.h -#include asm/arch/omap.h - -/* Display CPU and Board Info */ +#define CONFIG_OMAP54XX #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_MISC_INIT_R +#define CONFIG_ARCH_CPU_INIT -#define CONFIG_OF_LIBFDT -#define CONFIG_CMD_BOOTZ +#define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG +/* Use General purpose timer 1 */ +#define CONFIG_SYS_TIMERBASE GPT2_BASE + +#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS + +/* Defines for SDRAM init */ +#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION +#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS +#endif + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_PALMAS_POWER +#endif + +#include asm/arch/cpu.h +#include asm/arch/omap.h -/* - * Size of malloc() pool - * Total Size Environment - 128k - * Malloc - add 256k - */ #define CONFIG_ENV_SIZE(128 10) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 10)) -/* Vector Base */ -#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE -/* - * Hardware drivers - */ +#include configs/ti_armv7_common.h /* - * serial port - NS16550 compatible + * Hardware drivers */ -#define V_NS16550_CLK 4800 - #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE(-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* CPU */ -#define CONFIG_ARCH_CPU_INIT - -/* I2C */ -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 10 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C -#define CONFIG_I2C_MULTI_BUS - -/* MMC */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_OMAP_HSMMC -#define CONFIG_DOS_PARTITION - -#define CONFIG_SYS_CONSOLE_IS_IN_ENV - -/* Flash */ -#define CONFIG_SYS_NO_FLASH - -/* Cache */ -#define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_SYS_CACHELINE_SHIFT 6 - -/* commands to include */ -#include config_cmd_default.h - -/* Enabled commands */ -#define CONFIG_CMD_EXT2/* EXT2 Support */ -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_SYS_NS16550_CLK 4800 -/* Disabled commands */ +/* Per-SoC commands */ #undef CONFIG_CMD_NET #undef CONFIG_CMD_NFS -#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ -#undef CONFIG_CMD_IMLS /* List all found images*/ /* * Environment setup */ - -#define CONFIG_BOOTDELAY
[U-Boot] [PATCH v2 6/9] TI:am33xx: Create common config files for TI ARMv7 platforms, and AM33xx
We create two new files, include/configs/ti_armv7_common.h for all of the common IP blocks and related features / commands we share in virtually all of our platforms. We then create include/configs/ti_am335x_common.h for everything common to the am335x SoC leaving just the board specific parts to include/configs/ti_am335x_common.h. Signed-off-by: Tom Rini tr...@ti.com --- Changes in v2: - Address Dan Murphy's comments - Add link to am335x documentation from TI --- include/configs/am335x_evm.h | 235 +++--- include/configs/ti_am335x_common.h | 60 + include/configs/ti_armv7_common.h | 247 3 files changed, 325 insertions(+), 217 deletions(-) create mode 100644 include/configs/ti_am335x_common.h create mode 100644 include/configs/ti_armv7_common.h diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 85c4632..e0a87f8 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -16,43 +16,20 @@ #ifndef __CONFIG_AM335X_EVM_H #define __CONFIG_AM335X_EVM_H -#define CONFIG_AM33XX -#define CONFIG_OMAP +#include configs/ti_am335x_common.h -#include asm/arch/omap.h - -#define CONFIG_DMA_COHERENT -#define CONFIG_DMA_COHERENT_SIZE (1 20) - -#define CONFIG_ENV_SIZE(128 10) /* 128 KiB */ -#define CONFIG_SYS_MALLOC_LEN (1024 10) -#define CONFIG_SYS_LONGHELP/* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use hush command parser */ -#define CONFIG_SYS_PROMPT U-Boot# -#define CONFIG_BOARD_LATE_INIT -#define CONFIG_SYS_NO_FLASH #define MACH_TYPE_TIAM335EVM 3589/* Until the next sync */ #define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM -#define CONFIG_OF_LIBFDT -#define CONFIG_CMD_BOOTZ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_CMDLINE_EDITING -#define CONFIG_STACKSIZE (128 * 1024) -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG +/* Clock Defines */ +#define V_OSCK 2400 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) /* Custom script for NOR */ #define CONFIG_SYS_LDSCRIPTboard/ti/am335x/u-boot.lds -#define CONFIG_SYS_CACHELINE_SIZE 64 - -/* commands to include */ -#include config_cmd_default.h - -#define CONFIG_CMD_ASKENV -#define CONFIG_VERSION_VARIABLE +/* Always 128 KiB env size */ +#define CONFIG_ENV_SIZE(128 10) #ifdef CONFIG_NAND #define NANDARGS \ @@ -75,10 +52,8 @@ #define NANDARGS #endif -/* set to negative value for no autoboot */ -#define CONFIG_BOOTDELAY 1 -#define CONFIG_ENV_VARS_UBOOT_CONFIG #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ loadaddr=0x8020\0 \ @@ -196,60 +171,11 @@ run mmcboot; \ run nandboot; -/* Clock Defines */ -#define V_OSCK 2400 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -#define CONFIG_CMD_ECHO - -/* We set the max number of command args high to avoid HUSH bugs. */ -#define CONFIG_SYS_MAXARGS 64 - -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 512 - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - + sizeof(CONFIG_SYS_PROMPT) + 16) - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE - -/* - * memtest works on 8 MB in DRAM after skipping 32MB from - * start addr of ram disk - */ -#define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64 * 1024 * 1024)) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \ - + (8 * 1024 * 1024)) - -#define CONFIG_SYS_LOAD_ADDR 0x8100 /* Default load address */ - -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_OMAP_HSMMC -#define CONFIG_CMD_MMC -#define CONFIG_DOS_PARTITION -#define CONFIG_CMD_FAT -#define CONFIG_FAT_WRITE -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_EXT4 -#define CONFIG_CMD_FS_GENERIC - -#define CONFIG_SPI -#define CONFIG_OMAP3_SPI -#define CONFIG_MTD_DEVICE -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_WINBOND -#define CONFIG_CMD_SF -#define CONFIG_SF_DEFAULT_SPEED(2400) - /* USB Composite download gadget - g_dnl */ #define CONFIG_USB_GADGET #define CONFIG_USBDOWNLOAD_GADGET /* USB TI's IDs */ -#define CONFIG_USBD_HS #define CONFIG_G_DNL_VENDOR_NUM 0x0403 #define CONFIG_G_DNL_PRODUCT_NUM 0xBD00 #define CONFIG_G_DNL_MANUFACTURER Texas Instruments @@ -283,109 +209,24 @@ rootfs part 0 9 #endif - /* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ -#define PHYS_DRAM_1
[U-Boot] [PATCH v2 4/9] arm: spl: For Falcon Mode, set a default machid of ~0
With device trees, boards do not always set CONFIG_MACH_TYPE now, so we
must not rely on this define being set. The kernel uses ~0 to see if we
have a valid machine number or not, so set that as the default, invalid
machine, id and only fix if CONFIG_MACH_TYPE is set.
Acked-by: Dan Murphy dmur...@ti.com
Tested-by: Heiko Schocher h...@denx.de
Cc: Albert ARIBAUD albert.u.b...@aribaud.net
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/lib/spl.c |7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c
index 583bdb3..26d0be4 100644
--- a/arch/arm/lib/spl.c
+++ b/arch/arm/lib/spl.c
@@ -45,12 +45,17 @@ void __weak board_init_f(ulong dummy)
#ifdef CONFIG_SPL_OS_BOOT
void __noreturn jump_to_image_linux(void *arg)
{
+ unsigned long machid = 0x;
+#ifdef CONFIG_MACH_TYPE
+ machid = CONFIG_MACH_TYPE;
+#endif
+
debug(Entering kernel arg pointer: 0x%p\n, arg);
typedef void (*image_entry_arg_t)(int, int, void *)
__attribute__ ((noreturn));
image_entry_arg_t image_entry =
(image_entry_arg_t) spl_image.entry_point;
cleanup_before_linux();
- image_entry(0, CONFIG_MACH_TYPE, arg);
+ image_entry(0, machid, arg);
}
#endif
--
1.7.9.5
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[U-Boot] [PATCH v2 5/9] am335x_evm: Bring in 'boot_fdt' logic from i.MX
Bring in the 'boot_fdt' environment variable that i.MX boards use to try
and load a device tree when booting.
Signed-off-by: Tom Rini tr...@ti.com
---
include/configs/am335x_evm.h | 21 -
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 7d755f1..85c4632 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -84,6 +84,7 @@
loadaddr=0x8020\0 \
fdtaddr=0x80F8\0 \
fdt_high=0x\0 \
+ boot_fdt=try\0 \
rdaddr=0x8100\0 \
bootdir=/boot\0 \
bootfile=uImage\0 \
@@ -131,6 +132,20 @@
loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0 \
loaduimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0 \
loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0 \
+ mmcloados=run mmcargs; \
+ if test ${boot_fdt} = yes || test ${boot_fdt} = try; then \
+ if run loadfdt; then \
+ bootm ${loadaddr} - ${fdtaddr}; \
+ else \
+ if test ${boot_fdt} = try; then \
+ bootm; \
+ else \
+ echo WARN: Cannot load the DT; \
+ fi; \
+ fi; \
+ else \
+ bootm; \
+ fi;\0 \
mmcboot=mmc dev ${mmcdev}; \
if mmc rescan; then \
echo SD/MMC found on device ${mmcdev}; \
@@ -142,11 +157,7 @@
echo Running uenvcmd ...; \
run uenvcmd; \
fi; \
- if run loaduimage; then \
- run loadfdt; \
- run mmcargs; \
- bootm ${loadaddr} - ${fdtaddr}; \
- fi; \
+ run mmcloados; \
fi;\0 \
spiboot=echo Booting from spi ...; \
run spiargs; \
--
1.7.9.5
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[U-Boot] [PATCH v2 1/9] am33xx: CONFIG_DMA_COHERENT defines are unused, remove
Acked-by: Dan Murphy dmur...@ti.com Signed-off-by: Tom Rini tr...@ti.com --- include/configs/igep0033.h |4 include/configs/pcm051.h |3 --- include/configs/ti814x_evm.h |3 --- 3 files changed, 10 deletions(-) diff --git a/include/configs/igep0033.h b/include/configs/igep0033.h index 12f28f8..c8480dc 100644 --- a/include/configs/igep0033.h +++ b/include/configs/igep0033.h @@ -27,10 +27,6 @@ #define V_OSCK 2400 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -/* DMA defines */ -#define CONFIG_DMA_COHERENT -#define CONFIG_DMA_COHERENT_SIZE (1 20) - #define CONFIG_ENV_SIZE(128 10) /* 128 KiB */ #define CONFIG_SYS_MALLOC_LEN (1024 10) #define CONFIG_SYS_LONGHELP/* undef to save memory */ diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index 9b16c47..fe8350f 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -24,9 +24,6 @@ #include asm/arch/omap.h -#define CONFIG_DMA_COHERENT -#define CONFIG_DMA_COHERENT_SIZE (1 20) - #define CONFIG_ENV_SIZE(128 10) /* 128 KiB */ #define CONFIG_SYS_MALLOC_LEN (1024 10) #define CONFIG_SYS_LONGHELP/* undef to save memory */ diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index eac5ad0..b036e1b 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -23,9 +23,6 @@ #include asm/arch/omap.h -#define CONFIG_DMA_COHERENT -#define CONFIG_DMA_COHERENT_SIZE (1 20) - #define CONFIG_ENV_SIZE(128 10) /* 128 KiB */ #define CONFIG_SYS_MALLOC_LEN (1024 10) #define CONFIG_SYS_LONGHELP/* undef to save memory */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 7/8] ARM: extend non-secure switch to also go into HYP mode
On Fri, Aug 09, 2013 at 05:03:11PM +0200, Andre Przywara wrote: For the KVM and XEN hypervisors to be usable, we need to enter the kernel in HYP mode. Now that we already are in non-secure state, HYP mode switching is within short reach. While doing the non-secure switch, we have to enable the HVC instruction and setup the HYP mode HVBAR (while still secure). The actual switch is done by dropping back from a HYP mode handler without actually leaving HYP mode, so we introduce a new handler routine in our new secure exception vector table. In the assembly switching routine we save and restore the banked LR and SP registers around the hypercall to do the actual HYP mode switch. The C routine first checks whether we are in HYP mode already and also whether the virtualization extensions are available. It also checks whether the HYP mode switch was finally successful. The bootm command part only adds and adjusts some error reporting. Signed-off-by: Andre Przywara andre.przyw...@linaro.org --- arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/cpu/armv7/nonsec_virt.S | 43 +++- arch/arm/cpu/armv7/virt-v7.c | 37 ++ arch/arm/include/asm/armv7.h | 6 -- arch/arm/lib/bootm.c | 7 ++- 5 files changed, 86 insertions(+), 9 deletions(-) diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 5813e87..c20df3d 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -36,7 +36,7 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONF SOBJS+= lowlevel_init.o endif -ifneq ($(CONFIG_ARMV7_NONSEC),) +ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),) SOBJS+= nonsec_virt.o COBJS+= virt-v7.o endif diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index a88fa6b..fb1651d 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -1,5 +1,5 @@ /* - * code for switching cores into non-secure state + * code for switching cores into non-secure state and into HYP mode * * Copyright (c) 2013Andre Przywara andre.przyw...@linaro.org * @@ -28,15 +28,16 @@ #include asm/armv7.h .arch_extension sec +.arch_extension virt -/* the vector table for secure state */ +/* the vector table for secure state and HYP mode */ _monitor_vectors: .word 0 /* reset */ .word 0 /* undef */ adr pc, _secure_monitor .word 0 .word 0 - .word 0 + adr pc, _hyp_trap .word 0 .word 0 .word 0 /* pad */ @@ -54,10 +55,27 @@ _secure_monitor: bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits orr r1, r1, #0x31 @ enable NS, AW, FW bits +#ifdef CONFIG_ARMV7_VIRT + mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 + and r0, r0, #CPUID_ARM_VIRT_MASK@ mask virtualization bits + cmp r0, #(1 CPUID_ARM_VIRT_SHIFT) + orreq r1, r1, #0x100 @ allow HVC instruction +#endif + mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set) +#ifdef CONFIG_ARMV7_VIRT + mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value + mcreq p15, 4, r0, c12, c0, 0 @ write HVBAR +#endif + movspc, lr @ return to non-secure SVC +_hyp_trap: + mrs lr, elr_hyp @ for older asm: .byte 0x00, 0xe3, 0x0e, 0xe1 I see you kep this as is, oh well. + mov pc, lr @ do no switch modes, but + @ return to caller + /* * Secondary CPUs start here and call the code for the core specific parts * of the non-secure and HYP mode transition. The GIC distributor specific @@ -72,9 +90,13 @@ ENTRY(_smp_pen) mcr p15, 0, r1, c12, c0, 0 @ set VBAR bl _nonsec_init + mov r12, r0 @ save GICC address +#ifdef CONFIG_ARMV7_VIRT + bl _switch_to_hyp +#endif - ldr r1, [r0, #GICC_IAR] @ acknowledge IPI - str r1, [r0, #GICC_EOIR]@ signal end of interrupt + ldr r1, [r12, #GICC_IAR]@ acknowledge IPI + str r1, [r12, #GICC_EOIR] @ signal end of interrupt adr r0, _smp_pen@ do not use this address again b smp_waitloop@ wait for IPIs, board specific @@ -161,3 +183,14 @@ ENTRY(_nonsec_init) bx lr ENDPROC(_nonsec_init) + +ENTRY(_switch_to_hyp) + mov r0, lr + mov r1, sp @ save SVC copy of LR and SP + isb + hvc #0 @ for older asm: .byte 0x70, 0x00, 0x40, 0xe1 + mov sp, r1 + mov lr, r0
Re: [U-Boot] [PATCH v4 0/8] ARMv7: Add HYP mode switching support
On Fri, Aug 09, 2013 at 05:03:04PM +0200, Andre Przywara wrote: (for GIT URL and Changelog see below) ARM CPUs with the virtualization extension have a new mode called HYP mode, which allows hypervisors to safely control and monitor guests. The current hypervisor implementations (KVM and Xen) require the kernel to be entered in that HYP mode. This patch series introduces a configuration variable CONFIG_ARMV7_VIRT which enables code to switch all cores into HYP mode. This is done automatically during execution of the bootm command. The process of switching into HYP mode requires the CPU to be in secure state initially when entering u-boot, it will then setup some register and switch to non-secure state. This requires the GIC to be programmed properly first. Explanations about the details are in the commit messages of the respective patches. The patches are structured like this: 1/8: prepare header file 2/8: add monitor handler (assembly) 3/8: add per CPU non-secure switch routine (assembly) 4/8: add system wide non-secure setup (C) 5/8: trigger non-secure switch during bootm command 6/8: add generic SMP functionality 7/8: add HYP mode switching 8/8: board specific code for ARM Versatile Express TC2 Since up to patch 6/8 this code works on non-virtualization capable CPUs also and there has been a request, there is now a second configuration variable CONFIG_ARMV7_NONSEC, which omits the final HYP mode switch and just goes into non-secure SVC state. You can specify either (or none) of them, the code cares about the dependency. The code aims to be as generic as possible, though currently it has only been tested on the Versatile Express TC-2 board. The last patch thus enables the feature for that board and should serve as an example for supporting other boards. For convenience there is a GIT tree which you can pull these patches from (hypmode_v4 branch): git://git.linaro.org/people/aprzywara/u-boot.git Changes RFC..v1 * not a dedicated command anymore, code run by bootm friends * protecting code with #ifdefs to avoid unnecessary inclusion and accidental crashing (when accessing restricted registers) * moving prototypes to header file to meet checkpatch recommendation * adding comment as proposed by Christoffer Changes v1..v2 mostly style and code layout changes * restructure assembly code to live in a new file and not start.S * split smp, nonsec_init and hyp_init to be separate functions * used named constants from common header files * split C function to be more readable * extend comments to be more precise and elaborate * add provision to override GIC base address (needed for Arndale?) * add configuration variable to enable VExpress specific SMP code * use writel/readl for MMIO GIC accesses * remove superfluous isb instructions * more minor fixes Changes v2..v3 * fix clobbering of GICC address actually spoiling the stack * do CNTFRQ setup in assembly per core (and not only once per SoC) * moving the new code files into arch/arm/cpu/armv7 * add config variable for doing non-secure switch only * use actual HYP and secure instructions mnemonics instead of the encoded byte sequence. This requires more recent compilers. * make the identification of the CPU core more robust and saner * use enum for error codes and rename them * lots of smaller layout and style fixes Changes v3..v4 * mask reserved bits in CBAR register * move the VExpress board specific SMP code into the board directory * embed error reporting in the respective functions and getting rid of the error code enum at all (by popular demand ;-) * minor style fixes Please review and comment! Only had those very few nits sent separately, which can be fixed later if we want. Otherwise looks good. Reviewed-by: Christoffer Dall christoffer.d...@linaro.org Thanks, -Christoffer ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 4/8] ARM: add C function to switch to non-secure state
On Fri, Aug 09, 2013 at 05:03:08PM +0200, Andre Przywara wrote:
The core specific part of the work is done in the assembly routine
in nonsec_virt.S, introduced with the previous patch, but for the full
glory we need to setup the GIC distributor interface once for the
whole system, which is done in C here.
The routine is placed in arch/arm/cpu/armv7 to allow easy access from
other ARMv7 boards.
We check the availability of the security extensions first.
Since we need a safe way to access the GIC, we use the PERIPHBASE
registers on Cortex-A15 and A7 CPUs and do some sanity checks.
Boards not implementing the CBAR can override this value via a
configuration file variable.
Then we actually do the GIC enablement:
a) enable the GIC distributor, both for non-secure and secure state
(GICD_CTLR[1:0] = 11b)
b) allow all interrupts to be handled from non-secure state
(GICD_IGROUPRn = 0x)
The core specific GIC setup is then done in the assembly routine.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/cpu/armv7/Makefile | 1 +
arch/arm/cpu/armv7/virt-v7.c | 121
+++
arch/arm/include/asm/armv7.h | 3 ++
3 files changed, 125 insertions(+)
create mode 100644 arch/arm/cpu/armv7/virt-v7.c
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 11a8ad5..5813e87 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -38,6 +38,7 @@ endif
ifneq ($(CONFIG_ARMV7_NONSEC),)
SOBJS+= nonsec_virt.o
+COBJS+= virt-v7.o
endif
SRCS := $(START:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
new file mode 100644
index 000..689023f
--- /dev/null
+++ b/arch/arm/cpu/armv7/virt-v7.c
@@ -0,0 +1,121 @@
+/*
+ * (C) Copyright 2013
+ * Andre Przywara, Linaro
+ *
+ * Routines to transition ARMv7 processors from secure into non-secure state
+ * needed to enable ARMv7 virtualization for current hypervisors
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/armv7.h
+#include asm/gic.h
+#include asm/io.h
+
+unsigned long gic_dist_addr;
+
+static unsigned int read_id_pfr1(void)
+{
+ unsigned int reg;
+
+ asm(mrc p15, 0, %0, c0, c1, 1\n : =r(reg));
+ return reg;
+}
+
+static unsigned long get_gicd_base_address(void)
+{
+#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
+ return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET;
+#else
+ unsigned midr;
+ unsigned periphbase;
+
+ /* check whether we are an Cortex-A15 or A7.
+ * The actual HYP switch should work with all CPUs supporting
+ * the virtualization extension, but we need the GIC address,
+ * which we know only for sure for those two CPUs.
+ */
+ asm(mrc p15, 0, %0, c0, c0, 0\n : =r(midr));
+ switch (midr MIDR_PRIMARY_PART_MASK) {
+ case MIDR_CORTEX_A9_R0P1:
+ case MIDR_CORTEX_A15_R0P0:
+ case MIDR_CORTEX_A7_R0P0:
+ break;
+ default:
+ printf(nonsec: could not determine GIC address.\n);
+ return -1;
+ }
+
+ /* get the GIC base address from the CBAR register */
+ asm(mrc p15, 4, %0, c15, c0, 0\n : =r (periphbase));
+
+ /* the PERIPHBASE can be mapped above 4 GB (lower 8 bits used to
+ * encode this). Bail out here since we cannot access this without
+ * enabling paging.
+ */
+ if ((periphbase 0xff) != 0) {
+ printf(nonsec: PERIPHBASE is above 4 GB, no access.\n);
+ return -1;
+ }
+
+ return (periphbase CBAR_MASK) + GIC_DIST_OFFSET;
+#endif
+}
+
+int armv7_switch_nonsec(void)
+{
+ unsigned int reg;
+ unsigned itlinesnr, i;
+
+ /* check whether the CPU supports the security extensions */
+ reg = read_id_pfr1();
+ if ((reg 0xF0) == 0) {
+ printf(nonsec: Security extensions not implemented.\n);
+ return -1;
+ }
+
+ /* the SCR register will be set directly in the monitor mode handler,
+ * according to the spec one should not tinker with it in secure state
+
[U-Boot] [PATCH] configs: Remove unused CONFIG_BOOTP_DEFAULT
Signed-off-by: Tom Rini tr...@ti.com --- include/configs/calimain.h |1 - include/configs/cam_enc_4xx.h |1 - include/configs/da830evm.h |1 - include/configs/da850evm.h |1 - include/configs/davinci_dm365evm.h |1 - include/configs/davinci_dm6467evm.h |1 - include/configs/davinci_dvevm.h |1 - include/configs/davinci_schmoogie.h |1 - include/configs/davinci_sffsdr.h|1 - include/configs/davinci_sonata.h|1 - include/configs/ea20.h |1 - include/configs/enbw_cmc.h |1 - include/configs/hawkboard.h |1 - include/configs/igep0033.h |1 - include/configs/mcx.h |1 - include/configs/pcm051.h|1 - include/configs/tam3517-common.h|1 - include/configs/ti814x_evm.h|1 - 18 files changed, 18 deletions(-) diff --git a/include/configs/calimain.h b/include/configs/calimain.h index c76bc2c..d20074c 100644 --- a/include/configs/calimain.h +++ b/include/configs/calimain.h @@ -185,7 +185,6 @@ #ifdef CONFIG_DRIVER_TI_EMAC #define CONFIG_EMAC_MDIO_PHY_NUM 1 #define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h index 0f3f61a..ac7ed81 100644 --- a/include/configs/cam_enc_4xx.h +++ b/include/configs/cam_enc_4xx.h @@ -49,7 +49,6 @@ #define CONFIG_EMAC_MDIO_PHY_NUM 0 #defineCONFIG_SYS_EMAC_TI_CLKDIV 0xa9/* 1MHz */ #define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h index 9407eaf..3e71ae5 100644 --- a/include/configs/da830evm.h +++ b/include/configs/da830evm.h @@ -74,7 +74,6 @@ */ #ifdef CONFIG_DRIVER_TI_EMAC #define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 3c0aacd..e63d7c4 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -227,7 +227,6 @@ */ #ifdef CONFIG_DRIVER_TI_EMAC #define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h index e3084d3..82dc1a2 100644 --- a/include/configs/davinci_dm365evm.h +++ b/include/configs/davinci_dm365evm.h @@ -44,7 +44,6 @@ /* Network Configuration */ #define CONFIG_DRIVER_TI_EMAC #define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h index 3c430ae..7f57877 100644 --- a/include/configs/davinci_dm6467evm.h +++ b/include/configs/davinci_dm6467evm.h @@ -69,7 +69,6 @@ extern unsigned int davinci_arm_clk_get(void); /* Network Ethernet Configuration */ #define CONFIG_DRIVER_TI_EMAC #define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index 6526478..a49a989 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -87,7 +87,6 @@ /*==*/ #define CONFIG_DRIVER_TI_EMAC #define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h index 29b10dd..1595bc7 100644 --- a/include/configs/davinci_schmoogie.h +++ b/include/configs/davinci_schmoogie.h @@ -56,7 +56,6 @@ /*==*/ #define CONFIG_DRIVER_TI_EMAC #define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h index 34a64b3..6ebbe81 100644 --- a/include/configs/davinci_sffsdr.h +++ b/include/configs/davinci_sffsdr.h @@ -50,7 +50,6 @@ /* Network Ethernet Configuration */ #define CONFIG_DRIVER_TI_EMAC #define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h index d35aea7..3eaa7c0 100644 --- a/include/configs/davinci_sonata.h +++ b/include/configs/davinci_sonata.h @@ -88,7 +88,6 @@ /*==*/ #define CONFIG_DRIVER_TI_EMAC #define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2
[U-Boot] [PATCH] galaxy5200: Convert from unused CONFIG_BOOTP_MASK to specific list
Signed-off-by: Tom Rini tr...@ti.com --- include/configs/galaxy5200.h |7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h index 984f274..47e65d8 100644 --- a/include/configs/galaxy5200.h +++ b/include/configs/galaxy5200.h @@ -360,10 +360,9 @@ #define CONFIG_CRC32_VERIFY 1 -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ -CONFIG_BOOTP_DNS | \ -CONFIG_BOOTP_DNS2 | \ -CONFIG_BOOTP_SEND_HOSTNAME ) +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_VERSION_VARIABLE 1 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] U-Boot mini-summit at ELCE 2013 in Edinburgh - call for participation!
On Fri, Aug 9, 2013 at 10:08 AM, Tom Rini tr...@ti.com wrote: On Thu, Aug 08, 2013 at 11:24:58AM +0200, Wolfgang Denk wrote: I think we should bring the upcoming U-Boot mini-summit in Edinburgh back to attention - it's still more than two months, so no reason to panic yet, but as we all know, time flies like an arrow... ... I'll be giving a presentation called Redundant booting with U-Boot (or: Welcome to the redundancy theatre playhouse) that will cover the redundancy features we've had practically for forever (but are now enabled more often in stock configs) as well as some ideas I've had kicking around my head for a while and now have to go and implement. I wish I could go :-( arrg! -- Otavio Salvador O.S. Systems http://www.ossystems.com.brhttp://projetos.ossystems.com.br Mobile: +55 (53) 9981-7854Mobile: +1 (347) 903-9750 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v7 02/11] video: add Faraday FTLCDC200 LCD controller support
On Mon, 29 Jul 2013 13:51:44 +0800 Kuo-Jung Su dant...@gmail.com wrote: From: Kuo-Jung Su dant...@faraday-tech.com Faraday FTLCDC200 Color LCD controller performs translation of pixel-coded data into the required formats and timings to drive a variety of single/dual mono and color LCDs. Depending on the LCD type and mode, the unpacked data can represent: 1. an actual true display gray or color value 2. an address to a 256 x 16 bit wide palette RAM gray or color value. The FTLCDC200 generates 4 individual interrupts for: 1. DMA FIFO underflow 2. base address update 3. vertical status 4. bus error. There is also a single combined interrupt that is raised when any of the individual interrupts become active. Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com CC: Albert Aribaud albert.u.b...@aribaud.net CC: Anatolij Gustschin ag...@denx.de --- Changes for v7: - Update license to use SPDX identifiers. Changes for v6: - Nothing updates Changes for v5: - Coding Style cleanup: struct chip_regs __iomem *regs - struct chip_regs *regs - Chain it back to Faraday A360/A369 patch series, because Faraday A369 depends on the header file of this patch for I2C work-around.(Enable I2C clock to prevent I2C bus hangs) Changes for v4: - Nothing updates Changes for v3: - Nothing updates Changes for v2: - Make it a separate patch, rather then a part of Faraday A36x patch series drivers/video/Makefile |1 + drivers/video/ftlcdc200.c | 136 + drivers/video/ftlcdc200_panel.c | 209 +++ include/faraday/ftlcdc200.h | 178 + include/lcd.h | 33 +++ 5 files changed, 557 insertions(+) create mode 100644 drivers/video/ftlcdc200.c create mode 100644 drivers/video/ftlcdc200_panel.c create mode 100644 include/faraday/ftlcdc200.h Acked-by: Anatolij Gustschin ag...@denx.de Thanks, Anatolij ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 02/11] video: Allocate the MXSFB framebuffer aligned
On Tue, 30 Jul 2013 23:37:52 +0200 Marek Vasut ma...@denx.de wrote: Allocate the framebuffer aligned so it can be flushed and the flush_dcache_range() function won't complain. Signed-off-by: Marek Vasut ma...@denx.de Cc: Anatolij Gustschin ag...@denx.de Cc: Fabio Estevam fabio.este...@freescale.com Cc: Otavio Salvador ota...@ossystems.com.br Cc: Stefano Babic sba...@denx.de --- drivers/video/mxsfb.c |3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) Applied to u-boot-video/master. Thanks! Anatolij ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 03/11] video: Add System-Mode configuration hook into mxsfb
On Tue, 30 Jul 2013 23:37:53 +0200 Marek Vasut ma...@denx.de wrote: Add hook that allow configuring SmartLCD attached the MXS LCDIF controller operating in System-Mode. This hook can be overriden by a platform-specific SmartLCD programming routine, which writes the SmartLCD specific values into it's registers. Also, this patch makes sure the SYNC signals are off for the SmartLCD case. Signed-off-by: Marek Vasut ma...@denx.de Cc: Anatolij Gustschin ag...@denx.de Cc: Fabio Estevam fabio.este...@freescale.com Cc: Otavio Salvador ota...@ossystems.com.br Cc: Stefano Babic sba...@denx.de --- drivers/video/mxsfb.c | 16 1 file changed, 16 insertions(+) Applied to u-boot-video/master. Thanks! Anatolij ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 01/11] dma: apbh: Add special circular mode for LCD
On Tue, 30 Jul 2013 23:37:51 +0200 Marek Vasut ma...@denx.de wrote: Add special function that executes a specially crafted circular DMA descriptor. The function doesn't wait for the descriptor to finish the transfer, since the descritor never finishes. This is useful when operating a SmartLCD through the LCDIF interface, as the LCDIF does not give us any means to have continuous refresh of the SmartLCD. Instead, the RUN bit in the LCDIF CTRL register must be triggered manually. This can be worked around by starting an DMA transfer which continuously sets the RUN bit. This function allows starting exactly such transfer. Signed-off-by: Marek Vasut ma...@denx.de Cc: Anatolij Gustschin ag...@denx.de Cc: Fabio Estevam fabio.este...@freescale.com Cc: Otavio Salvador ota...@ossystems.com.br Cc: Stefano Babic sba...@denx.de --- arch/arm/include/asm/imx-common/dma.h |2 ++ drivers/dma/apbh_dma.c| 22 ++ 2 files changed, 24 insertions(+) Applied to u-boot-video/master. Thanks! Anatolij ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 04/11] video: Implement continuous screen refresh for SmartLCD into mxsfb
On Tue, 30 Jul 2013 23:37:54 +0200 Marek Vasut ma...@denx.de wrote: The LCDIF interface doesn't give us any means to do continuous refresh when driving a SmartLCD. To work this around, we produce a special circular DMA descriptor, which only writes the HW_LCDIF_CTRL0 register and sets the RUN bit. Signed-off-by: Marek Vasut ma...@denx.de Cc: Anatolij Gustschin ag...@denx.de Cc: Fabio Estevam fabio.este...@freescale.com Cc: Otavio Salvador ota...@ossystems.com.br Cc: Stefano Babic sba...@denx.de --- drivers/video/mxsfb.c | 26 ++ 1 file changed, 26 insertions(+) Applied to u-boot-video/master. Thanks! Anatolij ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/1] linkstation_HGLAN: Convert from unused CONFIG_BOOTP_MASK to specific list
Signed-off-by: Tom Rini tr...@ti.com --- include/configs/linkstation.h | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/include/configs/linkstation.h b/include/configs/linkstation.h index 2ec7761..932dac3 100644 --- a/include/configs/linkstation.h +++ b/include/configs/linkstation.h @@ -95,7 +95,17 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_EXT2 -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_NISDOMAIN +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_NTPSERVER +#define CONFIG_BOOTP_TIMEOFFSET #define CONFIG_OF_LIBFDT 1 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Some custodian changes
On Thu, Aug 8, 2013 at 10:39 AM, Tom Rini tr...@ti.com wrote: Hey all, I want to announce a few custodian changes. Andy Fleming is stepping down from both his PowerPC and MMC custodianships to go off and do something non-technical and fun for a while. I want to thank him for all his time and wish him the best! Taking over for Andy for mpc85xx and mpc86xx will be York Sun, and taking over for MMC will be Pantelis Antoniou. Welcome aboard guys! Thank you, York and Pantelis, for stepping in. I really enjoy being part of this community, so I plan to lurk around for the foreseeable future. :) Thanks! Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] U-Boot mini-summit at ELCE 2013 in Edinburgh - call for participation!
Hi Il giorno 09/ago/2013 20:58, Otavio Salvador ota...@ossystems.com.br ha scritto: On Fri, Aug 9, 2013 at 10:08 AM, Tom Rini tr...@ti.com wrote: On Thu, Aug 08, 2013 at 11:24:58AM +0200, Wolfgang Denk wrote: I think we should bring the upcoming U-Boot mini-summit in Edinburgh back to attention - it's still more than two months, so no reason to panic yet, but as we all know, time flies like an arrow... ... I'll be giving a presentation called Redundant booting with U-Boot (or: Welcome to the redundancy theatre playhouse) that will cover the redundancy features we've had practically for forever (but are now enabled more often in stock configs) as well as some ideas I've had kicking around my head for a while and now have to go and implement. I wish I could go :-( arrg! Edinburgh is a nice city. I will be there with my tribe :D. Marek will be happy. Michael -- Otavio Salvador O.S. Systems http://www.ossystems.com.brhttp://projetos.ossystems.com.br Mobile: +55 (53) 9981-7854Mobile: +1 (347) 903-9750 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] 83xx/pcie: fix build error for 83xx pcie
From: Roy Zang tie-fei.z...@freescale.com Fix the following build error caused by patch powerpc/pcie: add PCIe version 3.x support: pcie.c:302:34: error: 'PCI_LTSSM' undeclared (first use in this function) pcie.c:303:15: error: 'PCI_LTSSM_L0' undeclared (first use in this function) Signed-off-by: Roy Zang tie-fei.z...@freescale.com --- This patch will be needed if this one is applied http://patchwork.ozlabs.org/patch/256684/ arch/powerpc/cpu/mpc83xx/pcie.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c index 09970b0..28c25e5 100644 --- a/arch/powerpc/cpu/mpc83xx/pcie.c +++ b/arch/powerpc/cpu/mpc83xx/pcie.c @@ -299,6 +299,8 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg) printf(PCIE%d: , bus); +#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ +#define PCI_LTSSM_L0 0x16 /* L0 state */ reg16 = in_le16(hose_cfg_base + PCI_LTSSM); if (reg16 = PCI_LTSSM_L0) printf(link\n); -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Unified u-boot feature set for simpler distro support
On 08/03/2013 01:11 AM, Dennis Gilmore wrote: Hi all, I wanted to start a discussion on defining a unified feature set that makes it simpler for the different distros to support ARM systems using u-boot. I have based a lot of my thoughts on how calxeda ship their systems configured as it works fairly well, recently i sent in a patch implementing most of what I would like to see for the wandboard[1] There's also the possibility of chain-loading e.g. Grub from U-Boot, which I think would satisfy at least some of your desires, although there would still be a need for U-Boot's bootcmd to know to modified to be able to load Grub, and also enable e.g. CONFIG_API, so still needs some U-Boot work. https://wiki.linaro.org/LEG/Engineering/Kernel/GRUBonUBOOT I got it working pretty easily on one Tegra board... An advantage would be familiar config file format and UI. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Unified u-boot feature set for simpler distro support
Dear Stephen Warren, In message 52056b16.7050...@wwwdotorg.org you wrote: There's also the possibility of chain-loading e.g. Grub from U-Boot, which I think would satisfy at least some of your desires, although there would still be a need for U-Boot's bootcmd to know to modified to be able to load Grub, and also enable e.g. CONFIG_API, so still needs some U-Boot work. It appears boot time and increased complexity are no concern to you? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de In the realm of scientific observation, luck is granted only to those who are prepared. - Louis Pasteur ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Unified u-boot feature set for simpler distro support
On 08/09/2013 04:49 PM, Wolfgang Denk wrote: Dear Stephen Warren, In message 52056b16.7050...@wwwdotorg.org you wrote: There's also the possibility of chain-loading e.g. Grub from U-Boot, which I think would satisfy at least some of your desires, although there would still be a need for U-Boot's bootcmd to know to modified to be able to load Grub, and also enable e.g. CONFIG_API, so still needs some U-Boot work. It appears boot time and increased complexity are no concern to you? I don't think this is any different than a BIOS booting grub on x86. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] RFC: tegra: Avoid using I2C prior to relocation
On 08/07/2013 10:20 AM, Stephen Warren wrote: On 08/06/2013 11:52 PM, Simon Glass wrote: Tegra recently moved to the new I2C framework, which sets up I2C prior to relocation, and prior to calling i2c_init_board(). This causes a crash on Tegra boards. note: There are many ways to fix this. I believe this is one. It disables i2c_init() until relocation is complete. I have been unable to test it so far due to problems getting my Seaboard to work. I will try another Tegra board, but send this for comment in the meantime. Tested-by: Stephen Warren swar...@nvidia.com (On Beaver and Dalmore, tested booting to U-Boot command prompt followed by i2c dev 0; i2c probe) Note: I believe this is an enormous hack that hacks around the problem of dynamic device initialization just not being well thought out relative to the restrictions of U-Boot's various boot stages. I'd still prefer an outright revert of the broken code. In other words, tegra_i2c_init() simply shouldn't be called at the wrong time; it shouldn't have to handle being called at the wrong time and null itself out when that happens. However, if this is what it takes to get U-Boot working again, then let's apply it ASAP. This doesn't seem to have been applied yet. Are you expecting this to go through the main U-boot Tree, I2C tree, or Tegra tree? I just noticed that you only CC'd the Tegra maintainer... ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/7 v10] NAND: TPL : introduce the TPL based on the SPL
On Thu, 2013-07-25 at 15:44 +0800, ying.zh...@freescale.com wrote: This patch is on top of the patch: SPL: Makefile: Build a separate autoconf.mk for SPL Could you fix the reported build problem with that patch and submit it? -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 0/5] ARM: at91: atmel_nand: check ONFI ecc minimum requirement
On Fri, 2013-08-09 at 18:00 +0800, Josh Wu wrote: Hi, Any feedback for those patch series? Best Regards, Josh Wu Acked-by: Scott Wood scottw...@freescale.com -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 1/4] mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform
On Tue, 2013-08-06 at 15:25 +0530, Pekon Gupta wrote: BCH8_ECC scheme implemented in omap_gpmc.c driver has following two favours +---+-+-+ |ECC Scheme | ECC Calculation | Error Detection | +---+-+-+ |OMAP_ECC_BCH8_CODE_HW |GPMC |ELM H/W engine | |OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |GPMC |S/W BCH library | +---+-+-+ Current implementation enables of BCH8_CODE_HW only for AM33xx SoC family. (using CONFIG_AM33XX). However, other SoC families (like TI81xx) also have ELM hardware module, and can support ECC error detection using ELM. This patch - replaces CONFIG_AM33xx define with generic CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW so that all device families having required h/w capability can use ELM for error detection in ECC_BCHx schemes. - replaces CONFIG_NAND_OMAP_BCH8 with CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW_DETECTION_SW and separates out code for above mentioned BCH8_ECC implementations so that driver can be build independently using anyone of them. Please document these CONFIG symbols in the README. Is the choice of ECC mode dictated by the hardware, or is it software's choice? If the former, it should be CONFIG_SYS rather than just CONFIG. Signed-off-by: Pekon Gupta pe...@ti.com --- drivers/mtd/nand/omap_gpmc.c | 117 +++ include/configs/am335x_evm.h | 1 + include/configs/ti814x_evm.h | 2 +- include/configs/tricorder.h | 2 +- 4 files changed, 65 insertions(+), 57 deletions(-) diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index ec1787f..c6c5cec 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -12,11 +12,12 @@ #include asm/arch/cpu.h #include asm/omap_gpmc.h #include linux/mtd/nand_ecc.h -#include linux/bch.h #include linux/compiler.h #include nand.h -#ifdef CONFIG_AM33XX +#if defined(CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW) #include asm/arch/elm.h +#elif defined(CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW_DETECTION_SW) +#include linux/bch.h #endif Normally includes don't get ifdeffed... and what is the connection between a particular ECC mode and asm/arch/elm.h? -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] RFC: tegra: Avoid using I2C prior to relocation
+Tom Rini Hi Stephen, On Fri, Aug 9, 2013 at 5:17 PM, Stephen Warren swar...@wwwdotorg.orgwrote: On 08/07/2013 10:20 AM, Stephen Warren wrote: On 08/06/2013 11:52 PM, Simon Glass wrote: Tegra recently moved to the new I2C framework, which sets up I2C prior to relocation, and prior to calling i2c_init_board(). This causes a crash on Tegra boards. note: There are many ways to fix this. I believe this is one. It disables i2c_init() until relocation is complete. I have been unable to test it so far due to problems getting my Seaboard to work. I will try another Tegra board, but send this for comment in the meantime. Tested-by: Stephen Warren swar...@nvidia.com (On Beaver and Dalmore, tested booting to U-Boot command prompt followed by i2c dev 0; i2c probe) Note: I believe this is an enormous hack that hacks around the problem of dynamic device initialization just not being well thought out relative to the restrictions of U-Boot's various boot stages. I'd still prefer an outright revert of the broken code. In other words, tegra_i2c_init() simply shouldn't be called at the wrong time; it shouldn't have to handle being called at the wrong time and null itself out when that happens. However, if this is what it takes to get U-Boot working again, then let's apply it ASAP. This doesn't seem to have been applied yet. Are you expecting this to go through the main U-boot Tree, I2C tree, or Tegra tree? I just noticed that you only CC'd the Tegra maintainer... I put tegra: on the front expecting it to go that way, but it doesn't matter. Also your comments did not exactly represent a glowing recommendation. Tom (Rini) are you willing to pick this up as a bug fix please? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Unified u-boot feature set for simpler distro support
On 08/09/2013 05:00 PM, Stephen Warren wrote: On 08/09/2013 04:49 PM, Wolfgang Denk wrote: Dear Stephen Warren, In message 52056b16.7050...@wwwdotorg.org you wrote: There's also the possibility of chain-loading e.g. Grub from U-Boot, which I think would satisfy at least some of your desires, although there would still be a need for U-Boot's bootcmd to know to modified to be able to load Grub, and also enable e.g. CONFIG_API, so still needs some U-Boot work. It appears boot time and increased complexity are no concern to you? I don't think this is any different than a BIOS booting grub on x86. I suppose one way of addressing this might be for U-Boot to support grub.cfg; either by integrating some code from the Grub project or a re-implementation. This ends up pretty similar to Dennis' original suggestion, but with the advantage that that config file format is something already widely generated by distros. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
