Re: [U-Boot] [PATCH v3 4/4] cmd_eeprom: bug fix for i2c read/write

[Alexey Brodkin]

On Tue, 2013-12-03 at 08:55 +0800, Kuo-Jung Su wrote:
> The comment bellow clearly explain the issue here.
> 
> soft_i2c.c: line 351 ~ 367:
> 
> #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
> /*
>  * EEPROM chips that implement "address overflow" are ones
>  * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
>  * address and the extra bits end up in the "chip address"
>  * bit slots. This makes a 24WC08 (1Kbyte) chip look like
>  * four 256 byte chips.
>  *
>  * Note that we consider the length of the address field to
>  * still be one byte because the extra address bits are
>  * hidden in the chip address.
>  */
> chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
> 
> PRINTD("i2c_read: fix addr_overflow: chip %02X addr %02X\n",
> chip, addr);
> #endif

Indeed comment is pretty clear.
But IMHO this code is very generic (how is it bound to any specific
device driver?) and because of this I believe it should be in common I2C
sources but not in device-specific ones.

Otherwise do we need to copy-paste this snippet to all I2C drivers?

I do like the code above for modification of slave address ("chip") -
for me it looks very clear and CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW makes
perfect sense.

So why don't we try to push this in generic "eeprom_{read|write}"?

> Yes,the address/offset tricks are device specific (not only EEPROM, it
> also applies to Audio Codecs..etc.)

Saying "device specific" I meant not "I2C driver specific" but "attached
I2C slave specific".

As you correctly stated this kind of tricky addressing is used by
EEPROMs, audio codecs etc.

So when we need to work with EEPPROM with "ADDR_OVERFLOW" I expect to
enable CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW in configuration.

But imagine if the same I2C bus has another slave which expects "normal"
I2C addressing. So how then you're going to configure your I2C driver so
it correctly works with both slaves?

My vision of resolution is like this: I2C driver always work in "normal
addressing" mode - just uses "chip" and "address" values as they are,
but in higher level code like in ours "cmd_eeprom" we may modify both
"chip" and "offset" values for each particular type of attached I2C
device.

> But this code was there over a decade. And if everything works just
> fine, why bother ?

Well as it turned out not everything worked that fine. As I discovered
"dw_i2c" didn't work because of missing address re-calculation.

Indeed I may agree with your previous patch:
=
if (i2c_write(dev_addr, offset, alen - 1, buffer, len))
=
and implement address modification in "dw_i2c" driver.

But still there're questions:
1. Which other drivers will require update? and who's going to check/fix
it there?
2. Why do we need all this address modification part in "cmd_eeprom.c"?
And if we don't need - who's going to clean this up?

BTW what I cannot understand is why "soft_i2c_read" has this "chip"
modification part while "soft_i2c_write" doesn't? Is it done on purpose?
And how it actually works at all then?

Regards,
Alexey
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Re: [U-Boot] [v4 1/6] Driver/DDR: Moving Freescale DDR driver to a common driver

[york sun]

On Dec 2, 2013, at 10:49 PM, Masahiro Yamada wrote:

> Hello York.
> 
>>> And it also looks weird to me.
>>> 
>>> Why did you put this code in arch/powerpc/cpu/mpc83xx/Makefie,
>>> not drivers/ddr/fsl/Makefile ?
>>> 
>> 
>> I understand this looks weird. Most 83xx didn't use the same driver as 85xx 
>> SoCs do. Freescale DDR driver has two parts. One is the calculation. This 
>> can be shared by all families. The other, smaller, is the writing registers 
>> part. Each family has its own driver. You may have noticed one for 85xx, and 
>> one for 86xx. We could create one for 83xx. But till now, there is no other 
>> 83xx SoC uses it.
>> 
>> After this patch set, we have consolidated Freescale DDR drivers and header 
>> files into one set. It becomes more clear that we can and probably should 
>> merge this one as well. It's on my list to clean up, but this one has low 
>> priority.
>> 
>> Hope I explained it clearly.
> 
> OK.
> This refactoring is up to you.
> But, anyway, we can't use absolute paths for obj-y.
> 
> So, I posted a patch:
> http://patchwork.ozlabs.org/patch/296086/


Thanks for the patch. I am not against either way. I noticed the path for out 
of tree compiling and I didn't see which one is better. I found examples of 
both. I personally think using $(SRCTREE) is cleaner. Let's wait for others to 
chime in.

York

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Re: [U-Boot] [PATCH 0/4] Trats2 code cleanups

[Minkyu Kang]

On 27/11/13 19:10, Piotr Wilczek wrote:
> This patch series cleanups some code for Trats2.
> 
> Unused defines are removed.
> For envs, hardcoded names are replaced with variable names.
> In the board file, 'samsung_get_base' common functions are used.
> Tizen partions layout is updated.
> 
> This patch series is based on:
> http://patchwork.ozlabs.org/patch/290667/
> http://patchwork.ozlabs.org/patch/293163/
> http://patchwork.ozlabs.org/patch/293162/
> 
> Piotr Wilczek (4):
>   board: trats2: remove unused defines from config file
>   board:trats2: fix config
>   board:trats2: fix access to samsung registers
>   board:trats2: update Tizen partition definitions
> 
>  board/samsung/trats2/trats2.c |   16 
>  include/configs/trats2.h  |   28 +++-
>  2 files changed, 19 insertions(+), 25 deletions(-)
> 

applied to u-boot-samsung.

Thanks,
Minkyu Kang.
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Re: [U-Boot] [v4 1/6] Driver/DDR: Moving Freescale DDR driver to a common driver

[Masahiro Yamada]

Hello York.

> > And it also looks weird to me.
> > 
> > Why did you put this code in arch/powerpc/cpu/mpc83xx/Makefie,
> > not drivers/ddr/fsl/Makefile ?
> > 
> 
> I understand this looks weird. Most 83xx didn't use the same driver as 85xx 
> SoCs do. Freescale DDR driver has two parts. One is the calculation. This can 
> be shared by all families. The other, smaller, is the writing registers part. 
> Each family has its own driver. You may have noticed one for 85xx, and one 
> for 86xx. We could create one for 83xx. But till now, there is no other 83xx 
> SoC uses it.
> 
> After this patch set, we have consolidated Freescale DDR drivers and header 
> files into one set. It becomes more clear that we can and probably should 
> merge this one as well. It's on my list to clean up, but this one has low 
> priority.
> 
> Hope I explained it clearly.

OK.
This refactoring is up to you.
But, anyway, we can't use absolute paths for obj-y.

So, I posted a patch:
http://patchwork.ozlabs.org/patch/296086/


Best Regards
Masahiro Yamada

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[U-Boot] [PATCH] include/mmc.h: Remove declaration for spl_mmc_load()

[Lad, Prabhakar]

From: "Lad, Prabhakar" 

The spl_mmc_load() was removed while converting to
CONFIG_SPL_FRAMEWORK usage the definition was removed
but the declaration was missed. This patch removes this
declaration.

Signed-off-by: Lad, Prabhakar 
---
 include/mmc.h |1 -
 1 file changed, 1 deletion(-)

diff --git a/include/mmc.h b/include/mmc.h
index cb558da..8f51c93 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -304,7 +304,6 @@ int board_mmc_getcd(struct mmc *mmc);
 int mmc_switch_part(int dev_num, unsigned int part_num);
 int mmc_getcd(struct mmc *mmc);
 int mmc_getwp(struct mmc *mmc);
-void spl_mmc_load(void) __noreturn;
 /* Function to change the size of boot partition and rpmb partitions */
 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
unsigned long rpmbsize);
-- 
1.7.9.5

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[U-Boot] [PATCH] PowerPC: mpc83xx: Do not use absolute paths for obj-y

[Masahiro Yamada]

Signed-off-by: Masahiro Yamada 
---

Please make sure relative paths always should be used
when $(obj-y) points to objects under a different directory.

The absolute path like follows:
  obj-$(CONFIG_MPC8349) += $(SRCTREE)/drivers/ddr/fsl/mpc85xx_ddr_gen2.o
creates an object file under a strange path for out-of-tree build.

  $ rm -rf build/
  $ make O=build MPC8349EMDS_config
  Configuring for MPC8349EMDS board...
  $ make O=build CROSS_COMPILE=powerpc-linux-
  <>
  $ find . -name mpc85xx_ddr_gen2.o
  
./build/arch/powerpc/cpu/mpc83xx/home/yamada/workspace/u-boot/drivers/ddr/fsl/mpc85xx_ddr_gen2.o


 arch/powerpc/cpu/mpc83xx/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/cpu/mpc83xx/Makefile 
b/arch/powerpc/cpu/mpc83xx/Makefile
index c345dd6..d184c04 100644
--- a/arch/powerpc/cpu/mpc83xx/Makefile
+++ b/arch/powerpc/cpu/mpc83xx/Makefile
@@ -39,7 +39,7 @@ obj-$(CONFIG_OF_LIBFDT) += fdt.o
 obj-y += cache.o
 
 ifdef CONFIG_SYS_FSL_DDR2
-obj-$(CONFIG_MPC8349) += $(SRCTREE)/drivers/ddr/fsl/mpc85xx_ddr_gen2.o
+obj-$(CONFIG_MPC8349) += ../../../../drivers/ddr/fsl/mpc85xx_ddr_gen2.o
 else
 obj-y += spd_sdram.o
 endif
-- 
1.8.3.2

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Re: [U-Boot] [PATCH V3] exynos: spl: Add a custom spi copy function

[Minkyu Kang]

On 02/12/13 22:17, Rajeshwari Birje wrote:
> Hi Minkyu Kang,
> 
> Thank you for comments.
> 
> 
> 
> On Mon, Dec 2, 2013 at 2:18 PM, Minkyu Kang  wrote:
>> On 09/10/13 16:55, Rajeshwari Birje wrote:
>>> Hi Minkyu Kang,
>>>
>>> Since this patch is related to arch/arm spi booting, I had a doubt
>>> where would it get merged in u-boot-samsung.git or u-boot-spi.git.
>>>
>>> This patch is based on "[U-Boot] [PATCH 4/4] spi: exynos: Support word
>>> transfers" which is already merged in u-boot-spi.git.
>>
>> Now, that patch is merged to u-boot-samsung.
>> Anyway I'm OK to pick this patch to u-boot-spi.
>>
>>>
>>> Regards,
>>> Rajeshwari Shinde.
>>>
>>> On Tue, Oct 8, 2013 at 6:42 PM, Rajeshwari S Shinde
>>>  wrote:
 This patch implements a custom spi_copy funtion to copy u-boot from SF
 to RAM. This is faster then iROM spi_copy funtion as this runs spi at
 50Mhz and also in WORD mode of operation.

 Changed a printf in pinmux.c to debug just to avoid the compilation
 error in SPL.

 Signed-off-by: Alim Akhtar 
 Signed-off-by: Tom Wai-Hong Tam 
 Signed-off-by: Rajeshwari S Shinde 
 ---
 Based on following patch yet to be merged:
 "[U-Boot] [PATCH 4/4] spi: exynos: Support word transfers"
 Changes in V2:
 - Corrected the commit message.
 - Added a SPI timeout check.
 - Corrected the comments.
 Changes in V3:
 - Rebased on the latest u-boot-spi tree.
  arch/arm/cpu/armv7/exynos/pinmux.c |   2 +-
  arch/arm/cpu/armv7/exynos/spl_boot.c   | 122 
 -
  arch/arm/include/asm/arch-exynos/spi.h |   1 +
  include/configs/exynos5250-dt.h|   2 +
  4 files changed, 123 insertions(+), 4 deletions(-)

 diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c 
 b/arch/arm/cpu/armv7/exynos/pinmux.c
 index 8002bce..74cc700 100644
 --- a/arch/arm/cpu/armv7/exynos/pinmux.c
 +++ b/arch/arm/cpu/armv7/exynos/pinmux.c
 @@ -462,7 +462,7 @@ static int exynos4_pinmux_config(int peripheral, int 
 flags)
 case PERIPH_ID_SDMMC1:
 case PERIPH_ID_SDMMC3:
 case PERIPH_ID_SDMMC4:
 -   printf("SDMMC device %d not implemented\n", peripheral);
 +   debug("SDMMC device %d not implemented\n", peripheral);
>>
>> unrelated change.
>>
> As mentioned commit message
> "Changed a printf in pinmux.c to debug just to avoid the compilation
> error in SPL."
 return -1;
 default:
 debug("%s: invalid peripheral %d", __func__, peripheral);
 diff --git a/arch/arm/cpu/armv7/exynos/spl_boot.c 
 b/arch/arm/cpu/armv7/exynos/spl_boot.c
 index 3651c00..6faf13f 100644
 --- a/arch/arm/cpu/armv7/exynos/spl_boot.c
 +++ b/arch/arm/cpu/armv7/exynos/spl_boot.c
 @@ -10,8 +10,11 @@
  #include 
  #include 
  #include 
 +#include 
 +#include 
  #include 
  #include 
 +#include 

  #include "common_setup.h"
  #include "clock_init.h"
 @@ -59,6 +62,119 @@ static int config_branch_prediction(int set_cr_z)
  }
  #endif

 +static void spi_rx_tx(struct exynos_spi *regs, int todo,
 +   void *dinp, void const *doutp, int i)
 +{
 +   uint *rxp = (uint *)(dinp + (i * (32 * 1024)));
 +   int rx_lvl, tx_lvl;
 +   uint out_bytes, in_bytes;
 +
 +   out_bytes = todo;
 +   in_bytes = todo;
 +   setbits_le32(®s->ch_cfg, SPI_CH_RST);
 +   clrbits_le32(®s->ch_cfg, SPI_CH_RST);
 +   writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
 +
 +   while (in_bytes) {
 +   uint32_t spi_sts;
 +   int temp;
 +
 +   spi_sts = readl(®s->spi_sts);
 +   rx_lvl = ((spi_sts >> 15) & 0x7f);
 +   tx_lvl = ((spi_sts >> 6) & 0x7f);
 +   while (tx_lvl < 32 && out_bytes) {
 +   temp = 0x;
 +   writel(temp, ®s->tx_data);
 +   out_bytes -= 4;
 +   tx_lvl += 4;
 +   }
 +   while (rx_lvl >= 4 && in_bytes) {
 +   temp = readl(®s->rx_data);
 +   if (rxp)
 +   *rxp++ = temp;
 +   in_bytes -= 4;
 +   rx_lvl -= 4;
 +   }
 +   }
 +}
 +
 +/*
 + * Copy uboot from spi flash to RAM
 + *
 + * @parma uboot_size   size of u-boot to copy
 + * @param uboot_addr   address in u-boot to copy
 + */
 +static void exynos_spi_copy(unsigned int uboot_size, unsigned int 
 uboot_addr)
 +{
 +   int upto, todo;
 +   int i, timeout = 100;
 +   struct exynos_spi *regs = (struct exynos_spi *

Re: [U-Boot] [PATCH 3/9 V9] Exynos5420: Add clock initialization for 5420

[Minkyu Kang]

Dear Rajeshwari S Shinde,

On 02/12/13 20:47, Rajeshwari S Shinde wrote:
> This patch adds code for clock initialization and clock settings
> of various IP's and controllers, required for Exynos5420
> 
> Signed-off-by: Rajeshwari S Shinde 
> Signed-off-by: Akshay Saraswat 
> Acked-by: Simon Glass 
> ---
> Changes in V2:
>   - None
> Changes in V3:
>   - None
> Changes in V4:
>   - Corrected the multiline commenting style
> Changes in V5:
>   - None
> Changes in V6:
>   - None
> Changes in V7:
>   - Correct the logic for exynos5420_set_spi_clk api.
> Changes in V8:
>   - Chnages the if condition loop for pro_id and cpu_id.
> Changes in V9:
>   - Used samsung_get_base to get base address of clock.
>  arch/arm/cpu/armv7/exynos/clock.c  | 258 -
>  arch/arm/cpu/armv7/exynos/clock_init.h |  17 +
>  arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 352 +++-
>  arch/arm/cpu/armv7/exynos/exynos5_setup.h  | 738 
> +++--
>  arch/arm/include/asm/arch-exynos/clk.h |   1 +
>  arch/arm/include/asm/arch-exynos/clock.h   | 494 +
>  6 files changed, 1659 insertions(+), 201 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c 
> b/arch/arm/cpu/armv7/exynos/clock.c
> index 36fedd6..f2f06ac 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -96,7 +96,7 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, 
> unsigned int k)
>  
>   freq = CONFIG_SYS_CLK_FREQ;
>  
> - if (pllreg == EPLL) {
> + if (pllreg == EPLL || pllreg == RPLL) {
>   k = k & 0x;
>   /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
>   fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 << s)));
> @@ -117,7 +117,7 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, 
> unsigned int k)
>   div = PLL_DIV_1024;
>   else if (proid_is_exynos4412())
>   div = PLL_DIV_65535;
> - else if (proid_is_exynos5250())
> + else if (proid_is_exynos5250() || proid_is_exynos5420())
>   div = PLL_DIV_65536;
>   else
>   return 0;
> @@ -362,6 +362,43 @@ unsigned long clock_get_periph_rate(int peripheral)
>   return 0;
>  }
>  
> +/* exynos5420: return pll clock frequency */
> +static unsigned long exynos5420_get_pll_clk(int pllreg)
> +{
> + struct exynos5420_clock *clk =
> + (struct exynos5420_clock *)samsung_get_base_clock();
> + unsigned long r, k = 0;
> +
> + switch (pllreg) {
> + case APLL:
> + r = readl(&clk->apll_con0);
> + break;
> + case MPLL:
> + r = readl(&clk->mpll_con0);
> + break;
> + case EPLL:
> + r = readl(&clk->epll_con0);
> + k = readl(&clk->epll_con1);
> + break;
> + case VPLL:
> + r = readl(&clk->vpll_con0);
> + k = readl(&clk->vpll_con1);
> + break;
> + case BPLL:
> + r = readl(&clk->bpll_con0);
> + break;
> + case RPLL:
> + r = readl(&clk->rpll_con0);
> + k = readl(&clk->rpll_con1);
> + break;
> + default:
> + printf("Unsupported PLL (%d)\n", pllreg);
> + return 0;
> + }
> +
> + return exynos_get_pll_clk(pllreg, r, k);
> +}
> +
>  /* exynos4: return ARM clock frequency */
>  static unsigned long exynos4_get_arm_clk(void)
>  {
> @@ -485,6 +522,27 @@ static unsigned long exynos4x12_get_pwm_clk(void)
>   return pclk;
>  }
>  
> +/* exynos5420: return pwm clock frequency */
> +static unsigned long exynos5420_get_pwm_clk(void)
> +{
> + struct exynos5420_clock *clk =
> + (struct exynos5420_clock *)samsung_get_base_clock();
> + unsigned long pclk, sclk;
> + unsigned int ratio;
> +
> + /*
> +  * CLK_DIV_PERIC3

peric0?

> +  * PWM_RATIO [3:0]

then, why you right shift to 28?

> +  */
> + ratio = readl(&clk->div_peric0);
> + ratio = (ratio >> 28) & 0xf;
> + sclk = get_pll_clk(MPLL);
> +
> + pclk = sclk / (ratio + 1);
> +
> + return pclk;
> +}
> +
>  /* exynos4: return uart clock frequency */
>  static unsigned long exynos4_get_uart_clk(int dev_index)
>  {
> @@ -624,6 +682,53 @@ static unsigned long exynos5_get_uart_clk(int dev_index)
>   return uclk;
>  }
>  
> +/* exynos5420: return uart clock frequency */
> +static unsigned long exynos5420_get_uart_clk(int dev_index)
> +{
> + struct exynos5420_clock *clk =
> + (struct exynos5420_clock *)samsung_get_base_clock();
> + unsigned long uclk, sclk;
> + unsigned int sel;
> + unsigned int ratio;
> +
> + /*
> +  * CLK_SRC_PERIC0
> +  * UART0_SEL [3:0]
> +  * UART1_SEL [7:4]
> +  * UART2_SEL [8:11]
> +  * UART3_SEL [12:15]
> +  * UART4_SEL [16:19]
> +  * UART5_

Re: [U-Boot] [PATCH 4/9 V9] Exynos5420: Add DDR3 initialization for 5420

[Minkyu Kang]

Dear Rajeshwari S Shinde,

On 02/12/13 20:47, Rajeshwari S Shinde wrote:
> This patch intends to add DDR3 initialization code for Exynos5420.
> 
> Signed-off-by: Rajeshwari S Shinde 
> Signed-off-by: Akshay Saraswat 
> Acked-by: Simon Glass 
> ---
> Changes in V2:
>   - Corrected a compilation issue for SMDK5250.
> Changes in V3:
>   - None
> Changes in V4:
>   - None
> Changes in V5:
>   - None
> Changes in V6:
>   - None
> Changes in V7:
>   - Fixed multi line comment.
> Changes in V8:
>   - None
> Changes in V9:
>   - Used samsung_get base to get the dmc base address
>  arch/arm/cpu/armv7/exynos/dmc_common.c|  10 +-
>  arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 425 
> +-
>  arch/arm/cpu/armv7/exynos/exynos5_setup.h |   2 +
>  arch/arm/include/asm/arch-exynos/cpu.h|   4 +
>  arch/arm/include/asm/arch-exynos/dmc.h| 123 ++---
>  arch/arm/include/asm/arch-exynos/power.h  |   6 +
>  6 files changed, 525 insertions(+), 45 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/exynos/dmc_common.c 
> b/arch/arm/cpu/armv7/exynos/dmc_common.c
> index 53cfe6e..9e432c2 100644
> --- a/arch/arm/cpu/armv7/exynos/dmc_common.c
> +++ b/arch/arm/cpu/armv7/exynos/dmc_common.c
> @@ -1,5 +1,5 @@
>  /*
> - * Mem setup common file for different types of DDR present on SMDK5250 
> boards.
> + * Mem setup common file for different types of DDR present on Exynos boards.
>   *
>   * Copyright (C) 2012 Samsung Electronics
>   *
> @@ -152,14 +152,6 @@ void dmc_config_prech(struct mem_timings *mem, struct 
> exynos5_dmc *dmc)
>   }
>  }
>  
> -void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc)
> -{
> - writel(mem->memconfig, &dmc->memconfig0);
> - writel(mem->memconfig, &dmc->memconfig1);
> - writel(DMC_MEMBASECONFIG0_VAL, &dmc->membaseconfig0);
> - writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1);
> -}
> -
>  void mem_ctrl_init(int reset)
>  {
>   struct spl_machine_param *param = spl_get_machine_params();
> diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c 
> b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
> index 5f5914e..aa46a43 100644
> --- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
> +++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
> @@ -1,5 +1,5 @@
>  /*
> - * DDR3 mem setup file for SMDK5250 board based on EXYNOS5
> + * DDR3 mem setup file for board based on EXYNOS5
>   *
>   * Copyright (C) 2012 Samsung Electronics
>   *
> @@ -11,12 +11,14 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include "common_setup.h"
>  #include "exynos5_setup.h"
>  #include "clock_init.h"
>  
> -#define RDLVL_COMPLETE_TIMEOUT   1
> +#define TIMEOUT  1
>  
> +#ifdef CONFIG_EXYNOS5250
>  static void reset_phy_ctrl(void)
>  {
>   struct exynos5_clock *clk =
> @@ -108,7 +110,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned 
> long mem_iv_size,
>  
>   /* Precharge Configuration */
>   writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
> -&dmc->prechconfig);
> +&dmc->prechconfig0);
>  
>   /* Power Down mode Configuration */
>   writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |
> @@ -174,7 +176,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned 
> long mem_iv_size,
>   writel(val, &phy1_ctrl->phy_con1);
>  
>   writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config);
> - i = RDLVL_COMPLETE_TIMEOUT;
> + i = TIMEOUT;
>   while ((readl(&dmc->phystatus) &
>   (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) !=
>   (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) {
> @@ -215,3 +217,418 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, 
> unsigned long mem_iv_size,
>   | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol);
>   return 0;
>  }
> +#endif
> +
> +#ifdef CONFIG_EXYNOS5420

we can avoid ifdef here.

int ddr3_mem_ctrl_init(...)
{
if (proid_is_exynos5250())
exynos5250_ddr3_mem_ctrl_init();
else
exynos5420_ddr3_mem_ctrl_init();
}

> +int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
> +int reset)
> +{
> + struct exynos5420_clock *clk =
> + (struct exynos5420_clock *)samsung_get_base_clock();
> + struct exynos5_power *power =
> + (struct exynos5_power *)samsung_get_base_power();
> + struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
> + struct exynos5_dmc *drex0, *drex1;
> + struct exynos5_tzasc *tzasc0, *tzasc1;
> + uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1;
> + int chip;
> + int i;
> +
> + phy0_ctrl = (struct exynos5_phy_control *)samsung_get_base_dmc_phy();
> + phy1_ctrl = (struct exynos5_phy_control *)(samsung_get_base_dmc_phy()
> + + DMC_OFFSET);
> + drex0 = (struct exynos5_dmc *)

Re: [U-Boot] [PATCH 1/9 V9] EXYNOS5: Create a common board file

[Minkyu Kang]

Dear Rajeshwari S Shinde,

On 02/12/13 20:47, Rajeshwari S Shinde wrote:
> Create a common board.c file for all functions which are common across
> all EXYNOS5 platforms.
> 
> exynos_init function is provided for platform specific code.
> 
> Signed-off-by: Rajeshwari S Shinde 
> ---
> Changes in V2:
>   - None
> Changes in V3:
>   - None
> Changes in V4:
>   - Added check for the compilation of MAX77686 pmic.
> Changes in V5:
>   - Moved board_eth_init and board_mmc_init in case of
>   device tree support
> Changes in V6:
>   - None.
> Changes in V7:
>   - None
> Changes in V8:
>   - None
> Changes in V9:
>   - Reabsed on latest code.
>  arch/arm/include/asm/arch-exynos/board.h |  17 ++
>  board/samsung/common/Makefile|   5 +
>  board/samsung/common/board.c | 405 
> +++
>  board/samsung/smdk5250/exynos5-dt.c  | 352 +--
>  board/samsung/smdk5250/smdk5250.c| 182 +-
>  include/configs/exynos5250-dt.h  |   2 +
>  6 files changed, 434 insertions(+), 529 deletions(-)
>  create mode 100644 arch/arm/include/asm/arch-exynos/board.h
>  create mode 100644 board/samsung/common/board.c
> 
> diff --git a/arch/arm/include/asm/arch-exynos/board.h 
> b/arch/arm/include/asm/arch-exynos/board.h
> new file mode 100644
> index 000..243fb12
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-exynos/board.h
> @@ -0,0 +1,17 @@
> +/*
> + * (C) Copyright 2013 Samsung Electronics
> + * Rajeshwari Shinde 
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#ifndef _EXYNOS_BOARD_H
> +#define _EXYNOS_BOARD_H
> +
> +/*
> + * Exynos baord specific changes for
> + * board_init
> + */
> +int exynos_init(void);
> +
> +#endif   /* EXYNOS_BOARD_H */
> diff --git a/board/samsung/common/Makefile b/board/samsung/common/Makefile
> index 501d974..efbf9ae 100644
> --- a/board/samsung/common/Makefile
> +++ b/board/samsung/common/Makefile
> @@ -8,3 +8,8 @@
>  obj-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o
>  obj-$(CONFIG_THOR_FUNCTION) += thor.o
>  obj-$(CONFIG_CMD_USB_MASS_STORAGE) += ums.o
> +
> +ifeq ($(CONFIG_SPL_BUILD),)

what means this ifeq?

> +COBJS-$(CONFIG_BOARD_COMMON) += board.o
> +endif
> +
> diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
> new file mode 100644
> index 000..9ebfc42
> --- /dev/null
> +++ b/board/samsung/common/board.c
> @@ -0,0 +1,405 @@
> +/*
> + * (C) Copyright 2013 SAMSUNG Electronics
> + * Rajeshwari Shinde 
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct local_info {
> + struct cros_ec_dev *cros_ec_dev;/* Pointer to cros_ec device */
> + int cros_ec_err;/* Error for cros_ec, 0 if ok */
> +};
> +
> +static struct local_info local;
> +
> +#if defined CONFIG_EXYNOS_TMU
> +/*
> + * Boot Time Thermal Analysis for SoC temperature threshold breach
> + */

It's a one line comment.

> +static void boot_temp_check(void)
> +{
> + int temp;
> +
> + switch (tmu_monitor(&temp)) {
> + case TMU_STATUS_NORMAL:
> + break;
> + /* Status TRIPPED ans WARNING means corresponding threshold breach */

please move this comment into TMU_STATUS_TRIPPED case.

> + case TMU_STATUS_TRIPPED:
> + puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
> + set_ps_hold_ctrl();
> + hang();
> + break;
> + case TMU_STATUS_WARNING:
> + puts("EXYNOS_TMU: WARNING! Temperature very high\n");
> + break;
> + /*
> +  * TMU_STATUS_INIT means something is wrong with temperature sensing
> +  * and TMU status was changed back from NORMAL to INIT.
> +  */

ditto.

> + case TMU_STATUS_INIT:

according to the comment for this state, "Unknown TMU state" message is wrong.

> + default:
> + debug("EXYNOS_TMU: Unknown TMU state\n");
> + }
> +}
> +#endif
> +
> +int board_init(void)
> +{
> + gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
> +#if defined CONFIG_EXYNOS_TMU
> + if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
> + debug("%s: Failed to init TMU\n", __func__);
> + return -1;
> + }
> + boot_temp_check();
> +#endif
> +
> +#ifdef CONFIG_EXYNOS_SPI
> + spi_init();
> +#endif
> + return exynos_init();
> +}
> +
> +int dram_init(void)
> +{
> + int i;
> + u32 addr;
> +
> + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
> + addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
> + gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
> + }
> + return 0;
> +}
> +
> +void dram_init_banksize(void)
> +{
> + int

Re: [U-Boot] [v4 1/6] Driver/DDR: Moving Freescale DDR driver to a common driver

[york sun]

On Dec 2, 2013, at 9:15 PM, Masahiro Yamada wrote:

> Hello York.
> 
>> --- a/arch/powerpc/cpu/mpc83xx/Makefile
>> +++ b/arch/powerpc/cpu/mpc83xx/Makefile
>> @@ -38,11 +38,11 @@ obj-$(CONFIG_OF_LIBFDT) += fdt.o
>> # Stub implementations of cache management functions for USB
>> obj-y += cache.o
>> 
>> -ifdef CONFIG_FSL_DDR2
>> -obj-$(CONFIG_MPC8349) += ../mpc85xx/ddr-gen2.o
>> +ifdef CONFIG_SYS_FSL_DDR2
>> +obj-$(CONFIG_MPC8349) += $(SRCTREE)/drivers/ddr/fsl/mpc85xx_ddr_gen2.o
> 
> This Makefile is NG.
> The object file, mpc85xx_ddr_gen2.o,  is created under a strange path.

It has been this way. I am not saying it is good. Explained below.
> 
> Just build with O=  and find out where this object is created.
> 
> $ rm -rf build/
> $ make O=build MPC8349EMDS_config
> Configuring for MPC8349EMDS board...
> $ make O=build CROSS_COMPILE=powerpc-linux-
> <>
> $ find . -name mpc85xx_ddr_gen2.o
> ./build/arch/powerpc/cpu/mpc83xx/home/yamada/workspace/u-boot/drivers/ddr/fsl/mpc85xx_ddr_gen2.o
> 
> 
> 
> And it also looks weird to me.
> 
> Why did you put this code in arch/powerpc/cpu/mpc83xx/Makefie,
> not drivers/ddr/fsl/Makefile ?
> 

I understand this looks weird. Most 83xx didn't use the same driver as 85xx 
SoCs do. Freescale DDR driver has two parts. One is the calculation. This can 
be shared by all families. The other, smaller, is the writing registers part. 
Each family has its own driver. You may have noticed one for 85xx, and one for 
86xx. We could create one for 83xx. But till now, there is no other 83xx SoC 
uses it.

After this patch set, we have consolidated Freescale DDR drivers and header 
files into one set. It becomes more clear that we can and probably should merge 
this one as well. It's on my list to clean up, but this one has low priority.

Hope I explained it clearly.

York

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Re: [U-Boot] [PATCH 2/2] Makefile: Select objects by CONFIG_ rather than $(ARCH) or $(CPU)

[Masahiro Yamada]

Hi Tom.

> --- a/arch/powerpc/cpu/mpc8xxx/Makefile
> +++ b/arch/powerpc/cpu/mpc8xxx/Makefile
> @@ -19,10 +19,8 @@ ifdef MINIMAL
>  obj-$(CONFIG_FSL_LAW) += law.o
>  
>  else
> -
> -ifneq ($(CPU),mpc83xx)
> -obj-y+= cpu.o
> -endif
> +obj-$(CONFIG_MPC85xx) += cpu.o
> +obj-$(CONFIG_MPC86xx) += cpu.o
>  
>  obj-$(CONFIG_OF_LIBFDT) += fdt.o
>  obj-$(CONFIG_FSL_IFC) += fsl_ifc.o


You might see a conflict
when applying this patch to the current u-boot/master.

Please git am  with "-C2" option
to avoid a conflict.


Best Regards
Masahiro Yamada

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Re: [U-Boot] why u-boot relocate it self to RAM from flash?

[Wolfgang Denk]

Dear tejas patel,

In message  
you wrote:
>
> I can not understand why u-boot relocate it self to RAM from flash? Why is
> it not executing from flash?
> Can anybody explain.

There is a ton of reasons.  One is that you cannot erase or program
the flash device and execute code from it at the same time, so we
would not be able to write a Linux kernel image - at least not without
special flash drivers that execute from RAM.  And we would not be able
to update the U-Boot image in flash. etc. etc.

In the end it is much easier to run from RAM.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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Re: [U-Boot] [PATCH 2/2] arm: exynos: remove the unused define.

[Alexey Brodkin]

On Tue, 2013-12-03 at 14:00 +0900, Jaehoon Chung wrote:

> These defines didn't use anywhere.
> 
> Signed-off-by: Jaehoon Chung 
> ---
>  arch/arm/include/asm/arch-exynos/dwmmc.h |4 
>  1 file changed, 4 deletions(-)

Acked-by: Alexey Brodkin 

Regards,
Alexey

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Re: [U-Boot] [v4 1/6] Driver/DDR: Moving Freescale DDR driver to a common driver

[Masahiro Yamada]

Hello York.

> --- a/arch/powerpc/cpu/mpc83xx/Makefile
> +++ b/arch/powerpc/cpu/mpc83xx/Makefile
> @@ -38,11 +38,11 @@ obj-$(CONFIG_OF_LIBFDT) += fdt.o
>  # Stub implementations of cache management functions for USB
>  obj-y += cache.o
>  
> -ifdef CONFIG_FSL_DDR2
> -obj-$(CONFIG_MPC8349) += ../mpc85xx/ddr-gen2.o
> +ifdef CONFIG_SYS_FSL_DDR2
> +obj-$(CONFIG_MPC8349) += $(SRCTREE)/drivers/ddr/fsl/mpc85xx_ddr_gen2.o

This Makefile is NG.
The object file, mpc85xx_ddr_gen2.o,  is created under a strange path.

Just build with O=  and find out where this object is created.

$ rm -rf build/
$ make O=build MPC8349EMDS_config
Configuring for MPC8349EMDS board...
$ make O=build CROSS_COMPILE=powerpc-linux-
<>
$ find . -name mpc85xx_ddr_gen2.o
./build/arch/powerpc/cpu/mpc83xx/home/yamada/workspace/u-boot/drivers/ddr/fsl/mpc85xx_ddr_gen2.o



And it also looks weird to me.

Why did you put this code in arch/powerpc/cpu/mpc83xx/Makefie,
not drivers/ddr/fsl/Makefile ?


Best Regards
Masahiro Yamada

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[U-Boot] [PATCH 1/2] arm: exynos/goni: fix the return type for s5p_mmc_init

[Jaehoon Chung]

The "int" type is right.

Signed-off-by: Jaehoon Chung 
---
 arch/arm/include/asm/arch-exynos/mmc.h  |2 +-
 arch/arm/include/asm/arch-s5pc1xx/mmc.h |2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-exynos/mmc.h 
b/arch/arm/include/asm/arch-exynos/mmc.h
index 98312d1..98d6530 100644
--- a/arch/arm/include/asm/arch-exynos/mmc.h
+++ b/arch/arm/include/asm/arch-exynos/mmc.h
@@ -55,7 +55,7 @@
 
 int s5p_sdhci_init(u32 regbase, int index, int bus_width);
 
-static inline unsigned int s5p_mmc_init(int index, int bus_width)
+static inline int s5p_mmc_init(int index, int bus_width)
 {
unsigned int base = samsung_get_base_mmc() +
(S5P_MMC_DEV_OFFSET * index);
diff --git a/arch/arm/include/asm/arch-s5pc1xx/mmc.h 
b/arch/arm/include/asm/arch-s5pc1xx/mmc.h
index 55ff10b..dd473c8 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/mmc.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/mmc.h
@@ -55,7 +55,7 @@
 
 int s5p_sdhci_init(u32 regbase, int index, int bus_width);
 
-static inline unsigned int s5p_mmc_init(int index, int bus_width)
+static inline int s5p_mmc_init(int index, int bus_width)
 {
unsigned int base = samsung_get_base_mmc() +
 (S5P_MMC_DEV_OFFSET * index);
-- 
1.7.9.5
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[U-Boot] [PATCH 1/2] arm: exynos/goni: fix the return type for s5p_mmc_init

[Jaehoon Chung]

The "int" type is right.

Signed-off-by: Jaehoon Chung 
---
 arch/arm/include/asm/arch-exynos/mmc.h  |2 +-
 arch/arm/include/asm/arch-s5pc1xx/mmc.h |2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-exynos/mmc.h 
b/arch/arm/include/asm/arch-exynos/mmc.h
index 98312d1..98d6530 100644
--- a/arch/arm/include/asm/arch-exynos/mmc.h
+++ b/arch/arm/include/asm/arch-exynos/mmc.h
@@ -55,7 +55,7 @@
 
 int s5p_sdhci_init(u32 regbase, int index, int bus_width);
 
-static inline unsigned int s5p_mmc_init(int index, int bus_width)
+static inline int s5p_mmc_init(int index, int bus_width)
 {
unsigned int base = samsung_get_base_mmc() +
(S5P_MMC_DEV_OFFSET * index);
diff --git a/arch/arm/include/asm/arch-s5pc1xx/mmc.h 
b/arch/arm/include/asm/arch-s5pc1xx/mmc.h
index 55ff10b..dd473c8 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/mmc.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/mmc.h
@@ -55,7 +55,7 @@
 
 int s5p_sdhci_init(u32 regbase, int index, int bus_width);
 
-static inline unsigned int s5p_mmc_init(int index, int bus_width)
+static inline int s5p_mmc_init(int index, int bus_width)
 {
unsigned int base = samsung_get_base_mmc() +
 (S5P_MMC_DEV_OFFSET * index);
-- 1.7.9.5 
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[U-Boot] [PATCH 2/2] arm: exynos: remove the unused define.

[Jaehoon Chung]

These defines didn't use anywhere.

Signed-off-by: Jaehoon Chung 
---
 arch/arm/include/asm/arch-exynos/dwmmc.h |4 
 1 file changed, 4 deletions(-)

diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h 
b/arch/arm/include/asm/arch-exynos/dwmmc.h
index d1c5d4f..09d739d 100644
--- a/arch/arm/include/asm/arch-exynos/dwmmc.h
+++ b/arch/arm/include/asm/arch-exynos/dwmmc.h
@@ -6,10 +6,6 @@
  */
 
 #define DWMCI_CLKSEL   0x09C
-#define DWMCI_SHIFT_0  0x0
-#define DWMCI_SHIFT_1  0x1
-#define DWMCI_SHIFT_2  0x2
-#define DWMCI_SHIFT_3  0x3
 #define DWMCI_SET_SAMPLE_CLK(x)(x)
 #define DWMCI_SET_DRV_CLK(x)   ((x) << 16)
 #define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
-- 
1.7.9.5
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Re: [U-Boot] why u-boot relocate it self to RAM from flash?

[tejas patel]

Thank you very much for explanation both graeme and FengHua.

I think i have got best answer from you Graeme from entire web.

Thanks
Tejas


On Tue, Dec 3, 2013 at 4:03 AM, Graeme Russ  wrote:

> Hi,
>
> On Tue, Dec 3, 2013 at 1:18 AM, FengHua  wrote:
>
>>
>> > Hi,
>> >
>> > I can not understand why u-boot relocate it self to RAM from flash? Why
>> is
>> > it not executing from flash?
>> > Can anybody explain.
>> >
>>
>> First, flash is slow.
>> Second, there are many data structures or variables which should be
>> writable.
>> So, we should copy u-boot to RAM and relocate it.
>>
>
> I'll expand a bit...
>
> In theory the writeable could be relocated into RAM, but this would
> require the relocation address to be hard-coded. Optimally, U-Boot places
> itself in a memory location to provide the maximum contiguous memory space
> to load the operating system kernel and supporting data (RAM disks, FDTs,
> etc).
>
> On most systems now, relocation is done by calculating the delta between
> the ROM address (TEXT_BASE) and the relocated address in RAM. The
> relocation code first copies the entire U-Boot image to RAM (apart from a
> few structures that are used only during the relocation calculation). It
> then scans the relocation entries (*.rel sections) to find where in the
> U-Boot executable all the references into the data sections. At each
> reference point in the executable, the relocation code modifies the
> reference by the relocation offset. None of this can happen if the U-Boot
> executable is in Flash.
>
> The other advantage of relocating U-Boot to RAM is that it makes it
> possible to flash a new U-Boot image from U-Boot. If you try to do this
> while U-Boot is running from flash, it will crash as you are overwriting
> the executable code while it's executing.
>
>  Regards,
>
> Graeme
>



-- 

Thanks and Regards
Tejas Patel
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Re: [U-Boot] [PATCH V2] arm: omap: i2c: don't zero cnt in i2c_write

[Lokesh Vutla]

Hi Lubomir,
On Monday 02 December 2013 09:17 PM, Lubomir Popov wrote:
> Hi Nikita,
> 
> On 28/11/13 18:04, Nikita Kiryanov wrote:
>> Writing zero into I2Ci.I2C_CNT register causes random I2C failures in OMAP3
>> based devices. This seems to be related to the following advisory which
>> apears in multiple erratas for OMAP3 SoCs (OMAP35xx, DM37xx), as well as
>> OMAP4430 TRM:
>>
>> Advisory:
>> I2C Module Does Not Allow 0-Byte Data Requests
>> Details:
>> When configured as the master, the I2C module does not allow 0-byte data
>> transfers. Note: Programming I2Ci.I2C_CNT[15:0]: DCOUNT = 0 will cause
>> undefined behavior.
>> Workaround(s):
>> No workaround. Do not use 0-byte data requests.
>>
>> The writes in question are unnecessary from a functional point of view.
>> Most of them are done after I/O has finished, and the only one that preceds
>> I/O (in i2c_probe()) is also unnecessary because a stop bit is sent before
>> actual data transmission takes place.
>>
>> Therefore, remove all writes that zero the cnt register.
>>
>> Cc: Heiko Schocher 
>> Cc: Thomas Petazzoni 
>> Cc: Tom Rini 
>> Cc: Lubomir Popov 
>> Cc: Enric Balletbo Serra 
>> Signed-off-by: Nikita Kiryanov 
>> ---
>> Changes in V2:   
>> Removed all instances of writew(0, &i2c_base->cnt) instead of just the
>> one in i2c_write (following a test of V1 by Thomas Petazzoni).
>>
>>
> Tested-by: Lubomir Popov 
> 
> In addition to the OMAP5430/32 tests performed last week, tested today
> on OMAP4 (4430/60/70) and on AM3359. Thus tests have covered OMAP4/5-
> compatible I2C IPs with revnb_lo=[0x000a to 0x000c] (revnb_hi is 0x5040
> for all those IPs).
May I know on top of which tree,tag you are trying this patch ?
I tried OMAP4 on top of v2014.01-rc1, but I am not able to boot. I applied this 
patch and still
not able to boot. There is a mail thread going on, on this topic.
So I just wanted to know that I am not missing very obvious. 

Thanks and regards,
Lokesh
> 

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Re: [U-Boot] [PATCH] drivers:power:exynos-tmu: add support for Exynos5260

[Minkyu Kang]

Dear Naveen Krishna Chatradhi,

On 26/11/13 20:56, Naveen Krishna Chatradhi wrote:
> This patch adds support for TMU on Exynos5260
> Register bit fields are little different from the previous
> versions.
> 
> Change-Id: Ibe835abe9cb255d2f8375c8e9e32d32cff19c093

please remove it.

> Signed-off-by: Naveen Krishna Chatradhi 
> ---
>  arch/arm/include/asm/arch-exynos/tmu.h |   11 +++
>  drivers/power/exynos-tmu.c |   25 +++--
>  2 files changed, 34 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-exynos/tmu.h 
> b/arch/arm/include/asm/arch-exynos/tmu.h
> index cad3569..19b8f62 100644
> --- a/arch/arm/include/asm/arch-exynos/tmu.h
> +++ b/arch/arm/include/asm/arch-exynos/tmu.h
> @@ -26,7 +26,11 @@ struct exynos5_tmu_reg {
>   u32 triminfo_control;
>   u32 rsvd5[2];
>   u32 tmu_control;
> +#ifdef CONFIG_EXYNOS5260
> + u32 tmu_control1;
> +#else
>   u32 rsvd7;
> +#endif
>   u32 tmu_status;
>   u32 sampling_internal;
>   u32 counter_value0;
> @@ -41,10 +45,17 @@ struct exynos5_tmu_reg {
>   u32 past_temp7_4;
>   u32 past_temp11_8;
>   u32 past_temp15_12;
> +#ifdef CONFIG_EXYNOS5260
> + u32 rsvd15[16];
> +#endif
>   u32 inten;
>   u32 intstat;
>   u32 intclear;
> +#ifdef CONFIG_EXYNOS5260
> + u32 rsvd31[17];
> +#else
>   u32 rsvd15;
> +#endif
>   u32 emul_con;
>  };
>  #endif /* __ASM_ARCH_TMU_H */
> diff --git a/drivers/power/exynos-tmu.c b/drivers/power/exynos-tmu.c
> index 9a093a5..de3ff82 100644
> --- a/drivers/power/exynos-tmu.c
> +++ b/drivers/power/exynos-tmu.c
> @@ -31,7 +31,13 @@
>  #define INTEN_RISE0  1
>  #define INTEN_RISE1  (1 << 4)
>  #define INTEN_RISE2  (1 << 8)
> +
> +#ifdef CONFIG_EXYNOS5250
> +#define INTEN_FALL0  (1 << 12)
> +#else
>  #define INTEN_FALL0  (1 << 16)
> +#endif
> +
>  #define INTEN_FALL1  (1 << 20)
>  #define INTEN_FALL2  (1 << 24)
>  
> @@ -43,9 +49,24 @@
>  #define INTCLEAR_FALL0   (1 << 16)
>  #define INTCLEAR_FALL1   (1 << 20)
>  #define INTCLEAR_FALL2   (1 << 24)
> +
> +#ifdef CONFIG_EXYNOS5260
> +#define INTEN_RISE3  (1 << 12)
> +#define INTEN_FALL3  (1 << 28)
> +#define INTCLEAR_RISE3   (1 << 12)
> +#define INTCLEAR_FALL3   (1 << 28)
> +#endif
> +
> +#if defined(INTCLEAR_RISE3) && defined(INTCLEAR_FALL3)
>  #define INTCLEARALL  (INTCLEAR_RISE0 | INTCLEAR_RISE1 | \
> -  INTCLEAR_RISE2 | INTCLEAR_FALL0 | \
> -  INTCLEAR_FALL1 | INTCLEAR_FALL2)
> + INTCLEAR_RISE2 | INTCLEAR_RISE3 | \
> + INTCLEAR_FALL0 | INTCLEAR_FALL1 | \
> + INTCLEAR_FALL2 | INTCLEAR_FALL3)
> +#else
> +#define INTCLEARALL  (INTCLEAR_RISE0 | INTCLEAR_RISE1 | \
> + INTCLEAR_RISE2 | INTCLEAR_FALL0 | \
> + INTCLEAR_FALL1 | INTCLEAR_FALL2)
> +#endif
>  
>  /* Tmeperature threshold values for various thermal events */
>  struct temperature_params {
> 

I recommended that don't use ifdefs.
And if you want to support exynos5260 then please post full features and board 
file.

Thanks,
Minkyu Kang.
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[U-Boot] Pull request: u-boot-sh/rmobile into u-boot-arm/master

[Nobuhiro Iwamatsu]

Dear Albert Aribaud,

Please pull u-boot-sh/rmobile into u-boot-arm/master.

The following changes since commit
77524d2c9d81e97c54e704b65c8a02e4bec0f441:

  Merge branch 'u-boot-atmel/master' into 'u-boot-arm/master'
(2013-12-02 16:00:10 +0100)

are available in the git repository at:


  git://git.denx.de/u-boot-sh.git rmobile

for you to fetch changes up to
cae83ce5159f9533b3dd3b442e9e5926fd0e285b:

  arm: rmobile: Remove config.mk (2013-12-03 09:47:15 +0900)


Nobuhiro Iwamatsu (7):
  arm: rmobile: Move lowlevel_init.o to taget of each CPU
  arm: rmobile: Add support R8A7790
  arm: rmobile: Add support lager board
  arm: rmobile: Add support R8A7791
  arm: rmobile: Add support koelsch board
  arm: kzm9g: Fix undefined reference to `__aeabi_uldivmod' error
  arm: rmobile: Remove config.mk

 arch/arm/cpu/armv7/rmobile/Makefile  |   11 +-
 arch/arm/cpu/armv7/rmobile/config.mk |9 -
 arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c|   22 +
 arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c|   29 +
 arch/arm/cpu/armv7/rmobile/cpu_info.c|   10 +
 arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S  |   60 ++
 arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c |  829
+++
 arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h |   92 ++
 arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c | 1117

 arch/arm/cpu/armv7/rmobile/timer.c   |8 +-
 arch/arm/include/asm/arch-rmobile/gpio.h |6 +
 arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h |  387 +++
 arch/arm/include/asm/arch-rmobile/r8a7790.h  |  614 +++
 arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h |  438 
 arch/arm/include/asm/arch-rmobile/r8a7791.h  |  664 
 arch/arm/include/asm/arch-rmobile/rmobile.h  |4 +
 board/renesas/koelsch/Makefile   |9 +
 board/renesas/koelsch/koelsch.c  |  283 +
 board/renesas/koelsch/qos.c  | 1220
++
 board/renesas/koelsch/qos.h  |   12 +
 board/renesas/lager/Makefile |9 +
 board/renesas/lager/lager.c  |  287 +
 board/renesas/lager/qos.c| 1119

 board/renesas/lager/qos.h|   12 +
 boards.cfg   |4 +
 include/configs/koelsch.h|  133 +++
 include/configs/lager.h  |  141 +++
 27 files changed, 7512 insertions(+), 17 deletions(-)
 delete mode 100644 arch/arm/cpu/armv7/rmobile/config.mk
 create mode 100644 arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c
 create mode 100644 arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c
 create mode 100644 arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
 create mode 100644 arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c
 create mode 100644 arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h
 create mode 100644 arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c
 create mode 100644 arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h
 create mode 100644 arch/arm/include/asm/arch-rmobile/r8a7790.h
 create mode 100644 arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h
 create mode 100644 arch/arm/include/asm/arch-rmobile/r8a7791.h
 create mode 100644 board/renesas/koelsch/Makefile
 create mode 100644 board/renesas/koelsch/koelsch.c
 create mode 100644 board/renesas/koelsch/qos.c
 create mode 100644 board/renesas/koelsch/qos.h
 create mode 100644 board/renesas/lager/Makefile
 create mode 100644 board/renesas/lager/lager.c
 create mode 100644 board/renesas/lager/qos.c
 create mode 100644 board/renesas/lager/qos.h
 create mode 100644 include/configs/koelsch.h
 create mode 100644 include/configs/lager.h

-- 
Nobuhiro Iwamatsu
   iwamatsu at {nigauri.org / debian.org}
   GPG ID: 40AD1FA6
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[U-Boot] [PATCH 1/3 v6] arm: rmobile: Move lowlevel_init.o to taget of each CPU

[Nobuhiro Iwamatsu]

Signed-off-by: Nobuhiro Iwamatsu 
---
 v6: Fix failure of application on arm/HEAD.
 v5: add this patch.

 arch/arm/cpu/armv7/rmobile/Makefile | 9 +++--
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm/cpu/armv7/rmobile/Makefile 
b/arch/arm/cpu/armv7/rmobile/Makefile
index 8f4cf3a..327df9e 100644
--- a/arch/arm/cpu/armv7/rmobile/Makefile
+++ b/arch/arm/cpu/armv7/rmobile/Makefile
@@ -5,16 +5,13 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y = lowlevel_init.o
-obj-y += cpu_info.o
+obj-y = cpu_info.o
 obj-y += emac.o
 
 obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o
 obj-$(CONFIG_GLOBAL_TIMER) += timer.o
-obj-$(CONFIG_R8A7740) += cpu_info-r8a7740.o
-obj-$(CONFIG_R8A7740) += pfc-r8a7740.o
-obj-$(CONFIG_SH73A0) += cpu_info-sh73a0.o
-obj-$(CONFIG_SH73A0) += pfc-sh73a0.o
+obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
+obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
 obj-$(CONFIG_TMU_TIMER) += sh_timer.o
 
 SRCS += $(obj)sh_timer.c
-- 
1.8.5

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Re: [U-Boot] [PATCH 5/5] ARM: mx6: Enable PCIe on Sabrelite

[Eric Nelson]

Hi Marek,

On 11/29/2013 05:06 PM, Marek Vasut wrote:

Dear Stefano Babic,


Hi Eric, Marek,

On 27/11/2013 17:19, Eric Nelson wrote:

It seems to lock up the system if you don't have the proper
device connected.

Without this bit, I was able to confirm proper enumeration

of a PCIe bus with a USB 3.0 controller:
00:01.0 - 16c3:abcd - Bridge device
01:00.0- 1b21:0612 - Mass storage controller

Unfortunately, in a quick test, the image fails to boot
without a PCIe device connected, or oddly, with a different
PCIe ethernet controller connected.

I think it's handy to have the placeholder here, but
I think you're the only person on the planet with the
right set of components to make it work at the moment.


Waiting for someone from Mars is coming to help Marek, I'll put the
patchset in the -next for better testing.


I got a hint from fourth dimension, let's see if the patch I produced in a
higher level of consciousness helps ... let's hope I wasn't too high (pun
intended, lol!)



Sorry for the delayed response. The holiday got in the way
of testing.

I think I already had this patch. I tested with these
patches against Stefano's master branch:

0001-ARM-mx6-Update-non-Freescale-boards-to-include-CPU-e.patch
0002-ARM-armv7-Make-indirect-vector-addresses-globl.patch
0003-ARM-lib-Add-cpu_clock_teardown-call.patch
0004-ARM-mx6-Add-PCI-express-clock-configuration.patch
0005-ARM-mx6-Add-PCI-express-driver.patch
0006-ARM-mx6-Enable-PCIe-on-Sabrelite.patch

I also apologize for some bad information the other day.

I saw (and reported) lock-ups during PCIE bus enumeration,
but I can't seem to reproduce them tonight.

I've tested against three different PCIe devices, and with
nothing connected, and everything boots.

As I mentioned, we don't have one of the ethernet
adapters you're using, but this patch set doesn't appear to
break anything.

I'll try on some other boards over the coming days and
let you know if I see any issues.

Regards,


Eric
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Re: [U-Boot] [PATCH v3 4/4] cmd_eeprom: bug fix for i2c read/write

[Kuo-Jung Su]

2013/12/2 Alexey Brodkin :
> On Mon, 2013-12-02 at 16:02 +0800, Kuo-Jung Su wrote:
>> From: Kuo-Jung Su 
>
>> diff --git a/common/cmd_eeprom.c b/common/cmd_eeprom.c
>> index 02539c4..3924805 100644
>> --- a/common/cmd_eeprom.c
>> +++ b/common/cmd_eeprom.c
>> @@ -161,7 +161,7 @@ int eeprom_read (unsigned dev_addr, unsigned offset, 
>> uchar *buffer, unsigned cnt
>>  #if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
>>   spi_read (addr, alen, buffer, len);
>>  #else
>> - if (i2c_read (addr[0], addr[1], alen-1, buffer, len) != 0)
>> + if (i2c_read(addr[0], offset, alen - 1, buffer, len))
>>   rcode = 1;
>>  #endif
>>   buffer += len;
>
> I think this change is whether incomplete or improper.
> Let's look at source code above line 161:
> =
>  125 #if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
>  126 uchar addr[2];
>  127
>  128 blk_off = offset & 0xFF;/* block offset */
>  129
>  130 addr[0] = offset >> 8;  /* block number */
>  131 addr[1] = blk_off;  /* block offset */
>  132 alen= 2;
>  133 #else
>  134 uchar addr[3];
>  135
>  136 blk_off = offset & 0xFF;/* block offset */
>  137
>  138 addr[0] = offset >> 16; /* block number */
>  139 addr[1] = offset >>  8; /* upper address
> octet */
>  140 addr[2] = blk_off;  /* lower address
> octet */
>  141 alen= 3;
>  142 #endif  /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
>  143
>  144 addr[0] |= dev_addr;/* insert device
> address */
> =
>
> From these line you see that "addr[0]" is set like this:
> ===
> If "CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1":
> addr[0] = offset >> 8;
>
> If "CONFIG_SYS_I2C_EEPROM_ADDR_LEN > 1":
> addr[0] = offset >> 16;
>
> And in both cases then OR with "dev_addr":
> addr[0] |= dev_addr;
> ===
>

This is the reason why I said:

CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW is always enabled inside cmd_eeprom.c

so everything is O.K.

> In other words it gets both real I2S slave address + MSB bits of offset.
> But note that "offset" value stays unchanged.
>

The comment bellow clearly explain the issue here.

soft_i2c.c: line 351 ~ 367:

#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
/*
 * EEPROM chips that implement "address overflow" are ones
 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 * address and the extra bits end up in the "chip address"
 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 * four 256 byte chips.
 *
 * Note that we consider the length of the address field to
 * still be one byte because the extra address bits are
 * hidden in the chip address.
 */
chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);

PRINTD("i2c_read: fix addr_overflow: chip %02X addr %02X\n",
chip, addr);
#endif

> So if you pass both "addr[0]" (which already has MSB bits of "offset")
> and "offset" itself then you'll get completely incorrect I2C command.
>
>> @@ -339,7 +339,7 @@ int eeprom_write (unsigned dev_addr, unsigned offset, 
>> uchar *buffer, unsigned cn
>>   /* Write is enabled ... now write eeprom value.
>>*/
>>  #endif
>> - if (i2c_write (addr[0], addr[1], alen-1, buffer, len) != 0)
>> + if (i2c_write(addr[0], offset, alen - 1, buffer, len))
>>   rcode = 1;
>>
>>  #endif
>
> Same goes to "eeprom_write".
>
> Moreover I'd say that this address/offset tricks are very
> EEPROM-specific and because of this we'd better keep it here and don't
> modify generic I2C code.
>

Yes,the address/offset tricks are device specific (not only EEPROM, it
also applies to Audio Codecs..etc.)
But this code was there over a decade. And if everything works just
fine, why bother ?

> Regards,
> Alexey
>



-- 
Best wishes,
Kuo-Jung Su
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Re: [U-Boot] [PATCH] arm: exynos: fix the align for exynos4_power structure

[Minkyu Kang]

On 02/12/13 15:09, Minkyu Kang wrote:
> res3 should be 4 bytes
> 
> Signed-off-by: Minkyu Kang 
> Cc: Dominik Klein 
> ---
>  arch/arm/include/asm/arch-exynos/power.h |2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

applied to u-boot-samsung.

Thanks,
Minkyu Kang.

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Re: [U-Boot] [PATCH] arm: exynos: fix set_mmc_clk for exynos4x12

[Minkyu Kang]

On 02/12/13 14:25, Jaehoon Chung wrote:
> Fix the set_mmc_clk() for exnos4x12.
> If board is exynos4x12, mmc clock should be set to wrong value.
> 
> Signed-off-by: Jaehoon Chung 
> ---
>  arch/arm/cpu/armv7/exynos/clock.c |3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 

applied to u-boot-samsung.

Thanks,
Minkyu Kang.

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Re: [U-Boot] [PATCH v2] trats: usb: Add usb_cable_connected() function

[Minkyu Kang]

On 02/12/13 21:54, Przemyslaw Marczak wrote:
> Changes:
> - define function usb_cable_connected() in trats board file
>   which returns 1 if cable is connected and 0 otherwise
> - trats.h: add CONFIG_USB_CHECK_CABLE
> 
> Changes v2:
> - add muic avaibility check

Change log should be under --- line.
This is not a commit message.

> 
> Signed-off-by: Przemyslaw Marczak 
> Cc: Minkyu Kang 
> ---
>  board/samsung/trats/trats.c |   11 +++
>  include/configs/trats.h |1 +
>  2 files changed, 12 insertions(+)
> 

Anyway...
applied to u-boot-samsung.

Thanks,
Minkyu Kang.

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Re: [U-Boot] Why u-boot relocate from flash to RAM

[Rommel G Custodio]

Dear tvpatel12,

tvpatel12  gmail.com> writes:

> 
> Hi,
> 
> I can't understand that why u-boot code relocate itself form flash to RAM?
> why it doesn't execute from flash?
> Can anybody explain. Plz

Read the very first paragraph of http://www.denx.de/wiki/DULG/DebuggingUBoot

> 
> Tejas

All the best,
Rommel


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[U-Boot] [PATCH v3] arm: at91: support for the Calao USB-A9263 board (based on AT91SAM9263)

[Mateusz Kulikowski]

Add support for USB-A9263 board manufactured by Calao Systems
(http://www.calao-systems.com/).
Code is based on old U-Boot sources (2010.09) released by Calao.

Signed-off-by: Mateusz Kulikowski 
---
Changes for v3
- Updated Makefile to a new build system
- Use generic GPIO for NAND and MAC (requires new GPIO patches)
- Use common at91 phy reset
- Dropped spi0 clock setup (pin is unused)
- Fixed PHY address as 0x0001 and dropped PHY autodetect
  (no need for autodetect - PHY address is bootstrapped to 1)
---
 board/calao/usb_a9263/Makefile|  14 
 board/calao/usb_a9263/usb_a9263.c | 148 +
 boards.cfg|   1 +
 include/configs/usb_a9263.h   | 169 ++
 4 files changed, 332 insertions(+)
 create mode 100644 board/calao/usb_a9263/Makefile
 create mode 100644 board/calao/usb_a9263/usb_a9263.c
 create mode 100644 include/configs/usb_a9263.h

diff --git a/board/calao/usb_a9263/Makefile b/board/calao/usb_a9263/Makefile
new file mode 100644
index 000..8a22b3e
--- /dev/null
+++ b/board/calao/usb_a9263/Makefile
@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop 
+# Lead Tech Design 
+#
+# (C) Copyright 2013
+# Mateusz Kulikowski 
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y  += usb_a9263.o
diff --git a/board/calao/usb_a9263/usb_a9263.c 
b/board/calao/usb_a9263/usb_a9263.c
new file mode 100644
index 000..266e950
--- /dev/null
+++ b/board/calao/usb_a9263/usb_a9263.c
@@ -0,0 +1,148 @@
+/*
+ * (C) Copyright 2007-2013
+ * Stelian Pop 
+ * Lead Tech Design 
+ * Thomas Petazzoni, Free Electrons, 
+ * Mateusz Kulikowski 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_HAS_DATAFLASH
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+   {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},   /* Logical adress, CS */
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+   {0x, 0x1FFF, FLAG_PROTECT_SET, 0, "Bootstrap"},
+   {0x2000, 0x3FFF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+   {0x4000, 0x, FLAG_PROTECT_CLEAR, 0, "U-Boot"},
+};
+#endif
+
+#ifdef CONFIG_CMD_NAND
+static void usb_a9263_nand_hw_init(void)
+{
+   unsigned long csa;
+   at91_smc_t *smc = (at91_smc_t *)ATMEL_BASE_SMC0;
+   at91_matrix_t *matrix = (at91_matrix_t *)ATMEL_BASE_MATRIX;
+   at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
+
+   /* Enable CS3 */
+   csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+   writel(csa, &matrix->csa[0]);
+
+   /* Configure SMC CS3 for NAND/SmartMedia */
+   writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+  AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+  &smc->cs[3].setup);
+
+   writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+  AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+  &smc->cs[3].pulse);
+
+   writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+  &smc->cs[3].cycle);
+
+   writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+  AT91_SMC_MODE_EXNW_DISABLE |
+  AT91_SMC_MODE_DBW_8 |
+  AT91_SMC_MODE_TDF_CYCLE(2), &smc->cs[3].mode);
+
+   writel(1 << ATMEL_ID_PIOA | 1 << ATMEL_ID_PIOCDE, &pmc->pcer);
+
+   /* Configure RDY/BSY */
+   gpio_request(CONFIG_SYS_NAND_READY_PIN, "NAND ready/busy");
+   gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+
+   /* Enable NandFlash */
+   gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "NAND enable");
+   gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void usb_a9263_macb_hw_init(void)
+{
+   at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
+
+   /* Enable clock */
+   writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
+
+   /*
+* Disable pull-up on:
+*  RXDV (PC25) => PHY normal mode (not Test mode)
+*  ERX0 (PE25) => PHY ADDR0
+*  ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
+*
+* PHY has internal weak pull-up/pull-down
+*/
+   gpio_request(GPIO_PIN_PC(25), "PHY mode");
+   gpio_direction_input(GPIO_PIN_PC(25));
+
+   gpio_request(GPIO_PIN_PE(25), "PHY ADDR0");
+   gpio_direction_input(GPIO_PIN_PE(25));
+
+   gpio_request(GPIO_PIN_PE(26), "PHY ADDR1");
+   gpio_direction_input(GPIO_PIN_PE(26));
+
+   at91_phy_reset();
+
+   /* It will set proper pinmux for ports PC25, PE25-26 */
+   at91_macb_hw_init();
+}
+#endif
+
+int board_init(void)
+{
+   /* adress of boot parameters */
+   gd->bd->bi_boot_params 

Re: [U-Boot] why u-boot relocate it self to RAM from flash?

[Graeme Russ]

Hi,

On Tue, Dec 3, 2013 at 1:18 AM, FengHua  wrote:

>
> > Hi,
> >
> > I can not understand why u-boot relocate it self to RAM from flash? Why
> is
> > it not executing from flash?
> > Can anybody explain.
> >
>
> First, flash is slow.
> Second, there are many data structures or variables which should be
> writable.
> So, we should copy u-boot to RAM and relocate it.
>

I'll expand a bit...

In theory the writeable could be relocated into RAM, but this would require
the relocation address to be hard-coded. Optimally, U-Boot places itself in
a memory location to provide the maximum contiguous memory space to load
the operating system kernel and supporting data (RAM disks, FDTs, etc).

On most systems now, relocation is done by calculating the delta between
the ROM address (TEXT_BASE) and the relocated address in RAM. The
relocation code first copies the entire U-Boot image to RAM (apart from a
few structures that are used only during the relocation calculation). It
then scans the relocation entries (*.rel sections) to find where in the
U-Boot executable all the references into the data sections. At each
reference point in the executable, the relocation code modifies the
reference by the relocation offset. None of this can happen if the U-Boot
executable is in Flash.

The other advantage of relocating U-Boot to RAM is that it makes it
possible to flash a new U-Boot image from U-Boot. If you try to do this
while U-Boot is running from flash, it will crash as you are overwriting
the executable code while it's executing.

 Regards,

Graeme
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[U-Boot] sf implementation

[Eggler, Ron (GE Energy Management, Non-GE)]

Hi Maillist,

I'm new here and just started looking through the source code as I'm interested 
to see, how the function sf for loading a serial flash is implemented. I 
however can not seem to be able to find this in the source code, may you have 
any hints for me? I'm working with version 2013.01.

Thank you,
Ron

Ron Eggler
Senior Embedded Firmware Engineer

General Electric Canada
Digital Energy
100 - 8525 Baxter Pl, Burnaby, BC CANADA
Direct: +1-604-421-8615



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[U-Boot] [PATCH v2 1/2] socfpga: Adding Scan Manager driver

[Chin Liang See]

Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings

Signed-off-by: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Wolfgang Denk 
CC: Pavel Machek 
Cc: Tom Rini 
Cc: Albert Aribaud 

Signed-off-by: Chin Liang See 
---
Changes for v2
- rebase with latest v2014.01-rc1
---
 arch/arm/cpu/armv7/socfpga/Makefile|2 +-
 arch/arm/cpu/armv7/socfpga/scan_manager.c  |  231 
 arch/arm/cpu/armv7/socfpga/spl.c   |4 +
 arch/arm/include/asm/arch-socfpga/scan_manager.h   |   97 
 .../include/asm/arch-socfpga/socfpga_base_addrs.h  |1 +
 include/configs/socfpga_cyclone5.h |1 +
 6 files changed, 335 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c
 create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h

diff --git a/arch/arm/cpu/armv7/socfpga/Makefile 
b/arch/arm/cpu/armv7/socfpga/Makefile
index 3e84a0c..4edc5d4 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -9,4 +9,4 @@
 
 obj-y  := lowlevel_init.o
 obj-y  += misc.o timer.o reset_manager.o system_manager.o
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
diff --git a/arch/arm/cpu/armv7/socfpga/scan_manager.c 
b/arch/arm/cpu/armv7/socfpga/scan_manager.c
new file mode 100644
index 000..30cbb8b
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/scan_manager.c
@@ -0,0 +1,231 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_scan_manager *scan_manager_base =
+   (void *)(SOCFPGA_SCANMGR_ADDRESS);
+static const struct socfpga_freeze_controller *freeze_controller_base =
+   (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
+
+/*
+ * Function to check IO scan chain engine status and wait if the engine is
+ * is active. Poll the IO scan chain engine till maximum iteration reached.
+ */
+static inline uint32_t scan_mgr_io_scan_chain_engine_is_idle(uint32_t max_iter)
+{
+   uint32_t scanmgr_status;
+
+   scanmgr_status = readl(&scan_manager_base->stat);
+
+   /* Poll the engine until the scan engine is inactive */
+   while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status)
+   || (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) > 0)) {
+
+   max_iter--;
+
+   if (max_iter > 0)
+   scanmgr_status = readl(&scan_manager_base->stat);
+   else
+   return SCAN_MGR_IO_SCAN_ENGINE_STATUS_ACTIVE;
+   }
+   return SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE;
+}
+
+
+
+/* Program HPS IO Scan Chain */
+uint32_t scan_mgr_io_scan_chain_prg(
+   uint32_t io_scan_chain_id,
+   uint32_t io_scan_chain_len_in_bits,
+   const uint32_t *iocsr_scan_chain)
+{
+
+   uint16_t tdi_tdo_header;
+   uint32_t io_program_iter;
+   uint32_t io_scan_chain_data_residual;
+   uint32_t residual;
+   uint32_t i;
+   uint32_t index = 0;
+
+   /* De-assert reinit if the IO scan chain is intended for HIO */
+   if (3 == io_scan_chain_id)
+   clrbits_le32(&freeze_controller_base->hioctrl,
+   SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
+
+   /*
+* Check if the scan chain engine is inactive and the
+* WFIFO is empty before enabling the IO scan chain
+*/
+   if (SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE
+   != scan_mgr_io_scan_chain_engine_is_idle(
+   MAX_WAITING_DELAY_IO_SCAN_ENGINE)) {
+   return 1;
+   }
+
+   /*
+* Enable IO Scan chain based on scan chain id
+* Note: only one chain can be enabled at a time
+*/
+   setbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
+
+   /*
+* Calculate number of iteration needed for full 128-bit (4 x32-bits)
+* bits shifting. Each TDI_TDO packet can shift in maximum 128-bits
+*/
+   io_program_iter = io_scan_chain_len_in_bits >>
+   IO_SCAN_CHAIN_128BIT_SHIFT;
+   io_scan_chain_data_residual = io_scan_chain_len_in_bits &
+   IO_SCAN_CHAIN_128BIT_MASK;
+
+   /* Construct TDI_TDO packet for 128-bit IO scan chain (2 bytes) */
+   tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE | (TDI_TDO_MAX_PAYLOAD <<
+   TDI_TDO_HEADER_SECOND_BYTE_SHIFT);
+
+   /* Program IO scan chain in 128-bit iteration */
+   for (i = 0; i < io_program_iter; i++) {
+
+   /* write TDI_TDO packet header to scan manager */
+   writel(tdi_tdo_header,  &scan_manager_base->fifodoublebyte);
+
+   /* calculate array index */
+   index = i * 4;
+
+   /* write 4 successive 32-bit IO scan chain data into WFIFO */

[U-Boot] [PATCH v2 2/2] socfpga: Adding Scan Manager IOCSR handoff files

[Chin Liang See]

The IOCSR handoff files will be consumed by Scan Manager driver.

Signed-off-by: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Wolfgang Denk 
CC: Pavel Machek 
Cc: Tom Rini 
Cc: Albert Aribaud 

Signed-off-by: Chin Liang See 
---
Changes for v2
- rebase with latest v2014.01-rc1
---
 board/altera/socfpga/iocsr_config.c |  653 +++
 board/altera/socfpga/iocsr_config.h |   12 +
 2 files changed, 665 insertions(+)
 create mode 100644 board/altera/socfpga/iocsr_config.c
 create mode 100644 board/altera/socfpga/iocsr_config.h

diff --git a/board/altera/socfpga/iocsr_config.c 
b/board/altera/socfpga/iocsr_config.c
new file mode 100644
index 000..7e66ff8
--- /dev/null
+++ b/board/altera/socfpga/iocsr_config.c
@@ -0,0 +1,653 @@
+
+/* This file is generated by Preloader Generator */
+
+#include 
+
+const unsigned long iocsr_scan_chain0_table[((
+   CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
+   0x,
+   0x,
+   0x0FF0,
+   0xC000,
+   0x003F,
+   0x8000,
+   0x00020080,
+   0x0802,
+   0x0800,
+   0x00018020,
+   0x,
+   0x4000,
+   0x00010040,
+   0x0401,
+   0x0400,
+   0x0010,
+   0x4010,
+   0x2000,
+   0x0002,
+   0x02008000,
+   0x0200,
+   0x0008,
+   0x2008,
+   0x1000,
+};
+
+const unsigned long iocsr_scan_chain1_table[((
+   CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = {
+   0x000C0300,
+   0x1004,
+   0x10C0,
+   0x0040,
+   0x00010040,
+   0x8000,
+   0x0008,
+   0x1806,
+   0x1800,
+   0x0060,
+   0x00018060,
+   0x4000,
+   0x00010040,
+   0x1000,
+   0x0400,
+   0x0010,
+   0x4010,
+   0x2000,
+   0x06008020,
+   0x02008000,
+   0x01FE,
+   0xF800,
+   0x0007,
+   0x1000,
+   0x4010,
+   0x01004000,
+   0x0100,
+   0x3004,
+   0x1004,
+   0x0800,
+   0x,
+   0x,
+   0x0080,
+   0x0002,
+   0x2000,
+   0x0400,
+   0x,
+   0x00401000,
+   0x0003,
+   0x,
+   0x,
+   0x0200,
+   0x00600802,
+   0x,
+   0x8020,
+   0x8600,
+   0x0200,
+   0x0100,
+   0x00300401,
+   0xC0100400,
+   0x4010,
+   0x4300,
+   0x000C0100,
+   0x0080,
+};
+
+const unsigned long iocsr_scan_chain2_table[((
+   CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = {
+   0x80040100,
+   0x,
+   0x0FF0,
+   0x,
+   0x0C010040,
+   0x8000,
+   0x18020080,
+   0x,
+   0x0800,
+   0x00040020,
+   0x06018060,
+   0x4000,
+   0x0C010040,
+   0x0401,
+   0x0030,
+   0x,
+   0x03004010,
+   0x2000,
+   0x06008020,
+   0x02008000,
+   0x0218,
+   0x6008,
+   0x01802008,
+   0x1000,
+   0x03004010,
+   0x01004000,
+   0x010C,
+   0x3004,
+   0x00C01004,
+   0x0800,
+};
+
+const unsigned long iocsr_scan_chain3_table[((
+   CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = {
+   0x2C420D80,
+   0x082000FF,
+   0x0A804001,
+   0x0790,
+   0x0802,
+   0x0010,
+   0x0A80,
+   0x0790,
+   0x0802,
+   0x0010,
+   0xC880,
+   0x3001,
+   0x00C00722,
+   0x,
+   0x0021,
+   0x8204,
+   0x0540,
+   0x03C8,
+   0x0401,
+   0x0008,
+   0x0540,
+   0x03C8,
+   0x0540,
+   0x03C8,
+   0xE440,
+   0x1800,
+   0x00600391,
+   0x800E4400,
+   0x0001,
+   0x4002,
+   0x02A0,
+   0x01E4,
+   0x02A0,
+   0x01E4,
+   0x02A0,
+   0x01E4,
+   0x02A0,
+   0x01E4,
+   0x7220,
+   0x8C00,
+   0x003001C8,
+   0xC0072200,
+   0x1C88,
+   0x2300,
+   0x0004,
+   0x5067,
+   0x0070,
+   0x2459,
+   0x1000,
+   0xA034,
+   0x0D01,
+   0x906808A2,
+   0xA2834024,
+   0x05141A00,
+   0x808A20D0,
+   0x34024906,
+   0x01A00A28,
+   0xA20D,
+   0x24906808,
+   0x00A28340,
+   0xD01A,
+   0x06808A20,
+   0x1004,
+   0x0020,
+   0x1004,
+   0x0020,
+   0x1500,
+   0x0F20,
+   0x1500,
+   0x0F20,
+   0x01FE,
+   0x,
+   0x01800E44,
+   0x00391000,
+   0x007F8006,
+   0x,
+   0x0A81,
+   0x0790,
+   

[U-Boot] [PATCH 0/2 v2] socfpga: Adding Scan Manager

[Chin Liang See]

Adding Scan Manager driver and handoff files. Scan Manager driver
will be called to configure the IO buffer setting.

Signed-off-by: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Wolfgang Denk 
CC: Pavel Machek 
Cc: Tom Rini 
Cc: Albert Aribaud 
---
Changes for v2
- Rebase with latest v2014.01-rc1

Chin Liang See (2):
  socfpga: Adding Scan Manager driver
  socfpga: Adding Scan Manager IOCSR handoff files

 arch/arm/cpu/armv7/socfpga/Makefile|2 +-
 arch/arm/cpu/armv7/socfpga/scan_manager.c  |  231 +++
 arch/arm/cpu/armv7/socfpga/spl.c   |4 +
 arch/arm/include/asm/arch-socfpga/scan_manager.h   |   97 +++
 .../include/asm/arch-socfpga/socfpga_base_addrs.h  |1 +
 board/altera/socfpga/iocsr_config.c|  653 
 board/altera/socfpga/iocsr_config.h|   12 +
 include/configs/socfpga_cyclone5.h |1 +
 8 files changed, 1000 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c
 create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h
 create mode 100644 board/altera/socfpga/iocsr_config.c
 create mode 100644 board/altera/socfpga/iocsr_config.h

-- 
1.7.9.5


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Re: [U-Boot] [PATCH v7 0/13] Driver model implementation, tests, demo and GPIO

[Simon Glass]

+Tom

Hi,

On 2 December 2013 12:02, Mateusz Zalega  wrote:
> On 11/29/13 02:00, Masahiro Yamada wrote:
>> How come 13/13 is missing?
>
> It's not.

I think it was missing until someone approved it, since it was over
the 100KB limit.

Regards,
Simon
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Re: [U-Boot] [PATCH] powerpc/mpc85xx: Add support for single source clocking

[York Sun]

On 11/27/2013 09:34 PM, Priyanka Jain wrote:
> Single-source clocking is new feature introduced in T1040.
> In this mode, a differential clock is supplied to the
> DIFF_SYSCLK_P/N inputs to the processor, which in turn is
> used to supply clocks to the sysclock, ddrclock and usbclock.
> 
> So, both ddrclock and syclock are driven by same differential
> sysclock in single-sourec clocking whereas in normal clocking
> mode, generally separate DDRCLK and SYSCLK pins provides
> reference clock for sysclock and ddrclock
> 
> DDR_REFCLK_SEL rcw bit is used to determine DDR clock source
> -If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in
>  normal clocking mode by DDR_Reference clock
> 
> -If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in
>  single source clocking mode by DIFF_SYSCLK
> 
> Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit.
> 
> Signed-off-by: Poonam Aggrwal 
> Signed-off-by: Priyanka Jain 
> ---
>  arch/powerpc/cpu/mpc85xx/speed.c  |   20 
>  arch/powerpc/include/asm/config_mpc85xx.h |1 +
>  arch/powerpc/include/asm/immap_85xx.h |3 +++
>  3 files changed, 24 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/powerpc/cpu/mpc85xx/speed.c 
> b/arch/powerpc/cpu/mpc85xx/speed.c
> index 1a58a19..cd49695 100644
> --- a/arch/powerpc/cpu/mpc85xx/speed.c
> +++ b/arch/powerpc/cpu/mpc85xx/speed.c
> @@ -77,7 +77,27 @@ void get_sys_info(sys_info_t *sys_info)
>  
>   sys_info->freq_systembus = sysclk;
>  #ifdef CONFIG_DDR_CLK_FREQ

Do you think it is right to put the single clock detection here? This
macro CONFIG_DDR_CLK_FREQ is used when a dedicated DDR reference clock
is used. In case the DIFF_SYSCLK is used, you don't have to have a DDR
reference clock, do you?

> +#ifdef CONFIG_SINGLE_SOURCE_CLK
> + /*
> +  * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
> +  * are driven by separate DDR Refclock or single source
> +  * differential clock.
> +  */
> + uint single_src;
> + single_src = (in_be32(&gur->rcwsr[5]) >>
> +   FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
> +   FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
> + /*
> +  * For single source clocking, both ddrclock and syclock
> +  * are driven by differential sysclock.
> +  */
> + if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
> + sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
> + else
> + sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
> +#else
>   sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
> +#endif
>  #else
>   sys_info->freq_ddrbus = sysclk;
>  #endif

My point is you probably don't have to define CONFIG_DDR_CLK_FREQ to use
single source clock.

York

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Re: [U-Boot] [PATCH v7 0/13] Driver model implementation, tests, demo and GPIO

[Mateusz Zalega]

On 11/29/13 02:00, Masahiro Yamada wrote:
> How come 13/13 is missing?

It's not.

-- 
Mateusz Zalega
Samsung R&D Institute Poland
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Re: [U-Boot] regarding RAM Test

[York Sun]

On 12/02/2013 10:20 AM, Beagle Board wrote:
> Hi all,
> 
> I wanted to perform a RAM test in u-boot for my DM8148 board. I've used the
> "*mtest*" command present in u-boot.
> But its taking ages and it looks like a never ending test.
> 
> So guys can anyone point me a way to test maximum RAM memory.
> Here why i'm asking maximum is if I try it from kernel level then some
> amount of RAM will be used up by kernel as well as other applications.
> 
> Any thoughts in this regard will be of great help.
> 

Just my 2 cents.

Memory testing has two targets. One is to confirm hardware connection.
For this, we have walking 1 test, address test, etc. You can catch
cross-talk, or other "hard" issues. I use POST memory test for this purpose.

The other target is to confirm timing configuration. I found memory test
algorithm is not helpful for this one. I never found any error with
software testing when there is a timing issue. My solution is to rely on
ECC detection and run some memory extensive tests and check ECC status.
The tests I use includes booting Linux, run lmbench, run md5sum on
ramdisk with know files filled with random data and checksum.

Hope this helps.

York


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[U-Boot] regarding RAM Test

[Beagle Board]

Hi all,

I wanted to perform a RAM test in u-boot for my DM8148 board. I've used the
"*mtest*" command present in u-boot.
But its taking ages and it looks like a never ending test.

So guys can anyone point me a way to test maximum RAM memory.
Here why i'm asking maximum is if I try it from kernel level then some
amount of RAM will be used up by kernel as well as other applications.

Any thoughts in this regard will be of great help.
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Re: [U-Boot] adding NAND support for omap4 (based on pandaboard)

[Gupta, Pekon]

>From: Abraham V. [mailto:abraham.varric...@vvdntech.com]
>
>4. At this point we'll get some complaints about missing static
>definitions, so apply the following patch to add them in the common
>configuration file;
>
>diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h
> 
These should go into your include/configs/your_board.h ?
Please don't add anything board specific into omap4_common.
Example: NAND device parameter (pagesize, blocksize, eccscheme)...
are based on NAND device present on your board. It would not be
present on all OMAP4 boards, so such CONFIGS should be local your_board.h

[...]

>
>The following edit is also needed in the panda configuration file (it
>won't work from the common file as the panda configuration will
>over-ride it)
>
You should not include omap4_panda.h.
Rather make a copy of it, and then make local modifications for your board.
Otherwise it would break u-boot for other omap4_panda users..

[...]

>And at this point, I encounter the same error I mentioned last time
>(output below). Quite frankly, I'm stuck on how to proceed. I
>*suspect* that the SPL build has some extra configuration file where I
>need to mention the NAND support, but am not sure where to look. :(
>
[...]
>Help?
>
If you can wait till next week may be I can get you patches for NAND on
OMAP4 and OMAP5, which you can test on your hardware and ack..
This is on my to-do list.. and I'm currently working on something similar.

>
>PS: Sorry about the HTML in my last reply. Hope this is better?
> 
No issues, thanks ...


with regards, pekon
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[U-Boot] [PATCH v5] socfpga: Adding Freeze Controller driver

[Chin Liang See]

Adding Freeze Controller driver. All HPS IOs need to be
in freeze state during pin mux or IO buffer configuration.
It is to avoid any glitch which might happen
during the configuration from propagating to external devices.

Signed-off-by: Chin Liang See 
Cc: Wolfgang Denk 
CC: Pavel Machek 
Cc: Dinh Nguyen 
Cc: Tom Rini 
Cc: Albert Aribaud 
---
Changes for v5
- Rebase with latest v2014.01-rc1
Changes for v4
- Removed additional lines
- Single function call to freeze and thaw all channels
Changes for v3
- Removed unused macro in freeze_controller.h
Changes for v2
- Removed FREEZE_CONTROLLER_FSM_HW
- Removed the get_timer_count_masked and convert to use delay in us
- Used shorter local variables
---
 arch/arm/cpu/armv7/socfpga/Makefile|2 +-
 arch/arm/cpu/armv7/socfpga/freeze_controller.c |  216 
 arch/arm/cpu/armv7/socfpga/spl.c   |9 +
 .../include/asm/arch-socfpga/freeze_controller.h   |   50 +
 4 files changed, 276 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/cpu/armv7/socfpga/freeze_controller.c
 create mode 100644 arch/arm/include/asm/arch-socfpga/freeze_controller.h

diff --git a/arch/arm/cpu/armv7/socfpga/Makefile 
b/arch/arm/cpu/armv7/socfpga/Makefile
index dac2bbd..3e84a0c 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -9,4 +9,4 @@
 
 obj-y  := lowlevel_init.o
 obj-y  += misc.o timer.o reset_manager.o system_manager.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
diff --git a/arch/arm/cpu/armv7/socfpga/freeze_controller.c 
b/arch/arm/cpu/armv7/socfpga/freeze_controller.c
new file mode 100644
index 000..330b4aa
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/freeze_controller.c
@@ -0,0 +1,216 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_freeze_controller *freeze_controller_base =
+   (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
+
+/*
+ * Default state from cold reset is FREEZE_ALL; the global
+ * flag is set to TRUE to indicate the IO banks are frozen
+ */
+static uint32_t frzctrl_channel_freeze[FREEZE_CHANNEL_NUM]
+   = { FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN,
+   FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN};
+
+/* Freeze HPS IOs */
+void sys_mgr_frzctrl_freeze_req(void)
+{
+   u32 ioctrl_reg_offset;
+   u32 reg_value;
+   u32 reg_cfg_mask;
+   u32 channel_id;
+
+   /* select software FSM */
+   writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src);
+
+   /* Freeze channel 0 to 2 */
+   for (channel_id = 0; channel_id <= 2; channel_id++) {
+   ioctrl_reg_offset = (u32)(
+   &freeze_controller_base->vioctrl +
+   (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
+
+   /*
+* Assert active low enrnsl, plniotri
+* and niotri signals
+*/
+   reg_cfg_mask =
+   SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK
+   | SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
+   | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
+   clrbits_le32(ioctrl_reg_offset, reg_cfg_mask);
+
+   /*
+* Note: Delay for 20ns at min
+* Assert active low bhniotri signal and de-assert
+* active high csrdone
+*/
+   reg_cfg_mask
+   = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
+   | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
+   clrbits_le32(ioctrl_reg_offset, reg_cfg_mask);
+
+   /* Set global flag to indicate channel is frozen */
+   frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN;
+   }
+
+   /* Freeze channel 3 */
+   /*
+* Assert active low enrnsl, plniotri and
+* niotri signals
+*/
+   reg_cfg_mask
+   = SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK
+   | SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
+   | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
+   clrbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask);
+
+   /*
+* assert active low bhniotri & nfrzdrv signals,
+* de-assert active high csrdone and assert
+* active high frzreg and nfrzdrv signals
+*/
+   reg_value = readl(&freeze_controller_base->hioctrl);
+   reg_cfg_mask
+   = SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
+   | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK;
+   reg_value
+   = (reg_value & ~reg_cfg_mask)
+   | SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK
+   | SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
+   writel(reg_value, &freeze_controller_base->hioctrl);
+
+   /*
+* assert active high reinit sign

Re: [U-Boot] [PATCH v4] socfpga: Adding Freeze Controller driver

[Chin Liang See]

Hi Albert

On Mon, 2013-12-02 at 18:15 +0100, ZY - albert.u.boot wrote:
> Hi Chin Liang,
> 
> On Tue, 1 Oct 2013 13:42:20 -0500, Chin Liang See 
> wrote:
> 
> > Hi guys,
> > 
> > Any further comments on this? Thanks
> 
> None from me, and I would happily apply it except it does not apply
> cleanly any more on ARM. Can you rebase and re-send?

Sure I already re-based it and will send it out after this email. Thanks
again for your helps.

Chin Liang


> 
> > Chin Liang
> 
> Amicalement,



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Re: [U-Boot] [PATCH v2] arm: ep9315: Return back Cirrus Logic EDB9315A board support

[Albert ARIBAUD]

Hi sergey.kostanbaev,

On Tue, 22 Oct 2013 17:18:45 +0400, "sergey.kostanbaev"
 wrote:

> From: Sergey Kostanbaev 
> 
> This patch returns back support for old ep93xx processors family
> 
> Signed-off-by: Sergey Kostanbaev 
> Cc: albert.u.b...@aribaud.net
> ---

This patch seems not to apply cleanly on current ARM. Can you rebase
and send V3?

Amicalement,
-- 
Albert.
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Re: [U-Boot] [PATCH v4] socfpga: Adding Freeze Controller driver

[Albert ARIBAUD]

Hi Chin Liang,

On Tue, 1 Oct 2013 13:42:20 -0500, Chin Liang See 
wrote:

> Hi guys,
> 
> Any further comments on this? Thanks

None from me, and I would happily apply it except it does not apply
cleanly any more on ARM. Can you rebase and re-send?

> Chin Liang

Amicalement,
-- 
Albert.
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Re: [U-Boot] Zynq serial - pull request

[Tom Rini]

On Mon, Dec 02, 2013 at 11:40:26AM +0100, Michal Simek wrote:

> Hi Tom,
> 
> this is one pending patch which is around for a while and hasn't been merged 
> yet.
> Please add it to your tree.
> 
> Thanks,
> Michal
> 
> The following changes since commit d19ad726bcd5d9106f7ba9c750462fcc369f1020:
> 
>   Prepare v2014.01-rc1 (2013-11-25 16:49:32 -0500)
> 
> are available in the git repository at:
> 
>   git://www.denx.de/git/u-boot-microblaze.git serial
> 
> for you to fetch changes up to 2785a4ae76330dab5e792d52fc9c449ac3d1072e:
> 
>   serial: zynq: Remove unused #defines (2013-12-02 11:36:36 +0100)
> 
> 
> Soren Brinkmann (1):
>   serial: zynq: Remove unused #defines
> 
>  drivers/serial/serial_zynq.c | 4 
>  1 file changed, 4 deletions(-)

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] [PATCH] Blackfin: remove executable permission of AWK script

[Tom Rini]

On Thu, Nov 21, 2013 at 04:10:20PM +0900, Masahiro Yamada wrote:

> Signed-off-by: Masahiro Yamada 
> ---
>  arch/blackfin/cpu/bootrom-asm-offsets.awk | 0
>  1 file changed, 0 insertions(+), 0 deletions(-)
>  mode change 100755 => 100644 arch/blackfin/cpu/bootrom-asm-offsets.awk
> 
> diff --git a/arch/blackfin/cpu/bootrom-asm-offsets.awk 
> b/arch/blackfin/cpu/bootrom-asm-offsets.awk
> old mode 100755
> new mode 100644

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [GIT PULL] u-boot-mips/master

[Tom Rini]

On Wed, Nov 27, 2013 at 12:56:23AM +0100, Daniel Schwierzeck wrote:

> Hi Tom,
> 
> please pull some additional fixes for MIPS malta board, thanks.
> 
> The following changes since commit d19ad726bcd5d9106f7ba9c750462fcc369f1020:
> 
>   Prepare v2014.01-rc1 (2013-11-25 16:49:32 -0500)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-mips.git master
> 
> for you to fetch changes up to 67d4752d1dae768c7ff381272880d4aceeb62085:
> 
>   malta: set CONFIG_SYS_BOOTM_LEN to 64MB (2013-11-26 21:49:42 +0100)
> 
> 
> Paul Burton (4):
>   mips: don't hardcode Malta env baudrate
>   malta: correct UART baudrate
>   malta: enable PIIX4 SERIRQ
>   malta: set CONFIG_SYS_BOOTM_LEN to 64MB
> 
>  arch/mips/include/asm/malta.h |  7 +++
>  arch/mips/lib/bootm.c |  6 --
>  board/imgtec/malta/malta.c| 12 
>  include/configs/malta.h   |  3 ++-
>  4 files changed, 25 insertions(+), 3 deletions(-)

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] [PATCH 0/3] OMAP USB host fixes for Beagle & Panda

[Marek Vasut]

Hi,

> Dear Roger Quadros,
> 
> > Hi,
> > 
> > This series
> > 
> > - Fixes OMAP4 Panda USB device detection issues
> > - Gets rid of ULPI reset errors on Beagle & Panda
> 
> Is this a V2 or what is this? I already see similar series posted a few
> days ago.

I see, it was not posted to the ML before.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 0/3] OMAP USB host fixes for Beagle & Panda

[Tom Rini]

-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1

On 12/02/2013 10:59 AM, Marek Vasut wrote:
> Dear Roger Quadros,
> 
>> Hi,
>> 
>> This series
>> 
>> - Fixes OMAP4 Panda USB device detection issues - Gets rid of 
>> ULPI reset errors on Beagle & Panda
> 
> Is this a V2 or what is this? I already see similar series posted
> a few days ago.

You missed my email.  Roger forgot to CC the mailing list.

- -- 
Tom
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[U-Boot] [PATCH] ARM: mx53: video: Add IPUv3 LCD support for M53EVK

[Marek Vasut]

This patch adds support for the AMPIRE 800x480 LCD panel that is available
for M53EVK.

Signed-off-by: Marek Vasut 
Cc: Stefano Babic 
---
 board/denx/m53evk/m53evk.c | 73 ++
 include/configs/m53evk.h   | 16 ++
 2 files changed, 89 insertions(+)

diff --git a/board/denx/m53evk/m53evk.c b/board/denx/m53evk/m53evk.c
index 3275170..a34b884 100644
--- a/board/denx/m53evk/m53evk.c
+++ b/board/denx/m53evk/m53evk.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -22,6 +23,11 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+
+/* Special MXCFB sync flags are here. */
+#include "../drivers/video/mxcfb.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -166,6 +172,32 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+#ifdef CONFIG_VIDEO
+static struct fb_videomode const ampire_wvga = {
+   .name   = "Ampire",
+   .refresh= 60,
+   .xres   = 800,
+   .yres   = 480,
+   .pixclock   = 29851, /* picosecond (33.5 MHz) */
+   .left_margin= 89,
+   .right_margin   = 164,
+   .upper_margin   = 23,
+   .lower_margin   = 10,
+   .hsync_len  = 10,
+   .vsync_len  = 10,
+   .sync   = FB_SYNC_CLK_LAT_FALL,
+};
+
+int board_video_skip(void)
+{
+   int ret;
+   ret = ipuv3_fb_init(&ire_wvga, 1, IPU_PIX_FMT_RGB666);
+   if (ret)
+   printf("Ampire LCD cannot be configured: %d\n", ret);
+   return ret;
+}
+#endif
+
 #define I2C_PAD_CTRL   (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
 
@@ -179,6 +211,46 @@ static void setup_iomux_i2c(void)
imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
 }
 
+static void setup_iomux_video(void)
+{
+   static const iomux_v3_cfg_t lcd_pads[] = {
+   MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0,
+   MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1,
+   MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2,
+   MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3,
+   MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4,
+   MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5,
+   MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6,
+   MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7,
+   MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8,
+   MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9,
+   MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10,
+   MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11,
+   MX53_PAD_EIM_A17__IPU_DISP1_DAT_12,
+   MX53_PAD_EIM_A18__IPU_DISP1_DAT_13,
+   MX53_PAD_EIM_A19__IPU_DISP1_DAT_14,
+   MX53_PAD_EIM_A20__IPU_DISP1_DAT_15,
+   MX53_PAD_EIM_A21__IPU_DISP1_DAT_16,
+   MX53_PAD_EIM_A22__IPU_DISP1_DAT_17,
+   MX53_PAD_EIM_A23__IPU_DISP1_DAT_18,
+   MX53_PAD_EIM_A24__IPU_DISP1_DAT_19,
+   MX53_PAD_EIM_D31__IPU_DISP1_DAT_20,
+   MX53_PAD_EIM_D30__IPU_DISP1_DAT_21,
+   MX53_PAD_EIM_D26__IPU_DISP1_DAT_22,
+   MX53_PAD_EIM_D27__IPU_DISP1_DAT_23,
+   MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK,
+   MX53_PAD_EIM_DA13__IPU_DI1_D0_CS,
+   MX53_PAD_EIM_DA14__IPU_DI1_D1_CS,
+   MX53_PAD_EIM_DA15__IPU_DI1_PIN1,
+   MX53_PAD_EIM_DA11__IPU_DI1_PIN2,
+   MX53_PAD_EIM_DA12__IPU_DI1_PIN3,
+   MX53_PAD_EIM_A25__IPU_DI1_PIN12,
+   MX53_PAD_EIM_DA10__IPU_DI1_PIN15,
+   };
+
+   imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+}
+
 static void setup_iomux_nand(void)
 {
static const iomux_v3_cfg_t nand_pads[] = {
@@ -269,6 +341,7 @@ int board_early_init_f(void)
setup_iomux_fec();
setup_iomux_i2c();
setup_iomux_nand();
+   setup_iomux_video();
 
m53_set_clock();
 
diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h
index 8c54549..a344af4 100644
--- a/include/configs/m53evk.h
+++ b/include/configs/m53evk.h
@@ -37,6 +37,7 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SATA
 #define CONFIG_CMD_USB
+#define CONFIG_VIDEO
 
 /*
  * Memory configurations
@@ -201,6 +202,21 @@
 #endif
 
 /*
+ * LCD
+ */
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_IPUV3_CLK   2
+#endif
+
+/*
  * Boot Linux
  */
 #define CONFIG_CMDLINE_TAG
-- 
1.8.4.2

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Re: [U-Boot] [PULL] u-boot-atmel/master -> u-boot-arm/master

[Albert ARIBAUD]

Hi Andreas,

On Sun,  1 Dec 2013 22:50:12 +0100, Andreas Bießmann
 wrote:

> Dear Albert Aribaud,
> 
> please pull u-boot-atmel/master into u-boot-arm/master.
> This PR supersedes http://patchwork.ozlabs.org/patch/291044/
> 
> The following changes since commit 56eb3da43fab5990a4b7bc118b76c7cae2ceb140:
> 
>   arm, am335x: update for the siemens boards (2013-11-12 09:53:59 -0500)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-atmel.git master
> 
> for you to fetch changes up to d07e2b598a690d6eb75019b379fc4933affe3d2c:
> 
>   arm: atmel: eb_cpux9k2: config clean up (2013-12-01 22:38:53 +0100)
> 
> 
> Andreas Bießmann (6):
>   video: remove AT91 legacy API from bus_vcxk
>   i2c: switch from AT91 legacy to ATMEL legacy
>   at91sam9m10g45ek: remove unused CONFIG_AT91_LEGACY
>   snapper9260: remove unused AT91_LEGACY
>   net: remove unused CONFIG_AT91_LEGACY
>   at91: remove all occourances of CONFIG_AT91_LEGACY
> 
> Bo Shen (8):
>   arm: atmel: sama5d3: correct the ID for DBGU and PIT
>   arm: at91: pm9261: remove undefined bit in mckr
>   arm: atmel: sama5d3: correct the error define of DIV
>   arm: atmel: sama5d3: the offset of MULA is 18
>   arm: atmel: sama5d3: early enable PIO peripherals
>   arm: atmel: add ddr2 initialization function
>   arm: atmel: sama5d3: spl boot from fat fs SD card
>   arm: atmel: sam9m10g45ek: let CONFIG_SYS_NO_FLASH at proper position
> 
> Heiko Schocher (1):
>   arm926ejs, at91: add common phy_reset function
> 
> Jens Scharsig (BuS Elektronik) (1):
>   arm: atmel: eb_cpux9k2: config clean up
> 
> Wu, Josh (1):
>   ARM: at91: sama5d3: add support for sama5d36 chip
> 
>  arch/arm/cpu/Makefile   |1 +
>  arch/arm/cpu/armv7/Makefile |2 +-
>  arch/arm/cpu/armv7/at91/sama5d3_devices.c   |6 +-
>  arch/arm/cpu/armv7/at91/timer.c |2 +-
>  arch/arm/cpu/at91-common/Makefile   |   12 +++
>  arch/arm/cpu/at91-common/mpddrc.c   |  124 
> +++
>  arch/arm/cpu/at91-common/phy.c  |   57 +++
>  arch/arm/cpu/at91-common/spl.c  |   90 
>  arch/arm/cpu/at91-common/u-boot-spl.lds |   50 +
>  arch/arm/include/asm/arch-at91/at91_common.h|5 +
>  arch/arm/include/asm/arch-at91/at91_pio.h   |   33 --
>  arch/arm/include/asm/arch-at91/at91_pit.h   |   16 ---
>  arch/arm/include/asm/arch-at91/at91_pmc.h   |   59 ++-
>  arch/arm/include/asm/arch-at91/at91_spi.h   |2 +-
>  arch/arm/include/asm/arch-at91/at91_wdt.h   |   21 
>  arch/arm/include/asm/arch-at91/at91cap9.h   |   69 -
>  arch/arm/include/asm/arch-at91/at91sam9_smc.h   |   60 ---
>  arch/arm/include/asm/arch-at91/atmel_mpddrc.h   |  115 +
>  arch/arm/include/asm/arch-at91/sama5d3.h|3 +
>  arch/arm/include/asm/arch-at91/spl.h|   20 
>  board/BuS/vl_ma2sc/vl_ma2sc.c   |   18 +---
>  board/afeb9260/afeb9260.c   |   18 +---
>  board/atmel/at91sam9260ek/at91sam9260ek.c   |   19 +---
>  board/atmel/at91sam9263ek/at91sam9263ek.c   |   19 +---
>  board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c |   19 +---
>  board/atmel/sama5d3xek/sama5d3xek.c |   91 +
>  board/bluewater/snapper9260/snapper9260.c   |   16 +--
>  board/calao/sbc35_a9g20/sbc35_a9g20.c   |   19 +---
>  board/eukrea/cpu9260/cpu9260.c  |   18 +---
>  board/taskit/stamp9g20/stamp9g20.c  |   31 +-
>  doc/README.at91-soc |7 ++
>  drivers/i2c/soft_i2c.c  |2 +-
>  drivers/net/at91_emac.c |9 --
>  drivers/video/bus_vcxk.c|   15 ---
>  include/configs/afeb9260.h  |2 +-
>  include/configs/at91sam9260ek.h |1 +
>  include/configs/at91sam9263ek.h |1 +
>  include/configs/at91sam9m10g45ek.h  |9 +-
>  include/configs/cpu9260.h   |1 +
>  include/configs/eb_cpux9k2.h|4 -
>  include/configs/pm9261.h|6 +-
>  include/configs/sama5d3xek.h|   34 +++
>  include/configs/sbc35_a9g20.h   |1 +
>  include/configs/snapper9260.h   |2 +-
>  include/configs/stamp9g20.h |1 +
>  include/configs/vl_ma2sc.h  |1 +
>  include/i2c.h   |2 +-
>  47 files changed, 655 insertions(+), 458 deletions(-)
>  create mode 100644 arch/arm/cpu/at91-common/Makefile
>  create mode 100644 arch/arm/cpu/at91-common/mpddrc.c
>  create mode 100644 arch/arm/cpu/at

Re: [U-Boot] [PATCH 0/3] OMAP USB host fixes for Beagle & Panda

[Marek Vasut]

Dear Roger Quadros,

> Hi,
> 
> This series
> 
> - Fixes OMAP4 Panda USB device detection issues
> - Gets rid of ULPI reset errors on Beagle & Panda

Is this a V2 or what is this? I already see similar series posted a few days 
ago.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH V2] arm: omap: i2c: don't zero cnt in i2c_write

[Lubomir Popov]

Hi Nikita,

On 28/11/13 18:04, Nikita Kiryanov wrote:

Writing zero into I2Ci.I2C_CNT register causes random I2C failures in OMAP3
based devices. This seems to be related to the following advisory which
apears in multiple erratas for OMAP3 SoCs (OMAP35xx, DM37xx), as well as
OMAP4430 TRM:

Advisory:
I2C Module Does Not Allow 0-Byte Data Requests
Details:
When configured as the master, the I2C module does not allow 0-byte data
transfers. Note: Programming I2Ci.I2C_CNT[15:0]: DCOUNT = 0 will cause
undefined behavior.
Workaround(s):
No workaround. Do not use 0-byte data requests.

The writes in question are unnecessary from a functional point of view.
Most of them are done after I/O has finished, and the only one that preceds
I/O (in i2c_probe()) is also unnecessary because a stop bit is sent before
actual data transmission takes place.

Therefore, remove all writes that zero the cnt register.

Cc: Heiko Schocher 
Cc: Thomas Petazzoni 
Cc: Tom Rini 
Cc: Lubomir Popov 
Cc: Enric Balletbo Serra 
Signed-off-by: Nikita Kiryanov 
---
Changes in V2:  
Removed all instances of writew(0, &i2c_base->cnt) instead of just the
one in i2c_write (following a test of V1 by Thomas Petazzoni).



Tested-by: Lubomir Popov 

In addition to the OMAP5430/32 tests performed last week, tested today
on OMAP4 (4430/60/70) and on AM3359. Thus tests have covered OMAP4/5-
compatible I2C IPs with revnb_lo=[0x000a to 0x000c] (revnb_hi is 0x5040
for all those IPs).

--
Regards,
Lubo

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Re: [U-Boot] Why u-boot relocate from flash to RAM

[FengHua]

> Hi,
> 
> I can't understand that why u-boot code relocate itself form flash to RAM?
> why it doesn't execute from flash?
> Can anybody explain. Plz
> 
First, flash is slow.
Second, there are many data structures or variables which should be writable.
So, we should copy u-boot to RAM and relocate it.






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Re: [U-Boot] why u-boot relocate it self to RAM from flash?

[FengHua]

> Hi,
> 
> I can not understand why u-boot relocate it self to RAM from flash? Why is
> it not executing from flash?
> Can anybody explain.
> 

First, flash is slow.
Second, there are many data structures or variables which should be writable.
So, we should copy u-boot to RAM and relocate it.

Regards





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[U-Boot] [STATUS] Resuming ARM activity

[Albert ARIBAUD]

Hello all,

Apologies for my inactivity for the last fifteen days. I am resuming
fully today, with PRs being applied first, then pending patches. If
anyone wants to draw my attention to some post on the list, just reply
to that post adding my e-mail address as "To:" rather than "Cc:" -- this
will 'red-flag' the message in my mailer).

Amicalement,
-- 
Albert.
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[U-Boot] [PATCH 2/3] omap3_beagle: Don't use ulpi_reset

[Roger Quadros]

Fixes this error message when USB is started.
"ULPI: ulpi_reset: failed writing reset bit"

It is pointless to manually reset the ULPI as the USB Host
Reset and PHY RESET line should take care of that.

Reported-by: Tomi Valkeinen 
Reviewed-by: Stefan Roese 
Signed-off-by: Roger Quadros 
---
 include/configs/omap3_beagle.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 9fcd50b..88b67e7 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -118,9 +118,6 @@
 #define CONFIG_USB_EHCI_OMAP
 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO   147
 
-#define CONFIG_USB_ULPI
-#define CONFIG_USB_ULPI_VIEWPORT_OMAP
-
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_SMSC95XX
-- 
1.8.3.2

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[U-Boot] [PATCH 0/3] OMAP USB host fixes for Beagle & Panda

[Roger Quadros]

Hi,

This series

- Fixes OMAP4 Panda USB device detection issues
- Gets rid of ULPI reset errors on Beagle & Panda

---
cheers,
-roger

Roger Quadros (3):
  usb: ehci-omap: Reset the USB Host OMAP module
  omap3_beagle: Don't use ulpi_reset
  omap4_panda: Don't use ulpi_reset

 drivers/usb/host/ehci-omap.c   | 57 +++---
 include/configs/omap3_beagle.h |  3 ---
 include/configs/omap4_panda.h  |  3 ---
 3 files changed, 42 insertions(+), 21 deletions(-)

-- 
1.8.3.2

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[U-Boot] [PATCH 3/3] omap4_panda: Don't use ulpi_reset

[Roger Quadros]

Fixes this error message when USB is started.
"ULPI: ulpi_reset: failed writing reset bit"

It is pointless to manually reset the ULPI as the USB Host
Reset and PHY RESET line should take care of that.

Reported-by: Tomi Valkeinen 
Reviewed-by: Stefan Roese 
Signed-off-by: Roger Quadros 
---
 include/configs/omap4_panda.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index 8294622..89b1c51 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -36,9 +36,6 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 
-#define CONFIG_USB_ULPI
-#define CONFIG_USB_ULPI_VIEWPORT_OMAP
-
 #include 
 #define CONFIG_CMD_NET
 
-- 
1.8.3.2

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[U-Boot] [PATCH 1/3] usb: ehci-omap: Reset the USB Host OMAP module

[Roger Quadros]

In commit bb1f327 we removed the UHH reset to fix NFS root (over usb
ethernet) problems with Beagleboard (3530 ES1.0). However, this
seems to cause USB detection problems for Pandaboard, about (3/8).

On further investigation, it seems that doing the UHH reset is not
the cause of the original Beagleboard problem, but in the way the reset
was done.

This patch adds proper UHH RESET mechanism for OMAP3 and OMAP4/5 based
on the UHH_REVISION register. This should fix the Beagleboard NFS
problem as well as the Pandaboard USB detection problem.

Reported-by: Tomi Valkeinen 
CC: Stefan Roese 
Reviewed-by: Stefan Roese 
Signed-off-by: Roger Quadros 
---
 drivers/usb/host/ehci-omap.c | 57 
 1 file changed, 42 insertions(+), 15 deletions(-)

diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c
index 3c58f9e..98cea00 100644
--- a/drivers/usb/host/ehci-omap.c
+++ b/drivers/usb/host/ehci-omap.c
@@ -28,21 +28,48 @@ static struct omap_ehci *const ehci = (struct omap_ehci 
*)OMAP_EHCI_BASE;
 
 static int omap_uhh_reset(void)
 {
-/*
- * Soft resetting the UHH module causes instability issues on
- * all OMAPs so we just avoid it.
- *
- * See OMAP36xx Errata
- *  i571: USB host EHCI may stall when entering smart-standby mode
- *  i660: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
- *
- * On OMAP4/5, soft-resetting the UHH module will put it into
- * Smart-Idle mode and lead to a deadlock.
- *
- * On OMAP3, this doesn't seem to be the case but still instabilities
- * are observed on beagle (3530 ES1.0) if soft-reset is used.
- * e.g. NFS root failures with Linux kernel.
- */
+   int timeout = 0;
+   u32 rev;
+
+   rev = readl(&uhh->rev);
+
+   /* Soft RESET */
+   writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc);
+
+   switch (rev) {
+   case OMAP_USBHS_REV1:
+   /* Wait for soft RESET to complete */
+   while (!(readl(&uhh->syss) & 0x1)) {
+   if (timeout > 100) {
+   printf("%s: RESET timeout\n", __func__);
+   return -1;
+   }
+   udelay(10);
+   timeout++;
+   }
+
+   /* Set No-Idle, No-Standby */
+   writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
+   break;
+
+   default:/* Rev. 2 onwards */
+
+   udelay(2); /* Need to wait before accessing SYSCONFIG back */
+
+   /* Wait for soft RESET to complete */
+   while ((readl(&uhh->sysc) & 0x1)) {
+   if (timeout > 100) {
+   printf("%s: RESET timeout\n", __func__);
+   return -1;
+   }
+   udelay(10);
+   timeout++;
+   }
+
+   writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
+   break;
+   }
+
return 0;
 }
 
-- 
1.8.3.2

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Re: [U-Boot] [PATCH V3] exynos: spl: Add a custom spi copy function

[Rajeshwari Birje]

Hi Minkyu Kang,

Thank you for comments.



On Mon, Dec 2, 2013 at 2:18 PM, Minkyu Kang  wrote:
> On 09/10/13 16:55, Rajeshwari Birje wrote:
>> Hi Minkyu Kang,
>>
>> Since this patch is related to arch/arm spi booting, I had a doubt
>> where would it get merged in u-boot-samsung.git or u-boot-spi.git.
>>
>> This patch is based on "[U-Boot] [PATCH 4/4] spi: exynos: Support word
>> transfers" which is already merged in u-boot-spi.git.
>
> Now, that patch is merged to u-boot-samsung.
> Anyway I'm OK to pick this patch to u-boot-spi.
>
>>
>> Regards,
>> Rajeshwari Shinde.
>>
>> On Tue, Oct 8, 2013 at 6:42 PM, Rajeshwari S Shinde
>>  wrote:
>>> This patch implements a custom spi_copy funtion to copy u-boot from SF
>>> to RAM. This is faster then iROM spi_copy funtion as this runs spi at
>>> 50Mhz and also in WORD mode of operation.
>>>
>>> Changed a printf in pinmux.c to debug just to avoid the compilation
>>> error in SPL.
>>>
>>> Signed-off-by: Alim Akhtar 
>>> Signed-off-by: Tom Wai-Hong Tam 
>>> Signed-off-by: Rajeshwari S Shinde 
>>> ---
>>> Based on following patch yet to be merged:
>>> "[U-Boot] [PATCH 4/4] spi: exynos: Support word transfers"
>>> Changes in V2:
>>> - Corrected the commit message.
>>> - Added a SPI timeout check.
>>> - Corrected the comments.
>>> Changes in V3:
>>> - Rebased on the latest u-boot-spi tree.
>>>  arch/arm/cpu/armv7/exynos/pinmux.c |   2 +-
>>>  arch/arm/cpu/armv7/exynos/spl_boot.c   | 122 
>>> -
>>>  arch/arm/include/asm/arch-exynos/spi.h |   1 +
>>>  include/configs/exynos5250-dt.h|   2 +
>>>  4 files changed, 123 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c 
>>> b/arch/arm/cpu/armv7/exynos/pinmux.c
>>> index 8002bce..74cc700 100644
>>> --- a/arch/arm/cpu/armv7/exynos/pinmux.c
>>> +++ b/arch/arm/cpu/armv7/exynos/pinmux.c
>>> @@ -462,7 +462,7 @@ static int exynos4_pinmux_config(int peripheral, int 
>>> flags)
>>> case PERIPH_ID_SDMMC1:
>>> case PERIPH_ID_SDMMC3:
>>> case PERIPH_ID_SDMMC4:
>>> -   printf("SDMMC device %d not implemented\n", peripheral);
>>> +   debug("SDMMC device %d not implemented\n", peripheral);
>
> unrelated change.
>
As mentioned commit message
"Changed a printf in pinmux.c to debug just to avoid the compilation
error in SPL."
>>> return -1;
>>> default:
>>> debug("%s: invalid peripheral %d", __func__, peripheral);
>>> diff --git a/arch/arm/cpu/armv7/exynos/spl_boot.c 
>>> b/arch/arm/cpu/armv7/exynos/spl_boot.c
>>> index 3651c00..6faf13f 100644
>>> --- a/arch/arm/cpu/armv7/exynos/spl_boot.c
>>> +++ b/arch/arm/cpu/armv7/exynos/spl_boot.c
>>> @@ -10,8 +10,11 @@
>>>  #include 
>>>  #include 
>>>  #include 
>>> +#include 
>>> +#include 
>>>  #include 
>>>  #include 
>>> +#include 
>>>
>>>  #include "common_setup.h"
>>>  #include "clock_init.h"
>>> @@ -59,6 +62,119 @@ static int config_branch_prediction(int set_cr_z)
>>>  }
>>>  #endif
>>>
>>> +static void spi_rx_tx(struct exynos_spi *regs, int todo,
>>> +   void *dinp, void const *doutp, int i)
>>> +{
>>> +   uint *rxp = (uint *)(dinp + (i * (32 * 1024)));
>>> +   int rx_lvl, tx_lvl;
>>> +   uint out_bytes, in_bytes;
>>> +
>>> +   out_bytes = todo;
>>> +   in_bytes = todo;
>>> +   setbits_le32(®s->ch_cfg, SPI_CH_RST);
>>> +   clrbits_le32(®s->ch_cfg, SPI_CH_RST);
>>> +   writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
>>> +
>>> +   while (in_bytes) {
>>> +   uint32_t spi_sts;
>>> +   int temp;
>>> +
>>> +   spi_sts = readl(®s->spi_sts);
>>> +   rx_lvl = ((spi_sts >> 15) & 0x7f);
>>> +   tx_lvl = ((spi_sts >> 6) & 0x7f);
>>> +   while (tx_lvl < 32 && out_bytes) {
>>> +   temp = 0x;
>>> +   writel(temp, ®s->tx_data);
>>> +   out_bytes -= 4;
>>> +   tx_lvl += 4;
>>> +   }
>>> +   while (rx_lvl >= 4 && in_bytes) {
>>> +   temp = readl(®s->rx_data);
>>> +   if (rxp)
>>> +   *rxp++ = temp;
>>> +   in_bytes -= 4;
>>> +   rx_lvl -= 4;
>>> +   }
>>> +   }
>>> +}
>>> +
>>> +/*
>>> + * Copy uboot from spi flash to RAM
>>> + *
>>> + * @parma uboot_size   size of u-boot to copy
>>> + * @param uboot_addr   address in u-boot to copy
>>> + */
>>> +static void exynos_spi_copy(unsigned int uboot_size, unsigned int 
>>> uboot_addr)
>>> +{
>>> +   int upto, todo;
>>> +   int i, timeout = 100;
>>> +   struct exynos_spi *regs = (struct exynos_spi *)CONFIG_ENV_SPI_BASE;
>>> +
>>> +   set_spi_clk(PERIPH_ID_SPI1, 5000); /* set spi clock to 50Mhz */
>>> +   /* set the spi1 GPIO */
>>> +   exynos_pinmux_config(PERIPH_ID_SPI1, P

Re: [U-Boot] Compiling a debug version of u-boot on panda board

[Lokesh Vutla]

Hi Vikram,
On Monday 02 December 2013 04:01 PM, Vikram Singh Shekhawat wrote:
> Hi all,
> 
> I want to compile a u-boot with debug enable.But i am getting some problem
> in that.
> 
> I am using omap4460 panda board. When i am enabling DEBUG in config
> file(include/configs/omap4_panda.h). I am getting error that .rodaata not
> fit in region .sram ,  sram overflowed (might be because the size of spl
> image is larger then expected).
> 
> Is there any way to enable DEBUG to whole u-boot source code.
Since you are trying to debug, you can try the following diif:

diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h
index ea56eeb..9e9b955 100644
--- a/include/configs/omap4_common.h
+++ b/include/configs/omap4_common.h
@@ -149,8 +149,8 @@
"fi"
 
 /* Defines for SPL */
-#define CONFIG_SPL_TEXT_BASE   0x40304350
-#define CONFIG_SPL_MAX_SIZE(38 * 1024)
+#define CONFIG_SPL_TEXT_BASE   0x40300350
+#define CONFIG_SPL_MAX_SIZE(0x4030C000 - CONFIG_SPL_TEXT_BASE)
 #define CONFIG_SPL_DISPLAY_PRINT
 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"


This will increase the SPL_MAX_SIZE.

Please let me know if you need more info.

Thanks and regards,
Lokesh
> 
> Waiting for your views on this problem.
> 
> 
> 
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> http://lists.denx.de/mailman/listinfo/u-boot
> 

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[U-Boot] [PATCH v2] trats: usb: Add usb_cable_connected() function

[Przemyslaw Marczak]

Changes:
- define function usb_cable_connected() in trats board file
  which returns 1 if cable is connected and 0 otherwise
- trats.h: add CONFIG_USB_CHECK_CABLE

Changes v2:
- add muic avaibility check

Signed-off-by: Przemyslaw Marczak 
Cc: Minkyu Kang 
---
 board/samsung/trats/trats.c |   11 +++
 include/configs/trats.h |1 +
 2 files changed, 12 insertions(+)

diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index 7012c13..6bd106e 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -501,6 +501,17 @@ int board_usb_init(int index, enum usb_init_type init)
debug("USB_udc_probe\n");
return s3c_udc_probe(&s5pc210_otg_data);
 }
+
+#ifdef CONFIG_USB_CABLE_CHECK
+int usb_cable_connected(void)
+{
+   struct pmic *muic = pmic_get("MAX8997_MUIC");
+   if (!muic)
+   return 0;
+
+   return !!muic->chrg->chrg_type(muic);
+}
+#endif
 #endif
 
 static void pmic_reset(void)
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 3d080c4..8ff9800 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -308,6 +308,7 @@
 #define CONFIG_USB_GADGET_S3C_UDC_OTG
 #define CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_USB_GADGET_VBUS_DRAW2
+#define CONFIG_USB_CABLE_CHECK
 
 /* LCD */
 #define CONFIG_EXYNOS_FB
-- 
1.7.9.5

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[U-Boot] Compiling a debug version of u-boot on panda board

[Vikram Singh Shekhawat]

Hi all,

I want to compile a u-boot with debug enable.But i am getting some problem
in that.

I am using omap4460 panda board. When i am enabling DEBUG in config
file(include/configs/omap4_panda.h). I am getting error that .rodaata not
fit in region .sram ,  sram overflowed (might be because the size of spl
image is larger then expected).

Is there any way to enable DEBUG to whole u-boot source code.

Waiting for your views on this problem.
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Re: [U-Boot] [PATCH V2] arm: omap: i2c: don't zero cnt in i2c_write

[Thomas Petazzoni]

Dear Nikita Kiryanov,

On Thu, 28 Nov 2013 18:04:42 +0200, Nikita Kiryanov wrote:
> Writing zero into I2Ci.I2C_CNT register causes random I2C failures in OMAP3
> based devices. This seems to be related to the following advisory which
> apears in multiple erratas for OMAP3 SoCs (OMAP35xx, DM37xx), as well as
> OMAP4430 TRM:
> 
> Advisory:
> I2C Module Does Not Allow 0-Byte Data Requests
> Details:
> When configured as the master, the I2C module does not allow 0-byte data
> transfers. Note: Programming I2Ci.I2C_CNT[15:0]: DCOUNT = 0 will cause
> undefined behavior.
> Workaround(s):
> No workaround. Do not use 0-byte data requests.
> 
> The writes in question are unnecessary from a functional point of view.
> Most of them are done after I/O has finished, and the only one that preceds
> I/O (in i2c_probe()) is also unnecessary because a stop bit is sent before
> actual data transmission takes place.
> 
> Therefore, remove all writes that zero the cnt register.
> 
> Cc: Heiko Schocher 
> Cc: Thomas Petazzoni 
> Cc: Tom Rini 
> Cc: Lubomir Popov 
> Cc: Enric Balletbo Serra 
> Signed-off-by: Nikita Kiryanov 
> ---
> Changes in V2:
>   Removed all instances of writew(0, &i2c_base->cnt) instead of just the
>   one in i2c_write (following a test of V1 by Thomas Petazzoni).

Tested-by: Thomas Petazzoni 

On IGEPv2, OMAP36XX/37XX-GP ES1.2.

Thanks a lot!

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[U-Boot] [PATCH 7/9 V9] DTS: Add dts support for SMDK5420

[Rajeshwari S Shinde]

This patch adds dts support for SMDK5420.
exynos5.dtsi created is a common file which has the nodes common
to both 5420 and 5250.

Signed-off-by: Akshay Saraswat 
Signed-off-by: Rajeshwari S Shinde 
Acked-by: Simon Glass 
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- Added /include/ "exynos5420.dtsi
Changes in V5:
- None
Changes in V6:
- None
Changes in V7:
- Corrected the license.
Changes in V8:
- None
Changes in V9:
- Reabsed on latest code.
 arch/arm/dts/exynos5.dtsi | 198 ++
 arch/arm/dts/exynos5250.dtsi  | 194 +
 arch/arm/dts/exynos5420.dtsi  |  70 +++
 board/samsung/dts/exynos5420-smdk5420.dts | 169 +
 4 files changed, 441 insertions(+), 190 deletions(-)
 create mode 100644 arch/arm/dts/exynos5.dtsi
 create mode 100644 arch/arm/dts/exynos5420.dtsi
 create mode 100644 board/samsung/dts/exynos5420-smdk5420.dts

diff --git a/arch/arm/dts/exynos5.dtsi b/arch/arm/dts/exynos5.dtsi
new file mode 100644
index 000..f8c8741
--- /dev/null
+++ b/arch/arm/dts/exynos5.dtsi
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2013 The Chromium OS Authors
+ * SAMSUNG EXYNOS5 SoC device tree source
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+   compatible = "samsung,exynos5";
+
+   sromc@1225 {
+   compatible = "samsung,exynos-sromc";
+   reg = <0x1225 0x20>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   i2c@12c6 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "samsung,s3c2440-i2c";
+   reg = <0x12C6 0x100>;
+   interrupts = <0 56 0>;
+   };
+
+   i2c@12c7 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "samsung,s3c2440-i2c";
+   reg = <0x12C7 0x100>;
+   interrupts = <0 57 0>;
+   };
+
+   i2c@12c8 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "samsung,s3c2440-i2c";
+   reg = <0x12C8 0x100>;
+   interrupts = <0 58 0>;
+   };
+
+   i2c@12c9 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "samsung,s3c2440-i2c";
+   reg = <0x12C9 0x100>;
+   interrupts = <0 59 0>;
+   };
+
+   spi@12d2 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "samsung,exynos-spi";
+   reg = <0x12d2 0x30>;
+   interrupts = <0 68 0>;
+   };
+
+   spi@12d3 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "samsung,exynos-spi";
+   reg = <0x12d3 0x30>;
+   interrupts = <0 69 0>;
+   };
+
+   spi@12d4 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "samsung,exynos-spi";
+   reg = <0x12d4 0x30>;
+   clock-frequency = <5000>;
+   interrupts = <0 70 0>;
+};
+
+   spi@131a {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "samsung,exynos-spi";
+   reg = <0x131a 0x30>;
+   interrupts = <0 129 0>;
+   };
+
+   spi@131b {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "samsung,exynos-spi";
+   reg = <0x131b 0x30>;
+   interrupts = <0 130 0>;
+   };
+
+   ehci@1211 {
+   compatible = "samsung,exynos-ehci";
+   reg = <0x1211 0x100>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   phy {
+   compatible = "samsung,exynos-usb-phy";
+   reg = <0x1213 0x100>;
+   };
+   };
+
+   tmu@1006 {
+   compatible = "samsung,exynos-tmu";
+   reg = <0x1006 0x1>;
+   };
+
+   fimd@1440 {
+   compatible = "samsung,exynos-fimd";
+   reg = <0x1440 0x1>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   };
+
+   dp@145b {
+   compatible = "samsung,exynos5-dp";
+   reg = <0x145b 0x1000>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   };
+
+   xhci0: xhci@1200 {
+   compatible = "samsung,exynos5250-xhci";
+   reg = <0x1200 0x1>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   phy {
+  

[U-Boot] [PATCH 5/9 V9] Exynos5420: Add support for 5420 in pinmux and gpio

[Rajeshwari S Shinde]

Adds code in pinmux and gpio framework to support Exynos5420.

Signed-off-by: Naveen Krishna Chatradhi 
Signed-off-by: Akshay Saraswat 
Signed-off-by: Rajeshwari S Shinde 
Acked-by: Simon Glass 
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- Added correct calculation of gpio based addresses.
Changes in V5:
- None
Changes in V6:
- None
Changes in V7:
- Corrected the coding style nits.
Chnages in V8:
- Corrected the coding style nits pointed by Minkyu Kang.
Changes in V9:
- None
 arch/arm/cpu/armv7/exynos/pinmux.c| 260 +-
 arch/arm/include/asm/arch-exynos/gpio.h   | 143 ++--
 arch/arm/include/asm/arch-exynos/periph.h |   3 +
 3 files changed, 390 insertions(+), 16 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c 
b/arch/arm/cpu/armv7/exynos/pinmux.c
index 8002bce..272ecb3 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -46,6 +46,42 @@ static void exynos5_uart_config(int peripheral)
}
 }
 
+static void exynos5420_uart_config(int peripheral)
+{
+   struct exynos5420_gpio_part1 *gpio1 =
+   (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
+   struct s5p_gpio_bank *bank;
+   int i, start, count;
+
+   switch (peripheral) {
+   case PERIPH_ID_UART0:
+   bank = &gpio1->a0;
+   start = 0;
+   count = 4;
+   break;
+   case PERIPH_ID_UART1:
+   bank = &gpio1->a0;
+   start = 4;
+   count = 4;
+   break;
+   case PERIPH_ID_UART2:
+   bank = &gpio1->a1;
+   start = 0;
+   count = 4;
+   break;
+   case PERIPH_ID_UART3:
+   bank = &gpio1->a1;
+   start = 4;
+   count = 2;
+   break;
+   }
+
+   for (i = start; i < start + count; i++) {
+   s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+   s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+   }
+}
+
 static int exynos5_mmc_config(int peripheral, int flags)
 {
struct exynos5_gpio_part1 *gpio1 =
@@ -101,6 +137,75 @@ static int exynos5_mmc_config(int peripheral, int flags)
return 0;
 }
 
+static int exynos5420_mmc_config(int peripheral, int flags)
+{
+   struct exynos5420_gpio_part3 *gpio3 =
+   (struct exynos5420_gpio_part3 *)samsung_get_base_gpio_part3();
+   struct s5p_gpio_bank *bank = NULL, *bank_ext = NULL;
+   int i, start;
+
+   switch (peripheral) {
+   case PERIPH_ID_SDMMC0:
+   bank = &gpio3->c0;
+   bank_ext = &gpio3->c3;
+   start = 0;
+   break;
+   case PERIPH_ID_SDMMC1:
+   bank = &gpio3->c1;
+   bank_ext = &gpio3->d1;
+   start = 4;
+   break;
+   case PERIPH_ID_SDMMC2:
+   bank = &gpio3->c2;
+   bank_ext = NULL;
+   start = 0;
+   break;
+   default:
+   start = 0;
+   debug("%s: invalid peripheral %d", __func__, peripheral);
+   return -1;
+   }
+
+   if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
+   debug("SDMMC device %d does not support 8bit mode",
+ peripheral);
+   return -1;
+   }
+
+   if (flags & PINMUX_FLAG_8BIT_MODE) {
+   for (i = start; i <= (start + 3); i++) {
+   s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x2));
+   s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
+   s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+   }
+   }
+
+   for (i = 0; i < 3; i++) {
+   /*
+* MMC0 is intended to be used for eMMC. The
+* card detect pin is used as a VDDEN signal to
+* power on the eMMC. The 5420 iROM makes
+* this same assumption.
+*/
+   if ((peripheral == PERIPH_ID_SDMMC0) && (i == 2)) {
+   s5p_gpio_set_value(bank, i, 1);
+   s5p_gpio_cfg_pin(bank, i, GPIO_OUTPUT);
+   } else {
+   s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+   }
+   s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+   s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+   }
+
+   for (i = 3; i <= 6; i++) {
+   s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+   s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
+   s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+   }
+
+   return 0;
+}
+
 static void exynos5_sromc_config(int flags)
 {
struct exynos5_gpio_part1 *gpio1 =
@@ -216,6 +321,59 @@ static void exynos5_i2c_config(int peripheral, int flags)
}
 }
 
+static void exynos5420_i2c_config(int perip

[U-Boot] [PATCH 8/9 V9] Config: Add initial config for SMDK5420

[Rajeshwari S Shinde]

Adding initial config for SMDK5420 to build and boot U-Boot
over Exynos based SMDK5420.

Signed-off-by: Rajeshwari S Shinde 
Signed-off-by: Akshay Saraswat 
Acked-by: Simon Glass 
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- Created a common exynos5-dt.h
Changes in V5:
- None
Changes in V6:
- None
Chnages in V7:
- Corrected the coding style nits.
Changes in V8:
- None
Changes in V9:
- Rebased on latest code.
 include/configs/exynos5-dt.h| 289 
 include/configs/exynos5250-dt.h | 283 +--
 include/configs/smdk5420.h  |  50 +++
 3 files changed, 346 insertions(+), 276 deletions(-)
 create mode 100644 include/configs/exynos5-dt.h
 create mode 100644 include/configs/smdk5420.h

diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h
new file mode 100644
index 000..4447ef9
--- /dev/null
+++ b/include/configs/exynos5-dt.h
@@ -0,0 +1,289 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG EXYNOS5 board.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG /* in a SAMSUNG core */
+#define CONFIG_S5P /* S5P Family */
+#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
+
+#include   /* get chip and board defs */
+
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_COMMON
+#define CONFIG_ARCH_EARLY_INIT_R
+#define CONFIG_EXYNOS_SPL
+
+/* Enable fdt support for Exynos5250 */
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* Allow tracing to be enabled */
+#define CONFIG_TRACE
+#define CONFIG_CMD_TRACE
+#define CONFIG_TRACE_BUFFER_SIZE   (16 << 20)
+#define CONFIG_TRACE_EARLY_SIZE(8 << 20)
+#define CONFIG_TRACE_EARLY
+#define CONFIG_TRACE_EARLY_ADDR0x5000
+
+/* Keep L2 Cache Disabled */
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_CACHELINE_SIZE  64
+
+/* Enable ACE acceleration for SHA1 and SHA256 */
+#define CONFIG_EXYNOS_ACE_SHA
+#define CONFIG_SHA_HW_ACCEL
+
+/* input clock of PLL: SMDK5250 has 24MHz input clock */
+#define CONFIG_SYS_CLK_FREQ2400
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+/* Power Down Modes */
+#define S5P_CHECK_SLEEP0x0BAD
+#define S5P_CHECK_DIDLE0xBAD0
+#define S5P_CHECK_LPA  0xABAD
+
+/* Offset for inform registers */
+#define INFORM0_OFFSET 0x800
+#define INFORM1_OFFSET 0x804
+#define INFORM2_OFFSET 0x808
+#define INFORM3_OFFSET 0x80c
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN  (CONFIG_ENV_SIZE + (4 << 20))
+
+/* select serial console configuration */
+#define CONFIG_BAUDRATE115200
+#define EXYNOS5_DEFAULT_UART_OFFSET0x01
+#define CONFIG_SILENT_CONSOLE
+
+/* Enable keyboard */
+#define CONFIG_CROS_EC /* CROS_EC protocol */
+#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */
+#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */
+#define CONFIG_CROS_EC_KEYB/* CROS_EC keyboard input */
+#define CONFIG_CMD_CROS_EC
+#define CONFIG_KEYBOARD
+
+/* Console configuration */
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define EXYNOS_DEVICE_SETTINGS \
+   "stdin=serial,cros-ec-keyb\0" \
+   "stdout=serial,lcd\0" \
+   "stderr=serial,lcd\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+   EXYNOS_DEVICE_SETTINGS
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_S5P_SDHCI
+#define CONFIG_DWMMC
+#define CONFIG_EXYNOS_DWMMC
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* PWM */
+#define CONFIG_PWM
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition*/
+#include 
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_HASH
+
+#define CONFIG_BOOTDELAY   3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+/* Thermal Management Unit */
+#define CONFIG_EXYNOS_TMU
+#define CONFIG_CMD_DTT
+#define CONFIG_TMU_CMD_DTT
+
+/* TPM */
+#define CONFIG_TPM
+#define CONFIG_CMD_TPM
+#define CONFIG_TPM_TIS_I2C
+#define CONFIG_TPM_TIS_I2C_BUS_NUMBER  3
+#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR  0x20
+
+/* MMC SPL */
+#define CONFIG_SPL
+#define COPY_BL2_FNPTR_ADDR0x02020030
+
+#de

[U-Boot] [PATCH 2/9 V9] Exynos5420: Add base addresses for 5420

[Rajeshwari S Shinde]

Adds base addresses of various IPs and controllers required for
Exynos5420.

Signed-off-by: Rajeshwari S Shinde 
Signed-off-by: Akshay Saraswat 
Acked-by: Simon Glass 
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- Added base address for TZPC.
Changes in V5:
- None
Chnages in V6:
- Rebased on latest samsung mainline branch.
Changes in V7:
- Corrected the comments
Changes in V8:
- None
Chnages in V9:
- None
 arch/arm/include/asm/arch-exynos/cpu.h | 49 +-
 1 file changed, 48 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-exynos/cpu.h 
b/arch/arm/include/asm/arch-exynos/cpu.h
index b4ef03e..2b44210 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -92,7 +92,7 @@
 #define EXYNOS4X12_USB_HOST_XHCI_BASE  DEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_USB3PHY_BASEDEVICE_NOT_AVAILABLE
 
-/* EXYNOS5 Common*/
+/* EXYNOS5 */
 #define EXYNOS5_I2C_SPACING0x1
 
 #define EXYNOS5_AUDIOSS_BASE   0x0381
@@ -130,6 +130,46 @@
 #define EXYNOS5_ADC_BASE   DEVICE_NOT_AVAILABLE
 #define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE
 
+/* EXYNOS5420 */
+#define EXYNOS5420_AUDIOSS_BASE0x0381
+#define EXYNOS5420_GPIO_PART5_BASE 0x0386
+#define EXYNOS5420_PRO_ID  0x1000
+#define EXYNOS5420_CLOCK_BASE  0x1001
+#define EXYNOS5420_POWER_BASE  0x1004
+#define EXYNOS5420_SWRESET 0x10040400
+#define EXYNOS5420_SYSREG_BASE 0x1005
+#define EXYNOS5420_TZPC_BASE   0x100E
+#define EXYNOS5420_WATCHDOG_BASE   0x101D
+#define EXYNOS5420_ACE_SFR_BASE0x1083
+#define EXYNOS5420_DMC_PHY_BASE0x10C0
+#define EXYNOS5420_DMC_CTRL_BASE   0x10C2
+#define EXYNOS5420_DMC_TZASC0_BASE 0x10D4
+#define EXYNOS5420_DMC_TZASC1_BASE 0x10D5
+#define EXYNOS5420_USB_HOST_EHCI_BASE  0x1211
+#define EXYNOS5420_MMC_BASE0x1220
+#define EXYNOS5420_SROMC_BASE  0x1225
+#define EXYNOS5420_UART_BASE   0x12C0
+#define EXYNOS5420_I2C_BASE0x12C6
+#define EXYNOS5420_I2C_8910_BASE   0x12E0
+#define EXYNOS5420_SPI_BASE0x12D2
+#define EXYNOS5420_I2S_BASE0x12D6
+#define EXYNOS5420_PWMTIMER_BASE   0x12DD
+#define EXYNOS5420_SPI_ISP_BASE0x131A
+#define EXYNOS5420_GPIO_PART2_BASE 0x1340
+#define EXYNOS5420_GPIO_PART3_BASE 0x1341
+#define EXYNOS5420_GPIO_PART4_BASE 0x1400
+#define EXYNOS5420_GPIO_PART1_BASE 0x1401
+#define EXYNOS5420_MIPI_DSIM_BASE  0x1450
+#define EXYNOS5420_DP_BASE 0x145B
+
+#define EXYNOS5420_USBPHY_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_USBOTG_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_FIMD_BASE   DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_ADC_BASEDEVICE_NOT_AVAILABLE
+#define EXYNOS5420_MODEM_BASE  DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_USB3PHY_BASEDEVICE_NOT_AVAILABLE
+#define EXYNOS5420_USB_HOST_XHCI_BASE  DEVICE_NOT_AVAILABLE
+
 #ifndef __ASSEMBLY__
 #include 
 /* CPU detection macros */
@@ -163,6 +203,10 @@ static inline void s5p_set_cpu_id(void)
/* Exynos5250 */
s5p_cpu_id = 0x5250;
break;
+   case 0x420:
+   /* Exynos5420 */
+   s5p_cpu_id = 0x5420;
+   break;
}
 }
 
@@ -190,6 +234,7 @@ static inline int __attribute__((no_instrument_function)) \
 IS_EXYNOS_TYPE(exynos4210, 0x4210)
 IS_EXYNOS_TYPE(exynos4412, 0x4412)
 IS_EXYNOS_TYPE(exynos5250, 0x5250)
+IS_EXYNOS_TYPE(exynos5420, 0x5420)
 
 #define SAMSUNG_BASE(device, base) \
 static inline unsigned int __attribute__((no_instrument_function)) \
@@ -200,6 +245,8 @@ static inline unsigned int 
__attribute__((no_instrument_function)) \
return EXYNOS4X12_##base;   \
return EXYNOS4_##base;  \
} else if (cpu_is_exynos5()) {  \
+   if (proid_is_exynos5420())  \
+   return EXYNOS5420_##base;   \
return EXYNOS5_##base;  \
}   \
return 0;   \
-- 
1.7.12.4

___
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[U-Boot] [PATCH 6/9 V9] Exynos5420: Add base patch for SMDK5420

[Rajeshwari S Shinde]

Adding the base patch for Exynos based SMDK5420.
This shall enable compilation and basic boot support for
SMDK5420.

Signed-off-by: Rajeshwari S Shinde 
Signed-off-by: Akshay Saraswat 
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- Rebased on latest u-boot-samsung tree.
Changes in V5:
- Removed functions board_eth_init and board_mmc_init
as they were moved to common/board.c
Changes in V6:
- None
Changes in V7:
- added CONFIG_EXYNOS_SPL to build 5420 and 5250  
Changes in V8:
- None
Changes in V9:
- Rebased on latest code.
 board/samsung/common/board.c  |   2 +
 board/samsung/smdk5420/Makefile   |  13 +++
 board/samsung/smdk5420/smdk5420.c | 159 ++
 board/samsung/smdk5420/smdk5420_spl.c |  52 +++
 boards.cfg|   1 +
 include/configs/arndale.h |   1 +
 include/configs/exynos5250-dt.h   |   1 +
 tools/Makefile|   3 +-
 8 files changed, 231 insertions(+), 1 deletion(-)
 create mode 100644 board/samsung/smdk5420/Makefile
 create mode 100644 board/samsung/smdk5420/smdk5420.c
 create mode 100644 board/samsung/smdk5420/smdk5420_spl.c

diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 9ebfc42..2512a59 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -143,6 +143,7 @@ struct cros_ec_dev *board_get_cros_ec_dev(void)
return local.cros_ec_dev;
 }
 
+#ifdef CONFIG_CROS_EC
 static int board_init_cros_ec_devices(const void *blob)
 {
local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev);
@@ -151,6 +152,7 @@ static int board_init_cros_ec_devices(const void *blob)
 
return 0;
 }
+#endif
 
 #if defined(CONFIG_POWER)
 #ifdef CONFIG_POWER_MAX77686
diff --git a/board/samsung/smdk5420/Makefile b/board/samsung/smdk5420/Makefile
new file mode 100644
index 000..c440753
--- /dev/null
+++ b/board/samsung/smdk5420/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright (C) 2013 Samsung Electronics
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+
+obj-y  += smdk5420_spl.o
+
+ifndef CONFIG_SPL_BUILD
+obj-y  += smdk5420.o
+endif
+
diff --git a/board/samsung/smdk5420/smdk5420.c 
b/board/samsung/smdk5420/smdk5420.c
new file mode 100644
index 000..3ad2ad0
--- /dev/null
+++ b/board/samsung/smdk5420/smdk5420.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_USB_EHCI_EXYNOS
+static int board_usb_vbus_init(void)
+{
+   struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
+   samsung_get_base_gpio_part1();
+
+   /* Enable VBUS power switch */
+   s5p_gpio_direction_output(&gpio1->x2, 6, 1);
+
+   /* VBUS turn ON time */
+   mdelay(3);
+
+   return 0;
+}
+#endif
+
+int exynos_init(void)
+{
+#ifdef CONFIG_USB_EHCI_EXYNOS
+   board_usb_vbus_init();
+#endif
+   return 0;
+}
+
+#ifdef CONFIG_LCD
+void cfg_lcd_gpio(void)
+{
+   struct exynos5_gpio_part1 *gpio1 =
+   (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
+
+   /* For Backlight */
+   s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
+   s5p_gpio_set_value(&gpio1->b2, 0, 1);
+
+   /* LCD power on */
+   s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
+   s5p_gpio_set_value(&gpio1->x1, 5, 1);
+
+   /* Set Hotplug detect for DP */
+   s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
+}
+
+vidinfo_t panel_info = {
+   .vl_freq= 60,
+   .vl_col = 2560,
+   .vl_row = 1600,
+   .vl_width   = 2560,
+   .vl_height  = 1600,
+   .vl_clkp= CONFIG_SYS_LOW,
+   .vl_hsp = CONFIG_SYS_LOW,
+   .vl_vsp = CONFIG_SYS_LOW,
+   .vl_dp  = CONFIG_SYS_LOW,
+   .vl_bpix= 4,/* LCD_BPP = 2^4, for output conosle on LCD */
+
+   /* wDP panel timing infomation */
+   .vl_hspw= 32,
+   .vl_hbpd= 80,
+   .vl_hfpd= 48,
+
+   .vl_vspw= 6,
+   .vl_vbpd= 37,
+   .vl_vfpd= 3,
+   .vl_cmd_allow_len = 0xf,
+
+   .win_id = 3,
+   .cfg_gpio   = cfg_lcd_gpio,
+   .backlight_on   = NULL,
+   .lcd_power_on   = NULL,
+   .reset_lcd  = NULL,
+   .dual_lcd_enabled = 0,
+
+   .init_delay = 0,
+   .power_on_delay = 0,
+   .reset_delay= 0,
+   .interface_mode = FIMD_RGB_INTERFACE,
+   .dp_enabled = 1,
+};
+
+static struct edp_device_info edp_info = {
+   .disp_info = {
+   .h_res = 2560,
+   .h_sync_width = 32,
+   .h_back_porch = 80,
+   .h_front_porch = 48,
+

[U-Boot] [PATCH 9/9 V9] SPL: EXYNOS: Prepare for variable size SPL support

[Rajeshwari S Shinde]

When variable size SPL is used, the BL1 expects the SPL to be
encapsulated differently: instead of putting the checksum at a fixed
offset in the SPL blob, prepend the blob with a header including the
size and the checksum.

The enhancements include
- adding a command line option, '--vs' to indicate the need for the
variable size encapsulation
- padding the fixed size encapsulated blob with 0xff instead of random
memory contents
- do not silently truncate the input file, report error instead
- no need to explicitly closing files/freeing memory, this all happens
on exit; removing cleanups it makes code clearer
- profuse commenting
- modify Makefile to allow enabling the new feature per board

Signed-off-by: Vadim Bendebury 
Signed-off-by: Rajeshwari S Shinde 
Acked-by: Simon Glass 
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- Created a common exynos5-dt.h
Changes in V5:
- None
Changes in V6:
- None.
Changes in V7:
- None.
Changes in V8:
- None
Changes in V9:
- Rebased on latest code.
 include/configs/smdk5420.h |   6 ++
 spl/Makefile   |   7 +-
 tools/mkexynosspl.c| 167 +
 3 files changed, 136 insertions(+), 44 deletions(-)

diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h
index 9eab7d6..447f8e5 100644
--- a/include/configs/smdk5420.h
+++ b/include/configs/smdk5420.h
@@ -19,6 +19,8 @@
 
 #define CONFIG_ARCH_DEVICE_TREEexynos5420
 
+#define CONFIG_VAR_SIZE_SPL
+
 #define CONFIG_SYS_SDRAM_BASE  0x2000
 #define CONFIG_SYS_TEXT_BASE   0x23E0
 
@@ -31,7 +33,11 @@
 /* select serial console configuration */
 #define CONFIG_SERIAL3 /* use SERIAL 3 */
 
+#ifdef CONFIG_VAR_SIZE_SPL
+#define CONFIG_SPL_TEXT_BASE   0x02024410
+#else
 #define CONFIG_SPL_TEXT_BASE   0x02024400
+#endif
 
 #define CONFIG_BOOTCOMMAND "mmc read 20007000 451 2000; bootm 20007000"
 
diff --git a/spl/Makefile b/spl/Makefile
index cbd3d27..9eedbdd 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -174,8 +174,13 @@ endif
 all:   $(ALL-y)
 
 ifdef CONFIG_SAMSUNG
+ifdef CONFIG_VAR_SIZE_SPL
+VAR_SIZE_PARAM = --vs
+else
+VAR_SIZE_PARAM =
+endif
 $(obj)$(BOARD)-spl.bin: $(obj)u-boot-spl.bin
-   $(OBJTREE)/tools/mk$(BOARD)spl \
+   $(OBJTREE)/tools/mk$(BOARD)spl $(VAR_SIZE_PARAM) \
$(obj)u-boot-spl.bin $(obj)$(BOARD)-spl.bin
 endif
 
diff --git a/tools/mkexynosspl.c b/tools/mkexynosspl.c
index ef685b7..32b786c 100644
--- a/tools/mkexynosspl.c
+++ b/tools/mkexynosspl.c
@@ -14,93 +14,174 @@
 #include 
 
 #define CHECKSUM_OFFSET(14*1024-4)
-#define BUFSIZE(14*1024)
 #define FILE_PERM  (S_IRUSR | S_IWUSR | S_IRGRP \
| S_IWGRP | S_IROTH | S_IWOTH)
 /*
-* Requirement:
-* IROM code reads first 14K bytes from boot device.
-* It then calculates the checksum of 14K-4 bytes and compare with data at
-* 14K-4 offset.
-*
-* This function takes two filenames:
-* IN  "u-boot-spl.bin" and
-* OUT "$(BOARD)-spl.bin as filenames.
-* It reads the "u-boot-spl.bin" in 16K buffer.
-* It calculates checksum of 14K-4 Bytes and stores at 14K-4 offset in buffer.
-* It writes the buffer to "$(BOARD)-spl.bin" file.
-*/
+ * Requirement for the fixed size SPL header:
+ * IROM code reads first (CHECKSUM_OFFSET + 4) bytes from boot device. It then
+ * calculates the checksum of CHECKSUM_OFFSET bytes and compares with data at
+ * CHECKSUM_OFFSET location.
+ *
+ * Requirement for the variable size SPL header:
+
+ * IROM code reads the below header to find out the size of the blob (total
+ * size, header size included) and its checksum. Then it reads the rest of the
+ * blob [i.e size - sizeof(struct var_size_header) bytes], calculates the
+ * checksum and compares it with value read from the header.
+ */
+struct var_size_header {
+   uint32_t spl_size;
+   uint32_t spl_checksum;
+   uint32_t reserved[2];
+};
+
+static const char *prog_name;
+
+static void write_to_file(int ofd, void *buffer, int size)
+{
+   if (write(ofd, buffer, size) == size)
+   return;
+
+   fprintf(stderr, "%s: Failed to write to output file: %s\n",
+   prog_name, strerror(errno));
+   exit(EXIT_FAILURE);
+}
 
+/*
+ * The argv is expected to include one optional parameter and two filenames:
+ * [--vs] IN OUT
+ *
+ * --vs - turns on the variable size SPL mode
+ * IN  - the u-boot SPL binary, usually u-boot-spl.bin
+ * OUT - the prepared SPL blob, usually ${BOARD}-spl.bin
+ *
+ * This utility first reads the "u-boot-spl.bin" into a buffer. In case of
+ * fixed size SPL the buffer size is exactly CHECKSUM_OFFSET (such that
+ * smaller u-boot-spl.bin gets padded with 0xff bytes, the larger than limit
+ * u-boot-spl.bin causes an error). For variable size SPL the buff

[U-Boot] [PATCH 1/9 V9] EXYNOS5: Create a common board file

[Rajeshwari S Shinde]

Create a common board.c file for all functions which are common across
all EXYNOS5 platforms.

exynos_init function is provided for platform specific code.

Signed-off-by: Rajeshwari S Shinde 
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- Added check for the compilation of MAX77686 pmic.
Changes in V5:
- Moved board_eth_init and board_mmc_init in case of
device tree support
Changes in V6:
- None.
Changes in V7:
- None
Changes in V8:
- None
Changes in V9:
- Reabsed on latest code.
 arch/arm/include/asm/arch-exynos/board.h |  17 ++
 board/samsung/common/Makefile|   5 +
 board/samsung/common/board.c | 405 +++
 board/samsung/smdk5250/exynos5-dt.c  | 352 +--
 board/samsung/smdk5250/smdk5250.c| 182 +-
 include/configs/exynos5250-dt.h  |   2 +
 6 files changed, 434 insertions(+), 529 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-exynos/board.h
 create mode 100644 board/samsung/common/board.c

diff --git a/arch/arm/include/asm/arch-exynos/board.h 
b/arch/arm/include/asm/arch-exynos/board.h
new file mode 100644
index 000..243fb12
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/board.h
@@ -0,0 +1,17 @@
+/*
+ * (C) Copyright 2013 Samsung Electronics
+ * Rajeshwari Shinde 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _EXYNOS_BOARD_H
+#define _EXYNOS_BOARD_H
+
+/*
+ * Exynos baord specific changes for
+ * board_init
+ */
+int exynos_init(void);
+
+#endif /* EXYNOS_BOARD_H */
diff --git a/board/samsung/common/Makefile b/board/samsung/common/Makefile
index 501d974..efbf9ae 100644
--- a/board/samsung/common/Makefile
+++ b/board/samsung/common/Makefile
@@ -8,3 +8,8 @@
 obj-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o
 obj-$(CONFIG_THOR_FUNCTION) += thor.o
 obj-$(CONFIG_CMD_USB_MASS_STORAGE) += ums.o
+
+ifeq ($(CONFIG_SPL_BUILD),)
+COBJS-$(CONFIG_BOARD_COMMON)   += board.o
+endif
+
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
new file mode 100644
index 000..9ebfc42
--- /dev/null
+++ b/board/samsung/common/board.c
@@ -0,0 +1,405 @@
+/*
+ * (C) Copyright 2013 SAMSUNG Electronics
+ * Rajeshwari Shinde 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct local_info {
+   struct cros_ec_dev *cros_ec_dev;/* Pointer to cros_ec device */
+   int cros_ec_err;/* Error for cros_ec, 0 if ok */
+};
+
+static struct local_info local;
+
+#if defined CONFIG_EXYNOS_TMU
+/*
+ * Boot Time Thermal Analysis for SoC temperature threshold breach
+ */
+static void boot_temp_check(void)
+{
+   int temp;
+
+   switch (tmu_monitor(&temp)) {
+   case TMU_STATUS_NORMAL:
+   break;
+   /* Status TRIPPED ans WARNING means corresponding threshold breach */
+   case TMU_STATUS_TRIPPED:
+   puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
+   set_ps_hold_ctrl();
+   hang();
+   break;
+   case TMU_STATUS_WARNING:
+   puts("EXYNOS_TMU: WARNING! Temperature very high\n");
+   break;
+   /*
+* TMU_STATUS_INIT means something is wrong with temperature sensing
+* and TMU status was changed back from NORMAL to INIT.
+*/
+   case TMU_STATUS_INIT:
+   default:
+   debug("EXYNOS_TMU: Unknown TMU state\n");
+   }
+}
+#endif
+
+int board_init(void)
+{
+   gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+#if defined CONFIG_EXYNOS_TMU
+   if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
+   debug("%s: Failed to init TMU\n", __func__);
+   return -1;
+   }
+   boot_temp_check();
+#endif
+
+#ifdef CONFIG_EXYNOS_SPI
+   spi_init();
+#endif
+   return exynos_init();
+}
+
+int dram_init(void)
+{
+   int i;
+   u32 addr;
+
+   for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+   addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+   gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+   }
+   return 0;
+}
+
+void dram_init_banksize(void)
+{
+   int i;
+   u32 addr, size;
+
+   for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+   addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+   size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+
+   gd->bd->bi_dram[i].start = addr;
+   gd->bd->bi_dram[i].size = size;
+   }
+}
+
+static int board_uart_init(void)
+{
+   int err, uart_id, ret = 0;
+
+   for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
+   err = exynos_pinmux_co

[U-Boot] [PATCH 4/9 V9] Exynos5420: Add DDR3 initialization for 5420

[Rajeshwari S Shinde]

This patch intends to add DDR3 initialization code for Exynos5420.

Signed-off-by: Rajeshwari S Shinde 
Signed-off-by: Akshay Saraswat 
Acked-by: Simon Glass 
---
Changes in V2:
- Corrected a compilation issue for SMDK5250.
Changes in V3:
- None
Changes in V4:
- None
Changes in V5:
- None
Changes in V6:
- None
Changes in V7:
- Fixed multi line comment.
Changes in V8:
- None
Changes in V9:
- Used samsung_get base to get the dmc base address
 arch/arm/cpu/armv7/exynos/dmc_common.c|  10 +-
 arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 425 +-
 arch/arm/cpu/armv7/exynos/exynos5_setup.h |   2 +
 arch/arm/include/asm/arch-exynos/cpu.h|   4 +
 arch/arm/include/asm/arch-exynos/dmc.h| 123 ++---
 arch/arm/include/asm/arch-exynos/power.h  |   6 +
 6 files changed, 525 insertions(+), 45 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/dmc_common.c 
b/arch/arm/cpu/armv7/exynos/dmc_common.c
index 53cfe6e..9e432c2 100644
--- a/arch/arm/cpu/armv7/exynos/dmc_common.c
+++ b/arch/arm/cpu/armv7/exynos/dmc_common.c
@@ -1,5 +1,5 @@
 /*
- * Mem setup common file for different types of DDR present on SMDK5250 boards.
+ * Mem setup common file for different types of DDR present on Exynos boards.
  *
  * Copyright (C) 2012 Samsung Electronics
  *
@@ -152,14 +152,6 @@ void dmc_config_prech(struct mem_timings *mem, struct 
exynos5_dmc *dmc)
}
 }
 
-void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc)
-{
-   writel(mem->memconfig, &dmc->memconfig0);
-   writel(mem->memconfig, &dmc->memconfig1);
-   writel(DMC_MEMBASECONFIG0_VAL, &dmc->membaseconfig0);
-   writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1);
-}
-
 void mem_ctrl_init(int reset)
 {
struct spl_machine_param *param = spl_get_machine_params();
diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c 
b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
index 5f5914e..aa46a43 100644
--- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
+++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
@@ -1,5 +1,5 @@
 /*
- * DDR3 mem setup file for SMDK5250 board based on EXYNOS5
+ * DDR3 mem setup file for board based on EXYNOS5
  *
  * Copyright (C) 2012 Samsung Electronics
  *
@@ -11,12 +11,14 @@
 #include 
 #include 
 #include 
+#include 
 #include "common_setup.h"
 #include "exynos5_setup.h"
 #include "clock_init.h"
 
-#define RDLVL_COMPLETE_TIMEOUT 1
+#define TIMEOUT1
 
+#ifdef CONFIG_EXYNOS5250
 static void reset_phy_ctrl(void)
 {
struct exynos5_clock *clk =
@@ -108,7 +110,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned 
long mem_iv_size,
 
/* Precharge Configuration */
writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
-  &dmc->prechconfig);
+  &dmc->prechconfig0);
 
/* Power Down mode Configuration */
writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |
@@ -174,7 +176,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned 
long mem_iv_size,
writel(val, &phy1_ctrl->phy_con1);
 
writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config);
-   i = RDLVL_COMPLETE_TIMEOUT;
+   i = TIMEOUT;
while ((readl(&dmc->phystatus) &
(RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) !=
(RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) {
@@ -215,3 +217,418 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned 
long mem_iv_size,
| (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol);
return 0;
 }
+#endif
+
+#ifdef CONFIG_EXYNOS5420
+int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
+  int reset)
+{
+   struct exynos5420_clock *clk =
+   (struct exynos5420_clock *)samsung_get_base_clock();
+   struct exynos5_power *power =
+   (struct exynos5_power *)samsung_get_base_power();
+   struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
+   struct exynos5_dmc *drex0, *drex1;
+   struct exynos5_tzasc *tzasc0, *tzasc1;
+   uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1;
+   int chip;
+   int i;
+
+   phy0_ctrl = (struct exynos5_phy_control *)samsung_get_base_dmc_phy();
+   phy1_ctrl = (struct exynos5_phy_control *)(samsung_get_base_dmc_phy()
+   + DMC_OFFSET);
+   drex0 = (struct exynos5_dmc *)samsung_get_base_dmc_ctrl();
+   drex1 = (struct exynos5_dmc *)(samsung_get_base_dmc_ctrl()
+   + DMC_OFFSET);
+   tzasc0 = (struct exynos5_tzasc *)samsung_get_base_dmc_tzasc0();
+   tzasc1 = (struct exynos5_tzasc *)(samsung_get_base_dmc_tzasc0()
+   + DMC_OFFSET);
+
+   /* Enable PAUSE for DREX */
+   setbits_le32(&clk->pause, ENABLE_BI

[U-Boot] [PATCH 0/9 V9] EXYNOS5420: Add SMDK5420 board support

[Rajeshwari S Shinde]

This patch adds basic board support for SMDK5420 board.
These patches are tested for booting fine on EVT1 SMDK5420.

Changes in V2:
- Corrected a compilation issue for SMDK5420.

Changes in V3:
- Add patch to support variable size SPL support
- Add patch to disable SMU for eMMC.

Changes in V4:
- Added check for MAX77686 pmic compilation.
- Added correct calculation of gpio based addresses.
- Rebased on the latest u-boot code.
- Removed patches for UART and TZPC changes as
they were not needed.
- Added flag to disable SMU for eMMC.

Changes in V5:
- Moved functions board_mmc_init and board_eth_init 
to common/board.c in case of device tree support.

Changes in V6:
- Rebased on the latest mainline branch.
- Moved the definitions for SMU to arch/arm dwmmc.h

Changes in V7:
- Removed below patch as it is already merged
"DWMMC: SMDK5420: Disable SMU for eMMC"
- Corrected the multi line comments and removal of
blank spaces and lines.
- Corrected the license.

Changes in V8:
- corrected the if loops with if conditions of
pro_id and cpu_id.

Changes in V9:
- Added macros to get the base address
- Rebased on latest code.

Rajeshwari S Shinde (9):
  EXYNOS5: Create a common board file
  Exynos5420: Add base addresses for 5420
  Exynos5420: Add clock initialization for 5420
  Exynos5420: Add DDR3 initialization for 5420
  Exynos5420: Add support for 5420 in pinmux and gpio
  Exynos5420: Add base patch for SMDK5420
  DTS: Add dts support for SMDK5420
  Config: Add initial config for SMDK5420
  SPL: EXYNOS: Prepare for variable size SPL support

 arch/arm/cpu/armv7/exynos/clock.c  | 258 -
 arch/arm/cpu/armv7/exynos/clock_init.h |  17 +
 arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 352 +++-
 arch/arm/cpu/armv7/exynos/dmc_common.c |  10 +-
 arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c  | 425 +-
 arch/arm/cpu/armv7/exynos/exynos5_setup.h  | 740 +++--
 arch/arm/cpu/armv7/exynos/pinmux.c | 260 -
 arch/arm/dts/exynos5.dtsi  | 198 +++
 arch/arm/dts/exynos5250.dtsi   | 194 +--
 arch/arm/dts/exynos5420.dtsi   |  70 +++
 arch/arm/include/asm/arch-exynos/board.h   |  17 +
 arch/arm/include/asm/arch-exynos/clk.h |   1 +
 arch/arm/include/asm/arch-exynos/clock.h   | 494 +
 arch/arm/include/asm/arch-exynos/cpu.h |  53 +-
 arch/arm/include/asm/arch-exynos/dmc.h | 123 ++--
 arch/arm/include/asm/arch-exynos/gpio.h| 143 -
 arch/arm/include/asm/arch-exynos/periph.h  |   3 +
 arch/arm/include/asm/arch-exynos/power.h   |   6 +
 board/samsung/common/Makefile  |   5 +
 board/samsung/common/board.c   | 407 ++
 board/samsung/dts/exynos5420-smdk5420.dts  | 169 ++
 board/samsung/smdk5250/exynos5-dt.c| 352 +---
 board/samsung/smdk5250/smdk5250.c  | 182 +-
 board/samsung/smdk5420/Makefile|  13 +
 board/samsung/smdk5420/smdk5420.c  | 159 ++
 board/samsung/smdk5420/smdk5420_spl.c  |  52 ++
 boards.cfg |   1 +
 include/configs/arndale.h  |   1 +
 include/configs/exynos5-dt.h   | 289 ++
 include/configs/exynos5250-dt.h| 280 +-
 include/configs/smdk5420.h |  56 ++
 spl/Makefile   |   7 +-
 tools/Makefile |   3 +-
 tools/mkexynosspl.c| 167 --
 34 files changed, 4207 insertions(+), 1300 deletions(-)
 create mode 100644 arch/arm/dts/exynos5.dtsi
 create mode 100644 arch/arm/dts/exynos5420.dtsi
 create mode 100644 arch/arm/include/asm/arch-exynos/board.h
 create mode 100644 board/samsung/common/board.c
 create mode 100644 board/samsung/dts/exynos5420-smdk5420.dts
 create mode 100644 board/samsung/smdk5420/Makefile
 create mode 100644 board/samsung/smdk5420/smdk5420.c
 create mode 100644 board/samsung/smdk5420/smdk5420_spl.c
 create mode 100644 include/configs/exynos5-dt.h
 create mode 100644 include/configs/smdk5420.h

-- 
1.7.12.4

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Re: [U-Boot] [PATCH v3 4/4] cmd_eeprom: bug fix for i2c read/write

[Alexey Brodkin]

On Mon, 2013-12-02 at 16:02 +0800, Kuo-Jung Su wrote:
> From: Kuo-Jung Su 

> diff --git a/common/cmd_eeprom.c b/common/cmd_eeprom.c
> index 02539c4..3924805 100644
> --- a/common/cmd_eeprom.c
> +++ b/common/cmd_eeprom.c
> @@ -161,7 +161,7 @@ int eeprom_read (unsigned dev_addr, unsigned offset, 
> uchar *buffer, unsigned cnt
>  #if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
>   spi_read (addr, alen, buffer, len);
>  #else
> - if (i2c_read (addr[0], addr[1], alen-1, buffer, len) != 0)
> + if (i2c_read(addr[0], offset, alen - 1, buffer, len))
>   rcode = 1;
>  #endif
>   buffer += len;

I think this change is whether incomplete or improper.
Let's look at source code above line 161:
=
 125 #if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
 126 uchar addr[2];
 127 
 128 blk_off = offset & 0xFF;/* block offset */
 129 
 130 addr[0] = offset >> 8;  /* block number */
 131 addr[1] = blk_off;  /* block offset */
 132 alen= 2;
 133 #else
 134 uchar addr[3];
 135 
 136 blk_off = offset & 0xFF;/* block offset */
 137 
 138 addr[0] = offset >> 16; /* block number */
 139 addr[1] = offset >>  8; /* upper address
octet */
 140 addr[2] = blk_off;  /* lower address
octet */
 141 alen= 3;
 142 #endif  /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
 143 
 144 addr[0] |= dev_addr;/* insert device
address */
=

>From these line you see that "addr[0]" is set like this:
===
If "CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1":
addr[0] = offset >> 8;

If "CONFIG_SYS_I2C_EEPROM_ADDR_LEN > 1":
addr[0] = offset >> 16;

And in both cases then OR with "dev_addr":
addr[0] |= dev_addr;
===

In other words it gets both real I2S slave address + MSB bits of offset.
But note that "offset" value stays unchanged.

So if you pass both "addr[0]" (which already has MSB bits of "offset")
and "offset" itself then you'll get completely incorrect I2C command.

> @@ -339,7 +339,7 @@ int eeprom_write (unsigned dev_addr, unsigned offset, 
> uchar *buffer, unsigned cn
>   /* Write is enabled ... now write eeprom value.
>*/
>  #endif
> - if (i2c_write (addr[0], addr[1], alen-1, buffer, len) != 0)
> + if (i2c_write(addr[0], offset, alen - 1, buffer, len))
>   rcode = 1;
> 
>  #endif

Same goes to "eeprom_write".

Moreover I'd say that this address/offset tricks are very
EEPROM-specific and because of this we'd better keep it here and don't
modify generic I2C code.

Regards,
Alexey

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Re: [U-Boot] [PATCH v2] dwmmc: make driver usable for non-exynos platforms

[Alexey Brodkin]

On Mon, 2013-12-02 at 14:45 +0900, Jaehoon Chung wrote:
> Hi, Rajeshwari
> 
> It didn't need to include this patch.
> 
> Best Regards,
> Jaehoon Chung

Agree, there's no need in this particular patch any more.
Jaehoon Chung did appropriate changes in dwmmc driver.

Thanks for collaboration.

-Alexey
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[U-Boot] Zynq serial - pull request

[Michal Simek]

Hi Tom,

this is one pending patch which is around for a while and hasn't been merged 
yet.
Please add it to your tree.

Thanks,
Michal

The following changes since commit d19ad726bcd5d9106f7ba9c750462fcc369f1020:

  Prepare v2014.01-rc1 (2013-11-25 16:49:32 -0500)

are available in the git repository at:

  git://www.denx.de/git/u-boot-microblaze.git serial

for you to fetch changes up to 2785a4ae76330dab5e792d52fc9c449ac3d1072e:

  serial: zynq: Remove unused #defines (2013-12-02 11:36:36 +0100)


Soren Brinkmann (1):
  serial: zynq: Remove unused #defines

 drivers/serial/serial_zynq.c | 4 
 1 file changed, 4 deletions(-)


-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform




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Re: [U-Boot] [PATCH 0/2] Add usb eth support

[Chander Kashyap]

Ping

On 19 November 2013 11:09, Chander Kashyap  wrote:
> Ping..
>
> On 19 October 2013 12:19, Inderpal Singh  wrote:
>> From: Chander Kashyap 
>>
>> Arndale board has AX88760, which is USB 2.0 Hub & USB 2.0 Ethernet Combo
>> controller, connected to HSIC Phy of USB host controller via USB3503 hub.
>>
>> This patchset add support for this usb ethernet controllor.
>>
>> Chander Kashyap (1):
>>   exynos5: arndale: Add network support
>>
>> Inderpal Singh (1):
>>   usb: ehci: exynos: set/reset hsic phys
>>
>>  arch/arm/include/asm/arch-exynos/ehci.h |   14 +
>>  board/samsung/arndale/arndale.c |   23 +++
>>  drivers/usb/host/ehci-exynos.c  |   48 
>> +++
>>  include/configs/arndale.h   |6 
>>  4 files changed, 91 insertions(+)
>>
>> --
>> 1.7.9.5
>>
>
>
>
> --
> with warm regards,
> Chander Kashyap



-- 
with warm regards,
Chander Kashyap
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Re: [U-Boot] [PATCH] mmc: dw_mmc: remove the exynos specific code in dw-mmc.c

[Minkyu Kang]

On 29/11/13 21:01, Pantelis Antoniou wrote:
> Hi Jaehoon,
> 
> Looks good
> 
> On Nov 29, 2013, at 1:08 PM, Jaehoon Chung wrote:
> 
>> dw-mmc.c is the general driver file.
>> So, remove the exynos specific code at dw-mmc.c.
>> Instead, exynos specific cod can be move into exynos-dw_mmc.c.
>>
>> Signed-off-by: Jaehoon Chung 
>> ---
>> drivers/mmc/dw_mmc.c|   12 ++--
>> drivers/mmc/exynos_dw_mmc.c |   14 ++
>> include/dwmmc.h |1 +
>> 3 files changed, 17 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
>> index 1e0f72b..38f50ce 100644
>> --- a/drivers/mmc/dw_mmc.c
>> +++ b/drivers/mmc/dw_mmc.c
>> @@ -11,7 +11,6 @@
>> #include 
>> #include 
>> #include 
>> -#include 
>>
>> #define PAGE_SIZE 4096
>>
>> @@ -302,15 +301,8 @@ static int dwmci_init(struct mmc *mmc)
>>  struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
>>  u32 fifo_size;
>>
>> -if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
>> -dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
>> -dwmci_writel(host, EMMCP_SEND0, 0);
>> -dwmci_writel(host, EMMCP_CTRL0,
>> - MPSCTRL_SECURE_READ_BIT |
>> - MPSCTRL_SECURE_WRITE_BIT |
>> - MPSCTRL_NON_SECURE_READ_BIT |
>> - MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
>> -}
>> +if (host->board_init)
>> +host->board_init(host);
>>
>>  dwmci_writel(host, DWMCI_PWREN, 1);
>>
>> diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
>> index a0f1511..b3e5c5e 100644
>> --- a/drivers/mmc/exynos_dw_mmc.c
>> +++ b/drivers/mmc/exynos_dw_mmc.c
>> @@ -34,6 +34,19 @@ unsigned int exynos_dwmci_get_clk(int dev_index)
>>  return get_mmc_clk(dev_index);
>> }
>>
>> +static void exynos_dwmci_board_init(struct dwmci_host *host)
>> +{
>> +if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
>> +dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
>> +dwmci_writel(host, EMMCP_SEND0, 0);
>> +dwmci_writel(host, EMMCP_CTRL0,
>> + MPSCTRL_SECURE_READ_BIT |
>> + MPSCTRL_SECURE_WRITE_BIT |
>> + MPSCTRL_NON_SECURE_READ_BIT |
>> + MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
>> +}
>> +}
>> +
>> /*
>>  * This function adds the mmc channel to be registered with mmc core.
>>  * index -   mmc channel number.
>> @@ -65,6 +78,7 @@ int exynos_dwmci_add_port(int index, u32 regbase, int 
>> bus_width, u32 clksel)
>> #ifdef CONFIG_EXYNOS5420
>>  host->quirks = DWMCI_QUIRK_DISABLE_SMU;
>> #endif
>> +host->board_init = exynos_dwmci_board_init;
>>
>>  if (clksel) {
>>  host->clksel_val = clksel;
>> diff --git a/include/dwmmc.h b/include/dwmmc.h
>> index 6c91143..a02dd67 100644
>> --- a/include/dwmmc.h
>> +++ b/include/dwmmc.h
>> @@ -141,6 +141,7 @@ struct dwmci_host {
>>  struct mmc *mmc;
>>
>>  void (*clksel)(struct dwmci_host *host);
>> +void (*board_init)(struct dwmci_host *host);
>>  unsigned int (*get_mmc_clk)(int dev_index);
>> };
>>
>> -- 
>> 1.7.9.5
> 
> Acked-by: Pantelis Antoniou 
> 

Acked-by: Minkyu Kang 

Thanks,
Minkyu Kang.
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Re: [U-Boot] [PATCH V3] exynos: spl: Add a custom spi copy function

[Minkyu Kang]

On 09/10/13 16:55, Rajeshwari Birje wrote:
> Hi Minkyu Kang,
> 
> Since this patch is related to arch/arm spi booting, I had a doubt
> where would it get merged in u-boot-samsung.git or u-boot-spi.git.
> 
> This patch is based on "[U-Boot] [PATCH 4/4] spi: exynos: Support word
> transfers" which is already merged in u-boot-spi.git.

Now, that patch is merged to u-boot-samsung.
Anyway I'm OK to pick this patch to u-boot-spi.

> 
> Regards,
> Rajeshwari Shinde.
> 
> On Tue, Oct 8, 2013 at 6:42 PM, Rajeshwari S Shinde
>  wrote:
>> This patch implements a custom spi_copy funtion to copy u-boot from SF
>> to RAM. This is faster then iROM spi_copy funtion as this runs spi at
>> 50Mhz and also in WORD mode of operation.
>>
>> Changed a printf in pinmux.c to debug just to avoid the compilation
>> error in SPL.
>>
>> Signed-off-by: Alim Akhtar 
>> Signed-off-by: Tom Wai-Hong Tam 
>> Signed-off-by: Rajeshwari S Shinde 
>> ---
>> Based on following patch yet to be merged:
>> "[U-Boot] [PATCH 4/4] spi: exynos: Support word transfers"
>> Changes in V2:
>> - Corrected the commit message.
>> - Added a SPI timeout check.
>> - Corrected the comments.
>> Changes in V3:
>> - Rebased on the latest u-boot-spi tree.
>>  arch/arm/cpu/armv7/exynos/pinmux.c |   2 +-
>>  arch/arm/cpu/armv7/exynos/spl_boot.c   | 122 
>> -
>>  arch/arm/include/asm/arch-exynos/spi.h |   1 +
>>  include/configs/exynos5250-dt.h|   2 +
>>  4 files changed, 123 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c 
>> b/arch/arm/cpu/armv7/exynos/pinmux.c
>> index 8002bce..74cc700 100644
>> --- a/arch/arm/cpu/armv7/exynos/pinmux.c
>> +++ b/arch/arm/cpu/armv7/exynos/pinmux.c
>> @@ -462,7 +462,7 @@ static int exynos4_pinmux_config(int peripheral, int 
>> flags)
>> case PERIPH_ID_SDMMC1:
>> case PERIPH_ID_SDMMC3:
>> case PERIPH_ID_SDMMC4:
>> -   printf("SDMMC device %d not implemented\n", peripheral);
>> +   debug("SDMMC device %d not implemented\n", peripheral);

unrelated change.

>> return -1;
>> default:
>> debug("%s: invalid peripheral %d", __func__, peripheral);
>> diff --git a/arch/arm/cpu/armv7/exynos/spl_boot.c 
>> b/arch/arm/cpu/armv7/exynos/spl_boot.c
>> index 3651c00..6faf13f 100644
>> --- a/arch/arm/cpu/armv7/exynos/spl_boot.c
>> +++ b/arch/arm/cpu/armv7/exynos/spl_boot.c
>> @@ -10,8 +10,11 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>> +#include 
>>  #include 
>>  #include 
>> +#include 
>>
>>  #include "common_setup.h"
>>  #include "clock_init.h"
>> @@ -59,6 +62,119 @@ static int config_branch_prediction(int set_cr_z)
>>  }
>>  #endif
>>
>> +static void spi_rx_tx(struct exynos_spi *regs, int todo,
>> +   void *dinp, void const *doutp, int i)
>> +{
>> +   uint *rxp = (uint *)(dinp + (i * (32 * 1024)));
>> +   int rx_lvl, tx_lvl;
>> +   uint out_bytes, in_bytes;
>> +
>> +   out_bytes = todo;
>> +   in_bytes = todo;
>> +   setbits_le32(®s->ch_cfg, SPI_CH_RST);
>> +   clrbits_le32(®s->ch_cfg, SPI_CH_RST);
>> +   writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
>> +
>> +   while (in_bytes) {
>> +   uint32_t spi_sts;
>> +   int temp;
>> +
>> +   spi_sts = readl(®s->spi_sts);
>> +   rx_lvl = ((spi_sts >> 15) & 0x7f);
>> +   tx_lvl = ((spi_sts >> 6) & 0x7f);
>> +   while (tx_lvl < 32 && out_bytes) {
>> +   temp = 0x;
>> +   writel(temp, ®s->tx_data);
>> +   out_bytes -= 4;
>> +   tx_lvl += 4;
>> +   }
>> +   while (rx_lvl >= 4 && in_bytes) {
>> +   temp = readl(®s->rx_data);
>> +   if (rxp)
>> +   *rxp++ = temp;
>> +   in_bytes -= 4;
>> +   rx_lvl -= 4;
>> +   }
>> +   }
>> +}
>> +
>> +/*
>> + * Copy uboot from spi flash to RAM
>> + *
>> + * @parma uboot_size   size of u-boot to copy
>> + * @param uboot_addr   address in u-boot to copy
>> + */
>> +static void exynos_spi_copy(unsigned int uboot_size, unsigned int 
>> uboot_addr)
>> +{
>> +   int upto, todo;
>> +   int i, timeout = 100;
>> +   struct exynos_spi *regs = (struct exynos_spi *)CONFIG_ENV_SPI_BASE;
>> +
>> +   set_spi_clk(PERIPH_ID_SPI1, 5000); /* set spi clock to 50Mhz */
>> +   /* set the spi1 GPIO */
>> +   exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE);
>> +
>> +   /* set pktcnt and enable it */
>> +   writel(4 | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
>> +   /* set FB_CLK_SEL */
>> +   writel(SPI_FB_DELAY_180, ®s->fb_clk);
>> +   /* set CH_WIDTH and BUS_WIDTH as word */
>> +   setbits_le32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
>> +   

Re: [U-Boot] [PATCH v3 0/4] i2c: fti2c010: bug fix & new driver model

[Heiko Schocher]

Hello Kuo-Jung,

Am 02.12.2013 09:09, schrieb Kuo-Jung Su:

Hi Heiko:

Sorry, my 3G network was unstable this morning, I've re-sent this v3
patch series.

Please check it out few minutes later, thank you.


Your patches have reached the ML now, thanks!

bye,
Heiko
--
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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[U-Boot] [PATCH v6] spi: Add support SH Quad SPI driver

[Nobuhiro Iwamatsu]

This patch adds a driver for Renesas SoC's Quad SPI bus.
This supports with 8 bits per transfer to use with SPI flash.

Signed-off-by: Kouei Abe 
Signed-off-by: Nobuhiro Iwamatsu 
Signed-off-by: Jagannadha Sutradharudu Teki 
---

Changes for v6:
  - Update Makefile to new style.
Changes for v5: 
  - Add print abort when call ctrlc().
  - Move source code in spi_xfer() which should be processed by
spi_cs_activate(). 
  - Move source code in spi_xfer() which should be processed by
spi_cs_deactivate().
  - Remove sh_qspi_xfer, move to spi_xfer().
Changes for v4: 
  - Added tabs
  - Added comments
  - Added sh_qspi_init()
Changes for v3: 
  - Change Queued to Quad.
  - Remove path of file from file header.
  - Use read* and write* directly instead of sh_qspi_write* sh_qspi_read*. 
  - Change driver format.
Changes for v2: 
  - "SH QSPI" to "SH QSPI (Queued SPI)".
  - Remove magic number.

 drivers/spi/Makefile  |   1 +
 drivers/spi/sh_qspi.c | 244 ++
 2 files changed, 245 insertions(+)
 create mode 100644 drivers/spi/sh_qspi.c

diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 27902fe..914e71f 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
 obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
 obj-$(CONFIG_SOFT_SPI) += soft_spi.o
 obj-$(CONFIG_SH_SPI) += sh_spi.o
+obj-$(CONFIG_SH_QSPI) += sh_qspi.o
 obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
 obj-$(CONFIG_FDT_SPI) += fdt_spi.o
 obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c
new file mode 100644
index 000..8f53552
--- /dev/null
+++ b/drivers/spi/sh_qspi.c
@@ -0,0 +1,244 @@
+/*
+ * SH QSPI (Quad SPI) driver
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Nobuhiro Iwamatsu 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+/* SH QSPI register bit masks _ */
+#define SPCR_MSTR  0x08
+#define SPCR_SPE   0x40
+#define SPSR_SPRFF 0x80
+#define SPSR_SPTEF 0x20
+#define SPPCR_IO3FV0x04
+#define SPPCR_IO2FV0x02
+#define SPPCR_IO1FV0x01
+#define SPBDCR_RXBC0   (1 << 0)
+#define SPCMD_SCKDEN   (1 << 15)
+#define SPCMD_SLNDEN   (1 << 14)
+#define SPCMD_SPNDEN   (1 << 13)
+#define SPCMD_SSLKP(1 << 7)
+#define SPCMD_BRDV0(1 << 2)
+#define SPCMD_INIT1SPCMD_SCKDEN | SPCMD_SLNDEN | \
+   SPCMD_SPNDEN | SPCMD_SSLKP | \
+   SPCMD_BRDV0
+#define SPCMD_INIT2SPCMD_SPNDEN | SPCMD_SSLKP | \
+   SPCMD_BRDV0
+#define SPBFCR_TXRST   (1 << 7)
+#define SPBFCR_RXRST   (1 << 6)
+
+/* SH QSPI register set */
+struct sh_qspi_regs {
+   unsigned char spcr;
+   unsigned char sslp;
+   unsigned char sppcr;
+   unsigned char spsr;
+   unsigned long spdr;
+   unsigned char spscr;
+   unsigned char spssr;
+   unsigned char spbr;
+   unsigned char spdcr;
+   unsigned char spckd;
+   unsigned char sslnd;
+   unsigned char spnd;
+   unsigned char dummy0;
+   unsigned short spcmd0;
+   unsigned short spcmd1;
+   unsigned short spcmd2;
+   unsigned short spcmd3;
+   unsigned char spbfcr;
+   unsigned char dummy1;
+   unsigned short spbdcr;
+   unsigned long spbmul0;
+   unsigned long spbmul1;
+   unsigned long spbmul2;
+   unsigned long spbmul3;
+};
+
+struct sh_qspi_slave {
+   struct spi_slaveslave;
+   struct sh_qspi_regs *regs;
+};
+
+static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave)
+{
+   return container_of(slave, struct sh_qspi_slave, slave);
+}
+
+static void sh_qspi_init(struct sh_qspi_slave *ss)
+{
+   /* QSPI initialize */
+   writeb(SPCR_MSTR, &ss->regs->spcr);
+   writeb(0x00, &ss->regs->sslp);
+   writeb(SPPCR_IO3FV|SPPCR_IO2FV, &ss->regs->sppcr);
+
+   /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
+   writeb(0x01, &ss->regs->spbr);
+
+   writeb(0x00, &ss->regs->spdcr);
+   writeb(0x00, &ss->regs->spckd);
+   writeb(0x00, &ss->regs->sslnd);
+   writeb(0x00, &ss->regs->spnd);
+   writew(SPCMD_INIT1, &ss->regs->spcmd0);
+   writew(SPCMD_INIT2, &ss->regs->spcmd0);
+   writeb(SPBFCR_TXRST|SPBFCR_RXRST, &ss->regs->spbfcr);
+   writeb(0x00, &ss->regs->spbfcr);
+   writeb(0x00, &ss->regs->spscr);
+   writeb(SPCR_SPE|SPCR_MSTR, &ss->regs->spcr);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+   return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+   struct sh_qspi_slave *ss = to_sh_qspi(slave);
+
+   writeb(SPCR_MSTR, &ss->regs->spcr);
+   writew(SPCMD_INIT1, &ss->regs->spcmd0);
+   writeb(SPBFCR_TXRST|SPBFCR_RXRST, &ss->regs->spbfcr);
+   writeb(0x00, &ss->regs->spbfcr);
+   writeb(0x00, &ss->regs->spscr);
+   writeb(SPCR_SPE|SPCR_MSTR, &ss->regs-

Re: [U-Boot] [PATCH v3 0/4] i2c: fti2c010: bug fix & new driver model

[Kuo-Jung Su]

Hi Heiko:

Sorry, my 3G network was unstable this morning, I've re-sent this v3
patch series.

Please check it out few minutes later, thank you.

Best Wishes
Dante Su

2013/12/2 Heiko Schocher :
> Hello Kuop-Jung,
>
> Am 02.12.2013 03:57, schrieb Kuo-Jung Su:
>>
>> From: Kuo-Jung Su
>>
>> This changeset adapts the fti2c010.c to the new i2c driver model.
>>
>> Changes for v3:
>>1. cmd_eeprom: Pass 'addr[0]' instead of 'dev_addr' into i2c r/w
>>   routines.
>>2. fti2c010: serial out r/w address in MSB order: coding style update
>>
>> Changes for v2:
>>1. cmd_eeprom: bug fix for i2c read/write
>>2. fti2c010: serial out r/w address in MSB order
>>
>> Kuo-Jung Su (4):
>>i2c: fti2c010: cosmetic: coding style cleanup
>>i2c: fti2c010: migrate to new i2c model
>>i2c: fti2c010: serial out r/w address in MSB order
>>cmd_eeprom: bug fix for i2c read/write
>
>
> I see only v3 1/4 on the ML. Did you send the patches v3 2-4/4 ?
>
> bye,
> Heiko
> --
> DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany



-- 
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Kuo-Jung Su
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[U-Boot] [PATCH v3 4/4] cmd_eeprom: bug fix for i2c read/write

[Kuo-Jung Su]

From: Kuo-Jung Su 

The local pointer of address (i.e., addr) only gets
referenced under SPI mode, and it won't be appropriate
to pass only 1-byte addr[1] to i2c_read/i2c_write while
CONFIG_SYS_I2C_EEPROM_ADDR_LEN > 1.

1. In U-boot's I2C model, the address would be re-assembled
   to a byte string in MSB order inside I2C controller drivers.

2. The 'CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW' option which could
   be found at soft_i2c.c is always turned on in cmd_eeprom.c,
   the addr[0] always contains the device address with overflowed
   MSB address bits.

Signed-off-by: Kuo-Jung Su 
Cc: Alexey Brodkin 
Cc: Jean-Christophe PLAGNIOL-VILLARD 
cc: Peter Tyser 
Cc: Heiko Schocher 
Cc: Wolfgang Denk 
Cc: Stefan Roese 
Cc: Mischa Jonker 
---
 Changes for v3:
  - It turns out that what we did before 2013-11-13
(i.e., cmd_eeprom: fix i2c_{read|write} usage if env is in I2C EEPROM)
is still the best one, this patch simply rollback to it with coding
style fix.

 Changes for v2:
  - Initial release

 common/cmd_eeprom.c |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/common/cmd_eeprom.c b/common/cmd_eeprom.c
index 02539c4..3924805 100644
--- a/common/cmd_eeprom.c
+++ b/common/cmd_eeprom.c
@@ -161,7 +161,7 @@ int eeprom_read (unsigned dev_addr, unsigned offset, uchar 
*buffer, unsigned cnt
 #if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
spi_read (addr, alen, buffer, len);
 #else
-   if (i2c_read (addr[0], addr[1], alen-1, buffer, len) != 0)
+   if (i2c_read(addr[0], offset, alen - 1, buffer, len))
rcode = 1;
 #endif
buffer += len;
@@ -339,7 +339,7 @@ int eeprom_write (unsigned dev_addr, unsigned offset, uchar 
*buffer, unsigned cn
/* Write is enabled ... now write eeprom value.
 */
 #endif
-   if (i2c_write (addr[0], addr[1], alen-1, buffer, len) != 0)
+   if (i2c_write(addr[0], offset, alen - 1, buffer, len))
rcode = 1;

 #endif
--
1.7.9.5

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[U-Boot] [PATCH v3 3/4] i2c: fti2c010: serial out r/w address in MSB order

[Kuo-Jung Su]

From: Kuo-Jung Su 

For a eeprom with a 2-bytes address (e.g., Ateml AT24C1024B),
the r/w address should be serial out in MSB order.

Signed-off-by: Kuo-Jung Su 
Cc: Heiko Schocher 
---
 Changes for v3:
  - Coding style update

 Changes for v2:
  - Initial release

 drivers/i2c/fti2c010.c |   26 ++
 1 file changed, 18 insertions(+), 8 deletions(-)

diff --git a/drivers/i2c/fti2c010.c b/drivers/i2c/fti2c010.c
index eccc1da..fb9fa35 100644
--- a/drivers/i2c/fti2c010.c
+++ b/drivers/i2c/fti2c010.c
@@ -179,6 +179,22 @@ static int fti2c010_probe(struct i2c_adapter *adap, u8 dev)
return ret;
 }

+static void to_i2c_addr(u8 *buf, uint32_t addr, int alen)
+{
+   int i, shift;
+
+   if (!buf || alen <= 0)
+   return;
+
+   /* MSB first */
+   i = 0;
+   shift = (alen - 1) * 8;
+   while (alen-- > 0) {
+   buf[i] = (u8)(addr >> shift);
+   shift -= 8;
+   }
+}
+
 static int fti2c010_read(struct i2c_adapter *adap,
u8 dev, uint addr, int alen, uchar *buf, int len)
 {
@@ -187,10 +203,7 @@ static int fti2c010_read(struct i2c_adapter *adap,
int ret, pos;
uchar paddr[4];

-   paddr[0] = (addr >> 0)  & 0xFF;
-   paddr[1] = (addr >> 8)  & 0xFF;
-   paddr[2] = (addr >> 16) & 0xFF;
-   paddr[3] = (addr >> 24) & 0xFF;
+   to_i2c_addr(paddr, addr, alen);

/*
 * Phase A. Set register address
@@ -252,10 +265,7 @@ static int fti2c010_write(struct i2c_adapter *adap,
int ret, pos;
uchar paddr[4];

-   paddr[0] = (addr >> 0)  & 0xFF;
-   paddr[1] = (addr >> 8)  & 0xFF;
-   paddr[2] = (addr >> 16) & 0xFF;
-   paddr[3] = (addr >> 24) & 0xFF;
+   to_i2c_addr(paddr, addr, alen);

/*
 * Phase A. Set register address
--
1.7.9.5

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[U-Boot] [PATCH v3 2/4] i2c: fti2c010: migrate to new i2c model

[Kuo-Jung Su]

From: Kuo-Jung Su 

Replace the legacy i2c model with the new one.

Signed-off-by: Kuo-Jung Su 
Cc: Heiko Schocher 
---
 Changes for v2 & v3:
  - Nothing updates

 drivers/i2c/fti2c010.c |  299 +---
 1 file changed, 133 insertions(+), 166 deletions(-)

diff --git a/drivers/i2c/fti2c010.c b/drivers/i2c/fti2c010.c
index ec6afc9..eccc1da 100644
--- a/drivers/i2c/fti2c010.c
+++ b/drivers/i2c/fti2c010.c
@@ -13,14 +13,14 @@

 #include "fti2c010.h"

-#ifndef CONFIG_HARD_I2C
-#error "fti2c010: CONFIG_HARD_I2C is not defined"
-#endif
-
 #ifndef CONFIG_SYS_I2C_SPEED
 #define CONFIG_SYS_I2C_SPEED5000
 #endif

+#ifndef CONFIG_SYS_I2C_SLAVE
+#define CONFIG_SYS_I2C_SLAVE0
+#endif
+
 #ifndef CONFIG_FTI2C010_CLOCK
 #define CONFIG_FTI2C010_CLOCK   clk_get_rate("I2C")
 #endif
@@ -35,44 +35,54 @@

 struct fti2c010_chip {
struct fti2c010_regs *regs;
-   uint bus;
-   uint speed;
 };

 static struct fti2c010_chip chip_list[] = {
{
-   .bus  = 0,
.regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE,
},
-#ifdef CONFIG_I2C_MULTI_BUS
-# ifdef CONFIG_FTI2C010_BASE1
+#ifdef CONFIG_FTI2C010_BASE1
{
-   .bus  = 1,
.regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE1,
},
-# endif
-# ifdef CONFIG_FTI2C010_BASE2
+#endif
+#ifdef CONFIG_FTI2C010_BASE2
{
-   .bus  = 2,
.regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE2,
},
-# endif
-# ifdef CONFIG_FTI2C010_BASE3
+#endif
+#ifdef CONFIG_FTI2C010_BASE3
{
-   .bus  = 3,
.regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE3,
},
-# endif
-#endif  /* #ifdef CONFIG_I2C_MULTI_BUS */
+#endif
 };

-static struct fti2c010_chip *curr = chip_list;
+static int fti2c010_reset(struct fti2c010_chip *chip)
+{
+   ulong ts;
+   int ret = -1;
+   struct fti2c010_regs *regs = chip->regs;

-static int fti2c010_wait(uint32_t mask)
+   writel(CR_I2CRST, ®s->cr);
+   for (ts = get_timer(0); get_timer(ts) < CONFIG_FTI2C010_TIMEOUT; ) {
+   if (!(readl(®s->cr) & CR_I2CRST)) {
+   ret = 0;
+   break;
+   }
+   }
+
+   if (ret)
+   printf("fti2c010: reset timeout\n");
+
+   return ret;
+}
+
+static int fti2c010_wait(struct fti2c010_chip *chip, uint32_t mask)
 {
int ret = -1;
uint32_t stat, ts;
-   struct fti2c010_regs *regs = curr->regs;
+   struct fti2c010_regs *regs = chip->regs;

for (ts = get_timer(0); get_timer(ts) < CONFIG_FTI2C010_TIMEOUT; ) {
stat = readl(®s->sr);
@@ -85,74 +95,97 @@ static int fti2c010_wait(uint32_t mask)
return ret;
 }

-/*
- * u-boot I2C API
- */
+static unsigned int set_i2c_bus_speed(struct fti2c010_chip *chip,
+   unsigned int speed)
+{
+   struct fti2c010_regs *regs = chip->regs;
+   unsigned int clk = CONFIG_FTI2C010_CLOCK;
+   unsigned int gsr = 0;
+   unsigned int tsr = 32;
+   unsigned int div, rate;
+
+   for (div = 0; div < 0x3; ++div) {
+   /* SCLout = PCLK/(2*(COUNT + 2) + GSR) */
+   rate = clk / (2 * (div + 2) + gsr);
+   if (rate <= speed)
+   break;
+   }
+
+   writel(TGSR_GSR(gsr) | TGSR_TSR(tsr), ®s->tgsr);
+   writel(CDR_DIV(div), ®s->cdr);
+
+   return rate;
+}

 /*
  * Initialization, must be called once on start up, may be called
  * repeatedly to change the speed and slave addresses.
  */
-void i2c_init(int speed, int slaveaddr)
+static void fti2c010_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 {
-   if (speed || !curr->speed)
-   i2c_set_bus_speed(speed);
+   struct fti2c010_chip *chip = chip_list + adap->hwadapnr;

-   /* if slave mode disabled */
-   if (!slaveaddr)
+   if (adap->init_done)
return;

-   /*
-* TODO:
-* Implement slave mode, but is it really necessary?
-*/
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
+   /* Call board specific i2c bus reset routine before accessing the
+* environment, which might be in a chip on that bus. For details
+* about this problem see doc/I2C_Edge_Conditions.
+   */
+   i2c_init_board();
+#endif
+
+   /* master init */
+
+   fti2c010_reset(chip);
+
+   set_i2c_bus_speed(chip, speed);
+
+   /* slave init, don't care */
+
+#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
+   /* Call board specific i2c bus reset routine AFTER the bus has been
+* initialized. Use either this callpoint or i2c_init_board;
+* which is called before fti2c010_init operations.
+* For details about this problem see doc/I2C_Edge_Conditions.
+   */
+   i2c_board_late_init();
+#endif
 }

 /*
  * Probe the given I2C chip address.  Returns 0 if a chip responded,
  * not 0 on failure.
  */
-int i2c_probe(uchar c

[U-Boot] [PATCH v3 1/4] i2c: fti2c010: cosmetic: coding style cleanup

[Kuo-Jung Su]

From: Kuo-Jung Su 

Coding style cleanup

Signed-off-by: Kuo-Jung Su 
Cc: Heiko Schocher 
---
 Changes for v2 & v3:
  - Nothing updates

 drivers/i2c/fti2c010.c |   31 ---
 1 file changed, 16 insertions(+), 15 deletions(-)

diff --git a/drivers/i2c/fti2c010.c b/drivers/i2c/fti2c010.c
index ddeb941..ec6afc9 100644
--- a/drivers/i2c/fti2c010.c
+++ b/drivers/i2c/fti2c010.c
@@ -18,22 +18,23 @@
 #endif

 #ifndef CONFIG_SYS_I2C_SPEED
-#define CONFIG_SYS_I2C_SPEED5
+#define CONFIG_SYS_I2C_SPEED5000
 #endif

-#ifndef CONFIG_FTI2C010_FREQ
-#define CONFIG_FTI2C010_FREQclk_get_rate("I2C")
+#ifndef CONFIG_FTI2C010_CLOCK
+#define CONFIG_FTI2C010_CLOCK   clk_get_rate("I2C")
 #endif

-/* command timeout */
-#define CFG_CMD_TIMEOUT 10 /* ms */
+#ifndef CONFIG_FTI2C010_TIMEOUT
+#define CONFIG_FTI2C010_TIMEOUT 10 /* ms */
+#endif

-/* 7-bit chip address + 1-bit read/write */
-#define I2C_RD(chip)chip) << 1) & 0xff) | 1)
-#define I2C_WR(chip)(((chip) << 1) & 0xff)
+/* 7-bit dev address + 1-bit read/write */
+#define I2C_RD(dev) dev) << 1) & 0xfe) | 1)
+#define I2C_WR(dev) (((dev) << 1) & 0xfe)

 struct fti2c010_chip {
-   void __iomem *regs;
+   struct fti2c010_regs *regs;
uint bus;
uint speed;
 };
@@ -41,25 +42,25 @@ struct fti2c010_chip {
 static struct fti2c010_chip chip_list[] = {
{
.bus  = 0,
-   .regs = (void __iomem *)CONFIG_FTI2C010_BASE,
+   .regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE,
},
 #ifdef CONFIG_I2C_MULTI_BUS
 # ifdef CONFIG_FTI2C010_BASE1
{
.bus  = 1,
-   .regs = (void __iomem *)CONFIG_FTI2C010_BASE1,
+   .regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE1,
},
 # endif
 # ifdef CONFIG_FTI2C010_BASE2
{
.bus  = 2,
-   .regs = (void __iomem *)CONFIG_FTI2C010_BASE2,
+   .regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE2,
},
 # endif
 # ifdef CONFIG_FTI2C010_BASE3
{
.bus  = 3,
-   .regs = (void __iomem *)CONFIG_FTI2C010_BASE3,
+   .regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE3,
},
 # endif
 #endif  /* #ifdef CONFIG_I2C_MULTI_BUS */
@@ -73,7 +74,7 @@ static int fti2c010_wait(uint32_t mask)
uint32_t stat, ts;
struct fti2c010_regs *regs = curr->regs;

-   for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
+   for (ts = get_timer(0); get_timer(ts) < CONFIG_FTI2C010_TIMEOUT; ) {
stat = readl(®s->sr);
if ((stat & mask) == mask) {
ret = 0;
@@ -324,7 +325,7 @@ uint i2c_get_bus_num(void)
 int i2c_set_bus_speed(uint speed)
 {
struct fti2c010_regs *regs = curr->regs;
-   uint clk = CONFIG_FTI2C010_FREQ;
+   uint clk = CONFIG_FTI2C010_CLOCK;
uint gsr = 0, tsr = 32;
uint spd, div;

--
1.7.9.5

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[U-Boot] [PATCH v3 0/4] i2c: fti2c010: bug fix & new driver model

[Kuo-Jung Su]

From: Kuo-Jung Su 

This changeset adapts the fti2c010.c to the new i2c driver model.

Changes for v3:
  1. cmd_eeprom: Pass 'addr[0]' instead of 'dev_addr' into i2c r/w
 routines.
  2. fti2c010: serial out r/w address in MSB order: coding style update

Changes for v2:
  1. cmd_eeprom: bug fix for i2c read/write
  2. fti2c010: serial out r/w address in MSB order

Kuo-Jung Su (4):
  i2c: fti2c010: cosmetic: coding style cleanup
  i2c: fti2c010: migrate to new i2c model
  i2c: fti2c010: serial out r/w address in MSB order
  cmd_eeprom: bug fix for i2c read/write

 common/cmd_eeprom.c|4 +-
 drivers/i2c/fti2c010.c |  352 +++-
 2 files changed, 167 insertions(+), 189 deletions(-)

--
1.7.9.5

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