Re: [U-Boot] [PATCH v5 10/12] arm: goni: dfu: Add support for DFU to Goni target
On 29/04/14 04:13, Mateusz Zalega wrote: > Proper adjustment for supporting DFU at GONI target has been made. > The s5p_goni.h file has been updated. Moreover the code for low level > USB initialization has been added to GONI board code. > > The malloc pool has been enlarged in order to support larger buffer > sizes needed by DFU implementation. > > Signed-off-by: Arkadiusz Wlodarczyk > Signed-off-by: Kyungmin Park > Signed-off-by: Mateusz Zalega > Tested-by: Arkadiusz Wlodarczyk > Tested-by: Mateusz Zalega > Cc: Minkyu Kang > --- > Changes since v1: > - reordered > --- > board/samsung/goni/goni.c | 8 +++ > include/configs/s5p_goni.h | 54 > -- > 2 files changed, 51 insertions(+), 11 deletions(-) > applied to u-boot-samsung. Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 09/12] arm: goni: Update configuration for Goni target
On 29/04/14 04:13, Mateusz Zalega wrote: > Configuration file for GONI has been updated to support FAT file system, > new mmc partitioning scheme and read linux kernel from eMMC instead of > OneNAND. > > Signed-off-by: Arkadiusz Wlodarczyk > Signed-off-by: Kyungmin Park > Signed-off-by: Mateusz Zalega > Tested-by: Arkadiusz Wlodarczyk > Tested-by: Mateusz Zalega > Cc: Minkyu Kang > --- > Changes since v1: > - reordered > --- > include/configs/s5p_goni.h | 56 > +- > 1 file changed, 30 insertions(+), 26 deletions(-) > applied to u-boot-samsung. Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 11/12] arm: goni: enable GPT command
On 29/04/14 04:13, Mateusz Zalega wrote: > Signed-off-by: Mateusz Zalega > Cc: Minkyu Kang > --- > Changes since v1: > - reordered > --- > include/configs/s5p_goni.h | 5 + > 1 file changed, 5 insertions(+) > applied to u-boot-samsung. Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 12/12] arm: goni: enable USB Mass Storage
On 29/04/14 04:13, Mateusz Zalega wrote: > UMS-related defines were added to Samsung Goni config header. > > Signed-off-by: Mateusz Zalega > Cc: Minkyu Kang > --- > Changes since v1: > - reordered > --- > include/configs/s5p_goni.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h > index c52a00a..f551c22 100644 > --- a/include/configs/s5p_goni.h > +++ b/include/configs/s5p_goni.h > @@ -267,5 +267,7 @@ > #define CONFIG_USB_GADGET_S3C_UDC_OTG > #define CONFIG_USB_GADGET_DUALSPEED > #define CONFIG_USB_GADGET_VBUS_DRAW 2 > +#define CONFIG_CMD_USB_MASS_STORAGE > +#define CONFIG_USB_GADGET_MASS_STORAGE > > #endif /* __CONFIG_H */ > applied to u-boot-samsung. Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv5 00/14] mmc: exynos: code cleanup and support DDR mode
On 16/05/14 13:59, Jaehoon Chung wrote: > If card and host are supported DDR mode, then it can be used the DDR mode. > This patch-set has dependency about beomho's patch-set. > (Based-on u-boot-samsung repository) > > It's result for loading image. > > sdhci controller ->5260488 bytes read in 259 ms (19.4 MiB/s) > dwmmc controller without DDR mode -> 5260488 bytes read in 202 ms (24.8 MiB/s) > dwmmc controller with DDR mode -> 5260488 bytes read in 118 ms (42.5 MiB/s) > > Download the 400M image with lthor. > sdhci controller -> 59.4sec (Avg 6.95 MB/s) > dwmmc controller without DDR mode -> 61.6sec (Avg 6.72MB/s) > dwmmc controller with DDR mode -> 60.4sec (Avg 6.85MB/s) > > Beomho Seo (3): > arm: exynos: pinmux: add sdmmc4 gpio configratuion > arm: exynos: clock: Remove exynos4x12_set_mmc_clk function > board: trats2: Enable device tree on Trats2 > > Jaehoon Chung (11): > ARM: exynos: board: change the mmc/sd init sequence > ARM: exynos: clock: modify the set_mmc_clk for exynos4 > ARM: dts: exynos: rename from EXYNOS5_DWMMC to EXYNOS_DWMMC > mmc: exynos_dw_mmc: restore the property into host > mmc: remove the unnecessary define and fix the wrong bit control > mmc: support the DDR mode for eMMC > mmc: dw_mmc: support the DDR mode > ARM: dts: exnyos: enable dw-mmc controller > mmc: exynos_dw_mmc: enable the DDR mode > ARM: exynos4: enable the dwmmc configuration > mmc: s5p_sdhci: add the s5p_sdhci_core_init function > > arch/arm/cpu/armv7/exynos/clock.c | 45 ++- > arch/arm/cpu/armv7/exynos/pinmux.c| 35 - > arch/arm/dts/exynos4.dtsi |8 ++ > arch/arm/dts/exynos4412-trats2.dts| 12 ++ > arch/arm/dts/exynos5.dtsi |8 +- > arch/arm/include/asm/arch-exynos/clk.h|5 + > board/samsung/common/board.c | 13 +- > doc/device-tree-bindings/exynos/dwmmc.txt |8 +- > drivers/mmc/dw_mmc.c | 12 +- > drivers/mmc/exynos_dw_mmc.c | 205 > +++-- > drivers/mmc/mmc.c | 16 ++- > drivers/mmc/s5p_sdhci.c | 42 +++--- > include/configs/exynos4-dt.h |3 + > include/dwmmc.h |5 + > include/fdtdec.h |2 +- > include/mmc.h | 25 ++-- > lib/fdtdec.c |2 +- > 17 files changed, 275 insertions(+), 171 deletions(-) > applied to u-boot-samsung. Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: exynos5420: removed undefined gpio structure
On 14/05/14 19:44, Jaehoon Chung wrote:
> It's removed the exynos5_gpio_part1.
>
> Signed-off-by: Jaehoon Chung
> ---
> board/samsung/smdk5420/smdk5420.c |3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/board/samsung/smdk5420/smdk5420.c
> b/board/samsung/smdk5420/smdk5420.c
> index 9207522..183c522 100644
> --- a/board/samsung/smdk5420/smdk5420.c
> +++ b/board/samsung/smdk5420/smdk5420.c
> @@ -42,9 +42,6 @@ int exynos_init(void)
> #ifdef CONFIG_LCD
> void cfg_lcd_gpio(void)
> {
> - struct exynos5_gpio_part1 *gpio1 =
> - (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
> -
> /* For Backlight */
> gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_OUTPUT);
> gpio_set_value(EXYNOS5420_GPIO_B20, 1);
>
applied to u-boot-samsung.
Thanks,
Minkyu Kang.
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[U-Boot] [PATCH v2] examples: select libgcc for non-default architecture
In case of multilib-enabled toolchains if default architecture differ from the one examples are being built for linker will fail to link example object files with libgcc of another (non-compatible) architecture. Interesting enough for years in main Makefile we used CFLAGS/c_flags for this but not for examples. So fixing it now. Signed-off-by: Alexey Brodkin Cc: Masahiro Yamada Cc: Tom Rini Cc: Wolfgang Denx --- v2 copies functoinality for libgcc selection from main Makefile. This takes care of CONFIG_USE_PRIVATE_LIBGCC if one is used. examples/standalone/Makefile | 14 -- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile index 9ab5446..2c13c07 100644 --- a/examples/standalone/Makefile +++ b/examples/standalone/Makefile @@ -38,7 +38,17 @@ targets += $(patsubst $(obj)/%,%,$(LIB)) $(COBJS) $(LIBOBJS-y) LIBOBJS:= $(addprefix $(obj)/,$(LIBOBJS-y)) ELF:= $(addprefix $(obj)/,$(ELF)) -gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) +# Add GCC lib +ifdef CONFIG_USE_PRIVATE_LIBGCC +ifeq ($(CONFIG_USE_PRIVATE_LIBGCC),y) +PLATFORM_LIBGCC = arch/$(ARCH)/lib/lib.a +else +PLATFORM_LIBGCC = -L $(CONFIG_USE_PRIVATE_LIBGCC) -lgcc +endif +else +PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(PLATFORM_CPPFLAGS) \ + -print-libgcc-file-name`) -lgcc +endif # For PowerPC there's no need to compile standalone applications as a # relocatable executable. The relocation data is not needed, and @@ -63,7 +73,7 @@ $(LIB): $(LIBOBJS) FORCE quiet_cmd_link_elf = LD $@ cmd_link_elf = $(LD) $(LDFLAGS) -g -Ttext $(CONFIG_STANDALONE_LOAD_ADDR) \ --o $@ -e $(SYM_PREFIX)$(@F) $< $(LIB) -L$(gcclibdir) -lgcc +-o $@ -e $(SYM_PREFIX)$(@F) $< $(LIB) $(PLATFORM_LIBGCC) $(ELF): $(obj)/%: $(obj)/%.o $(LIB) FORCE $(call if_changed,link_elf) -- 1.9.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] spl: consolidate arch/arm/include/asm/arch-*/spl.h
Hi Tim, Tom, > > Tom / Masahiro, > > Any update on this? This is a very useful cleanup and there is at > least one pending patch series that depend on it. No update from me. Version 2 is the latest one. http://patchwork.ozlabs.org/patch/341817/ I am also waiting for the review. Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] spl: consolidate arch/arm/include/asm/arch-*/spl.h
On Mon, Apr 28, 2014 at 1:16 AM, Masahiro Yamada
wrote:
>
> Hi Tom,
>
> On Fri, 25 Apr 2014 14:52:06 -0400
> Tom Rini wrote:
>
> > On Wed, Apr 16, 2014 at 03:44:36PM +0900, Masahiro Yamada wrote:
> >
> > > arch/arm/include/asm/spl.h requires all SoCs to have
> > > arch/arm/include/asm/arch-*/spl.h.
> > >
> > > But many of them just define BOOT_DEVICE_* macros.
> > >
> > > Those macros are used in the "switch (boot_device) { ... }"
> > > statement in common/spl/spl.c.
> > >
> > > So they should not be archtecture specific, but described as
> > > a simpile enumeration.
> > >
> > > This commit merge most of arch/arm/include/asm/arch-*/spl.h
> > > into arch/arm/include/asm/spl.h.
> > >
> > > With a little more effort, arch-zynq/spl.h and arch-socfpga/spl.h
> > > will be merged, while I am not sure about OMAP and Exynos.
> >
> > The problem is that on TI platforms these values have meaning defined by
> > ROM (which changes occasionally). When ROM starts us up, we get a
> > little bit of info that says "I found and loaded you on ...". So while
> > we could move towards moving BOOT_DEVICE_FOO into we'd need in
> > arch/arm/cpu/armv7/omap-common/boot-common.c some logic to translate
> > from ROM numbers to U-Boot numbers.
>
> Could you apply my patch first and fix the OMAP translation logic lator?
>
> I want to stop duplication of similar spl.h headers.
>
> Best Regards
> Masahiro Yamada
Tom / Masahiro,
Any update on this? This is a very useful cleanup and there is at
least one pending patch series that depend on it.
Regards,
Tim
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Re: [U-Boot] [PATCH v3] dfu: Introduction of the "dfu_hash_algo" env variable for checksum method setting
Hi Wolfgang, > Dear Lukasz, > > In message <20140515154334.626923b4@amdc2363> you wrote: > > > > > This reinforces my speculation that you are actually addressing > > > the wrong problem. Instead of adding new code and environment > > > variables and making the system even more complex, we should just > > > leave everything as is, > > > > During working on this patch I've replaced the crc32() method with > > the call to hash_method(), which IMHO is welcome. > > Yes, indeed this is highly welcome. Thanks a lot for that! > > > I also don't personally like the crc32, hence I like the choice > > which this patch gives me to use other algorithm (for which I've > > got HW support on my platform - e.g. MD5). > > Well, is this really useful? dfu-utils provides only CRC caculation, > so where would you get the reference value for any other checksum > metod from? I was rather thinking about a test setup with my target connected via serial console to HOST machine. Then I could compare the CRC32/MD5/SHA1 just after sending the data. For my target it is better to use MD5 or SHA1 since support for them is provided via the specialized, embedded crypto IP. > > > > and you should try to find out why the CRC > > > calculation is so low for you. Checking if caches are enabled is > > > probably among the things that should be done first. > > > > L1 is enabled. L2 has been disabled on purpose (power consumption > > reduction). > > This certainly contributes to slow code execution. > > > Please note that the last revision of DFU is from 2004. I've > > contacted Greg KH (one of the original authors) and he replied that > > no new attempt to revise the standard was made. > > This may just mean that users were just happy with the current > situation. It is hard to say. > It's definitely better than if changed had been proposed > but rejected. True. > > > The best however, would be to revise the standard to include such > > functionality to it. In the same time I'm fully aware that this is > > very unlikely to happen. > > Why do you think it is unlikely? I don't have the experience with preparing USB standards, but I assume that it is somewhat hard to revise the standard after 10 years. > Of course, it would require that > someone comes up with such a proposal in the first place. But you > sound as if you were certain a proposal had no chance for being > considered. No, this is not what I meant. > I may be naive, but should we not at least try before > giving up? Unfortunately my time budget is limited and I feel like this has lower priority than fixing/solving current DFU problems. > > Best regards, > > Wolfgang Denk > -- Best regards, Lukasz Majewski Samsung R&D Institute Poland (SRPOL) | Linux Platform Group ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [AVR32] CONFIG_SYS_TEXT_BASE is missing from atngw100mkii board
Hi Andreass, I noticed by chance atngw100mkii board does not define CONFIG_SYS_TEXT_BASE, although the other AVR32 boards define it. Is this your intention, or mistake? This is what I did: $ git branch * master $ git describe v2014.07-rc1-79-g2072e72 $ make mrproper $ make atngw100mkii_config Configuring for atngw100mkii board... $ make -s -j8 CROSS_COMPILE=avr32-linux- $ grep CONFIG_SYS_TEXT_BASE include/autoconf.mk $ I can't find CONFIG_SYS_TEXT_BASE in include/autoconf.mk Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCHv5 08/14] mmc: remove the unnecessary define and fix the wrong bit control
Signed-off-by: Jaehoon Chung Reviewed-by: Lukasz Majeski Tested-by: Lukasz Majewski Acked-by: Lukasz Majewski --- drivers/mmc/mmc.c |2 +- include/mmc.h | 18 ++ 2 files changed, 7 insertions(+), 13 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 16051e5..dd6a6ef 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -514,7 +514,7 @@ static int mmc_change_freq(struct mmc *mmc) return 0; /* High Speed is set, there are two types: 52MHz and 26MHz */ - if (cardtype & MMC_HS_52MHZ) + if (cardtype & EXT_CSD_CARD_TYPE_52) mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; else mmc->card_caps |= MMC_MODE_HS; diff --git a/include/mmc.h b/include/mmc.h index bc11f45..d5a896f 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -32,15 +32,12 @@ #define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x429) #define MMC_VERSION_4_5(MMC_VERSION_MMC | 0x405) -#define MMC_MODE_HS0x001 -#define MMC_MODE_HS_52MHz 0x010 -#define MMC_MODE_4BIT 0x100 -#define MMC_MODE_8BIT 0x200 -#define MMC_MODE_SPI 0x400 -#define MMC_MODE_HC0x800 - -#define MMC_MODE_MASK_WIDTH_BITS (MMC_MODE_4BIT | MMC_MODE_8BIT) -#define MMC_MODE_WIDTH_BITS_SHIFT 8 +#define MMC_MODE_HS(1 << 0) +#define MMC_MODE_HS_52MHz (1 << 1) +#define MMC_MODE_4BIT (1 << 2) +#define MMC_MODE_8BIT (1 << 3) +#define MMC_MODE_SPI (1 << 4) +#define MMC_MODE_HC(1 << 5) #define SD_DATA_4BIT 0x0004 @@ -98,9 +95,6 @@ #define SD_HIGHSPEED_BUSY 0x0002 #define SD_HIGHSPEED_SUPPORTED 0x0002 -#define MMC_HS_TIMING 0x0100 -#define MMC_HS_52MHZ 0x2 - #define OCR_BUSY 0x8000 #define OCR_HCS0x4000 #define OCR_VOLTAGE_MASK 0x007FFF80 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCHv5 14/14] mmc: s5p_sdhci: add the s5p_sdhci_core_init function
To reuse the code, added the s5p_sdhci_core_init function.
Before applied this patch, didn't use the 8-bit mode at exynos baord.
Because it didn't set "MMC_MODE_8BIT".
Signed-off-by: Jaehoon Chung
Tested-by: Lukasz Majewski
Acked-by: Lukasz Majewski
---
drivers/mmc/s5p_sdhci.c | 42 +-
1 file changed, 17 insertions(+), 25 deletions(-)
diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c
index ccae4cc..2ff0ec2 100644
--- a/drivers/mmc/s5p_sdhci.c
+++ b/drivers/mmc/s5p_sdhci.c
@@ -65,17 +65,9 @@ static void s5p_sdhci_set_control_reg(struct sdhci_host
*host)
sdhci_writel(host, ctrl, SDHCI_CONTROL2);
}
-int s5p_sdhci_init(u32 regbase, int index, int bus_width)
+static int s5p_sdhci_core_init(struct sdhci_host *host)
{
- struct sdhci_host *host = NULL;
- host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
- if (!host) {
- printf("sdhci__host malloc fail!\n");
- return 1;
- }
-
host->name = S5P_NAME;
- host->ioaddr = (void *)regbase;
host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR |
@@ -85,15 +77,28 @@ int s5p_sdhci_init(u32 regbase, int index, int bus_width)
host->set_control_reg = &s5p_sdhci_set_control_reg;
host->set_clock = set_mmc_clk;
- host->index = index;
host->host_caps = MMC_MODE_HC;
- if (bus_width == 8)
+ if (host->bus_width == 8)
host->host_caps |= MMC_MODE_8BIT;
return add_sdhci(host, 5200, 40);
}
+int s5p_sdhci_init(u32 regbase, int index, int bus_width)
+{
+ struct sdhci_host *host = malloc(sizeof(struct sdhci_host));
+ if (!host) {
+ printf("sdhci__host malloc fail!\n");
+ return 1;
+ }
+ host->ioaddr = (void *)regbase;
+ host->index = index;
+ host->bus_width = bus_width;
+
+ return s5p_sdhci_core_init(host);
+}
+
#ifdef CONFIG_OF_CONTROL
struct sdhci_host sdhci_host[SDHCI_MAX_HOSTS];
@@ -126,20 +131,7 @@ static int do_sdhci_init(struct sdhci_host *host)
}
}
- host->name = S5P_NAME;
-
- host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
- SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR |
- SDHCI_QUIRK_WAIT_SEND_CMD;
- host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
- host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
-
- host->set_control_reg = &s5p_sdhci_set_control_reg;
- host->set_clock = set_mmc_clk;
-
- host->host_caps = MMC_MODE_HC;
-
- return add_sdhci(host, 5200, 40);
+ return s5p_sdhci_core_init(host);
}
static int sdhci_get_config(const void *blob, int node, struct sdhci_host
*host)
--
1.7.9.5
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[U-Boot] [PATCHv5 09/14] mmc: support the DDR mode for eMMC
Signed-off-by: Jaehoon Chung
Tested-by: Lukasz Majewski
Acked-by: Lukasz Majewski
---
drivers/mmc/mmc.c | 16 +---
include/mmc.h |7 +++
2 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index dd6a6ef..08187d5 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -158,6 +158,9 @@ int mmc_set_blocklen(struct mmc *mmc, int len)
{
struct mmc_cmd cmd;
+ if (mmc->card_caps & MMC_MODE_DDR_52MHz)
+ return 0;
+
cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = len;
@@ -514,10 +517,13 @@ static int mmc_change_freq(struct mmc *mmc)
return 0;
/* High Speed is set, there are two types: 52MHz and 26MHz */
- if (cardtype & EXT_CSD_CARD_TYPE_52)
+ if (cardtype & EXT_CSD_CARD_TYPE_52) {
+ if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
+ mmc->card_caps |= MMC_MODE_DDR_52MHz;
mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
- else
+ } else {
mmc->card_caps |= MMC_MODE_HS;
+ }
return 0;
}
@@ -1054,6 +1060,8 @@ static int mmc_startup(struct mmc *mmc)
/* An array of possible bus widths in order of preference */
static unsigned ext_csd_bits[] = {
+ EXT_CSD_DDR_BUS_WIDTH_8,
+ EXT_CSD_DDR_BUS_WIDTH_4,
EXT_CSD_BUS_WIDTH_8,
EXT_CSD_BUS_WIDTH_4,
EXT_CSD_BUS_WIDTH_1,
@@ -1061,13 +1069,15 @@ static int mmc_startup(struct mmc *mmc)
/* An array to map CSD bus widths to host cap bits */
static unsigned ext_to_hostcaps[] = {
+ [EXT_CSD_DDR_BUS_WIDTH_4] = MMC_MODE_DDR_52MHz,
+ [EXT_CSD_DDR_BUS_WIDTH_8] = MMC_MODE_DDR_52MHz,
[EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
[EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
};
/* An array to map chosen bus width to an integer */
static unsigned widths[] = {
- 8, 4, 1,
+ 8, 4, 8, 4, 1,
};
for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
diff --git a/include/mmc.h b/include/mmc.h
index d5a896f..aa2d1ca 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -38,6 +38,7 @@
#define MMC_MODE_8BIT (1 << 3)
#define MMC_MODE_SPI (1 << 4)
#define MMC_MODE_HC(1 << 5)
+#define MMC_MODE_DDR_52MHz (1 << 6)
#define SD_DATA_4BIT 0x0004
@@ -169,10 +170,16 @@
#define EXT_CSD_CARD_TYPE_26 (1 << 0)/* Card can run at 26MHz */
#define EXT_CSD_CARD_TYPE_52 (1 << 1)/* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
+#define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
+#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
+ | EXT_CSD_CARD_TYPE_DDR_1_2V)
#define EXT_CSD_BUS_WIDTH_10 /* Card is in 1 bit mode */
#define EXT_CSD_BUS_WIDTH_41 /* Card is in 4 bit mode */
#define EXT_CSD_BUS_WIDTH_82 /* Card is in 8 bit mode */
+#define EXT_CSD_DDR_BUS_WIDTH_45 /* Card is in 4 bit DDR mode */
+#define EXT_CSD_DDR_BUS_WIDTH_86 /* Card is in 8 bit DDR mode */
#define EXT_CSD_BOOT_ACK_ENABLE(1 << 6)
#define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
--
1.7.9.5
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[U-Boot] [PATCHv5 06/14] ARM: dts: exynos: rename from EXYNOS5_DWMMC to EXYNOS_DWMMC
Exynos serise can be supported the dw-mmc controller.
So, it's good that used the general prefix as "_EXYNOS_DWMMC".
Signed-off-by: Jaehoon Chung
---
arch/arm/dts/exynos5.dtsi |8
doc/device-tree-bindings/exynos/dwmmc.txt |8
include/fdtdec.h |2 +-
lib/fdtdec.c |2 +-
4 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/dts/exynos5.dtsi b/arch/arm/dts/exynos5.dtsi
index f8c8741..a2b533a 100644
--- a/arch/arm/dts/exynos5.dtsi
+++ b/arch/arm/dts/exynos5.dtsi
@@ -136,7 +136,7 @@
mmc@1220 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "samsung,exynos5250-dwmmc";
+ compatible = "samsung,exynos-dwmmc";
reg = <0x1220 0x1000>;
interrupts = <0 75 0>;
};
@@ -144,7 +144,7 @@
mmc@1221 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "samsung,exynos5250-dwmmc";
+ compatible = "samsung,exynos-dwmmc";
reg = <0x1221 0x1000>;
interrupts = <0 76 0>;
};
@@ -152,7 +152,7 @@
mmc@1222 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "samsung,exynos5250-dwmmc";
+ compatible = "samsung,exynos-dwmmc";
reg = <0x1222 0x1000>;
interrupts = <0 77 0>;
};
@@ -160,7 +160,7 @@
mmc@1223 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "samsung,exynos5250-dwmmc";
+ compatible = "samsung,exynos-dwmmc";
reg = <0x1223 0x1000>;
interrupts = <0 78 0>;
};
diff --git a/doc/device-tree-bindings/exynos/dwmmc.txt
b/doc/device-tree-bindings/exynos/dwmmc.txt
index 566da3b..694d195 100644
--- a/doc/device-tree-bindings/exynos/dwmmc.txt
+++ b/doc/device-tree-bindings/exynos/dwmmc.txt
@@ -1,18 +1,18 @@
-* Exynos 5250 DWC_mobile_storage
+* Exynos DWC_mobile_storage
-The Exynos 5250 provides DWC_mobile_storage interface which supports
+The Exynos provides DWC_mobile_storage interface which supports
. Embedded Multimedia Cards (EMMC-version 4.5)
. Secure Digital memory (SD mem-version 2.0)
. Secure Digital I/O (SDIO-version 3.0)
. Consumer Electronics Advanced Transport Architecture (CE-ATA-version 1.1)
-The Exynos 5250 DWC_mobile_storage provides four channels.
+The Exynos DWC_mobile_storage provides four channels.
SOC specific and Board specific properties are channel specific.
Required SoC Specific Properties:
- compatible: should be
- - samsung,exynos5250-dwmmc: for exynos5250 platforms
+ - samsung,exynos-dwmmc: for exynos platforms
- reg: physical base address of the controller and length of memory mapped
region.
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 3196cf6..8c751fd 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -81,7 +81,7 @@ enum fdt_compat_id {
COMPAT_SAMSUNG_EXYNOS_FIMD, /* Exynos Display controller */
COMPAT_SAMSUNG_EXYNOS_MIPI_DSI, /* Exynos mipi dsi */
COMPAT_SAMSUNG_EXYNOS5_DP, /* Exynos Display port controller */
- COMPAT_SAMSUNG_EXYNOS5_DWMMC, /* Exynos5 DWMMC controller */
+ COMPAT_SAMSUNG_EXYNOS_DWMMC,/* Exynos DWMMC controller */
COMPAT_SAMSUNG_EXYNOS_MMC, /* Exynos MMC controller */
COMPAT_SAMSUNG_EXYNOS_SERIAL, /* Exynos UART */
COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 8ecb80f..35e91b4 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -55,7 +55,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(SAMSUNG_EXYNOS_FIMD, "samsung,exynos-fimd"),
COMPAT(SAMSUNG_EXYNOS_MIPI_DSI, "samsung,exynos-mipi-dsi"),
COMPAT(SAMSUNG_EXYNOS5_DP, "samsung,exynos5-dp"),
- COMPAT(SAMSUNG_EXYNOS5_DWMMC, "samsung,exynos5250-dwmmc"),
+ COMPAT(SAMSUNG_EXYNOS_DWMMC, "samsung,exynos-dwmmc"),
COMPAT(SAMSUNG_EXYNOS_MMC, "samsung,exynos-mmc"),
COMPAT(SAMSUNG_EXYNOS_SERIAL, "samsung,exynos4210-uart"),
COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686_pmic"),
--
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[U-Boot] [PATCHv5 10/14] mmc: dw_mmc: support the DDR mode
Support the DDR mode at dw-mmc controller
Signed-off-by: Jaehoon Chung
Tested-by: Lukasz Majewski
Acked-by: Lukasz Majewski
---
drivers/mmc/dw_mmc.c | 12 ++--
include/dwmmc.h |3 +++
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index eb4e2be..5bf36a0 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -284,8 +284,8 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32
freq)
static void dwmci_set_ios(struct mmc *mmc)
{
- struct dwmci_host *host = mmc->priv;
- u32 ctype;
+ struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
+ u32 ctype, regs;
debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock);
@@ -304,6 +304,14 @@ static void dwmci_set_ios(struct mmc *mmc)
dwmci_writel(host, DWMCI_CTYPE, ctype);
+ regs = dwmci_readl(host, DWMCI_UHS_REG);
+ if (mmc->card_caps & MMC_MODE_DDR_52MHz)
+ regs |= DWMCI_DDR_MODE;
+ else
+ regs &= DWMCI_DDR_MODE;
+
+ dwmci_writel(host, DWMCI_UHS_REG, regs);
+
if (host->clksel)
host->clksel(host);
}
diff --git a/include/dwmmc.h b/include/dwmmc.h
index 14c7db8..b67f11b 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -123,6 +123,9 @@
#define DWMCI_BMOD_IDMAC_FB(1 << 1)
#define DWMCI_BMOD_IDMAC_EN(1 << 7)
+/* UHS register */
+#define DWMCI_DDR_MODE (1 << 16)
+
/* quirks */
#define DWMCI_QUIRK_DISABLE_SMU(1 << 0)
--
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[U-Boot] [PATCHv5 12/14] mmc: exynos_dw_mmc: enable the DDR mode
Set the ddr mode capability by default. Signed-off-by: Jaehoon Chung Tested-by: Lukasz Majewski Acked-by: Lukasz Majewski --- drivers/mmc/exynos_dw_mmc.c |1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index 28941ad..d96dfe1 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -95,6 +95,7 @@ static int exynos_dwmci_core_init(struct dwmci_host *host, int index) host->clksel_val = DWMMC_MMC2_CLKSEL_VAL; } + host->caps = MMC_MODE_DDR_52MHz; host->clksel = exynos_dwmci_clksel; host->dev_index = index; host->get_mmc_clk = exynos_dwmci_get_clk; -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCHv5 11/14] ARM: dts: exnyos: enable dw-mmc controller
Enabled the dw-mmc controller.
Signed-off-by: Jaehoon Chung
Tested-by: Lukasz Majewski
Acked-by: Lukasz Majewski
---
arch/arm/dts/exynos4412-trats2.dts |6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/exynos4412-trats2.dts
b/arch/arm/dts/exynos4412-trats2.dts
index 5269ae6..cc58c87 100644
--- a/arch/arm/dts/exynos4412-trats2.dts
+++ b/arch/arm/dts/exynos4412-trats2.dts
@@ -417,6 +417,7 @@
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
pwr-gpios = <&gpio 0xB2 0>;
+ status = "disabled";
};
sdhci@1252 {
@@ -435,8 +436,11 @@
dwmmc@1255 {
samsung,bus-width = <8>;
- samsung,timing = <0 1 0>;
+ samsung,timing = <2 1 0>;
pwr-gpios = <&gpio 0xB2 0>;
+ fifoth_val = <0x203f0040>;
+ bus_hz = <4>;
+ div = <0x3>;
index = <4>;
};
};
--
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[U-Boot] [PATCHv5 01/14] arm: exynos: pinmux: add sdmmc4 gpio configratuion
From: Beomho Seo
For use dwmmc controller at exynos4, add SDMMC4 gpio configuration.
Signed-off-by: Beomho Seo
Signed-off-by: Jaehoon Chung
Tested-by: Piotr Wilczek
Cc: Lukasz Majewski
Cc: Piotr Wilczek
Cc: Minkyu Kang
---
arch/arm/cpu/armv7/exynos/pinmux.c | 35 +--
1 file changed, 29 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
b/arch/arm/cpu/armv7/exynos/pinmux.c
index ee7c2e5..86a0c75 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -573,15 +573,26 @@ static void exynos4_i2c_config(int peripheral, int flags)
static int exynos4_mmc_config(int peripheral, int flags)
{
int i, start = 0, start_ext = 0;
+ unsigned int func, ext_func;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
start = EXYNOS4_GPIO_K00;
start_ext = EXYNOS4_GPIO_K13;
+ func = S5P_GPIO_FUNC(0x2);
+ ext_func = S5P_GPIO_FUNC(0x3);
break;
case PERIPH_ID_SDMMC2:
start = EXYNOS4_GPIO_K20;
start_ext = EXYNOS4_GPIO_K33;
+ func = S5P_GPIO_FUNC(0x2);
+ ext_func = S5P_GPIO_FUNC(0x3);
+ break;
+ case PERIPH_ID_SDMMC4:
+ start = EXYNOS4_GPIO_K00;
+ start_ext = EXYNOS4_GPIO_K13;
+ func = S5P_GPIO_FUNC(0x3);
+ ext_func = S5P_GPIO_FUNC(0x4);
break;
default:
return -1;
@@ -589,13 +600,14 @@ static int exynos4_mmc_config(int peripheral, int flags)
for (i = start; i < (start + 7); i++) {
if (i == (start + 2))
continue;
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(i, func);
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
+ /* SDMMC2 do not use 8bit mode at exynos4 */
if (flags & PINMUX_FLAG_8BIT_MODE) {
for (i = start_ext; i < (start_ext + 4); i++) {
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(i, ext_func);
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
@@ -676,15 +688,26 @@ static void exynos4x12_i2c_config(int peripheral, int
flags)
static int exynos4x12_mmc_config(int peripheral, int flags)
{
int i, start = 0, start_ext = 0;
+ unsigned int func, ext_func;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
start = EXYNOS4X12_GPIO_K00;
start_ext = EXYNOS4X12_GPIO_K13;
+ func = S5P_GPIO_FUNC(0x2);
+ ext_func = S5P_GPIO_FUNC(0x3);
break;
case PERIPH_ID_SDMMC2:
start = EXYNOS4X12_GPIO_K20;
start_ext = EXYNOS4X12_GPIO_K33;
+ func = S5P_GPIO_FUNC(0x2);
+ ext_func = S5P_GPIO_FUNC(0x3);
+ break;
+ case PERIPH_ID_SDMMC4:
+ start = EXYNOS4_GPIO_K00;
+ start_ext = EXYNOS4_GPIO_K13;
+ func = S5P_GPIO_FUNC(0x3);
+ ext_func = S5P_GPIO_FUNC(0x4);
break;
default:
return -1;
@@ -692,13 +715,13 @@ static int exynos4x12_mmc_config(int peripheral, int
flags)
for (i = start; i < (start + 7); i++) {
if (i == (start + 2))
continue;
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(i, func);
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
if (flags & PINMUX_FLAG_8BIT_MODE) {
for (i = start_ext; i < (start_ext + 4); i++) {
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(i, ext_func);
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
@@ -759,10 +782,10 @@ static int exynos4_pinmux_config(int peripheral, int
flags)
break;
case PERIPH_ID_SDMMC0:
case PERIPH_ID_SDMMC2:
+ case PERIPH_ID_SDMMC4:
return exynos4_mmc_config(peripheral, flags);
case PERIPH_ID_SDMMC1:
case PERIPH_ID_SDMMC3:
- case PERIPH_ID_SDMMC4:
debug("SDMMC device %d not implemented\n", peripheral);
return -1;
default:
@@ -794,10 +817,10 @@ static int exynos4x12_pinmux_config(int peripheral, int
flags)
break;
case PERIPH_ID_SDMMC0:
case PERIPH_ID_SDMMC2:
+ case PERIPH_ID_SDMMC4:
return exynos4x12_mmc_config(peripheral, flags);
case PERIPH_ID_SDMMC1:
case PERIPH_ID_SDMMC3:
- case PERIPH_ID_SDMMC4:
[U-Boot] [PATCHv5 04/14] ARM: exynos: board: change the mmc/sd init sequence
Exynos4 can be used the dwmmc controller for eMMC.
Then it needs to check dwmmc_init() at first.
Signed-off-by: Jaehoon Chung
Reviewed-by: Lukasz Majewski
Tested-by: Lukasz Majewski
Acked-by: Lukasz Majewski
---
board/samsung/common/board.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index de154e0..9dc7c83 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -243,13 +243,6 @@ int board_eth_init(bd_t *bis)
int board_mmc_init(bd_t *bis)
{
int ret;
-
-#ifdef CONFIG_SDHCI
- /* mmc initializattion for available channels */
- ret = exynos_mmc_init(gd->fdt_blob);
- if (ret)
- debug("mmc init failed\n");
-#endif
#ifdef CONFIG_DWMMC
/* dwmmc initializattion for available channels */
ret = exynos_dwmmc_init(gd->fdt_blob);
@@ -257,6 +250,12 @@ int board_mmc_init(bd_t *bis)
debug("dwmmc init failed\n");
#endif
+#ifdef CONFIG_SDHCI
+ /* mmc initializattion for available channels */
+ ret = exynos_mmc_init(gd->fdt_blob);
+ if (ret)
+ debug("mmc init failed\n");
+#endif
return ret;
}
#endif
--
1.7.9.5
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[U-Boot] [PATCHv5 13/14] ARM: exynos4: enable the dwmmc configuration
Signed-off-by: Jaehoon Chung Tested-by: Lukasz Majewski Acked-by: Lukasz Majewski --- include/configs/exynos4-dt.h |3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/exynos4-dt.h b/include/configs/exynos4-dt.h index cbd2d20..0c560ae 100644 --- a/include/configs/exynos4-dt.h +++ b/include/configs/exynos4-dt.h @@ -44,6 +44,9 @@ #define CONFIG_S5P_SDHCI #define CONFIG_SDHCI #define CONFIG_MMC_SDMA +#define CONFIG_DWMMC +#define CONFIG_EXYNOS_DWMMC +#define CONFIG_BOUNCE_BUFFER #define CONFIG_MMC_DEFAULT_DEV 0 /* PWM */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCHv5 02/14] arm: exynos: clock: Remove exynos4x12_set_mmc_clk function
From: Beomho Seo
exynos4x12_set_mmc_clk function have been removed.
Because, exynos4x12_clock and exynos4_clock return same div_fsys* value.
Signed-off-by: Beomho Seo
Signed-off-by: Jaehoon Chung
Tested-by: Piotr Wilczek
Cc: Lukasz Majewski
Cc: Piotr Wilczek
Cc: Minkyu Kang
---
arch/arm/cpu/armv7/exynos/clock.c | 29 +
1 file changed, 1 insertion(+), 28 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 1fea4d6..2c2029a 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -893,30 +893,6 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned
int div)
(div & 0xff) << ((dev_index << 4) + 8));
}
-/* exynos4x12: set the mmc clock */
-static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
-{
- struct exynos4x12_clock *clk =
- (struct exynos4x12_clock *)samsung_get_base_clock();
- unsigned int addr;
-
- /*
-* CLK_DIV_FSYS1
-* MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
-* CLK_DIV_FSYS2
-* MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
-*/
- if (dev_index < 2) {
- addr = (unsigned int)&clk->div_fsys1;
- } else {
- addr = (unsigned int)&clk->div_fsys2;
- dev_index -= 2;
- }
-
- clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
- (div & 0xff) << ((dev_index << 4) + 8));
-}
-
/* exynos5: set the mmc clock */
static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
{
@@ -1612,10 +1588,7 @@ void set_mmc_clk(int dev_index, unsigned int div)
else
exynos5_set_mmc_clk(dev_index, div);
} else {
- if (proid_is_exynos4412())
- exynos4x12_set_mmc_clk(dev_index, div);
- else
- exynos4_set_mmc_clk(dev_index, div);
+ exynos4_set_mmc_clk(dev_index, div);
}
}
--
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[U-Boot] [PATCHv5 07/14] mmc: exynos_dw_mmc: restore the property into host
Restore the platdata(property of dt) into host struct.
Then data's information is maintained and reused anywhere.
Signed-off-by: Jaehoon Chung
Tested-by: Lukasz Majewski
Acked-by: Lukasz Majewski
---
drivers/mmc/exynos_dw_mmc.c | 204 +++
include/dwmmc.h |2 +
2 files changed, 133 insertions(+), 73 deletions(-)
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index de8cdcc..28941ad 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -13,6 +13,8 @@
#include
#include
#include
+#include
+#include
#defineDWMMC_MAX_CH_NUM4
#defineDWMMC_MAX_FREQ 5200
@@ -44,7 +46,11 @@ unsigned int exynos_dwmci_get_clk(struct dwmci_host *host)
& DWMCI_DIVRATIO_MASK) + 1;
sclk = get_mmc_clk(host->dev_index);
- return sclk / clk_div;
+ /*
+* Assume to know divider value.
+* When clock unit is broken, need to set "host->div"
+*/
+ return sclk / clk_div / (host->div + 1);
}
static void exynos_dwmci_board_init(struct dwmci_host *host)
@@ -60,45 +66,32 @@ static void exynos_dwmci_board_init(struct dwmci_host *host)
}
}
-/*
- * This function adds the mmc channel to be registered with mmc core.
- * index - mmc channel number.
- * regbase - register base address of mmc channel specified in 'index'.
- * bus_width - operating bus width of mmc channel specified in 'index'.
- * clksel -value to be written into CLKSEL register in case of FDT.
- * NULL in case od non-FDT.
- */
-int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
+static int exynos_dwmci_core_init(struct dwmci_host *host, int index)
{
- struct dwmci_host *host = NULL;
unsigned int div;
unsigned long freq, sclk;
- host = malloc(sizeof(struct dwmci_host));
- if (!host) {
- printf("dwmci_host malloc fail!\n");
- return 1;
- }
+
+ if (host->bus_hz)
+ freq = host->bus_hz;
+ else
+ freq = DWMMC_MAX_FREQ;
+
/* request mmc clock vlaue of 52MHz. */
- freq = 5200;
sclk = get_mmc_clk(index);
div = DIV_ROUND_UP(sclk, freq);
/* set the clock divisor for mmc */
set_mmc_clk(index, div);
host->name = "EXYNOS DWMMC";
- host->ioaddr = (void *)regbase;
- host->buswidth = bus_width;
#ifdef CONFIG_EXYNOS5420
host->quirks = DWMCI_QUIRK_DISABLE_SMU;
#endif
host->board_init = exynos_dwmci_board_init;
- if (clksel) {
- host->clksel_val = clksel;
- } else {
- if (0 == index)
+ if (!host->clksel_val) {
+ if (index == 0)
host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;
- if (2 == index)
+ else if (index == 2)
host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;
}
@@ -113,69 +106,134 @@ int exynos_dwmci_add_port(int index, u32 regbase, int
bus_width, u32 clksel)
return 0;
}
+/*
+ * This function adds the mmc channel to be registered with mmc core.
+ * index - mmc channel number.
+ * regbase - register base address of mmc channel specified in 'index'.
+ * bus_width - operating bus width of mmc channel specified in 'index'.
+ * clksel -value to be written into CLKSEL register in case of FDT.
+ * NULL in case od non-FDT.
+ */
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
+{
+ struct dwmci_host *host = NULL;
+
+ host = malloc(sizeof(struct dwmci_host));
+ if (!host) {
+ error("dwmci_host malloc fail!\n");
+ return -ENOMEM;
+ }
+
+ host->ioaddr = (void *)regbase;
+ host->buswidth = bus_width;
+
+ if (clksel)
+ host->clksel_val = clksel;
+
+ return exynos_dwmci_core_init(host, index);
+}
+
#ifdef CONFIG_OF_CONTROL
-int exynos_dwmmc_init(const void *blob)
+static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM];
+
+static int do_dwmci_init(struct dwmci_host *host)
{
- int index, bus_width;
- int node_list[DWMMC_MAX_CH_NUM];
- int err = 0, dev_id, flag, count, i;
- u32 clksel_val, base, timing[3];
+ int index, flag, err;
- count = fdtdec_find_aliases_for_id(blob, "mmc",
- COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,
- DWMMC_MAX_CH_NUM);
+ index = host->dev_index;
- for (i = 0; i < count; i++) {
- int node = node_list[i];
+ flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
+ err = exynos_pinmux_config(host->dev_id, flag);
+ if (err) {
+ debug("DWMMC not configure\n");
+ return err;
+ }
- if (node <= 0)
-
[U-Boot] [PATCHv5 05/14] ARM: exynos: clock: modify the set_mmc_clk for exynos4
Modified the mmc_set_clock for eynos4.
The goal of this patch is that fsys-div register should be reset.
And retore the div-value, not using the value of lowlevel_init.
(For using SDMMC4, this patch is needs)
Signed-off-by: Jaehoon Chung
Tested-by: Lukasz Majewski
Acked-by: Lukasz Majewski
---
arch/arm/cpu/armv7/exynos/clock.c | 16 +++-
arch/arm/include/asm/arch-exynos/clk.h |5 +
2 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 2c2029a..400d134 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -869,7 +869,7 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int
div)
{
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
- unsigned int addr;
+ unsigned int addr, clear_bit, set_bit;
/*
* CLK_DIV_FSYS1
@@ -877,20 +877,26 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned
int div)
* CLK_DIV_FSYS2
* MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
* CLK_DIV_FSYS3
-* MMC4_PRE_RATIO [15:8]
+* MMC4_RATIO [3:0]
*/
if (dev_index < 2) {
addr = (unsigned int)&clk->div_fsys1;
- } else if (dev_index == 4) {
+ clear_bit = MASK_PRE_RATIO(dev_index);
+ set_bit = SET_PRE_RATIO(dev_index, div);
+ } else if (dev_index == 4) {
addr = (unsigned int)&clk->div_fsys3;
dev_index -= 4;
+ /* MMC4 is controlled with the MMC4_RATIO value */
+ clear_bit = MASK_RATIO(dev_index);
+ set_bit = SET_RATIO(dev_index, div);
} else {
addr = (unsigned int)&clk->div_fsys2;
dev_index -= 2;
+ clear_bit = MASK_PRE_RATIO(dev_index);
+ set_bit = SET_PRE_RATIO(dev_index, div);
}
- clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
- (div & 0xff) << ((dev_index << 4) + 8));
+ clrsetbits_le32(addr, clear_bit, set_bit);
}
/* exynos5: set the mmc clock */
diff --git a/arch/arm/include/asm/arch-exynos/clk.h
b/arch/arm/include/asm/arch-exynos/clk.h
index cdeef32..ffbc07e 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -16,6 +16,11 @@
#define BPLL 5
#define RPLL 6
+#define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8))
+#define MASK_RATIO(x) (0xf << (x << 4))
+#define SET_PRE_RATIO(x, y)((y & 0xff) << ((x << 4) + 8))
+#define SET_RATIO(x, y)((y & 0xf) << (x << 4))
+
enum pll_src_bit {
EXYNOS_SRC_MPLL = 6,
EXYNOS_SRC_EPLL,
--
1.7.9.5
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[U-Boot] [PATCHv5 00/14] mmc: exynos: code cleanup and support DDR mode
If card and host are supported DDR mode, then it can be used the DDR mode. This patch-set has dependency about beomho's patch-set. (Based-on u-boot-samsung repository) It's result for loading image. sdhci controller ->5260488 bytes read in 259 ms (19.4 MiB/s) dwmmc controller without DDR mode -> 5260488 bytes read in 202 ms (24.8 MiB/s) dwmmc controller with DDR mode -> 5260488 bytes read in 118 ms (42.5 MiB/s) Download the 400M image with lthor. sdhci controller -> 59.4sec (Avg 6.95 MB/s) dwmmc controller without DDR mode -> 61.6sec (Avg 6.72MB/s) dwmmc controller with DDR mode -> 60.4sec (Avg 6.85MB/s) Beomho Seo (3): arm: exynos: pinmux: add sdmmc4 gpio configratuion arm: exynos: clock: Remove exynos4x12_set_mmc_clk function board: trats2: Enable device tree on Trats2 Jaehoon Chung (11): ARM: exynos: board: change the mmc/sd init sequence ARM: exynos: clock: modify the set_mmc_clk for exynos4 ARM: dts: exynos: rename from EXYNOS5_DWMMC to EXYNOS_DWMMC mmc: exynos_dw_mmc: restore the property into host mmc: remove the unnecessary define and fix the wrong bit control mmc: support the DDR mode for eMMC mmc: dw_mmc: support the DDR mode ARM: dts: exnyos: enable dw-mmc controller mmc: exynos_dw_mmc: enable the DDR mode ARM: exynos4: enable the dwmmc configuration mmc: s5p_sdhci: add the s5p_sdhci_core_init function arch/arm/cpu/armv7/exynos/clock.c | 45 ++- arch/arm/cpu/armv7/exynos/pinmux.c| 35 - arch/arm/dts/exynos4.dtsi |8 ++ arch/arm/dts/exynos4412-trats2.dts| 12 ++ arch/arm/dts/exynos5.dtsi |8 +- arch/arm/include/asm/arch-exynos/clk.h|5 + board/samsung/common/board.c | 13 +- doc/device-tree-bindings/exynos/dwmmc.txt |8 +- drivers/mmc/dw_mmc.c | 12 +- drivers/mmc/exynos_dw_mmc.c | 205 +++-- drivers/mmc/mmc.c | 16 ++- drivers/mmc/s5p_sdhci.c | 42 +++--- include/configs/exynos4-dt.h |3 + include/dwmmc.h |5 + include/fdtdec.h |2 +- include/mmc.h | 25 ++-- lib/fdtdec.c |2 +- 17 files changed, 275 insertions(+), 171 deletions(-) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCHv5 03/14] board: trats2: Enable device tree on Trats2
From: Beomho Seo
This patch add dwmmc emmc controller node on exynos4 and exynos4412 device tree.
Signed-off-by: Beomho Seo
Signed-off-by: Jaehoon Chung
Tested-by: Piotr Wilczek
Cc: Lukasz Majewski
Cc: Piotr Wilczek
Cc: Minkyu Kang
---
arch/arm/dts/exynos4.dtsi |8
arch/arm/dts/exynos4412-trats2.dts |8
2 files changed, 16 insertions(+)
diff --git a/arch/arm/dts/exynos4.dtsi b/arch/arm/dts/exynos4.dtsi
index 71dc7eb..110eb43 100644
--- a/arch/arm/dts/exynos4.dtsi
+++ b/arch/arm/dts/exynos4.dtsi
@@ -128,6 +128,14 @@
interrupts = <0 78 0>;
};
+ dwmmc@1255 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos-dwmmc";
+ reg = <0x1255 0x1000>;
+ interrupts = <0 131 0>;
+ };
+
gpio: gpio {
gpio-controller;
#gpio-cells = <2>;
diff --git a/arch/arm/dts/exynos4412-trats2.dts
b/arch/arm/dts/exynos4412-trats2.dts
index 1596f83..5269ae6 100644
--- a/arch/arm/dts/exynos4412-trats2.dts
+++ b/arch/arm/dts/exynos4412-trats2.dts
@@ -31,6 +31,7 @@
console = "/serial@1382";
mmc0 = "sdhci@1251";
mmc2 = "sdhci@1253";
+ mmc4 = "dwmmc@1255";
};
i2c@138d {
@@ -431,4 +432,11 @@
sdhci@1254 {
status = "disabled";
};
+
+ dwmmc@1255 {
+ samsung,bus-width = <8>;
+ samsung,timing = <0 1 0>;
+ pwr-gpios = <&gpio 0xB2 0>;
+ index = <4>;
+ };
};
--
1.7.9.5
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Re: [U-Boot] [PATCH 3/8] mxc_i2c: Use the 3th i2c channel for imx25
Hello Thomas, Am 15.05.2014 16:34, schrieb die...@gmx.de: From: Thomas Diener Signed-off-by: Thomas Diener --- drivers/i2c/mxc_i2c.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) as this I think goes through the imx tree: Acked-by: Heiko Schocher bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] examples: select libgcc for non-default architecture
Dear Alexey Brodkin, In message <1400176075-8709-1-git-send-email-abrod...@synopsys.com> you wrote: > In case of multilib-enabled toolchains if default architecture differ from > the one examples are being built for linker will fail to link example object > files with libgcc of another (non-compatible) architecture. > > Interesting enough for years in main Makefile we used CFLAGS/c_flags for this > but not for examples. > > So fixing it now. > > Signed-off-by: Alexey Brodkin > > Cc: Masahiro Yamada > Cc: Tom Rini > --- > examples/standalone/Makefile | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile > index 9ab5446..7234f30 100644 > --- a/examples/standalone/Makefile > +++ b/examples/standalone/Makefile > @@ -38,7 +38,8 @@ targets += $(patsubst $(obj)/%,%,$(LIB)) $(COBJS) > $(LIBOBJS-y) > LIBOBJS := $(addprefix $(obj)/,$(LIBOBJS-y)) > ELF := $(addprefix $(obj)/,$(ELF)) > > -gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) > +gcclibdir := $(shell dirname \ > +`$(CC) $(PLATFORM_CPPFLAGS) -print-libgcc-file-name`) Should this not also take CONFIG_USE_PRIVATE_LIBGCC into account ? I. e. use PLATFORM_LIBGCC ? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Business is like a wheelbarrow. Nothing ever happens until you start pushing. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH][v3] powerpc/t4qds: Add alternate serdes protocols to align with A-007186
From: Shaohui Xie
A-007186: SerDes PLL is calibrated at reset. It is possible for jitter to
increase and cause the PLL to unlock when the temperature delta from the
time the PLL is calibrated exceeds +56C/-66C when using X VDD of 1.35 V
(or +70C/-80C when using XnVDD of 1.5 V). No issues are seen with LC
VCO. Only the protocols using Ring VCOs are impacted.
Workaround:
For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring VCO, this need
to use alternate serdes protocols. The alternate option has the same
functionality as the original option; the only difference being LC VCO
rather than Ring VCO.
Signed-off-by: Shaohui Xie
---
changes for V3:
update t4_rcw.cfg.
changes for V2:
refined commit message.
arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 172
board/freescale/t4qds/eth.c | 20
board/freescale/t4qds/t4240qds.c| 27 +
board/freescale/t4qds/t4_rcw.cfg| 4 +-
4 files changed, 221 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index 1f99a0a..74c4c81 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -30,22 +30,41 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
+ {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
{28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+ {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
{36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+ {37, {NONE, NONE, QSGMII_FM1_B, NONE,
+ NONE, NONE, QSGMII_FM1_A, NONE} },
{38, {NONE, NONE, QSGMII_FM1_B, NONE,
NONE, NONE, QSGMII_FM1_A, NONE}},
+ {39, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ NONE, NONE, QSGMII_FM1_A, NONE} },
{40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
NONE, NONE, QSGMII_FM1_A, NONE}},
+ {45, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ NONE, NONE, QSGMII_FM1_A, NONE} },
{46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
NONE, NONE, QSGMII_FM1_A, NONE}},
+ {47, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ NONE, NONE, QSGMII_FM1_A, NONE} },
{48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
NONE, NONE, QSGMII_FM1_A, NONE}},
@@ -65,10 +84,18 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
+ {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -77,10 +104,18 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+
Re: [U-Boot] [PATCH] examples: select libgcc for non-default architecture
Hi Alexey, On Thu, 15 May 2014 21:47:55 +0400 Alexey Brodkin wrote: > In case of multilib-enabled toolchains if default architecture differ from > the one examples are being built for linker will fail to link example object > files with libgcc of another (non-compatible) architecture. > > Interesting enough for years in main Makefile we used CFLAGS/c_flags for this > but not for examples. > > So fixing it now. > > Signed-off-by: Alexey Brodkin > > Cc: Masahiro Yamada > Cc: Tom Rini > --- > examples/standalone/Makefile | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile > index 9ab5446..7234f30 100644 > --- a/examples/standalone/Makefile > +++ b/examples/standalone/Makefile > @@ -38,7 +38,8 @@ targets += $(patsubst $(obj)/%,%,$(LIB)) $(COBJS) > $(LIBOBJS-y) > LIBOBJS := $(addprefix $(obj)/,$(LIBOBJS-y)) > ELF := $(addprefix $(obj)/,$(ELF)) > > -gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) > +gcclibdir := $(shell dirname \ > +`$(CC) $(PLATFORM_CPPFLAGS) -print-libgcc-file-name`) > > # For PowerPC there's no need to compile standalone applications as a > # relocatable executable. The relocation data is not needed, and > -- > 1.9.0 Looks good to me. Acked-by: Masahiro Yamada Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Pull request: u-boot-sh/rmobile into u-boot-arm/master
Hi, Albert.
Could you apply this PR?
Best regards,
Nobuhiro
2014-05-02 5:14 GMT+09:00 Nobuhiro Iwamatsu :
> Dear Albert Aribaud,
>
> Please pull u-boot-sh/rmobile into u-boot-arm/master.
>
> The following changes since commit c9aab0f9dd23fddcebf5984dc19e62b514e759a7:
>
> Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' (2014-04-21
> 21:01:35 +0200)
>
> are available in the git repository at:
>
> git://git.denx.de/u-boot-sh.git rmobile
>
> for you to fetch changes up to 8d18bcfd439b8422ab3bada2001cc2abd525d9f8:
>
> arm: rmobile: lager: Remove MACH_TYPE_LAGER and CONFIG_MACH_TYPE
> (2014-04-28 04:35:12 +0900)
>
>
> Nobuhiro Iwamatsu (22):
> arm: rmobile: Coordinate the common part of the header file of
> r8a7790 and r8a7791
> arm: rmobile: r8a779x: Fix L2 cache init and latency setting
> arm: rmobile: koelsch: Change name of structure
> arm: rmobile: koelsch: Remove NOR-Flash support
> arm: rmobile: lager: Change name of the structure
> arm: rmobile: lager: Remove NOR-Flash support
> arm: rmobile: Merge functions to get the CPU information of
> R8A7790 and R8A7791
> arm: rmobile: Add 1 to value of the CPU revision in
> rmobile_get_cpu_rev_integer()
> arm: rmobile: Add rmobile_get_cpu_rev_fraction() for R-Car SoCs
> arm: rmobile: Add prototype for function to get the CPU
> information to rmobile.h
> arm: rmobile: Update print_cpuinfo function
> arm: rmobile: r8a7790: Add support ES2 revision
> arm: rmobile: r8a7791: Add support ES2 revision
> arm: rmobile: keolsch: Add support ES2 revision of R8A7791
> arm: rmobile: lager: Update QoS initialization to version 0.955
> arm: rmobile: koelsch: Update QoS initialization
> arm: rmobile: koelsch: Update calculation of CONFIG_SH_TMU_CLK_FREQ
> arm: rmobile: Add register infomation of PLL regsiter
> arm: rmobile: koelsch: Change to maximum CPU frequency
> arm: rmobile: lager: Update calculation of CONFIG_SH_TMU_CLK_FREQ
> arm: rmobile: lager: Change to maximum CPU frequency
> arm: rmobile: lager: Remove MACH_TYPE_LAGER and CONFIG_MACH_TYPE
>
> arch/arm/cpu/armv7/rmobile/Makefile| 4 +-
> arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c | 29 -
> .../{cpu_info-r8a7790.c => cpu_info-rcar.c}| 12 +-
> arch/arm/cpu/armv7/rmobile/cpu_info.c | 49 +-
> arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S| 20 +-
> arch/arm/include/asm/arch-rmobile/r8a7790.h| 609 +---
> arch/arm/include/asm/arch-rmobile/r8a7791.h| 626 +---
> arch/arm/include/asm/arch-rmobile/rcar-base.h | 637
> +
> arch/arm/include/asm/arch-rmobile/rmobile.h| 6 +
> board/renesas/koelsch/koelsch.c| 194 +--
> board/renesas/koelsch/qos.c| 404 +++--
> board/renesas/lager/lager.c| 196 +--
> board/renesas/lager/qos.c | 236
> boards.cfg | 2 -
> include/configs/koelsch.h | 36 +-
> include/configs/lager.h| 40 +-
> 16 files changed, 1092 insertions(+), 2008 deletions(-)
> delete mode 100644 arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c
> rename arch/arm/cpu/armv7/rmobile/{cpu_info-r8a7790.c => cpu_info-rcar.c}
> (50%)
> create mode 100644 arch/arm/include/asm/arch-rmobile/rcar-base.h
>
> --
> Nobuhiro Iwamatsu
>iwamatsu at {nigauri.org / debian.org}
>GPG ID: 40AD1FA6
--
Nobuhiro Iwamatsu
iwamatsu at {nigauri.org / debian.org}
GPG ID: 40AD1FA6
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Re: [U-Boot] [RESEND PATCHv4 07/14] mmc: exynos_dw_mmc: restore the property into host
On 15/05/14 17:57, Jaehoon Chung wrote:
> Restore the platdata(property of dt) into host struct.
> Then data's information is maintained and reused anywhere.
>
> Signed-off-by: Jaehoon Chung
> Tested-by: Lukasz Majewski
> Acked-by: Lukasz Majewski
> ---
> drivers/mmc/exynos_dw_mmc.c | 205
> ---
> include/dwmmc.h |2 +
> 2 files changed, 135 insertions(+), 72 deletions(-)
>
> diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
> index de8cdcc..99047a7 100644
> --- a/drivers/mmc/exynos_dw_mmc.c
> +++ b/drivers/mmc/exynos_dw_mmc.c
> @@ -13,6 +13,8 @@
> #include
> #include
> #include
> +#include
> +#include
>
> #define DWMMC_MAX_CH_NUM4
> #define DWMMC_MAX_FREQ 5200
> @@ -44,6 +46,13 @@ unsigned int exynos_dwmci_get_clk(struct dwmci_host *host)
> & DWMCI_DIVRATIO_MASK) + 1;
> sclk = get_mmc_clk(host->dev_index);
>
> + /*
> + * Assume to know divider value.
> + * When clock unit is broken, need to set "host->div"
> + */
> + if (host->div)
> + sclk /= (host->div + 1);
> +
> return sclk / clk_div;
then, it can be
return sclk / clk_div / (host->div +1);
> }
>
> @@ -60,45 +69,32 @@ static void exynos_dwmci_board_init(struct dwmci_host
> *host)
> }
> }
>
> -/*
> - * This function adds the mmc channel to be registered with mmc core.
> - * index - mmc channel number.
> - * regbase - register base address of mmc channel specified in 'index'.
> - * bus_width - operating bus width of mmc channel specified in 'index'.
> - * clksel - value to be written into CLKSEL register in case of FDT.
> - * NULL in case od non-FDT.
> - */
> -int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
> +static int exynos_dwmci_core_init(struct dwmci_host *host, int index)
> {
> - struct dwmci_host *host = NULL;
> unsigned int div;
> unsigned long freq, sclk;
> - host = malloc(sizeof(struct dwmci_host));
> - if (!host) {
> - printf("dwmci_host malloc fail!\n");
> - return 1;
> - }
> +
> + if (host->bus_hz)
> + freq = host->bus_hz;
> + else
> + freq = DWMMC_MAX_FREQ;
> +
> /* request mmc clock vlaue of 52MHz. */
> - freq = 5200;
> sclk = get_mmc_clk(index);
> div = DIV_ROUND_UP(sclk, freq);
> /* set the clock divisor for mmc */
> set_mmc_clk(index, div);
>
> host->name = "EXYNOS DWMMC";
> - host->ioaddr = (void *)regbase;
> - host->buswidth = bus_width;
> #ifdef CONFIG_EXYNOS5420
> host->quirks = DWMCI_QUIRK_DISABLE_SMU;
> #endif
> host->board_init = exynos_dwmci_board_init;
>
> - if (clksel) {
> - host->clksel_val = clksel;
> - } else {
> - if (0 == index)
> + if (!host->clksel_val) {
> + if (index == 0)
> host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;
> - if (2 == index)
> + if (index == 2)
else if?
or you can use switch..case.
> host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;
> }
>
> @@ -113,69 +109,134 @@ int exynos_dwmci_add_port(int index, u32 regbase, int
> bus_width, u32 clksel)
> return 0;
> }
>
> +/*
> + * This function adds the mmc channel to be registered with mmc core.
> + * index - mmc channel number.
> + * regbase - register base address of mmc channel specified in 'index'.
> + * bus_width - operating bus width of mmc channel specified in 'index'.
> + * clksel - value to be written into CLKSEL register in case of FDT.
> + * NULL in case od non-FDT.
> + */
> +int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
> +{
> + struct dwmci_host *host = NULL;
> +
> + host = malloc(sizeof(struct dwmci_host));
> + if (!host) {
> + error("dwmci_host malloc fail!\n");
> + return -ENOMEM;
> + }
> +
> + host->ioaddr = (void *)regbase;
> + host->buswidth = bus_width;
> +
> + if (clksel)
> + host->clksel_val = clksel;
> +
> + return exynos_dwmci_core_init(host, index);
> +}
> +
> #ifdef CONFIG_OF_CONTROL
> -int exynos_dwmmc_init(const void *blob)
> +struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM];
static struct?
> +
> +static int do_dwmci_init(struct dwmci_host *host)
> {
> - int index, bus_width;
> - int node_list[DWMMC_MAX_CH_NUM];
> - int err = 0, dev_id, flag, count, i;
> - u32 clksel_val, base, timing[3];
> + int index, flag = 0, err = 0;
= 0; unnecessary.
>
> - count = fdtdec_find_aliases_for_id(blob, "mmc",
> - COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,
> - DWMMC_MAX_CH_NUM);
> + index = host->dev_index;
>
> - for (i = 0; i < count; i++) {
> - int node = node_list[i];
> + flag =
Re: [U-Boot] please pull u-boot-samsung master
Hi Albert, On 15/05/14 23:28, Albert ARIBAUD wrote: > Hi Minkyu, > > On Tue, 13 May 2014 19:47:35 +0900, Minkyu Kang > wrote: > >> Dear Albert, >> >> The following changes since commit 7904b70885f3c589c239f6ac978f299a6744557f: >> >> ARM: highbank: use default prompt (2014-05-02 11:43:25 +0200) >> >> are available in the git repository at: >> >> http://git.denx.de/u-boot-samsung >> >> for you to fetch changes up to 9b97b727dcfbdc02a0a78e4c1d81670742f28784: > > Underway. Note: > > remote: error: refs/remotes/origin/mkimage does not point to a valid > object! > > You should remove this branch from the remote repo. > > done. Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] USB-ethernet LAN9500 U-Boot source
Hi Raghunath, On 14 May 2014 01:04, Raghunath Pol wrote: > Dear Simon Glass, > > In one of your post mentioned about SMSC LAN9500 u-boot drivers. > > http://www.mail-archive.com/u-boot@lists.denx.de/msg50068.html > we are in need of this drivers. Pls guide to source at earliest. It is at drivers/usb/eth/smsc95xx.c > > Thanks in advance. > > Regards, > > Raghunath Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] Add myself as maintainer for chromebook-x86
This is currently the only x86 board. Signed-off-by: Simon Glass --- boards.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards.cfg b/boards.cfg index 3a59686..a2980b7 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1211,7 +1211,7 @@ Active sparc leon3 - gaisler - Active sparc leon3 - gaisler - gr_ep2s60 - - Active sparc leon3 - gaisler - gr_xc3s_1500 - - Active sparc leon3 - gaisler - grsim - - -Active x86 x86corebootchromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x0111 - +Active x86 x86corebootchromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x0111 Simon Glass # The following were moved to "Orphan" in April, 2014 Orphan powerpc 74xx_7xx - - evb64260 ZUMA - Nye Liu Orphan powerpc mpc824x- - musenki MUSENKI - Jim Thompson -- 1.9.1.423.g4596e3a ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: Allow u-boot to run from offset base address
Dear Darwin,
In message <5374e64b.1060...@broadcom.com> you wrote:
>
> > This makes no sense to me. CONFIG_SYS_TEXT_BASE is a compile time
> > constant. So the result of all this is always known at compile time,
> > too. I feel you misunderstand that CONFIG_SYS_TEXT_BASE is just the
> > start address of the text segment. If you want to offset this by a
> > specific amount, you can just define this as needed.
>
> May I respectfully ask that you please bear with me a just a bit longer so
> I can try to explain things better?
>
> CONFIG_SYS_TEXT_BASE is also used by the relocation calculations at runtime
> to determine the relocation offset, which is also used for the symbol fixup
> logic. It is known at compile time, but is used at runtime by the stock
> u-boot code to determine the relocation offset. I am doing nothing more than
> existing code in this regard.
Let's have a look at your proposed code:
>> +int offset = CONFIG_SYS_TEXT_BASE % 4096;
>> +if (offset) {
>> +addr += offset;
>> +debug("Relocation Addr bumped to 0x%08lx\n", addr);
>> +}
> If I set it to 0x8820, then the code crashes because the symbol fixup
> depends on the relocation offset which is now wrong. The reason is that the
> relocation offset calculated in the code doesn't account for this offset.
> If we adjust the relocation address, then the relocation offset is now
> correct and the symbol fixups work perfectly.
First, please keep in mind that you cannot set CONFIG_SYS_TEXT_BASE in
arbitrary ways, at least not without adjusting your linker script
accordingly; also you may have limitations due to the way how the code
gets loaded / booted.
_If_ your code is correct, then the target address computed for the
relocation is completely irrelevant.
> Here's an example:
> CONFIG_SYS_TEXT_BASE = 0x8820
> relocated address = 0xfffa8000 (This 4K alignment assumption breaks the
> relocation)
> relocation offset = 0x77fa7fe0 (This is now wrong and the relocation breaks)
>
> My patch does the following:
> CONFIG_SYS_TEXT_BASE = 0x8820
> relocated address = 0xfffa8020
> relocation offset = 0x77fa8000 (symbol fixups now work)
You are mixing up copying code to another address range and relocating
symbols.
> So this patch just gives us a way to run u-boot at text sections with
> smaller alignments. In the past I never really understood why
> CONFIG_SYS_TEXT_BASE had to be on specific alignments like X000 for
> our architecture and the symbol fixup issue helps to explain this.
In many cases there is no strict reason. When storing the images in
NOR flash or other block oriented storage it is usually convenient to
align them to sector boundaaries. In systems where you have a MMU on,
it may be useful / convenient / necessary to have it aligned to page
boundaries. But al this is totally irrelevant here. Consider the
address arbitrarily chosen, it does not matter.
Also, moving the relocation address around by arbitrary amounts (that
are big enough not to cause alignment issues, say anything that is a
multiple of the cache line size) does not change anything.
If there are problems, these are somewhere in your implementation, and
not in the generic code.
> I know this is not the normal use case but it does fix the crash in the
> symbol relocation with arm64 and allows u-boot to be more flexible in
> it's text alignment requirements.
You ask for a "flexibility" that actually is already there; it's just
conveniend when debugging etc. to have "nice" addresses. If there is
something not working, it's in your code.
Setting CONFIG_SYS_TEXT_BASE to something like 0x8820 is extremly
fishy. If you want to add some header data to your image, you should
not shift the text segment, but rather include your header in the
start of the text segment. Or keep it completely separate, without
messing with CONFIG_SYS_TEXT_BASE.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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Re: [U-Boot] [PATCH] mmc: omap_hsmmc: add adma support
On Thu, May 15, 2014 at 07:45:28PM +0530, Balaji T K wrote: > On Monday 12 May 2014 08:20 PM, Tom Rini wrote: > >On Mon, May 12, 2014 at 07:12:44PM +0530, Balaji T K wrote: > >>On Monday 12 May 2014 06:58 PM, Tom Rini wrote: > >>>On Fri, May 02, 2014 at 07:25:20PM +0530, Balaji T K wrote: > >>> > MMC instance 1 and 2 is capable of ADMA in omap4, omap5. > Add support for ADMA and enable ADMA for read/write to > improve mmc throughput. > >>>[snip] > @@ -44,12 +45,30 @@ > #undef OMAP_HSMMC_USE_GPIO > #endif > > +#ifdef CONFIG_SPL_BUILD > +#undef CONFIG_OMAP_MMC_ADMA > +#endif > >>> > >>>Why? Especially since a number of the folks interested in this for > >>>performance want it for SPL OS mode. Thanks! > >> > >>Because in SoCs like OMAP4/5 mmc1/2 adma doesn't have access to sram. > >>So can't have descriptor or src / destination buffers (allocated on stack) > >>given by mmc core on sram. > > > >And we can't malloc them? > > > > For descriptor yes, but for src / dest, I doubt since > it would be difficult to force the upper (fs, mmc..) layers for controller > limitation > and some ARCH might require the buffers to be cache aligned > > Does malloc return buffers aligned to cache boundary ? Yes, with memalign which upper layers should also be using for such cases. FWIW, the ADMA patches I see in the omapzoom tree I'm fairly certain do SPL (since that's a focus of theirs) but incorrectly don't bother ensuring alignment with memalign. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] examples: select libgcc for non-default architecture
In case of multilib-enabled toolchains if default architecture differ from the one examples are being built for linker will fail to link example object files with libgcc of another (non-compatible) architecture. Interesting enough for years in main Makefile we used CFLAGS/c_flags for this but not for examples. So fixing it now. Signed-off-by: Alexey Brodkin Cc: Masahiro Yamada Cc: Tom Rini --- examples/standalone/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile index 9ab5446..7234f30 100644 --- a/examples/standalone/Makefile +++ b/examples/standalone/Makefile @@ -38,7 +38,8 @@ targets += $(patsubst $(obj)/%,%,$(LIB)) $(COBJS) $(LIBOBJS-y) LIBOBJS:= $(addprefix $(obj)/,$(LIBOBJS-y)) ELF:= $(addprefix $(obj)/,$(ELF)) -gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) +gcclibdir := $(shell dirname \ + `$(CC) $(PLATFORM_CPPFLAGS) -print-libgcc-file-name`) # For PowerPC there's no need to compile standalone applications as a # relocatable executable. The relocation data is not needed, and -- 1.9.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] pull request for u-boot-tegra/master into ARM/master
Hi Tom, On Tue, 13 May 2014 14:14:42 -0700, Tom Warren wrote: > Albert, > > Please pull u-boot-tegra/master into ARM/master. Thanks! > > ./MAKEALL -s tegra AOK, checkpatch.pl is OK, and ./MAKEALL -a arm only > shows failures that were already present in ARM/master. > > The following changes since commit d2a3e911390f9fc4d8c0ee4b3c7fc75f4fd3fd19: > > Merge branch 'u-boot/master' (2014-05-09 11:50:14 +0200) > > are available in the git repository at: > > git://git.denx.de/u-boot-tegra.git master > > for you to fetch changes up to 2364e151e432b4ccf32dc9e6147121253d4ff86d: > > ARM: tegra: use a CPU freq that all SKUs can support (2014-05-13 10:41:32 > -0700) > > > Stephen Warren (10): > ARM: tegra: set CONFIG_SYS_MMC_MAX_DEVICE > ARM: tegra: fix CPU VDD comment in Tegra30 CPU init code > ARM: tegra: allow pinmux mux option not to be set by init tables > ARM: tegra: add GPIO initialization table function > ARM: tegra: add function to enable input clamping on tristate > ARM: tegra: make use of GPIO init table on Jetson TK1 > ARM: tegra: clamp inputs on Jetson TK1 > ARM: tegra: update Venice2 pinmux > ARM: tegra: Venice2 pinmux spreadsheet updates > ARM: tegra: use a CPU freq that all SKUs can support > > arch/arm/cpu/arm720t/tegra-common/cpu.c| 10 +- > arch/arm/cpu/arm720t/tegra30/cpu.c | 23 +- > arch/arm/cpu/tegra-common/pinmux-common.c | 19 + > arch/arm/include/asm/arch-tegra/gpio.h | 20 + > arch/arm/include/asm/arch-tegra/pinmux.h | 5 + > arch/arm/include/asm/arch-tegra/tegra_mmc.h| 2 - > arch/arm/include/asm/arch-tegra114/pinmux.h| 1 + > arch/arm/include/asm/arch-tegra124/pinmux.h| 1 + > arch/arm/include/asm/arch-tegra20/pinmux.h | 1 + > arch/arm/include/asm/arch-tegra30/pinmux.h | 1 + > board/nvidia/jetson-tk1/jetson-tk1.c | 6 + > board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h | 256 +++--- > board/nvidia/venice2/pinmux-config-venice2.h | 567 > ++--- > board/nvidia/venice2/venice2.c | 19 +- > drivers/gpio/tegra_gpio.c | 20 + > drivers/mmc/tegra_mmc.c| 13 +- > include/configs/beaver.h | 3 + > include/configs/cardhu.h | 3 + > include/configs/tegra-common.h | 7 + > 19 files changed, 565 insertions(+), 412 deletions(-) Applied to u-boot-arm/master, thanks! Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: Allow u-boot to run from offset base address
On 14-05-15 08:21 AM, Wolfgang Denk wrote: Dear Darwin, In message <5374cd55.3010...@broadcom.com> you wrote: Do you really want to check a define at runtime? Placement is typically at the end of RAM and allocation goes down, not up as in this patch. Aren't you overlapping memory here? Yes, I wanted the runtime check since the adjustment to the relocation address is also done at runtime. This makes no sense to me. CONFIG_SYS_TEXT_BASE is a compile time constant. So the result of all this is always known at compile time, too. I feel you misunderstand that CONFIG_SYS_TEXT_BASE is just the start address of the text segment. If you want to offset this by a specific amount, you can just define this as needed. May I respectfully ask that you please bear with me a just a bit longer so I can try to explain things better? CONFIG_SYS_TEXT_BASE is also used by the relocation calculations at runtime to determine the relocation offset, which is also used for the symbol fixup logic. It is known at compile time, but is used at runtime by the stock u-boot code to determine the relocation offset. I am doing nothing more than existing code in this regard. If I set it to 0x8820, then the code crashes because the symbol fixup depends on the relocation offset which is now wrong. The reason is that the relocation offset calculated in the code doesn't account for this offset. If we adjust the relocation address, then the relocation offset is now correct and the symbol fixups work perfectly. Here's an example: CONFIG_SYS_TEXT_BASE = 0x8820 relocated address = 0xfffa8000 (This 4K alignment assumption breaks the relocation) relocation offset = 0x77fa7fe0 (This is now wrong and the relocation breaks) My patch does the following: CONFIG_SYS_TEXT_BASE = 0x8820 relocated address = 0xfffa8020 relocation offset = 0x77fa8000 (symbol fixups now work) So this patch just gives us a way to run u-boot at text sections with smaller alignments. In the past I never really understood why CONFIG_SYS_TEXT_BASE had to be on specific alignments like X000 for our architecture and the symbol fixup issue helps to explain this. I know this is not the normal use case but it does fix the crash in the symbol relocation with arm64 and allows u-boot to be more flexible in it's text alignment requirements. Thanks. Best regards, Darwin There is no overlap here. The reason is that the original masking operation to mask to a 4K boundary removed the small offset and backed up too far. So adding the lost offset is guaranteed to not overlap, and furthermore, correct the relocation offset so that arm64 images can run at smaller alignments than we normally use. This might even be a generic fix but can't be tested easily by me. Argh... This is black magic depending on specific properties of your process (which you don;t really explain). Sorry, but this is a full NAK for code that is build on sand like this. Best regards, Wolfgang Denk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4] net/phy: Add support for CS4315/CS4340 PHY
On 04/11/2014 03:14 AM, Shengzhou Liu wrote:
> Add support for Cortina CS4315/CS4340 10G PHY.
> - This driver loads CS43xx firmware to initialize Cortina PHY.
> - To define macro CONFIG_PHY_CORTINA will enable this driver.
> - Cortina PHY has non-standard offset of PHY ID registers, so
> define own get_phy_id().
>
> Signed-off-by: Shengzhou Liu
> ---
> v4: add support for loading cortina phy ucode from NAND/SPI/SD/REMOTE
> v3: move devad as '0' in cortina.c instead of in phy.c
> v2: no change.
>
> drivers/net/phy/Makefile | 1 +
> drivers/net/phy/cortina.c | 320
> ++
> drivers/net/phy/phy.c | 3 +
> include/cortina.h | 73 +++
> include/phy.h | 2 +
> 5 files changed, 399 insertions(+)
> create mode 100644 drivers/net/phy/cortina.c
> create mode 100644 include/cortina.h
>
> +void cs4340_upload_firmware(struct phy_device *phydev)
> +{
> + char line_temp[0x50] = {0};
> + char reg_addr[0x50] = {0};
> + char reg_data[0x50] = {0};
> + int i = 0;
> + int line_cnt = 0;
> + int column_cnt = 0;
> + struct cortina_reg_config fw_temp;
> + char *addr = NULL;
> +
> +#if defined(CONFIG_SYS_CORTINA_FW_IN_NOR) || \
> + defined(CONFIG_SYS_CORTINA_FW_IN_REMOTE)
> +
> + addr = (char *)CONFIG_CORTINA_FW_ADDR;
> +#elif defined(CONFIG_SYS_CORTINA_FW_IN_NAND)
> + size_t fw_length = CONFIG_CORTINA_FW_LENGTH;
> +
> + addr = malloc(CONFIG_CORTINA_FW_LENGTH);
> + rc = nand_read(&nand_info[0], (loff_t)CONFIG_CORTINA_FW_ADDR,
> +&fw_length, (u_char *)addr);
> + if (rc == -EUCLEAN) {
> + printf("NAND read of Cortina firmware at 0x%x failed %d\n",
> +CONFIG_CORTINA_FW_ADDR, rc);
> + }
Where is "rc" declared?
York
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Re: [U-Boot] [PATCH] arm: Allow u-boot to run from offset base address
Dear Darwin, In message <5374cd55.3010...@broadcom.com> you wrote: > > > Do you really want to check a define at runtime? Placement is typically > > at the end of RAM and allocation goes down, not up as in this patch. > > Aren't you overlapping memory here? > > Yes, I wanted the runtime check since the adjustment to the relocation > address is also done at runtime. This makes no sense to me. CONFIG_SYS_TEXT_BASE is a compile time constant. So the result of all this is always known at compile time, too. I feel you misunderstand that CONFIG_SYS_TEXT_BASE is just the start address of the text segment. If you want to offset this by a specific amount, you can just define this as needed. > There is no overlap here. The reason is that the original masking operation > to mask to a 4K boundary removed the small offset and backed up too far. So > adding the lost offset is guaranteed to not overlap, and furthermore, correct > the relocation offset so that arm64 images can run at smaller alignments than > we normally use. This might even be a generic fix but can't be tested easily > by me. Argh... This is black magic depending on specific properties of your process (which you don;t really explain). Sorry, but this is a full NAK for code that is build on sand like this. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de "I find this a nice feature but it is not according to the documen- tation. Or is it a BUG?" "Let's call it an accidental feature. :-)" - Larry Wall in <6...@jpl-devvax.jpl.nasa.gov> ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] please pull u-boot-samsung master
Hi Minkyu, On Tue, 13 May 2014 19:47:35 +0900, Minkyu Kang wrote: > Dear Albert, > > The following changes since commit 7904b70885f3c589c239f6ac978f299a6744557f: > > ARM: highbank: use default prompt (2014-05-02 11:43:25 +0200) > > are available in the git repository at: > > http://git.denx.de/u-boot-samsung > > for you to fetch changes up to 9b97b727dcfbdc02a0a78e4c1d81670742f28784: > > S5P: Exynos: Config: Enable GPIO CMD config (2014-05-13 15:20:38 +0900) > > > Akshay Saraswat (3): > Exynos5: config: Enable FIT > S5P: Exynos: Add GPIO pin numbering and rename definitions > S5P: Exynos: Config: Enable GPIO CMD config > > Inha Song (1): > samsung: misc: add env default option to lcd menu > > Jaehoon Chung (1): > ARM: exynos: remove the unused code > > Mateusz Zalega (1): > ARM: Samsung: s5p_goni: maintainer update > > Przemyslaw Marczak (4): > samsung: misc: allows using environmental macros as args in menu > commands > samsung: misc: add gpt restore option to lcd menu > samsung: misc: menu: increase delay in menu main loop > samsung: misc: remove download mode info screen > > Łukasz Majewski (2): > trats2: config: fix: Set default console to ttySAC2 > trats: config: fix: Set default console to ttySAC2 > > arch/arm/cpu/armv7/exynos/pinmux.c | 561 + > arch/arm/dts/exynos4210-origen.dts |4 +- > arch/arm/dts/exynos4210-trats.dts |6 +- > arch/arm/dts/exynos4210-universal_c210.dts |4 +- > arch/arm/dts/exynos4412-trats2.dts |4 +- > arch/arm/include/asm/arch-exynos/cpu.h | 17 +- > arch/arm/include/asm/arch-exynos/gpio.h| 1761 > +++- > arch/arm/include/asm/arch-s5pc1xx/gpio.h | 948 --- > board/samsung/arndale/arndale.c| 11 +- > board/samsung/common/misc.c| 130 +- > board/samsung/goni/goni.c | 32 +- > board/samsung/smdk5250/exynos5-dt.c| 20 +- > board/samsung/smdk5250/smdk5250.c | 19 +- > board/samsung/smdk5420/smdk5420.c | 15 +- > board/samsung/smdkc100/smdkc100.c |5 +- > board/samsung/smdkv310/smdkv310.c | 19 +- > board/samsung/trats/trats.c| 39 +- > board/samsung/trats2/trats2.c | 74 +- > board/samsung/universal_c210/universal.c | 51 +- > boards.cfg |2 +- > drivers/gpio/s5p_gpio.c| 204 +++- > include/configs/exynos5-dt.h |2 + > include/configs/s5p_goni.h |4 +- > include/configs/s5pc210_universal.h| 23 +- > include/configs/smdk5250.h |4 + > include/configs/smdk5420.h |4 + > include/configs/smdkv310.h |1 + > include/configs/snow.h |4 + > include/configs/trats.h| 17 +- > include/configs/trats2.h | 17 +- > include/samsung/misc.h |2 + > 31 files changed, 3002 insertions(+), 1002 deletions(-) > Applied to u-boot-arm/master, thanks! Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: Allow u-boot to run from offset base address
Dear Darwin, In message <5374cc3b.7000...@broadcom.com> you wrote: > > I mean that the loader loads u-boot to it's correct address, which is > offset by a small amount because of a previous header requiring alignment. > Here's an example. u-boot is compiled to run at 0x8820 because we want > to put a small header in front of the image, which starts at 0x8800 and > needs to be aligned for its own reasons. Now for arm64, I believe that u-boot > cannot normally be positioned at any alignment less than 0x800 hex. So I thing you have some misunderstanding of the meaning of the start address of the image versus the entry point address. These are not related. You can add any headers or padding you like to the image, and put the entry point at an arbitrary address. The restrictions we usually face are due to the bootmodes of the SoC, which may start from a fixed reset address (whwere we then must make sure that this is also the entry point address in the image), or where the ROM boot loader may have specific requirements. If you add some custom image header, you can also start at some random entry point addres.. Just adapt your linker script as needed. > And in these cases the relocation works fine. But if we want to position > u-boot > at a smaller offset than 0x800, the symbol relocation breaks for arm64. It > turns out that there is a trivial fix so that u-boot can run at smaller offset > addresses, which I have provided here, is tested, and solves our problem > nicely, > but only for arm64 right now. No, your patch is highly dubious actually. Note that the entry point address which we are talking about is where code execution starts _before_ relocation. Relocation is a totally different topic. The address where we relocate to gets computed at runtime, and does not depend on CONFIG_SYS_TEXT_BASE at all. Also, as had been pointed out before, memory allocation happens top down, so any adjustments you want to make must be to lower addresses, never upward. > Yes, I agree, but I am not sure if this is a arm64-only problem or not. Unfortunaltely you don't explain what you really want to do. We have the same task (loading the U-Boot image and starting it) in many, nmany configurations either when a ROM boot loader performs the loading, or where the SPL does it. This is a well understood procedure, and it has no such problem as you claim to have. I suspect you have bugs elsewhere in your port, may it be the linker script or your implementation of a special image header or whatever. > can provide on how to proceed would be appreciated. And if the fix is > not suitable for upstreaming, then we should know it. Please understand that this is not a question of suitable for upstreaming or not, it is a matter of correct or not. I am pretty much convinced that your modifcation cannot be right. > Also there might be a generic fix possible that works for all architectures > (by removing the ifdef CONFIG_ARM64), but I don't have the resources to test > them. Maybe it would be best to decide if we want to support this feature or > not first. Thanks! Please define "this feature" in an exact way, and why you think it would cause any problems. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Disc space - the final frontier! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/8] imx25: Add new hardware registers
From: Thomas Diener
Signed-off-by: Thomas Diener
---
arch/arm/include/asm/arch-mx25/iomux-mx25.h | 25 +++--
arch/arm/include/asm/imx-common/iomux-v3.h | 13 -
arch/arm/lib/asm-offsets.c |9 +
3 files changed, 40 insertions(+), 7 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx25/iomux-mx25.h
b/arch/arm/include/asm/arch-mx25/iomux-mx25.h
index 220cf4e..e403eb9 100644
--- a/arch/arm/include/asm/arch-mx25/iomux-mx25.h
+++ b/arch/arm/include/asm/arch-mx25/iomux-mx25.h
@@ -287,15 +287,19 @@ enum {
MX25_PAD_CSI_D6__CSI_D6 = IOMUX_PAD(0x328, 0x130, 0x10,
0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_D6__GPIO_1_31 = IOMUX_PAD(0x328, 0x130, 0x15,
0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_D6__CSPI3_SS0 = IOMUX_PAD(0x328, 0x130, 0x17,
0, 1, NO_PAD_CTRL),
MX25_PAD_CSI_D7__CSI_D7 = IOMUX_PAD(0x32c, 0x134, 0x10,
0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_D7__GPIO_1_6 = IOMUX_PAD(0x32c, 0x134, 0x15,
0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_D7__CSPI3_SS1 = IOMUX_PAD(0x32c, 0x134, 0x17,
0, 1, NO_PAD_CTRL),
MX25_PAD_CSI_D8__CSI_D8 = IOMUX_PAD(0x330, 0x138, 0x10,
0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_D8__GPIO_1_7 = IOMUX_PAD(0x330, 0x138, 0x15,
0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_D8__CSPI3_SS2 = IOMUX_PAD(0x330, 0x138, 0x17,
0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_D9__CSI_D9 = IOMUX_PAD(0x334, 0x13c, 0x10,
0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_D9__GPIO_4_21 = IOMUX_PAD(0x334, 0x13c, 0x15,
0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_D9__CSPI3_SS3 = IOMUX_PAD(0x334, 0x13c, 0x17,
0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_MCLK__CSI_MCLK = IOMUX_PAD(0x338, 0x140, 0x10,
0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_MCLK__GPIO_1_8 = IOMUX_PAD(0x338, 0x140, 0x15,
0, 0, NO_PAD_CTRL),
@@ -315,16 +319,18 @@ enum {
MX25_PAD_I2C1_DAT__I2C1_DAT = IOMUX_PAD(0x34c, 0x154, 0x10,
0, 0, NO_PAD_CTRL),
MX25_PAD_I2C1_DAT__GPIO_1_13= IOMUX_PAD(0x34c, 0x154, 0x15,
0, 0, NO_PAD_CTRL),
- MX25_PAD_CSPI1_MOSI__CSPI1_MOSI = IOMUX_PAD(0x350, 0x158, 0x10,
0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSPI1_MOSI__CSPI1_MOSI = IOMUX_PAD(0x350, 0x158, 0x10,
0x568, 0, NO_PAD_CTRL),
MX25_PAD_CSPI1_MOSI__GPIO_1_14 = IOMUX_PAD(0x350, 0x158, 0x15,
0, 0, NO_PAD_CTRL),
MX25_PAD_CSPI1_MISO__CSPI1_MISO = IOMUX_PAD(0x354, 0x15c, 0x10,
0, 0, NO_PAD_CTRL),
MX25_PAD_CSPI1_MISO__GPIO_1_15 = IOMUX_PAD(0x354, 0x15c, 0x15,
0, 0, NO_PAD_CTRL),
MX25_PAD_CSPI1_SS0__CSPI1_SS0 = IOMUX_PAD(0x358, 0x160, 0x10,
0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSPI1_SS0__LD16= IOMUX_PAD(0x358, 0x160, 0x11,
0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSPI1_SS0__PWM2_PWMO = IOMUX_PAD(0x358, 0x160, 0x14,
0, 0, 0),
MX25_PAD_CSPI1_SS0__GPIO_1_16 = IOMUX_PAD(0x358, 0x160, 0x15,
0, 0, NO_PAD_CTRL),
- MX25_PAD_CSPI1_SS1__CSPI1_SS1 = IOMUX_PAD(0x35c, 0x164, 0x10,
0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSPI1_SS1__CSPI1_SS1 = IOMUX_PAD(0x35c, 0x164, 0x10,
0x564, 0, NO_PAD_CTRL),
MX25_PAD_CSPI1_SS1__I2C3_DAT= IOMUX_PAD(0x35c, 0x164, 0x11,
0x528, 1, NO_PAD_CTRL),
MX25_PAD_CSPI1_SS1__GPIO_1_17 = IOMUX_PAD(0x35c, 0x164, 0x15,
0, 0, NO_PAD_CTRL),
@@ -341,6 +347,7 @@ enum {
MX25_PAD_UART1_TXD__GPIO_4_23 = IOMUX_PAD(0x36c, 0x174, 0x15,
0, 0, NO_PAD_CTRL),
MX25_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x370, 0x178, 0x10,
0, 0, PAD_CTL_PUS_100K_UP),
+ MX25_PAD_UART1_RTS__GPT3_CAPIN1 = IOMUX_PAD(0x370, 0x178, 0x12,
0, 0, NO_PAD_CTRL),
MX25_PAD_UART1_RTS__CSI_D0 = IOMUX_PAD(0x370, 0x178, 0x11,
0x488, 1, NO_PAD_CTRL),
MX25_PAD_UART1_RTS__GPIO_4_24 = IOMUX_PAD(0x370, 0x178, 0x15,
0, 0, NO_PAD_CTRL),
@@ -356,6 +363,7 @@ enum {
MX25_PAD_UART2_RTS__UART2_RTS = IOMUX_PAD(0x380, 0x188, 0x10,
0, 0, NO_PAD_CTRL),
MX25_PAD_UART2_RTS__FEC_COL = IOMUX_PAD(0x380, 0x188, 0x12,
0x504, 2, NO_PAD_CTRL),
+ MX25_PAD_UART2_RTS__GPT1_CAPIN1 = IOMUX_PAD(0x380, 0x188, 0x13,
0x504, 2, NO_PAD_CTRL),
MX25_PAD_UART2_RTS__GPIO_4_28 = IOMUX_PAD(0x380, 0x188, 0x15,
0, 0, NO_PAD_CTRL),
MX25_PAD_UART2_CTS__FEC_RX_ER = IOMUX_PAD(0x384, 0x18c, 0x12,
0x518, 2, NO_PAD_CTRL),
@@ -385,17 +393,21 @@ enum {
MX25_PAD_SD1_DATA3__FEC_CRS = IOMUX_PAD(0x39c, 0x1a4, 0x10,
0x508, 2, NO_PAD_CTRL),
MX25_PAD_SD1_DATA3__GPIO_2_28 = IOMUX_PAD(0x39c, 0x1a4, 0x15,
0, 0, NO_PAD_CTRL),
- MX25_PAD_KPP_ROW0__KPP_ROW0 = IOMUX_PAD(0x3a0, 0x1a8, 0x10,
0, 0, MX25_KPP_ROW_PAD_CTRL)
[U-Boot] [PATCH 7/8] imx25: Add new registers defines
From: Thomas Diener
Signed-off-by: Thomas Diener
---
arch/arm/include/asm/arch-mx25/imx-regs.h | 271 -
1 file changed, 264 insertions(+), 7 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h
b/arch/arm/include/asm/arch-mx25/imx-regs.h
index a17f828..dc9a298 100644
--- a/arch/arm/include/asm/arch-mx25/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx25/imx-regs.h
@@ -161,6 +161,126 @@ struct aips_regs {
u32 mpr_0_7;
u32 mpr_8_15;
};
+/* LCD controller registers */
+struct lcdc_regs {
+ u32 lssar; /* Screen Start Address */
+ u32 lsr;/* Size */
+ u32 lvpwr; /* Virtual Page Width */
+ u32 lcpr; /* Cursor Position */
+ u32 lcwhb; /* Cursor Width Height and Blink */
+ u32 lccmr; /* Color Cursor Mapping */
+ u32 lpcr; /* Panel Configuration */
+ u32 lhcr; /* Horizontal Configuration */
+ u32 lvcr; /* Vertical Configuration */
+ u32 lpor; /* Panning Offset */
+ u32 lscr; /* Sharp Configuration */
+ u32 lpccr; /* PWM Contrast Control */
+ u32 ldcr; /* DMA Control */
+ u32 lrmcr; /* Refresh Mode Control */
+ u32 licr; /* Interrupt Configuration */
+ u32 lier; /* Interrupt Enable */
+ u32 lisr; /* Interrupt Status */
+ u32 res0[3];
+ u32 lgwsar; /* Graphic Window Start Address */
+ u32 lgwsr; /* Graphic Window Size */
+ u32 lgwvpwr;/* Graphic Window Virtual Page Width Regist */
+ u32 lgwpor; /* Graphic Window Panning Offset */
+ u32 lgwpr; /* Graphic Window Position */
+ u32 lgwcr; /* Graphic Window Control */
+ u32 lgwdcr; /* Graphic Window DMA Control */
+ u32 res1[5];
+ u32 lauscr; /* AUS Mode Control */
+ u32 lausccr;/* AUS mode Cursor Control */
+ u32 res2[31 + 64*7];
+ u32 bglut; /* Background Lookup Table */
+ u32 gwlut; /* Graphic Window Lookup Table */
+};
+
+/* Wireless External Interface Module Registers */
+struct weim_regs {
+ u32 cscr0u; /* Chip Select 0 Upper Register */
+ u32 cscr0l; /* Chip Select 0 Lower Register */
+ u32 cscr0a; /* Chip Select 0 Addition Register */
+ u32 pad0;
+ u32 cscr1u; /* Chip Select 1 Upper Register */
+ u32 cscr1l; /* Chip Select 1 Lower Register */
+ u32 cscr1a; /* Chip Select 1 Addition Register */
+ u32 pad1;
+ u32 cscr2u; /* Chip Select 2 Upper Register */
+ u32 cscr2l; /* Chip Select 2 Lower Register */
+ u32 cscr2a; /* Chip Select 2 Addition Register */
+ u32 pad2;
+ u32 cscr3u; /* Chip Select 3 Upper Register */
+ u32 cscr3l; /* Chip Select 3 Lower Register */
+ u32 cscr3a; /* Chip Select 3 Addition Register */
+ u32 pad3;
+ u32 cscr4u; /* Chip Select 4 Upper Register */
+ u32 cscr4l; /* Chip Select 4 Lower Register */
+ u32 cscr4a; /* Chip Select 4 Addition Register */
+ u32 pad4;
+ u32 cscr5u; /* Chip Select 5 Upper Register */
+ u32 cscr5l; /* Chip Select 5 Lower Register */
+ u32 cscr5a; /* Chip Select 5 Addition Register */
+ u32 pad5;
+ u32 wcr;/* WEIM Configuration Register */
+};
+
+/* Multi-Master Memory Interface */
+struct m3if_regs {
+ u32 ctl;/* Control Register */
+ u32 wcfg0; /* Watermark Configuration Register 0 */
+ u32 wcfg1; /* Watermark Configuration Register1 */
+ u32 wcfg2; /* Watermark Configuration Register2 */
+ u32 wcfg3; /* Watermark Configuration Register 3 */
+ u32 wcfg4; /* Watermark Configuration Register 4 */
+ u32 wcfg5; /* Watermark Configuration Register 5 */
+ u32 wcfg6; /* Watermark Configuration Register 6 */
+ u32 wcfg7; /* Watermark Configuration Register 7 */
+ u32 wcsr; /* Watermark Control and Status Register */
+ u32 scfg0; /* Snooping Configuration Register 0 */
+ u32 scfg1; /* Snooping Configuration Register 1 */
+ u32 scfg2; /* Snooping Configuration Register 2 */
+ u32 ssr0; /* Snooping Status Register 0 */
+ u32 ssr1; /* Snooping Status Register 1 */
+ u32 res0;
+ u32 mlwe0; /* Master Lock WEIM CS0 Register */
+ u32 mlwe1; /* Master Lock WEIM CS1 Register */
+ u32 mlwe2; /* Master Lock WEIM CS2 Register */
+ u32 mlwe3; /* Master Lock WEIM CS3 Register */
+ u32 mlwe4; /* Master Lock WEIM CS4 Register */
+ u32 mlwe5; /* Master Lock WEIM CS5 Register */
+};
+
+/* Pulse width modulation */
+struct pwm_regs {
+ u32 cr; /* Control Register */
+ u32 sr; /* Status Register */
+ u32 ir; /* Interrupt Register */
+ u32 sar;/* Sample Register
[U-Boot] [PATCH 8/8] video: imx25lcdc: add board_video_init() call
From: Thomas Diener
Signed-off-by: Thomas Diener
---
drivers/video/imx25lcdc.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/video/imx25lcdc.c b/drivers/video/imx25lcdc.c
index 3b45472..94ef033 100644
--- a/drivers/video/imx25lcdc.c
+++ b/drivers/video/imx25lcdc.c
@@ -23,6 +23,19 @@
#define FB_SYNC_CLK_INV(1<<16) /* pixel clock inverted */
/*
+ * We do not enforce board code to provide empty/unused
+ * functions for this driver and define weak default
+ * functions here.
+ */
+unsigned int __board_video_init (void)
+{
+ return 0;
+}
+
+unsigned int board_video_init (void)
+ __attribute__((weak, alias("__board_video_init")));
+
+/*
* Graphic Device
*/
static GraphicDevice imx25fb;
@@ -117,6 +130,12 @@ void *video_hw_init(void)
writel(readl(&ccm->cgr1) | (1<<29), &ccm->cgr1);
}
+ /*
+* Initialization of the access to the graphic chipset Retreive base
+* address of the chipset (see board/RPXClassic/eccx.c)
+*/
+ board_video_init();
+
return pGD;
}
--
1.7.9.5
___
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[U-Boot] [PATCH 4/8] input: Add support for FMA1125 touch controller
From: Thomas Diener
Signed-off-by: Thomas Diener
---
drivers/input/Makefile |3 +-
drivers/input/fma1125.c | 47
include/fma1125.h | 140 +++
3 files changed, 189 insertions(+), 1 deletion(-)
create mode 100644 drivers/input/fma1125.c
create mode 100644 include/fma1125.h
diff --git a/drivers/input/Makefile b/drivers/input/Makefile
index 65c40ba..203a311 100644
--- a/drivers/input/Makefile
+++ b/drivers/input/Makefile
@@ -14,4 +14,5 @@ obj-$(CONFIG_PS2MULT) += ps2mult.o ps2ser.o
endif
obj-y += input.o
obj-$(CONFIG_OF_CONTROL) += key_matrix.o
-obj-$(CONFIG_POLYTOUCH) += polytouch.o
\ No newline at end of file
+obj-$(CONFIG_POLYTOUCH) += polytouch.o
+obj-$(CONFIG_FMA1125) += fma1125.o
\ No newline at end of file
diff --git a/drivers/input/fma1125.c b/drivers/input/fma1125.c
new file mode 100644
index 000..8241371
--- /dev/null
+++ b/drivers/input/fma1125.c
@@ -0,0 +1,47 @@
+/*
+ * (c) 2012 Graf-Syteco, Matthias Weisser
+ *
+ *
+ * fma1125.c - FUJITSU FMA1125 Touch Sensor Controller
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+
+#include
+#include
+#include
+
+int fma1125_init(int id, const struct fma1125_register_tbl *lu, uint16_t num)
+{
+ const struct fma1125_register_tbl *p;
+ int res = 0;
+
+ if (NULL == lu)
+ return res;
+
+ if (!i2c_probe(FMA1125_SA)) {
+ int i;
+
+ p = lu;
+
+ for (i = 0; i < num; i++) {
+ i2c_reg_write(id, p->addr, p->value);
+ p++;
+ }
+
+ res = 1;
+ }
+ return res;
+}
+
+int fma1125_get_touch_bits(void)
+{
+ uint8_t res = i2c_reg_read(FMA1125_SA, FMA1125_PA_TOUCH_BYTE);
+ return res;
+}
+
+void fma1125_set_gpio_out(uint8_t value)
+{
+ i2c_reg_write(FMA1125_SA, FMA1125_GPIO_DATA_OUT, value);
+}
diff --git a/include/fma1125.h b/include/fma1125.h
new file mode 100644
index 000..322cff5
--- /dev/null
+++ b/include/fma1125.h
@@ -0,0 +1,140 @@
+/*
+ * (c) 2012 Graf-Syteco, Matthias Weisser
+ *
+ *
+ * fma1125.h - FUJITSU FMA1125 Touch Sensor Controller
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __FMA1125_H
+#define __FMA1125_H
+
+
+#define FMA1125_SA 0x68
+
+#define FMA1125_PA0_ALPHA 0x00
+#define FMA1125_PA1_ALPHA 0x01
+#define FMA1125_PA2_ALPHA 0x02
+#define FMA1125_PA3_ALPHA 0x03
+#define FMA1125_PA4_ALPHA 0x04
+#define FMA1125_PA5_ALPHA 0x05
+#define FMA1125_PA6_ALPHA 0x06
+#define FMA1125_PA7_ALPHA 0x07
+#define FMA1125_REFERENCE_DELAY0x08
+#define FMA1125_BETA 0x09
+#define FMA1125_AIC_WAIT_TIME 0x0A
+#define FMA1125_PA0_STRENGTH_THRESHOLD 0x0B
+#define FMA1125_PA1_STRENGTH_THRESHOLD 0x0C
+#define FMA1125_PA2_STRENGTH_THRESHOLD 0x0D
+#define FMA1125_PA3_STRENGTH_THRESHOLD 0x0E
+#define FMA1125_PA4_STRENGTH_THRESHOLD 0x0F
+#define FMA1125_PA5_STRENGTH_THRESHOLD 0x10
+#define FMA1125_PA6_STRENGTH_THRESHOLD 0x11
+#define FMA1125_PA7_STRENGTH_THRESHOLD 0x12
+#define FMA1125_FEATURE_SELECT 0x13
+#define FMA1125_INTEGRATION_TIME 0x14
+#define FMA1125_IDLE_STATE_ENTER_TIME 0x15
+#define FMA1125_CONTROL_1 0x16
+#define FMA1125_CONTROL_2 0x17
+#define FMA1125_PA_DATA_OUT0x18
+#define FMA1125_GPIO_DATA_OUT 0x19
+#define FMA1125_PA_DIRECTION 0x1A
+#define FMA1125_GPIO_DIRECTION 0x1B
+#define FMA1125_PA_CONFIGURATION 0x1C
+#define FMA1125_GPIO_CONFIGURATION 0x1D
+#define FMA1125_CALIBRATION_INTERVAL 0x1E
+#define FMA1125_GINT_INTERRUPT_MASK0x1F
+#define FMA1125_GINT_INTERRUPT_CLEAR 0x20
+#define FMA1125_PA_EINT_ENABLE 0x21
+#define FMA1125_GPIO_EINT_ENABLE 0x22
+#define FMA1125_FILTER_PERIOD 0x23
+#define FMA1125_FILTER_THRESHOLD 0x24
+#define FMA1125_CONTROL_3 0x25
+#define FMA1125_GINT_INTERRUPT_EDGE_EN 0x26
+#define FMA1125_GPIO_INPUT_BOUNCE_PERIOD 0x27
+#define FMA1125_REGISTER_CHECK 0x28
+#define FMA1125_PA03_RESISTOR_SELECT 0x29
+#define FMA1125_PA47_RESISTOR_SELECT 0x2A
+#define FMA1125_REFERENCE_RESISTOR_SELECT 0x2B
+#define FMA1125_BETA_DISABLE 0x2C
+#define FMA1125_GPIO01_DIM_UNIT_PERIOD 0x2D
+#define FMA1125_GPIO23_DIM_UNIT_PERIOD 0x2E
+#define FMA1125_PA01_DIM_UNIT_PERIOD 0x2F
+#define FMA1125_PA23_DIM_UNIT_PERIOD 0x30
+#define FMA1125_GPIO0_DIMMING_CONTROL
[U-Boot] [PATCH 6/8] zmx25: Extended support for cpu and base boards
From: Thomas Diener
Added support for additional hardware variants.
Signed-off-by: Thomas Diener
---
We don't use a linux kernel and have to do the complete
hardware setup in the boot loader.
board/syteco/zmx25/lowlevel_init.S | 21 +
board/syteco/zmx25/zmx25.c | 1052 +---
include/configs/zmx25.h| 66 ++-
3 files changed, 1064 insertions(+), 75 deletions(-)
diff --git a/board/syteco/zmx25/lowlevel_init.S
b/board/syteco/zmx25/lowlevel_init.S
index 5eccf09..aa38459 100644
--- a/board/syteco/zmx25/lowlevel_init.S
+++ b/board/syteco/zmx25/lowlevel_init.S
@@ -92,6 +92,27 @@
lowlevel_init:
init_aips
init_max
+
+ /* Setup of NOR flash CS */
+ write32 IMX_WEIM_CTRL_BASE + WEIM_CSCR0U, \
+ (WEIM_CSCR_U_WSC(14) | WEIM_CSCR_U_EDC(2))
+ write32 IMX_WEIM_CTRL_BASE + WEIM_CSCR0L, \
+ (WEIM_CSCR_L_OAE(1) | WEIM_CSCR_L_OEN(1) | \
+ WEIM_CSCR_L_DSZ(5)| WEIM_CSCR_L_CS_EN)
+ write32 IMX_WEIM_CTRL_BASE + WEIM_CSCR0A, \
+ (WEIM_CSCR_A_RWA(1) | WEIM_CSCR_A_RWN(1))
+
+ /* Set some memory access priorities */
+ write32 IMX_M3IF_CTRL_BASE + M3IF_CTL, M3IF_CTL_MRRP(1)
+ write32 IMX_MAX_BASE + MAX_MGPCR0, MAX_MGPCR_AULB(0x4)
+ write32 IMX_MAX_BASE + MAX_MGPCR1, MAX_MGPCR_AULB(0x4)
+ write32 IMX_MAX_BASE + MAX_MGPCR2, MAX_MGPCR_AULB(0x4)
+ write32 IMX_MAX_BASE + MAX_MGPCR3, MAX_MGPCR_AULB(0x4)
+ write32 IMX_MAX_BASE + MAX_MGPCR4, MAX_MGPCR_AULB(0x4)
+
+ /* Need this early for voltage sequence on G305 */
+ write32 IMX_IOPADMUX_BASE + 0x38c, 5 //Offset 0x38C IOPADMUX_SD1_CLK
+
init_clocks
init_lpddr
mov pc, lr
diff --git a/board/syteco/zmx25/zmx25.c b/board/syteco/zmx25/zmx25.c
index bdbf02a..f6c018d 100644
--- a/board/syteco/zmx25/zmx25.c
+++ b/board/syteco/zmx25/zmx25.c
@@ -1,4 +1,7 @@
/*
+ * (c) 2014 Graf-Syteco, Thomas Diener
+ *
+ *
* (c) 2011 Graf-Syteco, Matthias Weisser
*
*
@@ -14,63 +17,705 @@
*
* SPDX-License-Identifier:GPL-2.0+
*/
+
#include
-#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
#include
+#include
#include
#include
+#include
+
+
+#define ZMX25_CPU_BOARD_TYPE_UNKNOWN 0
+#define ZMX25_CPU_BOARD_TYPE_G282A01
+#define ZMX25_CPU_BOARD_TYPE_G282A12
+#define ZMX25_CPU_BOARD_TYPE_G292 3
+#define ZMX25_CPU_BOARD_TYPE_G305 4
+
+#define ZMX25_IO_BOARD_TYPE_NONE 0
+#define ZMX25_IO_BOARD_TYPE_UNKNOWN1
+#define ZMX25_IO_BOARD_TYPE_G283 2
+#define ZMX25_IO_BOARD_TYPE_G297 3
+
+#define ZMX25_FIXED_EEPROM_ADDR_APP0x80
+#define ZMX25_FIXED_EEPROM_ADDR_BI10xA0
+#define ZMX25_FIXED_EEPROM_ADDR_BI20xC0
+
+#define ZMX25_BOOT_MODE_SLOW 0x5555
+#define ZMX25_BOOT_MODE_FAST 0xAAAA
DECLARE_GLOBAL_DATA_PTR;
-int board_init()
+static inline u32 hw_setup_common(void);
+
+static inline void hw_setup_cpu_g282g292(void);
+static inline void hw_setup_cpu_g282(void);
+static inline void hw_setup_cpu_g282a1(void);
+static inline void hw_setup_cpu_g292(void);
+static inline void hw_setup_cpu_g305(void);
+
+static inline void hw_setup_io_g283(void);
+static inline void hw_setup_io_g297(void);
+
+static const iomux_v3_cfg_t can_pads[] = {
+ CLEAR_MODE_SION(NEW_PAD_CTRL(MX25_PAD_GPIO_A__CAN1_TX, 0)),
+ CLEAR_MODE_SION(NEW_PAD_CTRL(MX25_PAD_GPIO_B__CAN1_RX,
+ PAD_CTL_PUS_100K_DOWN)),
+ CLEAR_MODE_SION(NEW_PAD_CTRL(MX25_PAD_GPIO_C__CAN2_TX, 0)),
+ CLEAR_MODE_SION(NEW_PAD_CTRL(MX25_PAD_GPIO_D__CAN2_RX, 0)),
+};
+
+static const struct fma1125_register_tbl fma1125_config[] = {
+ { FMA1125_COLD_RESET, 0x00 }, /* cold reset */
+ { FMA1125_REGISTER_CHECK, 0xFF }, /* register check */
+ { FMA1125_GINT_INTERRUPT_MASK, 0xFE }, /* Mask all interrupts */
+ { FMA1125_GINT_INTERRUPT_CLEAR, 0xFF }, /* Mask all interrupts */
+ { FMA1125_GPIO_DIRECTION, 0x00 }, /* All GPIOs are output */
+ { FMA1125_GPIO_CONFIGURATION, 0x0f }, /* All GPIOs are GPIOs */
+ { FMA1125_GPIO_DATA_OUT,0x03 }, /* Switch the LEDs off */
+
+ /* P0A - PA7 Alpha; sensitivity of each sensor input*/
+ { FMA1125_PA0_ALPHA,0x0A },
+ { FMA1125_PA1_ALPHA,0x0A },
+ { FMA1125_PA2_ALPHA,0x0A },
+ { FMA1125_PA3_ALPHA,0x0A },
+ { FMA1125_PA4_ALPHA,0x0A },
+ { FMA1125_PA5_ALPHA,0x0A },
+ { FMA1125_PA6_ALPHA,0x0A },
+ { FMA1125_PA7_ALPHA,0x0A },
+
+ { FMA1125_REFERENCE_DELAY, 0x50 }, /* Reference delay */
+ { FMA1125_BETA, 4 },/* Beta */
+ { FMA1125_AIC_WAIT_TIME,0x27 }, /* AIC wait time */
+
+ /* PA0 - PA7 Strength threshold to 2/10 of integration time */
+ { FMA1125_PA0_STRENGTH_THRESHOLD, 0x28 },
+ { FMA1125_PA1_STRENGTH_THRESHOLD, 0x28 },
+
[U-Boot] [PATCH 3/8] mxc_i2c: Use the 3th i2c channel for imx25
From: Thomas Diener Signed-off-by: Thomas Diener --- drivers/i2c/mxc_i2c.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 595019b..96cc739 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -540,7 +540,7 @@ U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe, mxc_i2c_set_bus_speed, CONFIG_SYS_MXC_I2C2_SPEED, CONFIG_SYS_MXC_I2C2_SLAVE, 1) -#if defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\ +#if defined(CONFIG_MX25) || defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\ defined(CONFIG_MX51) || defined(CONFIG_MX53) ||\ defined(CONFIG_MX6) U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe, -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/8] input: Add support for MPR121 touch controller
From: Thomas Diener
Signed-off-by: Thomas Diener
---
drivers/input/Makefile |3 +-
drivers/input/mpr121.c | 67
include/mpr121.h | 158
3 files changed, 227 insertions(+), 1 deletion(-)
create mode 100644 drivers/input/mpr121.c
create mode 100644 include/mpr121.h
diff --git a/drivers/input/Makefile b/drivers/input/Makefile
index 203a311..a9fe157 100644
--- a/drivers/input/Makefile
+++ b/drivers/input/Makefile
@@ -15,4 +15,5 @@ endif
obj-y += input.o
obj-$(CONFIG_OF_CONTROL) += key_matrix.o
obj-$(CONFIG_POLYTOUCH) += polytouch.o
-obj-$(CONFIG_FMA1125) += fma1125.o
\ No newline at end of file
+obj-$(CONFIG_FMA1125) += fma1125.o
+obj-$(CONFIG_MPR121) += mpr121.o
diff --git a/drivers/input/mpr121.c b/drivers/input/mpr121.c
new file mode 100644
index 000..66fcb2e
--- /dev/null
+++ b/drivers/input/mpr121.c
@@ -0,0 +1,67 @@
+/*
+ * (c) 2012 Graf-Syteco, Matthias Weisser
+ *
+ *
+ * mpr121.c - Freescale Semiconductor capacitive touch sensor controller
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+
+#include
+#include
+#include
+
+int mpr121_init(const struct mpr121_register_tbl *lu, uint16_t num)
+{
+ int addr = 0;
+
+ if (NULL == lu)
+ return 0;
+
+ if (!i2c_probe(MPR121_SA_0))
+ addr = MPR121_SA_0;
+ else if (!i2c_probe(MPR121_SA_1))
+ addr = MPR121_SA_1;
+
+ if (addr == MPR121_SA_0 || addr == MPR121_SA_1) {
+ const struct mpr121_register_tbl *p;
+ int i;
+
+ p = lu;
+
+ for (i = 0; i < num; i++) {
+ i2c_reg_write(addr, p->addr, p->value);
+ p++;
+ }
+
+ return addr;
+ }
+ return 0;
+}
+
+int mpr121_get_touch_bits(u8 sa)
+{
+ int res;
+
+ res = i2c_reg_read(sa, MPR121_ELE0_7_TOUCH);
+ res += i2c_reg_read(sa, MPR121_ELE8_11_TOUCH) * 256;
+
+ return res;
+}
+
+void mpr121_set_leds_on(void)
+{
+ i2c_reg_write(0x62, 0x00 | 0x80, 0x00);
+
+ i2c_reg_write(0x62, 0x1C | 0x80, 0xFF);
+
+ i2c_reg_write(0x62, 0x14 | 0x80, 0xaa);
+ i2c_reg_write(0x62, 0x15 | 0x80, 0xaa);
+ i2c_reg_write(0x62, 0x16 | 0x80, 0xaa);
+ i2c_reg_write(0x62, 0x17 | 0x80, 0xaa);
+
+ i2c_reg_write(0x62, 0x02 | 0x80, 0xff);
+ i2c_reg_write(0x62, 0x06 | 0x80, 0xff);
+}
+
diff --git a/include/mpr121.h b/include/mpr121.h
new file mode 100644
index 000..1dadf00
--- /dev/null
+++ b/include/mpr121.h
@@ -0,0 +1,158 @@
+/*
+ * (c) 2012 Graf-Syteco, Matthias Weisser
+ *
+ *
+ * mpr121.h - Freescale Semiconductor capacitive touch sensor controller
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+
+#ifndef __MPR121_H
+#define __MPR121_H
+
+#define MPR121_SA_00x5a
+#define MPR121_SA_10x5b
+#define MPR121_SA_20x5c
+#define MPR121_SA_30x5d
+
+#define MPR121_ELE0_7_TOUCH0x00 /* Touch Status */
+#define MPR121_ELE8_11_TOUCH 0x01 /* ELEPROX Touch Status */
+#define MPR121_ELE0_7_OOR 0x02 /* OOR Status */
+#define MPR121_ELE8_11_OOR 0x03 /* ELEPROX OOR Status */
+#define MPR121_ELE0_L 0x04 /* Electrode Filtered Data LSB */
+#define MPR121_ELE0_H 0x05 /* Electrode Filtered Data MSB */
+#define MPR121_ELE1_L 0x06 /* Electrode Filtered Data LSB */
+#define MPR121_ELE1_H 0x07 /* Electrode Filtered Data MSB */
+#define MPR121_ELE2_L 0x08 /* Electrode Filtered Data LSB */
+#define MPR121_ELE2_H 0x09 /* Electrode Filtered Data MSB */
+#define MPR121_ELE3_L 0x0A /* Electrode Filtered Data LSB */
+#define MPR121_ELE3_H 0x0B /* Electrode Filtered Data MSB */
+#define MPR121_ELE4_L 0x0C /* Electrode Filtered Data LSB */
+#define MPR121_ELE4_H 0x0D /* Electrode Filtered Data MSB */
+#define MPR121_ELE5_L 0x0E /* Electrode Filtered Data LSB */
+#define MPR121_ELE5_H 0x0F /* Electrode Filtered Data MSB */
+#define MPR121_ELE6_L 0x10 /* Electrode Filtered Data LSB */
+#define MPR121_ELE6_H 0x11 /* Electrode Filtered Data MSB */
+#define MPR121_ELE7_L 0x12 /* Electrode Filtered Data LSB */
+#define MPR121_ELE7_H 0x13 /* Electrode Filtered Data MSB */
+#define MPR121_ELE8_L 0x14 /* Electrode Filtered Data LSB */
+#define MPR121_ELE8_H 0x15 /* Electrode Filtered Data MSB */
+#define MPR121_ELE9_L 0x16 /* Electrode Filtered Data LSB */
+#define MPR121_ELE9_H 0x17 /* Electrode Filtered Data MSB */
+#define MPR121_ELE10_L 0x18 /* Electrode Filtered Data LSB */
+#define MPR121_ELE10_H 0x19 /* Electrode Filtered Data MSB */
+#define MPR121_ELE11_L 0x1A
[U-Boot] [PATCH 0/8] zmx25: Add hardware support
From: Thomas Diener This patchset is the result of the "[PATCH 3/4] zmx25: Add extended support for the cpu and base boards" (http://patchwork.ozlabs.org/patch/341717/). I split the patch up as Stefano Babic recommended. Thomas Diener (8): imx25: Add new hardware registers drivers: Add polytouch touch sensor controller mxc_i2c: Use the 3th i2c channel for imx25 input: Add support for FMA1125 touch controller input: Add support for MPR121 touch controller zmx25: Extended support for cpu and base boards imx25: Add new registers defines video: imx25lcdc: add board_video_init() call arch/arm/include/asm/arch-mx25/imx-regs.h | 271 ++- arch/arm/include/asm/arch-mx25/iomux-mx25.h | 25 +- arch/arm/include/asm/imx-common/iomux-v3.h | 13 +- arch/arm/lib/asm-offsets.c |9 + board/syteco/zmx25/lowlevel_init.S | 21 + board/syteco/zmx25/zmx25.c | 1052 +-- drivers/i2c/mxc_i2c.c |2 +- drivers/input/Makefile |3 + drivers/input/fma1125.c | 47 ++ drivers/input/mpr121.c | 67 ++ drivers/input/polytouch.c | 138 drivers/video/imx25lcdc.c | 19 + include/configs/zmx25.h | 66 +- include/fma1125.h | 140 include/mpr121.h| 158 include/polytouch.h | 35 + 16 files changed, 1976 insertions(+), 90 deletions(-) create mode 100644 drivers/input/fma1125.c create mode 100644 drivers/input/mpr121.c create mode 100644 drivers/input/polytouch.c create mode 100644 include/fma1125.h create mode 100644 include/mpr121.h create mode 100644 include/polytouch.h -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/8] input: Add polytouch touch sensor controller
From: Thomas Diener
Signed-off-by: Thomas Diener
---
drivers/input/Makefile|1 +
drivers/input/polytouch.c | 138 +
include/polytouch.h | 35
3 files changed, 174 insertions(+)
create mode 100644 drivers/input/polytouch.c
create mode 100644 include/polytouch.h
diff --git a/drivers/input/Makefile b/drivers/input/Makefile
index a8e9be2..65c40ba 100644
--- a/drivers/input/Makefile
+++ b/drivers/input/Makefile
@@ -14,3 +14,4 @@ obj-$(CONFIG_PS2MULT) += ps2mult.o ps2ser.o
endif
obj-y += input.o
obj-$(CONFIG_OF_CONTROL) += key_matrix.o
+obj-$(CONFIG_POLYTOUCH) += polytouch.o
\ No newline at end of file
diff --git a/drivers/input/polytouch.c b/drivers/input/polytouch.c
new file mode 100644
index 000..9f1f38f
--- /dev/null
+++ b/drivers/input/polytouch.c
@@ -0,0 +1,138 @@
+/*
+ * (c) 2013 Graf-Syteco, Matthias Weisser
+ *
+ *
+ * polytouch.c - EDT PolyTouch capacitive touch sensor controller
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+
+#include
+#include
+#include
+
+
+#define POLYTOUCH_CMD_GETVERSION 0xBB
+#define POLYTOUCH_CMD_GETTOUCH 0xF9
+#define POLYTOUCH_CMD_SETREG 0xFC
+#define POLYTOUCH_CMD_GETREG 0xFC
+
+#define POLYTOUCH_REG_THRESHOLD0x00
+#define POLYTOUCH_REG_MONITORTIME 0x07
+#define POLYTOUCH_REG_REPORTRATE 0x08
+#define POLYTOUCH_REG_GAIN 0x30
+#define POLYTOUCH_REG_OFFSET 0x31
+#define POLYTOUCH_REG_XRES 0x33
+#define POLYTOUCH_REG_YRES 0x34
+#define POLYTOUCH_REG_HIBERNATE0x3A
+
+#define POLYTOUCH_PACKET_LENGTH26
+
+static int xres;
+static int yres;
+
+static int32_t polytouch_set_reg(uint32_t reg, uint32_t val)
+{
+ uint8_t buf[3];
+ int r;
+
+ buf[0] = reg;
+ buf[1] = val;
+ buf[2] = POLYTOUCH_CMD_SETREG ^ buf[0] ^ buf[1];
+
+ r = i2c_write(POLYTOUCH_SA, POLYTOUCH_CMD_SETREG, 1, buf, 3);
+
+ if (0 != r)
+ printf("i2c_write failed with %d\n", r);
+
+ return r;
+}
+
+static int32_t polytouch_get_reg(uint32_t reg)
+{
+ uint8_t buf;
+
+ if (i2c_read(POLYTOUCH_SA, (POLYTOUCH_CMD_GETREG<<8) +
+ ((reg + 0x40)<<0), 2, &buf, 1) == 0)
+ return buf;
+
+ return -1;
+}
+
+int polytouch_init(void)
+{
+ char buf[32];
+
+ if (!i2c_probe(POLYTOUCH_SA)) {
+ if (i2c_read(POLYTOUCH_SA, POLYTOUCH_CMD_GETVERSION, 1,
+ (uint8_t *)buf, 22) == 0) {
+ uint32_t gain = 7;
+ uint32_t threshold = 40;
+ uint32_t offset = 0;
+
+ buf[22] = '\0';
+
+ xres = polytouch_get_reg(POLYTOUCH_REG_XRES) * 64;
+ yres = polytouch_get_reg(POLYTOUCH_REG_YRES) * 64;
+
+ if (0 != strstr(buf, "EP035")) {
+ gain = 3;
+ threshold = 25;
+ offset = 34;
+ } else if (0 != strstr(buf, "EP043")) {
+ gain = 5;
+ threshold = 35;
+ offset = 34;
+ } else if (0 != strstr(buf, "EP057")) {
+ gain = 2;
+ threshold = 25;
+ offset = 34;
+ } else if (0 != strstr(buf, "EP070")) {
+ gain = 2;
+ threshold = 27;
+ offset = 34;
+ }
+
+ polytouch_set_reg(POLYTOUCH_REG_GAIN, gain);
+ polytouch_set_reg(POLYTOUCH_REG_THRESHOLD, threshold);
+ polytouch_set_reg(POLYTOUCH_REG_OFFSET, offset);
+ polytouch_set_reg(POLYTOUCH_REG_REPORTRATE, 8);
+ polytouch_set_reg(POLYTOUCH_REG_MONITORTIME, 0xC8);
+
+ return 1;
+ }
+ }
+ return 0;
+}
+
+void polytouch_get_resolution(struct polytouch_resolution *res)
+{
+ if (NULL != res) {
+ res->x = xres;
+ res->y = yres;
+ }
+}
+
+int polytouch_is_touched(struct polytouch_area *area)
+{
+ if (NULL != area) {
+ uint8_t buf[POLYTOUCH_PACKET_LENGTH];
+ if (0 == i2c_read(POLYTOUCH_SA, POLYTOUCH_CMD_GETTOUCH, 1, buf,
+ POLYTOUCH_PACKET_LENGTH)) {
+ if ((buf[0] == 0xAA) && (buf[1] == 0xAA) &&
+ (buf[2] == 0x1A) && (buf[3] == 0x01)) {
+ uint16_t x;
+ uint16_t y;
+
+ x = ((buf[5] & 0x0F) << 8) + buf[6];
+ y = ((buf[7] & 0x0F) << 8) + buf[8
Re: [U-Boot] [PATCH v3 0/5] ARM: refactor start.S files
On Tue, 15 Apr 2014 16:13:46 +0200, Albert ARIBAUD wrote: > This series aims at refactoring start.S files. Some of these > files contain cache-related or cpu-reset-related core, which > is moved where it belongs. Useless symbols are removed, and > finally, exception vector code, common across all ARM CPUs, > is moved in its own file. > > At this point, the start.S files only contain CPU-specific reset > sequences. > > Changes in v3: > - factorized SPL/non-SPL code > - fixed socfpga_cyclone5 IRQ setting in save_boot_params > > Changes in v2: > - fixed checkpatch issues in arch/arm/cpu/arm946es/cpu.c > - fixed checkpatch issues in arch/arm/cpu/sa1100/cpu.c > - rebased onto u-boot-arm/master (de4fdfc1) > - adjusted comment in Zynq linker script > > Albert ARIBAUD (5): > arm1136: move cache code from start.S to cache.c > arm: move reset_cpu from start.S into cpu.c > arm: pxa: move SP check from start.S to cpuinfo.c > arm: remove unused _end_vect and _vectors_end symbols > arm: move exception handling out of start.S files > > arch/arm/cpu/arm1136/start.S| 254 +--- > arch/arm/cpu/arm1176/start.S| 198 +-- > arch/arm/cpu/arm720t/start.S| 229 +- > arch/arm/cpu/arm920t/ep93xx/u-boot.lds | 3 +- > arch/arm/cpu/arm920t/start.S| 216 + > arch/arm/cpu/arm926ejs/mxs/start.S | 92 + > arch/arm/cpu/arm926ejs/spear/start.S| 27 +-- > arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds | 1 + > arch/arm/cpu/arm926ejs/start.S | 262 + > arch/arm/cpu/arm946es/cpu.c | 13 ++ > arch/arm/cpu/arm946es/start.S | 246 +-- > arch/arm/cpu/arm_intcm/start.S | 228 +- > arch/arm/cpu/armv7/socfpga/lowlevel_init.S | 15 +- > arch/arm/cpu/armv7/start.S | 253 +--- > arch/arm/cpu/armv7/zynq/u-boot.lds | 2 +- > arch/arm/cpu/pxa/cpuinfo.c | 6 + > arch/arm/cpu/pxa/start.S| 253 +--- > arch/arm/cpu/sa1100/cpu.c | 14 ++ > arch/arm/cpu/sa1100/start.S | 225 + > arch/arm/cpu/u-boot-spl.lds | 1 + > arch/arm/cpu/u-boot.lds | 1 + > arch/arm/lib/Makefile | 2 +- > arch/arm/lib/cache.c| 13 +- > arch/arm/lib/vectors.S | 291 > > board/compulab/cm_t335/u-boot.lds | 1 + > board/freescale/mx31ads/u-boot.lds | 1 + > board/ti/am335x/u-boot.lds | 1 + > 27 files changed, 359 insertions(+), 2489 deletions(-) > create mode 100644 arch/arm/lib/vectors.S Applied to u-boot-arm/master. Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] please pull u-boot-samsung master
Hi Minkyu, On Tue, 13 May 2014 19:47:35 +0900, Minkyu Kang wrote: > Dear Albert, > > The following changes since commit 7904b70885f3c589c239f6ac978f299a6744557f: > > ARM: highbank: use default prompt (2014-05-02 11:43:25 +0200) > > are available in the git repository at: > > http://git.denx.de/u-boot-samsung > > for you to fetch changes up to 9b97b727dcfbdc02a0a78e4c1d81670742f28784: Underway. Note: remote: error: refs/remotes/origin/mkimage does not point to a valid object! You should remove this branch from the remote repo. Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: Allow u-boot to run from offset base address
On 14-05-14 03:41 PM, Jeroen Hofstee wrote:
Hello Darwin,
On wo, 2014-05-14 at 15:05 -0700, Darwin Rambo wrote:
+#ifdef CONFIG_ARM64
+ /*
+* Fix relocation if u-boot is not on an aligned address.
+*/
+ {
+ int offset = CONFIG_SYS_TEXT_BASE % 4096;
+ if (offset) {
+ addr += offset;
+ debug("Relocation Addr bumped to 0x%08lx\n", addr);
+ }
+ }
+#endif
+
Do you really want to check a define at runtime? Placement is typically
at the end of RAM and allocation goes down, not up as in this patch.
Aren't you overlapping memory here?
Yes, I wanted the runtime check since the adjustment to the relocation
address is also done at runtime.
There is no overlap here. The reason is that the original masking operation
to mask to a 4K boundary removed the small offset and backed up too far. So
adding the lost offset is guaranteed to not overlap, and furthermore, correct
the relocation offset so that arm64 images can run at smaller alignments than
we normally use. This might even be a generic fix but can't be tested easily
by me.
static int setup_reloc(void)
{
+#ifdef CONFIG_ARM64
+ /*
+* Fix relocation if u-boot is not on an aligned address.
+*/
+ int offset = CONFIG_SYS_TEXT_BASE % 4096;
+ if (offset) {
+ gd->relocaddr += offset;
+ debug("Relocation Addr bumped to 0x%08lx\n", gd->relocaddr);
+ }
+#endif
gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
This is a generic file, hell breaks loose if you start using arch /
board / pre bootloader specific workarounds here afaiac.
I don't disagree with this statement. Please see my other comments to
Wolfgang on this topic.
lucky for you, I am not a u-boot maintainer, but this looks at least a
bit weird, glancing at it.
Regards,
Jeroen
Thanks for your comments Jeroen. They are appreciated.
Darwin
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Re: [U-Boot] [PATCH] arm: Allow u-boot to run from offset base address
On 14-05-14 09:26 PM, Wolfgang Denk wrote: Dear Darwin Rambo, In message <1400105145-6628-1-git-send-email-dra...@broadcom.com> you wrote: If an earlier loader stage requires an image header and a specific offset, then u-boot's base address (CONFIG_SYS_TEXT_BASE) may be advanced beyond an aligned address. In this case the relocation Sorry, I cannot parse that. CONFIG_SYS_TEXT_BASE is a compile time constant, it cannot be "advanced" by a loader. Do you mean that some loader loads U-Boot to an incorrect address? Well, in this case the loader should be fixed, or? Thank you for your comments. I mean that the loader loads u-boot to it's correct address, which is offset by a small amount because of a previous header requiring alignment. Here's an example. u-boot is compiled to run at 0x8820 because we want to put a small header in front of the image, which starts at 0x8800 and needs to be aligned for its own reasons. Now for arm64, I believe that u-boot cannot normally be positioned at any alignment less than 0x800 hex. So u-boot would normally run at addresses like 0x8800, 0x88000800, 0x88001000, etc. And in these cases the relocation works fine. But if we want to position u-boot at a smaller offset than 0x800, the symbol relocation breaks for arm64. It turns out that there is a trivial fix so that u-boot can run at smaller offset addresses, which I have provided here, is tested, and solves our problem nicely, but only for arm64 right now. This change is done under CONFIG_ARM64 conditional compilation because it has only been tested there and may not be appropriate for other architectures. In any case, any such changes (if there should be agreement that they are actually useful) should be done in an architecture-neutral way. Implementing it for one specific architecture only is wrong. Yes, I agree, but I am not sure if this is a arm64-only problem or not. Armv7 doesn't show this problem, and I can't test other architectures for their alignment issues. So I thought that I would at least show the fix for arm64 so we can decide if and how to proceed. Any suggestions you can provide on how to proceed would be appreciated. And if the fix is not suitable for upstreaming, then we should know it. Is there a way to have architecture specific hooks like this called from the generic common/board_f.c? The fix is also in arch/arm/lib/board.c but it sounds like that file might be disappearing. Also there might be a generic fix possible that works for all architectures (by removing the ifdef CONFIG_ARM64), but I don't have the resources to test them. Maybe it would be best to decide if we want to support this feature or not first. Thanks! Regards, Darwin Best regards, Wolfgang Denk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mmc: omap_hsmmc: add adma support
On Monday 12 May 2014 08:20 PM, Tom Rini wrote: On Mon, May 12, 2014 at 07:12:44PM +0530, Balaji T K wrote: On Monday 12 May 2014 06:58 PM, Tom Rini wrote: On Fri, May 02, 2014 at 07:25:20PM +0530, Balaji T K wrote: MMC instance 1 and 2 is capable of ADMA in omap4, omap5. Add support for ADMA and enable ADMA for read/write to improve mmc throughput. [snip] @@ -44,12 +45,30 @@ #undef OMAP_HSMMC_USE_GPIO #endif +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_OMAP_MMC_ADMA +#endif Why? Especially since a number of the folks interested in this for performance want it for SPL OS mode. Thanks! Because in SoCs like OMAP4/5 mmc1/2 adma doesn't have access to sram. So can't have descriptor or src / destination buffers (allocated on stack) given by mmc core on sram. And we can't malloc them? For descriptor yes, but for src / dest, I doubt since it would be difficult to force the upper (fs, mmc..) layers for controller limitation and some ARCH might require the buffers to be cache aligned Does malloc return buffers aligned to cache boundary ? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] dfu: Introduction of the "dfu_hash_algo" env variable for checksum method setting
Dear Lukasz, In message <20140515154334.626923b4@amdc2363> you wrote: > > > This reinforces my speculation that you are actually addressing the > > wrong problem. Instead of adding new code and environment variables > > and making the system even more complex, we should just leave > > everything as is, > > During working on this patch I've replaced the crc32() method with the > call to hash_method(), which IMHO is welcome. Yes, indeed this is highly welcome. Thanks a lot for that! > I also don't personally like the crc32, hence I like the choice which > this patch gives me to use other algorithm (for which I've got HW > support on my platform - e.g. MD5). Well, is this really useful? dfu-utils provides only CRC caculation, so where would you get the reference value for any other checksum metod from? > > and you should try to find out why the CRC > > calculation is so low for you. Checking if caches are enabled is > > probably among the things that should be done first. > > L1 is enabled. L2 has been disabled on purpose (power consumption > reduction). This certainly contributes to slow code execution. > Please note that the last revision of DFU is from 2004. I've contacted > Greg KH (one of the original authors) and he replied that no new attempt > to revise the standard was made. This may just mean that users were just happy with the current situation. It's definitely better than if changed had been proposed but rejected. > The best however, would be to revise the standard to include such > functionality to it. In the same time I'm fully aware that this is > very unlikely to happen. Why do you think it is unlikely? Of course, it would require that someone comes up with such a proposal in the first place. But you sound as if you were certain a proposal had no chance for being considered. I may be naive, but should we not at least try before giving up? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de God may be subtle, but He isn't plain mean. - Albert Einstein ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] dfu: Introduction of the "dfu_hash_algo" env variable for checksum method setting
Hi Wolfgang, > Dear Lukasz, > > In message <20140515090904.32f1d13d@amdc2363> you wrote: > > > > > > What I complained about is the change in behaviour. I asked to > > > > make the existing behaviour the default, so unaware users will > > > > not be affected. Only if you intentionally want some other > > > > behaviour you can then enable this by setting the env variable. > > > > > > Well, looking at mainline usage of DFU, Lukasz is speaking for > > > about half of the users / implementors. Since Denx is working > > > with the other half, can you shed some light on actual use vs > > > theoretical possibilities? > > > > I don't want to urge anybody on making any conclusion here :-), but > > I would be very grateful if we could come up with an agreement. > > > > As I've stated previously, my opinion is similar to the one > > presented by Tom in this message. > > > > For me it would be best to not calculate any checksum on default and > > only enable it when needed. > > I asked Heiko to run some actual tests on the boards where he has to > maintain DFU for. For a 288 MiB image he did not measure any > difference - with your patch applied, both with and without CRC > enabled, we would get the same (slow) 1:54 minutes download time. As I've spoken with Heiko, am33xx uses NAND memory. I deal with eMMC. Moreover, the size of "chunks" are different - 1 MiB and 32 MiB. I must double check for the rationale for chunk size of 32 MiB at Trats/Trats2 boards. I suspect, that eMMC write performance depend on that. I will perform some performance tests with 1 MiB chunk size and share the result. > > This reinforces my speculation that you are actually addressing the > wrong problem. Instead of adding new code and environment variables > and making the system even more complex, we should just leave > everything as is, During working on this patch I've replaced the crc32() method with the call to hash_method(), which IMHO is welcome. I also don't personally like the crc32, hence I like the choice which this patch gives me to use other algorithm (for which I've got HW support on my platform - e.g. MD5). > and you should try to find out why the CRC > calculation is so low for you. Checking if caches are enabled is > probably among the things that should be done first. L1 is enabled. L2 has been disabled on purpose (power consumption reduction). > > > Regarding the checksumming topic in general: the fact that the DFU > standard defines a method to verify the checksum of the image (dwCRC > field in the DFU File Suffix), but does not transmit this vital data > to the target so the actual file download and storage procedure on the > target is completely unprotected is IMO a serious design flaw of the > DFU protocl. Do you think it would be possible to have this augmented > / fixed? Please note that the last revision of DFU is from 2004. I've contacted Greg KH (one of the original authors) and he replied that no new attempt to revise the standard was made. It is possible to fix this problem, by augmenting the current implementation. I saw the idea [*] of defining only one (or special) alt setting and in this one file embed the header with integrity data, list of files/partitions images included in this file, and even the information to where we want to write. In this way we would still comply with DFU 1.1 standard, which would be "wrapped" to some host scripts and special u-boot code. It even would be possible to leave the current code untouched. The original link with the idea [*]: http://codelectron.wordpress.com/2014/02/28/flexible-firmware-upgrade/ And the ML discussion: http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/181715/match=proposal+hack+efficient+usb+dfu+linux+based+boards The best however, would be to revise the standard to include such functionality to it. In the same time I'm fully aware that this is very unlikely to happen. > > > > Best regards, > > Wolfgang Denk > -- Best regards, Lukasz Majewski Samsung R&D Institute Poland (SRPOL) | Linux Platform Group ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/5] zynq: fix OF control of Zynq
On 05/15/2014 01:37 PM, Masahiro Yamada wrote: > Zynq boards define CONFIG_OF_CONTROL and CONFIG_OF_SEPARATE, > but it is not working. > > One possible workaround was to edit include/configs/zynq-common.h > to disable > CONFIG_OF_CONTROL > CONFIG_OF_SEPARATE > CONFIG_DISPLAY_BOARDINFO_LATE > CONFIG_FIT_SIGNATURE > CONFIG_RSA > > I am not satisfied with this temporal workaround. > > My motivation is to run U-boot mainline on Zynq boards > with OF control. > > To achieve this, SPL must load u-boot-dtb.bin. > > 1/5 adds support u-boot-dtb.img (= uImage header + u-boot-dtb.bin) > > 2/5 switches to load u-boot-dtb.img. > > 3/5 thru 5/5 add missing some nodes to device tree. > > This series was tested on my ZC706 board. > > > Changes in v2: > - Select either "u-boot-dtb.img" or "u-boot.img" >for CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME. > - Import zynq-7000.dtsi from Linux Kernel v3.15-rc5 > > Masahiro Yamada (5): > build: support a new image u-boot-dtb.img > zynq: load u-boot-dtb.img if CONFIG_OF_SEPARATE is defined > zynq: import zynq-7000.dtsi from Linux Kernel > zynq: add memory nodes to device tree to initialize DRAM with OF > zynq: add UART nodes to device tree to initialize UART with OF > > Makefile | 8 ++ > arch/arm/dts/zynq-7000.dtsi | 194 > ++ > arch/arm/dts/zynq-microzed.dts| 9 ++ > arch/arm/dts/zynq-zc702.dts | 9 ++ > arch/arm/dts/zynq-zc706.dts | 9 ++ > arch/arm/dts/zynq-zc770-xm010.dts | 9 ++ > arch/arm/dts/zynq-zc770-xm012.dts | 9 ++ > arch/arm/dts/zynq-zc770-xm013.dts | 9 ++ > arch/arm/dts/zynq-zed.dts | 9 ++ > include/configs/zynq-common.h | 20 ++-- > 10 files changed, 277 insertions(+), 8 deletions(-) All patches are working fine I have tested it on zc702. Applied to my zynq branch. Thanks, Michal ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 4/5] net/designware: reorder struct dw_eth_dev to pack more efficiently.
On Wed, 14 May 2014 19:30:29 +0100
Ian Campbell wrote:
> On Thu, 2014-05-08 at 22:26 +0100, Ian Campbell wrote:
> > The {r,t}xbuffs fields also need to be aligned. Previously this was done
> > implicitly because they immediately followed the descriptor tables. Make
> > this
> > explicit and also move to the head of the struct.
>
> Looks like I managed to not actually commit the move of the field to the
> head of the struct! v3.1 follows
>
> Ian.
>
> 8<
>
> From 2937ba01841887317f6792709ed57cb86b5fc0cd Mon Sep 17 00:00:00 2001
> From: Ian Campbell
> Date: Thu, 1 May 2014 19:45:15 +0100
> Subject: [PATCH] net/designware: reorder struct dw_eth_dev to pack more
> efficiently.
>
> The {tx,rx}_mac_descrtable fields are aligned to ARCH_DMA_MINALIGN, which
> could
> be 256 or even larger. That means there is a potentially huge hole in the
> struct before those fields, so move them to the front where they are better
> packed.
>
> Moving them to the front also helps ensure that so long as dw_eth_dev is
> properly aligned (which it is since "net/designware: ensure device private
> data
> is DMA aligned.") the {tx,rx}_mac_descrtable will be too, or at least avoids
> having to worry too much about compiler specifics.
>
> The {r,t}xbuffs fields also need to be aligned. Previously this was done
> implicitly because they immediately followed the descriptor tables. Make this
> explicit and also move to the head of the struct.
>
> Signed-off-by: Ian Campbell
> Cc: Alexey Brodkin
> ---
> v3.1: Actually move to the head of the struct, like the commit log said...
> v3: Also align tx and rx bufs
> ---
> drivers/net/designware.h | 11 +--
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/net/designware.h b/drivers/net/designware.h
> index 382b0c7..de2fdcb 100644
> --- a/drivers/net/designware.h
> +++ b/drivers/net/designware.h
> @@ -215,15 +215,14 @@ struct dmamacdescr {
> #endif
>
> struct dw_eth_dev {
> - u32 interface;
> - u32 tx_currdescnum;
> - u32 rx_currdescnum;
> -
> struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
> struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
> + char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
> + char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
>
> - char txbuffs[TX_TOTAL_BUFSIZE];
> - char rxbuffs[RX_TOTAL_BUFSIZE];
> + u32 interface;
> + u32 tx_currdescnum;
> + u32 rx_currdescnum;
>
> struct eth_mac_regs *mac_regs_p;
> struct eth_dma_regs *dma_regs_p;
Thanks for your hard work addressing this nasty tftp breakage
regression on the Cubietruck (and on the other ARM hardware, which
happens to use the same designware driver). Now everything looks
perfect. The whole v3 patch set with this v3.1 reorder fix is
Tested-by: Siarhei Siamashka
and also if anybody cares
Reviewed-by: Siarhei Siamashka
--
Best regards,
Siarhei Siamashka
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[U-Boot] [PATCH] board/t208x: update t2080qds/t2080rdb for errata A-007186
As errata A-007186, we need to use the alternate serdes
protocol instead of those impacted protocols.
- add support for serdes protocols: 0x1b, 0x50, 0x5e,
0x64, 0x6a, 0xd2, 0x67, 0x70.
- update t2080_rcw.cfg to adapt to new rcw_66_15 for
t2080qds and t2080rdb.
Signed-off-by: Shengzhou Liu
---
arch/powerpc/cpu/mpc85xx/t2080_serdes.c | 26 +++---
board/freescale/t208xqds/eth_t208xqds.c | 8
board/freescale/t208xqds/t2080_rcw.cfg | 2 +-
board/freescale/t208xqds/t208xqds.c | 12 +---
board/freescale/t208xrdb/t2080_rcw.cfg | 2 +-
5 files changed, 38 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
index 07e27de..2b7c698 100644
--- a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
@@ -43,6 +43,10 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
{0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
PCIE4, PCIE4, PCIE4, PCIE4} },
+ {0x1B, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
@@ -59,18 +63,34 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x50, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+ XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+ PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{0x51, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
XAUI_FM1_MAC9, XAUI_FM1_MAC9,
PCIE4, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x5E, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{0x5F, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
PCIE4, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x64, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{0x65, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
PCIE4, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x6A, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+ XFI_FM1_MAC1, XFI_FM1_MAC2,
+ PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{0x6B, {XFI_FM1_MAC9, XFI_FM1_MAC10,
XFI_FM1_MAC1, XFI_FM1_MAC2,
PCIE4, SGMII_FM1_DTSEC4,
@@ -115,6 +135,9 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
{0xD9, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0xD2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{0xD3, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
@@ -127,8 +150,6 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
{0x66, {XFI_FM1_MAC9, XFI_FM1_MAC10,
XFI_FM1_MAC1, XFI_FM1_MAC2,
PCIE4, PCIE4, PCIE4, PCIE4} },
-
-#if defined(CONFIG_PPC_T2081)
{0xAA, {PCIE3, PCIE3, PCIE3, PCIE3,
PCIE4, PCIE4, PCIE4, PCIE4} },
{0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
@@ -137,7 +158,6 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
{0x70, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1,
SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
-#endif
{}
};
diff --git a/board/freescale/t208xqds/eth_t208xqds.c
b/board/freescale/t208xqds/eth_t208xqds.c
index d7a804d..5879198 100644
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -416,6 +416,7 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
switch (srds_s1) {
+ case 0x1b:
case 0x1c:
case 0x95:
case 0xa2:
@@ -429,8 +430,11 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
Re: [U-Boot] [Bug Report] Patman removes author's Signed-off-by credit
Hi Simon, On Wed, 14 May 2014 19:41:55 -0600 Simon Glass wrote: > > Yes I noticed it too. I am not sure how I introduced this bug, but it > serves me right for not writing a unit test. Please try this patch. > > http://patchwork.ozlabs.org/patch/348502/ > Oops, I overlooked this patch. I confirmed it fixed the problem. Thanks! Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/4] zynq: load u-boot-dtb.img for SD boot
Hi Michal, > > diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h > > index 731e69b..38e3d54 100644 > > --- a/include/configs/zynq-common.h > > +++ b/include/configs/zynq-common.h > > @@ -253,7 +253,7 @@ > > #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION1 > > #define CONFIG_SPL_LIBDISK_SUPPORT > > #define CONFIG_SPL_FAT_SUPPORT > > -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" > > +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot-dtb.img" > > Here should be just for sure. > #if defined(CONFIG_OF_CONTROL) && defined(CONFIG_OF_SEPARATE) > # define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot-dtb.img" > #else > # define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" > #endif Fixed in v2. Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/4] zynq: fix OF control of Zynq
On Wed, 14 May 2014 16:14:55 +0200 Michal Simek wrote: > I have tested it on zc702 and it is working correctly. > > Tested-by: Michal Simek > > Regarding patches 3/4 and 4/4 maybe will be just easier > to add full DTS because you will want to use OF configuration > for ethernet, mmc, usb, etc. Taken it from mainline kernel > make sense. Thanks for your review and test! I imported and adjusted zynq-7000.dtsi in v2. Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 5/5] zynq: add UART nodes to device tree to initialize UART with OF
Commit c9416b92 added OF UART initialization support
but aliases nodes are missing in device tree.
Signed-off-by: Masahiro Yamada
Cc: Michal Simek
Tested-by: Masahiro Yamada [on ZC706 board]
Tested-by: Michal Simek [on ZC702 board]
---
Changes in v2: None
arch/arm/dts/zynq-microzed.dts| 4
arch/arm/dts/zynq-zc702.dts | 4
arch/arm/dts/zynq-zc706.dts | 4
arch/arm/dts/zynq-zc770-xm010.dts | 4
arch/arm/dts/zynq-zc770-xm012.dts | 4
arch/arm/dts/zynq-zc770-xm013.dts | 4
arch/arm/dts/zynq-zed.dts | 4
7 files changed, 28 insertions(+)
diff --git a/arch/arm/dts/zynq-microzed.dts b/arch/arm/dts/zynq-microzed.dts
index 842896f..c373a2c 100644
--- a/arch/arm/dts/zynq-microzed.dts
+++ b/arch/arm/dts/zynq-microzed.dts
@@ -12,6 +12,10 @@
model = "Zynq MicroZED Board";
compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000";
+ aliases {
+ serial0 = &uart1;
+ };
+
memory {
device_type = "memory";
reg = <0 0x4000>;
diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
index a94e331..4fa0b00 100644
--- a/arch/arm/dts/zynq-zc702.dts
+++ b/arch/arm/dts/zynq-zc702.dts
@@ -12,6 +12,10 @@
model = "Zynq ZC702 Board";
compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
+ aliases {
+ serial0 = &uart1;
+ };
+
memory {
device_type = "memory";
reg = <0 0x4000>;
diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts
index 92de947..2a80195 100644
--- a/arch/arm/dts/zynq-zc706.dts
+++ b/arch/arm/dts/zynq-zc706.dts
@@ -12,6 +12,10 @@
model = "Zynq ZC706 Board";
compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
+ aliases {
+ serial0 = &uart1;
+ };
+
memory {
device_type = "memory";
reg = <0 0x4000>;
diff --git a/arch/arm/dts/zynq-zc770-xm010.dts
b/arch/arm/dts/zynq-zc770-xm010.dts
index 8d68208..5e66174 100644
--- a/arch/arm/dts/zynq-zc770-xm010.dts
+++ b/arch/arm/dts/zynq-zc770-xm010.dts
@@ -12,6 +12,10 @@
model = "Zynq ZC770 XM010 Board";
compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
+ aliases {
+ serial0 = &uart1;
+ };
+
memory {
device_type = "memory";
reg = <0 0x4000>;
diff --git a/arch/arm/dts/zynq-zc770-xm012.dts
b/arch/arm/dts/zynq-zc770-xm012.dts
index 9ebbddf..127a661 100644
--- a/arch/arm/dts/zynq-zc770-xm012.dts
+++ b/arch/arm/dts/zynq-zc770-xm012.dts
@@ -12,6 +12,10 @@
model = "Zynq ZC770 XM012 Board";
compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
+ aliases {
+ serial0 = &uart1;
+ };
+
memory {
device_type = "memory";
reg = <0 0x4000>;
diff --git a/arch/arm/dts/zynq-zc770-xm013.dts
b/arch/arm/dts/zynq-zc770-xm013.dts
index b4f7fa2..c61c7e7 100644
--- a/arch/arm/dts/zynq-zc770-xm013.dts
+++ b/arch/arm/dts/zynq-zc770-xm013.dts
@@ -12,6 +12,10 @@
model = "Zynq ZC770 XM013 Board";
compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000";
+ aliases {
+ serial0 = &uart0;
+ };
+
memory {
device_type = "memory";
reg = <0 0x4000>;
diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts
index 3488a56..70cc8a6 100644
--- a/arch/arm/dts/zynq-zed.dts
+++ b/arch/arm/dts/zynq-zed.dts
@@ -12,6 +12,10 @@
model = "Zynq ZED Board";
compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";
+ aliases {
+ serial0 = &uart1;
+ };
+
memory {
device_type = "memory";
reg = <0 0x2000>;
--
1.9.1
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[U-Boot] [PATCH v2 1/5] build: support a new image u-boot-dtb.img
In SPL framework, SPL uses u-boot.img to load u-boot.bin. Here, u-boot.img = uImage header + u-boot.bin To use OF control with a separate devicetree, u-boot.dtb must be placed right after u-boot.bin. In this case, u-boot-dtb.bin is generally used. Here, u-boot-dtb.bin = u-boot.bin + u-boot.dtb We need u-boot-dtb.img to use both SPL framework and separate OF control at the same time. u-boot-dtb.img = uImage header + u-boot-dtb.bin For example, Zynq boards already define all of - CONFIG_SPL - CONFIG_OF_CONTROL - CONFIG_OF_SEPARATE So, the support of u-boot-dtb.img is urgent. Signed-off-by: Masahiro Yamada Cc: Michal Simek Acked-by: Simon Glass --- Changes in v2: None Makefile | 8 1 file changed, 8 insertions(+) diff --git a/Makefile b/Makefile index e82f616..83d1cc6 100644 --- a/Makefile +++ b/Makefile @@ -752,6 +752,9 @@ ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin ALL-$(CONFIG_OF_SEPARATE) += u-boot.dtb u-boot-dtb.bin +ifeq ($(CONFIG_SPL_FRAMEWORK),y) +ALL-$(CONFIG_OF_SEPARATE) += u-boot-dtb.img +endif ALL-$(CONFIG_OF_HOSTFILE) += u-boot.dtb ifneq ($(CONFIG_SPL_TARGET),) ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%) @@ -854,6 +857,11 @@ MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \ u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE $(call if_changed,mkimage) +MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img) + +u-boot-dtb.img: u-boot-dtb.bin FORCE + $(call if_changed,mkimage) + u-boot.sha1: u-boot.bin tools/ubsha1 u-boot.bin -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 2/5] zynq: load u-boot-dtb.img if CONFIG_OF_SEPARATE is defined
SPL should load "u-boot-dtb.img" if both CONFIG_OF_CONTROL and CONFIG_OF_SEPARATE are defined. Otherwise, "u-boot.img" should be loaded. Since CONFIG_OF_CONTROL is always undefined for SPL_BUILD, the undef block should be moved below the conditional definition of CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME. Signed-off-by: Masahiro Yamada Cc: Michal Simek --- Changes in v2: - Select either "u-boot-dtb.img" or "u-boot.img" for CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME. include/configs/zynq-common.h | 20 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 731e69b..47b9d0d 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -238,13 +238,6 @@ #define CONFIG_SPL_LDSCRIPT"arch/arm/cpu/armv7/zynq/u-boot-spl.lds" -/* Disable dcache for SPL just for sure */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_DCACHE_OFF -#undef CONFIG_FPGA -#undef CONFIG_OF_CONTROL -#endif - /* MMC support */ #ifdef CONFIG_ZYNQ_SDHCI0 #define CONFIG_SPL_MMC_SUPPORT @@ -253,7 +246,18 @@ #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION1 #define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#if defined(CONFIG_OF_CONTROL) && defined(CONFIG_OF_SEPARATE) +# define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot-dtb.img" +#else +# define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#endif +#endif + +/* Disable dcache for SPL just for sure */ +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_DCACHE_OFF +#undef CONFIG_FPGA +#undef CONFIG_OF_CONTROL #endif /* Address in RAM where the parameters must be copied by SPL. */ -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 4/5] zynq: add memory nodes to device tree to initialize DRAM with OF
Commit 9e0e37ac added OF RAM initialization support
but memory nodes are missing in device tree.
Signed-off-by: Masahiro Yamada
Cc: Michal Simek
Tested-by: Masahiro Yamada [on ZC706 board]
Tested-by: Michal Simek [on ZC702 board]
---
Changes in v2: None
arch/arm/dts/zynq-microzed.dts| 5 +
arch/arm/dts/zynq-zc702.dts | 5 +
arch/arm/dts/zynq-zc706.dts | 5 +
arch/arm/dts/zynq-zc770-xm010.dts | 5 +
arch/arm/dts/zynq-zc770-xm012.dts | 5 +
arch/arm/dts/zynq-zc770-xm013.dts | 5 +
arch/arm/dts/zynq-zed.dts | 5 +
7 files changed, 35 insertions(+)
diff --git a/arch/arm/dts/zynq-microzed.dts b/arch/arm/dts/zynq-microzed.dts
index 6da71c1..842896f 100644
--- a/arch/arm/dts/zynq-microzed.dts
+++ b/arch/arm/dts/zynq-microzed.dts
@@ -11,4 +11,9 @@
/ {
model = "Zynq MicroZED Board";
compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000";
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x4000>;
+ };
};
diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
index 667dc28..a94e331 100644
--- a/arch/arm/dts/zynq-zc702.dts
+++ b/arch/arm/dts/zynq-zc702.dts
@@ -11,4 +11,9 @@
/ {
model = "Zynq ZC702 Board";
compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x4000>;
+ };
};
diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts
index 526fc88..92de947 100644
--- a/arch/arm/dts/zynq-zc706.dts
+++ b/arch/arm/dts/zynq-zc706.dts
@@ -11,4 +11,9 @@
/ {
model = "Zynq ZC706 Board";
compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x4000>;
+ };
};
diff --git a/arch/arm/dts/zynq-zc770-xm010.dts
b/arch/arm/dts/zynq-zc770-xm010.dts
index 8b542a1..8d68208 100644
--- a/arch/arm/dts/zynq-zc770-xm010.dts
+++ b/arch/arm/dts/zynq-zc770-xm010.dts
@@ -11,4 +11,9 @@
/ {
model = "Zynq ZC770 XM010 Board";
compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x4000>;
+ };
};
diff --git a/arch/arm/dts/zynq-zc770-xm012.dts
b/arch/arm/dts/zynq-zc770-xm012.dts
index 0379a07..9ebbddf 100644
--- a/arch/arm/dts/zynq-zc770-xm012.dts
+++ b/arch/arm/dts/zynq-zc770-xm012.dts
@@ -11,4 +11,9 @@
/ {
model = "Zynq ZC770 XM012 Board";
compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x4000>;
+ };
};
diff --git a/arch/arm/dts/zynq-zc770-xm013.dts
b/arch/arm/dts/zynq-zc770-xm013.dts
index a4f9e05..b4f7fa2 100644
--- a/arch/arm/dts/zynq-zc770-xm013.dts
+++ b/arch/arm/dts/zynq-zc770-xm013.dts
@@ -11,4 +11,9 @@
/ {
model = "Zynq ZC770 XM013 Board";
compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000";
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x4000>;
+ };
};
diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts
index 91a5deb..3488a56 100644
--- a/arch/arm/dts/zynq-zed.dts
+++ b/arch/arm/dts/zynq-zed.dts
@@ -11,4 +11,9 @@
/ {
model = "Zynq ZED Board";
compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x2000>;
+ };
};
--
1.9.1
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[U-Boot] [PATCH v2 0/5] zynq: fix OF control of Zynq
Zynq boards define CONFIG_OF_CONTROL and CONFIG_OF_SEPARATE, but it is not working. One possible workaround was to edit include/configs/zynq-common.h to disable CONFIG_OF_CONTROL CONFIG_OF_SEPARATE CONFIG_DISPLAY_BOARDINFO_LATE CONFIG_FIT_SIGNATURE CONFIG_RSA I am not satisfied with this temporal workaround. My motivation is to run U-boot mainline on Zynq boards with OF control. To achieve this, SPL must load u-boot-dtb.bin. 1/5 adds support u-boot-dtb.img (= uImage header + u-boot-dtb.bin) 2/5 switches to load u-boot-dtb.img. 3/5 thru 5/5 add missing some nodes to device tree. This series was tested on my ZC706 board. Changes in v2: - Select either "u-boot-dtb.img" or "u-boot.img" for CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME. - Import zynq-7000.dtsi from Linux Kernel v3.15-rc5 Masahiro Yamada (5): build: support a new image u-boot-dtb.img zynq: load u-boot-dtb.img if CONFIG_OF_SEPARATE is defined zynq: import zynq-7000.dtsi from Linux Kernel zynq: add memory nodes to device tree to initialize DRAM with OF zynq: add UART nodes to device tree to initialize UART with OF Makefile | 8 ++ arch/arm/dts/zynq-7000.dtsi | 194 ++ arch/arm/dts/zynq-microzed.dts| 9 ++ arch/arm/dts/zynq-zc702.dts | 9 ++ arch/arm/dts/zynq-zc706.dts | 9 ++ arch/arm/dts/zynq-zc770-xm010.dts | 9 ++ arch/arm/dts/zynq-zc770-xm012.dts | 9 ++ arch/arm/dts/zynq-zc770-xm013.dts | 9 ++ arch/arm/dts/zynq-zed.dts | 9 ++ include/configs/zynq-common.h | 20 ++-- 10 files changed, 277 insertions(+), 8 deletions(-) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 3/5] zynq: import zynq-7000.dtsi from Linux Kernel
Our current motivation is to use OF initialization for RAM and UART.
But adding full DTS would be helpful in future, for instance,
for OF configuration of Ethernet, MMC, USB, etc.
This commit imports arch/arm/boot/dts/zynq-7000.dtsi from Linux 3.15-rc5
and adjusts the license comment block for SPDX.
Signed-off-by: Masahiro Yamada
Suggested-by: Michal Simek
---
Changes in v2:
- Import zynq-7000.dtsi from Linux Kernel v3.15-rc5
arch/arm/dts/zynq-7000.dtsi | 194
1 file changed, 194 insertions(+)
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index f20b8bd..2d076f1 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -10,4 +10,198 @@
/ {
compatible = "xlnx,zynq-7000";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ reg = <0>;
+ clocks = <&clkc 3>;
+ clock-latency = <1000>;
+ operating-points = <
+ /* kHzuV */
+ 67 100
+ 34 100
+ 23 100
+ >;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ reg = <1>;
+ clocks = <&clkc 3>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <0 5 4>, <0 6 4>;
+ interrupt-parent = <&intc>;
+ reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
+ };
+
+ amba {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ ranges;
+
+ i2c0: zynq-i2c@e0004000 {
+ compatible = "cdns,i2c-r1p10";
+ status = "disabled";
+ clocks = <&clkc 38>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 25 4>;
+ reg = <0xe0004000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: zynq-i2c@e0005000 {
+ compatible = "cdns,i2c-r1p10";
+ status = "disabled";
+ clocks = <&clkc 39>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 48 4>;
+ reg = <0xe0005000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ intc: interrupt-controller@f8f01000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ interrupt-controller;
+ reg = <0xF8F01000 0x1000>,
+ <0xF8F00100 0x100>;
+ };
+
+ L2: cache-controller {
+ compatible = "arm,pl310-cache";
+ reg = <0xF8F02000 0x1000>;
+ arm,data-latency = <3 2 2>;
+ arm,tag-latency = <2 2 2>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ uart0: uart@e000 {
+ compatible = "xlnx,xuartps";
+ status = "disabled";
+ clocks = <&clkc 23>, <&clkc 40>;
+ clock-names = "ref_clk", "aper_clk";
+ reg = <0xE000 0x1000>;
+ interrupts = <0 27 4>;
+ };
+
+ uart1: uart@e0001000 {
+ compatible = "xlnx,xuartps";
+ status = "disabled";
+ clocks = <&clkc 24>, <&clkc 41>;
+ clock-names = "ref_clk", "aper_clk";
+ reg = <0xE0001000 0x1000>;
+ interrupts = <0 50 4>;
+ };
+
+ gem0: ethernet@e000b000 {
+ compatible = "cdns,gem";
+ reg = <0xe000b000 0x4000>;
+ status = "disabled";
+ interrupts = <0 22 4>;
+ clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
+ clock-names = "pclk", "hclk", "tx_clk";
+ };
+
+ gem1: ethernet@e000c000 {
+ compatible = "cdns,gem";
+ reg = <0xe000c000 0x4000>;
+
Re: [U-Boot] [PATCH v3] dfu: Introduction of the "dfu_hash_algo" env variable for checksum method setting
Dear Lukasz, In message <20140515090904.32f1d13d@amdc2363> you wrote: > > > > What I complained about is the change in behaviour. I asked to make > > > the existing behaviour the default, so unaware users will not be > > > affected. Only if you intentionally want some other behaviour you > > > can then enable this by setting the env variable. > > > > Well, looking at mainline usage of DFU, Lukasz is speaking for about > > half of the users / implementors. Since Denx is working with the > > other half, can you shed some light on actual use vs theoretical > > possibilities? > > I don't want to urge anybody on making any conclusion here :-), but I > would be very grateful if we could come up with an agreement. > > As I've stated previously, my opinion is similar to the one presented > by Tom in this message. > > For me it would be best to not calculate any checksum on default and > only enable it when needed. I asked Heiko to run some actual tests on the boards where he has to maintain DFU for. For a 288 MiB image he did not measure any difference - with your patch applied, both with and without CRC enabled, we would get the same (slow) 1:54 minutes download time. This reinforces my speculation that you are actually addressing the wrong problem. Instead of adding new code and environment variables and making the system even more complex, we should just leave everything as is, and you should try to find out why the CRC calculation is so low for you. Checking if caches are enabled is probably among the things that should be done first. Regarding the checksumming topic in general: the fact that the DFU standard defines a method to verify the checksum of the image (dwCRC field in the DFU File Suffix), but does not transmit this vital data to the target so the actual file download and storage procedure on the target is completely unprotected is IMO a serious design flaw of the DFU protocl. Do you think it would be possible to have this augmented / fixed? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de "Free markets select for winning solutions."- Eric S. Raymond ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH][v2] board/p1_p2_rdb:Enable p1_p2_rdb boot from NAND/SD/SPI in SPL
In the earlier patches, the SPL/TPL fraamework was introduced.
For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The
SPL was loaded by the code from the internal on-chip ROM. The SPL initializes
the DDR according to the SPD and loads the final uboot image into DDR, then
jump to the DDR to begin execution.
For NAND booting way, the nand SPL has size limitation on some board(e.g.
P1010RDB), it can not be more than 4KB, we can call it "minimal SPL", So the
dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is
loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD
and loads the final uboot image into DDR,then jump to the DDR to begin
execution.
This patch enabled SPL/TPL for P1_P2_RDB to support starting from NAND/SD/SPI
flash with SPL framework and initializing the DDR according to SPD in the
SPL/TPL.
Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to
execute, so the section .resetvec is no longer needed.
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Incroporated York' comments
board/freescale/p1_p2_rdb/Makefile | 21 +-
board/freescale/p1_p2_rdb/ddr.c| 16 +-
board/freescale/p1_p2_rdb/spl.c| 141 +
board/freescale/p1_p2_rdb/spl_minimal.c| 84
board/freescale/p1_p2_rdb/tlb.c| 18 +-
include/configs/P1_P2_RDB.h| 265
nand_spl/board/freescale/p1_p2_rdb/Makefile| 91
nand_spl/board/freescale/p1_p2_rdb/nand_boot.c | 82
8 files changed, 450 insertions(+), 268 deletions(-)
create mode 100644 board/freescale/p1_p2_rdb/spl.c
create mode 100644 board/freescale/p1_p2_rdb/spl_minimal.c
delete mode 100644 nand_spl/board/freescale/p1_p2_rdb/Makefile
delete mode 100644 nand_spl/board/freescale/p1_p2_rdb/nand_boot.c
diff --git a/board/freescale/p1_p2_rdb/Makefile
b/board/freescale/p1_p2_rdb/Makefile
index f7b568a..a97bf45 100644
--- a/board/freescale/p1_p2_rdb/Makefile
+++ b/board/freescale/p1_p2_rdb/Makefile
@@ -4,8 +4,27 @@
# SPDX-License-Identifier: GPL-2.0+
#
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+obj-y += spl_minimal.o tlb.o law.o
+
+else
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
obj-y += p1_p2_rdb.o
+obj-$(CONFIG_PCI) += pci.o
+endif
obj-y += ddr.o
obj-y += law.o
-obj-$(CONFIG_PCI) += pci.o
obj-y += tlb.o
+
+endif
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
index 17d3bea..98ee5f1 100644
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -180,27 +180,22 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
phys_size_t fixed_sdram (void)
{
- char buf[32];
fsl_ddr_cfg_regs_t ddr_cfg_regs;
size_t ddr_size;
struct cpu_type *cpu;
ulong ddr_freq, ddr_freq_mhz;
cpu = gd->arch.cpu;
- /* P1020 and it's derivatives support max 32bit DDR width */
- if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
- ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
- } else {
- ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
- }
+
+ ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
#if defined(CONFIG_SYS_RAMBOOT)
return ddr_size;
#endif
ddr_freq = get_ddr_freq(0);
ddr_freq_mhz = ddr_freq / 100;
- printf("Configuring DDR for %s MT/s data rate\n",
- strmhz(buf, ddr_freq));
+ printf("Configuring DDR for %ld T/s data rate\n", ddr_freq);
if(ddr_freq_mhz <= 400)
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
@@ -211,8 +206,7 @@ phys_size_t fixed_sdram (void)
else if(ddr_freq_mhz <= 800)
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
else
- panic("Unsupported DDR data rate %s MT/s data rate\n",
- strmhz(buf, ddr_freq));
+ panic("Unsupported DDR data rate %ld T/s\n", ddr_freq);
/* P1020 and it's derivatives support max 32bit DDR width */
if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
diff --git a/board/freescale/p1_p2_rdb/spl.c b/board/freescale/p1_p2_rdb/spl.c
new file mode 100644
index 000..f30c5fe
--- /dev/null
+++ b/board/freescale/p1_p2_rdb/spl.c
@@ -0,0 +1,141 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SYSCLK_MASK0x0020
+#define BOARDREV_MASK 0x1010
+
+#define SYSCLK_66
+#define SYSCLK_100 1
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx
Re: [U-Boot] [PATCH v3] dfu: Introduction of the "dfu_hash_algo" env variable for checksum method setting
Hello Lukasz, Sorry for answering so late to this thread ... Am 15.05.2014 09:09, schrieb Lukasz Majewski: Hi Tom, Wolfgang, On Fri, May 09, 2014 at 10:31:54AM +0200, Wolfgang Denk wrote: Dear Lukasz, In message<20140509085203.31133238@amdc2363> you wrote: For automated tests I use MD5 and compare this value before sending data to target via DFU and after I read it. This testing is done purely on HOST machine. This is unsufficient. You should always verify the image on the target after the download has completed. True. But this patch doesn't really change what you would have to do, and arguably make it easier. Participants have agreed, that we shall optionally enable crc32 (or other algorithm) calculation. If this is the default now, it should remain the default. Keep in mind what this current default is. We say "here was the CRC32". We do not compare it with an expected value nor do we have the ability to since we're not passed from the host what the value was. 2. The current crc32 implementation is painfully slow (although I have only L1 enabled on my target). This is an unrelated problem then, which should excluded from this discussion here. Agreed. 3. With large files (like rootfs images) we store data (to medium) with 32 MiB chunks, which means that when we calculate complete crc32 the image is already written to its final destination. You can still detect if the download was corrupted, report a proper error and initiate a re-download. This would at least give you a chance to react to corrupted data. Just closing the eyes and hoping no errors will ever happen has always been a bad strategy. Before and after this change, only if the console is being monitored by some script. We do not nor are we given an expected hash so we cannot say data was corrupted. 4. This patch also allows some flexibility: by setting the env variable we can decide which algorithm to use (crc32, sha1, etc). It is appealing since we use the hash_* code anyway. Agreed. This was not my point. What I complained about is the change in behaviour. I asked to make the existing behaviour the default, so unaware users will not be affected. Only if you intentionally want some other behaviour you can then enable this by setting the env variable. Well, looking at mainline usage of DFU, Lukasz is speaking for about half of the users / implementors. Since Denx is working with the other half, can you shed some light on actual use vs theoretical possibilities? I don't want to urge anybody on making any conclusion here :-), but I would be very grateful if we could come up with an agreement. As I've stated previously, my opinion is similar to the one presented by Tom in this message. For me it would be best to not calculate any checksum on default and only enable it when needed. Hmm.. as we use the calculated crc only for printing it on the console, the question is really, why should we calculate it? I try this patch on the siemens boards and report if the speed impact is there also so big as in your tests. (which board was this? Are there caches enabled?) And I ask the customer of the siemens boards, if they check the crc value on the u-boot console output, if not, I vote for droping the crc calculation as default ... BTW: Should such a crc check not be added to dfu-util and u-boot? bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] serial_mxc: disable new features of autobaud detection
Hi Eric, On 15/05/2014 01:58, Eric Nelson wrote: > Bit 7 of UCR3 is described in the i.MX3x/i.MX5x/i.MX6x > reference manuals as follows: > > Autobaud Detection Not Improved-. Disables new features of > autobaud detection (See Baud Rate Automatic Detection > Protocol, for more details). > > 0 Autobaud detection new features selected > 1 Keep old autobaud detection mechanism > > On at least i.MX6DQ, i.MX6DLS and i.MX53, the "new features" > occasionally cause the receiver to get out of sync and > continuously produce received characters of '\xff'. > > This patch disables the "new feature" on all boards, since > there's no support for auto-baud in U-Boot on any of them. > > More details are available in this post on i.MX Community: > https://community.freescale.com/message/403254 > > Signed-off-by: Eric Nelson > Tested-by: Fabio Estevam > --- > drivers/serial/serial_mxc.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c > index 56bee55..313d560 100644 > --- a/drivers/serial/serial_mxc.c > +++ b/drivers/serial/serial_mxc.c > @@ -77,7 +77,7 @@ > #define UCR3_DSR(1<<10) /* Data set ready */ > #define UCR3_DCD(1<<9) /* Data carrier detect */ > #define UCR3_RI (1<<8) /* Ring indicator */ > -#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ > +#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ > #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ > #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ > #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ > @@ -186,7 +186,7 @@ static int mxc_serial_init(void) > > while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST)); > > - __REG(UART_PHYS + UCR3) = 0x0704; > + __REG(UART_PHYS + UCR3) = 0x0704 | UCR3_ADNIMP; > __REG(UART_PHYS + UCR4) = 0x8000; > __REG(UART_PHYS + UESC) = 0x002b; > __REG(UART_PHYS + UTIM) = 0x0; > Thanks to have found a solved this issue ! Acked-by: Stefano Babic Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 12/12] imx: ventana: switch to SPL
Hi Tim, On 15/05/2014 00:32, Tim Harvey wrote: > > I figured this one out - it has nothing to do with the order of > calling arch_cpu_init() its that the MMDC isn't always 'ready' by the > time the BSS is cleared and thus in my failure case the BSS isn't > getting entirely cleared which causes the spl_image global var to not > be cleared as expected and triggers an invalid codepath. I will update > the mmdc config patch when I find the right solution. Thanks for the explanation ! I cannot guess why arch_cpu_init() should be called later. Nice you found the reason ! > > Sorry for the noise. There was no noise ;-) Best regards, Stefano -- = DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PULL] : Please pull u-boot-imx
Hi Albert, please pull from u-boot-imx, thanks ! The following changes since commit d2a3e911390f9fc4d8c0ee4b3c7fc75f4fd3fd19: Merge branch 'u-boot/master' (2014-05-09 11:50:14 +0200) are available in the git repository at: git://www.denx.de/git/u-boot-imx.git master for you to fetch changes up to e7f9350525d73233d4eaf1793f8fe618e9fd4910: Merge branch 'master' of git://git.denx.de/u-boot-arm (2014-05-15 10:27:32 +0200) Eric Benard (8): imx-common: add board_video_skip nitrogen6x: use common board_video_skip mx6sabresd: use common board_video_skip RiOTboard and MarSBoard: add new boards support imx-common/video: add detect_hdmi nitrogen6x: use common detect_hdmi mx6sabresd: use common detect_hdmi embest/mx6boards: use common detect_hdmi Eric Nelson (1): ARM: imx6: nitrogen6x: Enable CONFIG_SYS_GENERIC_BOARD Fabio Estevam (11): wandboard: Convert to generic board mx53loco: Convert to generic board mx6sabre_common: Convert to generic board mx53ard: Convert to generic board mx53smd: Convert to generic board mx53evk: Convert to generic board udoo: Convert to generic board hummingboard: Convert to generic board mx6slevk: Add SPI NOR flash support nitrogen6x: Fix the PAD settings for the ECSPI chipselect iomux-v3: Add support for mx6sl LVE bit Marek Vasut (1): arm: mxs: Enable CONFIG_SYS_GENERIC_BOARD Otavio Salvador (2): wandboard: add Future Eletronics 7" WVGA LCD extension board wandboard: Pass video kernel arguments for HDMI and LCD Stefano Babic (3): mx6: fix weird formatting in imx6q-sabreauto.dts Merge branch 'master' of git://git.denx.de/u-boot-arm Merge branch 'master' of git://git.denx.de/u-boot-arm Thomas Diener (2): imx25: Add new hardware registers video: Add support for imx25 lcd controller Tim Harvey (10): ventana: fixed comments in eeprom header ventana: remove redundant include power: make pfuze100 be able to coexist with other pmics ventana: use non-generic pfuze100 init power: Add support for LTC3676 PMIC ventana: Add support for the LTC3676 PMIC imx6: ventana: fix system-serial dt property imx: ventana: Convert to generic board imx: ventana: add HDMI and LVDS display capability nand: remove CONFIG_SYS_NAND_PAGE_SIZE arch/arm/dts/imx6q-sabreauto.dts| 10 +- arch/arm/imx-common/Makefile| 1 + arch/arm/imx-common/iomux-v3.c | 8 + arch/arm/imx-common/video.c | 65 arch/arm/include/asm/arch-mx25/imx-regs.h | 175 arch/arm/include/asm/arch-mx6/mx6sl_pins.h | 4 + arch/arm/include/asm/imx-common/iomux-v3.h | 5 + arch/arm/include/asm/imx-common/video.h | 24 +++ board/boundary/nitrogen6x/nitrogen6x.c | 69 +--- board/embest/mx6boards/Makefile | 9 ++ board/embest/mx6boards/mx6boards.c | 601 + board/freescale/mx6sabresd/mx6sabresd.c | 67 +--- board/freescale/mx6slevk/mx6slevk.c | 20 +++ board/gateworks/gw_ventana/gw_ventana.c | 215 ++--- board/gateworks/gw_ventana/ventana_eeprom.h | 14 +- board/wandboard/wandboard.c | 146 ++--- boards.cfg | 2 + common/spl/spl_nand.c | 2 +- drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_ltc3676.c | 32 drivers/power/pmic/pmic_pfuze100.c | 2 +- drivers/video/Makefile | 1 + drivers/video/imx25lcdc.c | 121 ++ include/configs/embestmx6boards.h | 336 +++ include/configs/gw_ventana.h| 20 +++ include/configs/hummingboard.h | 2 + include/configs/m28evk.h| 1 - include/configs/mx53ard.h | 2 + include/configs/mx53evk.h | 2 + include/configs/mx53loco.h | 2 + include/configs/mx53smd.h | 2 + include/configs/mx6sabre_common.h | 2 + include/configs/mx6sabresd.h| 1 + include/configs/mx6slevk.h | 12 ++ include/configs/mxs.h | 1 + include/configs/nitrogen6x.h| 2 + include/configs/udoo.h | 2 + include/configs/wandboard.h | 38 - include/power/ltc3676_pmic.h| 51 ++ include/power/pfuze100_pmic.h | 1 + 40 files changed, 1876 insertions(+), 195 deletions(-) create mode 100644 arch/arm/imx-common/video.c create mode 100644 arch/arm/include/asm/imx-common/video.h create m
[U-Boot] [RESEND PATCHv4 14/14] mmc: s5p_sdhci: add the s5p_sdhci_core_init function
To reuse the code, added the s5p_sdhci_core_init function.
Before applied this patch, didn't use the 8-bit mode at exynos baord.
Because it didn't set "MMC_MODE_8BIT".
Signed-off-by: Jaehoon Chung
Tested-by: Lukasz Majewski
Acked-by: Lukasz Majewski
---
drivers/mmc/s5p_sdhci.c | 42 +-
1 file changed, 17 insertions(+), 25 deletions(-)
diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c
index ccae4cc..2ff0ec2 100644
--- a/drivers/mmc/s5p_sdhci.c
+++ b/drivers/mmc/s5p_sdhci.c
@@ -65,17 +65,9 @@ static void s5p_sdhci_set_control_reg(struct sdhci_host
*host)
sdhci_writel(host, ctrl, SDHCI_CONTROL2);
}
-int s5p_sdhci_init(u32 regbase, int index, int bus_width)
+static int s5p_sdhci_core_init(struct sdhci_host *host)
{
- struct sdhci_host *host = NULL;
- host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
- if (!host) {
- printf("sdhci__host malloc fail!\n");
- return 1;
- }
-
host->name = S5P_NAME;
- host->ioaddr = (void *)regbase;
host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR |
@@ -85,15 +77,28 @@ int s5p_sdhci_init(u32 regbase, int index, int bus_width)
host->set_control_reg = &s5p_sdhci_set_control_reg;
host->set_clock = set_mmc_clk;
- host->index = index;
host->host_caps = MMC_MODE_HC;
- if (bus_width == 8)
+ if (host->bus_width == 8)
host->host_caps |= MMC_MODE_8BIT;
return add_sdhci(host, 5200, 40);
}
+int s5p_sdhci_init(u32 regbase, int index, int bus_width)
+{
+ struct sdhci_host *host = malloc(sizeof(struct sdhci_host));
+ if (!host) {
+ printf("sdhci__host malloc fail!\n");
+ return 1;
+ }
+ host->ioaddr = (void *)regbase;
+ host->index = index;
+ host->bus_width = bus_width;
+
+ return s5p_sdhci_core_init(host);
+}
+
#ifdef CONFIG_OF_CONTROL
struct sdhci_host sdhci_host[SDHCI_MAX_HOSTS];
@@ -126,20 +131,7 @@ static int do_sdhci_init(struct sdhci_host *host)
}
}
- host->name = S5P_NAME;
-
- host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
- SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR |
- SDHCI_QUIRK_WAIT_SEND_CMD;
- host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
- host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
-
- host->set_control_reg = &s5p_sdhci_set_control_reg;
- host->set_clock = set_mmc_clk;
-
- host->host_caps = MMC_MODE_HC;
-
- return add_sdhci(host, 5200, 40);
+ return s5p_sdhci_core_init(host);
}
static int sdhci_get_config(const void *blob, int node, struct sdhci_host
*host)
--
1.7.9.5
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[U-Boot] [RESEND PATCHv4 00/14] mmc: exynos: code cleanup and support DDR mode
If card and host are supported DDR mode, then it can be used the DDR mode. This patch-set has dependency about beomho's patch-set. (Based-on u-boot-samsung repository) It's result for loading image. sdhci controller ->5260488 bytes read in 259 ms (19.4 MiB/s) dwmmc controller without DDR mode -> 5260488 bytes read in 202 ms (24.8 MiB/s) dwmmc controller with DDR mode -> 5260488 bytes read in 118 ms (42.5 MiB/s) Download the 400M image with lthor. sdhci controller -> 59.4sec (Avg 6.95 MB/s) dwmmc controller without DDR mode -> 61.6sec (Avg 6.72MB/s) dwmmc controller with DDR mode -> 60.4sec (Avg 6.85MB/s) Beomho Seo (3): arm: exynos: pinmux: add sdmmc4 gpio configratuion arm: exynos: clock: Remove exynos4x12_set_mmc_clk function board: trats2: Enable device tree on Trats2 Jaehoon Chung (11): ARM: exynos: board: change the mmc/sd init sequence ARM: exynos: clock: modify the set_mmc_clk for exynos4 ARM: dts: exynos: rename from EXYNOS5_DWMMC to EXYNOS_DWMMC mmc: exynos_dw_mmc: restore the property into host mmc: remove the unnecessary define and fix the wrong bit control mmc: support the DDR mode for eMMC mmc: dw_mmc: support the DDR mode ARM: dts: exnyos: enable dw-mmc controller mmc: exynos_dw_mmc: enable the DDR mode ARM: exynos4: enable the dwmmc configuration mmc: s5p_sdhci: add the s5p_sdhci_core_init function arch/arm/cpu/armv7/exynos/clock.c | 45 ++- arch/arm/cpu/armv7/exynos/pinmux.c| 35 - arch/arm/dts/exynos4.dtsi |8 ++ arch/arm/dts/exynos4412-trats2.dts| 12 ++ arch/arm/dts/exynos5.dtsi |8 +- arch/arm/include/asm/arch-exynos/clk.h|5 + board/samsung/common/board.c | 13 +- doc/device-tree-bindings/exynos/dwmmc.txt |8 +- drivers/mmc/dw_mmc.c | 12 +- drivers/mmc/exynos_dw_mmc.c | 206 +++-- drivers/mmc/mmc.c | 16 ++- drivers/mmc/s5p_sdhci.c | 42 +++--- include/configs/exynos4-dt.h |3 + include/dwmmc.h |5 + include/fdtdec.h |2 +- include/mmc.h | 25 ++-- lib/fdtdec.c |2 +- 17 files changed, 277 insertions(+), 170 deletions(-) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RESEND PATCHv4 13/14] ARM: exynos4: enable the dwmmc configuration
Signed-off-by: Jaehoon Chung Tested-by: Lukasz Majewski Acked-by: Lukasz Majewski --- include/configs/exynos4-dt.h |3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/exynos4-dt.h b/include/configs/exynos4-dt.h index 2040bf7..7710bae 100644 --- a/include/configs/exynos4-dt.h +++ b/include/configs/exynos4-dt.h @@ -44,6 +44,9 @@ #define CONFIG_S5P_SDHCI #define CONFIG_SDHCI #define CONFIG_MMC_SDMA +#define CONFIG_DWMMC +#define CONFIG_EXYNOS_DWMMC +#define CONFIG_BOUNCE_BUFFER #define CONFIG_MMC_DEFAULT_DEV 0 /* PWM */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RESEND PATCHv4 04/14] ARM: exynos: board: change the mmc/sd init sequence
Exynos4 can be used the dwmmc controller for eMMC.
Then it needs to check dwmmc_init() at first.
Signed-off-by: Jaehoon Chung
Reviewed-by: Lukasz Majewski
Tested-by: Lukasz Majewski
Acked-by: Lukasz Majewski
---
board/samsung/common/board.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index de154e0..9dc7c83 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -243,13 +243,6 @@ int board_eth_init(bd_t *bis)
int board_mmc_init(bd_t *bis)
{
int ret;
-
-#ifdef CONFIG_SDHCI
- /* mmc initializattion for available channels */
- ret = exynos_mmc_init(gd->fdt_blob);
- if (ret)
- debug("mmc init failed\n");
-#endif
#ifdef CONFIG_DWMMC
/* dwmmc initializattion for available channels */
ret = exynos_dwmmc_init(gd->fdt_blob);
@@ -257,6 +250,12 @@ int board_mmc_init(bd_t *bis)
debug("dwmmc init failed\n");
#endif
+#ifdef CONFIG_SDHCI
+ /* mmc initializattion for available channels */
+ ret = exynos_mmc_init(gd->fdt_blob);
+ if (ret)
+ debug("mmc init failed\n");
+#endif
return ret;
}
#endif
--
1.7.9.5
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[U-Boot] [RESEND PATCHv4 08/14] mmc: remove the unnecessary define and fix the wrong bit control
Signed-off-by: Jaehoon Chung Reviewed-by: Lukasz Majeski Tested-by: Lukasz Majewski Acked-by: Lukasz Majewski --- drivers/mmc/mmc.c |2 +- include/mmc.h | 18 ++ 2 files changed, 7 insertions(+), 13 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 16051e5..dd6a6ef 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -514,7 +514,7 @@ static int mmc_change_freq(struct mmc *mmc) return 0; /* High Speed is set, there are two types: 52MHz and 26MHz */ - if (cardtype & MMC_HS_52MHZ) + if (cardtype & EXT_CSD_CARD_TYPE_52) mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; else mmc->card_caps |= MMC_MODE_HS; diff --git a/include/mmc.h b/include/mmc.h index 42d0125..da9f812 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -31,15 +31,12 @@ #define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x429) #define MMC_VERSION_4_5(MMC_VERSION_MMC | 0x405) -#define MMC_MODE_HS0x001 -#define MMC_MODE_HS_52MHz 0x010 -#define MMC_MODE_4BIT 0x100 -#define MMC_MODE_8BIT 0x200 -#define MMC_MODE_SPI 0x400 -#define MMC_MODE_HC0x800 - -#define MMC_MODE_MASK_WIDTH_BITS (MMC_MODE_4BIT | MMC_MODE_8BIT) -#define MMC_MODE_WIDTH_BITS_SHIFT 8 +#define MMC_MODE_HS(1 << 0) +#define MMC_MODE_HS_52MHz (1 << 1) +#define MMC_MODE_4BIT (1 << 2) +#define MMC_MODE_8BIT (1 << 3) +#define MMC_MODE_SPI (1 << 4) +#define MMC_MODE_HC(1 << 5) #define SD_DATA_4BIT 0x0004 @@ -97,9 +94,6 @@ #define SD_HIGHSPEED_BUSY 0x0002 #define SD_HIGHSPEED_SUPPORTED 0x0002 -#define MMC_HS_TIMING 0x0100 -#define MMC_HS_52MHZ 0x2 - #define OCR_BUSY 0x8000 #define OCR_HCS0x4000 #define OCR_VOLTAGE_MASK 0x007FFF80 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RESEND PATCHv4 06/14] ARM: dts: exynos: rename from EXYNOS5_DWMMC to EXYNOS_DWMMC
Exynos serise can be supported the dw-mmc controller.
So, it's good that used the general prefix as "_EXYNOS_DWMMC".
Signed-off-by: Jaehoon Chung
---
arch/arm/dts/exynos5.dtsi |8
doc/device-tree-bindings/exynos/dwmmc.txt |8
include/fdtdec.h |2 +-
lib/fdtdec.c |2 +-
4 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/dts/exynos5.dtsi b/arch/arm/dts/exynos5.dtsi
index f8c8741..a2b533a 100644
--- a/arch/arm/dts/exynos5.dtsi
+++ b/arch/arm/dts/exynos5.dtsi
@@ -136,7 +136,7 @@
mmc@1220 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "samsung,exynos5250-dwmmc";
+ compatible = "samsung,exynos-dwmmc";
reg = <0x1220 0x1000>;
interrupts = <0 75 0>;
};
@@ -144,7 +144,7 @@
mmc@1221 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "samsung,exynos5250-dwmmc";
+ compatible = "samsung,exynos-dwmmc";
reg = <0x1221 0x1000>;
interrupts = <0 76 0>;
};
@@ -152,7 +152,7 @@
mmc@1222 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "samsung,exynos5250-dwmmc";
+ compatible = "samsung,exynos-dwmmc";
reg = <0x1222 0x1000>;
interrupts = <0 77 0>;
};
@@ -160,7 +160,7 @@
mmc@1223 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "samsung,exynos5250-dwmmc";
+ compatible = "samsung,exynos-dwmmc";
reg = <0x1223 0x1000>;
interrupts = <0 78 0>;
};
diff --git a/doc/device-tree-bindings/exynos/dwmmc.txt
b/doc/device-tree-bindings/exynos/dwmmc.txt
index 566da3b..694d195 100644
--- a/doc/device-tree-bindings/exynos/dwmmc.txt
+++ b/doc/device-tree-bindings/exynos/dwmmc.txt
@@ -1,18 +1,18 @@
-* Exynos 5250 DWC_mobile_storage
+* Exynos DWC_mobile_storage
-The Exynos 5250 provides DWC_mobile_storage interface which supports
+The Exynos provides DWC_mobile_storage interface which supports
. Embedded Multimedia Cards (EMMC-version 4.5)
. Secure Digital memory (SD mem-version 2.0)
. Secure Digital I/O (SDIO-version 3.0)
. Consumer Electronics Advanced Transport Architecture (CE-ATA-version 1.1)
-The Exynos 5250 DWC_mobile_storage provides four channels.
+The Exynos DWC_mobile_storage provides four channels.
SOC specific and Board specific properties are channel specific.
Required SoC Specific Properties:
- compatible: should be
- - samsung,exynos5250-dwmmc: for exynos5250 platforms
+ - samsung,exynos-dwmmc: for exynos platforms
- reg: physical base address of the controller and length of memory mapped
region.
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 3196cf6..8c751fd 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -81,7 +81,7 @@ enum fdt_compat_id {
COMPAT_SAMSUNG_EXYNOS_FIMD, /* Exynos Display controller */
COMPAT_SAMSUNG_EXYNOS_MIPI_DSI, /* Exynos mipi dsi */
COMPAT_SAMSUNG_EXYNOS5_DP, /* Exynos Display port controller */
- COMPAT_SAMSUNG_EXYNOS5_DWMMC, /* Exynos5 DWMMC controller */
+ COMPAT_SAMSUNG_EXYNOS_DWMMC,/* Exynos DWMMC controller */
COMPAT_SAMSUNG_EXYNOS_MMC, /* Exynos MMC controller */
COMPAT_SAMSUNG_EXYNOS_SERIAL, /* Exynos UART */
COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 33265ec..86b88c7 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -54,7 +54,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(SAMSUNG_EXYNOS_FIMD, "samsung,exynos-fimd"),
COMPAT(SAMSUNG_EXYNOS_MIPI_DSI, "samsung,exynos-mipi-dsi"),
COMPAT(SAMSUNG_EXYNOS5_DP, "samsung,exynos5-dp"),
- COMPAT(SAMSUNG_EXYNOS5_DWMMC, "samsung,exynos5250-dwmmc"),
+ COMPAT(SAMSUNG_EXYNOS_DWMMC, "samsung,exynos-dwmmc"),
COMPAT(SAMSUNG_EXYNOS_MMC, "samsung,exynos-mmc"),
COMPAT(SAMSUNG_EXYNOS_SERIAL, "samsung,exynos4210-uart"),
COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686_pmic"),
--
1.7.9.5
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[U-Boot] [RESEND PATCHv4 07/14] mmc: exynos_dw_mmc: restore the property into host
Restore the platdata(property of dt) into host struct.
Then data's information is maintained and reused anywhere.
Signed-off-by: Jaehoon Chung
Tested-by: Lukasz Majewski
Acked-by: Lukasz Majewski
---
drivers/mmc/exynos_dw_mmc.c | 205 ---
include/dwmmc.h |2 +
2 files changed, 135 insertions(+), 72 deletions(-)
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index de8cdcc..99047a7 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -13,6 +13,8 @@
#include
#include
#include
+#include
+#include
#defineDWMMC_MAX_CH_NUM4
#defineDWMMC_MAX_FREQ 5200
@@ -44,6 +46,13 @@ unsigned int exynos_dwmci_get_clk(struct dwmci_host *host)
& DWMCI_DIVRATIO_MASK) + 1;
sclk = get_mmc_clk(host->dev_index);
+ /*
+* Assume to know divider value.
+* When clock unit is broken, need to set "host->div"
+*/
+ if (host->div)
+ sclk /= (host->div + 1);
+
return sclk / clk_div;
}
@@ -60,45 +69,32 @@ static void exynos_dwmci_board_init(struct dwmci_host *host)
}
}
-/*
- * This function adds the mmc channel to be registered with mmc core.
- * index - mmc channel number.
- * regbase - register base address of mmc channel specified in 'index'.
- * bus_width - operating bus width of mmc channel specified in 'index'.
- * clksel -value to be written into CLKSEL register in case of FDT.
- * NULL in case od non-FDT.
- */
-int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
+static int exynos_dwmci_core_init(struct dwmci_host *host, int index)
{
- struct dwmci_host *host = NULL;
unsigned int div;
unsigned long freq, sclk;
- host = malloc(sizeof(struct dwmci_host));
- if (!host) {
- printf("dwmci_host malloc fail!\n");
- return 1;
- }
+
+ if (host->bus_hz)
+ freq = host->bus_hz;
+ else
+ freq = DWMMC_MAX_FREQ;
+
/* request mmc clock vlaue of 52MHz. */
- freq = 5200;
sclk = get_mmc_clk(index);
div = DIV_ROUND_UP(sclk, freq);
/* set the clock divisor for mmc */
set_mmc_clk(index, div);
host->name = "EXYNOS DWMMC";
- host->ioaddr = (void *)regbase;
- host->buswidth = bus_width;
#ifdef CONFIG_EXYNOS5420
host->quirks = DWMCI_QUIRK_DISABLE_SMU;
#endif
host->board_init = exynos_dwmci_board_init;
- if (clksel) {
- host->clksel_val = clksel;
- } else {
- if (0 == index)
+ if (!host->clksel_val) {
+ if (index == 0)
host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;
- if (2 == index)
+ if (index == 2)
host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;
}
@@ -113,69 +109,134 @@ int exynos_dwmci_add_port(int index, u32 regbase, int
bus_width, u32 clksel)
return 0;
}
+/*
+ * This function adds the mmc channel to be registered with mmc core.
+ * index - mmc channel number.
+ * regbase - register base address of mmc channel specified in 'index'.
+ * bus_width - operating bus width of mmc channel specified in 'index'.
+ * clksel -value to be written into CLKSEL register in case of FDT.
+ * NULL in case od non-FDT.
+ */
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
+{
+ struct dwmci_host *host = NULL;
+
+ host = malloc(sizeof(struct dwmci_host));
+ if (!host) {
+ error("dwmci_host malloc fail!\n");
+ return -ENOMEM;
+ }
+
+ host->ioaddr = (void *)regbase;
+ host->buswidth = bus_width;
+
+ if (clksel)
+ host->clksel_val = clksel;
+
+ return exynos_dwmci_core_init(host, index);
+}
+
#ifdef CONFIG_OF_CONTROL
-int exynos_dwmmc_init(const void *blob)
+struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM];
+
+static int do_dwmci_init(struct dwmci_host *host)
{
- int index, bus_width;
- int node_list[DWMMC_MAX_CH_NUM];
- int err = 0, dev_id, flag, count, i;
- u32 clksel_val, base, timing[3];
+ int index, flag = 0, err = 0;
- count = fdtdec_find_aliases_for_id(blob, "mmc",
- COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,
- DWMMC_MAX_CH_NUM);
+ index = host->dev_index;
- for (i = 0; i < count; i++) {
- int node = node_list[i];
+ flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
+ err = exynos_pinmux_config(host->dev_id, flag);
+ if (err) {
+ debug("DWMMC not configure\n");
+ return err;
+ }
- if (node <= 0)
- continue;
+ return exynos_dwmci_core_ini
[U-Boot] [RESEND PATCHv4 10/14] mmc: dw_mmc: support the DDR mode
Support the DDR mode at dw-mmc controller
Signed-off-by: Jaehoon Chung
Tested-by: Lukasz Majewski
Acked-by: Lukasz Majewski
---
drivers/mmc/dw_mmc.c | 12 ++--
include/dwmmc.h |3 +++
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index eb4e2be..5bf36a0 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -284,8 +284,8 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32
freq)
static void dwmci_set_ios(struct mmc *mmc)
{
- struct dwmci_host *host = mmc->priv;
- u32 ctype;
+ struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
+ u32 ctype, regs;
debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock);
@@ -304,6 +304,14 @@ static void dwmci_set_ios(struct mmc *mmc)
dwmci_writel(host, DWMCI_CTYPE, ctype);
+ regs = dwmci_readl(host, DWMCI_UHS_REG);
+ if (mmc->card_caps & MMC_MODE_DDR_52MHz)
+ regs |= DWMCI_DDR_MODE;
+ else
+ regs &= DWMCI_DDR_MODE;
+
+ dwmci_writel(host, DWMCI_UHS_REG, regs);
+
if (host->clksel)
host->clksel(host);
}
diff --git a/include/dwmmc.h b/include/dwmmc.h
index 14c7db8..b67f11b 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -123,6 +123,9 @@
#define DWMCI_BMOD_IDMAC_FB(1 << 1)
#define DWMCI_BMOD_IDMAC_EN(1 << 7)
+/* UHS register */
+#define DWMCI_DDR_MODE (1 << 16)
+
/* quirks */
#define DWMCI_QUIRK_DISABLE_SMU(1 << 0)
--
1.7.9.5
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[U-Boot] [RESEND PATCHv4 05/14] ARM: exynos: clock: modify the set_mmc_clk for exynos4
Modified the mmc_set_clock for eynos4.
The goal of this patch is that fsys-div register should be reset.
And retore the div-value, not using the value of lowlevel_init.
(For using SDMMC4, this patch is needs)
Signed-off-by: Jaehoon Chung
Tested-by: Lukasz Majewski
Acked-by: Lukasz Majewski
---
arch/arm/cpu/armv7/exynos/clock.c | 16 +++-
arch/arm/include/asm/arch-exynos/clk.h |5 +
2 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 2c2029a..400d134 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -869,7 +869,7 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int
div)
{
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
- unsigned int addr;
+ unsigned int addr, clear_bit, set_bit;
/*
* CLK_DIV_FSYS1
@@ -877,20 +877,26 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned
int div)
* CLK_DIV_FSYS2
* MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
* CLK_DIV_FSYS3
-* MMC4_PRE_RATIO [15:8]
+* MMC4_RATIO [3:0]
*/
if (dev_index < 2) {
addr = (unsigned int)&clk->div_fsys1;
- } else if (dev_index == 4) {
+ clear_bit = MASK_PRE_RATIO(dev_index);
+ set_bit = SET_PRE_RATIO(dev_index, div);
+ } else if (dev_index == 4) {
addr = (unsigned int)&clk->div_fsys3;
dev_index -= 4;
+ /* MMC4 is controlled with the MMC4_RATIO value */
+ clear_bit = MASK_RATIO(dev_index);
+ set_bit = SET_RATIO(dev_index, div);
} else {
addr = (unsigned int)&clk->div_fsys2;
dev_index -= 2;
+ clear_bit = MASK_PRE_RATIO(dev_index);
+ set_bit = SET_PRE_RATIO(dev_index, div);
}
- clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
- (div & 0xff) << ((dev_index << 4) + 8));
+ clrsetbits_le32(addr, clear_bit, set_bit);
}
/* exynos5: set the mmc clock */
diff --git a/arch/arm/include/asm/arch-exynos/clk.h
b/arch/arm/include/asm/arch-exynos/clk.h
index cdeef32..ffbc07e 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -16,6 +16,11 @@
#define BPLL 5
#define RPLL 6
+#define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8))
+#define MASK_RATIO(x) (0xf << (x << 4))
+#define SET_PRE_RATIO(x, y)((y & 0xff) << ((x << 4) + 8))
+#define SET_RATIO(x, y)((y & 0xf) << (x << 4))
+
enum pll_src_bit {
EXYNOS_SRC_MPLL = 6,
EXYNOS_SRC_EPLL,
--
1.7.9.5
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[U-Boot] [RESEND PATCHv4 12/14] mmc: exynos_dw_mmc: enable the DDR mode
Set the ddr mode capability by default. Signed-off-by: Jaehoon Chung Tested-by: Lukasz Majewski Acked-by: Lukasz Majewski --- drivers/mmc/exynos_dw_mmc.c |1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index 99047a7..4b8d23b 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -98,6 +98,7 @@ static int exynos_dwmci_core_init(struct dwmci_host *host, int index) host->clksel_val = DWMMC_MMC2_CLKSEL_VAL; } + host->caps = MMC_MODE_DDR_52MHz; host->clksel = exynos_dwmci_clksel; host->dev_index = index; host->get_mmc_clk = exynos_dwmci_get_clk; -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RESEND PATCHv4 02/14] arm: exynos: clock: Remove exynos4x12_set_mmc_clk function
From: Beomho Seo
exynos4x12_set_mmc_clk function have been removed.
Because, exynos4x12_clock and exynos4_clock return same div_fsys* value.
Signed-off-by: Beomho Seo
Signed-off-by: Jaehoon Chung
Tested-by: Piotr Wilczek
Cc: Lukasz Majewski
Cc: Piotr Wilczek
Cc: Minkyu Kang
---
arch/arm/cpu/armv7/exynos/clock.c | 29 +
1 file changed, 1 insertion(+), 28 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 1fea4d6..2c2029a 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -893,30 +893,6 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned
int div)
(div & 0xff) << ((dev_index << 4) + 8));
}
-/* exynos4x12: set the mmc clock */
-static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
-{
- struct exynos4x12_clock *clk =
- (struct exynos4x12_clock *)samsung_get_base_clock();
- unsigned int addr;
-
- /*
-* CLK_DIV_FSYS1
-* MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
-* CLK_DIV_FSYS2
-* MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
-*/
- if (dev_index < 2) {
- addr = (unsigned int)&clk->div_fsys1;
- } else {
- addr = (unsigned int)&clk->div_fsys2;
- dev_index -= 2;
- }
-
- clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
- (div & 0xff) << ((dev_index << 4) + 8));
-}
-
/* exynos5: set the mmc clock */
static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
{
@@ -1612,10 +1588,7 @@ void set_mmc_clk(int dev_index, unsigned int div)
else
exynos5_set_mmc_clk(dev_index, div);
} else {
- if (proid_is_exynos4412())
- exynos4x12_set_mmc_clk(dev_index, div);
- else
- exynos4_set_mmc_clk(dev_index, div);
+ exynos4_set_mmc_clk(dev_index, div);
}
}
--
1.7.9.5
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[U-Boot] [RESEND PATCHv4 01/14] arm: exynos: pinmux: add sdmmc4 gpio configratuion
From: Beomho Seo
For use dwmmc controller at exynos4, add SDMMC4 gpio configuration.
Signed-off-by: Beomho Seo
Signed-off-by: Jaehoon Chung
Tested-by: Piotr Wilczek
Cc: Lukasz Majewski
Cc: Piotr Wilczek
Cc: Minkyu Kang
---
arch/arm/cpu/armv7/exynos/pinmux.c | 35 +--
1 file changed, 29 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
b/arch/arm/cpu/armv7/exynos/pinmux.c
index ee7c2e5..86a0c75 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -573,15 +573,26 @@ static void exynos4_i2c_config(int peripheral, int flags)
static int exynos4_mmc_config(int peripheral, int flags)
{
int i, start = 0, start_ext = 0;
+ unsigned int func, ext_func;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
start = EXYNOS4_GPIO_K00;
start_ext = EXYNOS4_GPIO_K13;
+ func = S5P_GPIO_FUNC(0x2);
+ ext_func = S5P_GPIO_FUNC(0x3);
break;
case PERIPH_ID_SDMMC2:
start = EXYNOS4_GPIO_K20;
start_ext = EXYNOS4_GPIO_K33;
+ func = S5P_GPIO_FUNC(0x2);
+ ext_func = S5P_GPIO_FUNC(0x3);
+ break;
+ case PERIPH_ID_SDMMC4:
+ start = EXYNOS4_GPIO_K00;
+ start_ext = EXYNOS4_GPIO_K13;
+ func = S5P_GPIO_FUNC(0x3);
+ ext_func = S5P_GPIO_FUNC(0x4);
break;
default:
return -1;
@@ -589,13 +600,14 @@ static int exynos4_mmc_config(int peripheral, int flags)
for (i = start; i < (start + 7); i++) {
if (i == (start + 2))
continue;
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(i, func);
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
+ /* SDMMC2 do not use 8bit mode at exynos4 */
if (flags & PINMUX_FLAG_8BIT_MODE) {
for (i = start_ext; i < (start_ext + 4); i++) {
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(i, ext_func);
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
@@ -676,15 +688,26 @@ static void exynos4x12_i2c_config(int peripheral, int
flags)
static int exynos4x12_mmc_config(int peripheral, int flags)
{
int i, start = 0, start_ext = 0;
+ unsigned int func, ext_func;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
start = EXYNOS4X12_GPIO_K00;
start_ext = EXYNOS4X12_GPIO_K13;
+ func = S5P_GPIO_FUNC(0x2);
+ ext_func = S5P_GPIO_FUNC(0x3);
break;
case PERIPH_ID_SDMMC2:
start = EXYNOS4X12_GPIO_K20;
start_ext = EXYNOS4X12_GPIO_K33;
+ func = S5P_GPIO_FUNC(0x2);
+ ext_func = S5P_GPIO_FUNC(0x3);
+ break;
+ case PERIPH_ID_SDMMC4:
+ start = EXYNOS4_GPIO_K00;
+ start_ext = EXYNOS4_GPIO_K13;
+ func = S5P_GPIO_FUNC(0x3);
+ ext_func = S5P_GPIO_FUNC(0x4);
break;
default:
return -1;
@@ -692,13 +715,13 @@ static int exynos4x12_mmc_config(int peripheral, int
flags)
for (i = start; i < (start + 7); i++) {
if (i == (start + 2))
continue;
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(i, func);
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
if (flags & PINMUX_FLAG_8BIT_MODE) {
for (i = start_ext; i < (start_ext + 4); i++) {
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(i, ext_func);
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
@@ -759,10 +782,10 @@ static int exynos4_pinmux_config(int peripheral, int
flags)
break;
case PERIPH_ID_SDMMC0:
case PERIPH_ID_SDMMC2:
+ case PERIPH_ID_SDMMC4:
return exynos4_mmc_config(peripheral, flags);
case PERIPH_ID_SDMMC1:
case PERIPH_ID_SDMMC3:
- case PERIPH_ID_SDMMC4:
debug("SDMMC device %d not implemented\n", peripheral);
return -1;
default:
@@ -794,10 +817,10 @@ static int exynos4x12_pinmux_config(int peripheral, int
flags)
break;
case PERIPH_ID_SDMMC0:
case PERIPH_ID_SDMMC2:
+ case PERIPH_ID_SDMMC4:
return exynos4x12_mmc_config(peripheral, flags);
case PERIPH_ID_SDMMC1:
case PERIPH_ID_SDMMC3:
- case PERIPH_ID_SDMMC4:
[U-Boot] [RESEND PATCHv4 09/14] mmc: support the DDR mode for eMMC
Signed-off-by: Jaehoon Chung
Tested-by: Lukasz Majewski
Acked-by: Lukasz Majewski
---
drivers/mmc/mmc.c | 16 +---
include/mmc.h |7 +++
2 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index dd6a6ef..08187d5 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -158,6 +158,9 @@ int mmc_set_blocklen(struct mmc *mmc, int len)
{
struct mmc_cmd cmd;
+ if (mmc->card_caps & MMC_MODE_DDR_52MHz)
+ return 0;
+
cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = len;
@@ -514,10 +517,13 @@ static int mmc_change_freq(struct mmc *mmc)
return 0;
/* High Speed is set, there are two types: 52MHz and 26MHz */
- if (cardtype & EXT_CSD_CARD_TYPE_52)
+ if (cardtype & EXT_CSD_CARD_TYPE_52) {
+ if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
+ mmc->card_caps |= MMC_MODE_DDR_52MHz;
mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
- else
+ } else {
mmc->card_caps |= MMC_MODE_HS;
+ }
return 0;
}
@@ -1054,6 +1060,8 @@ static int mmc_startup(struct mmc *mmc)
/* An array of possible bus widths in order of preference */
static unsigned ext_csd_bits[] = {
+ EXT_CSD_DDR_BUS_WIDTH_8,
+ EXT_CSD_DDR_BUS_WIDTH_4,
EXT_CSD_BUS_WIDTH_8,
EXT_CSD_BUS_WIDTH_4,
EXT_CSD_BUS_WIDTH_1,
@@ -1061,13 +1069,15 @@ static int mmc_startup(struct mmc *mmc)
/* An array to map CSD bus widths to host cap bits */
static unsigned ext_to_hostcaps[] = {
+ [EXT_CSD_DDR_BUS_WIDTH_4] = MMC_MODE_DDR_52MHz,
+ [EXT_CSD_DDR_BUS_WIDTH_8] = MMC_MODE_DDR_52MHz,
[EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
[EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
};
/* An array to map chosen bus width to an integer */
static unsigned widths[] = {
- 8, 4, 1,
+ 8, 4, 8, 4, 1,
};
for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
diff --git a/include/mmc.h b/include/mmc.h
index da9f812..40efb56 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -37,6 +37,7 @@
#define MMC_MODE_8BIT (1 << 3)
#define MMC_MODE_SPI (1 << 4)
#define MMC_MODE_HC(1 << 5)
+#define MMC_MODE_DDR_52MHz (1 << 6)
#define SD_DATA_4BIT 0x0004
@@ -168,10 +169,16 @@
#define EXT_CSD_CARD_TYPE_26 (1 << 0)/* Card can run at 26MHz */
#define EXT_CSD_CARD_TYPE_52 (1 << 1)/* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
+#define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
+#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
+ | EXT_CSD_CARD_TYPE_DDR_1_2V)
#define EXT_CSD_BUS_WIDTH_10 /* Card is in 1 bit mode */
#define EXT_CSD_BUS_WIDTH_41 /* Card is in 4 bit mode */
#define EXT_CSD_BUS_WIDTH_82 /* Card is in 8 bit mode */
+#define EXT_CSD_DDR_BUS_WIDTH_45 /* Card is in 4 bit DDR mode */
+#define EXT_CSD_DDR_BUS_WIDTH_86 /* Card is in 8 bit DDR mode */
#define EXT_CSD_BOOT_ACK_ENABLE(1 << 6)
#define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
--
1.7.9.5
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[U-Boot] [RESEND PATCHv4 03/14] board: trats2: Enable device tree on Trats2
From: Beomho Seo
This patch add dwmmc emmc controller node on exynos4 and exynos4412 device tree.
Signed-off-by: Beomho Seo
Signed-off-by: Jaehoon Chung
Tested-by: Piotr Wilczek
Cc: Lukasz Majewski
Cc: Piotr Wilczek
Cc: Minkyu Kang
---
arch/arm/dts/exynos4.dtsi |8
arch/arm/dts/exynos4412-trats2.dts |8
2 files changed, 16 insertions(+)
diff --git a/arch/arm/dts/exynos4.dtsi b/arch/arm/dts/exynos4.dtsi
index 71dc7eb..110eb43 100644
--- a/arch/arm/dts/exynos4.dtsi
+++ b/arch/arm/dts/exynos4.dtsi
@@ -128,6 +128,14 @@
interrupts = <0 78 0>;
};
+ dwmmc@1255 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos-dwmmc";
+ reg = <0x1255 0x1000>;
+ interrupts = <0 131 0>;
+ };
+
gpio: gpio {
gpio-controller;
#gpio-cells = <2>;
diff --git a/arch/arm/dts/exynos4412-trats2.dts
b/arch/arm/dts/exynos4412-trats2.dts
index 1596f83..5269ae6 100644
--- a/arch/arm/dts/exynos4412-trats2.dts
+++ b/arch/arm/dts/exynos4412-trats2.dts
@@ -31,6 +31,7 @@
console = "/serial@1382";
mmc0 = "sdhci@1251";
mmc2 = "sdhci@1253";
+ mmc4 = "dwmmc@1255";
};
i2c@138d {
@@ -431,4 +432,11 @@
sdhci@1254 {
status = "disabled";
};
+
+ dwmmc@1255 {
+ samsung,bus-width = <8>;
+ samsung,timing = <0 1 0>;
+ pwr-gpios = <&gpio 0xB2 0>;
+ index = <4>;
+ };
};
--
1.7.9.5
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[U-Boot] [RESEND PATCHv4 11/14] ARM: dts: exnyos: enable dw-mmc controller
Enabled the dw-mmc controller.
Signed-off-by: Jaehoon Chung
Tested-by: Lukasz Majewski
Acked-by: Lukasz Majewski
---
arch/arm/dts/exynos4412-trats2.dts |6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/exynos4412-trats2.dts
b/arch/arm/dts/exynos4412-trats2.dts
index 5269ae6..cc58c87 100644
--- a/arch/arm/dts/exynos4412-trats2.dts
+++ b/arch/arm/dts/exynos4412-trats2.dts
@@ -417,6 +417,7 @@
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
pwr-gpios = <&gpio 0xB2 0>;
+ status = "disabled";
};
sdhci@1252 {
@@ -435,8 +436,11 @@
dwmmc@1255 {
samsung,bus-width = <8>;
- samsung,timing = <0 1 0>;
+ samsung,timing = <2 1 0>;
pwr-gpios = <&gpio 0xB2 0>;
+ fifoth_val = <0x203f0040>;
+ bus_hz = <4>;
+ div = <0x3>;
index = <4>;
};
};
--
1.7.9.5
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Re: [U-Boot] [PATCHv4 00/13] mmc: exynos: code cleanup and support DDR mode
Discard this patch-set. I missed the some patch..resend the patch. Sorry! Best Regards, Jaehoon Chung On 05/15/2014 05:49 PM, Jaehoon Chung wrote: > If card and host are supported DDR mode, then it can be used the DDR mode. > This patch-set has dependency about beomho's patch-set. > (Based-on u-boot-samsung repository) > > It's result for loading image. > > sdhci controller ->5260488 bytes read in 259 ms (19.4 MiB/s) > dwmmc controller without DDR mode -> 5260488 bytes read in 202 ms (24.8 MiB/s) > dwmmc controller with DDR mode -> 5260488 bytes read in 118 ms (42.5 MiB/s) > > Download the 400M image with lthor. > sdhci controller -> 59.4sec (Avg 6.95 MB/s) > dwmmc controller without DDR mode -> 61.6sec (Avg 6.72MB/s) > dwmmc controller with DDR mode -> 60.4sec (Avg 6.85MB/s) > > Beomho Seo (2): > arm: exynos: clock: Remove exynos4x12_set_mmc_clk function > board: trats2: Enable device tree on Trats2 > > Jaehoon Chung (11): > ARM: exynos: board: change the mmc/sd init sequence > ARM: exynos: clock: modify the set_mmc_clk for exynos4 > ARM: dts: exynos: rename from EXYNOS5_DWMMC to EXYNOS_DWMMC > mmc: exynos_dw_mmc: restore the property into host > mmc: remove the unnecessary define and fix the wrong bit control > mmc: support the DDR mode for eMMC > mmc: dw_mmc: support the DDR mode > ARM: dts: exnyos: enable dw-mmc controller > mmc: exynos_dw_mmc: enable the DDR mode > ARM: exynos4: enable the dwmmc configuration > mmc: s5p_sdhci: add the s5p_sdhci_core_init function > > arch/arm/cpu/armv7/exynos/clock.c | 45 ++- > arch/arm/dts/exynos4.dtsi |8 ++ > arch/arm/dts/exynos4412-trats2.dts| 12 ++ > arch/arm/dts/exynos5.dtsi |8 +- > arch/arm/include/asm/arch-exynos/clk.h|5 + > board/samsung/common/board.c | 13 +- > doc/device-tree-bindings/exynos/dwmmc.txt |8 +- > drivers/mmc/dw_mmc.c | 12 +- > drivers/mmc/exynos_dw_mmc.c | 206 > +++-- > drivers/mmc/mmc.c | 16 ++- > drivers/mmc/s5p_sdhci.c | 42 +++--- > include/configs/exynos4-dt.h |3 + > include/dwmmc.h |5 + > include/fdtdec.h |2 +- > include/mmc.h | 25 ++-- > lib/fdtdec.c |2 +- > 16 files changed, 248 insertions(+), 164 deletions(-) > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/4] bootm: make use of legacy image format configurable
On 05/15/2014 07:47 AM, Heiko Schocher wrote: > Hello Michal, > > Am 14.05.2014 13:16, schrieb Michal Simek: >> On 05/14/2014 12:54 PM, Heiko Schocher wrote: >>> make the use of legacy image format configurable through >>> the config define CONFIG_IMAGE_FORMAT_LEGACY. >>> >>> When relying on signed FIT images with required signature check >>> the legacy image format should be disabled. Therefore introduce >>> this new define and enable legacy image format if CONFIG_FIT_SIGNATURE >>> is not set. If CONFIG_FIT_SIGNATURE is set disable per default >>> the legacy image format. >>> >>> Signed-off-by: Heiko Schocher >>> Cc: Simon Glass >>> Cc: Lars Steubesand >>> Cc: Mike Pearce >>> Cc: Wolfgang Denk >>> Cc: Tom Rini >>> Cc: Michal Simek >>> Cc: Michael Conrad >>> >>> --- >>> - changes for v2: >>>- make the legacy image format configurable through >>> the define CONFIG_IMAGE_FORMAT_LEGACY. >>> >>> Default: >>> if not CONFIG_FIT_SIGNATURE is defined it is enabled, >>> else disabled. >>> >>> Disable it with CONFIG_DISABLE_IMAGE_LEGACY if >>> CONFIG_FIT_SIGNATURE is not defined. >> >> Just a note that ifdef CONFIG_IMAGE_FORMAT_LEGACY >> should be also used in SPL code. > > I think thats the case, as I did the default settings in > include/config_defaults.h and a MAKEALL for arm and powerpc > dropped no compiler errors/warnings. > > This is just a first step to deactivate legacy image format. > A complete remove patch of it needs more work/time ... SPL is using just legacy image format. > >> But that means that FIT image with signature feature >> should be enabled for SPL. > > Why? I described this differently than I wanted. Enable FIT for SPL as one step and enabling FIT with signature is optional. >> If possible please also enable CONFIG_IMAGE_FORMAT_LEGACY >> for zynq because we are using legacy formats too. > > You mean in "include/configs/zynq-common.h" ? > Prepared this for v3, but I could not test it... Yes. I will test it that's not a problem. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCHv4 07/13] mmc: remove the unnecessary define and fix the wrong bit control
Signed-off-by: Jaehoon Chung Reviewed-by: Lukasz Majeski Tested-by: Lukasz Majewski Acked-by: Lukasz Majewski --- drivers/mmc/mmc.c |2 +- include/mmc.h | 18 ++ 2 files changed, 7 insertions(+), 13 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 16051e5..dd6a6ef 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -514,7 +514,7 @@ static int mmc_change_freq(struct mmc *mmc) return 0; /* High Speed is set, there are two types: 52MHz and 26MHz */ - if (cardtype & MMC_HS_52MHZ) + if (cardtype & EXT_CSD_CARD_TYPE_52) mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; else mmc->card_caps |= MMC_MODE_HS; diff --git a/include/mmc.h b/include/mmc.h index 42d0125..da9f812 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -31,15 +31,12 @@ #define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x429) #define MMC_VERSION_4_5(MMC_VERSION_MMC | 0x405) -#define MMC_MODE_HS0x001 -#define MMC_MODE_HS_52MHz 0x010 -#define MMC_MODE_4BIT 0x100 -#define MMC_MODE_8BIT 0x200 -#define MMC_MODE_SPI 0x400 -#define MMC_MODE_HC0x800 - -#define MMC_MODE_MASK_WIDTH_BITS (MMC_MODE_4BIT | MMC_MODE_8BIT) -#define MMC_MODE_WIDTH_BITS_SHIFT 8 +#define MMC_MODE_HS(1 << 0) +#define MMC_MODE_HS_52MHz (1 << 1) +#define MMC_MODE_4BIT (1 << 2) +#define MMC_MODE_8BIT (1 << 3) +#define MMC_MODE_SPI (1 << 4) +#define MMC_MODE_HC(1 << 5) #define SD_DATA_4BIT 0x0004 @@ -97,9 +94,6 @@ #define SD_HIGHSPEED_BUSY 0x0002 #define SD_HIGHSPEED_SUPPORTED 0x0002 -#define MMC_HS_TIMING 0x0100 -#define MMC_HS_52MHZ 0x2 - #define OCR_BUSY 0x8000 #define OCR_HCS0x4000 #define OCR_VOLTAGE_MASK 0x007FFF80 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCHv4 11/13] mmc: exynos_dw_mmc: enable the DDR mode
Set the ddr mode capability by default. Signed-off-by: Jaehoon Chung Tested-by: Lukasz Majewski Acked-by: Lukasz Majewski --- drivers/mmc/exynos_dw_mmc.c |1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index 99047a7..4b8d23b 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -98,6 +98,7 @@ static int exynos_dwmci_core_init(struct dwmci_host *host, int index) host->clksel_val = DWMMC_MMC2_CLKSEL_VAL; } + host->caps = MMC_MODE_DDR_52MHz; host->clksel = exynos_dwmci_clksel; host->dev_index = index; host->get_mmc_clk = exynos_dwmci_get_clk; -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCHv4 08/13] mmc: support the DDR mode for eMMC
Signed-off-by: Jaehoon Chung
Tested-by: Lukasz Majewski
Acked-by: Lukasz Majewski
---
drivers/mmc/mmc.c | 16 +---
include/mmc.h |7 +++
2 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index dd6a6ef..08187d5 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -158,6 +158,9 @@ int mmc_set_blocklen(struct mmc *mmc, int len)
{
struct mmc_cmd cmd;
+ if (mmc->card_caps & MMC_MODE_DDR_52MHz)
+ return 0;
+
cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = len;
@@ -514,10 +517,13 @@ static int mmc_change_freq(struct mmc *mmc)
return 0;
/* High Speed is set, there are two types: 52MHz and 26MHz */
- if (cardtype & EXT_CSD_CARD_TYPE_52)
+ if (cardtype & EXT_CSD_CARD_TYPE_52) {
+ if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
+ mmc->card_caps |= MMC_MODE_DDR_52MHz;
mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
- else
+ } else {
mmc->card_caps |= MMC_MODE_HS;
+ }
return 0;
}
@@ -1054,6 +1060,8 @@ static int mmc_startup(struct mmc *mmc)
/* An array of possible bus widths in order of preference */
static unsigned ext_csd_bits[] = {
+ EXT_CSD_DDR_BUS_WIDTH_8,
+ EXT_CSD_DDR_BUS_WIDTH_4,
EXT_CSD_BUS_WIDTH_8,
EXT_CSD_BUS_WIDTH_4,
EXT_CSD_BUS_WIDTH_1,
@@ -1061,13 +1069,15 @@ static int mmc_startup(struct mmc *mmc)
/* An array to map CSD bus widths to host cap bits */
static unsigned ext_to_hostcaps[] = {
+ [EXT_CSD_DDR_BUS_WIDTH_4] = MMC_MODE_DDR_52MHz,
+ [EXT_CSD_DDR_BUS_WIDTH_8] = MMC_MODE_DDR_52MHz,
[EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
[EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
};
/* An array to map chosen bus width to an integer */
static unsigned widths[] = {
- 8, 4, 1,
+ 8, 4, 8, 4, 1,
};
for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
diff --git a/include/mmc.h b/include/mmc.h
index da9f812..40efb56 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -37,6 +37,7 @@
#define MMC_MODE_8BIT (1 << 3)
#define MMC_MODE_SPI (1 << 4)
#define MMC_MODE_HC(1 << 5)
+#define MMC_MODE_DDR_52MHz (1 << 6)
#define SD_DATA_4BIT 0x0004
@@ -168,10 +169,16 @@
#define EXT_CSD_CARD_TYPE_26 (1 << 0)/* Card can run at 26MHz */
#define EXT_CSD_CARD_TYPE_52 (1 << 1)/* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
+#define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
+#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
+ | EXT_CSD_CARD_TYPE_DDR_1_2V)
#define EXT_CSD_BUS_WIDTH_10 /* Card is in 1 bit mode */
#define EXT_CSD_BUS_WIDTH_41 /* Card is in 4 bit mode */
#define EXT_CSD_BUS_WIDTH_82 /* Card is in 8 bit mode */
+#define EXT_CSD_DDR_BUS_WIDTH_45 /* Card is in 4 bit DDR mode */
+#define EXT_CSD_DDR_BUS_WIDTH_86 /* Card is in 8 bit DDR mode */
#define EXT_CSD_BOOT_ACK_ENABLE(1 << 6)
#define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
--
1.7.9.5
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[U-Boot] [PATCHv4 12/13] ARM: exynos4: enable the dwmmc configuration
Signed-off-by: Jaehoon Chung Tested-by: Lukasz Majewski Acked-by: Lukasz Majewski --- include/configs/exynos4-dt.h |3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/exynos4-dt.h b/include/configs/exynos4-dt.h index 2040bf7..7710bae 100644 --- a/include/configs/exynos4-dt.h +++ b/include/configs/exynos4-dt.h @@ -44,6 +44,9 @@ #define CONFIG_S5P_SDHCI #define CONFIG_SDHCI #define CONFIG_MMC_SDMA +#define CONFIG_DWMMC +#define CONFIG_EXYNOS_DWMMC +#define CONFIG_BOUNCE_BUFFER #define CONFIG_MMC_DEFAULT_DEV 0 /* PWM */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCHv4 09/13] mmc: dw_mmc: support the DDR mode
Support the DDR mode at dw-mmc controller
Signed-off-by: Jaehoon Chung
Tested-by: Lukasz Majewski
Acked-by: Lukasz Majewski
---
drivers/mmc/dw_mmc.c | 12 ++--
include/dwmmc.h |3 +++
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index eb4e2be..5bf36a0 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -284,8 +284,8 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32
freq)
static void dwmci_set_ios(struct mmc *mmc)
{
- struct dwmci_host *host = mmc->priv;
- u32 ctype;
+ struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
+ u32 ctype, regs;
debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock);
@@ -304,6 +304,14 @@ static void dwmci_set_ios(struct mmc *mmc)
dwmci_writel(host, DWMCI_CTYPE, ctype);
+ regs = dwmci_readl(host, DWMCI_UHS_REG);
+ if (mmc->card_caps & MMC_MODE_DDR_52MHz)
+ regs |= DWMCI_DDR_MODE;
+ else
+ regs &= DWMCI_DDR_MODE;
+
+ dwmci_writel(host, DWMCI_UHS_REG, regs);
+
if (host->clksel)
host->clksel(host);
}
diff --git a/include/dwmmc.h b/include/dwmmc.h
index 14c7db8..b67f11b 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -123,6 +123,9 @@
#define DWMCI_BMOD_IDMAC_FB(1 << 1)
#define DWMCI_BMOD_IDMAC_EN(1 << 7)
+/* UHS register */
+#define DWMCI_DDR_MODE (1 << 16)
+
/* quirks */
#define DWMCI_QUIRK_DISABLE_SMU(1 << 0)
--
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