Re: [U-Boot] Please pull u-boot-sunxi.git/next

[Ian Campbell]

On Tue, 2014-07-08 at 23:30 +0200, Jeroen Hofstee wrote:
 On 08-07-14 21:20, Ian Campbell wrote:
  Hi Tom
 
  Sending to you for #next in Albert's absence.
 
  The following changes since commit 23f23f23d509e8e873797884456070c8a47d72b2:
 
 socfpga: Relocate arch common functions away from board (2014-07-05 
  10:14:46 +0200)
 
  are available in the git repository at:
 
 git://git.denx.de/u-boot-sunxi.git next
 
  for you to fetch changes up to 799aff38dfc1b2d860ec8430572f9402d3ce9881:
 
 sunxi: Avoid unused variable warning. (2014-07-08 07:45:06 +0100)
 
 
 I am a bit lost here, why do want to send next branches for
 pull requests??

I discussed this with Albert on IRC and he said:

aaribaud: ijc: Re: next branches, you could push to next and
send a PR for my next indeed.

Ian.

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Re: [U-Boot] [Question] Any plan to refactor Generic Board Framework?

[Masahiro Yamada]

Hi Simon,

On Mon, 7 Jul 2014 20:51:00 +1000
Simon Glass s...@chromium.org wrote:


 
  Is there any plan to fix them? When? By whom?
 
  (They include some old platform macros such as CONFIG_8xx.
  Is it worth refactoring? If so, who will do it? )
 
 
 
  Besides, there are many 'TODO' marks.
  But it seems nothing has happened so far...
 
 
  Now generic board is suppored in ARM, PPC, MIPS, Sandbox, ARC, x86.
 
  Accoding to doc/README.generic-board,
  we are expecting the other architectures will support it before October.
  I think we should start to do something now.
 
  If we keep going without any clean-up, I guess it will be messed up.
 
 The code is trying to duplicate the old board init without
 changing/breaking anything. So the #ifdefs are trying to duplicate
 those in the old board init code.

Thanks. I was missing this.
This verbatim dupulication makes it easy to switch to generic board,
in most cases, just by adding CONFIG_SYS_GENERIC_BOARD
although run-test is strongly recommended.

Then, we can clean-up code after removing arch/*/lib/board.c
(Maybe next year?)



Best Regards
Masahiro Yamada

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[U-Boot] [PATCH 2/2] i2c: ST33ZP24 I2C TPM driver

[Jean-Luc BLANC]

This driver add support for STMicroelectronics ST33ZP24 I2C TPM.
---
 README |6 +
 drivers/tpm/Makefile   |1 +
 drivers/tpm/tpm_i2c_stm_st33.c |  633 
 3 files changed, 640 insertions(+)
 create mode 100644 drivers/tpm/tpm_i2c_stm_st33.c

diff --git a/README b/README
index a4aa28a..c4463d8 100644
--- a/README
+++ b/README
@@ -1426,6 +1426,12 @@ The following options need to be configured:
TPM1_SPI_CS
Define SPI Chip Select ID connected to TPM
 
+   CONFIG_TPM_ST_I2C
+   Support I2C STMicroelectronics TPM. Require I2C support
+
+   CONFIG_TPM_I2C_BUS
+   Define the i2c bus number for the TPM device
+
 - USB Support:
At the moment only the UHCI host controller is
supported (PIP405, MIP405, MPC5200); define
diff --git a/drivers/tpm/Makefile b/drivers/tpm/Makefile
index 1ee707e..29e1f80 100644
--- a/drivers/tpm/Makefile
+++ b/drivers/tpm/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_TPM_TIS_I2C) += tpm_tis_i2c.o
 obj-$(CONFIG_TPM_TIS_LPC) += tpm_tis_lpc.o
 obj-$(CONFIG_TPM_TIS_SANDBOX) += tpm_tis_sandbox.o
 obj-$(CONFIG_TPM_ST_SPI) += tpm_spi_stm_st33.o
+obj-$(CONFIG_TPM_ST_I2C) += tpm_i2c_stm_st33.o
diff --git a/drivers/tpm/tpm_i2c_stm_st33.c b/drivers/tpm/tpm_i2c_stm_st33.c
new file mode 100644
index 000..6e20f8c
--- /dev/null
+++ b/drivers/tpm/tpm_i2c_stm_st33.c
@@ -0,0 +1,633 @@
+/*
+ * STMicroelectronics TPM I2C UBOOT Linux driver for TPM ST33ZP24
+ * Copyright (C) 2014  STMicroelectronics
+ *
+ * Description: Device driver for ST33ZP24 I2C TPM TCG.
+ *
+ * This device driver implements the TPM interface as defined in
+ * the TCG TPM Interface Spec version 1.21, revision 1.0 and the
+ * STMicroelectronics I2C Protocol Stack Specification version 1.2.0.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * @Author: Jean-Luc BLANC jean-luc.bl...@st.com
+ *
+ * @File: tpm_i2c_stm_st33.c
+ */
+
+#include common.h
+#include i2c.h
+#include linux/types.h
+#include tpm.h
+#include errno.h
+#include asm/unaligned.h
+
+#define MINOR_NUM_I2C  224
+
+#define TPM_ACCESS 0x0
+#define TPM_STS0x18
+#define TPM_HASH_END   0x20
+#define TPM_DATA_FIFO  0x24
+#define TPM_HASH_DATA  0x24
+#define TPM_HASH_START 0x28
+#define TPM_INTF_CAPABILITY0x14
+#define TPM_INT_STATUS 0x10
+#define TPM_INT_ENABLE 0x08
+
+#define TPM_DUMMY_BYTE 0xAA
+#define TPM_WRITE_DIRECTION0x80
+#define TPM_HEADER_SIZE10
+#define TPM_BUFSIZE2048
+
+#define LOCALITY0  0
+#define LOCALITY4  4
+#define LOCALITY0_I2C_ADDR 0x13
+#define LOCALITY4_I2C_ADDR 0x1B
+
+/* Index of Count field in TPM response buffer */
+#define TPM_RSP_SIZE_BYTE  2
+
+/* Maximum command duration */
+#define TPM_MAX_COMMAND_DURATION_MS12
+
+enum stm33zp24_access {
+   TPM_ACCESS_VALID = 0x80,
+   TPM_ACCESS_ACTIVE_LOCALITY = 0x20,
+   TPM_ACCESS_REQUEST_PENDING = 0x04,
+   TPM_ACCESS_REQUEST_USE = 0x02,
+};
+
+enum stm33zp24_status {
+   TPM_STS_VALID = 0x80,
+   TPM_STS_COMMAND_READY = 0x40,
+   TPM_STS_GO = 0x20,
+   TPM_STS_DATA_AVAIL = 0x10,
+   TPM_STS_DATA_EXPECT = 0x08,
+};
+
+enum stm33zp24_int_flags {
+   TPM_GLOBAL_INT_ENABLE = 0x80,
+   TPM_INTF_CMD_READY_INT = 0x080,
+   TPM_INTF_FIFO_AVALAIBLE_INT = 0x040,
+   TPM_INTF_WAKE_UP_READY_INT = 0x020,
+   TPM_INTF_LOCTPM_BUFSIZE4SOFTRELEASE_INT = 0x008,
+   TPM_INTF_LOCALITY_CHANGE_INT = 0x004,
+   TPM_INTF_STS_VALID_INT = 0x002,
+   TPM_INTF_DATA_AVAIL_INT = 0x001,
+};
+
+enum tis_defaults {
+   TIS_SHORT_TIMEOUT_MS = 750, /* ms */
+   TIS_LONG_TIMEOUT_MS = 2000, /* 2 sec */
+};
+
+/**
+ * @addr: TPM I2C address
+ * @i2c_bus: I2C bus ID the TPM is connected to
+ * @is_open: TPM connection establishment information
+ * @locality: active locality of the TPM (0 OR 4)
+ * @buf: command/response buffer
+ * @timeout_*: timeouts for TPM states changes
+ * @duration: maximum time for a TPM command processing
+ */
+struct tpm_chip {
+   uint addr;
+   uint i2c_bus;
+   int is_open;
+   u8 buf[TPM_BUFSIZE];
+   int locality;
+   unsigned long timeout_a, timeout_b, timeout_c, timeout_d;  /* msec */
+   unsigned long duration;  /* msec */
+};
+
+static struct tpm_chip tpm_dev;
+
+/*
+ * write8_reg(): Send byte to the TIS register according to I2C TPM protocol.
+ * @tpm_register, the tpm tis register where the data should be written
+ * @tpm_data, the tpm_data to write inside the tpm_register
+ * @tpm_size, The length of the data
+ * @return: Returns zero in case of success else the 

Re: [U-Boot] CONFIG_SYS_GENERIC_BOARD status

[Masahiro Yamada]

Hi.

On Tue, 8 Jul 2014 21:38:17 +1000
Simon Glass s...@chromium.org wrote:

 Hi,
 
 According to my calculations, as of commit 80a7cac we now have more
 than 238 boards converted to generic board, out of 1171. That is a
 little over 20%, which is a big improvement from last release. I am
 unable to include MIPS or ARM64 so it is an under-estimate.
 
 
 ./tools/buildman/buildman -b dm3b --step 0 -k
 
 grep -l CONFIG_SYS_GENERIC_BOARD
 dm3b/01_of_93_g80a7cac0_Merge-branch-\'tom\'-o/*/autoconf.mk |\wc -l
 238
 

And in terms of architectures, 40% (6/15)
I don't want any archs left over.



Best Regards
Masahiro Yamada

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Re: [U-Boot] [PATCH v3 00/10] sunxi: Bug fixes, sun4i and sun5i support and network improvements

[Ian Campbell]

On Tue, 2014-07-08 at 09:47 +0200, Hans de Goede wrote:
 Have you looked at extending the SPL buildsys bits, which in essence do
 2 builds, to do 3 builds for sunxi, so that we simply always build
 both SPL flavors?

I hadn't thought of it. Is it only the SPL binary which differs between
FEL and non-FEL then?

Ian.

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Re: [U-Boot] SPL broken on i.mx31 platforms, FIX?

[Helmut Raiger]

Hi,

finally I have the SPL running again, with this fix:

diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
index 1cfcca9..53bde12 100644
--- a/arch/arm/cpu/arm1136/start.S
+++ b/arch/arm/cpu/arm1136/start.S
@@ -91,4 +91,9 @@ cpu_init_crit:
bl  lowlevel_init   /* go setup pll,mux,memory */
mov lr, ip  /* restore link */
mov pc, lr  /* back to my caller */
+
+   nop
+   nop
+   nop
+
 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S
index d68cc47..8c0e3c1 100644
--- a/arch/arm/lib/vectors.S
+++ b/arch/arm/lib/vectors.S
@@ -50,7 +50,8 @@ _start:
 #endif

 _start:
-   ldr pc, _reset
+   /* be position independent if SPL is linked at different location */
+   b   reset
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort


I have no clue why the nops are necessary after cpu_init_crit(), but it 
won't work

unless there are at least 3 nops there (pipeline?).
It would be nice to have _some_ explanation for this before posting a patch.

Helmut

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Re: [U-Boot] [PATCH v3 00/10] sunxi: Bug fixes, sun4i and sun5i support and network improvements

[Hans de Goede]

Hi,

On 07/09/2014 10:00 AM, Ian Campbell wrote:
 On Tue, 2014-07-08 at 09:47 +0200, Hans de Goede wrote:
 Have you looked at extending the SPL buildsys bits, which in essence do
 2 builds, to do 3 builds for sunxi, so that we simply always build
 both SPL flavors?
 
 I hadn't thought of it. Is it only the SPL binary which differs between
 FEL and non-FEL then?

AFAIK, Yes.

Note an alternative to doing 3 builds would be to move the load
address for the mmc spl to 0x2000 too, and to change the mmc spl
header to jump to 0x2000 instead of 0x20. The question here is
if the spl with mmc support will fit if we don't use the first
0x2000 bytes. One thing we could do is move the stack to another
sram area (the area where we later copy the PSCI code for example),
which will free up some space.

We would then also need to modify the unified SPL to detect
whether it has booted from mmc or FEL, and only try to load the
real u-boot from mmc in the mmc boot case.

If we do this, we would just need to modify the final build steps
of the SPL build a bit to produce both SPL flavors.

I guess the big question is if we can make the mmc spl fit if
we load it at 0x2000. If you're interested in working on this
you should probably talk to hno about this. Another complication
is that the brom uses some of the 32k sram at address 0 when in
fel mode, so I think you cannot use all of it. hno can probably
give more details here about which bits of the first 32k sram
are used by the brom in fel mode and in mmc mode.

Regards,

Hans



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[U-Boot] [U-boot] question about nand_scan_bbt()

[TigerLiu]

Hi, Scott:

I have a question about nand_scan_bbt() function in
drivers/mtd/nand/nand_bbt.c .

 ..

 len = (1  this-bbt_erase_shift); // bbt_erase_shift = 18
(256KB)

 len += (len  this-page_shift) * mtd-oobsize;

 buf = vmalloc(len);

 ..

 

Why does it need to allocate 1 block size + all pages' oob size in this
block .

It seems other functions called in nand_scan_bbt() only needs a small
buf (one page size + its oob size).

 

Best wishes,

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[U-Boot] [PATCH] ARM: OMAP4/5: Change omap4_sdp/panda and omap5_uevm maintainer

[Lokesh Vutla]

Updating omap4_sdp/panda and omap5_uevm maintainer.

Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
 boards.cfg |6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/boards.cfg b/boards.cfg
index f16a0e6..1c426e6 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -363,13 +363,13 @@ Active  arm armv7  omap3   ti 
 evm
 Active  arm armv7  omap3   ti  sdp3430 
omap3_sdp3430 - 

Nishanth Menon n...@ti.com
 Active  arm armv7  omap3   timll   devkit8000  
devkit8000- 

Thomas Weber we...@corscience.de
 Active  arm armv7  omap4   gumstix duovero 
duovero   - 

Ash Charles a...@gumstix.com
-Active  arm armv7  omap4   ti  panda   
omap4_panda   - 

Sricharan R r.sricha...@ti.com
-Active  arm armv7  omap4   ti  sdp4430 
omap4_sdp4430 - 

Sricharan R r.sricha...@ti.com
+Active  arm armv7  omap4   ti  panda   
omap4_panda   - 

Lokesh Vutla lokeshvu...@ti.com
+Active  arm armv7  omap4   ti  sdp4430 
omap4_sdp4430 - 

Lokesh Vutla lokeshvu...@ti.com
 Active  arm armv7  omap5   compulabcm_t54  
cm_t54- 

Dmitry Lifshitz lifsh...@compulab.co.il
 Active  arm armv7  omap5   ti  dra7xx  
dra7xx_evmdra7xx_evm:CONS_INDEX=1   

Lokesh Vutla lokeshvu...@ti.com
 Active  arm armv7  omap5   ti  dra7xx  
dra7xx_evm_qspiboot   dra7xx_evm:CONS_INDEX=1,QSPI_BOOT 

Lokesh Vutla lokeshvu...@ti.com
 Active  arm armv7  omap5   ti  dra7xx  
dra7xx_evm_uart3  
dra7xx_evm:CONS_INDEX=3,SPL_YMODEM_SUPPORT  
  Lokesh Vutla 
lokeshvu...@ti.com
-Active  arm armv7  omap5   ti  omap5_uevm  
omap5_uevm- 

-
+Active  arm armv7  omap5   ti  omap5_uevm  
omap5_uevm- 

Lokesh Vutla lokeshvu...@ti.com
 Active  arm armv7  rmobile atmark-techno   
armadillo-800evaarmadillo-800eva  - 

Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
 Active  arm armv7  rmobile kmc kzm9g   
kzm9g - 

Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com:Tetsuyuki 
Kobayashi k...@kmckk.co.jp
 Active  arm armv7  rmobile renesas koelsch 
koelsch   - 

Nobuhiro Iwamatsu 

Re: [U-Boot] [PATCH] ARM: OMAP4/5: Change omap4_sdp/panda and omap5_uevm maintainer

[Sricharan R]

On Wednesday 09 July 2014 05:32 PM, Lokesh Vutla wrote:
 Updating omap4_sdp/panda and omap5_uevm maintainer.
 
 Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
 ---
  boards.cfg |6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)
 
 diff --git a/boards.cfg b/boards.cfg
 index f16a0e6..1c426e6 100644
 --- a/boards.cfg
 +++ b/boards.cfg
 @@ -363,13 +363,13 @@ Active  arm armv7  omap3   ti   
evm
  Active  arm armv7  omap3   ti  sdp3430   
   omap3_sdp3430 - 
   
   Nishanth Menon n...@ti.com
  Active  arm armv7  omap3   timll   devkit8000
   devkit8000- 
   
   Thomas Weber we...@corscience.de
  Active  arm armv7  omap4   gumstix duovero   
   duovero   - 
   
   Ash Charles a...@gumstix.com
 -Active  arm armv7  omap4   ti  panda 
   omap4_panda   - 
   
   Sricharan R r.sricha...@ti.com
 -Active  arm armv7  omap4   ti  sdp4430   
   omap4_sdp4430 - 
   
   Sricharan R r.sricha...@ti.com
 +Active  arm armv7  omap4   ti  panda 
   omap4_panda   - 
   
   Lokesh Vutla lokeshvu...@ti.com
 +Active  arm armv7  omap4   ti  sdp4430   
   omap4_sdp4430 - 
   
   Lokesh Vutla lokeshvu...@ti.com
  Active  arm armv7  omap5   compulabcm_t54
   cm_t54- 
   
   Dmitry Lifshitz lifsh...@compulab.co.il
  Active  arm armv7  omap5   ti  dra7xx
   dra7xx_evmdra7xx_evm:CONS_INDEX=1   
   
   Lokesh Vutla lokeshvu...@ti.com
  Active  arm armv7  omap5   ti  dra7xx
   dra7xx_evm_qspiboot   dra7xx_evm:CONS_INDEX=1,QSPI_BOOT 
   
   Lokesh Vutla lokeshvu...@ti.com
  Active  arm armv7  omap5   ti  dra7xx
   dra7xx_evm_uart3  
 dra7xx_evm:CONS_INDEX=3,SPL_YMODEM_SUPPORT
 Lokesh Vutla 
 lokeshvu...@ti.com
 -Active  arm armv7  omap5   ti  omap5_uevm
   omap5_uevm- 
   
   -
 +Active  arm armv7  omap5   ti  omap5_uevm
   omap5_uevm- 
   
   Lokesh Vutla lokeshvu...@ti.com
  Active  arm armv7  rmobile atmark-techno   
 armadillo-800evaarmadillo-800eva  -   
   
 Nobuhiro Iwamatsu 
 nobuhiro.iwamatsu...@renesas.com
  Active  arm armv7  rmobile kmc kzm9g 
   kzm9g - 
   
   Nobuhiro Iwamatsu 
 nobuhiro.iwamatsu...@renesas.com:Tetsuyuki Kobayashi k...@kmckk.co.jp
  Active  arm armv7  rmobile renesas koelsch   
   koelsch   -  

Re: [U-Boot] [PATCH 1/6] ARM: m28evk: add needed commands and options

[Marek Vasut]

On Thursday, June 26, 2014 at 11:01:27 AM, Marek Vasut wrote:
 - env ask, env grep and setexpr are needed for commissioning
 - add support for ext4 file systems
 - adjust default environment to use ext4 commands
 - add write support for (V)FAT and EXT4
 - add bitmap and splashscreen support
 - print timestamp information for images
 
 Signed-off-by: Marek Vasut ma...@denx.de
 Cc: Stefano Babic sba...@denx.de

Tom, can you please pick those 6 for .07 ? Also, as pestered on IRC, which 
exact 
patches do I need to pick from Filipe ? He ignores my email inquiry ...

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v2 2/2] usb: phy: omap_usb_phy: implement usb_phy_power() for AM437x

[Tom Rini]

On Mon, Jul 07, 2014 at 08:08:29PM +0200, Marek Vasut wrote:
 On Monday, July 07, 2014 at 06:14:23 PM, Felipe Balbi wrote:
  hi,
  
  On Mon, Jun 23, 2014 at 05:18:24PM -0500, Felipe Balbi wrote:
   Newer AM437x silicon requires us to explicitly power up
   the USB2 PHY. By implementing usb_phy_power() we can
   achieve that.
   
   Signed-off-by: Felipe Balbi ba...@ti.com
   ---
   
   Changes since v1:
 - add macros for USB1_CTRL register and bits
  
  same here. Still pending, am437x will remain broken until this is
  applied.
 
 What do you need for .07, this and 1/2 of this series ? Or did I miss
 something else?
 
 In any case, sorry, will apply them once I know which ones.

Yes, 1/2 and 2/2 are the missing USB bits..

-- 
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Re: [U-Boot] [PATCH 1/6] ARM: m28evk: add needed commands and options

[Tom Rini]

On Wed, Jul 09, 2014 at 02:09:05PM +0200, Marek Vasut wrote:

 On Thursday, June 26, 2014 at 11:01:27 AM, Marek Vasut wrote:
  - env ask, env grep and setexpr are needed for commissioning
  - add support for ext4 file systems
  - adjust default environment to use ext4 commands
  - add write support for (V)FAT and EXT4
  - add bitmap and splashscreen support
  - print timestamp information for images
  
  Signed-off-by: Marek Vasut ma...@denx.de
  Cc: Stefano Babic sba...@denx.de
 
 Tom, can you please pick those 6 for .07 ? Also, as pestered on IRC,
 which exact patches do I need to pick from Filipe ? He ignores my
 email inquiry ...

If Stefano gives me a PR, since these are i.MX things, yes.

-- 
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Re: [U-Boot] [PATCH v2 2/2] usb: phy: omap_usb_phy: implement usb_phy_power() for AM437x

[Michael Trimarchi]

Hi Tom

On Wed, Jul 9, 2014 at 2:41 PM, Tom Rini tr...@ti.com wrote:
 On Mon, Jul 07, 2014 at 08:08:29PM +0200, Marek Vasut wrote:
 On Monday, July 07, 2014 at 06:14:23 PM, Felipe Balbi wrote:
  hi,
 
  On Mon, Jun 23, 2014 at 05:18:24PM -0500, Felipe Balbi wrote:
   Newer AM437x silicon requires us to explicitly power up
   the USB2 PHY. By implementing usb_phy_power() we can
   achieve that.
  
   Signed-off-by: Felipe Balbi ba...@ti.com
   ---
  
   Changes since v1:
 - add macros for USB1_CTRL register and bits
 
  same here. Still pending, am437x will remain broken until this is
  applied.

 What do you need for .07, this and 1/2 of this series ? Or did I miss
 something else?

 In any case, sorry, will apply them once I know which ones.

 Yes, 1/2 and 2/2 are the missing USB bits..


Marek comment out about using clrbits and setbits. So it's better
to resend them

Michael

 --
 Tom

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Re: [U-Boot] [PATCH 1/6] ARM: m28evk: add needed commands and options

[Stefano Babic]

On 09/07/2014 14:42, Tom Rini wrote:
 On Wed, Jul 09, 2014 at 02:09:05PM +0200, Marek Vasut wrote:
 
 On Thursday, June 26, 2014 at 11:01:27 AM, Marek Vasut wrote:
 - env ask, env grep and setexpr are needed for
 commissioning - add support for ext4 file systems - adjust
 default environment to use ext4 commands - add write support
 for (V)FAT and EXT4 - add bitmap and splashscreen support -
 print timestamp information for images
 
 Signed-off-by: Marek Vasut ma...@denx.de Cc: Stefano Babic
 sba...@denx.de
 
 Tom, can you please pick those 6 for .07 ? Also, as pestered on
 IRC, which exact patches do I need to pick from Filipe ? He
 ignores my email inquiry ...
 
 If Stefano gives me a PR, since these are i.MX things, yes.
 

ok, I'll provide it.

Stefano

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Re: [U-Boot] [PATCH] MX6: Correct calculation of PLL_SYS

[Stefano Babic]

On 09/06/2014 22:47, Andre Renaud wrote:
 DIV_SELECT is used as Fout = Fin * div_select / 2.0, so we should do
 the shift after the multiply to avoid rounding errors
 
 Signed-off-by: Andre Renaud an...@bluewatersys.com
 ---
  arch/arm/cpu/armv7/mx6/clock.c |2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
 index bd65a08..7dd83ec 100644
 --- a/arch/arm/cpu/armv7/mx6/clock.c

Applied to u-boot-imx, as a fix, thanks !

Best regards,
Stefano Babic


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Re: [U-Boot] [PATCH] mx6: soc: Update the comments of set_ldo_voltage()

[Stefano Babic]

Hi Fabio,

On 13/06/2014 06:42, Fabio Estevam wrote:
 From: Fabio Estevam fabio.este...@freescale.com
 
 Commit 3d622b78 (mx6: soc: Introduce set_ldo_voltage()) introduces 
 set_ldo_voltage() function that can be used to set the voltages
 of any of the three LDO regulators controlled by the PMU_REG_CORE register.
 
 Prior to this commit there was a single set_vddsoc() which only configured the
 VDDSOC regulator.
 
 Update the comments to align with the new set_ldo_voltage() implementation.
 
 Signed-off-by: Fabio Estevam fabio.este...@freescale.com
 ---

Applied to u-boot-imx (fix), thanks !

Best regards,
Stefano Babic


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Re: [U-Boot] [PATCH] boards.cfg: keep it sorted filling the board field

[Tom Rini]

On Wed, Jul 09, 2014 at 05:34:28PM +0900, Masahiro Yamada wrote:
 The boards.cfg file has allowed to use - for the board (= 6th) field
 if the board name is the same as the 7th field.
 
 But I notice one problem.
 Because tools/reformat.py sorts the lines in the simple alphabetical
 order (= the order of character code), some entries for the same board
 are not lined up together.
 
 For example, bf527-ezkit and bf527-ezkit-v2 share the same board.
 But they are located separately because bf527-ezkit fills the board
 field with - whereas bf527-ezkit-v2 specifies it explicitely.
 
 The similar things can be seen:
  - between trizepsive and polaris
  - between RRvision and RRvision_LCD
  - between korat and korat_perm
  - between lwmon5 and lcd4_lwmon5
 
 This commit was generated by the following command:
 
 awk '$6 == - { $6 = $7 } { print }' boards.cfg \
   | tools/reformat.py -i -d '-' -s 8   boards0.cfg; \
   mv boards0.cfg boards.cfg
 
 Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com

Tricky!  So I'm fine with correcting this problem but we also need to
update the top part of baords.cfg where it says how to re-sort things so
that we don't lose this in the future.

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Re: [U-Boot] [PATCH v3 00/10] sunxi: Bug fixes, sun4i and sun5i support and network improvements

[Henrik Nordström]

ons 2014-07-09 klockan 09:00 +0100 skrev Ian Campbell:

 I hadn't thought of it. Is it only the SPL binary which differs between
 FEL and non-FEL then?

There is also a small difference in the default environment to enable
boot-from-RAM in the FEL version of main u-boot. This is not enabled in
the normal u-boot to avoid any risk of infinite looping boot failure
from wrongly detected ram boot image.

Regards
Henrik

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[U-Boot] [PULL]: small fixes from u-boot-imx

[Stefano Babic]

Hi Tom,

please pull from u-boot-imx - hopefully last fixes for the release. Thanks !

The following changes since commit 3f4c01d9f9d38e383f004dcd06c0d5661f2a57e0:

  mx25pdk: Remove CONFIG_SYS_GENERIC_BOARD (2014-06-26 10:17:19 +0200)

are available in the git repository at:

  git://www.denx.de/git/u-boot-imx.git master

for you to fetch changes up to 157f45da91b306d71dbf3a51325352dc11bf16d1:

  mx6: soc: Update the comments of set_ldo_voltage() (2014-07-09
15:10:10 +0200)


Andre Renaud (1):
  MX6: Correct calculation of PLL_SYS

Fabio Estevam (1):
  mx6: soc: Update the comments of set_ldo_voltage()

Lothar Rubusch (2):
  ARM: m28evk: Update default environment
  ARM: m53evk: Update default environment

Marek Vasut (4):
  ARM: m28evk: add needed commands and options
  ARM: m28evk: Adjust mtdparts
  ARM: m53evk: add needed commands and options
  ARM: m53evk: Adjust mtdparts settings

 arch/arm/cpu/armv7/mx6/clock.c |   2 +-
 arch/arm/cpu/armv7/mx6/soc.c   |   5 +-
 include/configs/m28evk.h   | 116
++-
 include/configs/m53evk.h   | 122
+
 4 files changed, 215 insertions(+), 30 deletions(-)


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Re: [U-Boot] ARM: OMAP4/5: Change omap4_sdp/panda and omap5_uevm maintainer

[Tom Rini]

On Wed, Jul 09, 2014 at 05:32:26PM +0530, Lokesh Vutla wrote:

 Updating omap4_sdp/panda and omap5_uevm maintainer.
 
 Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
 Acked-by: R Sricharan r.sricha...@ti.com

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PULL]: small fixes from u-boot-imx

[Tom Rini]

On Wed, Jul 09, 2014 at 03:19:19PM +0200, Stefano Babic wrote:

 Hi Tom,
 
 please pull from u-boot-imx - hopefully last fixes for the release. Thanks !
 
 The following changes since commit 3f4c01d9f9d38e383f004dcd06c0d5661f2a57e0:
 
   mx25pdk: Remove CONFIG_SYS_GENERIC_BOARD (2014-06-26 10:17:19 +0200)
 
 are available in the git repository at:
 
   git://www.denx.de/git/u-boot-imx.git master
 
 for you to fetch changes up to 157f45da91b306d71dbf3a51325352dc11bf16d1:
 
   mx6: soc: Update the comments of set_ldo_voltage() (2014-07-09
 15:10:10 +0200)
 
 
 Andre Renaud (1):
   MX6: Correct calculation of PLL_SYS
 
 Fabio Estevam (1):
   mx6: soc: Update the comments of set_ldo_voltage()
 
 Lothar Rubusch (2):
   ARM: m28evk: Update default environment
   ARM: m53evk: Update default environment
 
 Marek Vasut (4):
   ARM: m28evk: add needed commands and options
   ARM: m28evk: Adjust mtdparts
   ARM: m53evk: add needed commands and options
   ARM: m53evk: Adjust mtdparts settings
 
  arch/arm/cpu/armv7/mx6/clock.c |   2 +-
  arch/arm/cpu/armv7/mx6/soc.c   |   5 +-
  include/configs/m28evk.h   | 116
 ++-
  include/configs/m53evk.h   | 122
 +
  4 files changed, 215 insertions(+), 30 deletions(-)

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] [PATCH v2 17/29] dm: Introduce device sequence numbering

[Jon Loeliger]

HI Simon,

On Tue, Jul 8, 2014 at 10:38 PM, Simon Glass s...@chromium.org wrote:
 In U-Boot it is pretty common to number devices from 0 and access them
 on the command line using this numbering. While it may come to pass that
 we will move away from this numbering, the possibility seems remote at
 present.

 Given that devices within a uclass will have an implied numbering, it
 makes sense to build this into driver model as a core feature. The cost
 is fairly small in terms of code and data space.

Hmmm.  I'm not entirely in agreement here.  I think this is the wrong
long-term approach, and this just reinforces the status quo rather than
allowing a migration to a better approach.

 With each uclass having numbered devices we can ask for SPI port 0 or
 serial port 1 and receive a single device.

That's nice, but we should allow them to be named by their actual
names as found in the device tree too.

 Devices typically request a sequence number using aliases in the device
 tree. These are resolved when the device is probed, to deal with conflicts.
 Sequence numbers need not be sequential and holes are permitted.

So they are unreliably unpredictable, unless you also happen
to have the DTS decoder ring in hand too?


 +This indicates that in the uclass called serial, the named node
 +(/serial@2223) will be given sequence number 2. Any command or driver
 +which requests serial device 2 will obtain this device.
 +
 +Some devices represent buses where the devices on the bus are numbered or
 +addressed. For example, SPI typically numbers its slaves from 0, and I2C
 +uses a 7-bit address. In these cases the 'reg' property of the subnode is
 +used, for example:
 +
 +{
 +   aliases {
 +   spi2 = /spi@2230;
 +   };
 +
 +   spi@2230 {
 +   #address-cells = 1;
 +   #size-cells = 1;
 +   spi-flash@0 {
 +   reg = 0;
 +   ...
 +   }
 +   eeprom@1 {
 +   reg = 1;
 +   };
 +   };

And not everyone agrees that this is the best approach, even in Linux land.
Specifically, we should be in agreement with Linux, and we should not
have our DTS stray from the definitions that Linux will accept for the same
devices.  And this approach won't be bought by the Linux crowd.  (Yes,
there are some that use  a reg = 0; approach here, but there are many
that do not too.  It's not a universally accepted approach.)

This concept is crucial.

I've said it before, and I will say it again if needed.

So:  Sure, put this approach in, but make it be the backward compatible
approach.  Also please put in a correct naming approach so that we can
move forward with a better longer term solution too.

Thanks,
jdl
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Re: [U-Boot] [PATCH v3 00/10] sunxi: Bug fixes, sun4i and sun5i support and network improvements

[Hans de Goede]

Hi,

On 07/09/2014 03:03 PM, Henrik Nordström wrote:
 ons 2014-07-09 klockan 09:00 +0100 skrev Ian Campbell:
 
 I hadn't thought of it. Is it only the SPL binary which differs between
 FEL and non-FEL then?
 
 There is also a small difference in the default environment to enable
 boot-from-RAM in the FEL version of main u-boot. This is not enabled in
 the normal u-boot to avoid any risk of infinite looping boot failure
 from wrongly detected ram boot image.

Henrik, can you provide us with some memorymap info of the first
32K of SRAM for when booted from FEL vs MMC for all of sun4i, sun5i
and sun7i ?

It would be good to know which bits of SRAM actually get uses by the BROM,
and thus should not be overwritten, and which ones are free to use.

Regards,

Hans
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[U-Boot] [PATCH] doc: Add zynq fragment to git-mailrc file

[Michal Simek]

Signed-off-by: Michal Simek michal.si...@xilinx.com
---

 doc/git-mailrc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/doc/git-mailrc b/doc/git-mailrc
index 3d97d306144d..ae7e7bfb5bba 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -62,6 +62,7 @@ alias sunxi  uboot, ijc, jwrdegoede
 alias tegra  uboot, sjg, Tom Warren twar...@nvidia.com, Stephen 
Warren swar...@nvidia.com
 alias tegra2 tegra
 alias ti uboot, trini
+alias zynq   uboot, monstr

 alias avr32  uboot, abiessmann

--
1.8.2.3



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Re: [U-Boot] [PATCH] doc: Add zynq fragment to git-mailrc file

[Tom Rini]

On Wed, Jul 09, 2014 at 04:10:49PM +0200, Michal Simek wrote:

 Signed-off-by: Michal Simek michal.si...@xilinx.com

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH 2/5] sunxi: add USB EHCI driver

[Ian Campbell]

On Tue, 2014-07-08 at 22:21 +0200, Roman Byshko wrote:
 diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c
 new file mode 100644
 index 000..5817fc7
 --- /dev/null
 +++ b/drivers/usb/host/ehci-sunxi.c
 @@ -0,0 +1,236 @@
 +/*
 + * Copyright (C) 2014 arokux
 + *
 + * arokux aro...@gmail.com

The authorship info here contradicts the authorship suggested by the
commit email metadata and the S-o-b.

If arokux wrote this patch then the commit message should begin with 

From: Arokux X aro...@gmail.com

on the first line and arokux needs to have Signed-off on the patch.

I'm not sure what u-boot policy says about pseudonyms.

 + *
 + * Based on code from
 + * Allwinner Technology Co., Ltd. www.allwinnertech.com
 + *
 + * See file CREDITS for list of people who contributed to this
 + * project.
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License as
 + * published by the Free Software Foundation; either version 2 of
 + * the License, or (at your option) any later version.

Please use the SPDX tag instead of the full license.

 + dat = readl(pio-dat);
 + if (val)
 + dat |= 0x1  num;
 + else
 + dat = ~(0x1  num);
 +
 + writel(dat, pio-dat);

This is 
if (val)
setbits_le32(pio-dat, 1num);
else
clrbits_le32(pio-dat, 1num);

It seems like there are a bunch of similar constructs around the place.

 + return 0;
 +}
 +
 +static void usb_phy_write(struct sunxi_ehci_hcd *sunxi_ehci, int addr,
 +   int data, int len)
 +{
 + int temp = 0, j = 0, usbc_bit = 0;
 + void *dest = sunxi_ehci-csr;
 +
 + usbc_bit = BIT(sunxi_ehci-id * 2);
 + for (j = 0; j  len; j++) {
 + /* set the bit address to be written */
 + temp = readl(dest);
 + temp = ~(0xff  8);
 + temp |= ((addr + j)  8);
 + writel(temp, dest);

clrsetbits?

 +
 + clrbits_le32(dest, usbc_bit);
 + /* set data bit */
 + if (data  0x1)
 + temp |= BIT(7);
 + else
 + temp = ~BIT(7);
 + writeb(temp, dest);

AFAICT this will clobber the clearing of usbc_bit which you just did,
since temp was read before that, is that right?

This should probably use the clr/setbits_le32 stuff and if it really is
deliberately clobbering usbc_bit I think it needs a comment.

 +
 + setbits_le32(dest, usbc_bit);
 +
 + clrbits_le32( dest, usbc_bit);

Extra space in this line.

 + /* gpio_direction_output(sunxi_ehci-gpio_vbus, 1); */

???

 +static void sunxi_ehci_disable(struct sunxi_ehci_hcd *sunxi_ehci)
 +{
 + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 +
 + /* gpio_direction_output(sunxi_ehci-gpio_vbus, 0); */

???

Ian.

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[U-Boot] [PATCH] tricorder: convert to generic board

[Andreas Bießmann]

Signed-off-by: Andreas Bießmann andreas.de...@googlemail.com
Cc: Thomas Weber thomas.we...@corscience.de
---

 include/configs/tricorder.h |2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index 80985a2..847e099 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -35,6 +35,8 @@
 #include asm/arch/cpu.h  /* get chip and board defs */
 #include asm/arch/omap3.h
 
+#define CONFIG_SYS_GENERIC_BOARD
+
 /* Display CPU and Board information */
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
-- 
1.7.10.4

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[U-Boot] [PATCH 2/3] ARM: omap: Remove unused arch/arm/cpu/armv7/omap3/mem.c

[Stefan Roese]

These functions have been merged into the common GPMC init code
with this commit a0a37183 (ARM: omap: merge GPMC initialization code
for all platform). The file is not compiled any more. So remove it
as well.

Signed-off-by: Stefan Roese s...@denx.de
Cc: Pekon Gupta pe...@ti.com
Cc: Tom Rini tr...@ti.com
---
 arch/arm/cpu/armv7/omap3/mem.c | 139 -
 1 file changed, 139 deletions(-)
 delete mode 100644 arch/arm/cpu/armv7/omap3/mem.c

diff --git a/arch/arm/cpu/armv7/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c
deleted file mode 100644
index 1832aff..000
--- a/arch/arm/cpu/armv7/omap3/mem.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * (C) Copyright 2008
- * Texas Instruments, www.ti.com
- *
- * Author :
- * Manikandan Pillai mani.pil...@ti.com
- *
- * Initial Code from:
- * Richard Woodruff r-woodru...@ti.com
- * Syed Mohammed Khasim kha...@ti.com
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#include common.h
-#include asm/io.h
-#include asm/arch/mem.h
-#include asm/arch/sys_proto.h
-#include command.h
-
-struct gpmc *gpmc_cfg;
-
-#if defined(CONFIG_CMD_NAND)
-static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
-   M_NAND_GPMC_CONFIG1,
-   M_NAND_GPMC_CONFIG2,
-   M_NAND_GPMC_CONFIG3,
-   M_NAND_GPMC_CONFIG4,
-   M_NAND_GPMC_CONFIG5,
-   M_NAND_GPMC_CONFIG6, 0
-};
-#endif /* CONFIG_CMD_NAND */
-
-#if defined(CONFIG_CMD_ONENAND)
-static const u32 gpmc_onenand[GPMC_MAX_REG] = {
-   ONENAND_GPMC_CONFIG1,
-   ONENAND_GPMC_CONFIG2,
-   ONENAND_GPMC_CONFIG3,
-   ONENAND_GPMC_CONFIG4,
-   ONENAND_GPMC_CONFIG5,
-   ONENAND_GPMC_CONFIG6, 0
-};
-#endif /* CONFIG_CMD_ONENAND */
-
-/
- *  mem_ok() - test used to see if timings are correct
- * for a part. Helps in guessing which part
- * we are currently using.
- ***/
-u32 mem_ok(u32 cs)
-{
-   u32 val1, val2, addr;
-   u32 pattern = 0x12345678;
-
-   addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
-
-   writel(0x0, addr + 0x400);  /* clear pos A */
-   writel(pattern, addr);  /* pattern to pos B */
-   writel(0x0, addr + 4);  /* remove pattern off the bus */
-   val1 = readl(addr + 0x400); /* get pos A value */
-   val2 = readl(addr); /* get val2 */
-   writel(0x0, addr + 0x400);  /* clear pos A */
-
-   if ((val1 != 0) || (val2 != pattern))   /* see if pos A val changed */
-   return 0;
-   else
-   return 1;
-}
-
-void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 
base,
-   u32 size)
-{
-   writel(0, cs-config7);
-   sdelay(1000);
-   /* Delay for settling */
-   writel(gpmc_config[0], cs-config1);
-   writel(gpmc_config[1], cs-config2);
-   writel(gpmc_config[2], cs-config3);
-   writel(gpmc_config[3], cs-config4);
-   writel(gpmc_config[4], cs-config5);
-   writel(gpmc_config[5], cs-config6);
-
-   /*
-* Enable the config.  size is the CS size and goes in
-* bits 11:8.  We set bit 6 to enable this CS and the base
-* address goes into bits 5:0.
-*/
-writel((size  8) | (GPMC_CS_ENABLE  6) |
-((base  24)  GPMC_BASEADDR_MASK),
-cs-config7);
-   sdelay(2000);
-}
-
-/*
- * gpmc_init(): init gpmc bus
- * Init GPMC for x16, MuxMode (SDRAM in x32).
- * This code can only be executed from SRAM or SDRAM.
- */
-void gpmc_init(void)
-{
-   /* putting a blanket check on GPMC based on ZeBu for now */
-   gpmc_cfg = (struct gpmc *)GPMC_BASE;
-#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
-   const u32 *gpmc_config = NULL;
-   u32 base = 0;
-   u32 size = 0;
-#endif
-   u32 config = 0;
-
-   /* global settings */
-   writel(0, gpmc_cfg-irqenable); /* isr's sources masked */
-   writel(0, gpmc_cfg-timeout_control);/* timeout disable */
-
-   config = readl(gpmc_cfg-config);
-   config = (~0xf00);
-   writel(config, gpmc_cfg-config);
-
-   /*
-* Disable the GPMC0 config set by ROM code
-* It conflicts with our MPDB (both at 0x0800)
-*/
-   writel(0, gpmc_cfg-cs[0].config7);
-   sdelay(1000);
-
-#if defined(CONFIG_CMD_NAND)   /* CS 0 */
-   gpmc_config = gpmc_m_nand;
-
-   base = PISMO1_NAND_BASE;
-   size = PISMO1_NAND_SIZE;
-   enable_gpmc_cs_config(gpmc_config, gpmc_cfg-cs[0], base, size);
-#endif
-
-#if defined(CONFIG_CMD_ONENAND)
-   gpmc_config = gpmc_onenand;
-   base = PISMO1_ONEN_BASE;
-   size = PISMO1_ONEN_SIZE;
-   enable_gpmc_cs_config(gpmc_config, gpmc_cfg-cs[0], base, size);
-#endif
-}
-- 
2.0.1

[U-Boot] [PATCH 3/3] ARM: omap: tao3530: Convert to generic board

[Stefan Roese]

Use generic board setup functions by defining
CONFIG_SYS_GENERIC_BOARD.

Signed-off-by: Stefan Roese s...@denx.de
Cc: Tom Rini tr...@ti.com
---
 include/configs/tao3530.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
index 1b0fee9..62613e1 100644
--- a/include/configs/tao3530.h
+++ b/include/configs/tao3530.h
@@ -22,6 +22,7 @@
 
 #define CONFIG_OMAP_GPIO
 #define CONFIG_OMAP_COMMON
+#define CONFIG_SYS_GENERIC_BOARD
 
 #define MACH_TYPE_OMAP3_TAO35302836
 
-- 
2.0.1

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[U-Boot] [PATCH 1/3] ARM: omap: Fix GPMC init for OMAP3 platforms

[Stefan Roese]

Commit a0a37183 (ARM: omap: merge GPMC initialization code for all
platform) broke NAND on OMAP3 based platforms. I noticed this while
testing the latest 2014.07-rc version on the TAO3530 board. NAND
detection did not work with this error message:

NAND:  nand: error: Unable to find NAND settings in GPMC Configuration - 
quitting

As OMAP3 configs don't set CONFIG_NAND but CONFIG_NAND_CMD. the GPMC
was not initialized for NAND at all. This patch now fixes this issue.

Tested on TAO3530 board.

Signed-off-by: Stefan Roese s...@denx.de
Cc: Pekon Gupta pe...@ti.com
Cc: Tom Rini tr...@ti.com
---
 arch/arm/cpu/armv7/omap-common/mem-common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c 
b/arch/arm/cpu/armv7/omap-common/mem-common.c
index 5bc7e1f..ba26cd1 100644
--- a/arch/arm/cpu/armv7/omap-common/mem-common.c
+++ b/arch/arm/cpu/armv7/omap-common/mem-common.c
@@ -89,7 +89,7 @@ void gpmc_init(void)
};
u32 size = GPMC_SIZE_16M;
u32 base = CONFIG_SYS_FLASH_BASE;
-#elif defined(CONFIG_NAND)
+#elif defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
 /* configure GPMC for NAND */
const u32  gpmc_regs[GPMC_MAX_REG] = {  M_NAND_GPMC_CONFIG1,
M_NAND_GPMC_CONFIG2,
-- 
2.0.1

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Re: [U-Boot] [PATCH] ARM: OMAP4/5: Change omap4_sdp/panda and omap5_uevm maintainer

[Nishanth Menon]

On 07/09/2014 07:02 AM, Lokesh Vutla wrote:

Updating omap4_sdp/panda and omap5_uevm maintainer.

Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
  boards.cfg |6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/boards.cfg b/boards.cfg
index f16a0e6..1c426e6 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -363,13 +363,13 @@ Active  arm armv7  omap3   ti 
 evm
  Active  arm armv7  omap3   ti  sdp3430 
omap3_sdp3430 -   
  
Nishanth Menon n...@ti.com
  Active  arm armv7  omap3   timll   devkit8000  
devkit8000-   
  
Thomas Weber we...@corscience.de
  Active  arm armv7  omap4   gumstix duovero 
duovero   -   
  Ash 
Charles a...@gumstix.com
-Active  arm armv7  omap4   ti  panda   
omap4_panda   -   
  
Sricharan R r.sricha...@ti.com
-Active  arm armv7  omap4   ti  sdp4430 
omap4_sdp4430 -   
  
Sricharan R r.sricha...@ti.com
+Active  arm armv7  omap4   ti  panda   
omap4_panda   -   
  
Lokesh Vutla lokeshvu...@ti.com
+Active  arm armv7  omap4   ti  sdp4430 
omap4_sdp4430 -   
  
Lokesh Vutla lokeshvu...@ti.com
  Active  arm armv7  omap5   compulabcm_t54  
cm_t54-   
  
Dmitry Lifshitz lifsh...@compulab.co.il
  Active  arm armv7  omap5   ti  dra7xx  
dra7xx_evmdra7xx_evm:CONS_INDEX=1 
  
Lokesh Vutla lokeshvu...@ti.com
  Active  arm armv7  omap5   ti  dra7xx  
dra7xx_evm_qspiboot   dra7xx_evm:CONS_INDEX=1,QSPI_BOOT   
  
Lokesh Vutla lokeshvu...@ti.com
  Active  arm armv7  omap5   ti  dra7xx  
dra7xx_evm_uart3  dra7xx_evm:CONS_INDEX=3,SPL_YMODEM_SUPPORT  
  
Lokesh Vutla lokeshvu...@ti.com
-Active  arm armv7  omap5   ti  omap5_uevm  
omap5_uevm- 

-
+Active  arm armv7  omap5   ti  omap5_uevm  
omap5_uevm-   
  
Lokesh Vutla lokeshvu...@ti.com
  Active  arm armv7  rmobile atmark-techno   armadillo-800eva
armadillo-800eva  -   
  
Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
  Active  arm armv7  rmobile kmc kzm9g   kzm9g  
   -
 Nobuhiro Iwamatsu 
nobuhiro.iwamatsu...@renesas.com:Tetsuyuki Kobayashi k...@kmckk.co.jp
  Active  arm armv7  rmobile renesas koelsch 
koelsch   -   
 

[U-Boot] [[U-boot] [Patch 1/6] ARM: keystone2: psc: use common PSC base

[Ivan Khoronzhuk]

Use common keystone2 Power Sleep controller base address instead of
directly deciding which keystone2 SoC is used in psc module.

Acked-by: Murali Karicheri m-kariche...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
 arch/arm/cpu/armv7/keystone/psc.c  | 42 ++
 arch/arm/include/asm/arch-keystone/hardware-k2hk.h |  1 -
 arch/arm/include/asm/arch-keystone/hardware.h  |  3 ++
 3 files changed, 22 insertions(+), 24 deletions(-)

diff --git a/arch/arm/cpu/armv7/keystone/psc.c 
b/arch/arm/cpu/armv7/keystone/psc.c
index c844dc8..fa5422f 100644
--- a/arch/arm/cpu/armv7/keystone/psc.c
+++ b/arch/arm/cpu/armv7/keystone/psc.c
@@ -16,10 +16,6 @@
 #define DEVICE_REG32_R(addr)   __raw_readl((u32 *)(addr))
 #define DEVICE_REG32_W(addr, val)  __raw_writel(val, (u32 *)(addr))
 
-#ifdef CONFIG_SOC_K2HK
-#define DEVICE_PSC_BASEK2HK_PSC_BASE
-#endif
-
 int psc_delay(void)
 {
udelay(10);
@@ -55,7 +51,7 @@ int psc_wait(u32 domain_num)
retry = 0;
 
do {
-   ptstat = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PSTAT);
+   ptstat = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PSTAT);
ptstat = ptstat  (1  domain_num);
} while ((ptstat != 0)  ((retry += psc_delay()) 
 PSC_PTSTAT_TIMEOUT_LIMIT));
@@ -71,7 +67,7 @@ u32 psc_get_domain_num(u32 mod_num)
u32 domain_num;
 
/* Get the power domain associated with the module number */
-   domain_num = DEVICE_REG32_R(DEVICE_PSC_BASE +
+   domain_num = DEVICE_REG32_R(KS2_PSC_BASE +
PSC_REG_MDCFG(mod_num));
domain_num = PSC_REG_MDCFG_GET_PD(domain_num);
 
@@ -106,7 +102,7 @@ int psc_set_state(u32 mod_num, u32 state)
 * Get the power domain associated with the module number, and reset
 * isolation functionality
 */
-   v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
+   v = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
domain_num = PSC_REG_MDCFG_GET_PD(v);
reset_iso  = PSC_REG_MDCFG_GET_RESET_ISO(v);
 
@@ -123,24 +119,24 @@ int psc_set_state(u32 mod_num, u32 state)
 * change is made if the new state is power down.
 */
if (state == PSC_REG_VAL_MDCTL_NEXT_ON) {
-   pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE +
+   pdctl = DEVICE_REG32_R(KS2_PSC_BASE +
   PSC_REG_PDCTL(domain_num));
pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl,
   PSC_REG_VAL_PDCTL_NEXT_ON);
-   DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num),
+   DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num),
   pdctl);
}
 
/* Set the next state for the module to enabled/disabled */
-   mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+   mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state);
mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, reset_iso);
-   DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+   DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
 
/* Trigger the enable */
-   ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
+   ptcmd = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PTCMD);
ptcmd |= (u32)(1domain_num);
-   DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
+   DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PTCMD, ptcmd);
 
/* Wait on the complete */
return psc_wait(domain_num);
@@ -161,7 +157,7 @@ int psc_enable_module(u32 mod_num)
u32 mdctl;
 
/* Set the bit to apply reset */
-   mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+   mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
if ((mdctl  0x3f) == PSC_REG_VAL_MDSTAT_STATE_ON)
return 0;
 
@@ -180,11 +176,11 @@ int psc_disable_module(u32 mod_num)
u32 mdctl;
 
/* Set the bit to apply reset */
-   mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+   mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
if ((mdctl  0x3f) == 0)
return 0;
mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0);
-   DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+   DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
 
return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE);
 }
@@ -203,11 +199,11 @@ int psc_set_reset_iso(u32 mod_num)
u32 mdctl;
 
/* Set the reset isolation bit */
-   mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+   mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = 

[U-Boot] [[U-boot] [Patch 2/6] keystone: ddr3: add ddr3.h to hold ddr3 API

[Ivan Khoronzhuk]

It's convinient to hold ddr3 function definitions in separate file
such as ddr3.h. So move this from hardware.h to ddr3.h.

Acked-by: Murali Karicheri m-kariche...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
 arch/arm/cpu/armv7/keystone/ddr3.c|  6 +--
 arch/arm/include/asm/arch-keystone/ddr3.h | 55 +++
 arch/arm/include/asm/arch-keystone/hardware.h | 39 ---
 board/ti/k2hk_evm/board.c |  3 +-
 board/ti/k2hk_evm/ddr3.c  | 27 +++--
 5 files changed, 76 insertions(+), 54 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-keystone/ddr3.h

diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c 
b/arch/arm/cpu/armv7/keystone/ddr3.c
index 4875db7..bb16551 100644
--- a/arch/arm/cpu/armv7/keystone/ddr3.c
+++ b/arch/arm/cpu/armv7/keystone/ddr3.c
@@ -7,10 +7,10 @@
  * SPDX-License-Identifier: GPL-2.0+
  */
 
-#include asm/arch/hardware.h
 #include asm/io.h
+#include asm/arch/ddr3.h
 
-void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
+void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
 {
unsigned int tmp;
 
@@ -57,7 +57,7 @@ void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
;
 }
 
-void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
+void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
 {
__raw_writel(emif_cfg-sdcfg,  base + KS2_DDR3_SDCFG_OFFSET);
__raw_writel(emif_cfg-sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);
diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h 
b/arch/arm/include/asm/arch-keystone/ddr3.h
new file mode 100644
index 000..05b7e29
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/ddr3.h
@@ -0,0 +1,55 @@
+/*
+ * DDR3
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DDR3_H_
+#define _DDR3_H_
+
+#include asm/arch/hardware.h
+
+struct ddr3_phy_config {
+   unsigned int pllcr;
+   unsigned int pgcr1_mask;
+   unsigned int pgcr1_val;
+   unsigned int ptr0;
+   unsigned int ptr1;
+   unsigned int ptr2;
+   unsigned int ptr3;
+   unsigned int ptr4;
+   unsigned int dcr_mask;
+   unsigned int dcr_val;
+   unsigned int dtpr0;
+   unsigned int dtpr1;
+   unsigned int dtpr2;
+   unsigned int mr0;
+   unsigned int mr1;
+   unsigned int mr2;
+   unsigned int dtcr;
+   unsigned int pgcr2;
+   unsigned int zq0cr1;
+   unsigned int zq1cr1;
+   unsigned int zq2cr1;
+   unsigned int pir_v1;
+   unsigned int pir_v2;
+};
+
+struct ddr3_emif_config {
+   unsigned int sdcfg;
+   unsigned int sdtim1;
+   unsigned int sdtim2;
+   unsigned int sdtim3;
+   unsigned int sdtim4;
+   unsigned int zqcfg;
+   unsigned int sdrfc;
+};
+
+void ddr3_init(void);
+void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
+void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
+
+#endif
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h 
b/arch/arm/include/asm/arch-keystone/hardware.h
index 4e49143..f8f986c 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -22,42 +22,6 @@
 typedef volatile unsigned int   dv_reg;
 typedef volatile unsigned int   *dv_reg_p;
 
-struct ddr3_phy_config {
-   unsigned int pllcr;
-   unsigned int pgcr1_mask;
-   unsigned int pgcr1_val;
-   unsigned int ptr0;
-   unsigned int ptr1;
-   unsigned int ptr2;
-   unsigned int ptr3;
-   unsigned int ptr4;
-   unsigned int dcr_mask;
-   unsigned int dcr_val;
-   unsigned int dtpr0;
-   unsigned int dtpr1;
-   unsigned int dtpr2;
-   unsigned int mr0;
-   unsigned int mr1;
-   unsigned int mr2;
-   unsigned int dtcr;
-   unsigned int pgcr2;
-   unsigned int zq0cr1;
-   unsigned int zq1cr1;
-   unsigned int zq2cr1;
-   unsigned int pir_v1;
-   unsigned int pir_v2;
-};
-
-struct ddr3_emif_config {
-   unsigned int sdcfg;
-   unsigned int sdtim1;
-   unsigned int sdtim2;
-   unsigned int sdtim3;
-   unsigned int sdtim4;
-   unsigned int zqcfg;
-   unsigned int sdrfc;
-};
-
 #endif
 
 #defineBIT(x)  (1  (x))
@@ -149,9 +113,6 @@ static inline int cpu_revision(void)
 
 void share_all_segments(int priv_id);
 int cpu_to_bus(u32 *ptr, u32 length);
-void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
-void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
-void init_ddr3(void);
 void sdelay(unsigned long);
 
 #endif
diff --git a/board/ti/k2hk_evm/board.c b/board/ti/k2hk_evm/board.c
index ef90f9d..f910ebe 100644
--- a/board/ti/k2hk_evm/board.c
+++ b/board/ti/k2hk_evm/board.c
@@ -12,6 +12,7 @@
 #include fdt_support.h
 #include libfdt.h
 
+#include asm/arch/ddr3.h
 #include asm/arch/hardware.h
 

[U-Boot] [[U-boot] [Patch 3/6] keystone2: ddr: add DDR3 PHY configs updated for PG 2.0

[Ivan Khoronzhuk]

From: Hao Zhang hzh...@ti.com

Add DDR3 PHY configs updated for PG 2.0
Also add DDR3A PHY reset before init for PG2.0 SoCs.

Acked-by: Murali Karicheri m-mariche...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
 arch/arm/cpu/armv7/keystone/ddr3.c| 19 +++
 arch/arm/include/asm/arch-keystone/ddr3.h |  1 +
 arch/arm/include/asm/arch-keystone/hardware.h |  2 +
 board/ti/k2hk_evm/ddr3.c  | 80 ++-
 4 files changed, 100 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c 
b/arch/arm/cpu/armv7/keystone/ddr3.c
index bb16551..b711b81 100644
--- a/arch/arm/cpu/armv7/keystone/ddr3.c
+++ b/arch/arm/cpu/armv7/keystone/ddr3.c
@@ -8,6 +8,7 @@
  */
 
 #include asm/io.h
+#include common.h
 #include asm/arch/ddr3.h
 
 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
@@ -67,3 +68,21 @@ void ddr3_init_ddremif(u32 base, struct ddr3_emif_config 
*emif_cfg)
__raw_writel(emif_cfg-zqcfg,  base + KS2_DDR3_ZQCFG_OFFSET);
__raw_writel(emif_cfg-sdrfc,  base + KS2_DDR3_SDRFC_OFFSET);
 }
+
+void ddr3_reset_ddrphy(void)
+{
+   u32 tmp;
+
+   /* Assert DDR3A  PHY reset */
+   tmp = readl(K2HK_DDR3APLLCTL1);
+   tmp |= KS2_DDR3_PLLCTRL_PHY_RESET;
+   writel(tmp, K2HK_DDR3APLLCTL1);
+
+   /* wait 10us to catch the reset */
+   udelay(10);
+
+   /* Release DDR3A PHY reset */
+   tmp = readl(K2HK_DDR3APLLCTL1);
+   tmp = ~KS2_DDR3_PLLCTRL_PHY_RESET;
+   __raw_writel(tmp, K2HK_DDR3APLLCTL1);
+}
diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h 
b/arch/arm/include/asm/arch-keystone/ddr3.h
index 05b7e29..4d229a2 100644
--- a/arch/arm/include/asm/arch-keystone/ddr3.h
+++ b/arch/arm/include/asm/arch-keystone/ddr3.h
@@ -49,6 +49,7 @@ struct ddr3_emif_config {
 };
 
 void ddr3_init(void);
+void ddr3_reset_ddrphy(void);
 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
 void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
 
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h 
b/arch/arm/include/asm/arch-keystone/hardware.h
index f8f986c..db2d36b 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -80,6 +80,8 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_DDR3_PMCTL_OFFSET   0x38
 #define KS2_DDR3_ZQCFG_OFFSET   0xC8
 
+#define KS2_DDR3_PLLCTRL_PHY_RESET 0x8000
+
 #define KS2_UART0_BASE 0x02530c00
 #define KS2_UART1_BASE 0x02531000
 
diff --git a/board/ti/k2hk_evm/ddr3.c b/board/ti/k2hk_evm/ddr3.c
index 0085f29..b604266 100644
--- a/board/ti/k2hk_evm/ddr3.c
+++ b/board/ti/k2hk_evm/ddr3.c
@@ -188,6 +188,61 @@ static struct ddr3_phy_config ddr3phy_1333_64 = {
.pir_v2 = 0xFF81ul,
 };
 /**/
+
+/* DDR PHY Configs Updated for PG 2.0
+ * zq0,1,2cr1 are updated for PG 2.0 specific configs *_pg2 */
+static struct ddr3_phy_config ddr3phy_1600_64A_pg2 = {
+   .pllcr  = 0x0001C000ul,
+   .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+   .pgcr1_val  = ((1  2) | (1  7) | (1  23)),
+   .ptr0   = 0x42C21590ul,
+   .ptr1   = 0xD05612C0ul,
+   .ptr2   = 0, /* not set in gel */
+   .ptr3   = 0x0D861A80ul,
+   .ptr4   = 0x0C827100ul,
+   .dcr_mask   = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+   .dcr_val= ((1  10)),
+   .dtpr0  = 0xA19DBB66ul,
+   .dtpr1  = 0x32868300ul,
+   .dtpr2  = 0x50035200ul,
+   .mr0= 0x1C70ul,
+   .mr1= 0x0006ul,
+   .mr2= 0x0018ul,
+   .dtcr   = 0x730035C7ul,
+   .pgcr2  = 0x00F07A12ul,
+   .zq0cr1 = 0x0001005Dul,
+   .zq1cr1 = 0x0001005Bul,
+   .zq2cr1 = 0x0001005Bul,
+   .pir_v1 = 0x0033ul,
+   .pir_v2 = 0xFF81ul,
+};
+
+static struct ddr3_phy_config ddr3phy_1333_64A_pg2 = {
+   .pllcr  = 0x0005C000ul,
+   .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+   .pgcr1_val  = ((1  2) | (1  7) | (1  23)),
+   .ptr0   = 0x42C21590ul,
+   .ptr1   = 0xD05612C0ul,
+   .ptr2   = 0, /* not set in gel */
+   .ptr3   = 0x0B4515C2ul,
+   .ptr4   = 0x0A6E08B4ul,
+   .dcr_mask   = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+   .dcr_val= ((1  10)),
+   .dtpr0  = 0x8558AA55ul,
+   .dtpr1  = 0x32857280ul,
+   .dtpr2  = 0x5002C200ul,
+   .mr0= 0x1A60ul,
+   .mr1= 0x0006ul,
+   .mr2= 0x0010ul,
+   .dtcr   = 0x710035C7ul,
+   .pgcr2  = 0x00F065B8ul,
+   .zq0cr1 = 0x0001005Dul,
+   

[U-Boot] [[U-boot] [Patch 0/6] Optimize Keystone2 code for other SoC types

[Ivan Khoronzhuk]

Optimize Keystone2 code. The Keystone2 code is going to be updated
to support several SoC types. Before adding new SoC type it's good
to add some general optimizations in order to avoid re patching
after. So this series holds the optimizations.

Based on [U-boot] [Patch v2 0/3] Add support for NAND U-boot image upgrade
https://www.mail-archive.com/u-boot@lists.denx.de/msg141655.html

Hao Zhang (3):
  keystone2: ddr: add DDR3 PHY configs updated for PG 2.0
  keystone2: move cpu_to_bus() to keystone.c
  keystone2: add possibility to turn off all dsps

Ivan Khoronzhuk (3):
  ARM: keystone2: psc: use common PSC base
  keystone: ddr3: add ddr3.h to hold ddr3 API
  ARM: keystone2: keystone_nav: make it dependent on keystone driver

 arch/arm/cpu/armv7/keystone/Makefile   |   3 +-
 arch/arm/cpu/armv7/keystone/ddr3.c |  25 -
 arch/arm/cpu/armv7/keystone/keystone.c |  87 +
 arch/arm/cpu/armv7/keystone/psc.c  |  42 -
 arch/arm/include/asm/arch-keystone/ddr3.h  |  56 +++
 arch/arm/include/asm/arch-keystone/hardware-k2hk.h |   6 +-
 arch/arm/include/asm/arch-keystone/hardware.h  |  50 +++---
 arch/arm/include/asm/arch-keystone/mon.h   |  15 +++
 board/ti/k2hk_evm/board.c  |  17 +---
 board/ti/k2hk_evm/ddr3.c   | 103 ++---
 10 files changed, 309 insertions(+), 95 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/keystone/keystone.c
 create mode 100644 arch/arm/include/asm/arch-keystone/ddr3.h
 create mode 100644 arch/arm/include/asm/arch-keystone/mon.h

-- 
1.8.3.2

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[U-Boot] [[U-boot] [Patch 4/6] ARM: keystone2: keystone_nav: make it dependent on keystone driver

[Ivan Khoronzhuk]

This driver is needed in case if keystone driver is used.
Currently only keystone_net driver uses it. So to avoid
redundant code compilation make the keystone_nav dependent
on keystone net driver. It also leads to compilation errors
for boards that does't use it.

Acked-by: Murali Karicheri m-kariche...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
 arch/arm/cpu/armv7/keystone/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/keystone/Makefile 
b/arch/arm/cpu/armv7/keystone/Makefile
index c4af252..02ecf7e 100644
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ b/arch/arm/cpu/armv7/keystone/Makefile
@@ -10,7 +10,7 @@ obj-y += psc.o
 obj-y  += clock.o
 obj-y  += cmd_clock.o
 obj-y  += cmd_mon.o
-obj-y  += keystone_nav.o
+obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o
 obj-y  += msmc.o
 obj-$(CONFIG_SPL_BUILD)+= spl.o
 obj-y  += ddr3.o
-- 
1.8.3.2

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[U-Boot] [[U-boot] [Patch 6/6] keystone2: add possibility to turn off all dsps

[Ivan Khoronzhuk]

From: Hao Zhang hzh...@ti.com

By default all DSPs are turned off, for another case option
to turn off them is added in this commit.
Also add command to turn off itself.

Acked-by: Murali Karicheri m-mariche...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
 arch/arm/cpu/armv7/keystone/keystone.c | 59 ++
 arch/arm/include/asm/arch-keystone/hardware-k2hk.h |  5 +-
 arch/arm/include/asm/arch-keystone/hardware.h  |  6 +++
 arch/arm/include/asm/arch-keystone/mon.h   | 15 ++
 4 files changed, 83 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-keystone/mon.h

diff --git a/arch/arm/cpu/armv7/keystone/keystone.c 
b/arch/arm/cpu/armv7/keystone/keystone.c
index 48c8690..1c8c038 100644
--- a/arch/arm/cpu/armv7/keystone/keystone.c
+++ b/arch/arm/cpu/armv7/keystone/keystone.c
@@ -9,6 +9,9 @@
 
 #include common.h
 #include asm/io.h
+#include asm/arch/mon.h
+#include asm/arch/psc_defs.h
+#include asm/arch/hardware.h
 #include asm/arch/hardware.h
 
 /**
@@ -26,3 +29,59 @@ int cpu_to_bus(u32 *ptr, u32 length)
 
return 0;
 }
+
+static int turn_off_myself(void)
+{
+   printf(Turning off ourselves\r\n);
+   mon_power_off(0);
+
+   psc_disable_module(KS2_LPSC_TETRIS);
+   psc_disable_domain(KS2_TETRIS_PWR_DOMAIN);
+
+   asm volatile (isb\n
+ dsb\n
+ wfi\n);
+
+   printf(What! Should not see that\n);
+   return 0;
+}
+
+static void turn_off_all_dsps(int num_dsps)
+{
+   int i;
+
+   for (i = 0; i  num_dsps; i++) {
+   if (psc_disable_module(i + KS2_LPSC_GEM_0))
+   printf(Cannot disable module for #%d DSP, i);
+
+   if (psc_disable_domain(i + 8))
+   printf(Cannot disable domain for #%d DSP, i);
+   }
+}
+
+int do_killme_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+   return turn_off_myself();
+}
+
+U_BOOT_CMD(
+   killme, 1,  0,  do_killme_cmd,
+   turn off main ARM core,
+   turn off main ARM core. Should not live after that :(\n
+);
+
+int misc_init_r(void)
+{
+   char *env;
+   long ks2_debug = 0;
+
+   env = getenv(ks2_debug);
+
+   if (env)
+   ks2_debug = simple_strtol(env, NULL, 0);
+
+   if ((ks2_debug  DBG_LEAVE_DSPS_ON) == 0)
+   turn_off_all_dsps(KS2_NUM_DSPS);
+
+   return 0;
+}
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h 
b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
index 2cac633..5e2f659 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
@@ -68,7 +68,6 @@
 #define K2HK_LPSC_VUSR012
 #define K2HK_LPSC_CHIP_SRSS13
 #define K2HK_LPSC_MSMC 14
-#define K2HK_LPSC_GEM_015
 #define K2HK_LPSC_GEM_116
 #define K2HK_LPSC_GEM_217
 #define K2HK_LPSC_GEM_318
@@ -105,7 +104,6 @@
 #define K2HK_LPSC_VUSR149
 #define K2HK_LPSC_XGE  50
 #define K2HK_LPSC_ARM_SREFLEX  51
-#define K2HK_LPSC_TETRIS   52
 
 /* DDR3A definitions */
 #define K2HK_DDR3A_EMIF_CTRL_BASE  0x2101
@@ -137,4 +135,7 @@
 /* MSMC control */
 #define K2HK_MSMC_CTRL_BASE 0x0bc0
 
+/* Number of DSP cores */
+#define KS2_NUM_DSPS   8
+
 #endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h 
b/arch/arm/include/asm/arch-keystone/hardware.h
index db2d36b..0dcc31a 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -87,11 +87,17 @@ typedef volatile unsigned int   *dv_reg_p;
 
 /* PSC */
 #define KS2_PSC_BASE   0x0235
+#define KS2_LPSC_GEM_0 15
+#define KS2_LPSC_TETRIS52
+#define KS2_TETRIS_PWR_DOMAIN  31
 
 /* AEMIF */
 #define KS2_AEMIF_CNTRL_BASE   0x21000a00
 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE   KS2_AEMIF_CNTRL_BASE
 
+/* Flag from ks2_debug options to check if DSPs need to stay ON */
+#define DBG_LEAVE_DSPS_ON  0x1
+
 #ifdef CONFIG_SOC_K2HK
 #include asm/arch/hardware-k2hk.h
 #endif
diff --git a/arch/arm/include/asm/arch-keystone/mon.h 
b/arch/arm/include/asm/arch-keystone/mon.h
new file mode 100644
index 000..33a2876
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/mon.h
@@ -0,0 +1,15 @@
+/*
+ * K2HK: secure kernel command header file
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _MON_H_
+#define _MON_H_
+
+int mon_power_off(int core_id);
+
+#endif
-- 
1.8.3.2

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[U-Boot] [[U-boot] [Patch 5/6] keystone2: move cpu_to_bus() to keystone.c

[Ivan Khoronzhuk]

From: Hao Zhang hzh...@ti.com

The SoC related common functions in board.c should be placed to
a common keystone.c arch file.

Acked-by: Murali Karicheri m-mariche...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
 arch/arm/cpu/armv7/keystone/Makefile   |  1 +
 arch/arm/cpu/armv7/keystone/keystone.c | 28 
 board/ti/k2hk_evm/board.c  | 14 --
 3 files changed, 29 insertions(+), 14 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/keystone/keystone.c

diff --git a/arch/arm/cpu/armv7/keystone/Makefile 
b/arch/arm/cpu/armv7/keystone/Makefile
index 02ecf7e..64e42a6 100644
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ b/arch/arm/cpu/armv7/keystone/Makefile
@@ -14,3 +14,4 @@ obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o
 obj-y  += msmc.o
 obj-$(CONFIG_SPL_BUILD)+= spl.o
 obj-y  += ddr3.o
+obj-y  += keystone.o
diff --git a/arch/arm/cpu/armv7/keystone/keystone.c 
b/arch/arm/cpu/armv7/keystone/keystone.c
new file mode 100644
index 000..48c8690
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/keystone.c
@@ -0,0 +1,28 @@
+/*
+ * Keystone EVM : Board initialization
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/hardware.h
+
+/**
+ * cpu_to_bus - swap bytes of the 32-bit data if the device is BE
+ * @ptr - array of data
+ * @length - lenght of data array
+ */
+int cpu_to_bus(u32 *ptr, u32 length)
+{
+   u32 i;
+
+   if (!(readl(K2HK_DEVSTAT)  0x1))
+   for (i = 0; i  length; i++, ptr++)
+   *ptr = cpu_to_be32(*ptr);
+
+   return 0;
+}
diff --git a/board/ti/k2hk_evm/board.c b/board/ti/k2hk_evm/board.c
index f910ebe..eb0 100644
--- a/board/ti/k2hk_evm/board.c
+++ b/board/ti/k2hk_evm/board.c
@@ -23,8 +23,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-u32 device_big_endian;
-
 unsigned int external_clk[ext_clk_count] = {
[sys_clk]   =   12288,
[alt_core_clk]  =   12500,
@@ -136,18 +134,6 @@ int board_eth_init(bd_t *bis)
 }
 #endif
 
-/* Byte swap the 32-bit data if the device is BE */
-int cpu_to_bus(u32 *ptr, u32 length)
-{
-   u32 i;
-
-   if (device_big_endian)
-   for (i = 0; i  length; i++, ptr++)
-   *ptr = __swab32(*ptr);
-
-   return 0;
-}
-
 #if defined(CONFIG_BOARD_EARLY_INIT_F)
 int board_early_init_f(void)
 {
-- 
1.8.3.2

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[U-Boot] [U-boot] [Patch v2 0/6] Optimize Keystone2 code for other SoC types

[Ivan Khoronzhuk]

Optimize Keystone2 code. The Keystone2 code is going to be updated
to support several SoC types. Before adding new SoC type it's good
to add some general optimizations in order to avoid re patching
after. So this series holds the optimizations.

Based on [U-boot] [Patch v2 0/3] Add support for NAND U-boot image upgrade
https://www.mail-archive.com/u-boot@lists.denx.de/msg141655.html

v2..v1:
Removed redundant [ in subj.

Hao Zhang (3):
  keystone2: ddr: add DDR3 PHY configs updated for PG 2.0
  keystone2: move cpu_to_bus() to keystone.c
  keystone2: add possibility to turn off all dsps

Ivan Khoronzhuk (3):
  ARM: keystone2: psc: use common PSC base
  keystone: ddr3: add ddr3.h to hold ddr3 API
  ARM: keystone2: keystone_nav: make it dependent on keystone driver

 arch/arm/cpu/armv7/keystone/Makefile   |   3 +-
 arch/arm/cpu/armv7/keystone/ddr3.c |  25 -
 arch/arm/cpu/armv7/keystone/keystone.c |  87 +
 arch/arm/cpu/armv7/keystone/psc.c  |  42 -
 arch/arm/include/asm/arch-keystone/ddr3.h  |  56 +++
 arch/arm/include/asm/arch-keystone/hardware-k2hk.h |   6 +-
 arch/arm/include/asm/arch-keystone/hardware.h  |  50 +++---
 arch/arm/include/asm/arch-keystone/mon.h   |  15 +++
 board/ti/k2hk_evm/board.c  |  17 +---
 board/ti/k2hk_evm/ddr3.c   | 103 ++---
 10 files changed, 309 insertions(+), 95 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/keystone/keystone.c
 create mode 100644 arch/arm/include/asm/arch-keystone/ddr3.h
 create mode 100644 arch/arm/include/asm/arch-keystone/mon.h

-- 
1.8.3.2

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[U-Boot] [U-boot] [Patch v2 3/6] keystone2: ddr: add DDR3 PHY configs updated for PG 2.0

[Ivan Khoronzhuk]

From: Hao Zhang hzh...@ti.com

Add DDR3 PHY configs updated for PG 2.0
Also add DDR3A PHY reset before init for PG2.0 SoCs.

Acked-by: Murali Karicheri m-mariche...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
 arch/arm/cpu/armv7/keystone/ddr3.c| 19 +++
 arch/arm/include/asm/arch-keystone/ddr3.h |  1 +
 arch/arm/include/asm/arch-keystone/hardware.h |  2 +
 board/ti/k2hk_evm/ddr3.c  | 80 ++-
 4 files changed, 100 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c 
b/arch/arm/cpu/armv7/keystone/ddr3.c
index bb16551..b711b81 100644
--- a/arch/arm/cpu/armv7/keystone/ddr3.c
+++ b/arch/arm/cpu/armv7/keystone/ddr3.c
@@ -8,6 +8,7 @@
  */
 
 #include asm/io.h
+#include common.h
 #include asm/arch/ddr3.h
 
 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
@@ -67,3 +68,21 @@ void ddr3_init_ddremif(u32 base, struct ddr3_emif_config 
*emif_cfg)
__raw_writel(emif_cfg-zqcfg,  base + KS2_DDR3_ZQCFG_OFFSET);
__raw_writel(emif_cfg-sdrfc,  base + KS2_DDR3_SDRFC_OFFSET);
 }
+
+void ddr3_reset_ddrphy(void)
+{
+   u32 tmp;
+
+   /* Assert DDR3A  PHY reset */
+   tmp = readl(K2HK_DDR3APLLCTL1);
+   tmp |= KS2_DDR3_PLLCTRL_PHY_RESET;
+   writel(tmp, K2HK_DDR3APLLCTL1);
+
+   /* wait 10us to catch the reset */
+   udelay(10);
+
+   /* Release DDR3A PHY reset */
+   tmp = readl(K2HK_DDR3APLLCTL1);
+   tmp = ~KS2_DDR3_PLLCTRL_PHY_RESET;
+   __raw_writel(tmp, K2HK_DDR3APLLCTL1);
+}
diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h 
b/arch/arm/include/asm/arch-keystone/ddr3.h
index 05b7e29..4d229a2 100644
--- a/arch/arm/include/asm/arch-keystone/ddr3.h
+++ b/arch/arm/include/asm/arch-keystone/ddr3.h
@@ -49,6 +49,7 @@ struct ddr3_emif_config {
 };
 
 void ddr3_init(void);
+void ddr3_reset_ddrphy(void);
 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
 void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
 
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h 
b/arch/arm/include/asm/arch-keystone/hardware.h
index f8f986c..db2d36b 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -80,6 +80,8 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_DDR3_PMCTL_OFFSET   0x38
 #define KS2_DDR3_ZQCFG_OFFSET   0xC8
 
+#define KS2_DDR3_PLLCTRL_PHY_RESET 0x8000
+
 #define KS2_UART0_BASE 0x02530c00
 #define KS2_UART1_BASE 0x02531000
 
diff --git a/board/ti/k2hk_evm/ddr3.c b/board/ti/k2hk_evm/ddr3.c
index 0085f29..b604266 100644
--- a/board/ti/k2hk_evm/ddr3.c
+++ b/board/ti/k2hk_evm/ddr3.c
@@ -188,6 +188,61 @@ static struct ddr3_phy_config ddr3phy_1333_64 = {
.pir_v2 = 0xFF81ul,
 };
 /**/
+
+/* DDR PHY Configs Updated for PG 2.0
+ * zq0,1,2cr1 are updated for PG 2.0 specific configs *_pg2 */
+static struct ddr3_phy_config ddr3phy_1600_64A_pg2 = {
+   .pllcr  = 0x0001C000ul,
+   .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+   .pgcr1_val  = ((1  2) | (1  7) | (1  23)),
+   .ptr0   = 0x42C21590ul,
+   .ptr1   = 0xD05612C0ul,
+   .ptr2   = 0, /* not set in gel */
+   .ptr3   = 0x0D861A80ul,
+   .ptr4   = 0x0C827100ul,
+   .dcr_mask   = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+   .dcr_val= ((1  10)),
+   .dtpr0  = 0xA19DBB66ul,
+   .dtpr1  = 0x32868300ul,
+   .dtpr2  = 0x50035200ul,
+   .mr0= 0x1C70ul,
+   .mr1= 0x0006ul,
+   .mr2= 0x0018ul,
+   .dtcr   = 0x730035C7ul,
+   .pgcr2  = 0x00F07A12ul,
+   .zq0cr1 = 0x0001005Dul,
+   .zq1cr1 = 0x0001005Bul,
+   .zq2cr1 = 0x0001005Bul,
+   .pir_v1 = 0x0033ul,
+   .pir_v2 = 0xFF81ul,
+};
+
+static struct ddr3_phy_config ddr3phy_1333_64A_pg2 = {
+   .pllcr  = 0x0005C000ul,
+   .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+   .pgcr1_val  = ((1  2) | (1  7) | (1  23)),
+   .ptr0   = 0x42C21590ul,
+   .ptr1   = 0xD05612C0ul,
+   .ptr2   = 0, /* not set in gel */
+   .ptr3   = 0x0B4515C2ul,
+   .ptr4   = 0x0A6E08B4ul,
+   .dcr_mask   = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+   .dcr_val= ((1  10)),
+   .dtpr0  = 0x8558AA55ul,
+   .dtpr1  = 0x32857280ul,
+   .dtpr2  = 0x5002C200ul,
+   .mr0= 0x1A60ul,
+   .mr1= 0x0006ul,
+   .mr2= 0x0010ul,
+   .dtcr   = 0x710035C7ul,
+   .pgcr2  = 0x00F065B8ul,
+   .zq0cr1 = 0x0001005Dul,
+   

[U-Boot] [U-boot] [Patch v2 1/6] ARM: keystone2: psc: use common PSC base

[Ivan Khoronzhuk]

Use common keystone2 Power Sleep controller base address instead of
directly deciding which keystone2 SoC is used in psc module.

Acked-by: Murali Karicheri m-kariche...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
 arch/arm/cpu/armv7/keystone/psc.c  | 42 ++
 arch/arm/include/asm/arch-keystone/hardware-k2hk.h |  1 -
 arch/arm/include/asm/arch-keystone/hardware.h  |  3 ++
 3 files changed, 22 insertions(+), 24 deletions(-)

diff --git a/arch/arm/cpu/armv7/keystone/psc.c 
b/arch/arm/cpu/armv7/keystone/psc.c
index c844dc8..fa5422f 100644
--- a/arch/arm/cpu/armv7/keystone/psc.c
+++ b/arch/arm/cpu/armv7/keystone/psc.c
@@ -16,10 +16,6 @@
 #define DEVICE_REG32_R(addr)   __raw_readl((u32 *)(addr))
 #define DEVICE_REG32_W(addr, val)  __raw_writel(val, (u32 *)(addr))
 
-#ifdef CONFIG_SOC_K2HK
-#define DEVICE_PSC_BASEK2HK_PSC_BASE
-#endif
-
 int psc_delay(void)
 {
udelay(10);
@@ -55,7 +51,7 @@ int psc_wait(u32 domain_num)
retry = 0;
 
do {
-   ptstat = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PSTAT);
+   ptstat = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PSTAT);
ptstat = ptstat  (1  domain_num);
} while ((ptstat != 0)  ((retry += psc_delay()) 
 PSC_PTSTAT_TIMEOUT_LIMIT));
@@ -71,7 +67,7 @@ u32 psc_get_domain_num(u32 mod_num)
u32 domain_num;
 
/* Get the power domain associated with the module number */
-   domain_num = DEVICE_REG32_R(DEVICE_PSC_BASE +
+   domain_num = DEVICE_REG32_R(KS2_PSC_BASE +
PSC_REG_MDCFG(mod_num));
domain_num = PSC_REG_MDCFG_GET_PD(domain_num);
 
@@ -106,7 +102,7 @@ int psc_set_state(u32 mod_num, u32 state)
 * Get the power domain associated with the module number, and reset
 * isolation functionality
 */
-   v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
+   v = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
domain_num = PSC_REG_MDCFG_GET_PD(v);
reset_iso  = PSC_REG_MDCFG_GET_RESET_ISO(v);
 
@@ -123,24 +119,24 @@ int psc_set_state(u32 mod_num, u32 state)
 * change is made if the new state is power down.
 */
if (state == PSC_REG_VAL_MDCTL_NEXT_ON) {
-   pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE +
+   pdctl = DEVICE_REG32_R(KS2_PSC_BASE +
   PSC_REG_PDCTL(domain_num));
pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl,
   PSC_REG_VAL_PDCTL_NEXT_ON);
-   DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num),
+   DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num),
   pdctl);
}
 
/* Set the next state for the module to enabled/disabled */
-   mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+   mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state);
mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, reset_iso);
-   DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+   DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
 
/* Trigger the enable */
-   ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
+   ptcmd = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PTCMD);
ptcmd |= (u32)(1domain_num);
-   DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
+   DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PTCMD, ptcmd);
 
/* Wait on the complete */
return psc_wait(domain_num);
@@ -161,7 +157,7 @@ int psc_enable_module(u32 mod_num)
u32 mdctl;
 
/* Set the bit to apply reset */
-   mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+   mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
if ((mdctl  0x3f) == PSC_REG_VAL_MDSTAT_STATE_ON)
return 0;
 
@@ -180,11 +176,11 @@ int psc_disable_module(u32 mod_num)
u32 mdctl;
 
/* Set the bit to apply reset */
-   mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+   mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
if ((mdctl  0x3f) == 0)
return 0;
mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0);
-   DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+   DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
 
return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE);
 }
@@ -203,11 +199,11 @@ int psc_set_reset_iso(u32 mod_num)
u32 mdctl;
 
/* Set the reset isolation bit */
-   mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+   mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = 

[U-Boot] [U-boot] [Patch v2 6/6] keystone2: add possibility to turn off all dsps

[Ivan Khoronzhuk]

From: Hao Zhang hzh...@ti.com

By default all DSPs are turned off, for another case option
to turn off them is added in this commit.
Also add command to turn off itself.

Acked-by: Murali Karicheri m-mariche...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
 arch/arm/cpu/armv7/keystone/keystone.c | 59 ++
 arch/arm/include/asm/arch-keystone/hardware-k2hk.h |  5 +-
 arch/arm/include/asm/arch-keystone/hardware.h  |  6 +++
 arch/arm/include/asm/arch-keystone/mon.h   | 15 ++
 4 files changed, 83 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-keystone/mon.h

diff --git a/arch/arm/cpu/armv7/keystone/keystone.c 
b/arch/arm/cpu/armv7/keystone/keystone.c
index 48c8690..1c8c038 100644
--- a/arch/arm/cpu/armv7/keystone/keystone.c
+++ b/arch/arm/cpu/armv7/keystone/keystone.c
@@ -9,6 +9,9 @@
 
 #include common.h
 #include asm/io.h
+#include asm/arch/mon.h
+#include asm/arch/psc_defs.h
+#include asm/arch/hardware.h
 #include asm/arch/hardware.h
 
 /**
@@ -26,3 +29,59 @@ int cpu_to_bus(u32 *ptr, u32 length)
 
return 0;
 }
+
+static int turn_off_myself(void)
+{
+   printf(Turning off ourselves\r\n);
+   mon_power_off(0);
+
+   psc_disable_module(KS2_LPSC_TETRIS);
+   psc_disable_domain(KS2_TETRIS_PWR_DOMAIN);
+
+   asm volatile (isb\n
+ dsb\n
+ wfi\n);
+
+   printf(What! Should not see that\n);
+   return 0;
+}
+
+static void turn_off_all_dsps(int num_dsps)
+{
+   int i;
+
+   for (i = 0; i  num_dsps; i++) {
+   if (psc_disable_module(i + KS2_LPSC_GEM_0))
+   printf(Cannot disable module for #%d DSP, i);
+
+   if (psc_disable_domain(i + 8))
+   printf(Cannot disable domain for #%d DSP, i);
+   }
+}
+
+int do_killme_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+   return turn_off_myself();
+}
+
+U_BOOT_CMD(
+   killme, 1,  0,  do_killme_cmd,
+   turn off main ARM core,
+   turn off main ARM core. Should not live after that :(\n
+);
+
+int misc_init_r(void)
+{
+   char *env;
+   long ks2_debug = 0;
+
+   env = getenv(ks2_debug);
+
+   if (env)
+   ks2_debug = simple_strtol(env, NULL, 0);
+
+   if ((ks2_debug  DBG_LEAVE_DSPS_ON) == 0)
+   turn_off_all_dsps(KS2_NUM_DSPS);
+
+   return 0;
+}
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h 
b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
index 2cac633..5e2f659 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
@@ -68,7 +68,6 @@
 #define K2HK_LPSC_VUSR012
 #define K2HK_LPSC_CHIP_SRSS13
 #define K2HK_LPSC_MSMC 14
-#define K2HK_LPSC_GEM_015
 #define K2HK_LPSC_GEM_116
 #define K2HK_LPSC_GEM_217
 #define K2HK_LPSC_GEM_318
@@ -105,7 +104,6 @@
 #define K2HK_LPSC_VUSR149
 #define K2HK_LPSC_XGE  50
 #define K2HK_LPSC_ARM_SREFLEX  51
-#define K2HK_LPSC_TETRIS   52
 
 /* DDR3A definitions */
 #define K2HK_DDR3A_EMIF_CTRL_BASE  0x2101
@@ -137,4 +135,7 @@
 /* MSMC control */
 #define K2HK_MSMC_CTRL_BASE 0x0bc0
 
+/* Number of DSP cores */
+#define KS2_NUM_DSPS   8
+
 #endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h 
b/arch/arm/include/asm/arch-keystone/hardware.h
index db2d36b..0dcc31a 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -87,11 +87,17 @@ typedef volatile unsigned int   *dv_reg_p;
 
 /* PSC */
 #define KS2_PSC_BASE   0x0235
+#define KS2_LPSC_GEM_0 15
+#define KS2_LPSC_TETRIS52
+#define KS2_TETRIS_PWR_DOMAIN  31
 
 /* AEMIF */
 #define KS2_AEMIF_CNTRL_BASE   0x21000a00
 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE   KS2_AEMIF_CNTRL_BASE
 
+/* Flag from ks2_debug options to check if DSPs need to stay ON */
+#define DBG_LEAVE_DSPS_ON  0x1
+
 #ifdef CONFIG_SOC_K2HK
 #include asm/arch/hardware-k2hk.h
 #endif
diff --git a/arch/arm/include/asm/arch-keystone/mon.h 
b/arch/arm/include/asm/arch-keystone/mon.h
new file mode 100644
index 000..33a2876
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/mon.h
@@ -0,0 +1,15 @@
+/*
+ * K2HK: secure kernel command header file
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _MON_H_
+#define _MON_H_
+
+int mon_power_off(int core_id);
+
+#endif
-- 
1.8.3.2

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[U-Boot] [U-boot] [Patch v2 5/6] keystone2: move cpu_to_bus() to keystone.c

[Ivan Khoronzhuk]

From: Hao Zhang hzh...@ti.com

The SoC related common functions in board.c should be placed to
a common keystone.c arch file.

Acked-by: Murali Karicheri m-mariche...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
 arch/arm/cpu/armv7/keystone/Makefile   |  1 +
 arch/arm/cpu/armv7/keystone/keystone.c | 28 
 board/ti/k2hk_evm/board.c  | 14 --
 3 files changed, 29 insertions(+), 14 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/keystone/keystone.c

diff --git a/arch/arm/cpu/armv7/keystone/Makefile 
b/arch/arm/cpu/armv7/keystone/Makefile
index 02ecf7e..64e42a6 100644
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ b/arch/arm/cpu/armv7/keystone/Makefile
@@ -14,3 +14,4 @@ obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o
 obj-y  += msmc.o
 obj-$(CONFIG_SPL_BUILD)+= spl.o
 obj-y  += ddr3.o
+obj-y  += keystone.o
diff --git a/arch/arm/cpu/armv7/keystone/keystone.c 
b/arch/arm/cpu/armv7/keystone/keystone.c
new file mode 100644
index 000..48c8690
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/keystone.c
@@ -0,0 +1,28 @@
+/*
+ * Keystone EVM : Board initialization
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/hardware.h
+
+/**
+ * cpu_to_bus - swap bytes of the 32-bit data if the device is BE
+ * @ptr - array of data
+ * @length - lenght of data array
+ */
+int cpu_to_bus(u32 *ptr, u32 length)
+{
+   u32 i;
+
+   if (!(readl(K2HK_DEVSTAT)  0x1))
+   for (i = 0; i  length; i++, ptr++)
+   *ptr = cpu_to_be32(*ptr);
+
+   return 0;
+}
diff --git a/board/ti/k2hk_evm/board.c b/board/ti/k2hk_evm/board.c
index f910ebe..eb0 100644
--- a/board/ti/k2hk_evm/board.c
+++ b/board/ti/k2hk_evm/board.c
@@ -23,8 +23,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-u32 device_big_endian;
-
 unsigned int external_clk[ext_clk_count] = {
[sys_clk]   =   12288,
[alt_core_clk]  =   12500,
@@ -136,18 +134,6 @@ int board_eth_init(bd_t *bis)
 }
 #endif
 
-/* Byte swap the 32-bit data if the device is BE */
-int cpu_to_bus(u32 *ptr, u32 length)
-{
-   u32 i;
-
-   if (device_big_endian)
-   for (i = 0; i  length; i++, ptr++)
-   *ptr = __swab32(*ptr);
-
-   return 0;
-}
-
 #if defined(CONFIG_BOARD_EARLY_INIT_F)
 int board_early_init_f(void)
 {
-- 
1.8.3.2

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[U-Boot] [U-boot] [Patch v2 4/6] ARM: keystone2: keystone_nav: make it dependent on keystone driver

[Ivan Khoronzhuk]

This driver is needed in case if keystone driver is used.
Currently only keystone_net driver uses it. So to avoid
redundant code compilation make the keystone_nav dependent
on keystone net driver. It also leads to compilation errors
for boards that does't use it.

Acked-by: Murali Karicheri m-kariche...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
 arch/arm/cpu/armv7/keystone/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/keystone/Makefile 
b/arch/arm/cpu/armv7/keystone/Makefile
index c4af252..02ecf7e 100644
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ b/arch/arm/cpu/armv7/keystone/Makefile
@@ -10,7 +10,7 @@ obj-y += psc.o
 obj-y  += clock.o
 obj-y  += cmd_clock.o
 obj-y  += cmd_mon.o
-obj-y  += keystone_nav.o
+obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o
 obj-y  += msmc.o
 obj-$(CONFIG_SPL_BUILD)+= spl.o
 obj-y  += ddr3.o
-- 
1.8.3.2

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[U-Boot] [U-boot] [Patch v2 2/6] keystone: ddr3: add ddr3.h to hold ddr3 API

[Ivan Khoronzhuk]

It's convinient to hold ddr3 function definitions in separate file
such as ddr3.h. So move this from hardware.h to ddr3.h.

Acked-by: Murali Karicheri m-kariche...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
 arch/arm/cpu/armv7/keystone/ddr3.c|  6 +--
 arch/arm/include/asm/arch-keystone/ddr3.h | 55 +++
 arch/arm/include/asm/arch-keystone/hardware.h | 39 ---
 board/ti/k2hk_evm/board.c |  3 +-
 board/ti/k2hk_evm/ddr3.c  | 27 +++--
 5 files changed, 76 insertions(+), 54 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-keystone/ddr3.h

diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c 
b/arch/arm/cpu/armv7/keystone/ddr3.c
index 4875db7..bb16551 100644
--- a/arch/arm/cpu/armv7/keystone/ddr3.c
+++ b/arch/arm/cpu/armv7/keystone/ddr3.c
@@ -7,10 +7,10 @@
  * SPDX-License-Identifier: GPL-2.0+
  */
 
-#include asm/arch/hardware.h
 #include asm/io.h
+#include asm/arch/ddr3.h
 
-void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
+void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
 {
unsigned int tmp;
 
@@ -57,7 +57,7 @@ void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
;
 }
 
-void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
+void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
 {
__raw_writel(emif_cfg-sdcfg,  base + KS2_DDR3_SDCFG_OFFSET);
__raw_writel(emif_cfg-sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);
diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h 
b/arch/arm/include/asm/arch-keystone/ddr3.h
new file mode 100644
index 000..05b7e29
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/ddr3.h
@@ -0,0 +1,55 @@
+/*
+ * DDR3
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DDR3_H_
+#define _DDR3_H_
+
+#include asm/arch/hardware.h
+
+struct ddr3_phy_config {
+   unsigned int pllcr;
+   unsigned int pgcr1_mask;
+   unsigned int pgcr1_val;
+   unsigned int ptr0;
+   unsigned int ptr1;
+   unsigned int ptr2;
+   unsigned int ptr3;
+   unsigned int ptr4;
+   unsigned int dcr_mask;
+   unsigned int dcr_val;
+   unsigned int dtpr0;
+   unsigned int dtpr1;
+   unsigned int dtpr2;
+   unsigned int mr0;
+   unsigned int mr1;
+   unsigned int mr2;
+   unsigned int dtcr;
+   unsigned int pgcr2;
+   unsigned int zq0cr1;
+   unsigned int zq1cr1;
+   unsigned int zq2cr1;
+   unsigned int pir_v1;
+   unsigned int pir_v2;
+};
+
+struct ddr3_emif_config {
+   unsigned int sdcfg;
+   unsigned int sdtim1;
+   unsigned int sdtim2;
+   unsigned int sdtim3;
+   unsigned int sdtim4;
+   unsigned int zqcfg;
+   unsigned int sdrfc;
+};
+
+void ddr3_init(void);
+void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
+void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
+
+#endif
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h 
b/arch/arm/include/asm/arch-keystone/hardware.h
index 4e49143..f8f986c 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -22,42 +22,6 @@
 typedef volatile unsigned int   dv_reg;
 typedef volatile unsigned int   *dv_reg_p;
 
-struct ddr3_phy_config {
-   unsigned int pllcr;
-   unsigned int pgcr1_mask;
-   unsigned int pgcr1_val;
-   unsigned int ptr0;
-   unsigned int ptr1;
-   unsigned int ptr2;
-   unsigned int ptr3;
-   unsigned int ptr4;
-   unsigned int dcr_mask;
-   unsigned int dcr_val;
-   unsigned int dtpr0;
-   unsigned int dtpr1;
-   unsigned int dtpr2;
-   unsigned int mr0;
-   unsigned int mr1;
-   unsigned int mr2;
-   unsigned int dtcr;
-   unsigned int pgcr2;
-   unsigned int zq0cr1;
-   unsigned int zq1cr1;
-   unsigned int zq2cr1;
-   unsigned int pir_v1;
-   unsigned int pir_v2;
-};
-
-struct ddr3_emif_config {
-   unsigned int sdcfg;
-   unsigned int sdtim1;
-   unsigned int sdtim2;
-   unsigned int sdtim3;
-   unsigned int sdtim4;
-   unsigned int zqcfg;
-   unsigned int sdrfc;
-};
-
 #endif
 
 #defineBIT(x)  (1  (x))
@@ -149,9 +113,6 @@ static inline int cpu_revision(void)
 
 void share_all_segments(int priv_id);
 int cpu_to_bus(u32 *ptr, u32 length);
-void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
-void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
-void init_ddr3(void);
 void sdelay(unsigned long);
 
 #endif
diff --git a/board/ti/k2hk_evm/board.c b/board/ti/k2hk_evm/board.c
index ef90f9d..f910ebe 100644
--- a/board/ti/k2hk_evm/board.c
+++ b/board/ti/k2hk_evm/board.c
@@ -12,6 +12,7 @@
 #include fdt_support.h
 #include libfdt.h
 
+#include asm/arch/ddr3.h
 #include asm/arch/hardware.h
 

Re: [U-Boot] [PATCH 2/3] ARM: omap: Remove unused arch/arm/cpu/armv7/omap3/mem.c

[Gupta, Pekon]

From: Stefan Roese [mailto:s...@denx.de]
These functions have been merged into the common GPMC init code
with this commit a0a37183 (ARM: omap: merge GPMC initialization code
for all platform). The file is not compiled any more. So remove it
as well.

Signed-off-by: Stefan Roese s...@denx.de
Cc: Pekon Gupta pe...@ti.com
Cc: Tom Rini tr...@ti.com
---
 arch/arm/cpu/armv7/omap3/mem.c | 139 -
 1 file changed, 139 deletions(-)
 delete mode 100644 arch/arm/cpu/armv7/omap3/mem.c

Acked-by: Pekon Gupta pe...@ti.com

This file was removed in original patch, but probably was missed out
because Tom Rini had to manually rebase the patch before applying.

with regards, pekon
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Re: [U-Boot] [U-Boot, v1, 3/3] ARM: omap: merge GPMC initialization code for all platform

[Gupta, Pekon]

From: ashchar...@gmail.com 
On Mon, Jul 7, 2014 at 11:19 PM, Gupta, Pekon pe...@ti.com wrote:
 Sorry seeing this bit late. Were you able to root cause the issue ?
Did you see http://patchwork.ozlabs.org/patch/356984/ ?
This resolves the issue for me but I'd welcome any feedback you have
on this fix.

Thanks for the fix.
Though I don't know why GPMC initialization without any device connected
should cause a hang, that too on kernel side.

with regards, pekon
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Re: [U-Boot] [PATCH 1/3] ARM: omap: Fix GPMC init for OMAP3 platforms

[Gupta, Pekon]

Hi Stefan,

From: Stefan Roese [mailto:s...@denx.de]

Commit a0a37183 (ARM: omap: merge GPMC initialization code for all
platform) broke NAND on OMAP3 based platforms. I noticed this while
testing the latest 2014.07-rc version on the TAO3530 board. NAND
detection did not work with this error message:

NAND:  nand: error: Unable to find NAND settings in GPMC Configuration - 
quitting

As OMAP3 configs don't set CONFIG_NAND but CONFIG_NAND_CMD. the GPMC
was not initialized for NAND at all. This patch now fixes this issue.

Sorry couldn't understand this, why have users enabled CONFIG_NAND_CMD,
if CONFIG_NAND itself is not enabled ?
Otherwise, if TAO3530 board uses the on-die NAND, then it should enable
NAND in its board profile via boards.cfg

Tested on TAO3530 board.


with regards, pekon
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[U-Boot] [PATCH 2/2] mx6sxsabresd: Add PFUZE100 PMIC support

[Fabio Estevam]

From: Fabio Estevam fabio.este...@freescale.com

Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
 board/freescale/mx6sxsabresd/mx6sxsabresd.c | 84 +
 include/configs/mx6sxsabresd.h  | 13 +
 2 files changed, 97 insertions(+)

diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c 
b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index ff4c88f..24d6a51 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -14,10 +14,14 @@
 #include asm/gpio.h
 #include asm/imx-common/iomux-v3.h
 #include asm/io.h
+#include asm/imx-common/mxc_i2c.h
 #include linux/sizes.h
 #include common.h
 #include fsl_esdhc.h
 #include mmc.h
+#include i2c.h
+#include power/pmic.h
+#include power/pfuze100_pmic.h
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -29,6 +33,11 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |   \
PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
+#define I2C_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE |\
+   PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |   \
+   PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
+   PAD_CTL_ODE)
+
 int dram_init(void)
 {
gd-ram_size = PHYS_SDRAM_SIZE;
@@ -56,9 +65,77 @@ static void setup_iomux_uart(void)
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 }
 
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC */
+struct i2c_pads_info i2c_pad_info1 = {
+   .scl = {
+   .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
+   .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
+   .gp = IMX_GPIO_NR(1, 0),
+   },
+   .sda = {
+   .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
+   .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
+   .gp = IMX_GPIO_NR(1, 1),
+   },
+};
+
+static int pfuze_init(void)
+{
+   struct pmic *p;
+   int ret;
+   unsigned int reg;
+
+   ret = power_pfuze100_init(I2C_PMIC);
+   if (ret)
+   return ret;
+
+   p = pmic_get(PFUZE100_PMIC);
+   ret = pmic_probe(p);
+   if (ret)
+   return ret;
+
+   pmic_reg_read(p, PFUZE100_DEVICEID, reg);
+   printf(PMIC:  PFUZE100 ID=0x%02x\n, reg);
+
+   /* Set SW1AB standby voltage to 0.975V */
+   pmic_reg_read(p, PFUZE100_SW1ABSTBY, reg);
+   reg = ~0x3f;
+   reg |= 0x1b;
+   pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
+
+   /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+   pmic_reg_read(p, PUZE_100_SW1ABCONF, reg);
+   reg = ~0xc0;
+   reg |= 0x40;
+   pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
+
+   /* Set SW1C standby voltage to 0.975V */
+   pmic_reg_read(p, PFUZE100_SW1CSTBY, reg);
+   reg = ~0x3f;
+   reg |= 0x1b;
+   pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
+
+   /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+   pmic_reg_read(p, PFUZE100_SW1CCONF, reg);
+   reg = ~0xc0;
+   reg |= 0x40;
+   pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
+
+   /* Enable power of VGEN5 3V3, needed for SD3 */
+   pmic_reg_read(p, PFUZE100_VGEN5VOL, reg);
+   reg = ~0x1F;
+   reg |= 0x1F;
+   pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
+
+   return 0;
+}
+
 int board_early_init_f(void)
 {
setup_iomux_uart();
+   setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, i2c_pad_info1);
+
return 0;
 }
 
@@ -87,6 +164,13 @@ int board_init(void)
return 0;
 }
 
+int board_late_init(void)
+{
+   pfuze_init();
+
+   return 0;
+}
+
 int checkboard(void)
 {
puts(Board: MX6SX SABRE SDB\n);
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 390286b..7967b5d 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -28,6 +28,7 @@
 #define CONFIG_SYS_MALLOC_LEN  (3 * SZ_1M)
 
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
 #define CONFIG_MXC_GPIO
 
 #define CONFIG_MXC_UART
@@ -168,6 +169,18 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED 10
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH
 
-- 
1.8.3.2

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[U-Boot] [PATCH 1/2] mx6: soc: Do not apply the PFD erratum for mx6solox

[Fabio Estevam]

From: Fabio Estevam fabio.este...@freescale.com

The PFD issue is not present on mx6solox, so skip it in this case.

Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
 arch/arm/cpu/armv7/mx6/soc.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index e394e3f..5d96332 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -338,6 +338,10 @@ void s_init(void)
u32 mask480;
u32 mask528;
 
+
+   if (is_cpu_type(MXC_CPU_MX6SX))
+   return;
+
/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
 * to make sure PFD is working right, otherwise, PFDs may
 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
-- 
1.8.3.2

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Re: [U-Boot] [PATCH v2 2/2] usb: phy: omap_usb_phy: implement usb_phy_power() for AM437x

[Marek Vasut]

On Wednesday, July 09, 2014 at 02:48:55 PM, Michael Trimarchi wrote:
 Hi Tom
 
 On Wed, Jul 9, 2014 at 2:41 PM, Tom Rini tr...@ti.com wrote:
  On Mon, Jul 07, 2014 at 08:08:29PM +0200, Marek Vasut wrote:
  On Monday, July 07, 2014 at 06:14:23 PM, Felipe Balbi wrote:
   hi,
   
   On Mon, Jun 23, 2014 at 05:18:24PM -0500, Felipe Balbi wrote:
Newer AM437x silicon requires us to explicitly power up
the USB2 PHY. By implementing usb_phy_power() we can
achieve that.

Signed-off-by: Felipe Balbi ba...@ti.com
---

Changes since v1:
  - add macros for USB1_CTRL register and bits
   
   same here. Still pending, am437x will remain broken until this is
   applied.
  
  What do you need for .07, this and 1/2 of this series ? Or did I miss
  something else?
  
  In any case, sorry, will apply them once I know which ones.
  
  Yes, 1/2 and 2/2 are the missing USB bits..
 
 Marek comment out about using clrbits and setbits. So it's better
 to resend them

Wasn't this fixed in the V2 ?

Best regards,
Marek Vasut
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[U-Boot] [PATCH] i.MX6DL/S: add drive-strength back to pads DISP0_DAT2/DAT10

[Eric Nelson]

The pad settings for DISP0_DATA02 and DISP0_DAT10 were not
set in the same way as DISP0_DAT00-23, causing much flicker
in parallel RGB displays on Dual-Lite and Solo processors.

These settings now match the i.MX6 Dual and Quad core versions.

Note that this fixes a regression in commit b47abc3 and that
this is the second time we've had a regression on these two
pads (See commit e654ddf).

Signed-off-by: Eric Nelson eric.nel...@boundarydevices.com
---
 arch/arm/include/asm/arch-mx6/mx6dl_pins.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h 
b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
index 2e414ad..1a9604e 100644
--- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
@@ -158,7 +158,7 @@ MX6_PAD_DECL(DISP0_DAT1__IPU1_DISP0_DATA01, 0x03C8, 0x00B4, 
0, 0x, 0, PAD_CT
 MX6_PAD_DECL(DISP0_DAT1__LCD_DATA01,   0x03C8, 0x00B4, 1, 0x, 0, 0)
 MX6_PAD_DECL(DISP0_DAT1__ECSPI3_MOSI,  0x03C8, 0x00B4, 2, 0x, 0, 0)
 MX6_PAD_DECL(DISP0_DAT1__GPIO4_IO22,   0x03C8, 0x00B4, 5, 0x, 0, 0)
-MX6_PAD_DECL(DISP0_DAT10__IPU1_DISP0_DATA10,   0x03CC, 0x00B8, 0, 0x, 0, 0)
+MX6_PAD_DECL(DISP0_DAT10__IPU1_DISP0_DATA10,   0x03CC, 0x00B8, 0, 0x, 0, 
PAD_CTL_DSE_120ohm)
 MX6_PAD_DECL(DISP0_DAT10__LCD_DATA10,  0x03CC, 0x00B8, 1, 0x, 0, 
PAD_CTL_DSE_120ohm)
 MX6_PAD_DECL(DISP0_DAT10__GPIO4_IO31,  0x03CC, 0x00B8, 5, 0x, 0, 0)
 MX6_PAD_DECL(DISP0_DAT11__IPU1_DISP0_DATA11,   0x03D0, 0x00BC, 0, 0x, 0, 
PAD_CTL_DSE_120ohm)
@@ -206,7 +206,7 @@ MX6_PAD_DECL(DISP0_DAT19__AUD5_RXD, 0x03F0, 0x00DC, 3, 
0x07B0, 0, 0)
 MX6_PAD_DECL(DISP0_DAT19__AUD4_RXC,0x03F0, 0x00DC, 4, 0x07A0, 0, 0)
 MX6_PAD_DECL(DISP0_DAT19__GPIO5_IO13,  0x03F0, 0x00DC, 5, 0x, 0, 0)
 MX6_PAD_DECL(DISP0_DAT19__EIM_CS3_B,   0x03F0, 0x00DC, 7, 0x, 0, 0)
-MX6_PAD_DECL(DISP0_DAT2__IPU1_DISP0_DATA02,0x03F4, 0x00E0, 0, 0x, 0, 0)
+MX6_PAD_DECL(DISP0_DAT2__IPU1_DISP0_DATA02,0x03F4, 0x00E0, 0, 0x, 0, 
PAD_CTL_DSE_120ohm)
 MX6_PAD_DECL(DISP0_DAT2__LCD_DATA02,   0x03F4, 0x00E0, 1, 0x, 0, 0)
 MX6_PAD_DECL(DISP0_DAT2__ECSPI3_MISO,  0x03F4, 0x00E0, 2, 0x, 0, 0)
 MX6_PAD_DECL(DISP0_DAT2__GPIO4_IO23,   0x03F4, 0x00E0, 5, 0x, 0, 0)
-- 
1.9.1

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Re: [U-Boot] [PATCH] i.MX6DL/S: add drive-strength back to pads DISP0_DAT2/DAT10

[Otavio Salvador]

On Wed, Jul 9, 2014 at 4:27 PM, Eric Nelson
eric.nel...@boundarydevices.com wrote:
 The pad settings for DISP0_DATA02 and DISP0_DAT10 were not
 set in the same way as DISP0_DAT00-23, causing much flicker
 in parallel RGB displays on Dual-Lite and Solo processors.

 These settings now match the i.MX6 Dual and Quad core versions.

 Note that this fixes a regression in commit b47abc3 and that
 this is the second time we've had a regression on these two
 pads (See commit e654ddf).

 Signed-off-by: Eric Nelson eric.nel...@boundarydevices.com

Acked-by: Otavio Salvador ota...@ossystems.com.br

Stephano, can it be included in the upcoming release?

-- 
Otavio Salvador O.S. Systems
http://www.ossystems.com.brhttp://code.ossystems.com.br
Mobile: +55 (53) 9981-7854Mobile: +1 (347) 903-9750
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[U-Boot] [PULL] u-boot/master

[Marek Vasut]

Please apply for 2014.07:

The following changes since commit bc9a78acd40cf9bc7017639e8d4aec889b66e7ee:

  doc: Add zynq fragment to git-mailrc file (2014-07-09 10:45:15 -0400)

are available in the git repository at:

  git://git.denx.de/u-boot-usb.git HEAD

for you to fetch changes up to 5ba95541b700d2edecb4d97d4b905f51ed8551b3:

  usb: phy: omap_usb_phy: implement usb_phy_power() for AM437x (2014-07-09 
22:11:51 +0200)


Felipe Balbi (2):
  usb: host: xhci: make sure to power up PHY
  usb: phy: omap_usb_phy: implement usb_phy_power() for AM437x

 arch/arm/include/asm/arch-am33xx/hardware_am43xx.h |  5 +
 drivers/usb/host/xhci-omap.c   |  1 +
 drivers/usb/phy/omap_usb_phy.c | 17 -
 3 files changed, 22 insertions(+), 1 deletion(-)   
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[U-Boot] [PATCH] Fix help text of ext2load and fatload.

[Pavel Machek]

Fix help text of ext2load and fatload to match code in fs/fs.c

Signed-off-by: Pavel Machek pa...@denx.de

diff --git a/common/cmd_ext2.c b/common/cmd_ext2.c
index 5a4bcc1..2675ae8 100644
--- a/common/cmd_ext2.c
+++ b/common/cmd_ext2.c
@@ -45,7 +45,7 @@ U_BOOT_CMD(
 U_BOOT_CMD(
ext2load,   6,  0,  do_ext2load,
load binary file from a Ext2 filesystem,
-   interface dev[:part] [addr] [filename] [bytes]\n
+   interface [dev[:part] [addr [filename [bytes [pos]\n
- load binary file 'filename' from 'dev' on 'interface'\n
  to address 'addr' from ext2 filesystem.
 );
diff --git a/common/cmd_fat.c b/common/cmd_fat.c
index a12d8fa..b7e743a 100644
--- a/common/cmd_fat.c
+++ b/common/cmd_fat.c
@@ -26,7 +26,7 @@ int do_fat_fsload (cmd_tbl_t *cmdtp, int flag, int argc, char 
* const argv[])
 U_BOOT_CMD(
fatload,7,  0,  do_fat_fsload,
load binary file from a dos filesystem,
-   interface [dev[:part]]  addr filename [bytes [pos]]\n
+   interface [dev[:part] [addr [filename [bytes [pos]\n
- Load binary file 'filename' from 'dev' on 'interface'\n
  to address 'addr' from dos filesystem.\n
  'pos' gives the file position to start loading from.\n

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[U-Boot] [PATCH] catch wrong load address passed to fatload / ext2load

[Pavel Machek]

If filename is passed instead of address to ext2load or fatload,
u-boot silently accepts that, and uses 0 for load address and default
filename from environment. That is confusing, display help instead.

Signed-off-by: Pavel Machek pa...@denx.de

diff --git a/fs/fs.c b/fs/fs.c
index 79d432d..ea15c5f 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -276,6 +276,7 @@ int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[],
unsigned long pos;
int len_read;
unsigned long time;
+   char *ep;
 
if (argc  2)
return CMD_RET_USAGE;
@@ -286,7 +287,9 @@ int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[],
return 1;
 
if (argc = 4) {
-   addr = simple_strtoul(argv[3], NULL, 16);
+   addr = simple_strtoul(argv[3], ep, 16);
+   if (ep == argv[3] || *ep != '\0')
+   return CMD_RET_USAGE;
} else {
addr_str = getenv(loadaddr);
if (addr_str != NULL)

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[U-Boot] [U-boot] [Patch 0/6] Generalize Keystone2 code for other SoC types

[Ivan Khoronzhuk]

In order to be able to correctly add another Keysotne2 SoC type we
need to make some preparation changes to the sources. So generalize
Keystone2 code for other SoC types, in particular for Keystone 2
Edison (k2e) SoC. It's needed to add support for Keystone2 k2e_evm
evaluation board, so add some preparation in board files too.

Based on Optimize keystone2 code for other SoC types series.
http://www.mail-archive.com/u-boot@lists.denx.de/msg141989.html

Hao Zhang (3):
  ARM: keystone2: move K2HK board files to common KS2 board directory
  configs: k2hk_evm: config: add common EVM configuration header
  keystone: ddr3: move K2HK DDR3 configuration to a common file

Ivan Khoronzhuk (2):
  k2hk: use common KS2_ prefix for all hardware definitions
  ARM: keystone: clock: move K2HK SoC dependent code in separate file

Murali Karicheri (1):
  keystone2: add env option to do unitrd dt fixup

 arch/arm/cpu/armv7/keystone/Makefile   |   1 +
 arch/arm/cpu/armv7/keystone/clock-k2hk.c   | 113 +++
 arch/arm/cpu/armv7/keystone/clock.c| 152 ++---
 arch/arm/cpu/armv7/keystone/ddr3.c |   8 +-
 arch/arm/cpu/armv7/keystone/init.c |   4 +-
 arch/arm/cpu/armv7/keystone/keystone.c |   2 +-
 arch/arm/cpu/armv7/keystone/msmc.c |   2 +-
 arch/arm/include/asm/arch-keystone/clock-k2hk.h|  23 +-
 arch/arm/include/asm/arch-keystone/clock.h |  28 ++
 arch/arm/include/asm/arch-keystone/clock_defs.h|   2 +-
 arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 202 ++--
 arch/arm/include/asm/arch-keystone/hardware.h  |   4 +-
 board/ti/k2hk_evm/Makefile |   9 -
 board/ti/k2hk_evm/ddr3.c   | 349 -
 board/ti/ks2_evm/Makefile  |  11 +
 board/ti/{k2hk_evm/README = ks2_evm/README_K2HK}  |   0
 board/ti/{k2hk_evm = ks2_evm}/board.c | 139 +++-
 board/ti/ks2_evm/board.h   |  19 ++
 board/ti/ks2_evm/board_k2hk.c  |  81 +
 board/ti/ks2_evm/ddr3_cfg.c| 130 
 board/ti/ks2_evm/ddr3_cfg.h|  21 ++
 board/ti/ks2_evm/ddr3_k2hk.c   |  84 +
 boards.cfg |   2 +-
 include/configs/k2hk_evm.h | 257 +--
 include/configs/ks2_evm.h  | 275 
 25 files changed, 952 insertions(+), 966 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/keystone/clock-k2hk.c
 delete mode 100644 board/ti/k2hk_evm/Makefile
 delete mode 100644 board/ti/k2hk_evm/ddr3.c
 create mode 100644 board/ti/ks2_evm/Makefile
 rename board/ti/{k2hk_evm/README = ks2_evm/README_K2HK} (100%)
 rename board/ti/{k2hk_evm = ks2_evm}/board.c (68%)
 create mode 100644 board/ti/ks2_evm/board.h
 create mode 100644 board/ti/ks2_evm/board_k2hk.c
 create mode 100644 board/ti/ks2_evm/ddr3_cfg.c
 create mode 100644 board/ti/ks2_evm/ddr3_cfg.h
 create mode 100644 board/ti/ks2_evm/ddr3_k2hk.c
 create mode 100644 include/configs/ks2_evm.h

-- 
1.8.3.2

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[U-Boot] [U-boot] [Patch 2/6] keystone2: add env option to do unitrd dt fixup

[Ivan Khoronzhuk]

From: Murali Karicheri m-kariche...@ti.com

With latest v3.13 kernel, unitrd dt fixup is not needed. However for
older kernel versions such as v3.8/v3.10, it is needed. So to work
with both, add a u-boot env variable that can be set to do dt fixup
for older kernels.

Signed-off-by: Murali Karicheri m-kariche...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
 board/ti/k2hk_evm/board.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/board/ti/k2hk_evm/board.c b/board/ti/k2hk_evm/board.c
index eb0..646ecb3 100644
--- a/board/ti/k2hk_evm/board.c
+++ b/board/ti/k2hk_evm/board.c
@@ -157,11 +157,14 @@ void ft_board_setup(void *blob, bd_t *bd)
u64 size[2];
char name[32], *env, *endp;
int lpae, nodeoffset;
+   int unitrd_fixup = 0;
u32 ddr3a_size;
int nbanks;
 
env = getenv(mem_lpae);
lpae = env  simple_strtol(env, NULL, 0);
+   env = getenv(uinitrd_fixup);
+   unitrd_fixup = env  simple_strtol(env, NULL, 0);
 
ddr3a_size = 0;
if (lpae) {
@@ -204,10 +207,11 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory_banks(blob, start, size, nbanks);
 
/* Fix up the initrd */
-   if (lpae) {
+   if (lpae  unitrd_fixup) {
u64 initrd_start, initrd_end;
u32 *prop1, *prop2;
int err;
+
nodeoffset = fdt_path_offset(blob, /chosen);
if (nodeoffset = 0) {
prop1 = (u32 *)fdt_getprop(blob, nodeoffset,
-- 
1.8.3.2

___
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[U-Boot] [U-boot] [Patch 5/6] configs: k2hk_evm: config: add common EVM configuration header

[Ivan Khoronzhuk]

From: Hao Zhang hzh...@ti.com

This patch adds a common config header file for all the Keystone II
EVM platforms. It combines a lot of general definitions in one file.
The common header included in the EVM should be specific configuration
header.

Acked-by: Murali Karicheri m-kariche...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
 include/configs/k2hk_evm.h | 258 +++---
 include/configs/ks2_evm.h  | 275 +
 2 files changed, 289 insertions(+), 244 deletions(-)
 create mode 100644 include/configs/ks2_evm.h

diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h
index f727882..8aa616d 100644
--- a/include/configs/k2hk_evm.h
+++ b/include/configs/k2hk_evm.h
@@ -14,257 +14,27 @@
 #define CONFIG_SOC_K2HK
 #define CONFIG_K2HK_EVM
 
-/* U-Boot Build Configuration */
-#define CONFIG_SKIP_LOWLEVEL_INIT   /* U-Boot is a 2nd stage loader */
-#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_SYS_THUMB_BUILD
-
-/* SoC Configuration */
-#define CONFIG_ARMV7
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_ARCH_TIMER
-#define CONFIG_SYS_HZ   1000
-#define CONFIG_SYS_TEXT_BASE0x0c001000
-#define CONFIG_SPL_TARGET   u-boot-spi.gph
-#define CONFIG_SYS_DCACHE_OFF
-
-/* Memory Configuration */
-#define CONFIG_NR_DRAM_BANKS2
-#define CONFIG_SYS_SDRAM_BASE   0x8000
-#define CONFIG_SYS_LPAE_SDRAM_BASE  0x8
-#define CONFIG_MAX_RAM_BANK_SIZE(2  30)   /* 2GB */
-#define CONFIG_STACKSIZE(512  10) /* 512 KiB */
-#define CONFIG_SYS_MALLOC_LEN   (4  20)   /* 4 MiB */
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \
-GENERATED_GBL_DATA_SIZE)
-
-/* SPL SPI Loader Configuration */
-#define CONFIG_SPL_TEXT_BASE0x0c20
-#define CONFIG_SPL_PAD_TO   65536
-#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8)
-#define CONFIG_SPL_BSS_START_ADDR   (CONFIG_SPL_TEXT_BASE + \
-CONFIG_SPL_MAX_SIZE)
-#define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024)
-#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
-CONFIG_SPL_BSS_MAX_SIZE)
-#define CONFIG_SYS_SPL_MALLOC_SIZE  (32 * 1024)
-#define CONFIG_SPL_STACK_SIZE   (8 * 1024)
-#define CONFIG_SPL_STACK(CONFIG_SYS_SPL_MALLOC_START + \
-CONFIG_SYS_SPL_MALLOC_SIZE + \
-CONFIG_SPL_STACK_SIZE - 4)
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS  0
-#define CONFIG_SPL_SPI_CS   0
-#define CONFIG_SYS_SPI_U_BOOT_OFFS  CONFIG_SPL_PAD_TO
-#define CONFIG_SPL_FRAMEWORK
-
-/* UART Configuration */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_MEM32
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE
-#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE
-#define CONFIG_SYS_NS16550_CLK  clk_get_rate(KS2_CLK1_6)
-#define CONFIG_CONS_INDEX   1
-#define CONFIG_BAUDRATE 115200
-
-/* SPI Configuration */
-#define CONFIG_SPI
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_DAVINCI_SPI
-#define CONFIG_SYS_SPI0
-#define CONFIG_SYS_SPI_BASE KS2_SPI_BASE
-#define CONFIG_SYS_SPI0_NUM_CS  4
-#define CONFIG_SYS_SPI1
-#define CONFIG_SYS_SPI1_BASEKS2_SPI1_BASE
-#define CONFIG_SYS_SPI1_NUM_CS  4
-#define CONFIG_SYS_SPI2
-#define CONFIG_SYS_SPI2_NUM_CS  4
-#define CONFIG_SYS_SPI2_BASEKS2_SPI2_BASE
-#define CONFIG_CMD_SPI
-#define CONFIG_SYS_SPI_CLK  clk_get_rate(KS2_LPSC_EMIF25_SPI)
-#define CONFIG_SF_DEFAULT_SPEED 3000
-#define CONFIG_ENV_SPI_MAX_HZ   CONFIG_SF_DEFAULT_SPEED
+/* U-Boot general configuration */
+#define CONFIG_SYS_PROMPT   K2HK EVM # 
 
-/* I2C Configuration */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED10
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE0x10 /* SMBus host address */
-#define CONFIG_SYS_DAVINCI_I2C_SPEED1   10
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE1   0x10 /* SMBus host address */
-#define CONFIG_SYS_DAVINCI_I2C_SPEED2   10
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE2   0x10 /* SMBus host address */
-#define I2C_BUS_MAX 3
+#define KS2_ARGS_UBI   

[U-Boot] [U-boot] [Patch 1/6] k2hk: use common KS2_ prefix for all hardware definitions

[Ivan Khoronzhuk]

Use KS2_ prefix in all definitions, for that replace K2HK_ prefix and
add KS2_ prefix where it's needed. It requires to change names also
in places where they're used. Align lines and remove redundant
definitions in kardware-k2hk.h at the same time.

Using common KS2_ prefix helps resolve redundant redefinitions and
adds opportunity to use KS2_ definition across a project not thinking about
what SoC should be used. It's more convenient and we don't need to worry
about the SoC type in common files, hardware.h will think about that.
The hardware.h decides definitions of what SoC to use.

Acked-by: Murali Karicheri m-kariche...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
 arch/arm/cpu/armv7/keystone/clock.c|  24 +--
 arch/arm/cpu/armv7/keystone/ddr3.c |   8 +-
 arch/arm/cpu/armv7/keystone/init.c |   4 +-
 arch/arm/cpu/armv7/keystone/keystone.c |   2 +-
 arch/arm/cpu/armv7/keystone/msmc.c |   2 +-
 arch/arm/include/asm/arch-keystone/clock-k2hk.h|   2 +-
 arch/arm/include/asm/arch-keystone/clock_defs.h|   2 +-
 arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 202 ++---
 arch/arm/include/asm/arch-keystone/hardware.h  |   4 +-
 board/ti/k2hk_evm/ddr3.c   |  24 +--
 include/configs/k2hk_evm.h |  12 +-
 11 files changed, 138 insertions(+), 148 deletions(-)

diff --git a/arch/arm/cpu/armv7/keystone/clock.c 
b/arch/arm/cpu/armv7/keystone/clock.c
index bfa4c9d..f905fdc 100644
--- a/arch/arm/cpu/armv7/keystone/clock.c
+++ b/arch/arm/cpu/armv7/keystone/clock.c
@@ -29,11 +29,11 @@ struct pll_regs {
 };
 
 static const struct pll_regs pll_regs[] = {
-   [CORE_PLL]  = { K2HK_MAINPLLCTL0, K2HK_MAINPLLCTL1},
-   [PASS_PLL]  = { K2HK_PASSPLLCTL0, K2HK_PASSPLLCTL1},
-   [TETRIS_PLL]= { K2HK_ARMPLLCTL0,  K2HK_ARMPLLCTL1},
-   [DDR3A_PLL] = { K2HK_DDR3APLLCTL0, K2HK_DDR3APLLCTL1},
-   [DDR3B_PLL] = { K2HK_DDR3BPLLCTL0, K2HK_DDR3BPLLCTL1},
+   [CORE_PLL]  = { KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+   [PASS_PLL]  = { KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+   [TETRIS_PLL]= { KS2_ARMPLLCTL0,  KS2_ARMPLLCTL1},
+   [DDR3A_PLL] = { KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+   [DDR3B_PLL] = { KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
 };
 
 /* Fout = Fref * NF(mult) / NR(prediv) / OD */
@@ -47,7 +47,7 @@ static unsigned long pll_freq_get(int pll)
ret = external_clk[sys_clk];
if (pllctl_reg_read(pll, ctl)  PLLCTL_PLLEN) {
/* PLL mode */
-   tmp = __raw_readl(K2HK_MAINPLLCTL0);
+   tmp = __raw_readl(KS2_MAINPLLCTL0);
prediv = (tmp  PLL_DIV_MASK) + 1;
mult = (((tmp  PLLM_MULT_HI_SMASK)  6) |
(pllctl_reg_read(pll, mult) 
@@ -61,19 +61,19 @@ static unsigned long pll_freq_get(int pll)
switch (pll) {
case PASS_PLL:
ret = external_clk[pa_clk];
-   reg = K2HK_PASSPLLCTL0;
+   reg = KS2_PASSPLLCTL0;
break;
case TETRIS_PLL:
ret = external_clk[tetris_clk];
-   reg = K2HK_ARMPLLCTL0;
+   reg = KS2_ARMPLLCTL0;
break;
case DDR3A_PLL:
ret = external_clk[ddr3a_clk];
-   reg = K2HK_DDR3APLLCTL0;
+   reg = KS2_DDR3APLLCTL0;
break;
case DDR3B_PLL:
ret = external_clk[ddr3b_clk];
-   reg = K2HK_DDR3BPLLCTL0;
+   reg = KS2_DDR3BPLLCTL0;
break;
default:
return 0;
@@ -214,7 +214,7 @@ void init_pll(const struct pll_init_data *data)
 * Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass)
 * only applicable for Kepler
 */
-   clrbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
+   clrbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
/* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */
setbits_le32(pll_regs[data-pll].reg1 ,
 PLL_PLLRST | PLLCTL_ENSAT);
@@ -255,7 +255,7 @@ void init_pll(const struct pll_init_data *data)
 * 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass)
 * only applicable for Kepler
 */
-   setbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
+   setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
} else {
setbits_le32(pll_regs[data-pll].reg1, PLLCTL_ENSAT);
/*
diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c 
b/arch/arm/cpu/armv7/keystone/ddr3.c
index 

[U-Boot] [U-boot] [Patch 3/6] ARM: keystone2: move K2HK board files to common KS2 board directory

[Ivan Khoronzhuk]

From: Hao Zhang hzh...@ti.com

This patch moves K2HK board directory to a common Keystone II board
directory. The Board related common functions are moved to a common
keystone board file.

Acked-by: Murali Karicheri m-kariche...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
 board/ti/{k2hk_evm = ks2_evm}/Makefile   |   7 +-
 board/ti/{k2hk_evm/README = ks2_evm/README_K2HK} |   0
 board/ti/{k2hk_evm = ks2_evm}/board.c| 135 ++
 board/ti/ks2_evm/board.h  |  19 +++
 board/ti/ks2_evm/board_k2hk.c |  81 +
 board/ti/{k2hk_evm/ddr3.c = ks2_evm/ddr3_k2hk.c} |   0
 boards.cfg|   2 +-
 include/configs/k2hk_evm.h|   1 +
 8 files changed, 142 insertions(+), 103 deletions(-)
 rename board/ti/{k2hk_evm = ks2_evm}/Makefile (50%)
 rename board/ti/{k2hk_evm/README = ks2_evm/README_K2HK} (100%)
 rename board/ti/{k2hk_evm = ks2_evm}/board.c (69%)
 create mode 100644 board/ti/ks2_evm/board.h
 create mode 100644 board/ti/ks2_evm/board_k2hk.c
 rename board/ti/{k2hk_evm/ddr3.c = ks2_evm/ddr3_k2hk.c} (100%)

diff --git a/board/ti/k2hk_evm/Makefile b/board/ti/ks2_evm/Makefile
similarity index 50%
rename from board/ti/k2hk_evm/Makefile
rename to board/ti/ks2_evm/Makefile
index 3645f2f..58d77dc 100644
--- a/board/ti/k2hk_evm/Makefile
+++ b/board/ti/ks2_evm/Makefile
@@ -1,9 +1,10 @@
 #
-# K2HK-EVM: board Makefile
+# KS2-EVM: board Makefile
 # (C) Copyright 2012-2014
 # Texas Instruments Incorporated, www.ti.com
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y  += board.o
-obj-y  += ddr3.o
+obj-y += board.o
+obj-$(CONFIG_K2HK_EVM) += board_k2hk.o
+obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o
diff --git a/board/ti/k2hk_evm/README b/board/ti/ks2_evm/README_K2HK
similarity index 100%
rename from board/ti/k2hk_evm/README
rename to board/ti/ks2_evm/README_K2HK
diff --git a/board/ti/k2hk_evm/board.c b/board/ti/ks2_evm/board.c
similarity index 69%
rename from board/ti/k2hk_evm/board.c
rename to board/ti/ks2_evm/board.c
index 646ecb3..dfe7be6 100644
--- a/board/ti/k2hk_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -1,44 +1,22 @@
 /*
- * K2HK EVM : Board initialization
+ * Keystone : Board initialization
  *
- * (C) Copyright 2012-2014
+ * (C) Copyright 2014
  * Texas Instruments Incorporated, www.ti.com
  *
  * SPDX-License-Identifier: GPL-2.0+
  */
 
+#include board.h
 #include common.h
 #include exports.h
 #include fdt_support.h
-#include libfdt.h
-
 #include asm/arch/ddr3.h
-#include asm/arch/hardware.h
-#include asm/arch/clock.h
-#include asm/io.h
-#include asm/mach-types.h
 #include asm/arch/emac_defs.h
-#include asm/arch/psc_defs.h
 #include asm/ti-common/ti-aemif.h
 
 DECLARE_GLOBAL_DATA_PTR;
 
-unsigned int external_clk[ext_clk_count] = {
-   [sys_clk]   =   12288,
-   [alt_core_clk]  =   12500,
-   [pa_clk]=   12288,
-   [tetris_clk]=   12500,
-   [ddr3a_clk] =   1,
-   [ddr3b_clk] =   1,
-   [mcm_clk]   =   31250,
-   [pcie_clk]  =   1,
-   [sgmii_srio_clk] =  15625,
-   [xgmii_clk] =   15625,
-   [usb_clk]   =   1,
-   [rp1_clk]   =   123456789/* TODO: cannot find
-   what is that */
-};
-
 static struct aemif_config aemif_configs[] = {
{   /* CS0 */
.mode   = AEMIF_MODE_NAND,
@@ -51,13 +29,6 @@ static struct aemif_config aemif_configs[] = {
.turn_around= 3,
.width  = AEMIF_WIDTH_8,
},
-
-};
-
-static struct pll_init_data pll_config[] = {
-   CORE_PLL_1228,
-   PASS_PLL_983,
-   TETRIS_PLL_1200,
 };
 
 int dram_init(void)
@@ -70,42 +41,18 @@ int dram_init(void)
return 0;
 }
 
-#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
-struct eth_priv_t eth_priv_cfg[] = {
-   {
-   .int_name   = K2HK_EMAC,
-   .rx_flow= 22,
-   .phy_addr   = 0,
-   .slave_port = 1,
-   .sgmii_link_type = SGMII_LINK_MAC_PHY,
-   },
-   {
-   .int_name   = K2HK_EMAC1,
-   .rx_flow= 23,
-   .phy_addr   = 1,
-   .slave_port = 2,
-   .sgmii_link_type = SGMII_LINK_MAC_PHY,
-   },
-   {
-   .int_name   = K2HK_EMAC2,
-   .rx_flow= 24,
-   .phy_addr   = 2,
-   .slave_port = 3,
-   .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
-   },
-   {
-   .int_name   = K2HK_EMAC3,
-   .rx_flow= 25,
-   .phy_addr   = 3,
-   .slave_port = 4,
-   .sgmii_link_type = 

[U-Boot] [U-boot] [Patch 6/6] keystone: ddr3: move K2HK DDR3 configuration to a common file

[Ivan Khoronzhuk]

From: Hao Zhang hzh...@ti.com

It's convenient to hold configurations for DDR3 PHY and EMIF in
separate common place. This patch moves K2HK DDR3 PHY and EMIF
configuration data with different rates and memory size to a common
ddr3_cfg.c file.

Acked-by: Murali Karicheri m-kariche...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
 board/ti/ks2_evm/Makefile|   1 +
 board/ti/ks2_evm/ddr3_cfg.c  | 130 ++
 board/ti/ks2_evm/ddr3_cfg.h  |  21 +++
 board/ti/ks2_evm/ddr3_k2hk.c | 305 +++
 4 files changed, 172 insertions(+), 285 deletions(-)
 create mode 100644 board/ti/ks2_evm/ddr3_cfg.c
 create mode 100644 board/ti/ks2_evm/ddr3_cfg.h

diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile
index 58d77dc..774a7d5 100644
--- a/board/ti/ks2_evm/Makefile
+++ b/board/ti/ks2_evm/Makefile
@@ -6,5 +6,6 @@
 #
 
 obj-y += board.o
+obj-y += ddr3_cfg.o
 obj-$(CONFIG_K2HK_EVM) += board_k2hk.o
 obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o
diff --git a/board/ti/ks2_evm/ddr3_cfg.c b/board/ti/ks2_evm/ddr3_cfg.c
new file mode 100644
index 000..6e55af9
--- /dev/null
+++ b/board/ti/ks2_evm/ddr3_cfg.c
@@ -0,0 +1,130 @@
+/*
+ * Keystone2: DDR3 configuration
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+
+#include i2c.h
+#include asm/arch/ddr3.h
+#include asm/arch/hardware.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* DDR3 PHY configuration data with 1600M rate, 8GB size */
+struct ddr3_phy_config ddr3phy_1600_8g = {
+   .pllcr  = 0x0001C000ul,
+   .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+   .pgcr1_val  = ((1  2) | (1  7) | (1  23)),
+   .ptr0   = 0x42C21590ul,
+   .ptr1   = 0xD05612C0ul,
+   .ptr2   = 0, /* not set in gel */
+   .ptr3   = 0x0D861A80ul,
+   .ptr4   = 0x0C827100ul,
+   .dcr_mask   = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+   .dcr_val= ((1  10)),
+   .dtpr0  = 0xA19DBB66ul,
+   .dtpr1  = 0x32868300ul,
+   .dtpr2  = 0x50035200ul,
+   .mr0= 0x1C70ul,
+   .mr1= 0x0006ul,
+   .mr2= 0x0018ul,
+   .dtcr   = 0x730035C7ul,
+   .pgcr2  = 0x00F07A12ul,
+   .zq0cr1 = 0x005Dul,
+   .zq1cr1 = 0x005Bul,
+   .zq2cr1 = 0x005Bul,
+   .pir_v1 = 0x0033ul,
+   .pir_v2 = 0xFF81ul,
+};
+
+/* DDR3 EMIF configuration data with 1600M rate, 8GB size */
+struct ddr3_emif_config ddr3_1600_8g = {
+   .sdcfg  = 0x6200CE6Aul,
+   .sdtim1 = 0x16709C55ul,
+   .sdtim2 = 0x1D4Aul,
+   .sdtim3 = 0x435DFF54ul,
+   .sdtim4 = 0x553F0CFFul,
+   .zqcfg  = 0xF0073200ul,
+   .sdrfc  = 0x1869ul,
+};
+
+#ifdef CONFIG_K2HK_EVM
+/* DDR3 PHY configuration data with 1333M rate, and 2GB size */
+struct ddr3_phy_config ddr3phy_1333_2g = {
+   .pllcr  = 0x0005C000ul,
+   .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+   .pgcr1_val  = ((1  2) | (1  7) | (1  23)),
+   .ptr0   = 0x42C21590ul,
+   .ptr1   = 0xD05612C0ul,
+   .ptr2   = 0, /* not set in gel */
+   .ptr3   = 0x0B4515C2ul,
+   .ptr4   = 0x0A6E08B4ul,
+   .dcr_mask   = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+   .dcr_val= ((1  10)),
+   .dtpr0  = 0x8558AA55ul,
+   .dtpr1  = 0x32857280ul,
+   .dtpr2  = 0x5002C200ul,
+   .mr0= 0x1A60ul,
+   .mr1= 0x0006ul,
+   .mr2= 0x0010ul,
+   .dtcr   = 0x710035C7ul,
+   .pgcr2  = 0x00F065B8ul,
+   .zq0cr1 = 0x005Dul,
+   .zq1cr1 = 0x005Bul,
+   .zq2cr1 = 0x005Bul,
+   .pir_v1 = 0x0033ul,
+   .pir_v2 = 0xFF81ul,
+};
+
+/* DDR3 EMIF configuration data with 1333M rate, and 2GB size */
+struct ddr3_emif_config ddr3_1333_2g = {
+   .sdcfg  = 0x62008C62ul,
+   .sdtim1 = 0x125C8044ul,
+   .sdtim2 = 0x1D29ul,
+   .sdtim3 = 0x32CDFF43ul,
+   .sdtim4 = 0x543F0ADFul,
+   .zqcfg  = 0x70073200ul,
+   .sdrfc  = 0x1457ul,
+};
+#endif
+
+int ddr3_get_dimm_params(char *dimm_name)
+{
+   int ret;
+   int old_bus;
+   u8 spd_params[256];
+
+   i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
+
+   old_bus = i2c_get_bus_num();
+   i2c_set_bus_num(1);
+
+   ret = i2c_read(0x53, 0, 1, spd_params, 256);
+
+   i2c_set_bus_num(old_bus);
+
+   dimm_name[0] = '\0';
+
+   if (ret) {
+   puts(Cannot read DIMM params\n);
+   

Re: [U-Boot] [PATCH] catch wrong load address passed to fatload / ext2load

[Pavel Machek]

Hi!

 If filename is passed instead of address to ext2load or fatload,
 u-boot silently accepts that, and uses 0 for load address and default
 filename from environment. That is confusing, display help instead.
 
 Signed-off-by: Pavel Machek pa...@denx.de

Oops and actually I should warn... this patch is untested. I'm
currently fighting hard to get recent u-boot to run on socfpga.

Pavel

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[U-Boot] [U-boot] [Patch 4/6] ARM: keystone: clock: move K2HK SoC dependent code in separate file

[Ivan Khoronzhuk]

This patch in general spit SoC type clock dependent code and general
clock code. Before adding keystone II Edison k2e SoC which has
slightly different dpll set, move k2hk dependent clock code to
separate clock-k2hk.c file.

Acked-by: Murali Karicheri m-kariche...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
 arch/arm/cpu/armv7/keystone/Makefile|   1 +
 arch/arm/cpu/armv7/keystone/clock-k2hk.c| 113 ++
 arch/arm/cpu/armv7/keystone/clock.c | 148 
 arch/arm/include/asm/arch-keystone/clock-k2hk.h |  21 
 arch/arm/include/asm/arch-keystone/clock.h  |  28 +
 5 files changed, 166 insertions(+), 145 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/keystone/clock-k2hk.c

diff --git a/arch/arm/cpu/armv7/keystone/Makefile 
b/arch/arm/cpu/armv7/keystone/Makefile
index 64e42a6..74c5160 100644
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ b/arch/arm/cpu/armv7/keystone/Makefile
@@ -8,6 +8,7 @@
 obj-y  += init.o
 obj-y  += psc.o
 obj-y  += clock.o
+obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
 obj-y  += cmd_clock.o
 obj-y  += cmd_mon.o
 obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2hk.c 
b/arch/arm/cpu/armv7/keystone/clock-k2hk.c
new file mode 100644
index 000..96a9f72
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/clock-k2hk.c
@@ -0,0 +1,113 @@
+/*
+ * Keystone2: get clk rate for K2HK
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/arch/clock.h
+#include asm/arch/clock_defs.h
+
+const struct keystone_pll_regs keystone_pll_regs[] = {
+   [CORE_PLL]  = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+   [PASS_PLL]  = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+   [TETRIS_PLL]= {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
+   [DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+   [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
+};
+
+/**
+ * pll_freq_get - get pll frequency
+ * Fout = Fref * NF(mult) / NR(prediv) / OD
+ * @pll:   pll identifier
+ */
+static unsigned long pll_freq_get(int pll)
+{
+   unsigned long mult = 1, prediv = 1, output_div = 2;
+   unsigned long ret;
+   u32 tmp, reg;
+
+   if (pll == CORE_PLL) {
+   ret = external_clk[sys_clk];
+   if (pllctl_reg_read(pll, ctl)  PLLCTL_PLLEN) {
+   /* PLL mode */
+   tmp = __raw_readl(KS2_MAINPLLCTL0);
+   prediv = (tmp  PLL_DIV_MASK) + 1;
+   mult = (((tmp  PLLM_MULT_HI_SMASK)  6) |
+   (pllctl_reg_read(pll, mult) 
+PLLM_MULT_LO_MASK)) + 1;
+   output_div = ((pllctl_reg_read(pll, secctl) 
+  PLL_CLKOD_SHIFT)  PLL_CLKOD_MASK) + 1;
+
+   ret = ret / prediv / output_div * mult;
+   }
+   } else {
+   switch (pll) {
+   case PASS_PLL:
+   ret = external_clk[pa_clk];
+   reg = KS2_PASSPLLCTL0;
+   break;
+   case TETRIS_PLL:
+   ret = external_clk[tetris_clk];
+   reg = KS2_ARMPLLCTL0;
+   break;
+   case DDR3A_PLL:
+   ret = external_clk[ddr3a_clk];
+   reg = KS2_DDR3APLLCTL0;
+   break;
+   case DDR3B_PLL:
+   ret = external_clk[ddr3b_clk];
+   reg = KS2_DDR3BPLLCTL0;
+   break;
+   default:
+   return 0;
+   }
+
+   tmp = __raw_readl(reg);
+
+   if (!(tmp  PLLCTL_BYPASS)) {
+   /* Bypass disabled */
+   prediv = (tmp  PLL_DIV_MASK) + 1;
+   mult = ((tmp  PLL_MULT_SHIFT)  PLL_MULT_MASK) + 1;
+   output_div = ((tmp  PLL_CLKOD_SHIFT) 
+ PLL_CLKOD_MASK) + 1;
+   ret = ((ret / prediv) * mult) / output_div;
+   }
+   }
+
+   return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+   switch (clk) {
+   case core_pll_clk:  return pll_freq_get(CORE_PLL);
+   case pass_pll_clk:  return pll_freq_get(PASS_PLL);
+   case tetris_pll_clk:return pll_freq_get(TETRIS_PLL);
+   case ddr3a_pll_clk: return pll_freq_get(DDR3A_PLL);
+   case ddr3b_pll_clk: return pll_freq_get(DDR3B_PLL);
+   case sys_clk0_1_clk:
+   case sys_clk0_clk:  return pll_freq_get(CORE_PLL) / pll0div_read(1);
+   case sys_clk1_clk:  return pll_freq_get(CORE_PLL) / pll0div_read(2);
+   case sys_clk2_clk:  return pll_freq_get(CORE_PLL) / pll0div_read(3);
+  

[U-Boot] [PATCH 2/2] mx6: Adjust the GPR offset for mx6solox

[Fabio Estevam]

From: Fabio Estevam fabio.este...@freescale.com

On mx6solox there is an additional 0x4000 offset for the GPR registers.

Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
This applies against 'next' branch.

 arch/arm/include/asm/arch-mx6/imx-regs.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h 
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 782d9c4..cc746b8 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -398,6 +398,9 @@ struct src {
 
 
 struct iomuxc {
+#ifdef CONFIG_MX6SX
+   u8 reserved[0x4000];
+#endif
u32 gpr[14];
u32 omux[5];
/* mux and pad registers */
-- 
1.8.3.2

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[U-Boot] [PATCH 1/2] mx6: Remove duplication of iomuxc structure

[Fabio Estevam]

From: Fabio Estevam fabio.este...@freescale.com

There is no need to keep iomuxc_base_regs structure as it serves the exact same
purpose of the iomuxc structure, which is to provide access to the GPR 
registers.

The additional fields of iomuxc_base_regs are not used. Other advantage of
'iomuxc' is that it has a shorter name and the variable declarations can fit
into a single line.

So remove iomuxc_base_regs structure and use iomuxc instead.

Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
This applies against 'next' branch.

 arch/arm/imx-common/sata.c | 3 +--
 arch/arm/include/asm/arch-mx6/imx-regs.h   | 9 -
 board/boundary/nitrogen6x/nitrogen6x.c | 3 +--
 board/freescale/mx6slevk/mx6slevk.c| 3 +--
 board/gateworks/gw_ventana/gw_ventana.c| 3 +--
 board/solidrun/hummingboard/hummingboard.c | 3 +--
 6 files changed, 5 insertions(+), 19 deletions(-)

diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c
index c10dd28..d174a46 100644
--- a/arch/arm/imx-common/sata.c
+++ b/arch/arm/imx-common/sata.c
@@ -12,8 +12,7 @@
 
 int setup_sata(void)
 {
-   struct iomuxc_base_regs *const iomuxc_regs
-   = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+   struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret;
 
if (!is_cpu_type(MXC_CPU_MX6Q)  !is_cpu_type(MXC_CPU_MX6D))
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h 
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index df87123..782d9c4 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -764,15 +764,6 @@ struct anatop_regs {
 #define ANATOP_PFD_CLKGATE_SHIFT(n)(7+((n)*8))
 #define ANATOP_PFD_CLKGATE_MASK(n) (1ANATOP_PFD_CLKGATE_SHIFT(n))
 
-struct iomuxc_base_regs {
-   u32 gpr[14];/* 0x000 */
-   u32 obsrv[5];   /* 0x038 */
-   u32 swmux_ctl[197]; /* 0x04c */
-   u32 swpad_ctl[250]; /* 0x360 */
-   u32 swgrp[26];  /* 0x748 */
-   u32 daisy[104]; /* 0x7b0..94c */
-};
-
 struct wdog_regs {
u16 wcr;/* Control */
u16 wsr;/* Service */
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c 
b/board/boundary/nitrogen6x/nitrogen6x.c
index 84294db..60a09f4 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -644,8 +644,7 @@ int overwrite_console(void)
 
 int board_init(void)
 {
-   struct iomuxc_base_regs *const iomuxc_regs
-   = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+   struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 
clrsetbits_le32(iomuxc_regs-gpr[1],
IOMUXC_GPR1_OTG_ID_MASK,
diff --git a/board/freescale/mx6slevk/mx6slevk.c 
b/board/freescale/mx6slevk/mx6slevk.c
index d2b64cc..a990b4c 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -130,8 +130,7 @@ int board_eth_init(bd_t *bis)
 
 static int setup_fec(void)
 {
-   struct iomuxc_base_regs *iomuxc_regs =
-   (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+   struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret;
 
/* clear gpr1[14], gpr1[18:17] to select anatop clock */
diff --git a/board/gateworks/gw_ventana/gw_ventana.c 
b/board/gateworks/gw_ventana/gw_ventana.c
index 9d2651f..9967f80 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -1122,8 +1122,7 @@ int dram_init(void)
 
 int board_init(void)
 {
-   struct iomuxc_base_regs *const iomuxc_regs
-   = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+   struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 
clrsetbits_le32(iomuxc_regs-gpr[1],
IOMUXC_GPR1_OTG_ID_MASK,
diff --git a/board/solidrun/hummingboard/hummingboard.c 
b/board/solidrun/hummingboard/hummingboard.c
index 2e2fb2a..6d204b3 100644
--- a/board/solidrun/hummingboard/hummingboard.c
+++ b/board/solidrun/hummingboard/hummingboard.c
@@ -144,8 +144,7 @@ int board_phy_config(struct phy_device *phydev)
 
 int board_eth_init(bd_t *bis)
 {
-   struct iomuxc_base_regs *const iomuxc_regs =
-   (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+   struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 
int ret = enable_fec_anatop_clock(ENET_25MHz);
if (ret)
-- 
1.8.3.2

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Re: [U-Boot] [PATCH] Fix help text of ext2load and fatload.

[Marek Vasut]

On Wednesday, July 09, 2014 at 10:40:07 PM, Pavel Machek wrote:
 Fix help text of ext2load and fatload to match code in fs/fs.c

Which code in fs/fs.c do you mean? Are you referring to do_load() ?

Reviewed-by: Marek Vasut ma...@denx.de

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] catch wrong load address passed to fatload / ext2load

[Marek Vasut]

On Wednesday, July 09, 2014 at 10:42:57 PM, Pavel Machek wrote:
 If filename is passed instead of address to ext2load or fatload,
 u-boot silently accepts that, and uses 0 for load address and default
 filename from environment. That is confusing, display help instead.
 
 Signed-off-by: Pavel Machek pa...@denx.de

The handling of simple_strtoul() in fs.c could use improvement like this in 
general. Do you mind expanding this patch ?

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v2 2/2] usb: phy: omap_usb_phy: implement usb_phy_power() for AM437x

[Marek Vasut]

On Tuesday, June 24, 2014 at 12:18:24 AM, Felipe Balbi wrote:
 Newer AM437x silicon requires us to explicitly power up
 the USB2 PHY. By implementing usb_phy_power() we can
 achieve that.
 
 Signed-off-by: Felipe Balbi ba...@ti.com

Applied 1/2 and 2/2 v2 , thanks.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] catch wrong load address passed to fatload / ext2load

[Pavel Machek]

On Wed 2014-07-09 23:07:56, Marek Vasut wrote:
 On Wednesday, July 09, 2014 at 10:42:57 PM, Pavel Machek wrote:
  If filename is passed instead of address to ext2load or fatload,
  u-boot silently accepts that, and uses 0 for load address and default
  filename from environment. That is confusing, display help instead.
  
  Signed-off-by: Pavel Machek pa...@denx.de
 
 The handling of simple_strtoul() in fs.c could use improvement like this in 
 general. Do you mind expanding this patch ?

I'd prefer not to do that at this moment: I don't have working-enough
u-boot and hate to do changes without testing.

Pavel
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Re: [U-Boot] [PATCH] Fix help text of ext2load and fatload.

[Pavel Machek]

On Wed 2014-07-09 23:05:25, Marek Vasut wrote:
 On Wednesday, July 09, 2014 at 10:40:07 PM, Pavel Machek wrote:
  Fix help text of ext2load and fatload to match code in fs/fs.c
 
 Which code in fs/fs.c do you mean? Are you referring to do_load() ?

Yes, do_load.

 Reviewed-by: Marek Vasut ma...@denx.de

Thanks!
Pavel
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Re: [U-Boot] [PATCH] catch wrong load address passed to fatload / ext2load

[Wolfgang Denk]

Dear Pavel Machek,

In message 20140709204257.ga28...@amd.pavel.ucw.cz you wrote:
 
 If filename is passed instead of address to ext2load or fatload,
 u-boot silently accepts that, and uses 0 for load address and default
 filename from environment. That is confusing, display help instead.
 
 Signed-off-by: Pavel Machek pa...@denx.de
 
 diff --git a/fs/fs.c b/fs/fs.c
 index 79d432d..ea15c5f 100644
 --- a/fs/fs.c
 +++ b/fs/fs.c
 @@ -276,6 +276,7 @@ int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char * 
 const argv[],
   unsigned long pos;
   int len_read;
   unsigned long time;
 + char *ep;
  
   if (argc  2)
   return CMD_RET_USAGE;
 @@ -286,7 +287,9 @@ int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char * 
 const argv[],
   return 1;
  
   if (argc = 4) {
 - addr = simple_strtoul(argv[3], NULL, 16);
 + addr = simple_strtoul(argv[3], ep, 16);
 + if (ep == argv[3] || *ep != '\0')
 + return CMD_RET_USAGE;

What happens in case of filenames that look like numbers, say 0?
It may be silly to use such, but it should not be impossible to do so.

Viele Grüße,

Wolfgang Denk

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Re: [U-Boot] [PATCH] catch wrong load address passed to fatload / ext2load

[Pavel Machek]

On Thu 2014-07-10 01:08:28, Wolfgang Denk wrote:
 Dear Pavel Machek,
 
 In message 20140709204257.ga28...@amd.pavel.ucw.cz you wrote:
  
  If filename is passed instead of address to ext2load or fatload,
  u-boot silently accepts that, and uses 0 for load address and default
  filename from environment. That is confusing, display help instead.
  
  Signed-off-by: Pavel Machek pa...@denx.de
  
  diff --git a/fs/fs.c b/fs/fs.c
  index 79d432d..ea15c5f 100644
  --- a/fs/fs.c
  +++ b/fs/fs.c
  @@ -276,6 +276,7 @@ int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char 
  * const argv[],
  unsigned long pos;
  int len_read;
  unsigned long time;
  +   char *ep;
   
  if (argc  2)
  return CMD_RET_USAGE;
  @@ -286,7 +287,9 @@ int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char 
  * const argv[],
  return 1;
   
  if (argc = 4) {
  -   addr = simple_strtoul(argv[3], NULL, 16);
  +   addr = simple_strtoul(argv[3], ep, 16);
  +   if (ep == argv[3] || *ep != '\0')
  +   return CMD_RET_USAGE;
 
 What happens in case of filenames that look like numbers, say 0?
 It may be silly to use such, but it should not be impossible to do
 so.

It should be ok.

This catches error when someone passes non-number as a load
address. As long as you pass load address, nothing changes.

IOW  

fatload mmc 0:1 0 filename
# always worked/keeps working
fatload mmc 0:1 filename
# before my patch, this would try to parse filename as number, fail,
# and use default load address adn default filename. Not what user
# wanted.
fatload mmc 0:1 0 0
# Load filename 0 at address 0. Worked before, will work now.

Hope this helps,
Pavel
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Re: [U-Boot] [PATCH] boards.cfg: keep it sorted filling the board field

[Masahiro Yamada]

Hi Tom,



On Wed, 9 Jul 2014 09:12:48 -0400
Tom Rini tr...@ti.com wrote:

 On Wed, Jul 09, 2014 at 05:34:28PM +0900, Masahiro Yamada wrote:
  The boards.cfg file has allowed to use - for the board (= 6th) field
  if the board name is the same as the 7th field.
  
  But I notice one problem.
  Because tools/reformat.py sorts the lines in the simple alphabetical
  order (= the order of character code), some entries for the same board
  are not lined up together.
  
  For example, bf527-ezkit and bf527-ezkit-v2 share the same board.
  But they are located separately because bf527-ezkit fills the board
  field with - whereas bf527-ezkit-v2 specifies it explicitely.
  
  The similar things can be seen:
   - between trizepsive and polaris
   - between RRvision and RRvision_LCD
   - between korat and korat_perm
   - between lwmon5 and lcd4_lwmon5
  
  This commit was generated by the following command:
  
  awk '$6 == - { $6 = $7 } { print }' boards.cfg \
| tools/reformat.py -i -d '-' -s 8   boards0.cfg; \
mv boards0.cfg boards.cfg
  
  Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
 
 Tricky!  So I'm fine with correcting this problem but we also need to
 update the top part of baords.cfg where it says how to re-sort things so
 that we don't lose this in the future.
 

I guess you mentioned this part:

# It can be used from a shell:
#   tools/reformat.py -i -d '-' -s 8 boards.cfg boards0.cfg  mv 
boards0.cfg boards.cfg
# It can directly be invoked from vim:
#   :%!tools/reformat.py -i -d '-' -s 8




I don't think we need to fill the board field every time.
But my concern is that some people might add new boards
with '-' for that.

After this patch is applied, I will post a follow-up patch
to change mkconfig prohibiting '-' for the board field.
(Or perhaps changing the meaning of '-'. I want to use '-'
to define board is none.)


Best Regards
Masahiro Yamada

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[U-Boot] [PATCH 2/2] usb: phy: omap_usb_phy: implement usb_phy_power() for AM437x

[Felipe Balbi]

Newer AM437x silicon requires us to explicitly power up
the USB2 PHY. By implementing usb_phy_power() we can
achieve that.

Signed-off-by: Felipe Balbi ba...@ti.com
---
 arch/arm/include/asm/arch-am33xx/hardware_am43xx.h |  5 +
 drivers/usb/phy/omap_usb_phy.c | 11 ++-
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h 
b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
index b470319..efdecf4 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
@@ -43,6 +43,11 @@
 #define VTP0_CTRL_ADDR 0x44E10E0C
 #define VTP1_CTRL_ADDR 0x48140E10
 
+/* USB CTRL Base Address */
+#define USB1_CTRL  0x44e10628
+#define USB1_CTRL_CM_PWRDN BIT(0)
+#define USB1_CTRL_OTG_PWRDNBIT(1)
+
 /* DDR Base address */
 #define DDR_PHY_CMD_ADDR   0x44E12000
 #define DDR_PHY_DATA_ADDR  0x44E120C8
diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c
index af46db2..53778b3 100644
--- a/drivers/usb/phy/omap_usb_phy.c
+++ b/drivers/usb/phy/omap_usb_phy.c
@@ -222,7 +222,16 @@ static void am437x_enable_usb2_phy2(struct omap_xhci *omap)
 
 void usb_phy_power(int on)
 {
-   return;
+   /*
+* In order to get USB working on newer AM43xx silicon, we must
+* explicitly power the USB PHYs.
+*/
+   if (on)
+   clrbits_le32(USB1_CTRL, USB1_CTRL_CM_PWRDN |
+   USB1_CTRL_OTG_PWRDN);
+   else
+   setbits_le32(USB1_CTRL, USB1_CTRL_CM_PWRDN |
+   USB1_CTRL_OTG_PWRDN);
 }
 #endif /* CONFIG_AM437X_USB2PHY2_HOST */
 
-- 
2.0.0.390.gcb682f8

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[U-Boot] [PATCH 1/2] usb: host: xhci: make sure to power up PHY

[Felipe Balbi]

some boards won't work if the PHY isn't explicitly
powered up.

Signed-off-by: Felipe Balbi ba...@ti.com
---
 drivers/usb/host/xhci-omap.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c
index e667810..912b2bd 100644
--- a/drivers/usb/host/xhci-omap.c
+++ b/drivers/usb/host/xhci-omap.c
@@ -98,6 +98,7 @@ static int omap_xhci_core_init(struct omap_xhci *omap)
 {
int ret = 0;
 
+   usb_phy_power(1);
omap_enable_phy(omap);
 
ret = dwc3_core_init(omap-dwc3_reg);
-- 
2.0.0.390.gcb682f8

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Re: [U-Boot] [PATCH 2/2] usb: phy: omap_usb_phy: implement usb_phy_power() for AM437x

[Felipe Balbi]

On Wed, Jul 09, 2014 at 11:02:43PM -0500, Felipe Balbi wrote:
 Newer AM437x silicon requires us to explicitly power up
 the USB2 PHY. By implementing usb_phy_power() we can
 achieve that.
 
 Signed-off-by: Felipe Balbi ba...@ti.com
 ---

the only change here is the use of {set,clr}bits_le32()

  arch/arm/include/asm/arch-am33xx/hardware_am43xx.h |  5 +
  drivers/usb/phy/omap_usb_phy.c | 11 ++-
  2 files changed, 15 insertions(+), 1 deletion(-)
 
 diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h 
 b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
 index b470319..efdecf4 100644
 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
 +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
 @@ -43,6 +43,11 @@
  #define VTP0_CTRL_ADDR   0x44E10E0C
  #define VTP1_CTRL_ADDR   0x48140E10
  
 +/* USB CTRL Base Address */
 +#define USB1_CTRL0x44e10628
 +#define USB1_CTRL_CM_PWRDN   BIT(0)
 +#define USB1_CTRL_OTG_PWRDN  BIT(1)
 +
  /* DDR Base address */
  #define DDR_PHY_CMD_ADDR 0x44E12000
  #define DDR_PHY_DATA_ADDR0x44E120C8
 diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c
 index af46db2..53778b3 100644
 --- a/drivers/usb/phy/omap_usb_phy.c
 +++ b/drivers/usb/phy/omap_usb_phy.c
 @@ -222,7 +222,16 @@ static void am437x_enable_usb2_phy2(struct omap_xhci 
 *omap)
  
  void usb_phy_power(int on)
  {
 - return;
 + /*
 +  * In order to get USB working on newer AM43xx silicon, we must
 +  * explicitly power the USB PHYs.
 +  */
 + if (on)
 + clrbits_le32(USB1_CTRL, USB1_CTRL_CM_PWRDN |
 + USB1_CTRL_OTG_PWRDN);
 + else
 + setbits_le32(USB1_CTRL, USB1_CTRL_CM_PWRDN |
 + USB1_CTRL_OTG_PWRDN);
  }
  #endif /* CONFIG_AM437X_USB2PHY2_HOST */
  
 -- 
 2.0.0.390.gcb682f8
 

-- 
balbi


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Re: [U-Boot] [PATCH 1/3] ARM: omap: Fix GPMC init for OMAP3 platforms

[Stefan Roese]

Hi Pekon,

On 09.07.2014 20:22, Gupta, Pekon wrote:

Commit a0a37183 (ARM: omap: merge GPMC initialization code for all
platform) broke NAND on OMAP3 based platforms. I noticed this while
testing the latest 2014.07-rc version on the TAO3530 board. NAND
detection did not work with this error message:

NAND:  nand: error: Unable to find NAND settings in GPMC Configuration - 
quitting

As OMAP3 configs don't set CONFIG_NAND but CONFIG_NAND_CMD. the GPMC
was not initialized for NAND at all. This patch now fixes this issue.


Sorry couldn't understand this, why have users enabled CONFIG_NAND_CMD,
if CONFIG_NAND itself is not enabled ?


CONFIG_NAND doesn't seem to be a mandatory define if NAND is used. Many 
OMAP3 based boards don't enable this define but still use NAND. The 
old mem.c also did only check for CONFIG_CMD_NAND to configure the 
GPMC accordingly. Thats why I chose to change mem-common.c to accept 
this kind of configuration instead of changing all those config headers 
to enable CONFIG_NAND.



Otherwise, if TAO3530 board uses the on-die NAND, then it should enable
NAND in its board profile via boards.cfg


Sorry, I don't understand what this has to do with on-die NAND. This 
patch is a clear fix to restore the original behavior with the old mem.c.


Thanks,
Stefan

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