Re: [U-Boot] [PATCH] imx6: add Bachmann OT1200 board
2014-09-09 16:41 GMT+02:00 Christian Gmeiner christian.gmei...@gmail.com: This patch adds support for the OT1200 series of devices. Following components are used in u-boot: + ethernet + i2c + emmc + gpio The main difference between the different models of the OT1200 series is how ethernet is connected (directly to a switch or to a normal phy). Signed-off-by: Christian Gmeiner christian.gmei...@gmail.com --- arch/arm/Kconfig | 4 + board/bachmann/ot1200/Kconfig | 23 board/bachmann/ot1200/MAINTAINERS | 6 + board/bachmann/ot1200/Makefile| 9 ++ board/bachmann/ot1200/ot1200.c| 262 ++ configs/ot1200_defconfig | 3 + include/configs/ot1200.h | 195 7 files changed, 502 insertions(+) create mode 100644 board/bachmann/ot1200/Kconfig create mode 100644 board/bachmann/ot1200/MAINTAINERS create mode 100644 board/bachmann/ot1200/Makefile create mode 100644 board/bachmann/ot1200/ot1200.c create mode 100644 configs/ot1200_defconfig create mode 100644 include/configs/ot1200.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 22f0f09..c93dcb6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -412,6 +412,9 @@ config TARGET_HUMMINGBOARD config TARGET_TQMA6 bool TQ Systems TQMa6 board +config TARGET_OT1200 + bool Bachmann OT1200 + config OMAP34XX bool OMAP34XX SoC @@ -564,6 +567,7 @@ source board/atmel/at91sam9rlek/Kconfig source board/atmel/at91sam9x5ek/Kconfig source board/atmel/sama5d3_xplained/Kconfig source board/atmel/sama5d3xek/Kconfig +source board/bachmann/ot1200/Kconfig source board/balloon3/Kconfig source board/barco/titanium/Kconfig source board/bluegiga/apx4devkit/Kconfig diff --git a/board/bachmann/ot1200/Kconfig b/board/bachmann/ot1200/Kconfig new file mode 100644 index 000..55a825d --- /dev/null +++ b/board/bachmann/ot1200/Kconfig @@ -0,0 +1,23 @@ +if TARGET_OT1200 + +config SYS_CPU + string + default armv7 + +config SYS_BOARD + string + default ot1200 + +config SYS_VENDOR + string + default bachmann + +config SYS_SOC + string + default mx6 + +config SYS_CONFIG_NAME + string + default ot1200 + +endif diff --git a/board/bachmann/ot1200/MAINTAINERS b/board/bachmann/ot1200/MAINTAINERS new file mode 100644 index 000..ad75c24 --- /dev/null +++ b/board/bachmann/ot1200/MAINTAINERS @@ -0,0 +1,6 @@ +BACHMANN ELECTRONIC OT1200 BOARD +M: Christian Gmeiner christian.gmei...@gmail.com +S: Maintained +F: board/bachmann/ot1200 +F: include/configs/ot1200.h +F: configs/ot1200*_defconfig diff --git a/board/bachmann/ot1200/Makefile b/board/bachmann/ot1200/Makefile new file mode 100644 index 000..1bd42e8 --- /dev/null +++ b/board/bachmann/ot1200/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2012-2013, Guennadi Liakhovetski l...@denx.de +# (C) Copyright 2012-2013 Freescale Semiconductor, Inc. +# Copyright (C) 2013, Boundary Devices i...@boundarydevices.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := ot1200.o diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c new file mode 100644 index 000..1c04f45 --- /dev/null +++ b/board/bachmann/ot1200/ot1200.c @@ -0,0 +1,262 @@ +/* + * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. + * Copyright (C) 2014, Bachmann electronic GmbH + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#include common.h +#include asm/io.h +#include asm/arch/clock.h +#include asm/arch/imx-regs.h +#include asm/arch/iomux.h +#include malloc.h +#include asm/arch/mx6-pins.h +#include asm/imx-common/iomux-v3.h +#include asm/imx-common/mxc_i2c.h +#include asm/imx-common/sata.h +#include asm/imx-common/boot_mode.h +#include asm/arch/crm_regs.h +#include mmc.h +#include fsl_esdhc.h +#include netdev.h +#include i2c.h +#include pca953x.h +#include asm/gpio.h +#include phy.h + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |\ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) + +int
Re: [U-Boot] [PATCH v4 1/6] nand: denali: add Denali NAND driver for SPL
Hi Masahiro,
On Fri, 2014-09-12 at 17:06 +0900, Masahiro Yamada wrote:
+/* nand_init() - initialize data to make nand usable by SPL */
+void nand_init(void)
+{
+ /* access to main area */
+ writel(0, denali_flash_reg + TRANSFER_SPARE_REG);
+
+ page_size = readl(denali_flash_reg + DEVICE_MAIN_AREA_SIZE);
+ oob_size = readl(denali_flash_reg + DEVICE_SPARE_AREA_SIZE);
+ pages_per_block = readl(denali_flash_reg + PAGES_PER_BLOCK);
I believe this will work for ONFI NAND devices only.
For non-ONFI, the value might not correct.
I don't think so.
It depends on the hardware; in my understanding
Denali IP is capable of detecting MAIN_AREA_SIZE etc.
for non-ONFI devices. At least this is working with non-ONFI devices
on some Panasonic boards.
If it does not work for Altera SoCs (and if you are planning to use
this driver), these three registers should be set in advance
in an earlier board init.
I recall one of my colleague was telling me that it doesn't work for one
of non ONFI part where it read incorrect page size. Nevertheless, we can
put comments so user which use this driver need to take note.
+}
+
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
+{
+ int block, page, column, readlen;
+ int ret;
+ int force_bad_block_check = 1;
+
+ page = offs / page_size;
+ column = offs % page_size;
+
+ block = page / pages_per_block;
+ page = page % pages_per_block;
+
+ while (size) {
I believe we need to error out when reading beyond last block.
How do you know the number of blocks of non-ONFI devices?
Scan nand_ids.c for SPL?
I believe we can have a macro for this. But rethinking back, we can skip
this check to make the SPL as simple as possible.
+ if (force_bad_block_check || page == 0) {
+ ret = nand_block_isbad(block);
+ if (ret 0)
+ return ret;
+
+ if (ret) {
+ block++;
+ continue;
+ }
+ }
+
+ force_bad_block_check = 0;
I believe we still need to check the subsequent block whether is bad or
not too. This can be enable when cross the block boundary.
I am afraid you are misunderstanding my code.
This function does bad block checking for every block.
Here,
if (force_bad_block_check || page == 0) {
ret = nand_block_isbad(block);
page == 0 means the beginning of each block.
Yup, you are right. I was confused with the variable.
Currently U-Boot has drivers/mtd/nand/nand_spl_simple.c which handling
the SPL NAND image load. Wonder this driver will be integrated into
nand_spl_simple.c once drivers/mtd/nand/denali.c is applied?
I am not planning to do so because:
[1] nand_spl_simple.c requires CONFIG_SYS_NAND_BLOCK_SIZE,
CONFIG_SYS_NAND_PAGE_SIZE,
CONFIG_SYS_NAND_PAGE_COUNT; we need to specify the device attributes at
compilation,
which the Denali IP is able to detect at run time.
It is not acceptable for us because we need (want) the run time configuration.
[2] nand_spl_simple.c is so generic that it cannot use the hardware
acceleration of
the Denali IP, that is, slower booting.
Yup, you identified the nand_spl_simple.c constrain. This is why I
patched this file at
http://rocketboards.org/gitweb/?p=u-boot-socfpga.git;a=commit;h=461a61b8f03d3b690de1f4ff007cd23fb80018a5.
But I didn't send this patch out as I am waiting the NAND driver patch
accepted.
Thanks
Chin Liang
Best Regards
Masahiro Yamada
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[U-Boot] [PATCH 0/3] imx:mx6: change CONFIG_SYS_FSL_ESDHC_ADDR
If board_mmc_init failed and returns with -1, cpu_mmc_init will invoke fsl_esdhc_mmc_init. fsl_esdhc_mmc_init will use CONFIG_SYS_FSL_ESDHC_ADDR to initialize SDHCx, so use USDHCx_BASE_ADDR to redefine the config macro. If not use USDHCx_BASE_ADDR to define CONFIG_SYS_FSL_ESDHC_ADDR, fsl_esdhc_mmc_init will use wrong base address to initialize SDHCx. Peng Fan (3): imx:mx6sxsabresd: change CONFIG_SYS_FSL_ESDHC_ADDR imx:mx6qarm2: change CONFIG_SYS_FSL_ESDHC_ADDR imx:mx6slevk: change CONFIG_SYS_FSL_ESDHC_ADDR include/configs/mx6qarm2.h | 2 +- include/configs/mx6slevk.h | 2 +- include/configs/mx6sxsabresd.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) -- 1.8.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/3] imx:mx6slevk: change CONFIG_SYS_FSL_ESDHC_ADDR
Define CONFIG_SYS_FSL_ESDHC_ADDR using USDHC2_BASE_ADDR which is used in board_mmc_init. Signed-off-by: Peng Fan peng@freescale.com --- include/configs/mx6slevk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 3d05a64..9a21605 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -38,7 +38,7 @@ /* MMC Configs */ #define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR #define CONFIG_MMC #define CONFIG_CMD_MMC -- 1.8.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] cleanup drivers/net/phy/micrel.c
On Tue, 2014-09-09 at 14:26 +0200, ZY - pavel wrote:
Old saying says that more than three exclamation marks in a row are
sign of mental disease. Cleanup micrel.c.
Signed-off-by: Pavel Machek pa...@denx.de
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 5d7e3be..06a31b0 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -25,8 +25,7 @@ static struct phy_driver KSZ804_driver = {
#ifndef CONFIG_PHY_MICREL_KSZ9021
/*
* I can't believe Micrel used the exact same part number
- * for the KSZ9021
- * Shame Micrel, Shame!
+ * for the KSZ9021. Shame Micrel, Shame!
*/
static struct phy_driver KS8721_driver = {
.name = Micrel KS8721BL,
@@ -40,7 +39,7 @@ static struct phy_driver KS8721_driver = {
#endif
-/**
+/*
* KSZ9021 - KSZ9031 common
*/
@@ -69,8 +68,8 @@ static int ksz90xx_startup(struct phy_device *phydev)
phydev-speed = SPEED_10;
return 0;
}
-#ifdef CONFIG_PHY_MICREL_KSZ9021
+#ifdef CONFIG_PHY_MICREL_KSZ9021
/*
* KSZ9021
*/
Acked-by: Chin Liang See cl...@altera.com
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Re: [U-Boot] [RFCv2] mainline u-boot on socfpga
Hi Pavel, On Mon, 2014-09-08 at 14:08 +0200, ZY - pavel wrote: Hi! I know coding style leaves something to be desired. But.. it recognizes MMC/ethernet, and can load linux kernel. Unfortunately, 1MB of memory at 0 is not available for some reason; but linux works ok if you avoid that area. The lowest 1MB region is configurable based on the ARM interconnect NIC-301 / L3REGS setting. I saw in this patch, there is a code which setup the PL310 / L2 controller address filter start address. This code will convert the lowest 1MB region as SDRAM. If the next 1MB memory is working, the lowest 1MB should work too. At same time, I noticed that the L2 controller address filter start address configuration is done at cpu_eth_init. I am wonder the failure you spotted is happening before this function is called? Chin Liang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] imx:mx6sxsabresd: change CONFIG_SYS_FSL_ESDHC_ADDR
Define CONFIG_SYS_FSL_ESDHC_ADDR using USDHC4_BASE_ADDR which is used in board_mmc_init. If board_mmc_init failed, cpu_mmc_init-fsl_esdhc_mmc_init will use CONFIG_SYS_FSL_ESDHC_ADDR to initialize sdhc. So set this macro to correct value. Signed-off-by: Peng Fan peng@freescale.com --- include/configs/mx6sxsabresd.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 1eda65e..c36ab23 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -159,7 +159,7 @@ /* MMC Configuration */ #define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR #define CONFIG_MMC #define CONFIG_CMD_MMC -- 1.8.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3] imx:mx6qarm2: change CONFIG_SYS_FSL_ESDHC_ADDR
Define CONFIG_SYS_FSL_ESDHC_ADDR using USDHC4_BASE_ADDR. USDHC3 and USDHC4 are both initialized in board_mmc_init. There is no restriction on USDHC3 addr or USDHC4 addr should be assigned to CONFIG_SYS_FSL_ESDHC_ADDR. So, just choose USDHC4_BASE_ADDR to avoid errors when fsl_esdhc_mmc_init is invoked. Signed-off-by: Peng Fan peng@freescale.com --- include/configs/mx6qarm2.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index fd651cf..fc0e284 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -35,7 +35,7 @@ /* MMC Configs */ #define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_MMC -- 1.8.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4] imx: mx6: Set Pfuze mode to decrease power number for DSM
Set all switches APS mode in normal and PFM mode in standby. So when
mx6 entering DSM mode, the power number can be decreased. There is
no impact for mx6 in run mode.
Signed-off-by: Ye.Li b37...@freescale.com
---
Changes since v1:
- Try to correct the return code per Fabio's comments, but send out a false
patch
Changes since v2:
- Correct the return code
Changes since v3:
- Separate this patch from patch set.
- Add the pfuze mode function to factorized pfuze codes and common file.
board/freescale/common/pfuze.c | 39 +++
1 files changed, 39 insertions(+), 0 deletions(-)
diff --git a/board/freescale/common/pfuze.c b/board/freescale/common/pfuze.c
index cf92c38..6004c61 100644
--- a/board/freescale/common/pfuze.c
+++ b/board/freescale/common/pfuze.c
@@ -8,6 +8,39 @@
#include power/pmic.h
#include power/pfuze100_pmic.h
+static int pfuze_setup_mode(struct pmic *p, int chip)
+{
+ unsigned char offset, i, switch_num, value;
+ int ret;
+
+ if (!chip) {
+ /* pfuze100 */
+ switch_num = 6;
+ offset = 0x31;
+ } else {
+ /* pfuze200 */
+ switch_num = 4;
+ offset = 0x38;
+ }
+
+ value = 0xc;
+ ret = pmic_reg_write(p, 0x23, value);
+ if (ret) {
+ printf(Set SW1AB mode error: %d!\n, ret);
+ return ret;
+ }
+
+ for (i = 0; i switch_num - 1; i++) {
+ ret = pmic_reg_write(p, offset + i * 7, value);
+ if (ret) {
+ printf(Set switch%x mode error: %d!\n, offset, ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
struct pmic * pfuze_common_init(unsigned char i2cbus)
{
struct pmic *p;
@@ -27,6 +60,12 @@ struct pmic * pfuze_common_init(unsigned char i2cbus)
printf(PMIC: PFUZE%s ID=0x%02x\n,
((reg 0xf) == 0) ? 100 : 200, reg);
+ ret = pfuze_setup_mode(p, (reg 0xf));
+ if (ret) {
+ printf(setup pfuze mode error: %d!\n, ret);
+ return NULL;
+ }
+
/* Set SW1AB stanby volage to 0.975V */
pmic_reg_read(p, PFUZE100_SW1ABSTBY, reg);
reg = ~0x3f;
--
1.7.4.1
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[U-Boot] [PATCH v4] imx: mx6sabre: pfuze: Add clear print for pfuze200
Add clear print log to show pfuze200 or pfuze100 found on mx6 sabre boards. Signed-off-by: Ye.Li b37...@freescale.com --- Changes since v1: - None Changes since v2: - None Changes since v3: - Separate the patch from patch set - Add the clear print to factorized pfuze function board/freescale/common/pfuze.c |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/board/freescale/common/pfuze.c b/board/freescale/common/pfuze.c index 4398170..cf92c38 100644 --- a/board/freescale/common/pfuze.c +++ b/board/freescale/common/pfuze.c @@ -24,7 +24,8 @@ struct pmic * pfuze_common_init(unsigned char i2cbus) return NULL; pmic_reg_read(p, PFUZE100_DEVICEID, reg); - printf(PMIC: PFUZE100 ID=0x%02x\n, reg); + printf(PMIC: PFUZE%s ID=0x%02x\n, + ((reg 0xf) == 0) ? 100 : 200, reg); /* Set SW1AB stanby volage to 0.975V */ pmic_reg_read(p, PFUZE100_SW1ABSTBY, reg); -- 1.7.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/3] imx: mx6slevk: Add PMIC Pfuze support
Initialize the Pfuze on I2C1 at mx6slekv board late init.
Signed-off-by: Ye.Li b37...@freescale.com
---
Changes since v1:
- None
Changes since v2:
- None
Changes since v3:
- Use the factorized pfuze common function in pfuze init
board/freescale/mx6slevk/mx6slevk.c | 22 ++
include/configs/mx6slevk.h |7 +++
2 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/board/freescale/mx6slevk/mx6slevk.c
b/board/freescale/mx6slevk/mx6slevk.c
index fedd5c3..c027d08 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -21,6 +21,8 @@
#include mmc.h
#include netdev.h
#include i2c.h
+#include power/pmic.h
+#include ../common/pfuze.h
DECLARE_GLOBAL_DATA_PTR;
@@ -48,6 +50,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+#define I2C_PMIC 0
+
/* I2C1 for PMIC */
struct i2c_pads_info i2c_pad_info0 = {
.sda = {
@@ -191,6 +195,24 @@ int board_init(void)
return 0;
}
+static int pfuze_init(void)
+{
+ struct pmic *p;
+
+ p = pfuze_common_init(I2C_PMIC);
+ if (!p)
+ return -ENODEV;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ pfuze_init();
+
+ return 0;
+}
+
u32 get_board_rev(void)
{
return get_cpu_rev();
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index bf5066f..09d0896 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -30,6 +30,7 @@
#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
@@ -66,6 +67,12 @@
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_SPEED 10
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
--
1.7.4.1
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[U-Boot] [PATCH 2/3] imx: mx6slevk: Add I2C1 support
Enable the MXC I2C driver for mx6slevk and setup the I2C1.
Signed-off-by: Ye.Li b37...@freescale.com
---
Changes since v1:
- None
Changes since v2:
- None
Changes since v3:
- Split the I2C1 pad setting to another new patch.
board/freescale/mx6slevk/mx6slevk.c | 26 ++
include/configs/mx6slevk.h |6 ++
2 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/board/freescale/mx6slevk/mx6slevk.c
b/board/freescale/mx6slevk/mx6slevk.c
index a990b4c..fedd5c3 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -13,12 +13,14 @@
#include asm/arch/sys_proto.h
#include asm/gpio.h
#include asm/imx-common/iomux-v3.h
+#include asm/imx-common/mxc_i2c.h
#include asm/io.h
#include linux/sizes.h
#include common.h
#include fsl_esdhc.h
#include mmc.h
#include netdev.h
+#include i2c.h
DECLARE_GLOBAL_DATA_PTR;
@@ -37,8 +39,29 @@ DECLARE_GLOBAL_DATA_PTR;
#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+#define I2C_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE |\
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
#define ETH_PHY_RESET IMX_GPIO_NR(4, 21)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+/* I2C1 for PMIC */
+struct i2c_pads_info i2c_pad_info0 = {
+ .sda = {
+ .i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
+ .gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC,
+ .gp = IMX_GPIO_NR(3, 13),
+ },
+ .scl = {
+ .i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
+ .gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC,
+ .gp = IMX_GPIO_NR(3, 12),
+ },
+};
+
int dram_init(void)
{
gd-ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -162,6 +185,9 @@ int board_init(void)
#ifdef CONFIG_FEC_MXC
setup_fec();
#endif
+
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, i2c_pad_info0);
+
return 0;
}
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index 3d05a64..bf5066f 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -60,6 +60,12 @@
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED 10
+
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
--
1.7.4.1
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[U-Boot] [PATCH 1/3] imx: mx6sololite: Add I2C1 pad settings
Add I2C1 SDA/SCL pad settings for mx6 sololite
Signed-off-by: Ye.Li b37...@freescale.com
---
Changes since v1:
- None
Changes since v2:
- None
Changes since v3:
- Split the I2C1 pad settings to a new patch since it is board independent.
arch/arm/include/asm/arch-mx6/mx6sl_pins.h |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
index 045ccc4..ac84270 100644
--- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -34,5 +34,10 @@ enum {
MX6_PAD_FEC_REF_CLK__FEC_REF_OUT=
IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0),
MX6_PAD_FEC_RX_ER__GPIO_4_19=
IOMUX_PAD(0x0428, 0x0138, 5, 0x, 0, 0),
MX6_PAD_FEC_TX_CLK__GPIO_4_21 =
IOMUX_PAD(0x0434, 0x0144, 5, 0x, 0, 0),
+
+ MX6_PAD_I2C1_SDA__I2C1_SDA =
IOMUX_PAD(0x0450, 0x0160, 0x10, 0x0720, 2, 0),
+ MX6_PAD_I2C1_SDA__GPIO_3_13 =
IOMUX_PAD(0x0450, 0x0160, 5, 0x, 0, 0),
+ MX6_PAD_I2C1_SCL__I2C1_SCL =
IOMUX_PAD(0x044C, 0x015C, 0x10, 0x071C, 2, 0),
+ MX6_PAD_I2C1_SCL__GPIO_3_12 =
IOMUX_PAD(0x044C, 0x015C, 5, 0x, 0, 0),
};
#endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
--
1.7.4.1
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Re: [U-Boot] [RFCv2] mainline u-boot on socfpga
Hi Pavel, On Mon, 2014-09-08 at 14:08 +0200, ZY - pavel wrote: Hi! I know coding style leaves something to be desired. But.. it recognizes MMC/ethernet, and can load linux kernel. Unfortunately, 1MB of memory at 0 is not available for some reason; but linux works ok if you avoid that area. fpga load 0 now seems to work. For some reason, I had to rewrite fpgamgr_axi_write(). There's some bug in assembly version, causing code to get confused after it is executed. This assembly version works well for me as I got daily test run to test this functionality. We got around 77% improvement using this assembly compared to C code previously. Having that said, probably you can share with me the details of your bug. Chin Liang If some ARM expert could take a look, that would be great; bug is likely also present in rocketboards version of u-boot. Best regards, Pavel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mtdcore: Fix a build error with CONFIG_CMD_MTDPARTS_SPREAD
Gentle ping.
On Mon, Sep 08, 2014 at 07:04:16PM +0200, Maxin B. John wrote:
This patch fixes the build error for CONFIG_CMD_MTDPARTS_SPREAD
Signed-off-by: Maxin B. John maxin.j...@enea.com
---
drivers/mtd/mtdcore.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c
index 6ad0357..c9efb3f 100644
--- a/drivers/mtd/mtdcore.c
+++ b/drivers/mtd/mtdcore.c
@@ -804,7 +804,7 @@ void mtd_get_len_incl_bad(struct mtd_info *mtd, uint64_t
offset,
*truncated = 0;
*len_incl_bad = 0;
- if (!mtd-block_isbad) {
+ if (!mtd-_block_isbad) {
*len_incl_bad = length;
return;
}
@@ -820,7 +820,7 @@ void mtd_get_len_incl_bad(struct mtd_info *mtd, uint64_t
offset,
block_len = mtd-erasesize - (offset (mtd-erasesize - 1));
- if (!mtd-block_isbad(mtd, offset ~(mtd-erasesize - 1)))
+ if (!mtd-_block_isbad(mtd, offset ~(mtd-erasesize - 1)))
len_excl_bad += block_len;
*len_incl_bad += block_len;
--
1.9.1
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Re: [U-Boot] A minor question on a Driver Model function
Hi,
On 09/14/14 21:28, Simon Glass wrote:
Hi Masahiro,
On 12 September 2014 05:25, Masahiro Yamada yamad...@jp.panasonic.com wrote:
Hi Simon,
I have a qustion about lists_driver_lookup_name() function.
for (entry = drv; entry != drv + n_ents; entry++) {
if (strncmp(name, entry-name, len))
continue;
/* Full match */
if (len == strlen(entry-name))
return entry;
}
Why is this not like follows?
for (entry = drv; entry != drv + n_ents; entry++) {
if (!strcmp(name, entry-name))
return entry;
}
I would suggest still using strncmp as it is safer,
but count also the '\0', so something like:
for (entry = drv; entry != drv + n_ents; entry++) {
if (!strncmp(name, entry-name, len + 1))
return entry;
}
[...]
--
Regards,
Igor.
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Re: [U-Boot] (no subject)
Hi On Fri, Sep 12, 2014 at 10:00 PM, Michael Trimarchi mich...@amarulasolutions.com wrote: Hi Il 12/set/2014 21:53 Mariusz Boguszewski mariusz.boguszew...@csr.com ha scritto: Hello, I need to get this new version of u-boot for my PandaBoard A6 rev. I tried Linaro release 14.08 from July 2014 but all I get is the error: U-Boot SPL 2013.01.-rc1-g43ee87a (May 25 2014 - 07:45:31) OMAP4430 ES2.3 SDRAM: identified size not same as expected size identified: 0 expected: 4000 Try to enable auto detection Just comment this /* Defines for SDRAM init */ #define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS #define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS #endif Michael Michael Is this fix applied to u-boot, and where can I get it ? Regards. Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom More information can be found at www.csr.com. Keep up to date with CSR on our technical blog, www.csr.com/blog, CSR people blog, www.csr.com/people, YouTube, www.youtube.com/user/CSRplc, Facebook, www.facebook.com/pages/CSR/191038434253534, or follow us on Twitter at www.twitter.com/CSR_plc. New for 2014, you can now access the wide range of products powered by aptX at www.aptx.com. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot -- | Michael Nazzareno Trimarchi Amarula Solutions BV | | COO - Founder Cruquiuskade 47 | | +31(0)851119172 Amsterdam 1018 AM NL | | [`as] http://www.amarulasolutions.com | ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFCv2] mainline u-boot on socfpga
Hi! I know coding style leaves something to be desired. But.. it recognizes MMC/ethernet, and can load linux kernel. Unfortunately, 1MB of memory at 0 is not available for some reason; but linux works ok if you avoid that area. fpga load 0 now seems to work. For some reason, I had to rewrite fpgamgr_axi_write(). There's some bug in assembly version, causing code to get confused after it is executed. This assembly version works well for me as I got daily test run to test this functionality. We got around 77% improvement using this assembly compared to C code previously. Having that said, probably you can share with me the details of your bug. It seems that if CONFIG_THUMB is enabled (as is in some versions, IIRC), it crashes and burns. Compared with MMC speed, it seems to be fast enough, but ok, 77% speedup is nice. We have fixed version in tree, Marek will post it soon. Best regards, Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] mainline u-boot on socfpga
Hi! Wolfgang's advice is valuable and noted. However, it is in Altera's best interest that we have 1 central gathering point for all our opensource software support. Full agreement here. But I would like to point out that your point of view appears to be biased: U-Boot mainline is a community project, and the community is very much vendor-independent. So the question we're trying to solve here is not what is optimal for Altera, but what is optimal for the community. As is, current mainline U-Boot is not really working well on most SoCFPGA systems. I would disagree on this. U-Boot with basic features is working well on Altera dev kit. I believe it works well for Pavel too as I recall from his emails. From his latest watchdog patch, seems he is able to boot to kernel too. I'd not characterize latest mainline u-boot as working well. I hit some obscure problems (time running 1000x too fast, low memory not working, linux not starting) and was not able to get it working in reliable way. In my eyes it was pretty predictable: when the port is without mmc and ethernet support, there's no surprise it bitrots. Linux still does not reliably start for me :-(. Now, don't spend too much time staring at [rfc] patch, there should be split up version later today. While for SPL, I would admit its bit slow. But almost all the essential drivers were there except the SDRAM. This has been dragged for long due to the legal discussion between GPL and BSD-3. I believe you are part of this length discussion too :) But this is resolved now after persuading our legal team. Hopefully we can send out the SDRAM patch soon. Good, so things are getting better. Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2][v3] mpc85xx: configs - Add hash command in freescale platforms
Hardware accelerated support for SHA-1 and SHA-256 has been added. Hash command enabled along with hardware accelerated support for SHA-1 and SHA-256 for platforms which have CAAM block. Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com CC: York Sun york...@freescale.com --- Change log: v2: No change The patch series is dependent on https://patchwork.ozlabs.org/patch/387174/ https://patchwork.ozlabs.org/patch/387175/ include/configs/B4860QDS.h | 4 include/configs/BSC9131RDB.h | 4 include/configs/BSC9132QDS.h | 4 include/configs/C29XPCIE.h | 4 include/configs/P1010RDB.h | 4 include/configs/P2041RDB.h | 4 include/configs/T1040QDS.h | 4 include/configs/T104xRDB.h | 4 include/configs/T208xQDS.h | 4 include/configs/T208xRDB.h | 4 include/configs/T4240QDS.h | 4 include/configs/T4240RDB.h | 4 include/configs/corenet_ds.h | 4 13 files changed, 52 insertions(+) diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 953d06b..58932ad 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -758,6 +758,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_NET #endif +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + /* * USB */ diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 56a3e94..fb50db0 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -382,6 +382,10 @@ extern unsigned long get_sdram_size(void); #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #endif +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + #define CONFIG_USB_EHCI #ifdef CONFIG_USB_EHCI diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index aeded6d..922ac00 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -598,6 +598,10 @@ combinations. this should be removed later #define CONFIG_DOS_PARTITION #endif +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + /* * Miscellaneous configurable options */ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 715616d..ca1b2f5 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -506,6 +506,10 @@ #define CONFIG_CMD_SETEXPR #define CONFIG_CMD_REGINFO +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + /* * Miscellaneous configurable options */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index a373990..45ef53d 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -832,6 +832,10 @@ extern unsigned long get_sdram_size(void); #define CONFIG_DOS_PARTITION #endif +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + /* * Miscellaneous configurable options */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 16f7525..7ff2dd5 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -647,6 +647,10 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_DOS_PARTITION #endif +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + /* * Miscellaneous configurable options */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index a781ba3..5870a49 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -716,6 +716,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_NET #endif +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + /* * Miscellaneous configurable options */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 0ee0ff2..8e43931 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -727,6 +727,10 @@ #define CONFIG_CMD_NET #endif +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + /* * Miscellaneous configurable options */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 395472b..9a8a3b6 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -777,6 +777,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_NET #endif +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + /* * Miscellaneous configurable options */ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index e5936c7..4ff31e6 100644 --- a/include/configs/T208xRDB.h +++
[U-Boot] [PATCH 1/2][v2] fsl_sec: Add hardware accelerated SHA256 and SHA1
SHA-256 and SHA-1 accelerated using SEC hardware in Freescale SoC's
The driver for SEC (CAAM) IP is based on linux drivers/crypto/caam.
Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
CC: York Sun york...@freescale.com
---
Change log
v2: Added a common function run_descriptor_jr to avoid repettion
of common code
The patch series is dependent on
https://patchwork.ozlabs.org/patch/387174/
https://patchwork.ozlabs.org/patch/387175/
arch/powerpc/cpu/mpc85xx/cpu_init.c | 5 +
arch/powerpc/include/asm/config.h | 4 +
arch/powerpc/include/asm/immap_85xx.h | 5 +
arch/powerpc/include/asm/types.h | 4 +
drivers/crypto/Makefile | 1 +
drivers/crypto/fsl/Makefile | 9 +
drivers/crypto/fsl/desc.h | 651 ++
drivers/crypto/fsl/desc_constr.h | 280 +++
drivers/crypto/fsl/error.c| 258 ++
drivers/crypto/fsl/fsl_hash.c | 77
drivers/crypto/fsl/jobdesc.c | 45 +++
drivers/crypto/fsl/jobdesc.h | 18 +
drivers/crypto/fsl/jr.c | 337 ++
drivers/crypto/fsl/jr.h | 97 +
include/fsl_sec.h | 45 +++
15 files changed, 1836 insertions(+)
create mode 100644 drivers/crypto/fsl/Makefile
create mode 100644 drivers/crypto/fsl/desc.h
create mode 100644 drivers/crypto/fsl/desc_constr.h
create mode 100644 drivers/crypto/fsl/error.c
create mode 100644 drivers/crypto/fsl/fsl_hash.c
create mode 100644 drivers/crypto/fsl/jobdesc.c
create mode 100644 drivers/crypto/fsl/jobdesc.h
create mode 100644 drivers/crypto/fsl/jr.c
create mode 100644 drivers/crypto/fsl/jr.h
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index bf9fbbf..21c3194 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -27,6 +27,7 @@
#include hwconfig.h
#include linux/compiler.h
#include mp.h
+#include fsl_sec.h
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
#include nand.h
#include errno.h
@@ -938,6 +939,10 @@ int cpu_init_r(void)
fman_enet_init();
#endif
+#if CONFIG_SYS_FSL_SEC_COMPAT = 4
+ sec_init();
+#endif
+
#if defined(CONFIG_FSL_SATA_V2) defined(CONFIG_FSL_SATA_ERRATUM_A001)
/*
* For P1022/1013 Rev1.0 silicon, after power on SATA host
diff --git a/arch/powerpc/include/asm/config.h
b/arch/powerpc/include/asm/config.h
index 423a6fb..e1b2c20 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -103,4 +103,8 @@
/* All PPC boards must swap IDE bytes */
#define CONFIG_IDE_SWAP_IO
+#if CONFIG_SYS_FSL_SEC_COMPAT = 4
+#define CONFIG_FSL_CAAM
+#endif
+
#endif /* _ASM_CONFIG_H_ */
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index e426314..88c1e08 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2875,6 +2875,7 @@ struct ccsr_sfp_regs {
#define CONFIG_SYS_MPC85xx_SATA1_OFFSET0x22
#define CONFIG_SYS_MPC85xx_SATA2_OFFSET0x221000
#define CONFIG_SYS_FSL_SEC_OFFSET 0x30
+#define CONFIG_SYS_FSL_JR0_OFFSET 0x301000
#define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
#define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
#define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
@@ -2935,8 +2936,10 @@ struct ccsr_sfp_regs {
#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET0x2e000
#if defined(CONFIG_PPC_C29X)
#define CONFIG_SYS_FSL_SEC_OFFSET 0x8
+#define CONFIG_SYS_FSL_JR0_OFFSET 0x81000
#else
#define CONFIG_SYS_FSL_SEC_OFFSET 0x3
+#define CONFIG_SYS_FSL_JR0_OFFSET 0x31000
#endif
#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
@@ -3041,6 +3044,8 @@ struct ccsr_sfp_regs {
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
#define CONFIG_SYS_FSL_SEC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
#define CONFIG_SYS_FSL_FM1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
diff --git a/arch/powerpc/include/asm/types.h b/arch/powerpc/include/asm/types.h
index b27a6b7..b29ce79 100644
--- a/arch/powerpc/include/asm/types.h
+++ b/arch/powerpc/include/asm/types.h
@@ -41,8 +41,12 @@ typedef unsigned long long u64;
#define BITS_PER_LONG 32
+#ifdef CONFIG_PHYS_64BIT
+typedef unsigned long long dma_addr_t;
+#else
/* DMA addresses are 32-bits wide */
typedef u32 dma_addr_t;
+#endif
#ifdef CONFIG_PHYS_64BIT
typedef unsigned long long phys_addr_t;
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index b807795..7b79237 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -6,3 +6,4 @@
#
[U-Boot] [PATCH] usb: ehci-mx6: Rename the USB register base address
The mx6sl/mx6sx has 2 OTG and 1 host. So they have name
USBO2H_USB_BASE_ADDR in imx-regs.h. The driver hard codes
the USB base address name to USBOH3, which causes the driver
failed to build for mx6sl/mx6sx.
This patch uniform the address name to USB_BASE_ADDR for all
mx6 series.
Signed-off-by: Ye.Li b37...@freescale.com
---
arch/arm/include/asm/arch-mx6/imx-regs.h |9 ++---
drivers/usb/host/ehci-mx6.c |4 ++--
2 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 22614fc..a159309 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -215,13 +215,8 @@
#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x8)
#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x4)
-#ifdef CONFIG_MX6SL
-#define USBO2H_PL301_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x)
-#define USBO2H_USB_BASE_ADDR(AIPS2_OFF_BASE_ADDR + 0x4000)
-#else
-#define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x)
-#define USBOH3_USB_BASE_ADDR(AIPS2_OFF_BASE_ADDR + 0x4000)
-#endif
+#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x)
+#define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
#ifdef CONFIG_MX6SL
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index c0a557b..9ec5a0a 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -174,7 +174,7 @@ struct usbnc_regs {
static void usb_oc_config(int index)
{
- struct usbnc_regs *usbnc = (struct usbnc_regs *)(USBOH3_USB_BASE_ADDR +
+ struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
USB_OTHERREGS_OFFSET);
void __iomem *ctrl = (void __iomem *)(usbnc-ctrl[index]);
u32 val;
@@ -207,7 +207,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
enum usb_init_type type;
- struct usb_ehci *ehci = (struct usb_ehci *)(USBOH3_USB_BASE_ADDR +
+ struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
(0x200 * index));
if (index 3)
--
1.7.4.1
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[U-Boot] [PATCH 2/2][v2] mpc85xx: configs - Add hash command in freescale platforms
Hardware accelerated support for SHA-1 and SHA-256 has been added. Hash command enabled along with hardware accelerated support for SHA-1 and SHA-256 for platforms which have CAAM block. Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com CC: York Sun york...@freescale.com --- Change log: v2: No change Fixed a typo in version number in the patch subject message. By mistake v3 was added instead of v2. The patch series is dependent on https://patchwork.ozlabs.org/patch/387174/ https://patchwork.ozlabs.org/patch/387175/ include/configs/B4860QDS.h | 4 include/configs/BSC9131RDB.h | 4 include/configs/BSC9132QDS.h | 4 include/configs/C29XPCIE.h | 4 include/configs/P1010RDB.h | 4 include/configs/P2041RDB.h | 4 include/configs/T1040QDS.h | 4 include/configs/T104xRDB.h | 4 include/configs/T208xQDS.h | 4 include/configs/T208xRDB.h | 4 include/configs/T4240QDS.h | 4 include/configs/T4240RDB.h | 4 include/configs/corenet_ds.h | 4 13 files changed, 52 insertions(+) diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 953d06b..58932ad 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -758,6 +758,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_NET #endif +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + /* * USB */ diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 56a3e94..fb50db0 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -382,6 +382,10 @@ extern unsigned long get_sdram_size(void); #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #endif +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + #define CONFIG_USB_EHCI #ifdef CONFIG_USB_EHCI diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index aeded6d..922ac00 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -598,6 +598,10 @@ combinations. this should be removed later #define CONFIG_DOS_PARTITION #endif +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + /* * Miscellaneous configurable options */ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 715616d..ca1b2f5 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -506,6 +506,10 @@ #define CONFIG_CMD_SETEXPR #define CONFIG_CMD_REGINFO +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + /* * Miscellaneous configurable options */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index a373990..45ef53d 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -832,6 +832,10 @@ extern unsigned long get_sdram_size(void); #define CONFIG_DOS_PARTITION #endif +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + /* * Miscellaneous configurable options */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 16f7525..7ff2dd5 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -647,6 +647,10 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_DOS_PARTITION #endif +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + /* * Miscellaneous configurable options */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index a781ba3..5870a49 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -716,6 +716,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_NET #endif +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + /* * Miscellaneous configurable options */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 0ee0ff2..8e43931 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -727,6 +727,10 @@ #define CONFIG_CMD_NET #endif +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + /* * Miscellaneous configurable options */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 395472b..9a8a3b6 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -777,6 +777,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_NET #endif +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + /* * Miscellaneous configurable options */ diff --git a/include/configs/T208xRDB.h
Re: [U-Boot] [PATCH] test: dfu: script: wrong md5sum on nand partitions
Hi Heiko, Hello Stephen, add Lukasz to Cc ... Am 12.09.2014 16:53, schrieb Stephen Warren: On 09/12/2014 12:27 AM, Heiko Schocher wrote: when uplaoding a file, at least from a nand partition, the complete mtd nand partition size is transferred. This leads in a wrong md5sum as the filesize is different between the downloaded file and the uploaded file. Limit the uploaded filesize to the downloaded fixes this. I was going to say that it'd be better to fix U-Boot's NAND code to transfer the correct amount of data. However, I suppose the correct amount *is* the whole partition for anything other than a filesystem file. As such, I'd suggest replacing nand in the patch description with something else, since presumably the exact same issue applies to partitions on eMMC. The issue applies to any partition. Yes, you are right. It is the case with testing raw/partition write. With NAND the procedure is as follows: 1. Erase NAND (0xFF on the whole partition) 2. Store the new partition (very rarely the partition.img == NAND partition size). Very often partition.img NAND partition. 3. The NAND code reads the whole partition (including the 0xFF padding). This padding causes md5sum to be wrong. I wonder if there's a way to distinguish between file tests and partition tests in dfu_gadget_test.sh, so that the $N_FILE_FULL - $N_FILE conversion can be applied only for partitions. Otherwise, a file upload/download test could end up changing (increasing) the file length and this bug wouldn't be detected. Lukasz could better comment on this ... currently filesize is changed on a raw partition, as the test download for example 960 bytes, and reads back the hole partition size ... which leads in a wrong md5sum. It would be good to have in the DFU protcol a length parameter ... so a device could at transfer start decide, if the filesize fits into the partition, if not, no need to tranfser the hole file, and detect this error at the end (with a broken partition now) ... Yes, the lack of size parameter is very inconvenient (for example we must then allocate bigger buffers than needed). However, for testing purposes we can introduce new test file name part_file_size.img - e.g. part_32M.img. Then this would indicate the test for the whole partition. The legacy dat_file_size.img (e.g. dat_960.img) would be truncated if needed in the script. This is a quick solution. Other thoughts: 1. In the dfu-util repo there is the dfu-prefix tool. It allows generating some special prefix for LPC and TI Stellaris SoCs. Maybe we could think about u-boot prefix and put there for example binary size and signature data. 2. The dfu-util 0.7 on the HOST when -l is typed shows the name= and serial=. If it was possible to add serial, then we could extend dfu-util to show size of the alt setting. In this way we could always perform truncation on the uploaded file in the host. bye, Heiko -- Best regards, Lukasz Majewski Samsung RD Institute Poland (SRPOL) | Linux Platform Group ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mtd: atmel_nand: Disable subpage NAND write when using Atmel PMECC
Hi, Boris On 9/2/2014 4:23 PM, Boris BREZILLON wrote: Disable subpage write when using PMECC to prevent buggy partial page write. This fix has been taken from linux sources (see commit 90445ff6241e2a13445310803e2efa606c61f276) Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com Sorry for the later reply. And Acked-by: Josh Wu josh...@atmel.com Best Regards, Josh Wu --- Hi, Here is a link to the linux commit: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/drivers/mtd/nand/atmel_nand.c?id=90445ff6241e2a13445310803e2efa606c61f276 Best Regards, Boris drivers/mtd/nand/atmel_nand.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index e73834d..ee67662 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -881,6 +881,7 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand, return -ENOMEM; } + nand-options |= NAND_NO_SUBPAGE_WRITE; nand-ecc.read_page = atmel_nand_pmecc_read_page; nand-ecc.write_page = atmel_nand_pmecc_write_page; nand-ecc.strength = cap; ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/2] usb: dfu: add fullspeed support for DFU
Hi Heiko, DFU now can use also fullspeed. Applied to u-boot-dfu -- Best regards, Lukasz Majewski Samsung RD Institute Poland (SRPOL) | Linux Platform Group ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/2] arm: am335x: siemens board use in DFU mode fullspeed only
Hi Heiko, Siemens boards are now using DFU in fullspeed only. For this CONFIG_USB_GADGET_DUALSPEED is undefined. Applied to u-boot-dfu -- Best regards, Lukasz Majewski Samsung RD Institute Poland (SRPOL) | Linux Platform Group ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] usb: dfu: thor: gadget: Remove dead code
Hi Lukasz, This code is not used anymore in the current DFU implementation and can be safely removed. Applied to u-boot-dfu -- Best regards, Lukasz Majewski Samsung RD Institute Poland (SRPOL) | Linux Platform Group ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] test: dfu: script: wrong md5sum on nand partitions
Hello Lukasz, Am 15.09.2014 11:45, schrieb Lukasz Majewski: Hi Heiko, Hello Stephen, add Lukasz to Cc ... Am 12.09.2014 16:53, schrieb Stephen Warren: On 09/12/2014 12:27 AM, Heiko Schocher wrote: when uplaoding a file, at least from a nand partition, the complete mtd nand partition size is transferred. This leads in a wrong md5sum as the filesize is different between the downloaded file and the uploaded file. Limit the uploaded filesize to the downloaded fixes this. I was going to say that it'd be better to fix U-Boot's NAND code to transfer the correct amount of data. However, I suppose the correct amount *is* the whole partition for anything other than a filesystem file. As such, I'd suggest replacing nand in the patch description with something else, since presumably the exact same issue applies to partitions on eMMC. The issue applies to any partition. Yes, you are right. It is the case with testing raw/partition write. With NAND the procedure is as follows: 1. Erase NAND (0xFF on the whole partition) 2. Store the new partition (very rarely the partition.img == NAND partition size). Very often partition.img NAND partition. 3. The NAND code reads the whole partition (including the 0xFF padding). This padding causes md5sum to be wrong. Yes. I wonder if there's a way to distinguish between file tests and partition tests in dfu_gadget_test.sh, so that the $N_FILE_FULL - $N_FILE conversion can be applied only for partitions. Otherwise, a file upload/download test could end up changing (increasing) the file length and this bug wouldn't be detected. Lukasz could better comment on this ... currently filesize is changed on a raw partition, as the test download for example 960 bytes, and reads back the hole partition size ... which leads in a wrong md5sum. It would be good to have in the DFU protcol a length parameter ... so a device could at transfer start decide, if the filesize fits into the partition, if not, no need to tranfser the hole file, and detect this error at the end (with a broken partition now) ... Yes, the lack of size parameter is very inconvenient (for example we must then allocate bigger buffers than needed). However, for testing purposes we can introduce new test file name part_file_size.img - e.g. part_32M.img. Then this would indicate the test for the whole partition. Hmm... yes, but I fear, that every board has different partition size, so we need a lot of files ... The legacy dat_file_size.img (e.g. dat_960.img) would be truncated if needed in the script. This is a quick solution. Yes ... I do not prefer this solution. Why not cutting the readden file to the length we transferred? Or fill the original file with 0xff until we reached the filesize we read from the device? Other thoughts: 1. In the dfu-util repo there is the dfu-prefix tool. It allows generating some special prefix for LPC and TI Stellaris SoCs. Maybe we could think about u-boot prefix and put there for example binary size and signature data. Hmm.. I do not like such special headers ... but this is just a personal opinion ... 2. The dfu-util 0.7 on the HOST when -l is typed shows the name= and serial=. If it was possible to add serial, then we could extend dfu-util to show size of the alt setting. [root@ts8 ~]# dfu-util -l dfu-util 0.7 Copyright 2005-2008 Weston Schmidt, Harald Welte and OpenMoko Inc. Copyright 2010-2012 Tormod Volden and Stefan Schmidt This program is Free Software and has ABSOLUTELY NO WARRANTY Please report bugs to dfu-u...@lists.gnumonks.org Found DFU: [0908:02c5] devnum=0, cfg=1, intf=0, alt=0, name=spl Found DFU: [0908:02c5] devnum=0, cfg=1, intf=0, alt=1, name=spl.backup1 Found DFU: [0908:02c5] devnum=0, cfg=1, intf=0, alt=2, name=spl.backup2 Found DFU: [0908:02c5] devnum=0, cfg=1, intf=0, alt=3, name=spl.backup3 Found DFU: [0908:02c5] devnum=0, cfg=1, intf=0, alt=4, name=u-boot Found DFU: [0908:02c5] devnum=0, cfg=1, intf=0, alt=5, name=kernel_a Found DFU: [0908:02c5] devnum=0, cfg=1, intf=0, alt=6, name=kernel_b Found DFU: [0908:02c5] devnum=0, cfg=1, intf=0, alt=7, name=rootfs [root@ts8 ~]# I do not see serial= for the siemens boards ... But if we could add here a size, that would be a good thing to have, so we coud at least read the size, and if our image fits not in it, break the transfer, before starting it ... and for the test script, we could read the size, and create a file, which fits into the partition ... In this way we could always perform truncation on the uploaded file in the host. bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 05/35] mmc: dw_mmc: cleanups
From: Pavel Machek pa...@denx.de
The dw_mmc driver was responding to errors with debug(). Change that
to prinf()/puts() respectively so that any errors are immediately
obvious. Also adjust english in comments.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
Cc: Pantelis Antoniou pa...@antoniou-consulting.com
---
drivers/mmc/dw_mmc.c | 26 ++
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 0df30bc..f4a6b88 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -119,7 +119,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd
*cmd,
while (dwmci_readl(host, DWMCI_STATUS) DWMCI_BUSY) {
if (get_timer(start) timeout) {
- printf(Timeout on data busy\n);
+ printf(%s: Timeout on data busy\n, __func__);
return TIMEOUT;
}
}
@@ -177,14 +177,16 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd
*cmd,
}
}
- if (i == retry)
+ if (i == retry) {
+ printf(%s: Timeout.\n, __func__);
return TIMEOUT;
+ }
if (mask DWMCI_INTMSK_RTO) {
- debug(Response Timeout..\n);
+ printf(%s: Response Timeout.\n, __func__);
return TIMEOUT;
} else if (mask DWMCI_INTMSK_RE) {
- debug(Response Error..\n);
+ printf(%s: Response Error.\n, __func__);
return -1;
}
@@ -204,7 +206,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd
*cmd,
do {
mask = dwmci_readl(host, DWMCI_RINTSTS);
if (mask (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
- debug(DATA ERROR!\n);
+ printf(%s: DATA ERROR!\n, __func__);
return -1;
}
} while (!(mask DWMCI_INTMSK_DTO));
@@ -232,16 +234,16 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32
freq)
if ((freq == host-clock) || (freq == 0))
return 0;
/*
-* If host-get_mmc_clk didn't define,
+* If host-get_mmc_clk isn't defined,
* then assume that host-bus_hz is source clock value.
-* host-bus_hz should be set from user.
+* host-bus_hz should be set by user.
*/
if (host-get_mmc_clk)
sclk = host-get_mmc_clk(host);
else if (host-bus_hz)
sclk = host-bus_hz;
else {
- printf(Didn't get source clock value..\n);
+ printf(%s: Didn't get source clock value.\n, __func__);
return -EINVAL;
}
@@ -260,7 +262,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32
freq)
do {
status = dwmci_readl(host, DWMCI_CMD);
if (timeout-- 0) {
- printf(TIMEOUT error!!\n);
+ printf(%s: Timeout!\n, __func__);
return -ETIMEDOUT;
}
} while (status DWMCI_CMD_START);
@@ -275,7 +277,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32
freq)
do {
status = dwmci_readl(host, DWMCI_CMD);
if (timeout-- 0) {
- printf(TIMEOUT error!!\n);
+ printf(%s: Timeout!\n, __func__);
return -ETIMEDOUT;
}
} while (status DWMCI_CMD_START);
@@ -290,7 +292,7 @@ static void dwmci_set_ios(struct mmc *mmc)
struct dwmci_host *host = (struct dwmci_host *)mmc-priv;
u32 ctype, regs;
- debug(Buswidth = %d, clock: %d\n,mmc-bus_width, mmc-clock);
+ debug(Buswidth = %d, clock: %d\n, mmc-bus_width, mmc-clock);
dwmci_setup_bus(host, mmc-clock);
switch (mmc-bus_width) {
@@ -329,7 +331,7 @@ static int dwmci_init(struct mmc *mmc)
dwmci_writel(host, DWMCI_PWREN, 1);
if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
- debug(%s[%d] Fail-reset!!\n,__func__,__LINE__);
+ printf(%s[%d] Fail-reset!!\n, __func__, __LINE__);
return -1;
}
--
2.1.0
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[U-Boot] [PATCH 01/35] net: Remove unused CONFIG_DW_SEARCH_PHY from configs
From: Pavel Machek pa...@denx.de Remove this symbol from configs, since it's unused. Signed-off-by: Pavel Machek pa...@denx.de Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@altera.com Cc: Dinh Nguyen dingu...@altera.com Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Rini tr...@ti.com Cc: Wolfgang Denk w...@denx.de Cc: Pavel Machek pa...@denx.de Cc: Joe Hershberger joe.hershber...@gmail.com --- include/configs/axs101.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/axs101.h b/include/configs/axs101.h index c22d6d0..1bf8390 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs101.h @@ -125,7 +125,6 @@ */ #define CONFIG_DESIGNWARE_ETH #define CONFIG_DW_AUTONEG -#define CONFIG_DW_SEARCH_PHY #define CONFIG_NET_MULTI /* -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 08/35] arm: socfpga: Complete the list of base addresses
From: Pavel Machek pa...@denx.de Add base addresses for all subsystems as documented in the Cyclone V HPS documentation. Signed-off-by: Pavel Machek pa...@denx.de Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@altera.com Cc: Dinh Nguyen dingu...@altera.com Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Rini tr...@ti.com Cc: Wolfgang Denk w...@denx.de Cc: Pavel Machek pa...@denx.de --- .../include/asm/arch-socfpga/socfpga_base_addrs.h | 40 ++ 1 file changed, 40 insertions(+) diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h index 2d3152d..cb062ac 100644 --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -7,16 +7,56 @@ #ifndef _SOCFPGA_BASE_ADDRS_H_ #define _SOCFPGA_BASE_ADDRS_H_ +#define SOCFPGA_SDMMC_ADDRESS 0xff704000 +#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xff706000 #define SOCFPGA_L3REGS_ADDRESS 0xff80 +#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffb9 #define SOCFPGA_UART0_ADDRESS 0xffc02000 #define SOCFPGA_UART1_ADDRESS 0xffc03000 +#define SOCFPGA_SDR_ADDRESS 0xffc2 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd0 +#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd01000 #define SOCFPGA_L4WD0_ADDRESS 0xffd02000 +#define SOCFPGA_L4WD1_ADDRESS 0xffd03000 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 #define SOCFPGA_SCANMGR_ADDRESS 0xfff02000 #define SOCFPGA_EMAC0_ADDRESS 0xff70 #define SOCFPGA_EMAC1_ADDRESS 0xff702000 +#define SOCFPGA_MPUL2_ADDRESS 0xfffef000 +#define SOCFPGA_MPUSCU_ADDRESS 0xfffec000 +#define SOCFPGA_STM_ADDRESS 0xfc00 +#define SOCFPGA_DAP_ADDRESS 0xff00 +#define SOCFPGA_LWFPGASLAVES_ADDRESS 0xff20 +#define SOCFPGA_LWHPS2FPGAREGS_ADDRESS 0xff40 +#define SOCFPGA_HPS2FPGAREGS_ADDRESS 0xff50 +#define SOCFPGA_FPGA2HPSREGS_ADDRESS 0xff60 +#define SOCFPGA_QSPI_ADDRESS 0xff705000 +#define SOCFPGA_ACPIDMAP_ADDRESS 0xff707000 +#define SOCFPGA_GPIO0_ADDRESS 0xff708000 +#define SOCFPGA_GPIO1_ADDRESS 0xff709000 +#define SOCFPGA_GPIO2_ADDRESS 0xff70a000 +#define SOCFPGA_NANDDATA_ADDRESS 0xff90 +#define SOCFPGA_QSPIDATA_ADDRESS 0xffa0 +#define SOCFPGA_USB0_ADDRESS 0xffb0 +#define SOCFPGA_USB1_ADDRESS 0xffb4 +#define SOCFPGA_NANDREGS_ADDRESS 0xffb8 +#define SOCFPGA_CAN0_ADDRESS 0xffc0 +#define SOCFPGA_CAN1_ADDRESS 0xffc01000 +#define SOCFPGA_I2C0_ADDRESS 0xffc04000 +#define SOCFPGA_I2C1_ADDRESS 0xffc05000 +#define SOCFPGA_I2C2_ADDRESS 0xffc06000 +#define SOCFPGA_I2C3_ADDRESS 0xffc07000 +#define SOCFPGA_SPTIMER0_ADDRESS 0xffc08000 +#define SOCFPGA_SPTIMER1_ADDRESS 0xffc09000 +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffe0 +#define SOCFPGA_DMASECURE_ADDRESS 0xffe01000 +#define SOCFPGA_SPIS0_ADDRESS 0xffe02000 +#define SOCFPGA_SPIS1_ADDRESS 0xffe03000 +#define SOCFPGA_SPIM0_ADDRESS 0xfff0 +#define SOCFPGA_SPIM1_ADDRESS 0xfff01000 +#define SOCFPGA_ROM_ADDRESS 0xfffd +#define SOCFPGA_OCRAM_ADDRESS 0x #endif /* _SOCFPGA_BASE_ADDRS_H_ */ -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 04/35] net: dwc: Make the cache handling less cryptic
Add a few new variables to make the cache handling less cryptic.
Add a variable for DMA and DATA descriptor start and end, so the
correctness of the code is easier to inspect.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
Cc: Joe Hershberger joe.hershber...@gmail.com
---
drivers/net/designware.c | 48 +++-
1 file changed, 23 insertions(+), 25 deletions(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index aaf146d..9ded895 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -279,19 +279,21 @@ static int dw_eth_send(struct eth_device *dev, void
*packet, int length)
struct eth_dma_regs *dma_p = priv-dma_regs_p;
u32 desc_num = priv-tx_currdescnum;
struct dmamacdescr *desc_p = priv-tx_mac_descrtable[desc_num];
-
+ uint32_t desc_start = (uint32_t)desc_p;
+ uint32_t desc_end = desc_start +
+ roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
+ uint32_t data_start = (uint32_t)desc_p-dmamac_addr;
+ uint32_t data_end = data_start +
+ roundup(length, ARCH_DMA_MINALIGN);
/*
* Strictly we only need to invalidate the txrx_status field
* for the following check, but on some platforms we cannot
-* invalidate only 4 bytes, so roundup to
-* ARCH_DMA_MINALIGN. This is safe because the individual
-* descriptors in the array are each aligned to
-* ARCH_DMA_MINALIGN.
+* invalidate only 4 bytes, so we flush the entire descriptor,
+* which is 16 bytes in total. This is safe because the
+* individual descriptors in the array are each aligned to
+* ARCH_DMA_MINALIGN and padded appropriately.
*/
- invalidate_dcache_range(
- (unsigned long)desc_p,
- (unsigned long)desc_p +
- roundup(sizeof(desc_p-txrx_status), ARCH_DMA_MINALIGN));
+ invalidate_dcache_range(desc_start, desc_end);
/* Check if the descriptor is owned by CPU */
if (desc_p-txrx_status DESC_TXSTS_OWNBYDMA) {
@@ -299,12 +301,10 @@ static int dw_eth_send(struct eth_device *dev, void
*packet, int length)
return -1;
}
- memcpy((void *)desc_p-dmamac_addr, packet, length);
+ memcpy(desc_p-dmamac_addr, packet, length);
/* Flush data to be sent */
- flush_dcache_range((unsigned long)desc_p-dmamac_addr,
- (unsigned long)desc_p-dmamac_addr +
- roundup(length, ARCH_DMA_MINALIGN));
+ flush_dcache_range(data_start, data_end);
#if defined(CONFIG_DW_ALTDESCRIPTOR)
desc_p-txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
@@ -322,8 +322,7 @@ static int dw_eth_send(struct eth_device *dev, void
*packet, int length)
#endif
/* Flush modified buffer descriptor */
- flush_dcache_range((unsigned long)desc_p,
- (unsigned long)desc_p + sizeof(struct dmamacdescr));
+ flush_dcache_range(desc_start, desc_end);
/* Test the wrap-around condition. */
if (++desc_num = CONFIG_TX_DESCR_NUM)
@@ -343,11 +342,14 @@ static int dw_eth_recv(struct eth_device *dev)
u32 status, desc_num = priv-rx_currdescnum;
struct dmamacdescr *desc_p = priv-rx_mac_descrtable[desc_num];
int length = 0;
+ uint32_t desc_start = (uint32_t)desc_p;
+ uint32_t desc_end = desc_start +
+ roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
+ uint32_t data_start = (uint32_t)desc_p-dmamac_addr;
+ uint32_t data_end;
/* Invalidate entire buffer descriptor */
- invalidate_dcache_range((unsigned long)desc_p,
- (unsigned long)desc_p +
- sizeof(struct dmamacdescr));
+ invalidate_dcache_range(desc_start, desc_end);
status = desc_p-txrx_status;
@@ -358,9 +360,8 @@ static int dw_eth_recv(struct eth_device *dev)
DESC_RXSTS_FRMLENSHFT;
/* Invalidate received data */
- invalidate_dcache_range((unsigned long)desc_p-dmamac_addr,
- (unsigned long)desc_p-dmamac_addr +
- roundup(length, ARCH_DMA_MINALIGN));
+ data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
+ invalidate_dcache_range(data_start, data_end);
NetReceive(desc_p-dmamac_addr, length);
@@ -371,10 +372,7 @@ static int dw_eth_recv(struct eth_device *dev)
desc_p-txrx_status |= DESC_RXSTS_OWNBYDMA;
/* Flush only status field - others weren't changed */
- flush_dcache_range((unsigned long)desc_p-txrx_status,
-
[U-Boot] [PATCH 09/35] arm: socfpga: Clean up base address file
Sort the list of functional block addresses and fix indentation. No functional change. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@altera.com Cc: Dinh Nguyen dingu...@altera.com Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Rini tr...@ti.com Cc: Wolfgang Denk w...@denx.de Cc: Pavel Machek pa...@denx.de --- .../include/asm/arch-socfpga/socfpga_base_addrs.h | 102 ++--- 1 file changed, 51 insertions(+), 51 deletions(-) diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h index cb062ac..6534283 100644 --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -7,56 +7,56 @@ #ifndef _SOCFPGA_BASE_ADDRS_H_ #define _SOCFPGA_BASE_ADDRS_H_ -#define SOCFPGA_SDMMC_ADDRESS 0xff704000 -#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xff706000 -#define SOCFPGA_L3REGS_ADDRESS 0xff80 -#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffb9 -#define SOCFPGA_UART0_ADDRESS 0xffc02000 -#define SOCFPGA_UART1_ADDRESS 0xffc03000 -#define SOCFPGA_SDR_ADDRESS 0xffc2 -#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd0 -#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd01000 -#define SOCFPGA_L4WD0_ADDRESS 0xffd02000 -#define SOCFPGA_L4WD1_ADDRESS 0xffd03000 -#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 -#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 -#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 -#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000 -#define SOCFPGA_EMAC0_ADDRESS 0xff70 -#define SOCFPGA_EMAC1_ADDRESS 0xff702000 -#define SOCFPGA_MPUL2_ADDRESS 0xfffef000 -#define SOCFPGA_MPUSCU_ADDRESS 0xfffec000 -#define SOCFPGA_STM_ADDRESS 0xfc00 -#define SOCFPGA_DAP_ADDRESS 0xff00 -#define SOCFPGA_LWFPGASLAVES_ADDRESS 0xff20 -#define SOCFPGA_LWHPS2FPGAREGS_ADDRESS 0xff40 -#define SOCFPGA_HPS2FPGAREGS_ADDRESS 0xff50 -#define SOCFPGA_FPGA2HPSREGS_ADDRESS 0xff60 -#define SOCFPGA_QSPI_ADDRESS 0xff705000 -#define SOCFPGA_ACPIDMAP_ADDRESS 0xff707000 -#define SOCFPGA_GPIO0_ADDRESS 0xff708000 -#define SOCFPGA_GPIO1_ADDRESS 0xff709000 -#define SOCFPGA_GPIO2_ADDRESS 0xff70a000 -#define SOCFPGA_NANDDATA_ADDRESS 0xff90 -#define SOCFPGA_QSPIDATA_ADDRESS 0xffa0 -#define SOCFPGA_USB0_ADDRESS 0xffb0 -#define SOCFPGA_USB1_ADDRESS 0xffb4 -#define SOCFPGA_NANDREGS_ADDRESS 0xffb8 -#define SOCFPGA_CAN0_ADDRESS 0xffc0 -#define SOCFPGA_CAN1_ADDRESS 0xffc01000 -#define SOCFPGA_I2C0_ADDRESS 0xffc04000 -#define SOCFPGA_I2C1_ADDRESS 0xffc05000 -#define SOCFPGA_I2C2_ADDRESS 0xffc06000 -#define SOCFPGA_I2C3_ADDRESS 0xffc07000 -#define SOCFPGA_SPTIMER0_ADDRESS 0xffc08000 -#define SOCFPGA_SPTIMER1_ADDRESS 0xffc09000 -#define SOCFPGA_DMANONSECURE_ADDRESS 0xffe0 -#define SOCFPGA_DMASECURE_ADDRESS 0xffe01000 -#define SOCFPGA_SPIS0_ADDRESS 0xffe02000 -#define SOCFPGA_SPIS1_ADDRESS 0xffe03000 -#define SOCFPGA_SPIM0_ADDRESS 0xfff0 -#define SOCFPGA_SPIM1_ADDRESS 0xfff01000 -#define SOCFPGA_ROM_ADDRESS 0xfffd -#define SOCFPGA_OCRAM_ADDRESS 0x +#define SOCFPGA_STM_ADDRESS0xfc00 +#define SOCFPGA_DAP_ADDRESS0xff00 +#define SOCFPGA_EMAC0_ADDRESS 0xff70 +#define SOCFPGA_EMAC1_ADDRESS 0xff702000 +#define SOCFPGA_SDMMC_ADDRESS 0xff704000 +#define SOCFPGA_QSPI_ADDRESS 0xff705000 +#define SOCFPGA_GPIO0_ADDRESS 0xff708000 +#define SOCFPGA_GPIO1_ADDRESS 0xff709000 +#define SOCFPGA_GPIO2_ADDRESS 0xff70a000 +#define SOCFPGA_L3REGS_ADDRESS 0xff80 +#define SOCFPGA_USB0_ADDRESS 0xffb0 +#define SOCFPGA_USB1_ADDRESS 0xffb4 +#define SOCFPGA_CAN0_ADDRESS 0xffc0 +#define SOCFPGA_CAN1_ADDRESS 0xffc01000 +#define SOCFPGA_UART0_ADDRESS 0xffc02000 +#define SOCFPGA_UART1_ADDRESS 0xffc03000 +#define SOCFPGA_I2C0_ADDRESS 0xffc04000 +#define SOCFPGA_I2C1_ADDRESS 0xffc05000 +#define SOCFPGA_I2C2_ADDRESS 0xffc06000 +#define SOCFPGA_I2C3_ADDRESS 0xffc07000 +#define SOCFPGA_SDR_ADDRESS0xffc2 +#define SOCFPGA_L4WD0_ADDRESS 0xffd02000 +#define SOCFPGA_L4WD1_ADDRESS 0xffd03000 +#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 +#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 +#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 +#define SOCFPGA_SPIS0_ADDRESS 0xffe02000 +#define SOCFPGA_SPIS1_ADDRESS 0xffe03000 +#define SOCFPGA_SPIM0_ADDRESS 0xfff0 +#define SOCFPGA_SPIM1_ADDRESS 0xfff01000 +#define SOCFPGA_SCANMGR_ADDRESS0xfff02000 +#define SOCFPGA_ROM_ADDRESS0xfffd +#define SOCFPGA_MPUSCU_ADDRESS 0xfffec000 +#define SOCFPGA_MPUL2_ADDRESS 0xfffef000 +#define SOCFPGA_OCRAM_ADDRESS 0x +#define SOCFPGA_LWFPGASLAVES_ADDRESS 0xff20 +#define SOCFPGA_LWHPS2FPGAREGS_ADDRESS 0xff40 +#define SOCFPGA_HPS2FPGAREGS_ADDRESS 0xff50
[U-Boot] [PATCH 00/35][RFC] arm: socfpga: Usability fixes
This entire RFC series is the first stab at making SoCFPGA usable with mainline U-Boot again. There are still some bits missing, but in general, this allows me to use mainline U-Boot on my SoCFPGA systems. The big missing part is the SPL generation, which still needs a lot of additional work. This set contains patches for a few subsystems, bu the most part is the SoCFPGA chip support. Most of the patches should be in good shape already, so I wonder if the RFC tag is really necessary. Charles Manning (1): tools: socfpga: Add socfpga preloader signing to mkimage Marek Vasut (21): net: dwc: Fix cache alignment issues net: dwc: Make the cache handling less cryptic mmc: dw_mmc: Fix cache alignment issue arm: socfpga: Clean up base address file arm: socfpga: sysmgr: Clean up system manager arm: socfpga: clock: Implant order into bit definitions arm: socfpga: clock: Drop nonsense inlining from clock manager code arm: socfpga: clock: Add missing stubs into board file arm: socfpga: clock: Trim down code duplication arm: socfpga: timer: Pull the timer reload value from config file arm: socfpga: reset: Add EMAC reset functions arm: socfpga: board: Align checkboard() output arm: socfpga: reset: Add function to reset FPGA bridges arm: socfpga: sysmgr: Add FPGA bits into system manager arm: cache: Add support for write-allocate D-Cache arm: socfpga: cache: Define cacheline size arm: socfpga: cache: Enable D-Cache arm: socfpga: cache: Enable PL310 L2 cache arm: socfpga: scu: Add SCU register file arm: socfpga: nic301: Add NIC-301 GPV register file arm: socfpga: pl310: Map SDRAM to 0x0 Pavel Machek (13): net: Remove unused CONFIG_DW_SEARCH_PHY from configs net: phy: Cleanup drivers/net/phy/micrel.c mmc: dw_mmc: cleanups arm: socfpga: Complete the list of base addresses arm: socfpga: Add watchdog disable for socfpga arm: socfpga: clock: Add code to read clock configuration arm: socfpga: mmc: Pick the clock from clock manager arm: socfpga: misc: Add proper ethernet initialization arm: socfpga: misc: Add SD controller init arm: socfpga: misc: Align print_cpuinfo() output arm: socfpga: board: Correctly set ATAG position arm: socfpga: fpga: Add SoCFPGA FPGA programming interface arm: socfpga: nic301: Add NIC-301 configuration code arch/arm/cpu/armv7/socfpga/Makefile| 3 +- arch/arm/cpu/armv7/socfpga/clock_manager.c | 218 - arch/arm/cpu/armv7/socfpga/fpga_manager.c | 354 + arch/arm/cpu/armv7/socfpga/misc.c | 144 - arch/arm/cpu/armv7/socfpga/reset_manager.c | 72 + arch/arm/cpu/armv7/socfpga/system_manager.c| 57 +++- arch/arm/cpu/armv7/socfpga/timer.c | 2 + arch/arm/include/asm/arch-socfpga/clock_manager.h | 209 arch/arm/include/asm/arch-socfpga/fpga_manager.h | 77 + arch/arm/include/asm/arch-socfpga/nic301.h | 195 arch/arm/include/asm/arch-socfpga/reset_manager.h | 6 + arch/arm/include/asm/arch-socfpga/scu.h| 23 ++ .../include/asm/arch-socfpga/socfpga_base_addrs.h | 62 +++- arch/arm/include/asm/arch-socfpga/system_manager.h | 111 +-- arch/arm/include/asm/system.h | 1 + arch/arm/lib/cache-cp15.c | 2 + board/altera/socfpga/pll_config.h | 3 + board/altera/socfpga/socfpga_cyclone5.c| 7 +- common/image.c | 1 + drivers/fpga/altera.c | 21 ++ drivers/mmc/dw_mmc.c | 26 +- drivers/mmc/socfpga_dw_mmc.c | 15 +- drivers/net/designware.c | 46 +-- drivers/net/phy/micrel.c | 7 +- include/altera.h | 1 + include/configs/axs101.h | 1 - include/configs/socfpga_cyclone5.h | 9 +- include/dwmmc.h| 2 +- include/image.h| 1 + tools/Makefile | 1 + tools/imagetool.c | 2 + tools/imagetool.h | 1 + tools/socfpgaimage.c | 255 +++ 33 files changed, 1753 insertions(+), 182 deletions(-) create mode 100644 arch/arm/cpu/armv7/socfpga/fpga_manager.c create mode 100644 arch/arm/include/asm/arch-socfpga/fpga_manager.h create mode 100644 arch/arm/include/asm/arch-socfpga/nic301.h create mode 100644 arch/arm/include/asm/arch-socfpga/scu.h create mode 100644 tools/socfpgaimage.c Cc: Chin Liang See cl...@altera.com Cc: Dinh Nguyen dingu...@altera.com Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Rini tr...@ti.com Cc: Wolfgang Denk w...@denx.de Cc: Pavel Machek pa...@denx.de Cc: Joe Hershberger
[U-Boot] [PATCH 12/35] arm: socfpga: clock: Implant order into bit definitions
The bit definitions for clock manager are complete chaos. Implement
some basic logical order into them.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
arch/arm/include/asm/arch-socfpga/clock_manager.h | 166 +-
1 file changed, 99 insertions(+), 67 deletions(-)
diff --git a/arch/arm/include/asm/arch-socfpga/clock_manager.h
b/arch/arm/include/asm/arch-socfpga/clock_manager.h
index babac0e..dea171e 100644
--- a/arch/arm/include/asm/arch-socfpga/clock_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/clock_manager.h
@@ -103,96 +103,128 @@ struct socfpga_clock_manager {
u32 _pad_0xe0_0x200[72];
};
-#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x0200
+#define CLKMGR_CTRL_SAFEMODE_MASK 0x0001
+#define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) 0) 0x0001)
+
+#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) 0) 0x0001)
+#define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) 4) 0x0010)
+#define CLKMGR_BYPASS_PERPLL_SET(x) (((x) 3) 0x0008)
+#define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) 2) 0x0004)
+#define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) 1) 0x0002)
+
+#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x0040
+#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x0080
+#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x0100
+
+/* Main PLL */
+#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) 0) 0x0001)
+#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) 16) 0x003f)
+#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) 1) 0x0002)
+#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) 3) 0xfff8)
+#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x0100
+#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) 2) 0x0004)
+#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x8000
+#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
+
+#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) 0) 0x01ff)
+
+#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) 0) 0x01ff)
+
+#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) 0) 0x01ff)
+
+#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) 0) 0x01ff)
+
+#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) (((x) 0) 0x01ff)
+
+#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) (((x) 0) 0x01ff)
+
+#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x0010
+#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x0020
#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x0080
#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x0040
-#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x0020
-#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x0010
#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x0004
-#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
-#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
-#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
+#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x0200
+
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) 0) 0x0003)
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) 2) 0x000c)
#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) 4) 0x0070)
#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) 7) 0x0380)
+
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) 0) 0x0003)
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) 2) 0x000c)
+
+#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) 0) 0x0007)
+
#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) 0) 0x0001)
#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) 1) 0x0002)
-#define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) 4) 0x0030)
-#define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) 2) 0x000c)
-#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) 0) 0x0003)
-#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) 16) 0x003f)
-#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) 3) 0xfff8)
-#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) 2) 0x0004)
-#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) 1) 0x0002)
-#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) 0) 0x0001)
-#define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) 22) 0x00c0)
+#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x
+
+/* Per PLL */
#define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) 16) 0x003f)
#define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) 3) 0xfff8)
-#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) 25) 0x7e00)
-#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) 24) 0x0100)
-#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) 22) 0x00c0)
-#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) 16) 0x003f)
-#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) 3) 0xfff8)
-#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) 0) 0x01ff)
-#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) 0) 0x01ff)
-#define
[U-Boot] [PATCH 06/35] mmc: dw_mmc: Fix cache alignment issue
The DMA descriptors used by the DW MMC block must be aligned to cacheline
size, otherwise we are unable to properly flush/inval cache over them and
we get data corruption.
The reason I chose this approach of expanding the structure is because
the driver allocates the descriptors in bulk. This approach does waste
space by inserting slop inbetween the descriptors, but it makes access
to the descriptors easy as the compiler does know the real size of the
structure. It also makes cache operations easy, since the size of the
structure is cache aligned and the structure start address is as well.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
Cc: Pantelis Antoniou pa...@antoniou-consulting.com
---
include/dwmmc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/dwmmc.h b/include/dwmmc.h
index b67f11b..109f7c8 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -157,7 +157,7 @@ struct dwmci_idmac {
u32 cnt;
u32 addr;
u32 next_addr;
-};
+} __aligned(ARCH_DMA_MINALIGN);
static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val)
{
--
2.1.0
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[U-Boot] [PATCH 14/35] arm: socfpga: clock: Add missing stubs into board file
Add some stub defines, which are used by the clock code, but are missing from the auto-generated header file for the SoCFPGA family. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@altera.com Cc: Dinh Nguyen dingu...@altera.com Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Rini tr...@ti.com Cc: Wolfgang Denk w...@denx.de Cc: Pavel Machek pa...@denx.de --- board/altera/socfpga/pll_config.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/altera/socfpga/pll_config.h b/board/altera/socfpga/pll_config.h index 9bd0442..f0f59a9 100644 --- a/board/altera/socfpga/pll_config.h +++ b/board/altera/socfpga/pll_config.h @@ -94,6 +94,9 @@ /* Info for driver */ #define CONFIG_HPS_CLK_OSC1_HZ (2500) +#define CONFIG_HPS_CLK_OSC2_HZ 0 +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 #define CONFIG_HPS_CLK_MAINVCO_HZ (16) #define CONFIG_HPS_CLK_PERVCO_HZ (10) #ifdef CONFIG_SOCFPGA_ARRIA5 -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 10/35] arm: socfpga: Add watchdog disable for socfpga
From: Pavel Machek pa...@denx.de
This adds watchdog disable. It is neccessary for running Linux kernel.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
arch/arm/cpu/armv7/socfpga/misc.c | 4
arch/arm/cpu/armv7/socfpga/reset_manager.c| 13 +
arch/arm/include/asm/arch-socfpga/reset_manager.h | 2 ++
3 files changed, 19 insertions(+)
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c
b/arch/arm/cpu/armv7/socfpga/misc.c
index ecae393..15cd8c2 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -8,6 +8,7 @@
#include asm/io.h
#include miiphy.h
#include netdev.h
+#include asm/arch/reset_manager.h
DECLARE_GLOBAL_DATA_PTR;
@@ -38,6 +39,9 @@ int overwrite_console(void)
int misc_init_r(void)
{
+ /* This is needed, otherwise kernel is rebooted by watchdog. */
+ watchdog_disable();
+
return 0;
}
diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c
b/arch/arm/cpu/armv7/socfpga/reset_manager.c
index e320c01..07b8c4f 100644
--- a/arch/arm/cpu/armv7/socfpga/reset_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c
@@ -14,6 +14,19 @@ DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS;
+#define RSTMGR_PERMODRST_L4WD0_LSB 6
+
+/* Disable the watchdog (toggle reset to watchdog) */
+void watchdog_disable(void)
+{
+ /* assert reset for watchdog */
+ setbits_le32(reset_manager_base-per_mod_reset,
+(1RSTMGR_PERMODRST_L4WD0_LSB));
+ /* deassert watchdog from reset (watchdog in not running state) */
+ clrbits_le32(reset_manager_base-per_mod_reset,
+(1RSTMGR_PERMODRST_L4WD0_LSB));
+}
+
/*
* Write the reset manager register to cause reset
*/
diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h
b/arch/arm/include/asm/arch-socfpga/reset_manager.h
index 3e95476..e004343 100644
--- a/arch/arm/include/asm/arch-socfpga/reset_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h
@@ -10,6 +10,8 @@
void reset_cpu(ulong addr);
void reset_deassert_peripherals_handoff(void);
+void watchdog_disable(void);
+
struct socfpga_reset_manager {
u32 status;
u32 ctrl;
--
2.1.0
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[U-Boot] [PATCH 03/35] net: dwc: Fix cache alignment issues
Fix remaining cache alignment issues in the DWC Ethernet driver. Please note that the cache handling in the driver is making the code hideous and thus the next patch cleans that up. In order to make this change reviewable though, the cleanup is split from it. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@altera.com Cc: Dinh Nguyen dingu...@altera.com Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Rini tr...@ti.com Cc: Wolfgang Denk w...@denx.de Cc: Pavel Machek pa...@denx.de Cc: Joe Hershberger joe.hershber...@gmail.com --- drivers/net/designware.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 7186e3b..aaf146d 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -303,7 +303,8 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) /* Flush data to be sent */ flush_dcache_range((unsigned long)desc_p-dmamac_addr, - (unsigned long)desc_p-dmamac_addr + length); + (unsigned long)desc_p-dmamac_addr + + roundup(length, ARCH_DMA_MINALIGN)); #if defined(CONFIG_DW_ALTDESCRIPTOR) desc_p-txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; @@ -372,7 +373,8 @@ static int dw_eth_recv(struct eth_device *dev) /* Flush only status field - others weren't changed */ flush_dcache_range((unsigned long)desc_p-txrx_status, (unsigned long)desc_p-txrx_status + - sizeof(desc_p-txrx_status)); + roundup(sizeof(desc_p-txrx_status), + ARCH_DMA_MINALIGN)); /* Test the wrap-around condition. */ if (++desc_num = CONFIG_RX_DESCR_NUM) -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 16/35] arm: socfpga: clock: Trim down code duplication
Pull out functions to read frequency of Main clock VCO and
PLL clock VCO as the code is duplicated multiple times.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
arch/arm/cpu/armv7/socfpga/clock_manager.c | 96 --
1 file changed, 38 insertions(+), 58 deletions(-)
diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c
b/arch/arm/cpu/armv7/socfpga/clock_manager.c
index 07cf74c..1ab62e7 100644
--- a/arch/arm/cpu/armv7/socfpga/clock_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c
@@ -361,7 +361,7 @@ void cm_basic_init(const cm_config_t *cfg)
writel(~0, clock_manager_base-sdr_pll.en);
}
-unsigned long cm_get_mpu_clk_hz(void)
+static unsigned int cm_get_main_vco_clk_hz(void)
{
uint32_t reg, clock;
@@ -371,6 +371,37 @@ unsigned long cm_get_mpu_clk_hz(void)
(CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
+ return clock;
+}
+
+static unsigned int cm_get_per_vco_clk_hz(void)
+{
+ uint32_t reg, clock = 0;
+
+ /* identify PER PLL clock source */
+ reg = readl(clock_manager_base-per_pll.vco);
+ reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
+ if (reg == CLKMGR_VCO_SSRC_EOSC1)
+ clock = CONFIG_HPS_CLK_OSC1_HZ;
+ else if (reg == CLKMGR_VCO_SSRC_EOSC2)
+ clock = CONFIG_HPS_CLK_OSC2_HZ;
+ else if (reg == CLKMGR_VCO_SSRC_F2S)
+ clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+
+ /* get the PER VCO clock */
+ reg = readl(clock_manager_base-per_pll.vco);
+ clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1);
+ clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1);
+
+ return clock;
+}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+ uint32_t reg, clock;
+
+ clock = cm_get_main_vco_clk_hz();
+
/* get the MPU clock */
reg = readl(clock_manager_base-altera.mpuclk);
clock /= (reg + 1);
@@ -415,11 +446,7 @@ unsigned int cm_get_l4_sp_clk_hz(void)
reg = CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(reg);
if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
- /* get the main VCO clock */
- reg = readl(clock_manager_base-main_pll.vco);
- clock = CONFIG_HPS_CLK_OSC1_HZ /
- (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
- clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
+ clock = cm_get_main_vco_clk_hz();
/* get the clock prior L4 SP divider (main clk) */
reg = readl(clock_manager_base-altera.mainclk);
@@ -427,20 +454,7 @@ unsigned int cm_get_l4_sp_clk_hz(void)
reg = readl(clock_manager_base-main_pll.mainclk);
clock /= (reg + 1);
} else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
- /* identify PER PLL clock source */
- reg = readl(clock_manager_base-per_pll.vco);
- reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
- if (reg == CLKMGR_VCO_SSRC_EOSC1)
- clock = CONFIG_HPS_CLK_OSC1_HZ;
- else if (reg == CLKMGR_VCO_SSRC_EOSC2)
- clock = CONFIG_HPS_CLK_OSC2_HZ;
- else if (reg == CLKMGR_VCO_SSRC_F2S)
- clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
-
- /* get the PER VCO clock */
- reg = readl(clock_manager_base-per_pll.vco);
- clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1);
- clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1);
+ clock = cm_get_per_vco_clk_hz();
/* get the clock prior L4 SP divider (periph_base_clk) */
reg = readl(clock_manager_base-per_pll.perbaseclk);
@@ -466,30 +480,13 @@ unsigned int cm_get_mmc_controller_clk_hz(void)
if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
} else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
- /* get the main VCO clock */
- reg = readl(clock_manager_base-main_pll.vco);
- clock = CONFIG_HPS_CLK_OSC1_HZ /
- (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
- clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
+ clock = cm_get_main_vco_clk_hz();
/* get the SDMMC clock */
reg = readl(clock_manager_base-main_pll.mainnandsdmmcclk);
clock /= (reg + 1);
} else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
- /* identify PER PLL clock source */
- reg = readl(clock_manager_base-per_pll.vco);
- reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
- if (reg == CLKMGR_VCO_SSRC_EOSC1)
-
[U-Boot] [PATCH 15/35] arm: socfpga: clock: Add code to read clock configuration
From: Pavel Machek pa...@denx.de
Add the entire bulk of code to read out clock configuration from the SoCFPGA
CPU registers. This is important for MMC, QSPI and UART drivers as otherwise
they cannot determine the frequency of their upstream clock.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
arch/arm/cpu/armv7/socfpga/clock_manager.c| 226 +-
arch/arm/include/asm/arch-socfpga/clock_manager.h | 43 +++-
include/configs/socfpga_cyclone5.h| 1 +
3 files changed, 267 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c
b/arch/arm/cpu/armv7/socfpga/clock_manager.c
index d032bbd..07cf74c 100644
--- a/arch/arm/cpu/armv7/socfpga/clock_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c
@@ -8,8 +8,10 @@
#include asm/io.h
#include asm/arch/clock_manager.h
+DECLARE_GLOBAL_DATA_PTR;
+
static const struct socfpga_clock_manager *clock_manager_base =
- (void *)SOCFPGA_CLKMGR_ADDRESS;
+ (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
#define CLKMGR_BYPASS_ENABLE 1
#define CLKMGR_BYPASS_DISABLE 0
@@ -358,3 +360,225 @@ void cm_basic_init(const cm_config_t *cfg)
writel(~0, clock_manager_base-per_pll.en);
writel(~0, clock_manager_base-sdr_pll.en);
}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+ uint32_t reg, clock;
+
+ /* get the main VCO clock */
+ reg = readl(clock_manager_base-main_pll.vco);
+ clock = CONFIG_HPS_CLK_OSC1_HZ /
+ (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
+ clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
+
+ /* get the MPU clock */
+ reg = readl(clock_manager_base-altera.mpuclk);
+ clock /= (reg + 1);
+ reg = readl(clock_manager_base-main_pll.mpuclk);
+ clock /= (reg + 1);
+ return clock;
+}
+
+unsigned long cm_get_sdram_clk_hz(void)
+{
+ uint32_t reg, clock = 0;
+
+ /* identify SDRAM PLL clock source */
+ reg = readl(clock_manager_base-sdr_pll.vco);
+ reg = CLKMGR_SDRPLLGRP_VCO_SSRC_GET(reg);
+ if (reg == CLKMGR_VCO_SSRC_EOSC1)
+ clock = CONFIG_HPS_CLK_OSC1_HZ;
+ else if (reg == CLKMGR_VCO_SSRC_EOSC2)
+ clock = CONFIG_HPS_CLK_OSC2_HZ;
+ else if (reg == CLKMGR_VCO_SSRC_F2S)
+ clock = CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
+
+ /* get the SDRAM VCO clock */
+ reg = readl(clock_manager_base-sdr_pll.vco);
+ clock /= (CLKMGR_SDRPLLGRP_VCO_DENOM_GET(reg) + 1);
+ clock *= (CLKMGR_SDRPLLGRP_VCO_NUMER_GET(reg) + 1);
+
+ /* get the SDRAM (DDR_DQS) clock */
+ reg = readl(clock_manager_base-sdr_pll.ddrdqsclk);
+ reg = CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_GET(reg);
+ clock /= (reg + 1);
+
+ return clock;
+}
+
+unsigned int cm_get_l4_sp_clk_hz(void)
+{
+ uint32_t reg, clock = 0;
+
+ /* identify the source of L4 SP clock */
+ reg = readl(clock_manager_base-main_pll.l4src);
+ reg = CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(reg);
+
+ if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
+ /* get the main VCO clock */
+ reg = readl(clock_manager_base-main_pll.vco);
+ clock = CONFIG_HPS_CLK_OSC1_HZ /
+ (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
+ clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
+
+ /* get the clock prior L4 SP divider (main clk) */
+ reg = readl(clock_manager_base-altera.mainclk);
+ clock /= (reg + 1);
+ reg = readl(clock_manager_base-main_pll.mainclk);
+ clock /= (reg + 1);
+ } else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
+ /* identify PER PLL clock source */
+ reg = readl(clock_manager_base-per_pll.vco);
+ reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
+ if (reg == CLKMGR_VCO_SSRC_EOSC1)
+ clock = CONFIG_HPS_CLK_OSC1_HZ;
+ else if (reg == CLKMGR_VCO_SSRC_EOSC2)
+ clock = CONFIG_HPS_CLK_OSC2_HZ;
+ else if (reg == CLKMGR_VCO_SSRC_F2S)
+ clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+
+ /* get the PER VCO clock */
+ reg = readl(clock_manager_base-per_pll.vco);
+ clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1);
+ clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1);
+
+ /* get the clock prior L4 SP divider (periph_base_clk) */
+ reg = readl(clock_manager_base-per_pll.perbaseclk);
+ clock /= (reg + 1);
+ }
+
+ /* get the L4 SP clock which supplied to UART */
+ reg =
[U-Boot] [PATCH 02/35] net: phy: Cleanup drivers/net/phy/micrel.c
From: Pavel Machek pa...@denx.de
Old saying says that more than three exclamation marks in a row are
sign of mental disease. Cleanup micrel.c.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
Cc: Joe Hershberger joe.hershber...@gmail.com
---
drivers/net/phy/micrel.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 5d7e3be..507b9a3 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -25,8 +25,7 @@ static struct phy_driver KSZ804_driver = {
#ifndef CONFIG_PHY_MICREL_KSZ9021
/*
* I can't believe Micrel used the exact same part number
- * for the KSZ9021
- * Shame Micrel, Shame!
+ * for the KSZ9021. Shame Micrel, Shame!
*/
static struct phy_driver KS8721_driver = {
.name = Micrel KS8721BL,
@@ -40,7 +39,7 @@ static struct phy_driver KS8721_driver = {
#endif
-/**
+/*
* KSZ9021 - KSZ9031 common
*/
@@ -69,8 +68,8 @@ static int ksz90xx_startup(struct phy_device *phydev)
phydev-speed = SPEED_10;
return 0;
}
-#ifdef CONFIG_PHY_MICREL_KSZ9021
+#ifdef CONFIG_PHY_MICREL_KSZ9021
/*
* KSZ9021
*/
--
2.1.0
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[U-Boot] [PATCH 18/35] arm: socfpga: timer: Pull the timer reload value from config file
The timer reload value is a property of the timer hardware and there is no reason for this to be configurable. Place this into the timer driver just like on the other hardware. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@altera.com Cc: Dinh Nguyen dingu...@altera.com Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Rini tr...@ti.com Cc: Wolfgang Denk w...@denx.de Cc: Pavel Machek pa...@denx.de --- arch/arm/cpu/armv7/socfpga/timer.c | 2 ++ include/configs/socfpga_cyclone5.h | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/socfpga/timer.c b/arch/arm/cpu/armv7/socfpga/timer.c index 58fc789..253cde3 100644 --- a/arch/arm/cpu/armv7/socfpga/timer.c +++ b/arch/arm/cpu/armv7/socfpga/timer.c @@ -8,6 +8,8 @@ #include asm/io.h #include asm/arch/timer.h +#define TIMER_LOAD_VAL 0x + static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE; /* diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 3b6cfb4..f50081b 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -195,8 +195,6 @@ /* This timer use eosc1 where the clock frequency is fixed * throughout any condition */ #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS -/* reload value when timer count to zero */ -#define TIMER_LOAD_VAL 0x /* Timer info */ #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_SYS_TIMER_RATE 240 -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 19/35] arm: socfpga: reset: Add EMAC reset functions
Add functions to reset the EMAC ethernet blocks. We cannot handle
two EMAC ethernet blocks yet, therefore the ifdefs. Once there is
hardware using both EMAC blocks, this ifdef will have to go.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
arch/arm/cpu/armv7/socfpga/reset_manager.c| 21 +
arch/arm/include/asm/arch-socfpga/reset_manager.h | 2 ++
2 files changed, 23 insertions(+)
diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c
b/arch/arm/cpu/armv7/socfpga/reset_manager.c
index 07b8c4f..77579b7 100644
--- a/arch/arm/cpu/armv7/socfpga/reset_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c
@@ -14,6 +14,8 @@ DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS;
+#define RSTMGR_PERMODRST_EMAC0_LSB 0
+#define RSTMGR_PERMODRST_EMAC1_LSB 1
#define RSTMGR_PERMODRST_L4WD0_LSB 6
/* Disable the watchdog (toggle reset to watchdog) */
@@ -50,3 +52,22 @@ void reset_deassert_peripherals_handoff(void)
{
writel(0, reset_manager_base-per_mod_reset);
}
+
+/* Change the reset state for EMAC 0 and EMAC 1 */
+void socfpga_emac_reset(int enable)
+{
+ const void *reset = reset_manager_base-per_mod_reset;
+
+ if (enable) {
+ setbits_le32(reset, 1 RSTMGR_PERMODRST_EMAC0_LSB);
+ setbits_le32(reset, 1 RSTMGR_PERMODRST_EMAC1_LSB);
+ } else {
+#if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS)
+ clrbits_le32(reset, 1 RSTMGR_PERMODRST_EMAC0_LSB);
+#elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS)
+ clrbits_le32(reset, 1 RSTMGR_PERMODRST_EMAC1_LSB);
+#else
+#error Incorrect CONFIG_EMAC_BASE value!
+#endif
+ }
+}
diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h
b/arch/arm/include/asm/arch-socfpga/reset_manager.h
index e004343..9d22576 100644
--- a/arch/arm/include/asm/arch-socfpga/reset_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h
@@ -10,6 +10,8 @@
void reset_cpu(ulong addr);
void reset_deassert_peripherals_handoff(void);
+void socfpga_emac_reset(int enable);
+
void watchdog_disable(void);
struct socfpga_reset_manager {
--
2.1.0
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[U-Boot] [PATCH 20/35] arm: socfpga: misc: Add proper ethernet initialization
From: Pavel Machek pa...@denx.de
Add function to initialize the EMAC blocks upon board startup.
The preprocessor guards against building on SoCFPGA-VT and against
SPL build are not needed as those are handled implicitly via both
SPL framework and the socfpga_cyclone5.h config file, which will
not define CONFIG_DESIGNWARE_ETH if building for SoCFPGA-VT.
We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs.
Once there is hardware using both EMAC blocks, this ifdef will have
to go.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
arch/arm/cpu/armv7/socfpga/misc.c | 58 --
arch/arm/include/asm/arch-socfpga/system_manager.h | 9
2 files changed, 52 insertions(+), 15 deletions(-)
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c
b/arch/arm/cpu/armv7/socfpga/misc.c
index 15cd8c2..ee7283b 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -9,15 +9,58 @@
#include miiphy.h
#include netdev.h
#include asm/arch/reset_manager.h
+#include asm/arch/system_manager.h
DECLARE_GLOBAL_DATA_PTR;
+static struct socfpga_system_manager *sysmgr_regs =
+ (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
int dram_init(void)
{
gd-ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
return 0;
}
+/*
+ * DesignWare Ethernet initialization
+ */
+#ifdef CONFIG_DESIGNWARE_ETH
+int cpu_eth_init(bd_t *bis)
+{
+#if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
+ const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
+#elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
+ const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
+#else
+#error Incorrect CONFIG_EMAC_BASE value!
+#endif
+
+ /* Initialize EMAC. This needs to be done at least once per boot. */
+
+ /*
+* Putting the EMAC controller to reset when configuring the PHY
+* interface select at System Manager
+*/
+ socfpga_emac_reset(1);
+
+ /* Clearing emac0 PHY interface select to 0 */
+ clrbits_le32(sysmgr_regs-emacgrp_ctrl,
+SYSMGR_EMACGRP_CTRL_PHYSEL_MASK physhift);
+
+ /* configure to PHY interface select choosed */
+ setbits_le32(sysmgr_regs-emacgrp_ctrl,
+SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII physhift);
+
+ /* Release the EMAC controller from reset */
+ socfpga_emac_reset(0);
+
+ /* initialize and register the emac */
+ return designware_initialize(CONFIG_EMAC_BASE,
+CONFIG_PHY_INTERFACE_MODE);
+}
+#endif
+
#if defined(CONFIG_DISPLAY_CPUINFO)
/*
* Print CPU information
@@ -44,18 +87,3 @@ int misc_init_r(void)
return 0;
}
-
-
-/*
- * DesignWare Ethernet initialization
- */
-int cpu_eth_init(bd_t *bis)
-{
-#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) !defined(CONFIG_SPL_BUILD)
- /* initialize and register the emac */
- return designware_initialize(CONFIG_EMAC_BASE,
-CONFIG_PHY_INTERFACE_MODE);
-#else
- return 0;
-#endif
-}
diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h
b/arch/arm/include/asm/arch-socfpga/system_manager.h
index 90d2720..071ec4f 100644
--- a/arch/arm/include/asm/arch-socfpga/system_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/system_manager.h
@@ -134,4 +134,13 @@ struct socfpga_system_manager {
#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
drvsel) 0) 0x7) | (((smplsel) 3) 0x38))
+/* EMAC Group Bit definitions */
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
+
+#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB2
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK0x3
+
#endif /* _SYSTEM_MANAGER_H_ */
--
2.1.0
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[U-Boot] [PATCH 07/35] tools: socfpga: Add socfpga preloader signing to mkimage
From: Charles Manning cdhmann...@gmail.com
Like many platforms, the Altera socfpga platform requires that the
preloader be signed in a certain way or the built-in boot ROM will
not boot the code.
This change automatically creates an appropriately signed preloader
from an SPL image.
The signed image includes a CRC which must, of course, be generated
with a CRC generator that the SoCFPGA boot ROM agrees with otherwise
the boot ROM will reject the image.
Unfortunately the CRC used in this boot ROM is not the same as the
Adler CRC in lib/crc32.c. Indeed the Adler code is not technically a
CRC but is more correctly described as a checksum.
Thus, the appropriate CRC generator is added to lib/ as crc32_alt.c.
Signed-off-by: Charles Manning cdhmann...@gmail.com
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
common/image.c | 1 +
include/image.h | 1 +
tools/Makefile | 1 +
tools/imagetool.c| 2 +
tools/imagetool.h| 1 +
tools/socfpgaimage.c | 255 +++
6 files changed, 261 insertions(+)
create mode 100644 tools/socfpgaimage.c
diff --git a/common/image.c b/common/image.c
index 38b56e3..085771c 100644
--- a/common/image.c
+++ b/common/image.c
@@ -138,6 +138,7 @@ static const table_entry_t uimage_type[] = {
{ IH_TYPE_PBLIMAGE, pblimage, Freescale PBL Boot Image,},
{ IH_TYPE_RAMDISK,ramdisk,RAMDisk Image, },
{ IH_TYPE_SCRIPT, script, Script, },
+ { IH_TYPE_SOCFPGAIMAGE, socfpgaimage, Altera SOCFPGA
preloader,},
{ IH_TYPE_STANDALONE, standalone, Standalone Program, },
{ IH_TYPE_UBLIMAGE, ublimage, Davinci UBL image,},
{ IH_TYPE_MXSIMAGE, mxsimage, Freescale MXS Boot Image,},
diff --git a/include/image.h b/include/image.h
index 3401056..4347532 100644
--- a/include/image.h
+++ b/include/image.h
@@ -232,6 +232,7 @@ struct lmb;
#define IH_TYPE_MXSIMAGE 16 /* Freescale MXSBoot Image */
#define IH_TYPE_GPIMAGE17 /* TI Keystone GPHeader Image
*/
#define IH_TYPE_ATMELIMAGE 18 /* ATMEL ROM bootable Image */
+#define IH_TYPE_SOCFPGAIMAGE 19 /* Altera SOCFPGA Preloader */
/*
* Compression Types
diff --git a/tools/Makefile b/tools/Makefile
index 90e966d..2b05b20 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -87,6 +87,7 @@ dumpimage-mkimage-objs := aisimage.o \
os_support.o \
pblimage.o \
pbl_crc32.o \
+ socfpgaimage.o \
lib/sha1.o \
lib/sha256.o \
ublimage.o \
diff --git a/tools/imagetool.c b/tools/imagetool.c
index 32d6278..98717bd 100644
--- a/tools/imagetool.c
+++ b/tools/imagetool.c
@@ -47,6 +47,8 @@ void register_image_tool(imagetool_register_t image_register)
init_ubl_image_type();
/* Init Davinci AIS support */
init_ais_image_type();
+ /* Init Altera SOCFPGA support */
+ init_socfpga_image_type();
/* Init TI Keystone boot image generation/list support */
init_gpimage_type();
}
diff --git a/tools/imagetool.h b/tools/imagetool.h
index c8af0e8..8bce059 100644
--- a/tools/imagetool.h
+++ b/tools/imagetool.h
@@ -168,6 +168,7 @@ void init_mxs_image_type(void);
void init_fit_image_type(void);
void init_ubl_image_type(void);
void init_omap_image_type(void);
+void init_socfpga_image_type(void);
void init_gpimage_type(void);
void pbl_load_uboot(int fd, struct image_tool_params *mparams);
diff --git a/tools/socfpgaimage.c b/tools/socfpgaimage.c
new file mode 100644
index 000..32fa09f
--- /dev/null
+++ b/tools/socfpgaimage.c
@@ -0,0 +1,255 @@
+/*
+ * Copyright (C) 2014 Charles Manning cdhmann...@gmail.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * Reference doc http://www.altera.com.cn/literature/hb/cyclone-v/cv_5400A.pdf
+ * Note this doc is not entirely accurate. Of particular interest to us is the
+ * header length field being in U32s and not bytes.
+ *
+ * Header is a structure of the following format.
+ * this is positioned at 0x40.
+ *
+ * Endian is LSB.
+ *
+ * Offset Length Usage
+ * ---
+ * 0x404 Validation word 0x31305341
+ * 0x441 Version (whatever, zero is fine)
+ * 0x451 Flags (unused, zero is fine)
+ * 0x462 Length (in units of u32, including the end checksum).
+ * 0x482 Zero
+ * 0x4A2 Checksum over the header. NB Not CRC32
+ *
+ * At the end of the code we have a 32-bit CRC checksum over whole binary
+ * excluding the CRC.
+ *
+ * Note that the CRC used here is **not** the
[U-Boot] [PATCH 11/35] arm: socfpga: sysmgr: Clean up system manager
Clean up the system manager register definition and add the missing
register definitions in place.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
arch/arm/cpu/armv7/socfpga/system_manager.c| 18 ++--
arch/arm/include/asm/arch-socfpga/system_manager.h | 102 +++--
2 files changed, 86 insertions(+), 34 deletions(-)
diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c
b/arch/arm/cpu/armv7/socfpga/system_manager.c
index d96521b..07c72e4 100644
--- a/arch/arm/cpu/armv7/socfpga/system_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/system_manager.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2013 Altera Corporation www.altera.com
+ * Copyright (C) 2013 Altera Corporation www.altera.com
*
* SPDX-License-Identifier:GPL-2.0+
*/
@@ -7,21 +7,23 @@
#include common.h
#include asm/io.h
#include asm/arch/system_manager.h
+#include asm/arch/fpga_manager.h
DECLARE_GLOBAL_DATA_PTR;
+static struct socfpga_system_manager *sysmgr_regs =
+ (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
/*
* Configure all the pin muxes
*/
void sysmgr_pinmux_init(void)
{
- unsigned long offset = CONFIG_SYSMGR_PINMUXGRP_OFFSET;
-
- const unsigned long *pval = sys_mgr_init_table;
- unsigned long i;
+ uint32_t regs = (uint32_t)sysmgr_regs-emacio[0];
+ int i;
- for (i = 0; i ARRAY_SIZE(sys_mgr_init_table);
- i++, offset += sizeof(unsigned long)) {
- writel(*pval++, (SOCFPGA_SYSMGR_ADDRESS + offset));
+ for (i = 0; i ARRAY_SIZE(sys_mgr_init_table); i++) {
+ writel(sys_mgr_init_table[i], regs);
+ regs += sizeof(regs);
}
}
diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h
b/arch/arm/include/asm/arch-socfpga/system_manager.h
index 838d210..90d2720 100644
--- a/arch/arm/include/asm/arch-socfpga/system_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/system_manager.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2013 Altera Corporation www.altera.com
+ * Copyright (C) 2013 Altera Corporation www.altera.com
*
* SPDX-License-Identifier:GPL-2.0+
*/
@@ -16,72 +16,122 @@ extern unsigned long
sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM];
#endif
-
-#define CONFIG_SYSMGR_PINMUXGRP_OFFSET (0x400)
-
-#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
- drvsel) 0) 0x7) | (((smplsel) 3) 0x38))
-
struct socfpga_system_manager {
- u32 siliconid1;
+ /* System Manager Module */
+ u32 siliconid1; /* 0x00 */
u32 siliconid2;
u32 _pad_0x8_0xf[2];
- u32 wddbg;
+ u32 wddbg; /* 0x10 */
u32 bootinfo;
u32 hpsinfo;
u32 parityinj;
- u32 fpgaintfgrp_gbl;
+ /* FPGA Interface Group */
+ u32 fpgaintfgrp_gbl;/* 0x20 */
u32 fpgaintfgrp_indiv;
u32 fpgaintfgrp_module;
u32 _pad_0x2c_0x2f;
- u32 scanmgrgrp_ctrl;
+ /* Scan Manager Group */
+ u32 scanmgrgrp_ctrl;/* 0x30 */
u32 _pad_0x34_0x3f[3];
- u32 frzctrl_vioctrl;
+ /* Freeze Control Group */
+ u32 frzctrl_vioctrl;/* 0x40 */
u32 _pad_0x44_0x4f[3];
- u32 frzctrl_hioctrl;
+ u32 frzctrl_hioctrl;/* 0x50 */
u32 frzctrl_src;
u32 frzctrl_hwctrl;
u32 _pad_0x5c_0x5f;
- u32 emacgrp_ctrl;
+ /* EMAC Group */
+ u32 emacgrp_ctrl; /* 0x60 */
u32 emacgrp_l3master;
u32 _pad_0x68_0x6f[2];
- u32 dmagrp_ctrl;
+ /* DMA Controller Group */
+ u32 dmagrp_ctrl;/* 0x70 */
u32 dmagrp_persecurity;
u32 _pad_0x78_0x7f[2];
- u32 iswgrp_handoff[8];
- u32 _pad_0xa0_0xbf[8];
- u32 romcodegrp_ctrl;
+ /* Preloader (initial software) Group */
+ u32 iswgrp_handoff[8]; /* 0x80 */
+ u32 _pad_0xa0_0xbf[8]; /* 0xa0 */
+ /* Boot ROM Code Register Group */
+ u32 romcodegrp_ctrl;/* 0xc0 */
u32 romcodegrp_cpu1startaddr;
u32 romcodegrp_initswstate;
u32 romcodegrp_initswlastld;
- u32 romcodegrp_bootromswstate;
+ u32 romcodegrp_bootromswstate; /* 0xd0 */
u32 __pad_0xd4_0xdf[3];
- u32 romcodegrp_warmramgrp_enable;
+ /* Warm Boot from On-Chip RAM Group */
+ u32 romcodegrp_warmramgrp_enable; /* 0xe0 */
u32 romcodegrp_warmramgrp_datastart;
u32 romcodegrp_warmramgrp_length;
u32
[U-Boot] [PATCH 22/35] arm: socfpga: misc: Align print_cpuinfo() output
From: Pavel Machek pa...@denx.de
Cosmetic change to the print_cpuinfo() function output. Align the
output with the rest of initial output produced by U-Boot.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
arch/arm/cpu/armv7/socfpga/misc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c
b/arch/arm/cpu/armv7/socfpga/misc.c
index 440d2a3..51be55c 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -80,7 +80,7 @@ int cpu_mmc_init(bd_t *bis)
*/
int print_cpuinfo(void)
{
- puts(CPU : Altera SOCFPGA Platform\n);
+ puts(CPU: Altera SoCFPGA Platform\n);
return 0;
}
#endif
--
2.1.0
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[U-Boot] [PATCH 27/35] arm: socfpga: sysmgr: Add FPGA bits into system manager
Add missing system manager bits from Altera U-Boot to make the code
comparable. These are the bits which depend on the FPGA manager.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
arch/arm/cpu/armv7/socfpga/system_manager.c | 39 +
1 file changed, 39 insertions(+)
diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c
b/arch/arm/cpu/armv7/socfpga/system_manager.c
index 07c72e4..11f7bad 100644
--- a/arch/arm/cpu/armv7/socfpga/system_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/system_manager.c
@@ -15,6 +15,43 @@ static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
/*
+ * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
+ * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
+ * CONFIG_SYSMGR_ISWGRP_HANDOFF.
+ */
+static void populate_sysmgr_fpgaintf_module(void)
+{
+ uint32_t handoff_val = 0;
+
+ /* ISWGRP_HANDOFF_FPGAINTF */
+ writel(0, sysmgr_regs-iswgrp_handoff[2]);
+
+ /* Enable the signal for those HPS peripherals that use FPGA. */
+ if (readl(sysmgr_regs-nandusefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ handoff_val |= SYSMGR_FPGAINTF_NAND;
+ if (readl(sysmgr_regs-rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ handoff_val |= SYSMGR_FPGAINTF_EMAC1;
+ if (readl(sysmgr_regs-sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ handoff_val |= SYSMGR_FPGAINTF_SDMMC;
+ if (readl(sysmgr_regs-rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ handoff_val |= SYSMGR_FPGAINTF_EMAC0;
+ if (readl(sysmgr_regs-spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ handoff_val |= SYSMGR_FPGAINTF_SPIM0;
+ if (readl(sysmgr_regs-spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ handoff_val |= SYSMGR_FPGAINTF_SPIM1;
+
+ /* populate (not writing) the value for SYSMGR.FPGAINTF.MODULE
+ based on pinmux setting */
+ setbits_le32(sysmgr_regs-iswgrp_handoff[2], handoff_val);
+
+ handoff_val = readl(sysmgr_regs-iswgrp_handoff[2]);
+ if (fpgamgr_test_fpga_ready()) {
+ /* Enable the required signals only */
+ writel(handoff_val, sysmgr_regs-fpgaintfgrp_module);
+ }
+}
+
+/*
* Configure all the pin muxes
*/
void sysmgr_pinmux_init(void)
@@ -26,4 +63,6 @@ void sysmgr_pinmux_init(void)
writel(sys_mgr_init_table[i], regs);
regs += sizeof(regs);
}
+
+ populate_sysmgr_fpgaintf_module();
}
--
2.1.0
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[U-Boot] [PATCH 17/35] arm: socfpga: mmc: Pick the clock from clock manager
From: Pavel Machek pa...@denx.de
Make the SoCFPGA MMC stub pick clock via the clock manager
frequency accessors instead of hard-coding the frequency.
Also fix calloc() misuse.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
drivers/mmc/socfpga_dw_mmc.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 1f96382..eb69aed 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -7,6 +7,7 @@
#include common.h
#include malloc.h
#include dwmmc.h
+#include errno.h
#include asm/arch/dwmmc.h
#include asm/arch/clock_manager.h
#include asm/arch/system_manager.h
@@ -44,12 +45,18 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
int socfpga_dwmmc_init(u32 regbase, int bus_width, int index)
{
struct dwmci_host *host;
+ unsigned long clk = cm_get_mmc_controller_clk_hz();
+
+ if (clk == 0) {
+ printf(%s: MMC clock is zero!, __func__);
+ return -EINVAL;
+ }
/* calloc for zero init */
- host = calloc(sizeof(struct dwmci_host), 1);
+ host = calloc(1, sizeof(struct dwmci_host));
if (!host) {
- printf(dwmci_host calloc fail!\n);
- return -1;
+ printf(%s: calloc() failed!\n, __func__);
+ return -ENOMEM;
}
host-name = SOCFPGA DWMMC;
@@ -58,7 +65,7 @@ int socfpga_dwmmc_init(u32 regbase, int bus_width, int index)
host-clksel = socfpga_dwmci_clksel;
host-dev_index = index;
/* fixed clock divide by 4 which due to the SDMMC wrapper */
- host-bus_hz = CONFIG_SOCFPGA_DWMMC_BUS_HZ;
+ host-bus_hz = clk;
host-fifoth_val = MSIZE(0x2) |
RX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2 - 1) |
TX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2);
--
2.1.0
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[U-Boot] [PATCH 26/35] arm: socfpga: reset: Add function to reset FPGA bridges
Add function to enable and disable FPGA bridges. This code is used
by the FPGA manager to disable the bridges before programming the
FPGA and will later be also used by the initialization code for the
chip to put the chip into well defined state during startup.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
arch/arm/cpu/armv7/socfpga/reset_manager.c| 38 +++
arch/arm/include/asm/arch-socfpga/reset_manager.h | 2 ++
2 files changed, 40 insertions(+)
diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c
b/arch/arm/cpu/armv7/socfpga/reset_manager.c
index 77579b7..85579c0 100644
--- a/arch/arm/cpu/armv7/socfpga/reset_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c
@@ -8,6 +8,7 @@
#include common.h
#include asm/io.h
#include asm/arch/reset_manager.h
+#include asm/arch/fpga_manager.h
DECLARE_GLOBAL_DATA_PTR;
@@ -53,6 +54,43 @@ void reset_deassert_peripherals_handoff(void)
writel(0, reset_manager_base-per_mod_reset);
}
+#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
+void socfpga_bridges_reset(int enable)
+{
+ /* For SoCFPGA-VT, this is NOP. */
+}
+#else
+
+#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
+#define L3REGS_REMAP_HPS2FPGA_MASK 0x08
+#define L3REGS_REMAP_OCRAM_MASK0x01
+
+void socfpga_bridges_reset(int enable)
+{
+ const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
+ L3REGS_REMAP_HPS2FPGA_MASK |
+ L3REGS_REMAP_OCRAM_MASK;
+
+ if (enable) {
+ /* brdmodrst */
+ writel(0x, reset_manager_base-brg_mod_reset);
+ } else {
+ /* Check signal from FPGA. */
+ if (fpgamgr_poll_fpga_ready()) {
+ /* FPGA not ready. Wait for watchdog timeout. */
+ printf(%s: fpga not ready, hanging.\n, __func__);
+ hang();
+ }
+
+ /* brdmodrst */
+ writel(0, reset_manager_base-brg_mod_reset);
+
+ /* Remap the bridges into memory map */
+ writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
+ }
+}
+#endif
+
/* Change the reset state for EMAC 0 and EMAC 1 */
void socfpga_emac_reset(int enable)
{
diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h
b/arch/arm/include/asm/arch-socfpga/reset_manager.h
index 9d22576..4cbce96 100644
--- a/arch/arm/include/asm/arch-socfpga/reset_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h
@@ -10,6 +10,8 @@
void reset_cpu(ulong addr);
void reset_deassert_peripherals_handoff(void);
+void socfpga_bridges_reset(int enable);
+
void socfpga_emac_reset(int enable);
void watchdog_disable(void);
--
2.1.0
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[U-Boot] [PATCH 25/35] arm: socfpga: fpga: Add SoCFPGA FPGA programming interface
From: Pavel Machek pa...@denx.de
Add code necessary to program the FPGA part of SoCFPGA from U-Boot
with an RBF blob. This patch also integrates the code into the
FPGA driver framework in U-Boot so it can be used via the 'fpga'
command.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
arch/arm/cpu/armv7/socfpga/Makefile | 3 +-
arch/arm/cpu/armv7/socfpga/fpga_manager.c| 354 +++
arch/arm/cpu/armv7/socfpga/misc.c| 37 +++
arch/arm/include/asm/arch-socfpga/fpga_manager.h | 77 +
drivers/fpga/altera.c| 21 ++
include/altera.h | 1 +
6 files changed, 492 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/socfpga/fpga_manager.c
create mode 100644 arch/arm/include/asm/arch-socfpga/fpga_manager.h
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index eb33f2c..8b6e108 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -8,5 +8,6 @@
#
obj-y := lowlevel_init.o
-obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o
+obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
+ fpga_manager.o
obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
diff --git a/arch/arm/cpu/armv7/socfpga/fpga_manager.c
b/arch/arm/cpu/armv7/socfpga/fpga_manager.c
new file mode 100644
index 000..38d48f8
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/fpga_manager.c
@@ -0,0 +1,354 @@
+/*
+ * Copyright (C) 2012 Altera Corporation www.altera.com
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier:BSD-3-Clause
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/errno.h
+#include asm/arch/fpga_manager.h
+#include asm/arch/reset_manager.h
+#include asm/arch/system_manager.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Timeout count */
+#define FPGA_TIMEOUT_CNT 0x100
+
+static struct socfpga_fpga_manager *fpgamgr_regs =
+ (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+static struct socfpga_system_manager *sysmgr_regs =
+ (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/* Check whether FPGA Init_Done signal is high */
+static int is_fpgamgr_initdone_high(void)
+{
+ unsigned long val;
+ val = readl(fpgamgr_regs-gpio_ext_porta);
+ return val FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK;
+}
+
+/* Get the FPGA mode */
+static int fpgamgr_get_mode(void)
+{
+ unsigned long val;
+ val = readl(fpgamgr_regs-stat);
+ return val FPGAMGRREGS_STAT_MODE_MASK;
+}
+
+/* Check whether FPGA is ready to be accessed */
+int fpgamgr_test_fpga_ready(void)
+{
+ /* Check for init done signal */
+ if (!is_fpgamgr_initdone_high())
+ return 0;
+
+ /* Check again to avoid false glitches */
+ if (!is_fpgamgr_initdone_high())
+ return 0;
+
+ if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE)
+ return 0;
+
+ return 1;
+}
+
+/* Poll until FPGA is ready to be accessed or timeout occurred */
+int fpgamgr_poll_fpga_ready(void)
+{
+ unsigned long i;
+
+ /* If FPGA is blank, wait till WD invoke warm reset */
+ for (i = 0; i FPGA_TIMEOUT_CNT; i++) {
+ /* check for init done signal */
+ if (!is_fpgamgr_initdone_high())
+ continue;
+ /* check again to avoid false glitches */
+ if (!is_fpgamgr_initdone_high())
+ continue;
+ return 1;
+ }
+
+ return 0;
+}
+
+/* Set CD ratio */
+static void fpgamgr_set_cd_ratio(unsigned long ratio)
+{
+ clrsetbits_le32(fpgamgr_regs-ctrl,
+ 0x3 FPGAMGRREGS_CTRL_CDRATIO_LSB,
+ (ratio 0x3) FPGAMGRREGS_CTRL_CDRATIO_LSB);
+}
+
+static int fpgamgr_dclkcnt_set(unsigned long cnt)
+{
+ unsigned long i;
+
+ /* Clear any existing done status */
+ if (readl(fpgamgr_regs-dclkstat))
+ writel(0x1, fpgamgr_regs-dclkstat);
+
+ /* Write the dclkcnt */
+ writel(cnt, fpgamgr_regs-dclkcnt);
+
+ /* Wait till the dclkcnt done */
+ for (i = 0; i FPGA_TIMEOUT_CNT; i++) {
+ if (!readl(fpgamgr_regs-dclkstat))
+ continue;
+
+ writel(0x1, fpgamgr_regs-dclkstat);
+ return 0;
+ }
+
+ return -ETIMEDOUT;
+}
+
+/* Start the FPGA programming by initialize the FPGA Manager */
+static int fpgamgr_program_init(void)
+{
+ unsigned long msel, i;
+
+ /* Get the MSEL value */
+ msel = readl(fpgamgr_regs-stat);
+ msel = FPGAMGRREGS_STAT_MSEL_MASK;
[U-Boot] [PATCH 29/35] arm: socfpga: cache: Define cacheline size
The Cortex-A9 has 32-byte long L1 cachelines. Define this value. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@altera.com Cc: Dinh Nguyen dingu...@altera.com Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Rini tr...@ti.com Cc: Wolfgang Denk w...@denx.de Cc: Pavel Machek pa...@denx.de --- include/configs/socfpga_cyclone5.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index f50081b..f0eac4d 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -26,6 +26,8 @@ #define CONFIG_SOCFPGA #define CONFIG_CLOCKS +#define CONFIG_SYS_CACHELINE_SIZE 32 + /* base address for .text section */ #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_SYS_TEXT_BASE 0x0840 -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 21/35] arm: socfpga: misc: Add SD controller init
From: Pavel Machek pa...@denx.de
Add CPU function to register and initialize the dw_mmc SD controller.
This allows us to use the HPS SDMMC block.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
arch/arm/cpu/armv7/socfpga/misc.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c
b/arch/arm/cpu/armv7/socfpga/misc.c
index ee7283b..440d2a3 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -10,6 +10,7 @@
#include netdev.h
#include asm/arch/reset_manager.h
#include asm/arch/system_manager.h
+#include asm/arch/dwmmc.h
DECLARE_GLOBAL_DATA_PTR;
@@ -61,6 +62,18 @@ int cpu_eth_init(bd_t *bis)
}
#endif
+#ifdef CONFIG_DWMMC
+/*
+ * Initializes MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+ return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS,
+ CONFIG_HPS_SDMMC_BUSWIDTH, 0);
+}
+#endif
+
#if defined(CONFIG_DISPLAY_CPUINFO)
/*
* Print CPU information
--
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[U-Boot] [PATCH 28/35] arm: cache: Add support for write-allocate D-Cache
Add configuration for the write-allocate mode of L1 D-Cache on ARM.
This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA .
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
arch/arm/include/asm/system.h | 1 +
arch/arm/lib/cache-cp15.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index d51ba66..ca2d44f 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -185,6 +185,7 @@ enum dcache_option {
DCACHE_OFF = 0x12,
DCACHE_WRITETHROUGH = 0x1a,
DCACHE_WRITEBACK = 0x1e,
+ DCACHE_WRITEALLOC = 0x16,
};
/* Size of an MMU section */
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 3e62d58..2155fe8 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -73,6 +73,8 @@ __weak void dram_bank_mmu_setup(int bank)
i++) {
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
set_section_dcache(i, DCACHE_WRITETHROUGH);
+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
+ set_section_dcache(i, DCACHE_WRITEALLOC);
#else
set_section_dcache(i, DCACHE_WRITEBACK);
#endif
--
2.1.0
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[U-Boot] [PATCH 13/35] arm: socfpga: clock: Drop nonsense inlining from clock manager code
The inlining is done by GCC whe needed, there is no need to do it
explicitly. Furthermore, the inline keyword does not force-inline
the code, but is only a hint for the compiler. Scrub this hint.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
arch/arm/cpu/armv7/socfpga/clock_manager.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c
b/arch/arm/cpu/armv7/socfpga/clock_manager.c
index 158501a..d032bbd 100644
--- a/arch/arm/cpu/armv7/socfpga/clock_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c
@@ -30,7 +30,7 @@ static const struct socfpga_clock_manager *clock_manager_base
=
CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
-static inline void cm_wait_for_lock(uint32_t mask)
+static void cm_wait_for_lock(uint32_t mask)
{
register uint32_t inter_val;
do {
@@ -39,7 +39,7 @@ static inline void cm_wait_for_lock(uint32_t mask)
}
/* function to poll in the fsm busy bit */
-static inline void cm_wait_for_fsm(void)
+static void cm_wait_for_fsm(void)
{
while (readl(clock_manager_base-stat) CLKMGR_STAT_BUSY)
;
@@ -49,22 +49,22 @@ static inline void cm_wait_for_fsm(void)
* function to write the bypass register which requires a poll of the
* busy bit
*/
-static inline void cm_write_bypass(uint32_t val)
+static void cm_write_bypass(uint32_t val)
{
writel(val, clock_manager_base-bypass);
cm_wait_for_fsm();
}
/* function to write the ctrl register which requires a poll of the busy bit */
-static inline void cm_write_ctrl(uint32_t val)
+static void cm_write_ctrl(uint32_t val)
{
writel(val, clock_manager_base-ctrl);
cm_wait_for_fsm();
}
/* function to write a clock register that has phase information */
-static inline void cm_write_with_phase(uint32_t value,
- uint32_t reg_address, uint32_t mask)
+static void cm_write_with_phase(uint32_t value,
+ uint32_t reg_address, uint32_t mask)
{
/* poll until phase is zero */
while (readl(reg_address) mask)
--
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[U-Boot] [PATCH 24/35] arm: socfpga: board: Align checkboard() output
Cosmetic change to the checkboard() function output. Align the
output with the rest of initial output produced by U-Boot.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
board/altera/socfpga/socfpga_cyclone5.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/altera/socfpga/socfpga_cyclone5.c
b/board/altera/socfpga/socfpga_cyclone5.c
index bc8a87c..4149842 100644
--- a/board/altera/socfpga/socfpga_cyclone5.c
+++ b/board/altera/socfpga/socfpga_cyclone5.c
@@ -17,7 +17,7 @@ DECLARE_GLOBAL_DATA_PTR;
*/
int checkboard(void)
{
- puts(BOARD : Altera SOCFPGA Cyclone5 Board\n);
+ puts(BOARD: Altera SoCFPGA Cyclone5 Board\n);
return 0;
}
--
2.1.0
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[U-Boot] [PATCH 23/35] arm: socfpga: board: Correctly set ATAG position
From: Pavel Machek pa...@denx.de
The bi_boot_params must point to offset 0x100 in DRAM. Make it so.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
board/altera/socfpga/socfpga_cyclone5.c | 4
1 file changed, 4 insertions(+)
diff --git a/board/altera/socfpga/socfpga_cyclone5.c
b/board/altera/socfpga/socfpga_cyclone5.c
index fb92852..bc8a87c 100644
--- a/board/altera/socfpga/socfpga_cyclone5.c
+++ b/board/altera/socfpga/socfpga_cyclone5.c
@@ -35,5 +35,9 @@ int board_early_init_f(void)
int board_init(void)
{
icache_enable();
+
+ /* Address of boot parameters for ATAG (if ATAG is used) */
+ gd-bd-bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
return 0;
}
--
2.1.0
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Re: [U-Boot] [PATCH] test: dfu: script: wrong md5sum on nand partitions
Hi Heiko, Hello Lukasz, Am 15.09.2014 11:45, schrieb Lukasz Majewski: Hi Heiko, Hello Stephen, add Lukasz to Cc ... Am 12.09.2014 16:53, schrieb Stephen Warren: On 09/12/2014 12:27 AM, Heiko Schocher wrote: when uplaoding a file, at least from a nand partition, the complete mtd nand partition size is transferred. This leads in a wrong md5sum as the filesize is different between the downloaded file and the uploaded file. Limit the uploaded filesize to the downloaded fixes this. I was going to say that it'd be better to fix U-Boot's NAND code to transfer the correct amount of data. However, I suppose the correct amount *is* the whole partition for anything other than a filesystem file. As such, I'd suggest replacing nand in the patch description with something else, since presumably the exact same issue applies to partitions on eMMC. The issue applies to any partition. Yes, you are right. It is the case with testing raw/partition write. With NAND the procedure is as follows: 1. Erase NAND (0xFF on the whole partition) 2. Store the new partition (very rarely the partition.img == NAND partition size). Very often partition.img NAND partition. 3. The NAND code reads the whole partition (including the 0xFF padding). This padding causes md5sum to be wrong. Yes. I wonder if there's a way to distinguish between file tests and partition tests in dfu_gadget_test.sh, so that the $N_FILE_FULL - $N_FILE conversion can be applied only for partitions. Otherwise, a file upload/download test could end up changing (increasing) the file length and this bug wouldn't be detected. Lukasz could better comment on this ... currently filesize is changed on a raw partition, as the test download for example 960 bytes, and reads back the hole partition size ... which leads in a wrong md5sum. It would be good to have in the DFU protcol a length parameter ... so a device could at transfer start decide, if the filesize fits into the partition, if not, no need to tranfser the hole file, and detect this error at the end (with a broken partition now) ... Yes, the lack of size parameter is very inconvenient (for example we must then allocate bigger buffers than needed). However, for testing purposes we can introduce new test file name part_file_size.img - e.g. part_32M.img. Then this would indicate the test for the whole partition. Hmm... yes, but I fear, that every board has different partition size, so we need a lot of files ... The legacy dat_file_size.img (e.g. dat_960.img) would be truncated if needed in the script. This is a quick solution. Yes ... I do not prefer this solution. Why not cutting the readden file to the length we transferred? I think that the truncation of the received file is acceptable. If we were about to test partition write, then we could prepare images with the size equal to the partition size. Or fill the original file with 0xff until we reached the filesize we read from the device? Other thoughts: 1. In the dfu-util repo there is the dfu-prefix tool. It allows generating some special prefix for LPC and TI Stellaris SoCs. Maybe we could think about u-boot prefix and put there for example binary size and signature data. Hmm.. I do not like such special headers ... but this is just a personal opinion ... 2. The dfu-util 0.7 on the HOST when -l is typed shows the name= and serial=. If it was possible to add serial, then we could extend dfu-util to show size of the alt setting. [root@ts8 ~]# dfu-util -l dfu-util 0.7 Copyright 2005-2008 Weston Schmidt, Harald Welte and OpenMoko Inc. Copyright 2010-2012 Tormod Volden and Stefan Schmidt This program is Free Software and has ABSOLUTELY NO WARRANTY Please report bugs to dfu-u...@lists.gnumonks.org Found DFU: [0908:02c5] devnum=0, cfg=1, intf=0, alt=0, name=spl Found DFU: [0908:02c5] devnum=0, cfg=1, intf=0, alt=1, name=spl.backup1 Found DFU: [0908:02c5] devnum=0, cfg=1, intf=0, alt=2, name=spl.backup2 Found DFU: [0908:02c5] devnum=0, cfg=1, intf=0, alt=3, name=spl.backup3 Found DFU: [0908:02c5] devnum=0, cfg=1, intf=0, alt=4, name=u-boot Found DFU: [0908:02c5] devnum=0, cfg=1, intf=0, alt=5, name=kernel_a Found DFU: [0908:02c5] devnum=0, cfg=1, intf=0, alt=6, name=kernel_b Found DFU: [0908:02c5] devnum=0, cfg=1, intf=0, alt=7, name=rootfs [root@ts8 ~]# I do not see serial= for the siemens boards ... This is strange. Could you checkout and build following dfu-util version: Repository: dfu-util-repo git://gitorious.org/dfu-util/dfu-util.git SHA1: dc15eefbb8f928aed932fa1e8daa341e34d0b096 With exynos I see the serial= output. But if we could add here a size, that would be a good thing to have, so we coud at least read the size, and if our image fits not in it, break the transfer, before starting it ... and for the test script, we could read the size, and create a file,
[U-Boot] [PATCH 30/35] arm: socfpga: cache: Enable D-Cache
The code is now fixed to the point where we can safely enable
the L1 data cache. Enable the D-Cache and set it as write-alloc.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
board/altera/socfpga/socfpga_cyclone5.c | 1 +
include/configs/socfpga_cyclone5.h | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/board/altera/socfpga/socfpga_cyclone5.c
b/board/altera/socfpga/socfpga_cyclone5.c
index 4149842..6b98277 100644
--- a/board/altera/socfpga/socfpga_cyclone5.c
+++ b/board/altera/socfpga/socfpga_cyclone5.c
@@ -35,6 +35,7 @@ int board_early_init_f(void)
int board_init(void)
{
icache_enable();
+ dcache_enable();
/* Address of boot parameters for ATAG (if ATAG is used) */
gd-bd-bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
diff --git a/include/configs/socfpga_cyclone5.h
b/include/configs/socfpga_cyclone5.h
index f0eac4d..20da1ac 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -18,7 +18,6 @@
#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_ARMV7
-#define CONFIG_SYS_DCACHE_OFF
#undef CONFIG_USE_IRQ
#define CONFIG_MISC_INIT_R
@@ -26,6 +25,7 @@
#define CONFIG_SOCFPGA
#define CONFIG_CLOCKS
+#define CONFIG_SYS_ARM_CACHE_WRITEALLOC
#define CONFIG_SYS_CACHELINE_SIZE 32
/* base address for .text section */
--
2.1.0
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Re: [U-Boot] [PATCH 3/5] fdt: add fdt_add_display_timings(..)
2014-01-16 12:44 GMT+01:00 Christian Gmeiner christian.gmei...@gmail.com:
Hi all
2014/1/14 Christian Gmeiner christian.gmei...@gmail.com:
2014/1/12 Anatolij Gustschin ag...@denx.de:
Hi Stefano,
On Wed, 08 Jan 2014 11:53:39 +0100
Stefano Babic sba...@denx.de wrote:
...
Agree that we have to sync u-boot and kernel, and this can be a way in
the short term.
I am asking if this is in the long term the best way to do it. You are
converting EDID values to fb_videomode *mode, and then again to the
device node as required by DT.
We have already had some talks about moving U-Boot configuration to DT,
that is U-Boot can be also configured by a DT file (see for example
support for Nvidia processors, they already support DT in U-Boot).
Anatolji, what do you think as best solution we have to follow for
display setting ?
many drivers use struct fb_videomode internally and this display-timings
binding already exists in linux, so I think a function for converting
from fb_videomode to DT is useful. However we should probably extend
this current implementation of the function, e.g. rename it to
fdt_update_display_timings() and pass more arguments: node compatible
and the name of the parent node containing the display-timings node.
The code for searching the display-timings node is also needed for
other boards, so if it is in the function itself, it will simplify
the usage.
This function could look for display-timings node and create it if
it doesn't exist. Or update the existing node with new info.
Thanks for your comments... will come up with something in the next version
of the patch series.
I have some time to work on this patch.
Anatolij are you happy witht the following functions?
int fdt_find_display_timings(void *fdt, const char *compat, const char
*parent)
{
int coff = fdt_node_offset_by_compatible(fdt, -1, compat);
int poff = fdt_subnode_offset(fdt, coff, parent);
int timings = fdt_subnode_offset(fdt, poff, display-timings);
return timings;
}
int fdt_update_display_timings(void *fdt, const char *compat, const
char *parent, struct fb_videomode *mode)
{
int timings = fdt_find_display_timings(fdt, compat, parent);
/* check if display-timings subnode does exist */
if (timings == -FDT_ERR_NOTFOUND) {
return timings;
}
/* set all needed properties */
if (timings != -FDT_ERR_NOTFOUND) {
fdt_setprop_u32(fdt, noff, clock-frequency, mode-pixclock);
fdt_setprop_u32(fdt, noff, hactive, mode-xres);
fdt_setprop_u32(fdt, noff, vactive, mode-yres);
fdt_setprop_u32(fdt, noff, hback-porch, mode-left_margin);
fdt_setprop_u32(fdt, noff, hfront-porch, mode-right_margin);
fdt_setprop_u32(fdt, noff, vback-porch, mode-upper_margin);
fdt_setprop_u32(fdt, noff, vfront-porch, mode-lower_margin);
fdt_setprop_u32(fdt, noff, hsync-len, mode-hsync_len);
fdt_setprop_u32(fdt, noff, vsync-len, mode-vsync_len);
}
return 0;
}
This would allow us to update an existing display-timings node via
fdt_update_display_timings(blob, fsl,imx6q-ldb, lvds-channel, mode);
Note: not even compile tested :)
I got no feedback over some months - bad. But okay I really want to get all
the bits of our imx6 based board upstream as soon as possible. So has something
changed in that area?
In the end I want to read EDID stored in an eeprom and put it into the
device tree (patching or creating new node).
greets
--
Christian Gmeiner, MSc
https://soundcloud.com/christian-gmeiner
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[U-Boot] [PATCH v2 0/30] Introduce driver model support for SPI, SPI flash, cros_ec
Up until now driver model has not been used for any type of bus. Buses have some unique properties and needs, so we cannot claim that driver model can cover all the common cases unless we have converted a bus over to driver model. SPI is a reasonable choice for this next step. It has a fairly simple API and not too many dependencies. The main one is SPI flash so we may as well convert that also. Since the boards I test with have cros_ec I have also included that, for SPI only. The technique used is make use of driver model's supported data structures to hold information currently kept by each subsystem in a private data structure. Since 'struct spi_slave' relates to the slave device on the bus it is stored in the 'parent' data with each child device of the bus. Since 'struct spi_flash' is a standard interface used for each SPI flash driver, it is stored in the SPI FLash uclass's private data for each device. New defines are created to enable driver model for each subsystem. These are: CONFIG_DM_SPI CONFIG_DM_SPI_FLASH CONFIG_DM_CROS_EC This allows us to move some boards and drivers to driver model, while leaving others behind. A 'big bang' conversion of everything to driver model, event at a subsystem level, is never going to work. There is some cost in changing the uclass interface after it is created, so if you have limited time, please spend it reviewing the uclass interfaces in spi.h and spi_flash.h. These need to be supported by each driver, so changing them later may involve changing multiple drivers. To assist with the conversion of other SPI drivers, a README file is added to walk through the process. As always, driver model patches are available at u-boot-dm.git branch 'working'. Changes in v2: - Add new patch to fix README merge error - Adjust binding to avoid Linux-specific mentions - Use 'bus' instead of 'dev' to make the API clearer - Fix code nits from Daniel Schwierzeck - Add missing comments for struct spi_slave - Fix comment on 'slave' parameter to match the parameter name - Fix a typo in the commit message - Add spi.h header to dfu_sf.c and some renesas boards - Correct sandbox's xfer() method signature - Use 'bus' instead of 'dev' to make the API clearer - Update for changes to exynos driver - Fix typos reported by Jagannadha Sutradharudu Teki - Add additional debug() statements - Use 'bus' instead of 'dev' to distinguish bus from slave - Adjust xfer() method for new API - Create a 'spi.bin' file for the SPI tests Simon Glass (30): dm: Fix repeated comment in README sandbox: Convert SPI flash emulation to use sf_params sandbox: config: Enable all SPI flash chips sandbox: dts: Add a SPI device and cros_ec device dm: spi: Move cmd device code into its own function spi: Add brackets and tidy defines in spi.h dm: spi: Add a uclass for SPI dm: sandbox: Add a SPI emulation uclass dm: Remove spi_init() from board_r.c when using driver model dm: Add spi.h header to a few files dm: spi: Adjust cmd_spi to work with driver model dm: sandbox: spi: Move to driver model dm: spi: Add documentation on how to convert over SPI drivers dm: spi: Rename soft_spi.c to soft_spi_legacy.c dm: spi: Remove SPI_INIT feature dm: spi: Add soft_spi implementation dm: exynos: Convert SPI to driver model exynos: universal_c210: Move to driver model soft_spi sf: Add an empty entry to the parameter list sf: Tidy up public and private header files spi: Use error return value in sf_ops dm: sf: Add a uclass for SPI flash dm: Convert spi_flash_probe() and 'sf probe' to use driver model dm: sf: sandbox: Convert SPI flash driver to driver model dm: exynos: config: Use driver model for SPI flash dm: spi: Add tests dm: sf: Add tests for SPI flash dm: cros_ec: Add support for driver model dm: sandbox: cros_ec: Move sandbox cros_ec to driver module dm: exynos: cros_ec: Move cros_ec_spi to driver model README | 5 +- arch/arm/dts/exynos4210-universal_c210.dts | 13 + arch/arm/dts/exynos5250-snow.dts | 8 + arch/arm/dts/exynos5420-peach-pit.dts | 1 + arch/sandbox/dts/sandbox.dts | 26 ++ arch/sandbox/include/asm/spi.h | 13 - arch/sandbox/include/asm/state.h | 2 +- board/buffalo/lsxl/lsxl.c | 3 +- board/renesas/sh7752evb/sh7752evb.c| 1 + board/renesas/sh7753evb/sh7753evb.c| 1 + board/renesas/sh7757lcr/sh7757lcr.c| 1 + board/samsung/common/board.c | 3 - board/samsung/universal_c210/universal.c | 52 --- common/board_r.c | 2 +- common/cmd_sf.c| 24 + common/cmd_spi.c | 73 +++- common/cros_ec.c | 30 ++ common/env_sf.c| 1 + common/exports.c |
[U-Boot] [PATCH v2 05/30] dm: spi: Move cmd device code into its own function
In preparation for changing the error handling in this code for driver
model, move it into its own function.
Reviewed-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
common/cmd_spi.c | 53 -
1 file changed, 32 insertions(+), 21 deletions(-)
diff --git a/common/cmd_spi.c b/common/cmd_spi.c
index 3c8e913..be5709c 100644
--- a/common/cmd_spi.c
+++ b/common/cmd_spi.c
@@ -11,6 +11,7 @@
#include common.h
#include command.h
+#include errno.h
#include spi.h
/*---
@@ -38,6 +39,35 @@ static int bitlen;
static uchar dout[MAX_SPI_BYTES];
static uchar din[MAX_SPI_BYTES];
+static int do_spi_xfer(int bus, int cs)
+{
+ struct spi_slave *slave;
+ int rcode = 0;
+
+ slave = spi_setup_slave(bus, cs, 100, mode);
+ if (!slave) {
+ printf(Invalid device %d:%d\n, bus, cs);
+ return -EINVAL;
+ }
+
+ spi_claim_bus(slave);
+ if (spi_xfer(slave, bitlen, dout, din,
+SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
+ printf(Error during SPI transaction\n);
+ rcode = -EIO;
+ } else {
+ int j;
+
+ for (j = 0; j ((bitlen + 7) / 8); j++)
+ printf(%02X, din[j]);
+ printf(\n);
+ }
+ spi_release_bus(slave);
+ spi_free_slave(slave);
+
+ return rcode;
+}
+
/*
* SPI read/write
*
@@ -51,11 +81,9 @@ static uchar din[MAX_SPI_BYTES];
int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- struct spi_slave *slave;
char *cp = 0;
uchar tmp;
int j;
- int rcode = 0;
/*
* We use the last specified parameters, unless new ones are
@@ -103,27 +131,10 @@ int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
return 1;
}
- slave = spi_setup_slave(bus, cs, 100, mode);
- if (!slave) {
- printf(Invalid device %d:%d\n, bus, cs);
+ if (do_spi_xfer(bus, cs))
return 1;
- }
-
- spi_claim_bus(slave);
- if(spi_xfer(slave, bitlen, dout, din,
- SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
- printf(Error during SPI transaction\n);
- rcode = 1;
- } else {
- for(j = 0; j ((bitlen + 7) / 8); j++) {
- printf(%02X, din[j]);
- }
- printf(\n);
- }
- spi_release_bus(slave);
- spi_free_slave(slave);
- return rcode;
+ return 0;
}
/***/
--
2.1.0.rc2.206.gedb03e5
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[U-Boot] [PATCH v2 10/30] dm: Add spi.h header to a few files
Some files are using SPI functions but not explitly including the SPI header file. Fix this, since driver model needs it. Signed-off-by: Simon Glass s...@chromium.org --- Changes in v2: - Add spi.h header to dfu_sf.c and some renesas boards board/renesas/sh7752evb/sh7752evb.c | 1 + board/renesas/sh7753evb/sh7753evb.c | 1 + board/renesas/sh7757lcr/sh7757lcr.c | 1 + common/env_sf.c | 1 + drivers/dfu/dfu_sf.c| 1 + drivers/mtd/spi/sf_params.c | 1 + 6 files changed, 6 insertions(+) diff --git a/board/renesas/sh7752evb/sh7752evb.c b/board/renesas/sh7752evb/sh7752evb.c index 5eedbf8..3aad532 100644 --- a/board/renesas/sh7752evb/sh7752evb.c +++ b/board/renesas/sh7752evb/sh7752evb.c @@ -9,6 +9,7 @@ #include asm/processor.h #include asm/io.h #include asm/mmc.h +#include spi.h #include spi_flash.h int checkboard(void) diff --git a/board/renesas/sh7753evb/sh7753evb.c b/board/renesas/sh7753evb/sh7753evb.c index 42b920f..9f64945 100644 --- a/board/renesas/sh7753evb/sh7753evb.c +++ b/board/renesas/sh7753evb/sh7753evb.c @@ -9,6 +9,7 @@ #include asm/processor.h #include asm/io.h #include asm/mmc.h +#include spi.h #include spi_flash.h int checkboard(void) diff --git a/board/renesas/sh7757lcr/sh7757lcr.c b/board/renesas/sh7757lcr/sh7757lcr.c index 1464f48..ddcf275 100644 --- a/board/renesas/sh7757lcr/sh7757lcr.c +++ b/board/renesas/sh7757lcr/sh7757lcr.c @@ -9,6 +9,7 @@ #include asm/processor.h #include asm/io.h #include asm/mmc.h +#include spi.h #include spi_flash.h int checkboard(void) diff --git a/common/env_sf.c b/common/env_sf.c index 37ab13a..5e3729c 100644 --- a/common/env_sf.c +++ b/common/env_sf.c @@ -12,6 +12,7 @@ #include common.h #include environment.h #include malloc.h +#include spi.h #include spi_flash.h #include search.h #include errno.h diff --git a/drivers/dfu/dfu_sf.c b/drivers/dfu/dfu_sf.c index 91f6df2..c3d3c3b 100644 --- a/drivers/dfu/dfu_sf.c +++ b/drivers/dfu/dfu_sf.c @@ -9,6 +9,7 @@ #include errno.h #include div64.h #include dfu.h +#include spi.h #include spi_flash.h static long dfu_get_medium_size_sf(struct dfu_entity *dfu) diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index ac886fd..53efdc8 100644 --- a/drivers/mtd/spi/sf_params.c +++ b/drivers/mtd/spi/sf_params.c @@ -7,6 +7,7 @@ */ #include common.h +#include spi.h #include spi_flash.h #include sf_internal.h -- 2.1.0.rc2.206.gedb03e5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 09/30] dm: Remove spi_init() from board_r.c when using driver model
Driver model does its own init, so we don't need this.
There is still a call in board_f.c but it is only enabled by CONFIG_HARD_SPI.
It is easy enough to disable that option when converting boards which use
it to driver model.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Fix a typo in the commit message
common/board_r.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/board_r.c b/common/board_r.c
index 231c6d6..cd92288 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -354,7 +354,7 @@ static int initr_flash(void)
}
#endif
-#ifdef CONFIG_PPC
+#if defined(CONFIG_PPC) !defined(CONFIG_DM_SPI)
static int initr_spi(void)
{
/* PPC does this here */
--
2.1.0.rc2.206.gedb03e5
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[U-Boot] [PATCH v2 03/30] sandbox: config: Enable all SPI flash chips
Sandbox may as well support everything. This increases the amount of code that is built/tested by sandbox, and also provides access to all the supported SPI flash devices. Signed-off-by: Simon Glass s...@chromium.org Reviewed-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com --- Changes in v2: None include/configs/sandbox.h | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index f5fa4b3..5e4e5fc 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -94,7 +94,7 @@ #define CONFIG_ENV_SIZE8192 #define CONFIG_ENV_IS_NOWHERE -/* SPI */ +/* SPI - enable all SPI flash types for testing purposes */ #define CONFIG_SANDBOX_SPI #define CONFIG_CMD_SF #define CONFIG_CMD_SF_TEST @@ -102,7 +102,13 @@ #define CONFIG_SPI_FLASH #define CONFIG_OF_SPI #define CONFIG_OF_SPI_FLASH +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_SPI_FLASH_EON +#define CONFIG_SPI_FLASH_GIGADEVICE +#define CONFIG_SPI_FLASH_MACRONIX #define CONFIG_SPI_FLASH_SANDBOX +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_SST #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SPI_FLASH_WINBOND -- 2.1.0.rc2.206.gedb03e5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 08/30] dm: sandbox: Add a SPI emulation uclass
U-Boot includes a SPI emulation driver already but it is not explicit, and
is hidden in the SPI flash code.
Conceptually with sandbox's SPI implementation we have a layer which
creates SPI bus transitions and a layer which interprets them, currently
only for SPI flash. The latter is actually an emulation, and it should be
possible to add more than one emulation - not just SPI flash.
Add a SPI emulation uclass so that other emulations can be plugged in to
support different types of emulated devices on difference buses/chip
selects.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Fix comment on 'slave' parameter to match the parameter name
drivers/spi/Makefile | 1 +
drivers/spi/spi-emul-uclass.c | 15 +++
include/dm/uclass-id.h| 1 +
include/spi.h | 30 ++
4 files changed, 47 insertions(+)
create mode 100644 drivers/spi/spi-emul-uclass.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d1f1dd0..a1de028 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -8,6 +8,7 @@
# There are many options which enable SPI, so make this library available
ifdef CONFIG_DM_SPI
obj-y += spi-uclass.o
+obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o
else
obj-y += spi.o
endif
diff --git a/drivers/spi/spi-emul-uclass.c b/drivers/spi/spi-emul-uclass.c
new file mode 100644
index 000..b436a0e
--- /dev/null
+++ b/drivers/spi/spi-emul-uclass.c
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include dm.h
+#include spi.h
+#include spi_flash.h
+
+UCLASS_DRIVER(spi_emul) = {
+ .id = UCLASS_SPI_EMUL,
+ .name = spi_emul,
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 8207483..dce405e 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -18,6 +18,7 @@ enum uclass_id {
UCLASS_TEST,
UCLASS_TEST_FDT,
UCLASS_TEST_BUS,
+ UCLASS_SPI_EMUL,/* sandbox SPI device emulator */
/* U-Boot uclasses start here */
UCLASS_GPIO,/* Bank of general-purpose I/O pins */
diff --git a/include/spi.h b/include/spi.h
index 13e9a1e..d60414e 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -423,6 +423,35 @@ struct dm_spi_ops {
int (*set_mode)(struct udevice *bus, uint mode);
};
+struct dm_spi_emul_ops {
+ /**
+* SPI transfer
+*
+* This writes bitlen bits out the SPI MOSI port and simultaneously
+* clocks bitlen bits in the SPI MISO port. That's just the way SPI
+* works. Here the device is a slave.
+*
+* The source of the outgoing bits is the dout parameter and the
+* destination of the input bits is the din parameter. Note that
+* dout and din can point to the same memory location, in which
+* case the input data overwrites the output data (since both are
+* buffered by temporary variables, this is OK).
+*
+* spi_xfer() interface:
+* @slave: The SPI slave which will be sending/receiving the data.
+* @bitlen: How many bits to write and read.
+* @dout: Pointer to a string of bits sent to the device. The
+* bits are held in a byte array and are sent MSB first.
+* @din:Pointer to a string of bits that will be sent back to
+* the master.
+* @flags: A bitwise combination of SPI_XFER_* flags.
+*
+* Returns: 0 on success, not -1 on failure
+*/
+ int (*xfer)(struct udevice *slave, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags);
+};
+
int spi_find_bus_and_cs(int busnum, int cs, struct udevice **busp,
struct udevice **devp);
@@ -443,6 +472,7 @@ int sandbox_spi_get_emul(struct sandbox_state *state,
/* Access the serial operations for a device */
#define spi_get_ops(dev) ((struct dm_spi_ops *)(dev)-driver-ops)
+#define spi_emul_get_ops(dev) ((struct dm_spi_emul_ops *)(dev)-driver-ops)
#endif /* CONFIG_DM_SPI */
#endif /* _SPI_H_ */
--
2.1.0.rc2.206.gedb03e5
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[U-Boot] [PATCH v2 01/30] dm: Fix repeated comment in README
A merge error ended up repeating a similar sentence twice. Fix it. Signed-off-by: Simon Glass s...@chromium.org --- Changes in v2: - Add new patch to fix README merge error README | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/README b/README index 0a0f528..298e8d6 100644 --- a/README +++ b/README @@ -3849,12 +3849,9 @@ Configuration Settings: The memory will be freed (or in fact just forgotton) when U-Boot relocates itself. - Pre-relocation malloc() is only supported on sandbox + Pre-relocation malloc() is only supported on ARM and sandbox at present but is fairly easy to enable for other archs. - Pre-relocation malloc() is only supported on ARM at present - but is fairly easy to enable for other archs. - - CONFIG_SYS_BOOTM_LEN: Normally compressed uImages are limited to an uncompressed size of 8 MBytes. If this is not enough, -- 2.1.0.rc2.206.gedb03e5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 04/30] sandbox: dts: Add a SPI device and cros_ec device
Add a SPI device which can be used for testing SPI flash features in
sandbox.
Also add a cros_ec device since with driver model the Chrome OS EC
emulation will not otherwise be available.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Adjust binding to avoid Linux-specific mentions
arch/sandbox/dts/sandbox.dts | 26 ++
doc/device-tree-bindings/mtd/spi/spi-flash.txt | 25 +
2 files changed, 51 insertions(+)
create mode 100644 doc/device-tree-bindings/mtd/spi/spi-flash.txt
diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
index 797478a..7614715 100644
--- a/arch/sandbox/dts/sandbox.dts
+++ b/arch/sandbox/dts/sandbox.dts
@@ -1,6 +1,9 @@
/dts-v1/;
/ {
+ #address-cells = 1;
+ #size-cells = 0;
+
chosen {
stdout-path = /serial;
};
@@ -131,4 +134,27 @@
num-gpios = 20;
};
+ spi@0 {
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0;
+ compatible = sandbox,spi;
+ cs-gpios = 0, gpio_a 0;
+ flash@0 {
+ reg = 0;
+ compatible = spansion,m25p16, sandbox,spi-flash;
+ spi-max-frequency = 4000;
+ sandbox,filename = spi.bin;
+ };
+ };
+
+ cros-ec@0 {
+ compatible = google,cros-ec;
+ #address-cells = 1;
+ #size-cells = 1;
+ firmware_storage_spi: flash@0 {
+ reg = 0 0x40;
+ };
+ };
+
};
diff --git a/doc/device-tree-bindings/mtd/spi/spi-flash.txt
b/doc/device-tree-bindings/mtd/spi/spi-flash.txt
new file mode 100644
index 000..85522d8
--- /dev/null
+++ b/doc/device-tree-bindings/mtd/spi/spi-flash.txt
@@ -0,0 +1,25 @@
+* MTD SPI driver for serial flash chips
+
+Required properties:
+- #address-cells, #size-cells : Must be present if the device has sub-nodes
+ representing partitions.
+- compatible : Should be the manufacturer and the name of the chip. Bear in
+ mind that the DT binding is not U-Boot-only, but in case of
+ U-Boot, see spi_flash_params_table table in
+ drivers/mtd/spi/sf_params.c for the list of supported chips.
+- reg : Chip-Select number
+- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at
+
+Optional properties:
+ - memory-map : Address and size of the flash, if memory mapped. This may
+apply to Intel chipsets, which tend to memory-map flash.
+
+Example:
+
+ flash: m25p80@0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = spansion,m25p80;
+ reg = 0;
+ spi-max-frequency = 4000;
+ };
--
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[U-Boot] [PATCH v2 06/30] spi: Add brackets and tidy defines in spi.h
Some of the #defines in spi.h are not bracketed. To avoid future mistakes add brackets. Also add an explanatory comment for SPI_CONN_DUAL_... Signed-off-by: Simon Glass s...@chromium.org Reviewed-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com --- Changes in v2: None include/spi.h | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/include/spi.h b/include/spi.h index ffd6647..b673be2 100644 --- a/include/spi.h +++ b/include/spi.h @@ -30,24 +30,24 @@ #define SPI_XFER_MMAP 0x08/* Memory Mapped start */ #define SPI_XFER_MMAP_END 0x10/* Memory Mapped End */ #define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END) -#define SPI_XFER_U_PAGE(1 5) +#define SPI_XFER_U_PAGE(1 5) /* SPI TX operation modes */ -#define SPI_OPM_TX_QPP 1 0 +#define SPI_OPM_TX_QPP (1 0) /* SPI RX operation modes */ -#define SPI_OPM_RX_AS 1 0 -#define SPI_OPM_RX_DOUT1 1 -#define SPI_OPM_RX_DIO 1 2 -#define SPI_OPM_RX_QOF 1 3 -#define SPI_OPM_RX_QIOF1 4 -#define SPI_OPM_RX_EXTNSPI_OPM_RX_AS | SPI_OPM_RX_DOUT | \ +#define SPI_OPM_RX_AS (1 0) +#define SPI_OPM_RX_DOUT(1 1) +#define SPI_OPM_RX_DIO (1 2) +#define SPI_OPM_RX_QOF (1 3) +#define SPI_OPM_RX_QIOF(1 4) +#define SPI_OPM_RX_EXTN(SPI_OPM_RX_AS | SPI_OPM_RX_DOUT | \ SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \ - SPI_OPM_RX_QIOF + SPI_OPM_RX_QIOF) -/* SPI bus connection options */ -#define SPI_CONN_DUAL_SHARED 1 0 -#define SPI_CONN_DUAL_SEPARATED1 1 +/* SPI bus connection options - see enum spi_dual_flash */ +#define SPI_CONN_DUAL_SHARED (1 0) +#define SPI_CONN_DUAL_SEPARATED(1 1) /* Header byte that marks the start of the message */ #define SPI_PREAMBLE_END_BYTE 0xec -- 2.1.0.rc2.206.gedb03e5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 18/30] exynos: universal_c210: Move to driver model soft_spi
Adjust this board to use the driver model soft_spi implementation.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/arm/dts/exynos4210-universal_c210.dts | 13
board/samsung/universal_c210/universal.c | 52 --
include/configs/s5pc210_universal.h| 11 +--
3 files changed, 14 insertions(+), 62 deletions(-)
diff --git a/arch/arm/dts/exynos4210-universal_c210.dts
b/arch/arm/dts/exynos4210-universal_c210.dts
index cf3354f..9139810 100644
--- a/arch/arm/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/dts/exynos4210-universal_c210.dts
@@ -41,6 +41,19 @@
status = disabled;
};
+ soft-spi {
+ compatible = u-boot,soft-spi;
+ cs-gpio = gpio 235 0;/* Y43 */
+ sclk-gpio = gpio 225 0; /* Y31 */
+ mosi-gpio = gpio 227 0; /* Y33 */
+ miso-gpio = gpio 224 0; /* Y30 */
+ spi-delay-us = 1;
+ #address-cells = 1;
+ #size-cells = 0;
+ cs@0 {
+ };
+ };
+
fimd@11c0 {
compatible = samsung,exynos-fimd;
reg = 0x11c0 0xa4;
diff --git a/board/samsung/universal_c210/universal.c
b/board/samsung/universal_c210/universal.c
index c04f48c..22b0849 100644
--- a/board/samsung/universal_c210/universal.c
+++ b/board/samsung/universal_c210/universal.c
@@ -201,53 +201,6 @@ int exynos_early_init_f(void)
return 0;
}
-#ifdef CONFIG_SOFT_SPI
-static void soft_spi_init(void)
-{
- gpio_direction_output(CONFIG_SOFT_SPI_GPIO_SCLK,
- CONFIG_SOFT_SPI_MODE SPI_CPOL);
- gpio_direction_output(CONFIG_SOFT_SPI_GPIO_MOSI, 1);
- gpio_direction_input(CONFIG_SOFT_SPI_GPIO_MISO);
- gpio_direction_output(CONFIG_SOFT_SPI_GPIO_CS,
- !(CONFIG_SOFT_SPI_MODE SPI_CS_HIGH));
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
- !(CONFIG_SOFT_SPI_MODE SPI_CS_HIGH));
- SPI_SCL(1);
- gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
- CONFIG_SOFT_SPI_MODE SPI_CS_HIGH);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
- !(CONFIG_SOFT_SPI_MODE SPI_CS_HIGH));
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return bus == 0 cs == 0;
-}
-
-void universal_spi_scl(int bit)
-{
- gpio_set_value(CONFIG_SOFT_SPI_GPIO_SCLK, bit);
-}
-
-void universal_spi_sda(int bit)
-{
- gpio_set_value(CONFIG_SOFT_SPI_GPIO_MOSI, bit);
-}
-
-int universal_spi_read(void)
-{
- return gpio_get_value(CONFIG_SOFT_SPI_GPIO_MISO);
-}
-#endif
-
static void init_pmic_lcd(void)
{
unsigned char val;
@@ -332,8 +285,6 @@ void exynos_cfg_lcd_gpio(void)
/* gpio pad configuration for LCD reset. */
gpio_request(EXYNOS4_GPIO_Y45, lcd_reset);
gpio_cfg_pin(EXYNOS4_GPIO_Y45, S5P_GPIO_OUTPUT);
-
- spi_init();
}
int mipi_power(void)
@@ -401,9 +352,6 @@ int exynos_init(void)
break;
}
-#ifdef CONFIG_SOFT_SPI
- soft_spi_init();
-#endif
check_hw_revision();
printf(HW Revision:\t0x%x\n, board_rev);
diff --git a/include/configs/s5pc210_universal.h
b/include/configs/s5pc210_universal.h
index b729bfc..05361ec 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -189,16 +189,7 @@
* SPI Settings
*/
#define CONFIG_SOFT_SPI
-#define CONFIG_SOFT_SPI_MODE SPI_MODE_3
-#define CONFIG_SOFT_SPI_GPIO_SCLK EXYNOS4_GPIO_Y31
-#define CONFIG_SOFT_SPI_GPIO_MOSI EXYNOS4_GPIO_Y33
-#define CONFIG_SOFT_SPI_GPIO_MISO EXYNOS4_GPIO_Y30
-#define CONFIG_SOFT_SPI_GPIO_CS EXYNOS4_GPIO_Y43
-
-#define SPI_DELAY udelay(1)
-#define SPI_SCL(bit) universal_spi_scl(bit)
-#define SPI_SDA(bit) universal_spi_sda(bit)
-#define SPI_READ universal_spi_read()
+
#ifndef__ASSEMBLY__
void universal_spi_scl(int bit);
void universal_spi_sda(int bit);
--
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[U-Boot] [PATCH v2 19/30] sf: Add an empty entry to the parameter list
The list is supposed to be terminated with a NULL name, but is not. If a
board probes a chip which does not appear in the table, U-Boot will crash
(at least on sandbox).
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/mtd/spi/sf_params.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 53efdc8..b3a3c7b 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -117,6 +117,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
{W25Q64DW, 0xef6017, 0x0, 64 * 1024, 128, RD_FULL,
WR_QPP | SECT_4K},
{W25Q128FW, 0xef6018, 0x0, 64 * 1024, 256, RD_FULL,
WR_QPP | SECT_4K},
#endif
+ {}, /* Empty entry to terminate the list */
/*
* Note:
* Below paired flash devices has similar spi_flash params.
--
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[U-Boot] [PATCH v2 07/30] dm: spi: Add a uclass for SPI
Add a uclass which provides access to SPI buses and includes operations
required by SPI.
For a time driver model will need to co-exist with the legacy SPI interface
so some parts of the header file are changed depending on which is in use.
The exports are adjusted also since some functions are not available with
driver model.
Boards must define CONFIG_DM_SPI to use driver model for SPI.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Use 'bus' instead of 'dev' to make the API clearer
- Fix code nits from Daniel Schwierzeck
- Add missing comments for struct spi_slave
common/exports.c | 4 +-
drivers/spi/Makefile | 4 +
drivers/spi/spi-uclass.c | 252 +++
include/dm/uclass-id.h | 1 +
include/spi.h| 140 ++
5 files changed, 400 insertions(+), 1 deletion(-)
create mode 100644 drivers/spi/spi-uclass.c
diff --git a/common/exports.c b/common/exports.c
index b97ca48..88fcfc8 100644
--- a/common/exports.c
+++ b/common/exports.c
@@ -27,10 +27,12 @@ unsigned long get_version(void)
# define i2c_write dummy
# define i2c_read dummy
#endif
-#ifndef CONFIG_CMD_SPI
+#if !defined(CONFIG_CMD_SPI) || defined(CONFIG_DM_SPI)
# define spi_init dummy
# define spi_setup_slave dummy
# define spi_free_slavedummy
+#endif
+#ifndef CONFIG_CMD_SPI
# define spi_claim_bus dummy
# define spi_release_bus dummy
# define spi_xfer dummy
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index f02c35a..d1f1dd0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -6,7 +6,11 @@
#
# There are many options which enable SPI, so make this library available
+ifdef CONFIG_DM_SPI
+obj-y += spi-uclass.o
+else
obj-y += spi.o
+endif
obj-$(CONFIG_EP93XX_SPI) += ep93xx_spi.o
obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
new file mode 100644
index 000..cbdcde1
--- /dev/null
+++ b/drivers/spi/spi-uclass.c
@@ -0,0 +1,252 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include dm.h
+#include errno.h
+#include fdtdec.h
+#include spi.h
+#include dm/device-internal.h
+#include dm/uclass-internal.h
+#include dm/root.h
+#include dm/lists.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int spi_set_speed_mode(struct udevice *bus, int speed, int mode)
+{
+ struct dm_spi_ops *ops;
+ int ret;
+
+ ops = spi_get_ops(bus);
+ if (ops-set_speed)
+ ret = ops-set_speed(bus, speed);
+ else
+ ret = -EINVAL;
+ if (ret) {
+ printf(Cannot set speed (err=%d)\n, ret);
+ return ret;
+ }
+
+ if (ops-set_mode)
+ ret = ops-set_mode(bus, mode);
+ else
+ ret = -EINVAL;
+ if (ret) {
+ printf(Cannot set mode (err=%d)\n, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ struct udevice *dev = slave-dev;
+ struct udevice *bus = dev-parent;
+ struct dm_spi_ops *ops = spi_get_ops(bus);
+ struct dm_spi_bus *spi = bus-uclass_priv;
+ int speed;
+ int ret;
+
+ speed = slave-max_hz;
+ if (spi-max_hz) {
+ if (speed)
+ speed = min(speed, spi-max_hz);
+ else
+ speed = spi-max_hz;
+ }
+ if (!speed)
+ speed = 10;
+ ret = spi_set_speed_mode(bus, speed, slave-mode);
+ if (ret)
+ return ret;
+
+ return ops-claim_bus ? ops-claim_bus(bus) : 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+ struct udevice *dev = slave-dev;
+ struct udevice *bus = dev-parent;
+ struct dm_spi_ops *ops = spi_get_ops(bus);
+
+ if (ops-release_bus)
+ ops-release_bus(bus);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+const void *dout, void *din, unsigned long flags)
+{
+ struct udevice *dev = slave-dev;
+ struct udevice *bus = dev-parent;
+
+ if (bus-uclass-uc_drv-id != UCLASS_SPI)
+ return -EOPNOTSUPP;
+
+ return spi_get_ops(bus)-xfer(dev, bitlen, dout, din, flags);
+}
+
+int spi_post_bind(struct udevice *dev)
+{
+ /* Scan the bus for devices */
+ return dm_scan_fdt_node(dev, gd-fdt_blob, dev-of_offset, false);
+}
+
+int spi_post_probe(struct udevice *dev)
+{
+ struct dm_spi_bus *spi = dev-uclass_priv;
+
+ spi-max_hz = fdtdec_get_int(gd-fdt_blob, dev-of_offset,
+spi-max-frequency, 0);
+
+ return 0;
+}
+
+int spi_bind_device(struct udevice *bus, int cs, const char *drv_name,
+ const char *dev_name, struct udevice **slavep)
+{
+ struct driver *drv;
+ int ret;
+
+ drv =
[U-Boot] [PATCH v2 11/30] dm: spi: Adjust cmd_spi to work with driver model
Driver model uses a different way to find the SPI bus and slave from the
numbered devices given on the command line. Adjust the code to suit.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
common/cmd_spi.c | 34 +++---
1 file changed, 27 insertions(+), 7 deletions(-)
diff --git a/common/cmd_spi.c b/common/cmd_spi.c
index be5709c..4ebd41b 100644
--- a/common/cmd_spi.c
+++ b/common/cmd_spi.c
@@ -11,6 +11,7 @@
#include common.h
#include command.h
+#include dm.h
#include errno.h
#include spi.h
@@ -42,19 +43,35 @@ static uchardin[MAX_SPI_BYTES];
static int do_spi_xfer(int bus, int cs)
{
struct spi_slave *slave;
- int rcode = 0;
+ int ret = 0;
+#ifdef CONFIG_DM_SPI
+ struct udevice *dev;
+
+ ret = spi_get_bus_and_cs(bus, cs, 100, mode, NULL, 0, dev,
+ slave);
+ if (ret)
+ return ret;
+#else
slave = spi_setup_slave(bus, cs, 100, mode);
if (!slave) {
printf(Invalid device %d:%d\n, bus, cs);
return -EINVAL;
}
+#endif
- spi_claim_bus(slave);
- if (spi_xfer(slave, bitlen, dout, din,
-SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
- printf(Error during SPI transaction\n);
- rcode = -EIO;
+ ret = spi_claim_bus(slave);
+ if (ret)
+ goto done;
+ ret = spi_xfer(slave, bitlen, dout, din,
+ SPI_XFER_BEGIN | SPI_XFER_END);
+#ifndef CONFIG_DM_SPI
+ /* We don't get an error code in this case */
+ if (ret)
+ ret = -EIO;
+#endif
+ if (ret) {
+ printf(Error %d during SPI transaction\n, ret);
} else {
int j;
@@ -62,10 +79,13 @@ static int do_spi_xfer(int bus, int cs)
printf(%02X, din[j]);
printf(\n);
}
+done:
spi_release_bus(slave);
+#ifndef CONFIG_DM_SPI
spi_free_slave(slave);
+#endif
- return rcode;
+ return ret;
}
/*
--
2.1.0.rc2.206.gedb03e5
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 20/30] sf: Tidy up public and private header files
Since spi_flash.h is supposed to be the public API for SPI flash, move
private things to sf_internal.h. Also tidy up a few comment nits.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
board/buffalo/lsxl/lsxl.c | 3 +-
common/cmd_sf.c| 1 +
drivers/mtd/spi/ramtron.c | 1 +
drivers/mtd/spi/sf_internal.h | 67 +-
drivers/mtd/spi/spi_spl_load.c | 1 +
include/spi_flash.h| 57 ---
6 files changed, 70 insertions(+), 60 deletions(-)
diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c
index 659a124..c1cb07b 100644
--- a/board/buffalo/lsxl/lsxl.c
+++ b/board/buffalo/lsxl/lsxl.c
@@ -13,11 +13,12 @@
#include malloc.h
#include netdev.h
#include miiphy.h
+#include spi.h
+#include spi_flash.h
#include asm/arch/kirkwood.h
#include asm/arch/cpu.h
#include asm/arch/mpp.h
#include asm/arch/gpio.h
-#include spi_flash.h
#include lsxl.h
diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index b4ceb71..1bb41d3 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -9,6 +9,7 @@
#include common.h
#include div64.h
#include malloc.h
+#include spi.h
#include spi_flash.h
#include asm/io.h
diff --git a/drivers/mtd/spi/ramtron.c b/drivers/mtd/spi/ramtron.c
index d50da37..a23032c 100644
--- a/drivers/mtd/spi/ramtron.c
+++ b/drivers/mtd/spi/ramtron.c
@@ -35,6 +35,7 @@
#include common.h
#include malloc.h
+#include spi.h
#include spi_flash.h
#include sf_internal.h
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 19d4914..5b7670c 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -10,6 +10,36 @@
#ifndef _SF_INTERNAL_H_
#define _SF_INTERNAL_H_
+#include linux/types.h
+#include linux/compiler.h
+
+/* Dual SPI flash memories - see SPI_COMM_DUAL_... */
+enum spi_dual_flash {
+ SF_SINGLE_FLASH = 0,
+ SF_DUAL_STACKED_FLASH = 1 0,
+ SF_DUAL_PARALLEL_FLASH = 1 1,
+};
+
+/* Enum list - Full read commands */
+enum spi_read_cmds {
+ ARRAY_SLOW = 1 0,
+ DUAL_OUTPUT_FAST= 1 1,
+ DUAL_IO_FAST= 1 2,
+ QUAD_OUTPUT_FAST= 1 3,
+ QUAD_IO_FAST= 1 4,
+};
+
+#define RD_EXTN(ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
+#define RD_FULL(RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
+
+/* sf param flags */
+enum {
+ SECT_4K = 1 0,
+ SECT_32K= 1 1,
+ E_FSR = 1 2,
+ WR_QPP = 1 3,
+};
+
#define SPI_FLASH_3B_ADDR_LEN 3
#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
#define SPI_FLASH_16MB_BOUN0x100
@@ -30,12 +60,12 @@
#define CMD_WRITE_STATUS 0x01
#define CMD_PAGE_PROGRAM 0x02
#define CMD_WRITE_DISABLE 0x04
-#define CMD_READ_STATUS0x05
+#define CMD_READ_STATUS0x05
#define CMD_QUAD_PAGE_PROGRAM 0x32
#define CMD_READ_STATUS1 0x35
#define CMD_WRITE_ENABLE 0x06
-#define CMD_READ_CONFIG0x35
-#define CMD_FLAG_STATUS0x70
+#define CMD_READ_CONFIG0x35
+#define CMD_FLAG_STATUS0x70
/* Read commands */
#define CMD_READ_ARRAY_SLOW0x03
@@ -57,7 +87,7 @@
/* Common status */
#define STATUS_WIP (1 0)
#define STATUS_QEB_WINSPAN (1 1)
-#define STATUS_QEB_MXIC(1 6)
+#define STATUS_QEB_MXIC(1 6)
#define STATUS_PEC (1 7)
#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
@@ -66,19 +96,42 @@
/* Flash timeout values */
#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
-#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
+#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ)
/* SST specific */
#ifdef CONFIG_SPI_FLASH_SST
-# define SST_WP0x01/* Supports AAI word program */
+# define SST_WP0x01/* Supports AAI word program */
# define CMD_SST_BP0x02/* Byte Program */
-# define CMD_SST_AAI_WP0xAD/* Auto Address Incr Word
Program */
+# define CMD_SST_AAI_WP0xAD/* Auto Address Incr Word Program */
int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
const void *buf);
#endif
+/**
+ * struct spi_flash_params - SPI/QSPI flash device params structure
+ *
+ * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
+ * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
+ * @ext_jedec: Device ext_jedec ID
+ * @sector_size: Sector size of this device
+ * @nr_sectors:No.of sectors on this device
+ * @e_rd_cmd: Enum list for read
[U-Boot] [PATCH v2 17/30] dm: exynos: Convert SPI to driver model
Move the exynos SPI driver over to driver model. This removes quite a bit
of boilerplate from the driver, although it adds some for driver model.
A few device tree additions are needed to make the SPI flash available.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add additional debug() statements
- Use 'bus' instead of 'dev' to distinguish bus from slave
- Adjust xfer() method for new API
arch/arm/dts/exynos5250-snow.dts | 8 +
arch/arm/dts/exynos5420-peach-pit.dts | 1 +
board/samsung/common/board.c | 3 -
drivers/spi/exynos_spi.c | 518 --
include/configs/exynos-common.h | 1 +
5 files changed, 195 insertions(+), 336 deletions(-)
diff --git a/arch/arm/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts
index 2003412..6fd9275 100644
--- a/arch/arm/dts/exynos5250-snow.dts
+++ b/arch/arm/dts/exynos5250-snow.dts
@@ -53,6 +53,14 @@
};
};
+ spi@12d3 {
+ spi-max-frequency = 5000;
+ firmware_storage_spi: flash@0 {
+ compatible = spi-flash;
+ reg = 0;
+ };
+ };
+
spi@131b {
spi-max-frequency = 100;
spi-deactivate-delay = 100;
diff --git a/arch/arm/dts/exynos5420-peach-pit.dts
b/arch/arm/dts/exynos5420-peach-pit.dts
index c4c4b8e..fde863d 100644
--- a/arch/arm/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/dts/exynos5420-peach-pit.dts
@@ -140,6 +140,7 @@
spi@12d3 { /* spi1 */
spi-max-frequency = 5000;
firmware_storage_spi: flash@0 {
+ compatible = spi-flash;
reg = 0;
/*
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index c119641..e1fc123 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -87,9 +87,6 @@ int board_init(void)
boot_temp_check();
#endif
-#ifdef CONFIG_EXYNOS_SPI
- spi_init();
-#endif
return exynos_init();
}
diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c
index 2969184..e96a9ce 100644
--- a/drivers/spi/exynos_spi.c
+++ b/drivers/spi/exynos_spi.c
@@ -6,6 +6,8 @@
*/
#include common.h
+#include dm.h
+#include errno.h
#include malloc.h
#include spi.h
#include fdtdec.h
@@ -19,176 +21,35 @@
DECLARE_GLOBAL_DATA_PTR;
-/* Information about each SPI controller */
-struct spi_bus {
+struct exynos_spi_platdata {
enum periph_id periph_id;
s32 frequency; /* Default clock frequency, -1 for none */
struct exynos_spi *regs;
- int inited; /* 1 if this bus is ready for use */
- int node;
uint deactivate_delay_us; /* Delay to wait after deactivate */
};
-/* A list of spi buses that we know about */
-static struct spi_bus spi_bus[EXYNOS5_SPI_NUM_CONTROLLERS];
-static unsigned int bus_count;
-
-struct exynos_spi_slave {
- struct spi_slave slave;
+struct exynos_spi_priv {
struct exynos_spi *regs;
unsigned int freq; /* Default frequency */
unsigned int mode;
enum periph_id periph_id; /* Peripheral ID for this device */
unsigned int fifo_size;
int skip_preamble;
- struct spi_bus *bus;/* Pointer to our SPI bus info */
ulong last_transaction_us; /* Time of last transaction end */
};
-static struct spi_bus *spi_get_bus(unsigned dev_index)
-{
- if (dev_index bus_count)
- return spi_bus[dev_index];
- debug(%s: invalid bus %d, __func__, dev_index);
-
- return NULL;
-}
-
-static inline struct exynos_spi_slave *to_exynos_spi(struct spi_slave *slave)
-{
- return container_of(slave, struct exynos_spi_slave, slave);
-}
-
-/**
- * Setup the driver private data
- *
- * @param bus ID of the bus that the slave is attached to
- * @param cs ID of the chip select connected to the slave
- * @param max_hz Required spi frequency
- * @param mode Required spi mode (clk polarity, clk phase and
- * master or slave)
- * @return new device or NULL
- */
-struct spi_slave *spi_setup_slave(unsigned int busnum, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct exynos_spi_slave *spi_slave;
- struct spi_bus *bus;
-
- if (!spi_cs_is_valid(busnum, cs)) {
- debug(%s: Invalid bus/chip select %d, %d\n, __func__,
- busnum, cs);
- return NULL;
- }
-
- spi_slave = spi_alloc_slave(struct exynos_spi_slave, busnum, cs);
- if (!spi_slave) {
- debug(%s: Could not allocate spi_slave\n, __func__);
- return NULL;
- }
-
- bus = spi_bus[busnum];
- spi_slave-bus = bus;
- spi_slave-regs = bus-regs;
- spi_slave-mode =
[U-Boot] [PATCH v2 02/30] sandbox: Convert SPI flash emulation to use sf_params
At present sandbox has its own table of supported SPI flash chips. Now that
the SPI flash system is fully consolidated and has its own list, sandbox
should use that.
This enables us to expand the number of chips that sandbox supports.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes in v2: None
drivers/mtd/spi/sandbox.c | 114 --
1 file changed, 38 insertions(+), 76 deletions(-)
diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
index a62ef4c..98e0a34 100644
--- a/drivers/mtd/spi/sandbox.c
+++ b/drivers/mtd/spi/sandbox.c
@@ -51,46 +51,7 @@ static const char *sandbox_sf_state_name(enum
sandbox_sf_state state)
/* Assume all SPI flashes have 3 byte addresses since they do atm */
#define SF_ADDR_LEN3
-struct sandbox_spi_flash_erase_commands {
- u8 cmd;
- u32 size;
-};
-#define IDCODE_LEN 5
-#define MAX_ERASE_CMDS 3
-struct sandbox_spi_flash_data {
- const char *name;
- u8 idcode[IDCODE_LEN];
- u32 size;
- const struct sandbox_spi_flash_erase_commands
- erase_cmds[MAX_ERASE_CMDS];
-};
-
-/* Structure describing all the flashes we know how to emulate */
-static const struct sandbox_spi_flash_data sandbox_sf_flashes[] = {
- {
- M25P16, { 0x20, 0x20, 0x15 }, (2 20),
- { /* erase commands */
- { 0xd8, (64 10), }, /* sector */
- { 0xc7, (2 20), }, /* bulk */
- },
- },
- {
- W25Q32, { 0xef, 0x40, 0x16 }, (4 20),
- { /* erase commands */
- { 0x20, (4 10), }, /* 4KB */
- { 0xd8, (64 10), }, /* sector */
- { 0xc7, (4 20), }, /* bulk */
- },
- },
- {
- W25Q128, { 0xef, 0x40, 0x18 }, (16 20),
- { /* erase commands */
- { 0x20, (4 10), }, /* 4KB */
- { 0xd8, (64 10), }, /* sector */
- { 0xc7, (16 20), }, /* bulk */
- },
- },
-};
+#define IDCODE_LEN 3
/* Used to quickly bulk erase backing store */
static u8 sandbox_sf_0xff[0x1000];
@@ -109,7 +70,8 @@ struct sandbox_spi_flash {
*/
enum sandbox_sf_state state;
uint cmd;
- const void *cmd_data;
+ /* Erase size of current erase command */
+ uint erase_size;
/* Current position in the flash; used when reading/writing/etc... */
uint off;
/* How many address bytes we've consumed */
@@ -117,7 +79,7 @@ struct sandbox_spi_flash {
/* The current flash status (see STAT_XXX defines above) */
u16 status;
/* Data describing the flash we're emulating */
- const struct sandbox_spi_flash_data *data;
+ const struct spi_flash_params *data;
/* The file on disk to serv up data from */
int fd;
};
@@ -127,8 +89,8 @@ static int sandbox_sf_setup(void **priv, const char *spec)
/* spec = idcode:file */
struct sandbox_spi_flash *sbsf;
const char *file;
- size_t i, len, idname_len;
- const struct sandbox_spi_flash_data *data;
+ size_t len, idname_len;
+ const struct spi_flash_params *data;
file = strchr(spec, ':');
if (!file) {
@@ -138,15 +100,14 @@ static int sandbox_sf_setup(void **priv, const char *spec)
idname_len = file - spec;
++file;
- for (i = 0; i ARRAY_SIZE(sandbox_sf_flashes); ++i) {
- data = sandbox_sf_flashes[i];
+ for (data = spi_flash_params_table; data-name; data++) {
len = strlen(data-name);
if (idname_len != len)
continue;
if (!memcmp(spec, data-name, len))
break;
}
- if (i == ARRAY_SIZE(sandbox_sf_flashes)) {
+ if (!data-name) {
printf(sandbox_sf: unknown flash '%*s'\n, (int)idname_len,
spec);
goto error;
@@ -223,7 +184,6 @@ static int sandbox_sf_process_cmd(struct sandbox_spi_flash
*sbsf, const u8 *rx,
sbsf-pad_addr_bytes = 1;
case CMD_READ_ARRAY_SLOW:
case CMD_PAGE_PROGRAM:
- state_addr:
sbsf-state = SF_ADDR;
break;
case CMD_WRITE_DISABLE:
@@ -241,24 +201,25 @@ static int sandbox_sf_process_cmd(struct
sandbox_spi_flash *sbsf, const u8 *rx,
sbsf-status |= STAT_WEL;
break;
default: {
- size_t i;
-
- /* handle erase commands first */
- for (i = 0; i MAX_ERASE_CMDS; ++i) {
- const struct sandbox_spi_flash_erase_commands *
- erase_cmd = sbsf-data-erase_cmds[i];
-
- if
[U-Boot] [PATCH v2 28/30] dm: cros_ec: Add support for driver model
Add support for driver model if enabled. This involves minimal changes
to the code, mostly just plumbing around the edges.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
common/cros_ec.c | 30 ++
drivers/misc/cros_ec.c | 122 +
drivers/misc/cros_ec_sandbox.c | 9 ++-
include/cros_ec.h | 27 -
include/dm/uclass-id.h | 1 +
5 files changed, 174 insertions(+), 15 deletions(-)
diff --git a/common/cros_ec.c b/common/cros_ec.c
index b8ce1b5..bb299bc 100644
--- a/common/cros_ec.c
+++ b/common/cros_ec.c
@@ -10,25 +10,44 @@
#include common.h
#include cros_ec.h
+#include dm.h
+#include errno.h
+
DECLARE_GLOBAL_DATA_PTR;
+#ifndef CONFIG_DM_CROS_EC
struct local_info {
struct cros_ec_dev *cros_ec_dev;/* Pointer to cros_ec device */
int cros_ec_err;/* Error for cros_ec, 0 if ok */
};
static struct local_info local;
+#endif
struct cros_ec_dev *board_get_cros_ec_dev(void)
{
+#ifdef CONFIG_DM_CROS_EC
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device(UCLASS_CROS_EC, 0, dev);
+ if (ret) {
+ debug(%s: Error %d\n, __func__, ret);
+ return NULL;
+ }
+ return dev-uclass_priv;
+#else
return local.cros_ec_dev;
+#endif
}
static int board_init_cros_ec_devices(const void *blob)
{
+#ifndef CONFIG_DM_CROS_EC
local.cros_ec_err = cros_ec_init(blob, local.cros_ec_dev);
if (local.cros_ec_err)
return -1; /* Will report in board_late_init() */
+#endif
return 0;
}
@@ -40,5 +59,16 @@ int cros_ec_board_init(void)
int cros_ec_get_error(void)
{
+#ifdef CONFIG_DM_CROS_EC
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device(UCLASS_CROS_EC, 0, dev);
+ if (ret ret != -ENODEV)
+ return ret;
+
+ return 0;
+#else
return local.cros_ec_err;
+#endif
}
diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c
index 068373b..521edfd 100644
--- a/drivers/misc/cros_ec.c
+++ b/drivers/misc/cros_ec.c
@@ -16,6 +16,7 @@
#include common.h
#include command.h
+#include dm.h
#include i2c.h
#include cros_ec.h
#include fdtdec.h
@@ -24,6 +25,8 @@
#include asm/errno.h
#include asm/io.h
#include asm-generic/gpio.h
+#include dm/device-internal.h
+#include dm/uclass-internal.h
#ifdef DEBUG_TRACE
#define debug_trace(fmt, b...) debug(fmt, #b)
@@ -38,7 +41,9 @@ enum {
CROS_EC_CMD_HASH_TIMEOUT_MS = 2000,
};
+#ifndef CONFIG_DM_CROS_EC
static struct cros_ec_dev static_dev, *last_dev;
+#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -204,6 +209,9 @@ static int send_command_proto3(struct cros_ec_dev *dev,
const void *dout, int dout_len,
uint8_t **dinp, int din_len)
{
+#ifdef CONFIG_DM_CROS_EC
+ struct dm_cros_ec_ops *ops;
+#endif
int out_bytes, in_bytes;
int rv;
@@ -218,6 +226,10 @@ static int send_command_proto3(struct cros_ec_dev *dev,
if (in_bytes 0)
return in_bytes;
+#ifdef CONFIG_DM_CROS_EC
+ ops = dm_cros_ec_get_ops(dev-dev);
+ rv = ops-packet(dev-dev, out_bytes, in_bytes);
+#else
switch (dev-interface) {
#ifdef CONFIG_CROS_EC_SPI
case CROS_EC_IF_SPI:
@@ -235,6 +247,7 @@ static int send_command_proto3(struct cros_ec_dev *dev,
debug(%s: Unsupported interface\n, __func__);
rv = -1;
}
+#endif
if (rv 0)
return rv;
@@ -246,6 +259,9 @@ static int send_command(struct cros_ec_dev *dev, uint8_t
cmd, int cmd_version,
const void *dout, int dout_len,
uint8_t **dinp, int din_len)
{
+#ifdef CONFIG_DM_CROS_EC
+ struct dm_cros_ec_ops *ops;
+#endif
int ret = -1;
/* Handle protocol version 3 support */
@@ -254,6 +270,11 @@ static int send_command(struct cros_ec_dev *dev, uint8_t
cmd, int cmd_version,
dout, dout_len, dinp, din_len);
}
+#ifdef CONFIG_DM_CROS_EC
+ ops = dm_cros_ec_get_ops(dev-dev);
+ ret = ops-command(dev-dev, cmd, cmd_version,
+ (const uint8_t *)dout, dout_len, dinp, din_len);
+#else
switch (dev-interface) {
#ifdef CONFIG_CROS_EC_SPI
case CROS_EC_IF_SPI:
@@ -280,6 +301,7 @@ static int send_command(struct cros_ec_dev *dev, uint8_t
cmd, int cmd_version,
default:
ret = -1;
}
+#endif
return ret;
}
@@ -990,6 +1012,7 @@ int cros_ec_get_ldo(struct cros_ec_dev *dev, uint8_t
index, uint8_t *state)
return 0;
}
+#ifndef CONFIG_DM_CROS_EC
/**
* Decode EC interface details from the device tree and allocate a suitable
* device.
@@ -1055,11 +1078,61 @@ static int cros_ec_decode_fdt(const void *blob, int
node,
return 0;
}
+#endif
[U-Boot] [PATCH v2 21/30] spi: Use error return value in sf_ops
Adjust spi_flash_probe_slave() to return an error value instead of a
pointer so we get the correct error return.
Have the caller allocate memory for spi_flash to simplify error handling,
and also so that driver model can use its existing allocated memory.
Add a spi.h include in the sf_params file.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/mtd/spi/sf_probe.c | 90 +-
1 file changed, 57 insertions(+), 33 deletions(-)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 4d148d1..212a825 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -9,6 +9,7 @@
*/
#include common.h
+#include errno.h
#include fdtdec.h
#include malloc.h
#include spi.h
@@ -95,15 +96,15 @@ static int spi_flash_set_qeb(struct spi_flash *flash, u8
idcode0)
}
}
-static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
- u8 *idcode)
+static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode,
+struct spi_flash *flash)
{
const struct spi_flash_params *params;
- struct spi_flash *flash;
u8 cmd;
u16 jedec = idcode[1] 8 | idcode[2];
u16 ext_jedec = idcode[3] 8 | idcode[4];
+ /* Validate params from spi_flash_params table */
params = spi_flash_params_table;
for (; params-name != NULL; params++) {
if ((params-jedec 16) == idcode[0]) {
@@ -120,13 +121,7 @@ static struct spi_flash *spi_flash_validate_params(struct
spi_slave *spi,
printf(SF: Unsupported flash IDs: );
printf(manuf %02x, jedec %04x, ext_jedec %04x\n,
idcode[0], jedec, ext_jedec);
- return NULL;
- }
-
- flash = calloc(1, sizeof(*flash));
- if (!flash) {
- debug(SF: Failed to allocate spi_flash\n);
- return NULL;
+ return -EPROTONOSUPPORT;
}
/* Assign spi data */
@@ -227,15 +222,18 @@ static struct spi_flash *spi_flash_validate_params(struct
spi_slave *spi,
#ifdef CONFIG_SPI_FLASH_BAR
u8 curr_bank = 0;
if (flash-size SPI_FLASH_16MB_BOUN) {
+ int ret;
+
flash-bank_read_cmd = (idcode[0] == 0x01) ?
CMD_BANKADDR_BRRD : CMD_EXTNADDR_RDEAR;
flash-bank_write_cmd = (idcode[0] == 0x01) ?
CMD_BANKADDR_BRWR : CMD_EXTNADDR_WREAR;
- if (spi_flash_read_common(flash, flash-bank_read_cmd, 1,
- curr_bank, 1)) {
+ ret = spi_flash_read_common(flash, flash-bank_read_cmd, 1,
+ curr_bank, 1);
+ if (ret) {
debug(SF: fail to read bank addr register\n);
- return NULL;
+ return ret;
}
flash-bank_curr = curr_bank;
} else {
@@ -250,7 +248,7 @@ static struct spi_flash *spi_flash_validate_params(struct
spi_slave *spi,
spi_flash_cmd_write_status(flash, 0);
#endif
- return flash;
+ return 0;
}
#ifdef CONFIG_OF_CONTROL
@@ -309,23 +307,29 @@ static int spi_enable_wp_pin(struct spi_flash *flash)
}
#endif
-static struct spi_flash *spi_flash_probe_slave(struct spi_slave *spi)
+/**
+ * spi_flash_probe_slave() - Probe for a SPI flash device on a bus
+ *
+ * @spi: Bus to probe
+ * @flashp: Pointer to place to put flash info, which may be NULL if the
+ * space should be allocated
+ */
+int spi_flash_probe_slave(struct spi_slave *spi, struct spi_flash *flash)
{
- struct spi_flash *flash = NULL;
u8 idcode[5];
int ret;
/* Setup spi_slave */
if (!spi) {
printf(SF: Failed to set up slave\n);
- return NULL;
+ return -ENODEV;
}
/* Claim spi bus */
ret = spi_claim_bus(spi);
if (ret) {
debug(SF: Failed to claim SPI bus: %d\n, ret);
- goto err_claim_bus;
+ return ret;
}
/* Read the ID codes */
@@ -340,10 +344,10 @@ static struct spi_flash *spi_flash_probe_slave(struct
spi_slave *spi)
print_buffer(0, idcode, 1, sizeof(idcode), 0);
#endif
- /* Validate params from spi_flash_params table */
- flash = spi_flash_validate_params(spi, idcode);
- if (!flash)
+ if (spi_flash_validate_params(spi, idcode, flash)) {
+ ret = -EINVAL;
goto err_read_id;
+ }
/* Set the quad enable bit - only for quad commands */
if ((flash-read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
@@ -351,13 +355,15 @@ static struct spi_flash *spi_flash_probe_slave(struct
spi_slave *spi)
(flash-write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
[U-Boot] [PATCH v2 29/30] dm: sandbox: cros_ec: Move sandbox cros_ec to driver module
Adjust the sandbox cros_ec emulation driver to work with driver model, and
switch over to driver model for sandbox cros_ec.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/misc/cros_ec_sandbox.c | 90 +++---
include/configs/sandbox.h | 1 +
2 files changed, 86 insertions(+), 5 deletions(-)
diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c
index 431cf26..99cc529 100644
--- a/drivers/misc/cros_ec_sandbox.c
+++ b/drivers/misc/cros_ec_sandbox.c
@@ -8,6 +8,7 @@
#include common.h
#include cros_ec.h
+#include dm.h
#include ec_commands.h
#include errno.h
#include hash.h
@@ -85,7 +86,7 @@ struct ec_state {
struct ec_keymatrix_entry *matrix; /* the key matrix info */
uint8_t keyscan[KEYBOARD_COLS];
bool recovery_req;
-} s_state, *state;
+} s_state, *g_state;
/**
* cros_ec_read_state() - read the sandbox EC state from the state file
@@ -138,7 +139,7 @@ static int cros_ec_read_state(const void *blob, int node)
*/
static int cros_ec_write_state(void *blob, int node)
{
- struct ec_state *ec = s_state;
+ struct ec_state *ec = g_state;
/* We are guaranteed enough space to write basic properties */
fdt_setprop_u32(blob, node, current-image, ec-current_image);
@@ -369,7 +370,7 @@ static int process_cmd(struct ec_state *ec,
struct fmap_entry *entry;
int ret, size;
- entry = state-ec_config.region[EC_FLASH_REGION_RW];
+ entry = ec-ec_config.region[EC_FLASH_REGION_RW];
switch (req-cmd) {
case EC_VBOOT_HASH_RECALC:
@@ -426,7 +427,7 @@ static int process_cmd(struct ec_state *ec,
case EC_FLASH_REGION_RO:
case EC_FLASH_REGION_RW:
case EC_FLASH_REGION_WP_RO:
- entry = state-ec_config.region[req-region];
+ entry = ec-ec_config.region[req-region];
resp-offset = entry-offset;
resp-size = entry-length;
len = sizeof(*resp);
@@ -466,16 +467,24 @@ static int process_cmd(struct ec_state *ec,
return len;
}
+#ifdef CONFIG_DM_CROS_EC
+int cros_ec_sandbox_packet(struct udevice *udev, int out_bytes, int in_bytes)
+{
+ struct cros_ec_dev *dev = udev-uclass_priv;
+ struct ec_state *ec = dev_get_priv(dev-dev);
+#else
int cros_ec_sandbox_packet(struct cros_ec_dev *dev, int out_bytes,
int in_bytes)
{
+ struct ec_state *ec = s_state;
+#endif
struct ec_host_request *req_hdr = (struct ec_host_request *)dev-dout;
const void *req_data = req_hdr + 1;
struct ec_host_response *resp_hdr = (struct ec_host_response *)dev-din;
void *resp_data = resp_hdr + 1;
int len;
- len = process_cmd(s_state, req_hdr, req_data, resp_hdr, resp_data);
+ len = process_cmd(ec, req_hdr, req_data, resp_hdr, resp_data);
if (len 0)
return len;
@@ -498,7 +507,11 @@ int cros_ec_sandbox_decode_fdt(struct cros_ec_dev *dev,
const void *blob)
void cros_ec_check_keyboard(struct cros_ec_dev *dev)
{
+#ifdef CONFIG_DM_CROS_EC
+ struct ec_state *ec = dev_get_priv(dev-dev);
+#else
struct ec_state *ec = s_state;
+#endif
ulong start;
printf(Press keys for EC to detect on reset (ESC=recovery)...);
@@ -512,6 +525,52 @@ void cros_ec_check_keyboard(struct cros_ec_dev *dev)
}
}
+#ifdef CONFIG_DM_CROS_EC
+int cros_ec_probe(struct udevice *dev)
+{
+ struct ec_state *ec = dev-priv;
+ struct cros_ec_dev *cdev = dev-uclass_priv;
+ const void *blob = gd-fdt_blob;
+ int node;
+ int err;
+
+ memcpy(ec, s_state, sizeof(*ec));
+ err = cros_ec_decode_ec_flash(blob, dev-of_offset, ec-ec_config);
+ if (err)
+ return err;
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_GOOGLE_CROS_EC_KEYB);
+ if (node 0) {
+ debug(%s: No cros_ec keyboard found\n, __func__);
+ } else if (keyscan_read_fdt_matrix(ec, blob, node)) {
+ debug(%s: Could not read key matrix\n, __func__);
+ return -1;
+ }
+
+ /* If we loaded EC data, check that the length matches */
+ if (ec-flash_data
+ ec-flash_data_len != ec-ec_config.flash.length) {
+ printf(EC data length is %x, expected %x, discarding data\n,
+ ec-flash_data_len, ec-ec_config.flash.length);
+ os_free(ec-flash_data);
+ ec-flash_data = NULL;
+ }
+
+ /* Otherwise allocate the memory */
+ if (!ec-flash_data) {
+ ec-flash_data_len = ec-ec_config.flash.length;
+ ec-flash_data = os_malloc(ec-flash_data_len);
+ if (!ec-flash_data)
+ return -ENOMEM;
+ }
+
+ cdev-dev = dev;
+
[U-Boot] [PATCH v2 27/30] dm: sf: Add tests for SPI flash
Add a simple test for SPI that uses SPI flash. It operates by creating a
SPI flash file and using the 'sf test' command to test that all
operations work correctly.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
test/dm/Makefile | 1 +
test/dm/sf.c | 43 +++
test/dm/test.dts | 17 -
3 files changed, 60 insertions(+), 1 deletion(-)
create mode 100644 test/dm/sf.c
diff --git a/test/dm/Makefile b/test/dm/Makefile
index d1b9c9a..75d3d41 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -19,4 +19,5 @@ obj-$(CONFIG_DM_TEST) += ut.o
ifneq ($(CONFIG_SANDBOX),)
obj-$(CONFIG_DM_GPIO) += gpio.o
obj-$(CONFIG_DM_SPI) += spi.o
+obj-$(CONFIG_DM_SPI_FLASH) += sf.o
endif
diff --git a/test/dm/sf.c b/test/dm/sf.c
new file mode 100644
index 000..57dd134
--- /dev/null
+++ b/test/dm/sf.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include dm.h
+#include fdtdec.h
+#include spi.h
+#include spi_flash.h
+#include asm/state.h
+#include dm/ut.h
+#include dm/test.h
+#include dm/util.h
+
+/* Test that sandbox SPI flash works correctly */
+static int dm_test_spi_flash(struct dm_test_state *dms)
+{
+ /*
+* Create an empty test file and run the SPI flash tests. This is a
+* long way from being a unit test, but it does test SPI device and
+* emulator binding, probing, the SPI flash emulator including
+* device tree decoding, plus the file-based backing store of SPI.
+*
+* More targeted tests could be created to perform the above steps
+* one at a time. This might not increase test coverage much, but
+* it would make bugs easier to find. It's not clear whether the
+* benefit is worth the extra complexity.
+*/
+ ut_asserteq(0, run_command_list(
+ sb save hostfs - spi.bin 0 20;
+ sf probe;
+ sf test 0 1, -1, 0));
+ /*
+* Since we are about to destroy all devices, we must tell sandbox
+* to forget the emulation device
+*/
+ sandbox_sf_unbind_emul(state_get_current(), 0, 0);
+
+ return 0;
+}
+DM_TEST(dm_test_spi_flash, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
diff --git a/test/dm/test.dts b/test/dm/test.dts
index 8489595..1fba792 100644
--- a/test/dm/test.dts
+++ b/test/dm/test.dts
@@ -81,7 +81,7 @@
compatible = google,another-fdt-test;
};
- base-gpios {
+ gpio_a: base-gpios {
compatible = sandbox,gpio;
gpio-bank-name = a;
num-gpios = 20;
@@ -92,4 +92,19 @@
gpio-bank-name = b;
num-gpios = 10;
};
+
+ spi@0 {
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0;
+ compatible = sandbox,spi;
+ cs-gpios = 0, gpio_a 0;
+ spi.bin@0 {
+ reg = 0;
+ compatible = spansion,m25p16, spi-flash;
+ spi-max-frequency = 4000;
+ sandbox,filename = spi.bin;
+ };
+ };
+
};
--
2.1.0.rc2.206.gedb03e5
___
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U-Boot@lists.denx.de
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[U-Boot] [PATCH v2 16/30] dm: spi: Add soft_spi implementation
Add a new implementation of soft_spi that uses device tree to specify the
GPIOs. This will replace soft_spi_legacy for boards which use driver model.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
doc/device-tree-bindings/spi/soft-spi.txt | 32
drivers/spi/Makefile | 1 +
drivers/spi/soft_spi.c| 252 ++
3 files changed, 285 insertions(+)
create mode 100644 doc/device-tree-bindings/spi/soft-spi.txt
create mode 100644 drivers/spi/soft_spi.c
diff --git a/doc/device-tree-bindings/spi/soft-spi.txt
b/doc/device-tree-bindings/spi/soft-spi.txt
new file mode 100644
index 000..e455b6d
--- /dev/null
+++ b/doc/device-tree-bindings/spi/soft-spi.txt
@@ -0,0 +1,32 @@
+Soft SPI
+
+The soft SPI bus implementation allows the use of GPIO pins to simulate a SPI
bus. No SPI host is required for this to work. The down-side is that the
performance will typically be much lower than a real SPI bus.
+
+The soft SPI node requires the following properties:
+
+compatible: u-boot,soft-spi
+soft_spi_cs: GPIO number to use for SPI chip select (output)
+soft_spi_sclk: GPIO number to use for SPI clock (output)
+soft_spi_mosi: GPIO number to use for SPI MOSI line (output)
+soft_spi_miso GPIO number to use for SPI MISO line (input)
+spi-delay-us: Number of microseconds of delay between each CS transition
+
+The GPIOs should be specified as required by the GPIO controller referenced.
+The first cell holds the phandle of the controller and the second cell
+typically holds the GPIO number.
+
+
+Example:
+
+ soft-spi {
+ compatible = u-boot,soft-spi;
+ cs-gpio = gpio 235 0;/* Y43 */
+ sclk-gpio = gpio 225 0; /* Y31 */
+ mosi-gpio = gpio 227 0; /* Y33 */
+ miso-gpio = gpio 224 0; /* Y30 */
+ spi-delay-us = 1;
+ #address-cells = 1;
+ #size-cells = 0;
+ cs@0 {
+ };
+ };
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 5cc8655..e718528 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -9,6 +9,7 @@
ifdef CONFIG_DM_SPI
obj-y += spi-uclass.o
obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o
+obj-$(CONFIG_SOFT_SPI) += soft_spi.o
else
obj-y += spi.o
obj-$(CONFIG_SOFT_SPI) += soft_spi_legacy.o
diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c
new file mode 100644
index 000..5588036
--- /dev/null
+++ b/drivers/spi/soft_spi.c
@@ -0,0 +1,252 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * (C) Copyright 2002
+ * Gerald Van Baren, Custom IDEAS, vanba...@cideas.com.
+ *
+ * Influenced by code from:
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include dm.h
+#include errno.h
+#include fdtdec.h
+#include malloc.h
+#include spi.h
+#include asm/gpio.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct soft_spi_platdata {
+ struct fdt_gpio_state cs;
+ struct fdt_gpio_state sclk;
+ struct fdt_gpio_state mosi;
+ struct fdt_gpio_state miso;
+ int spi_delay_us;
+};
+
+struct soft_spi_priv {
+ unsigned int mode;
+};
+
+static int soft_spi_scl(struct udevice *dev, int bit)
+{
+ struct soft_spi_platdata *plat = dev-platdata;
+ struct soft_spi_priv *priv = dev_get_priv(dev);
+
+ gpio_set_value(plat-sclk.gpio, priv-mode SPI_CPOL ? bit : !bit);
+
+ return 0;
+}
+
+static int soft_spi_sda(struct udevice *dev, int bit)
+{
+ struct soft_spi_platdata *plat = dev-platdata;
+
+ gpio_set_value(plat-mosi.gpio, bit);
+
+ return 0;
+}
+
+static int soft_spi_cs_activate(struct udevice *dev)
+{
+ struct soft_spi_platdata *plat = dev-platdata;
+ struct soft_spi_priv *priv = dev_get_priv(dev);
+
+ gpio_set_value(plat-cs.gpio, !(priv-mode SPI_CS_HIGH));
+ gpio_set_value(plat-sclk.gpio, priv-mode SPI_CPOL);
+ gpio_set_value(plat-cs.gpio, priv-mode SPI_CS_HIGH);
+
+ return 0;
+}
+
+static int soft_spi_cs_deactivate(struct udevice *dev)
+{
+ struct soft_spi_platdata *plat = dev-platdata;
+ struct soft_spi_priv *priv = dev_get_priv(dev);
+
+ gpio_set_value(plat-cs.gpio, !(priv-mode SPI_CS_HIGH));
+
+ return 0;
+}
+
+static int soft_spi_claim_bus(struct udevice *dev)
+{
+ /*
+* Make sure the SPI clock is in idle state as defined for
+* this slave.
+*/
+ return soft_spi_scl(dev, 0);
+}
+
+static int soft_spi_release_bus(struct udevice *dev)
+{
+ /* Nothing to do */
+ return 0;
+}
+
+/*---
+ * SPI transfer
+ *
+ * This writes bitlen bits out the SPI MOSI port and simultaneously clocks
+ * bitlen bits in the SPI MISO port. That's just the way SPI works.
+ *
+ * The source of the outgoing bits is the dout parameter and the
+ * destination of the
[U-Boot] [PATCH v2 25/30] dm: exynos: config: Use driver model for SPI flash
Use driver model for exynos5 board SPI flash. Signed-off-by: Simon Glass s...@chromium.org --- Changes in v2: None include/configs/exynos-common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index 0ec2ed7..47136b3 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -22,6 +22,7 @@ #define CONFIG_DM_GPIO #define CONFIG_DM_SERIAL #define CONFIG_DM_SPI +#define CONFIG_DM_SPI_FLASH #define CONFIG_ARCH_CPU_INIT #define CONFIG_DISPLAY_CPUINFO -- 2.1.0.rc2.206.gedb03e5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 14/30] dm: spi: Rename soft_spi.c to soft_spi_legacy.c
Reserve the 'normal' name for use by driver model, and rename the old
driver so that it is clear that it is for 'legacy' drivers only.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/spi/Makefile | 2 +-
drivers/spi/{soft_spi.c = soft_spi_legacy.c} | 0
2 files changed, 1 insertion(+), 1 deletion(-)
rename drivers/spi/{soft_spi.c = soft_spi_legacy.c} (100%)
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index a1de028..5cc8655 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -11,6 +11,7 @@ obj-y += spi-uclass.o
obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o
else
obj-y += spi.o
+obj-$(CONFIG_SOFT_SPI) += soft_spi_legacy.o
endif
obj-$(CONFIG_EP93XX_SPI) += ep93xx_spi.o
@@ -35,7 +36,6 @@ obj-$(CONFIG_MXS_SPI) += mxs_spi.o
obj-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
-obj-$(CONFIG_SOFT_SPI) += soft_spi.o
obj-$(CONFIG_SH_SPI) += sh_spi.o
obj-$(CONFIG_SH_QSPI) += sh_qspi.o
obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi_legacy.c
similarity index 100%
rename from drivers/spi/soft_spi.c
rename to drivers/spi/soft_spi_legacy.c
--
2.1.0.rc2.206.gedb03e5
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[U-Boot] [PATCH v2 22/30] dm: sf: Add a uclass for SPI flash
Add a driver model uclass for SPI flash which supports the common
operations (read, write, erase). Since we must keep support for the
non-dm interface, some modification of the spi_flash header is required.
CONFIG_DM_SPI_FLASH is used to enable driver model for SPI flash.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/mtd/spi/Makefile| 7 -
drivers/mtd/spi/sf-uclass.c | 63
include/dm/uclass-id.h | 1 +
include/spi_flash.h | 70 +
4 files changed, 140 insertions(+), 1 deletion(-)
create mode 100644 drivers/mtd/spi/sf-uclass.c
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 9e18fb4..15789a0 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -5,13 +5,18 @@
# SPDX-License-Identifier: GPL-2.0+
#
+obj-$(CONFIG_DM_SPI_FLASH) += sf-uclass.o
+
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_SPI_LOAD) += spi_spl_load.o
obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o
endif
+#ifndef CONFIG_DM_SPI
+obj-$(CONFIG_SPI_FLASH) += sf_probe.o
+#endif
obj-$(CONFIG_CMD_SF) += sf.o
-obj-$(CONFIG_SPI_FLASH) += sf_params.o sf_probe.o sf_ops.o
+obj-$(CONFIG_SPI_FLASH) += sf_ops.o sf_params.o
obj-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.o
obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
obj-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o
diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c
new file mode 100644
index 000..376d815
--- /dev/null
+++ b/drivers/mtd/spi/sf-uclass.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include dm.h
+#include spi.h
+#include spi_flash.h
+#include dm/device-internal.h
+#include sf_internal.h
+
+/*
+ * TODO(s...@chromium.org): This is an old-style function. We should remove
+ * it when all SPI flash drivers use dm
+ */
+struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode)
+{
+ struct udevice *dev;
+
+ if (spi_flash_probe_bus_cs(bus, cs, max_hz, spi_mode, dev))
+ return NULL;
+
+ return dev-uclass_priv;
+}
+
+void spi_flash_free(struct spi_flash *flash)
+{
+ spi_flash_remove(flash-spi-dev);
+}
+
+int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode,
+ struct udevice **devp)
+{
+ struct spi_slave *slave;
+ struct udevice *bus;
+ char name[20], *str;
+ int ret;
+
+ snprintf(name, sizeof(name), %d:%d, busnum, cs);
+ str = strdup(name);
+ ret = spi_get_bus_and_cs(busnum, cs, max_hz, spi_mode,
+ spi_flash_std, str, bus, slave);
+ if (ret)
+ return ret;
+
+ *devp = slave-dev;
+ return 0;
+}
+
+int spi_flash_remove(struct udevice *dev)
+{
+ return device_remove(dev);
+}
+
+UCLASS_DRIVER(spi_flash) = {
+ .id = UCLASS_SPI_FLASH,
+ .name = spi_flash,
+ .per_device_auto_alloc_size = sizeof(struct spi_flash),
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index dce405e..02aee45 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -24,6 +24,7 @@ enum uclass_id {
UCLASS_GPIO,/* Bank of general-purpose I/O pins */
UCLASS_SERIAL, /* Serial UART */
UCLASS_SPI, /* SPI bus */
+ UCLASS_SPI_FLASH, /* SPI flash */
UCLASS_COUNT,
UCLASS_INVALID = -1,
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 094a512..72903f5 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -15,6 +15,7 @@
#ifndef _SPI_FLASH_H_
#define _SPI_FLASH_H_
+#include dm.h/* Because we dereference struct udevice here */
#include linux/types.h
struct spi_slave;
@@ -48,7 +49,12 @@ struct spi_slave;
* return 0 - Success, 1 - Failure
*/
struct spi_flash {
+#ifdef CONFIG_DM_SPI_FLASH
struct spi_slave *spi;
+ struct udevice *dev;
+#else
+ struct spi_slave *spi;
+#endif
const char *name;
u8 dual_flash;
u8 shift;
@@ -69,12 +75,75 @@ struct spi_flash {
u8 dummy_byte;
void *memory_map;
+#ifndef CONFIG_DM_SPI_FLASH
+ /*
+* These are not strictly needed for driver model, but keep them here
+* whilt the transition is in progress.
+*
+* Normally each driver would provide its own operations, but for
+* SPI flash most chips use the same algorithms. One approach is
+* to create a 'common' SPI flash device which knows how to talk
+* to most devices, and then allow other drivers to be used instead
+* if requird, perhaps with a way of scanning through the list to
+* find the driver that matches the device.
+
[U-Boot] [PATCH v2 26/30] dm: spi: Add tests
These tests use SPI flash (and the sandbox emulation) to operate.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Create a 'spi.bin' file for the SPI tests
test/dm/Makefile | 1 +
test/dm/spi.c | 47 +++
test/dm/test-dm.sh | 2 ++
3 files changed, 50 insertions(+)
create mode 100644 test/dm/spi.c
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 5c2415e..d1b9c9a 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -18,4 +18,5 @@ obj-$(CONFIG_DM_TEST) += core.o
obj-$(CONFIG_DM_TEST) += ut.o
ifneq ($(CONFIG_SANDBOX),)
obj-$(CONFIG_DM_GPIO) += gpio.o
+obj-$(CONFIG_DM_SPI) += spi.o
endif
diff --git a/test/dm/spi.c b/test/dm/spi.c
new file mode 100644
index 000..45aabeb
--- /dev/null
+++ b/test/dm/spi.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include dm.h
+#include fdtdec.h
+#include spi.h
+#include spi_flash.h
+#include dm/test.h
+#include dm/ut.h
+#include dm/util.h
+#include asm/state.h
+
+/* Test that sandbox SPI works correctly */
+static int dm_test_spi(struct dm_test_state *dms)
+{
+ struct spi_slave *slave;
+ struct udevice *dev;
+ const int busnum = 0, cs = 0, mode = 0;
+ const char dout[5] = {0x9f};
+ unsigned char din[5];
+
+ ut_assertok(spi_get_bus_and_cs(busnum, cs, 100, mode, NULL, 0,
+ dev, slave));
+ ut_assertok(spi_claim_bus(slave));
+ ut_assertok(spi_xfer(slave, 40, dout, din,
+SPI_XFER_BEGIN | SPI_XFER_END));
+ ut_asserteq(0xff, din[0]);
+ ut_asserteq(0x20, din[1]);
+ ut_asserteq(0x20, din[2]);
+ ut_asserteq(0x15, din[3]);
+ spi_release_bus(slave);
+
+ /*
+* Since we are about to destroy all devices, we must tell sandbox
+* to forget the emulation device
+*/
+#ifdef CONFIG_DM_SPI_FLASH
+ sandbox_sf_unbind_emul(state_get_current(), busnum, cs);
+#endif
+
+ return 0;
+}
+DM_TEST(dm_test_spi, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
diff --git a/test/dm/test-dm.sh b/test/dm/test-dm.sh
index ef5aca5..bb99677 100755
--- a/test/dm/test-dm.sh
+++ b/test/dm/test-dm.sh
@@ -4,4 +4,6 @@ NUM_CPUS=$(cat /proc/cpuinfo |grep -c processor)
dtc -I dts -O dtb test/dm/test.dts -o test/dm/test.dtb
make O=sandbox sandbox_config
make O=sandbox -s -j${NUM_CPUS}
+dd if=/dev/zero of=spi.bin bs=1M count=2
./sandbox/u-boot -d test/dm/test.dtb -c dm test
+rm spi.bin
--
2.1.0.rc2.206.gedb03e5
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 23/30] dm: Convert spi_flash_probe() and 'sf probe' to use driver model
We want the SPI flash probing feature to operate as a standard driver.
Add a driver for the basic probing feature used by most boards. This
will be activated by device_probe() as with any other driver.
The 'sf probe' command currently keeps track of the SPI slave that it
last used. This doesn't work with driver model, since some other driver
or system may have probed the device and have access to it too. On the
other hand, if we try to probe a device twice the second probe is a nop
with driver model.
Fix this by searching for the matching device, removing it, and then
probing it again. This should work as expected regardless of other device
activity.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
common/cmd_sf.c| 23
drivers/mtd/spi/sf_probe.c | 65 --
2 files changed, 86 insertions(+), 2 deletions(-)
diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index 1bb41d3..b536b62 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -8,11 +8,13 @@
#include common.h
#include div64.h
+#include dm.h
#include malloc.h
#include spi.h
#include spi_flash.h
#include asm/io.h
+#include dm/device-internal.h
#ifndef CONFIG_SF_DEFAULT_SPEED
# define CONFIG_SF_DEFAULT_SPEED 100
@@ -94,7 +96,12 @@ static int do_spi_flash_probe(int argc, char * const argv[])
unsigned int speed = CONFIG_SF_DEFAULT_SPEED;
unsigned int mode = CONFIG_SF_DEFAULT_MODE;
char *endp;
+#ifdef CONFIG_DM_SPI_FLASH
+ struct udevice *new, *bus_dev;
+ int ret;
+#else
struct spi_flash *new;
+#endif
if (argc = 2) {
cs = simple_strtoul(argv[1], endp, 0);
@@ -122,6 +129,21 @@ static int do_spi_flash_probe(int argc, char * const
argv[])
return -1;
}
+#ifdef CONFIG_DM_SPI_FLASH
+ /* Remove the old device, otherwise probe will just be a nop */
+ ret = spi_find_bus_and_cs(bus, cs, bus_dev, new);
+ if (!ret)
+ device_remove(new);
+ flash = NULL;
+ ret = spi_flash_probe_bus_cs(bus, cs, speed, mode, new);
+ if (ret) {
+ printf(Failed to initialize SPI flash at %u:%u (error %d)\n,
+ bus, cs, ret);
+ return 1;
+ }
+
+ flash = new-uclass_priv;
+#else
new = spi_flash_probe(bus, cs, speed, mode);
if (!new) {
printf(Failed to initialize SPI flash at %u:%u\n, bus, cs);
@@ -131,6 +153,7 @@ static int do_spi_flash_probe(int argc, char * const argv[])
if (flash)
spi_flash_free(flash);
flash = new;
+#endif
return 0;
}
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 212a825..9487fc1 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -9,6 +9,7 @@
*/
#include common.h
+#include dm.h
#include errno.h
#include fdtdec.h
#include malloc.h
@@ -131,13 +132,15 @@ static int spi_flash_validate_params(struct spi_slave
*spi, u8 *idcode,
flash-dual_flash = flash-spi-option;
/* Assign spi_flash ops */
+#ifndef CONFIG_DM_SPI_FLASH
flash-write = spi_flash_cmd_write_ops;
-#ifdef CONFIG_SPI_FLASH_SST
+#if defined(CONFIG_SPI_FLASH_SST)
if (params-flags SST_WP)
flash-write = sst_write_wp;
#endif
flash-erase = spi_flash_cmd_erase_ops;
flash-read = spi_flash_cmd_read_ops;
+#endif
/* Compute the flash size */
flash-shift = (flash-dual_flash SF_DUAL_PARALLEL_FLASH) ? 1 : 0;
@@ -398,7 +401,8 @@ err_read_id:
return ret;
}
-static struct spi_flash *spi_flash_probe_tail(struct spi_slave *bus)
+#ifndef CONFIG_DM_SPI_FLASH
+struct spi_flash *spi_flash_probe_tail(struct spi_slave *bus)
{
struct spi_flash *flash;
@@ -443,3 +447,60 @@ void spi_flash_free(struct spi_flash *flash)
spi_free_slave(flash-spi);
free(flash);
}
+
+#else /* defined CONFIG_DM_SPI_FLASH */
+
+static int spi_flash_std_read(struct udevice *dev, u32 offset, size_t len,
+ void *buf)
+{
+ struct spi_flash *flash = dev-uclass_priv;
+
+ return spi_flash_cmd_read_ops(flash, offset, len, buf);
+}
+
+int spi_flash_std_write(struct udevice *dev, u32 offset, size_t len,
+ const void *buf)
+{
+ struct spi_flash *flash = dev-uclass_priv;
+
+ return spi_flash_cmd_write_ops(flash, offset, len, buf);
+}
+
+int spi_flash_std_erase(struct udevice *dev, u32 offset, size_t len)
+{
+ struct spi_flash *flash = dev-uclass_priv;
+
+ return spi_flash_cmd_erase_ops(flash, offset, len);
+}
+
+int spi_flash_std_probe(struct udevice *dev)
+{
+ struct spi_slave *slave = dev_get_parentdata(dev);
+ struct spi_flash *flash;
+
+ flash = dev-uclass_priv;
+ flash-dev = dev;
+ return spi_flash_probe_slave(slave, flash);
+}
+
+static const struct dm_spi_flash_ops
[U-Boot] [PATCH v2 24/30] dm: sf: sandbox: Convert SPI flash driver to driver model
Convert sandbox's spi flash emulation driver to use driver model.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/sandbox/include/asm/spi.h | 13 --
arch/sandbox/include/asm/state.h | 1 -
drivers/mtd/spi/sandbox.c| 326 +--
include/configs/sandbox.h| 1 +
4 files changed, 279 insertions(+), 62 deletions(-)
diff --git a/arch/sandbox/include/asm/spi.h b/arch/sandbox/include/asm/spi.h
index 49b4a0f..9985e3c 100644
--- a/arch/sandbox/include/asm/spi.h
+++ b/arch/sandbox/include/asm/spi.h
@@ -33,19 +33,6 @@ struct sandbox_spi_emu_ops {
};
/*
- * There are times when the data lines are allowed to tristate. What
- * is actually sensed on the line depends on the hardware. It could
- * always be 0xFF/0x00 (if there are pull ups/downs), or things could
- * float and so we'd get garbage back. This func encapsulates that
- * scenario so we can worry about the details here.
- */
-static inline void sandbox_spi_tristate(u8 *buf, uint len)
-{
- /* XXX: make this into a user config option ? */
- memset(buf, 0xff, len);
-}
-
-/*
* Extract the bus/cs from the spi spec and return the start of the spi
* client spec. If the bus/cs are invalid for the current config, then
* it returns NULL.
diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h
index 4e0981a..32d55cc 100644
--- a/arch/sandbox/include/asm/state.h
+++ b/arch/sandbox/include/asm/state.h
@@ -42,7 +42,6 @@ enum state_terminal_raw {
struct sandbox_spi_info {
const char *spec;
- const struct sandbox_spi_emu_ops *ops;
struct udevice *emul;
};
diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
index 98e0a34..7d572fd 100644
--- a/drivers/mtd/spi/sandbox.c
+++ b/drivers/mtd/spi/sandbox.c
@@ -9,6 +9,7 @@
*/
#include common.h
+#include dm.h
#include malloc.h
#include spi.h
#include os.h
@@ -19,6 +20,11 @@
#include asm/getopt.h
#include asm/spi.h
#include asm/state.h
+#include dm/device-internal.h
+#include dm/lists.h
+#include dm/uclass-internal.h
+
+DECLARE_GLOBAL_DATA_PTR;
/*
* The different states that our SPI flash transitions between.
@@ -34,12 +40,14 @@ enum sandbox_sf_state {
SF_ERASE, /* erase the flash */
SF_READ_STATUS, /* read the flash's status register */
SF_READ_STATUS1, /* read the flash's status register upper 8 bits*/
+ SF_WRITE_STATUS, /* write the flash's status register */
};
static const char *sandbox_sf_state_name(enum sandbox_sf_state state)
{
static const char * const states[] = {
CMD, ID, ADDR, READ, WRITE, ERASE, READ_STATUS,
+ READ_STATUS1, WRITE_STATUS,
};
return states[state];
}
@@ -84,71 +92,109 @@ struct sandbox_spi_flash {
int fd;
};
-static int sandbox_sf_setup(void **priv, const char *spec)
+struct sandbox_spi_flash_plat_data {
+ const char *filename;
+ const char *device_name;
+ int bus;
+ int cs;
+};
+
+/**
+ * This is a very strange probe function. If it has platform data (which may
+ * have come from the device tree) then this function gets the filename and
+ * device type from there. Failing that it looks at the command line
+ * parameter.
+ */
+static int sandbox_sf_probe(struct udevice *dev)
{
/* spec = idcode:file */
- struct sandbox_spi_flash *sbsf;
+ struct sandbox_spi_flash *sbsf = dev_get_priv(dev);
const char *file;
size_t len, idname_len;
const struct spi_flash_params *data;
-
- file = strchr(spec, ':');
- if (!file) {
- printf(sandbox_sf: unable to parse file\n);
- goto error;
+ struct sandbox_spi_flash_plat_data *pdata = dev_get_platdata(dev);
+ const char *spec = NULL;
+ int ret = 0;
+
+ if (!pdata-filename) {
+ struct sandbox_state *state = state_get_current();
+ struct udevice *bus = dev-parent;
+ int seq;
+
+ assert(bus-seq != -1);
+ seq = uclass_resolve_seq(dev);
+ if (seq 0)
+ return seq;
+ if (bus-seq CONFIG_SANDBOX_SPI_MAX_BUS
+ dev-req_seq CONFIG_SANDBOX_SPI_MAX_CS)
+ spec = state-spi[bus-seq][seq].spec;
+ if (!spec)
+ return -ENOENT;
+
+ file = strchr(spec, ':');
+ if (!file) {
+ printf(sandbox_sf: unable to parse file\n);
+ ret = -EINVAL;
+ goto error;
+ }
+ idname_len = file - spec;
+ pdata-filename = file + 1;
+ pdata-device_name = spec;
+ ++file;
+ } else {
+ spec = strchr(pdata-device_name, ',');
+ if (spec)
+ spec++;
+ else
+ spec =
[U-Boot] [PATCH v2 13/30] dm: spi: Add documentation on how to convert over SPI drivers
This README is intended to help maintainers move their SPI drivers over to
driver model. It works through the required steps with an example.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Update for changes to exynos driver
- Fix typos reported by Jagannadha Sutradharudu Teki
doc/driver-model/spi-howto.txt | 583 +
1 file changed, 583 insertions(+)
create mode 100644 doc/driver-model/spi-howto.txt
diff --git a/doc/driver-model/spi-howto.txt b/doc/driver-model/spi-howto.txt
new file mode 100644
index 000..5ad4ee7
--- /dev/null
+++ b/doc/driver-model/spi-howto.txt
@@ -0,0 +1,583 @@
+How to port a SPI driver to driver model
+
+
+Here is a rough step-by-step guide. It is based around converting the
+exynos SPI driver to driver model (DM) and the example code is based
+around U-Boot v2014.04 (commit dda0dbf).
+
+It is quite long since it includes actual code examples.
+
+Before driver model, SPI drivers have their own private structure which
+contains 'struct spi_slave'. With driver model, 'struct spi_slave' still
+exists, but now it is 'per-child data' for the SPI bus. Each child of the
+SPI bus is a SPI slave. The information that was stored in the
+driver-specific slave structure can now be port in private data for the
+SPI bus.
+
+For example, struct tegra_spi_slave looks like this:
+
+struct tegra_spi_slave {
+ struct spi_slave slave;
+ struct tegra_spi_ctrl *ctrl;
+};
+
+In this case 'slave' will be in per-child data, and 'ctrl' will be in the
+SPI's buses private data.
+
+
+0. How long does this take?
+
+start 14:00
+to 15:00
+start 16:30
+
+
+1. Enable driver mode for SPI and SPI flash
+
+Add these to your board config:
+
+#define CONFIG_DM_SPI
+#define CONFIG_DM_SPI_FLASH
+
+
+2. Add the skeleton
+
+Put this code at the bottom of your existing driver file:
+
+struct spi_slave *spi_setup_slave(unsigned int busnum, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ return NULL;
+}
+
+struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node,
+ int spi_node)
+{
+ return NULL;
+}
+
+static int exynos_spi_ofdata_to_platdata(struct udevice *dev)
+{
+ return -ENODEV;
+}
+
+static int exynos_spi_probe(struct udevice *dev)
+{
+ return -ENODEV;
+}
+
+static int exynos_spi_remove(struct udevice *dev)
+{
+ return -ENODEV;
+}
+
+static int exynos_spi_claim_bus(struct udevice *dev)
+{
+
+ return -ENODEV;
+}
+
+static int exynos_spi_release_bus(struct udevice *dev)
+{
+
+ return -ENODEV;
+}
+
+static int exynos_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+
+ return -ENODEV;
+}
+
+static int exynos_spi_set_speed(struct udevice *dev, uint speed)
+{
+ return -ENODEV;
+}
+
+static int exynos_spi_set_mode(struct udevice *dev, uint mode)
+{
+ return -ENODEV;
+}
+
+static const struct dm_spi_ops exynos_spi_ops = {
+ .claim_bus = exynos_spi_claim_bus,
+ .release_bus= exynos_spi_release_bus,
+ .xfer = exynos_spi_xfer,
+ .set_speed = exynos_spi_set_speed,
+ .set_mode = exynos_spi_set_mode,
+};
+
+static const struct udevice_id exynos_spi_ids[] = {
+ { .compatible = samsung,exynos-spi },
+ { }
+};
+
+U_BOOT_DRIVER(exynos_spi) = {
+ .name = exynos_spi,
+ .id = UCLASS_SPI,
+ .of_match = exynos_spi_ids,
+ .ops= exynos_spi_ops,
+ .ofdata_to_platdata = exynos_spi_ofdata_to_platdata,
+ .probe = exynos_spi_probe,
+ .remove = exynos_spi_remove,
+};
+
+
+3. Replace 'exynos' in the above code with your driver name
+
+
+4. #ifdef out all of the code in your driver except for the above
+
+This will allow you to get it building, which means you can work
+incrementally. Since all the methods return an error initially, there is
+less chance that you will accidentally leave something in.
+
+Also, even though your conversion is basically a rewrite, it might help
+reviewers if you leave functions in the same place in the file,
+particularly for large drivers.
+
+
+5. Add some includes
+
+Add these includes to your driver:
+
+#include dm.h
+#include errno.h
+
+
+6. Build
+
+At this point you should be able to build U-Boot for your board with the
+empty SPI driver. You still have empty methods in your driver, but we will
+write these one by one.
+
+If you have spi_init() functions or the like that are called from your
+board then the build will fail. Remove these calls and make a note of the
+init that needs to be done.
+
+
+7. Set up your platform data structure
+
+This will hold the information your driver to operate, like its hardware
+address or maximum frequency.
+
+You may already have a struct like this, or you may need to create one
+from some of the #defines or global
[U-Boot] [PATCH v2 12/30] dm: sandbox: spi: Move to driver model
Adjust the sandbox SPI driver to support driver model and move sandbox over
to driver model for SPI.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Correct sandbox's xfer() method signature
- Use 'bus' instead of 'dev' to make the API clearer
arch/sandbox/include/asm/state.h | 1 +
drivers/spi/sandbox_spi.c| 198 ++-
include/configs/sandbox.h| 3 +-
3 files changed, 74 insertions(+), 128 deletions(-)
diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h
index d17a82e..4e0981a 100644
--- a/arch/sandbox/include/asm/state.h
+++ b/arch/sandbox/include/asm/state.h
@@ -43,6 +43,7 @@ enum state_terminal_raw {
struct sandbox_spi_info {
const char *spec;
const struct sandbox_spi_emu_ops *ops;
+ struct udevice *emul;
};
/* The complete state of the test system */
diff --git a/drivers/spi/sandbox_spi.c b/drivers/spi/sandbox_spi.c
index 12e9bda..79248ff 100644
--- a/drivers/spi/sandbox_spi.c
+++ b/drivers/spi/sandbox_spi.c
@@ -9,26 +9,23 @@
*/
#include common.h
+#include dm.h
#include malloc.h
#include spi.h
+#include spi_flash.h
#include os.h
#include asm/errno.h
#include asm/spi.h
#include asm/state.h
+#include dm/device-internal.h
+
+DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SPI_IDLE_VAL
# define CONFIG_SPI_IDLE_VAL 0xFF
#endif
-struct sandbox_spi_slave {
- struct spi_slave slave;
- const struct sandbox_spi_emu_ops *ops;
- void *priv;
-};
-
-#define to_sandbox_spi_slave(s) container_of(s, struct sandbox_spi_slave,
slave)
-
const char *sandbox_spi_parse_spec(const char *arg, unsigned long *bus,
unsigned long *cs)
{
@@ -45,120 +42,52 @@ const char *sandbox_spi_parse_spec(const char *arg,
unsigned long *bus,
return endp + 1;
}
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return bus CONFIG_SANDBOX_SPI_MAX_BUS
- cs CONFIG_SANDBOX_SPI_MAX_CS;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- struct sandbox_spi_slave *sss = to_sandbox_spi_slave(slave);
-
- debug(sandbox_spi: activating CS\n);
- if (sss-ops-cs_activate)
- sss-ops-cs_activate(sss-priv);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- struct sandbox_spi_slave *sss = to_sandbox_spi_slave(slave);
-
- debug(sandbox_spi: deactivating CS\n);
- if (sss-ops-cs_deactivate)
- sss-ops-cs_deactivate(sss-priv);
-}
-
-void spi_init(void)
-{
-}
-
-void spi_set_speed(struct spi_slave *slave, uint hz)
+__weak int sandbox_spi_get_emul(struct sandbox_state *state,
+ struct udevice *bus, struct udevice *slave,
+ struct udevice **emulp)
{
+ return -ENOENT;
}
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
+static int sandbox_spi_xfer(struct udevice *slave, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
{
- struct sandbox_spi_slave *sss;
+ struct udevice *bus = slave-parent;
struct sandbox_state *state = state_get_current();
- const char *spec;
-
- if (!spi_cs_is_valid(bus, cs)) {
- debug(sandbox_spi: Invalid SPI bus/cs\n);
- return NULL;
- }
-
- sss = spi_alloc_slave(struct sandbox_spi_slave, bus, cs);
- if (!sss) {
- debug(sandbox_spi: Out of memory\n);
- return NULL;
- }
-
- spec = state-spi[bus][cs].spec;
- sss-ops = state-spi[bus][cs].ops;
- if (!spec || !sss-ops || sss-ops-setup(sss-priv, spec)) {
- free(sss);
- printf(sandbox_spi: unable to locate a slave client\n);
- return NULL;
- }
-
- return sss-slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct sandbox_spi_slave *sss = to_sandbox_spi_slave(slave);
-
- debug(sandbox_spi: releasing slave\n);
-
- if (sss-ops-free)
- sss-ops-free(sss-priv);
-
- free(sss);
-}
-
-static int spi_bus_claim_cnt[CONFIG_SANDBOX_SPI_MAX_BUS];
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- if (spi_bus_claim_cnt[slave-bus]++) {
- printf(sandbox_spi: error: bus already claimed: %d!\n,
- spi_bus_claim_cnt[slave-bus]);
- }
-
- return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
- if (--spi_bus_claim_cnt[slave-bus]) {
- printf(sandbox_spi: error: bus freed too often: %d!\n,
- spi_bus_claim_cnt[slave-bus]);
- }
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
-{
- struct sandbox_spi_slave *sss = to_sandbox_spi_slave(slave);
+ struct dm_spi_emul_ops *ops;
+ struct udevice
[U-Boot] [PATCH v2 15/30] dm: spi: Remove SPI_INIT feature
This feature provides for init of a single SPI port for the soft SPI
feature. It is not really compatible with driver model since it assumes a
single SPI port. Also, inserting SPI init into the driver by means of
a #define is not very nice.
This feature is not used by any active boards, so let's remove it.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/spi/soft_spi_legacy.c | 5 -
include/configs/s5pc210_universal.h | 1 -
include/configs/sacsng.h| 1 -
include/configs/zipitz2.h | 1 -
4 files changed, 8 deletions(-)
diff --git a/drivers/spi/soft_spi_legacy.c b/drivers/spi/soft_spi_legacy.c
index c969be3..941daa7 100644
--- a/drivers/spi/soft_spi_legacy.c
+++ b/drivers/spi/soft_spi_legacy.c
@@ -42,11 +42,6 @@ static inline struct soft_spi_slave *to_soft_spi(struct
spi_slave *slave)
*/
void spi_init (void)
{
-#ifdef SPI_INIT
- volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-
- SPI_INIT;
-#endif
}
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
diff --git a/include/configs/s5pc210_universal.h
b/include/configs/s5pc210_universal.h
index cd4cdfe..b729bfc 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -196,7 +196,6 @@
#define CONFIG_SOFT_SPI_GPIO_CS EXYNOS4_GPIO_Y43
#define SPI_DELAY udelay(1)
-#undef SPI_INIT
#define SPI_SCL(bit) universal_spi_scl(bit)
#define SPI_SDA(bit) universal_spi_sda(bit)
#define SPI_READ universal_spi_read()
diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h
index b5064ab..2dee315 100644
--- a/include/configs/sacsng.h
+++ b/include/configs/sacsng.h
@@ -259,7 +259,6 @@
#define I2C_MOSI 0x4000 /* PD 17: Master Out, Slave In */
#define I2C_MISO 0x8000 /* PD 16: Master In, Slave Out */
-#undef SPI_INIT /* no port initialization needed */
#define SPI_READ((immr-im_ioport.iop_pdatd I2C_MISO) != 0)
#define SPI_SDA(bit)do { \
if(bit) immr-im_ioport.iop_pdatd |= I2C_MOSI; \
diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
index 41a7c99..fe331bc 100644
--- a/include/configs/zipitz2.h
+++ b/include/configs/zipitz2.h
@@ -99,7 +99,6 @@
#defineCONFIG_VIDEO_BMP_GZIP
#defineCONFIG_VIDEO_BMP_RLE8
#defineCONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 20)
-#undef SPI_INIT
#defineSPI_DELAY udelay(10)
#defineSPI_SDA(val)zipitz2_spi_sda(val)
--
2.1.0.rc2.206.gedb03e5
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[U-Boot] [PATCH v2 30/30] dm: exynos: cros_ec: Move cros_ec_spi to driver model
Adjust this driver to use driver model and move smdk5420 boards over to
use it.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/misc/cros_ec_spi.c | 68 +++--
include/configs/peach-pit.h | 1 +
2 files changed, 60 insertions(+), 9 deletions(-)
diff --git a/drivers/misc/cros_ec_spi.c b/drivers/misc/cros_ec_spi.c
index 015333f..89616ce 100644
--- a/drivers/misc/cros_ec_spi.c
+++ b/drivers/misc/cros_ec_spi.c
@@ -15,23 +15,34 @@
#include common.h
#include cros_ec.h
+#include dm.h
+#include errno.h
#include spi.h
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_DM_CROS_EC
+int cros_ec_spi_packet(struct udevice *udev, int out_bytes, int in_bytes)
+{
+ struct cros_ec_dev *dev = udev-uclass_priv;
+#else
int cros_ec_spi_packet(struct cros_ec_dev *dev, int out_bytes, int in_bytes)
{
+#endif
+ struct spi_slave *slave = dev_get_parentdata(dev-dev);
int rv;
/* Do the transfer */
- if (spi_claim_bus(dev-spi)) {
+ if (spi_claim_bus(slave)) {
debug(%s: Cannot claim SPI bus\n, __func__);
return -1;
}
- rv = spi_xfer(dev-spi, max(out_bytes, in_bytes) * 8,
+ rv = spi_xfer(slave, max(out_bytes, in_bytes) * 8,
dev-dout, dev-din,
SPI_XFER_BEGIN | SPI_XFER_END);
- spi_release_bus(dev-spi);
+ spi_release_bus(slave);
if (rv) {
debug(%s: Cannot complete SPI transfer\n, __func__);
@@ -56,10 +67,19 @@ int cros_ec_spi_packet(struct cros_ec_dev *dev, int
out_bytes, int in_bytes)
* @param din_len Maximum size of response in bytes
* @return number of bytes in response, or -1 on error
*/
+#ifdef CONFIG_DM_CROS_EC
+int cros_ec_spi_command(struct udevice *udev, uint8_t cmd, int cmd_version,
+const uint8_t *dout, int dout_len,
+uint8_t **dinp, int din_len)
+{
+ struct cros_ec_dev *dev = udev-uclass_priv;
+#else
int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
const uint8_t *dout, int dout_len,
uint8_t **dinp, int din_len)
{
+#endif
+ struct spi_slave *slave = dev_get_parentdata(dev-dev);
int in_bytes = din_len + 4; /* status, length, checksum, trailer */
uint8_t *out;
uint8_t *p;
@@ -92,7 +112,7 @@ int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t
cmd, int cmd_version,
*/
memset(dev-din, '\0', in_bytes);
- if (spi_claim_bus(dev-spi)) {
+ if (spi_claim_bus(slave)) {
debug(%s: Cannot claim SPI bus\n, __func__);
return -1;
}
@@ -113,10 +133,10 @@ int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t
cmd, int cmd_version,
p = dev-din + sizeof(int64_t) - 2;
len = dout_len + 4;
cros_ec_dump_data(out, cmd, out, len);
- rv = spi_xfer(dev-spi, max(len, in_bytes) * 8, out, p,
+ rv = spi_xfer(slave, max(len, in_bytes) * 8, out, p,
SPI_XFER_BEGIN | SPI_XFER_END);
- spi_release_bus(dev-spi);
+ spi_release_bus(slave);
if (rv) {
debug(%s: Cannot complete SPI transfer\n, __func__);
@@ -146,6 +166,7 @@ int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t
cmd, int cmd_version,
return len;
}
+#ifndef CONFIG_DM_CROS_EC
int cros_ec_spi_decode_fdt(struct cros_ec_dev *dev, const void *blob)
{
/* Decode interface-specific FDT params */
@@ -165,11 +186,40 @@ int cros_ec_spi_decode_fdt(struct cros_ec_dev *dev, const
void *blob)
*/
int cros_ec_spi_init(struct cros_ec_dev *dev, const void *blob)
{
- dev-spi = spi_setup_slave_fdt(blob, dev-node, dev-parent_node);
- if (!dev-spi) {
+ int ret;
+
+ ret = spi_setup_slave_fdt(blob, dev-node, dev-parent_node,
+ slave);
+ if (ret) {
debug(%s: Could not setup SPI slave\n, __func__);
- return -1;
+ return ret;
}
return 0;
}
+#endif
+
+#ifdef CONFIG_DM_CROS_EC
+int cros_ec_probe(struct udevice *dev)
+{
+ return cros_ec_register(dev);
+}
+
+struct dm_cros_ec_ops cros_ec_ops = {
+ .packet = cros_ec_spi_packet,
+ .command = cros_ec_spi_command,
+};
+
+static const struct udevice_id cros_ec_ids[] = {
+ { .compatible = google,cros-ec },
+ { }
+};
+
+U_BOOT_DRIVER(cros_ec_spi) = {
+ .name = cros_ec,
+ .id = UCLASS_CROS_EC,
+ .of_match = cros_ec_ids,
+ .probe = cros_ec_probe,
+ .ops= cros_ec_ops,
+};
+#endif
diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h
index 0bf9e53..9df8538 100644
--- a/include/configs/peach-pit.h
+++ b/include/configs/peach-pit.h
@@ -41,6 +41,7 @@
#define CONFIG_POWER_TPS65090_EC
#define CONFIG_CROS_EC_SPI /* Support
[U-Boot] [PATCH 03/10] dm: core: Allow device_bind() to used without CONFIG_OF_CONTROL
The sequence number support in driver model requires device tree control.
It should be skipped if CONFIG_OF_CONTROL is not defined, and should not
require functions from fdtdec.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/core/device.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 166b073..ef41a9b 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -106,13 +106,16 @@ int device_bind(struct udevice *parent, struct driver
*drv, const char *name,
* a 'requested' sequence, and will be resolved (and -seq updated)
* when the device is probed.
*/
- dev-req_seq = fdtdec_get_int(gd-fdt_blob, of_offset, reg, -1);
dev-seq = -1;
+#ifdef CONFIG_OF_CONTROL
+ dev-req_seq = fdtdec_get_int(gd-fdt_blob, of_offset, reg, -1);
if (uc-uc_drv-name of_offset != -1) {
fdtdec_get_alias_seq(gd-fdt_blob, uc-uc_drv-name, of_offset,
dev-req_seq);
}
-
+#else
+ dev-req_seq = -1;
+#endif
if (!dev-platdata drv-platdata_auto_alloc_size)
dev-flags |= DM_FLAG_ALLOC_PDATA;
--
2.1.0.rc2.206.gedb03e5
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[U-Boot] [PATCH 0/10] dm: imx: Add driver model support for GPIO and serial on cm_fx6
This series adjusts the IMX serial and GPIO drivers to support driver model. As an example of its use, the recently-added cm_fx6 board is converted over to driver model. Some minor driver model core changed are required to make this work and these are included with this series. Simon Glass (10): dm: linker_lists: Add a way to declare multiple objects dm: core: Allow a list of devices to be declared in one step dm: core: Allow device_bind() to used without CONFIG_OF_CONTROL dm: serial: Don't require device tree to configure a console dm: serial: Put common code into separate functions dm: imx: Use gpio_request() to request GPIOs imximage.cfg: Remove copyright header dm: imx: gpio: Support driver model in MXC gpio driver dm: imx: serial: Support driver model in the MXC serial driver dm: imx: Move cm_fx6 to use driver model for serial and GPIO arch/arm/imx-common/i2c-mxv7.c | 14 ++ board/compulab/cm_fx6/cm_fx6.c | 19 +++ board/compulab/cm_fx6/common.c | 3 + board/compulab/cm_fx6/imximage.cfg | 6 - drivers/core/device.c | 7 +- drivers/gpio/mxc_gpio.c| 291 - drivers/serial/serial-uclass.c | 35 +++-- drivers/serial/serial_mxc.c| 170 ++ include/configs/cm_fx6.h | 11 ++ include/dm/platdata.h | 4 + include/linker_lists.h | 21 +++ include/serial_mxc.h | 14 ++ 12 files changed, 545 insertions(+), 50 deletions(-) create mode 100644 include/serial_mxc.h -- 2.1.0.rc2.206.gedb03e5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 08/10] dm: imx: gpio: Support driver model in MXC gpio driver
Add driver model support with this driver. In this case the platform data
is in the driver. It would be better to put this into an SOC-specific file,
but this is best attempted when more boards are moved over to use driver
model.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/gpio/mxc_gpio.c | 291 +++-
1 file changed, 290 insertions(+), 1 deletion(-)
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index 6a572d5..8669cf0 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -8,16 +8,31 @@
* SPDX-License-Identifier:GPL-2.0+
*/
#include common.h
+#include errno.h
+#include dm.h
+#include malloc.h
#include asm/arch/imx-regs.h
#include asm/gpio.h
#include asm/io.h
-#include errno.h
enum mxc_gpio_direction {
MXC_GPIO_DIRECTION_IN,
MXC_GPIO_DIRECTION_OUT,
};
+#define GPIO_NAME_SIZE 20
+#define GPIO_PER_BANK 32
+
+struct mxc_gpio_plat {
+ struct gpio_regs *regs;
+};
+
+struct mxc_bank_info {
+ char label[GPIO_PER_BANK][GPIO_NAME_SIZE];
+ struct gpio_regs *regs;
+};
+
+#ifndef CONFIG_DM_GPIO
#define GPIO_TO_PORT(n)(n / 32)
/* GPIO port description */
@@ -134,3 +149,277 @@ int gpio_direction_output(unsigned gpio, int value)
return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT);
}
+#endif
+
+#ifdef CONFIG_DM_GPIO
+static int mxc_gpio_is_output(struct gpio_regs *regs, int offset)
+{
+ u32 val;
+
+ val = readl(regs-gpio_dir);
+
+ return val (1 offset) ? 1 : 0;
+}
+
+static void mxc_gpio_bank_direction(struct gpio_regs *regs, int offset,
+ enum mxc_gpio_direction direction)
+{
+ u32 l;
+
+ l = readl(regs-gpio_dir);
+
+ switch (direction) {
+ case MXC_GPIO_DIRECTION_OUT:
+ l |= 1 offset;
+ break;
+ case MXC_GPIO_DIRECTION_IN:
+ l = ~(1 offset);
+ }
+ writel(l, regs-gpio_dir);
+}
+
+static void mxc_gpio_bank_set_value(struct gpio_regs *regs, int offset,
+ int value)
+{
+ u32 l;
+
+ l = readl(regs-gpio_dr);
+ if (value)
+ l |= 1 offset;
+ else
+ l = ~(1 offset);
+ writel(l, regs-gpio_dr);
+}
+
+static int mxc_gpio_bank_get_value(struct gpio_regs *regs, int offset)
+{
+ return (readl(regs-gpio_psr) offset) 0x01;
+}
+
+static int mxc_gpio_bank_get_output_value(struct gpio_regs *regs, int offset)
+{
+ return (readl(regs-gpio_dr) offset) 0x01;
+}
+
+static int check_reserved(struct udevice *dev, unsigned offset,
+ const char *func)
+{
+ struct mxc_bank_info *bank = dev_get_priv(dev);
+ struct gpio_dev_priv *uc_priv = dev-uclass_priv;
+
+ if (!*bank-label[offset]) {
+ printf(mxc_gpio: %s: error: gpio %s%d not reserved\n,
+ func, uc_priv-bank_name, offset);
+ return -EPERM;
+ }
+
+ return 0;
+}
+
+/* set GPIO pin 'gpio' as an input */
+static int mxc_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+ struct mxc_bank_info *bank = dev_get_priv(dev);
+ int ret;
+
+ ret = check_reserved(dev, offset, __func__);
+ if (ret)
+ return ret;
+
+ /* Configure GPIO direction as input. */
+ mxc_gpio_bank_direction(bank-regs, offset, MXC_GPIO_DIRECTION_IN);
+
+ return 0;
+}
+
+/* set GPIO pin 'gpio' as an output, with polarity 'value' */
+static int mxc_gpio_direction_output(struct udevice *dev, unsigned offset,
+ int value)
+{
+ struct mxc_bank_info *bank = dev_get_priv(dev);
+ int ret;
+
+ ret = check_reserved(dev, offset, __func__);
+ if (ret)
+ return ret;
+
+ /* Configure GPIO output value. */
+ mxc_gpio_bank_set_value(bank-regs, offset, value);
+
+ /* Configure GPIO direction as output. */
+ mxc_gpio_bank_direction(bank-regs, offset, MXC_GPIO_DIRECTION_OUT);
+
+ return 0;
+}
+
+/* read GPIO IN value of pin 'gpio' */
+static int mxc_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+ struct mxc_bank_info *bank = dev_get_priv(dev);
+ int ret;
+
+ ret = check_reserved(dev, offset, __func__);
+ if (ret)
+ return ret;
+
+ return mxc_gpio_bank_get_value(bank-regs, offset);
+}
+
+/* write GPIO OUT value to pin 'gpio' */
+static int mxc_gpio_set_value(struct udevice *dev, unsigned offset,
+int value)
+{
+ struct mxc_bank_info *bank = dev_get_priv(dev);
+ int ret;
+
+ ret = check_reserved(dev, offset, __func__);
+ if (ret)
+ return ret;
+
+ mxc_gpio_bank_set_value(bank-regs, offset, value);
+
+ return 0;
+}
+
+static int mxc_gpio_get_state(struct udevice *dev, unsigned int offset,
+
[U-Boot] [PATCH 06/10] dm: imx: Use gpio_request() to request GPIOs
GPIOs should be requested before use. Without this, driver model will not
permit the GPIO to be used.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/arm/imx-common/i2c-mxv7.c | 14 ++
board/compulab/cm_fx6/cm_fx6.c | 9 +
board/compulab/cm_fx6/common.c | 3 +++
3 files changed, 26 insertions(+)
diff --git a/arch/arm/imx-common/i2c-mxv7.c b/arch/arm/imx-common/i2c-mxv7.c
index a580873..7cea024 100644
--- a/arch/arm/imx-common/i2c-mxv7.c
+++ b/arch/arm/imx-common/i2c-mxv7.c
@@ -4,6 +4,7 @@
* SPDX-License-Identifier:GPL-2.0+
*/
#include common.h
+#include malloc.h
#include asm/arch/clock.h
#include asm/arch/imx-regs.h
#include asm/errno.h
@@ -72,8 +73,21 @@ static void * const i2c_bases[] = {
void setup_i2c(unsigned i2c_index, int speed, int slave_addr,
struct i2c_pads_info *p)
{
+ char *name;
+
if (i2c_index = ARRAY_SIZE(i2c_bases))
return;
+
+ name = malloc(9);
+ assert(name);
+ sprintf(name, i2c_sda%d, i2c_index);
+ gpio_request(p-sda.gp, name);
+
+ name = malloc(9);
+ assert(name);
+ sprintf(name, i2c_scl%d, i2c_index);
+ gpio_request(p-scl.gp, name);
+
/* Enable i2c clock */
enable_i2c_clk(1, i2c_index);
/* Make sure bus is idle */
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
index fdb8ebf..80a123d 100644
--- a/board/compulab/cm_fx6/cm_fx6.c
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -71,8 +71,15 @@ static iomux_v3_cfg_t const sata_pads[] = {
static void cm_fx6_setup_issd(void)
{
+ int i;
+
SETUP_IOMUX_PADS(sata_pads);
+
+ for (i = 0; i ARRAY_SIZE(cm_fx6_issd_gpios); i++)
+ gpio_request(cm_fx6_issd_gpios[i], sata);
+
/* Make sure this gpio has logical 0 value */
+ gpio_request(CM_FX6_SATA_PWLOSS_INT, sata_pwloss_int);
gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
udelay(100);
@@ -167,6 +174,7 @@ static int cm_fx6_usb_hub_reset(void)
}
SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
+ gpio_request(CM_FX6_USB_HUB_RST, usb_hub_rst);
gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
udelay(10);
gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
@@ -324,6 +332,7 @@ int board_eth_init(bd_t *bis)
SETUP_IOMUX_PADS(enet_pads);
/* phy reset */
+ gpio_request(CM_FX6_ENET_NRST, enet_nrst);
gpio_direction_output(CM_FX6_ENET_NRST, 0);
udelay(500);
gpio_set_value(CM_FX6_ENET_NRST, 1);
diff --git a/board/compulab/cm_fx6/common.c b/board/compulab/cm_fx6/common.c
index 1f39679..562313b 100644
--- a/board/compulab/cm_fx6/common.c
+++ b/board/compulab/cm_fx6/common.c
@@ -79,6 +79,9 @@ void cm_fx6_set_ecspi_iomux(void)
int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
+#ifndef CONFIG_SPL_BUILD
+ gpio_request(CM_FX6_ECSPI_BUS0_CS0, ecspi_bus0_cs0);
+#endif
return (bus == 0 cs == 0) ? (CM_FX6_ECSPI_BUS0_CS0) : -1;
}
#endif
--
2.1.0.rc2.206.gedb03e5
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[U-Boot] [PATCH 05/10] dm: serial: Put common code into separate functions
Avoid duplicating the code which deals with getc() and putc(). It is fairly
simple, but may expand later.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/serial/serial-uclass.c | 32 +---
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 1ac943f..e93c624 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -71,7 +71,7 @@ void serial_initialize(void)
serial_find_console_or_panic();
}
-void serial_putc(char ch)
+static void serial_putc_dev(struct udevice *dev, char ch)
{
struct dm_serial_ops *ops = serial_get_ops(cur_dev);
int err;
@@ -83,6 +83,11 @@ void serial_putc(char ch)
serial_putc('\r');
}
+void serial_putc(char ch)
+{
+ serial_putc_dev(cur_dev, ch);
+}
+
void serial_setbrg(void)
{
struct dm_serial_ops *ops = serial_get_ops(cur_dev);
@@ -107,28 +112,32 @@ int serial_tstc(void)
return 1;
}
-int serial_getc(void)
+static int serial_getc_dev(struct udevice *dev)
{
- struct dm_serial_ops *ops = serial_get_ops(cur_dev);
+ struct dm_serial_ops *ops = serial_get_ops(dev);
int err;
do {
- err = ops-getc(cur_dev);
+ err = ops-getc(dev);
} while (err == -EAGAIN);
return err = 0 ? err : 0;
}
+int serial_getc(void)
+{
+ return serial_getc_dev(cur_dev);
+}
+
void serial_stdio_init(void)
{
}
-void serial_stub_putc(struct stdio_dev *sdev, const char ch)
+static void serial_stub_putc(struct stdio_dev *sdev, const char ch)
{
struct udevice *dev = sdev-priv;
- struct dm_serial_ops *ops = serial_get_ops(dev);
- ops-putc(dev, ch);
+ serial_putc_dev(dev, ch);
}
void serial_stub_puts(struct stdio_dev *sdev, const char *str)
@@ -140,15 +149,8 @@ void serial_stub_puts(struct stdio_dev *sdev, const char
*str)
int serial_stub_getc(struct stdio_dev *sdev)
{
struct udevice *dev = sdev-priv;
- struct dm_serial_ops *ops = serial_get_ops(dev);
-
- int err;
- do {
- err = ops-getc(dev);
- } while (err == -EAGAIN);
-
- return err = 0 ? err : 0;
+ return serial_getc_dev(dev);
}
int serial_stub_tstc(struct stdio_dev *sdev)
--
2.1.0.rc2.206.gedb03e5
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[U-Boot] [PATCH 07/10] imximage.cfg: Remove copyright header
This seems to break mkimage: Invalid imximage commands Type - valid names are: BOOT_FROM, BOOT_OFFSET, DATA, CSF, IMAGE_VERSION Error: board/compulab/cm_fx6/imximage.cfg[1] - Invalid command(/*) Signed-off-by: Simon Glass s...@chromium.org --- board/compulab/cm_fx6/imximage.cfg | 6 -- 1 file changed, 6 deletions(-) diff --git a/board/compulab/cm_fx6/imximage.cfg b/board/compulab/cm_fx6/imximage.cfg index 420947e..95e27be 100644 --- a/board/compulab/cm_fx6/imximage.cfg +++ b/board/compulab/cm_fx6/imximage.cfg @@ -1,8 +1,2 @@ -/* - * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ - * - * SPDX-License-Identifier:GPL-2.0+ - */ - IMAGE_VERSION 2 BOOT_FROM sd -- 2.1.0.rc2.206.gedb03e5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 02/10] dm: core: Allow a list of devices to be declared in one step
The U_BOOT_DEVICE macro allows the declaration of a single U-Boot device.
Add an equivalent macro to declare an array of devices, for convenience.
Signed-off-by: Simon Glass s...@chromium.org
---
include/dm/platdata.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/dm/platdata.h b/include/dm/platdata.h
index 2bc8b14..9e47e51 100644
--- a/include/dm/platdata.h
+++ b/include/dm/platdata.h
@@ -25,4 +25,8 @@ struct driver_info {
#define U_BOOT_DEVICE(__name) \
ll_entry_declare(struct driver_info, __name, driver_info)
+/* Declare a list of devices. The argument is a driver_info[] array */
+#define U_BOOT_DEVICES(__name) \
+ ll_entry_declare_list(struct driver_info, __name, driver_info)
+
#endif
--
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