[U-Boot] [PATCH] net: macb: write mac address when initialization
When boot up without mac address setting, it will give the warning
message like: Warning: failed to set MAC address, however when
execute network related command, it still execute them without any
warning information.
With this patch, it will exit directly with following information:
gmac0: mac address is not valid
It also solve the problem after bootup then set mac address and the
mac address won't set to net device issue.
Signed-off-by: Bo Shen voice.s...@atmel.com
---
drivers/net/macb.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 375c8a4..4616f36 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -525,6 +525,7 @@ static int macb_phy_init(struct macb_device *macb)
return 1;
}
+static int macb_write_hwaddr(struct eth_device *dev);
static int macb_init(struct eth_device *netdev, bd_t *bd)
{
struct macb_device *macb = to_macb(netdev);
@@ -587,6 +588,14 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
#endif /* CONFIG_RMII */
}
+ /* update the ethaddr */
+ if (is_valid_ether_addr(netdev-enetaddr)) {
+ macb_write_hwaddr(netdev);
+ } else {
+ printf(%s: mac address is not valid\n, netdev-name);
+ return -1;
+ }
+
if (!macb_phy_init(macb))
return -1;
--
2.1.0.24.g4109c28
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[U-Boot] [PATCH] imximage: Fix the bootdata.size calculation
The bootdata.size should contain the IVT offset part, but the calculation
in imximage tool does not have. This will cause some data at
the end of image not be loaded into memory.
Signed-off-by: Ye.Li b37...@freescale.com
---
tools/imximage.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index faba238..526b7d4 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -587,7 +587,7 @@ static void imximage_set_header(void *ptr, struct stat
*sbuf, int ifd,
*
* The remaining fraction of a block bytes would not be loaded!
*/
- *header_size_ptr = ROUND(sbuf-st_size, 4096);
+ *header_size_ptr = ROUND((sbuf-st_size + imximage_ivt_offset), 4096);
if (csf_ptr imximage_csf_size) {
*csf_ptr = params-ep - imximage_init_loadsize +
--
1.7.4.1
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Re: [U-Boot] [PATCH] imximage: Fix the bootdata.size calculation
Hi Ye, On 22/10/2014 08:39, Ye.Li wrote: The bootdata.size should contain the IVT offset part, but the calculation in imximage tool does not have. This will cause some data at the end of image not be loaded into memory. Signed-off-by: Ye.Li b37...@freescale.com --- tools/imximage.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/tools/imximage.c b/tools/imximage.c index faba238..526b7d4 100644 --- a/tools/imximage.c +++ b/tools/imximage.c @@ -587,7 +587,7 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd, * * The remaining fraction of a block bytes would not be loaded! */ - *header_size_ptr = ROUND(sbuf-st_size, 4096); + *header_size_ptr = ROUND((sbuf-st_size + imximage_ivt_offset), 4096); Can you help me pointing which part of the manual(s) is describing this ? Checking into i.MX6Q, length is defined as size of the program image, that means without IVT. I have not yet checked into MX53. Which is the use case you find the error ? Do you had a size of exactly a multiple of 4K and have you discover that the whole image was not loaded ? Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] net: macb: write mac address when initialization
Hi Bo,
On Wed, 22 Oct 2014 14:45:56 +0800
Bo Shen voice.s...@atmel.com wrote:
When boot up without mac address setting, it will give the warning
message like: Warning: failed to set MAC address, however when
execute network related command, it still execute them without any
warning information.
With this patch, it will exit directly with following information:
gmac0: mac address is not valid
It also solve the problem after bootup then set mac address and the
mac address won't set to net device issue.
Signed-off-by: Bo Shen voice.s...@atmel.com
Thanks for fixing this.
Tested-by Boris Brezillon boris.brezil...@free-electrons.com
---
drivers/net/macb.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 375c8a4..4616f36 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -525,6 +525,7 @@ static int macb_phy_init(struct macb_device *macb)
return 1;
}
+static int macb_write_hwaddr(struct eth_device *dev);
static int macb_init(struct eth_device *netdev, bd_t *bd)
{
struct macb_device *macb = to_macb(netdev);
@@ -587,6 +588,14 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
#endif /* CONFIG_RMII */
}
+ /* update the ethaddr */
+ if (is_valid_ether_addr(netdev-enetaddr)) {
+ macb_write_hwaddr(netdev);
+ } else {
+ printf(%s: mac address is not valid\n, netdev-name);
+ return -1;
+ }
+
if (!macb_phy_init(macb))
return -1;
--
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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Re: [U-Boot] [PATCH] imximage: Fix the bootdata.size calculation
Hi Stefano, On 10/22/2014 3:22 PM, Stefano Babic wrote: Hi Ye, On 22/10/2014 08:39, Ye.Li wrote: The bootdata.size should contain the IVT offset part, but the calculation in imximage tool does not have. This will cause some data at the end of image not be loaded into memory. Signed-off-by: Ye.Li b37...@freescale.com --- tools/imximage.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/tools/imximage.c b/tools/imximage.c index faba238..526b7d4 100644 --- a/tools/imximage.c +++ b/tools/imximage.c @@ -587,7 +587,7 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd, * * The remaining fraction of a block bytes would not be loaded! */ -*header_size_ptr = ROUND(sbuf-st_size, 4096); +*header_size_ptr = ROUND((sbuf-st_size + imximage_ivt_offset), 4096); Can you help me pointing which part of the manual(s) is describing this ? Checking into i.MX6Q, length is defined as size of the program image, that means without IVT. I have not yet checked into MX53. Which is the use case you find the error ? Do you had a size of exactly a multiple of 4K and have you discover that the whole image was not loaded ? Best regards, Stefano Babic You can look into the Figure 8-21. Image Vector Table in the system boot chapter of i.MX6Q manual. The bootdata.start points to the beginning of the destination memory, which means the bootdata.size should have IVT offset included. We also have checked the boot rom codes for this. We found this issue when booting from QSPI NOR on i.MX6SX. The u-boot runs into abnormal (crash or stop) after booting. We checked the destination memory where the image is loaded to, and found hundreds of bytes at the image end are not loaded into memory. Since there is a 4096 bytes round in the calculation, so the image size decides if the issue can be reproduced. It is not easy to see the issue by SD boot. Best regards, Ye Li ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC] MW rule and its period
Hi Otavio, On 21/10/2014 21:14, Otavio Salvador wrote: On Tue, Oct 21, 2014 at 4:07 PM, Masahiro YAMADA yamad...@jp.panasonic.com wrote: ... So two options here I'd like to suggest [1] Every 2 months release with 2 weeks MW MW open: 2 weeks MW closed: 6.5 weeks I prefer this option however I also want to warn this will impose more active response from custodians. In case of the i.MX we had long delays in review and merges from Stefano from time to time and this would complicate a lot. Please understand that work as u-boot custodian is done by me (and by other custodians) in our spare time, and depending on our current load this time can be smaller as desired. So for i.MX specific case some patches got merged late and this complicates a lot testing. I confess I have been not so strict regarding merge window and its rules: if I can merge a patchset without affecting a lot the rest of U-Boot, I tend to do it, even if patches were sent later. This seems a common problem, as the thread was originated by socFPGA patches. We have to decide now if we should be more strict with merge window rule or not. However, this can bring that new features will be delayed to next releases. Mainly because sometimes one tree depends on changes in another This is due to the fact that subsystems and/or SOCs cannot be easy isolated. Sometimes it is also not clear who is the custodian responsible for a patch, and sometimes the same patchset is split into several are of competences. and a lack of u-boot-next where all them are automatic merged complicates a full test of upcoming release. This can help, but we need to define how conflicts are then resolved and who take care of them. Without defining those rules, it does not help a lot. p.s: this is not a personal attack but something which is clearly happening. Of course - we are trying all together to make the whole process better ;-) Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Revert sunxi: dram: Use divisor P=1 for PLL5
On Tue, 2014-10-21 at 16:58 -0400, Tom Rini wrote: We should be doing things right, in mainline. To bring up a different example, on TI OMAP4 parts at least for a long time in order to use mainline U-Boot on older kernels you had to manually add CONFIG_SOMETHING_OR_ANOTHER to enable additional clocks/mux that the old kernels had incorrectly relied on U-Boot to set. If we must do strange things to support old and incorrect but in the wild kernels we need to (a) make it opt-in (easier now with Kconfig!) and (b) schedule a removal of the hack all the same. A Kconfig option does sound like a reasonable compromise. Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] imximage: Fix the bootdata.size calculation
Hi Ye, On 22/10/2014 09:38, Li Ye-B37916 wrote: You can look into the Figure 8-21. Image Vector Table in the system boot chapter of i.MX6Q manual. The bootdata.start points to the beginning of the destination memory, which means the bootdata.size should have IVT offset included. Well, ok, this is an interpretation We also have checked the boot rom codes for this. ok - this is the most important thing. Is it the same for all MX6 and MX53 ? We found this issue when booting from QSPI NOR on i.MX6SX. The u-boot runs into abnormal (crash or stop) after booting. We checked the destination memory where the image is loaded to, and found hundreds of bytes at the image end are not loaded into memory. Since there is a 4096 bytes round in the calculation, so the image size decides if the issue can be reproduced. It is not easy to see the issue by SD boot. ok - the only thing that it looks weird is that the issue happens now and not with a MX6Q(D) booting from SPI-NOR. There are several boards booting from SPI, but I have not heard about such as problems. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v10 14/14] RFC: Deprecate MAKEALL
Dear Tom, In message 20141014081724.GF25506@bill-the-cat you wrote: No, not yet. I am going to mention in the release notes that we're going to strongly start thinking about deleting MAKEALL. We can pick up the deprecation patch early in the next merge window. Can we please keep at least some script (as a wrapper around buildman?) that keeps the old user interface in place? I frequently use git bisect run MAKEALL board ..., and it would be nice if we could keep this working even in newer versions of the code. Or is there a similar alternative command that works with identical parameters for - say - all versions of the last two years or so? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de I will also, for an appropriate fee, certify that your keyboard is object-oriented, and that the bits on your hard disk are template- compatible.- Jeffrey S. Haemer in 411akr$3...@cygnus.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] imximage: Fix the bootdata.size calculation
Hi Stefano, On 10/22/2014 4:14 PM, Stefano Babic wrote: Hi Ye, On 22/10/2014 09:38, Li Ye-B37916 wrote: You can look into the Figure 8-21. Image Vector Table in the system boot chapter of i.MX6Q manual. The bootdata.start points to the beginning of the destination memory, which means the bootdata.size should have IVT offset included. Well, ok, this is an interpretation We also have checked the boot rom codes for this. ok - this is the most important thing. Is it the same for all MX6 and MX53 ? Yes. This is same for all MX6 and MX53. We found this issue when booting from QSPI NOR on i.MX6SX. The u-boot runs into abnormal (crash or stop) after booting. We checked the destination memory where the image is loaded to, and found hundreds of bytes at the image end are not loaded into memory. Since there is a 4096 bytes round in the calculation, so the image size decides if the issue can be reproduced. It is not easy to see the issue by SD boot. ok - the only thing that it looks weird is that the issue happens now and not with a MX6Q(D) booting from SPI-NOR. There are several boards booting from SPI, but I have not heard about such as problems. Best regards, Stefano Babic There are some reasons: 1. The SPI-NOR IVT offset is 0x400, but QSPI-NOR IVT offset is 0x1000. Because of the 0x1000 round, the possibility of showing the issue on SPI-NOR is less than QSPI-NOR. Even for QSPI-NOR, we only reproduce it on some image with particular size . 2. The IVT_offset was once included in the calculation before this patch 2013-08-31 Stefano Babictools: imx_header should not include flash_offset. 3. At the end of the image, most of data are zero. Best regards, Ye Li ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Revert sunxi: dram: Use divisor P=1 for PLL5
Hi, On 10/22/2014 10:14 AM, Ian Campbell wrote: On Tue, 2014-10-21 at 16:58 -0400, Tom Rini wrote: We should be doing things right, in mainline. To bring up a different example, on TI OMAP4 parts at least for a long time in order to use mainline U-Boot on older kernels you had to manually add CONFIG_SOMETHING_OR_ANOTHER to enable additional clocks/mux that the old kernels had incorrectly relied on U-Boot to set. If we must do strange things to support old and incorrect but in the wild kernels we need to (a) make it opt-in (easier now with Kconfig!) and (b) schedule a removal of the hack all the same. A Kconfig option does sound like a reasonable compromise. Ok, I will look into this, my plan for now is to call it OLD_KERNEL_COMPAT, so that if we come across more cases like this we've one config option for them, rather then a ton of small isolated config options. Regards, Hans ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] arm: mx6: add support for TBS2910 Matrix ARM miniPC
Hi Soeren,
On 21/10/2014 19:54, Soeren Moch wrote:
This is also copied from sabresd. Can we factorize in some way ?
I can, and probably should, simplify this code. But in fact this code
is wrong, and in the same way for many imx6q boards (e.g. sabresd,
wandboard, nitrogen6x,...).
That makes things only worse. Duplicating the code, we have an
additional board with bad / wrong code.
This code configures the external video clock (LDB_DIx clock). This
clock is hardcoded to have 65MHz in drivers/video/ipu_common.c:ldb_clk.
But in fact the clock rate is configured to 75.42MHz (528MHz/7) on all
boards. So the display does not show 1024x768@60Hz as configured, but
something similar to 1024x768@70Hz (not VESA compliant), which much
monitors can handle, but on other monitors there are problems.
(one out of tree monitors works for me).
Ok, understood.
My intention was to get this initial support for tbs2910 merged with the
(wrong) code from sabresd used as template, and later to discuss how to
cleanup this code.
Do you prefer a simplified version of this code for the initial patch?
Maybe this is the best approach: you can at the beginning drop support
for video, an let your board be merged without wrong code. Then we can
discuss about fixing the wrong clock as shared code, letting that all
boards take advantage for that.
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+int board_eth_init(bd_t *bis)
+{
+setup_iomux_enet();
+setup_pcie();
+
+return cpu_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+setup_iomux_uart();
+#ifdef CONFIG_VIDEO_IPUV3
+setup_display();
I do not understand why setup_display() should be called at this point.
Generally, board_early_init_f() is called to setup iomux for peripherals
needed before relocation, as uart, letting the rest of the setup in
board_init(). Why do you need here ?
In fact this was also copied from sabresd/wandboard/nitrogen6x.
My assumption was, that the clocks must be configured before the
ipu is initialized.
That is correct, but ipu is initialized by video_init() after
board_init() is called. Generally, board_early_init() is responsible for
setup some initial peripherals, for example the iomux for uart or for
RAM controller. The common initialization is then put into board_init().
I am expecting that you have no issues by moving setup_display() in the
board_init() function.
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
new file mode 100644
index 000..602d691
--- /dev/null
+++ b/configs/tbs2910_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS=IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q
Be aware that changes in the ddr-setup in that file will have a
consequence on your board.
Yes, I'm aware of that. But nitrogen6x is very well maintained. So I see
no need to
duplicate this config and reuse it in the same way as wandboard does.
ok, that is enough, then it is fine with me.
Best regards,
Stefano Babic
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=
DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
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Re: [U-Boot] [PATCH] mx6sabresd: Add Seiko WVGA panel support
On 22/10/2014 01:14, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
Add support for the 4.3'' Seiko WVGA parallel display.
In order to direct the splash screen to the Seiko display:
= setenv panel SEIKO-WVGA
= save
= reset
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
board/freescale/mx6sabresd/mx6sabresd.c | 61
+
1 file changed, 61 insertions(+)
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c
b/board/freescale/mx6sabresd/mx6sabresd.c
index 81dcd6e..3d81fff 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -51,6 +51,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
+#define DISP0_PWR_EN IMX_GPIO_NR(1, 21)
+
int dram_init(void)
{
gd-ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -141,6 +143,45 @@ iomux_v3_cfg_t const ecspi1_pads[] = {
MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
+static iomux_v3_cfg_t const rgb_pads[] = {
+ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void enable_rgb(struct display_info_t const *dev)
+{
+ imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads));
+ gpio_direction_output(DISP0_PWR_EN, 1);
+}
+
static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
@@ -357,6 +398,26 @@ struct display_info_t const displays[] = {{
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus= 0,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = NULL,
+ .enable = enable_rgb,
+ .mode = {
+ .name = SEIKO-WVGA,
+ .refresh= 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 29850,
+ .left_margin= 89,
+ .right_margin = 164,
+ .upper_margin = 23,
+ .lower_margin = 10,
+ .hsync_len = 10,
+ .vsync_len = 10,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
} } };
size_t display_count = ARRAY_SIZE(displays);
Acked-by: Stefano Babic sba...@denx.de
Best regards,
Stefano Babic
--
=
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Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=
[U-Boot] [PATCH v2 2/8] ARM: sunxi: Add support for uart0 on port F (mmc0)
Allwinner SoCs provide uart0 muxed with mmc0, which can then be used
with a micro SD breakout board. On the A23, this is the only way to
use uart0.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Ian Campbell i...@hellion.org.uk
---
arch/arm/cpu/armv7/sunxi/board.c | 11 ++-
include/configs/sunxi-common.h | 2 ++
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index b6d63db..29d45b6 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -50,7 +50,16 @@ u32 spl_boot_mode(void)
int gpio_init(void)
{
-#if CONFIG_CONS_INDEX == 1 (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
+#if CONFIG_CONS_INDEX == 1 defined(CONFIG_UART0_PORT_F)
+#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)
+ /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
+#endif
+ sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX);
+ sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX);
+ sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
+#elif CONFIG_CONS_INDEX == 1 (defined(CONFIG_SUN4I) ||
defined(CONFIG_SUN7I))
sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index a8d08b4..6ba9df6 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -77,6 +77,7 @@
#define CONFIG_INITRD_TAG
/* mmc config */
+#if !defined(CONFIG_UART0_PORT_F)
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_CMD_MMC
@@ -84,6 +85,7 @@
#define CONFIG_MMC_SUNXI_SLOT 0
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC
controller */
+#endif
/* 4MB of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 20))
--
2.1.1
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[U-Boot] [PATCH v2 5/8] ARM: sunxi: Add support for R_PIO gpio banks
From: Hans de Goede hdego...@redhat.com
The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO
or R_PIO, which handles pin banks L and beyond.
Also add a clear description about SUNXI_GPIO_BANKS, stating it only
counts the number of pin banks in the _main_ pin controller.
Signed-off-by: Hans de Goede hdego...@redhat.com
[w...@csie.org: expanded commit message]
[w...@csie.org: add pin bank M and expand comments]
[w...@csie.org: add comment on SUNXI_GPIO_BANKS macro]
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/include/asm/arch-sunxi/gpio.h | 31 +--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include/asm/arch-sunxi/gpio.h
index 7e2b169..de7a86a 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -10,6 +10,7 @@
#define _SUNXI_GPIO_H
#include linux/types.h
+#include asm/arch/cpu.h
/*
* sunxi has 9 banks of gpio, they are:
@@ -27,8 +28,27 @@
#define SUNXI_GPIO_G 6
#define SUNXI_GPIO_H 7
#define SUNXI_GPIO_I 8
+
+/*
+ * This defines the number of GPIO banks for the _main_ GPIO controller.
+ * You should fix up the padding in struct sunxi_gpio_reg below if you
+ * change this.
+ */
#define SUNXI_GPIO_BANKS 9
+/*
+ * sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO)
+ * at a different register offset.
+ *
+ * sun6i has 2 banks:
+ * PL0 - PL8 | PM0 - PM7
+ *
+ * sun8i has 1 bank:
+ * PL0 - PL11
+ */
+#define SUNXI_GPIO_L 11
+#define SUNXI_GPIO_M 12
+
struct sunxi_gpio {
u32 cfg[4];
u32 dat;
@@ -50,8 +70,9 @@ struct sunxi_gpio_reg {
struct sunxi_gpio_int gpio_int;
};
-#define BANK_TO_GPIO(bank) \
- ((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)-gpio_bank[bank]
+#define BANK_TO_GPIO(bank) (((bank) SUNXI_GPIO_L) ? \
+ ((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)-gpio_bank[bank] : \
+ ((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)-gpio_bank[(bank) -
SUNXI_GPIO_L])
#define GPIO_BANK(pin) ((pin) 5)
#define GPIO_NUM(pin) ((pin) 0x1f)
@@ -75,6 +96,8 @@ struct sunxi_gpio_reg {
#define SUNXI_GPIO_G_NR32
#define SUNXI_GPIO_H_NR32
#define SUNXI_GPIO_I_NR32
+#define SUNXI_GPIO_L_NR32
+#define SUNXI_GPIO_M_NR32
#define SUNXI_GPIO_NEXT(__gpio) \
((__gpio##_START) + (__gpio##_NR) + 0)
@@ -89,6 +112,8 @@ enum sunxi_gpio_number {
SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F),
SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G),
SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
+ SUNXI_GPIO_L_START = 352,
+ SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
};
/* SUNXI GPIO number definitions */
@@ -101,6 +126,8 @@ enum sunxi_gpio_number {
#define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr))
#define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr))
#define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr))
+#define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr))
+#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr))
/* GPIO pin function config */
#define SUNXI_GPIO_INPUT 0
--
2.1.1
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[U-Boot] [PATCH v2 0/8] ARM: sunxi: Add Allwinner A23 (sun8i) support
Hi everyone, This series adds support for Allwinner's A23 SoC. All the patches are either direct cherry-picks or changes manually merged from u-boot-sunxi. Patch 1 adds uart0 pinmux values for A23. Patch 2 adds support for using uart0 on port F, either using a breakout board or soldering wires to exposed pads. At least one version of A23 tablets requires this, as no other uarts are exposed. Patch 3 adds support for sun8i in the mmc driver. This is the same as sun6i. Patch 4 adds machine support for sun8i. Patch 5 adds support for gpio banks L and beyond, which is used by r_uart, p2wi (on sun6i) and rsb (on sun8i). Patch 6 makes the prcm apb0 clock enabling function to take an argument for which modules should be enabled. Patch 7 adds support for using r_uart as a console (with CONS_INDEX=5). Patch 8 adds a defconfig for the Ippo Q8H A23 tablet board. Changes since v1: - Dropped ARM: sunxi: Fix build break when CONFIG_MMC is not defined (already merged) - Add clarifying comment about SUNXI_GPIO_BANKS macro - Correct R_PIO L pin bank starting offset - Check for R_PIO pins by matching against L pin bank start pin number Cheers ChenYu Chen-Yu Tsai (7): ARM: sunxi: Add sun8i (A23) UART0 pin mux support ARM: sunxi: Add support for uart0 on port F (mmc0) mmc: sunxi: Add support for sun8i (A23) ARM: sunxi: Add basic A23 support ARM: sunxi: Allow specifying module in prcm apb0 init function ARM: sunxi: Add support for using R_UART as console ARM: sunxi: Add Ippo-q8h-v5 A23 tablet board defconfig Hans de Goede (1): ARM: sunxi: Add support for R_PIO gpio banks arch/arm/Kconfig| 3 +++ arch/arm/cpu/armv7/sunxi/Makefile | 2 ++ arch/arm/cpu/armv7/sunxi/board.c| 18 +-- arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 6 + arch/arm/cpu/armv7/sunxi/cpu_info.c | 2 ++ arch/arm/cpu/armv7/sunxi/prcm.c | 12 +- arch/arm/include/asm/arch-sunxi/clock.h | 2 +- arch/arm/include/asm/arch-sunxi/cpu.h | 1 + arch/arm/include/asm/arch-sunxi/gpio.h | 40 +++-- arch/arm/include/asm/arch-sunxi/mmc.h | 2 +- arch/arm/include/asm/arch-sunxi/prcm.h | 2 +- board/sunxi/Kconfig | 3 ++- board/sunxi/MAINTAINERS | 5 + configs/Ippo_q8h_defconfig | 4 drivers/mmc/sunxi_mmc.c | 2 +- include/configs/sun8i.h | 23 +++ include/configs/sunxi-common.h | 3 +++ 17 files changed, 116 insertions(+), 14 deletions(-) create mode 100644 configs/Ippo_q8h_defconfig create mode 100644 include/configs/sun8i.h -- 2.1.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mx6sabresd: Add Seiko WVGA panel support
Hello Fabio,
On 22-10-14 01:14, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
Add support for the 4.3'' Seiko WVGA parallel display.
In order to direct the splash screen to the Seiko display:
= setenv panel SEIKO-WVGA
= save
= reset
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
[snip]
+} }, {
+ .bus= 0,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = NULL,
+ .enable = enable_rgb,
+ .mode = {
+ .name = SEIKO-WVGA,
+ .refresh= 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 29850,
+ .left_margin= 89,
+ .right_margin = 164,
+ .upper_margin = 23,
+ .lower_margin = 10,
+ .hsync_len = 10,
+ .vsync_len = 10,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
} } };
size_t display_count = ARRAY_SIZE(displays);
If [1] is a datasheet for this lcd, you likely want to add
#include ../drivers/video/mxcfb.h
.sync = FB_SYNC_CLK_LAT_FALL,
Or something similar, since the data is sampled on the falling edge
of the pixel clock / the pixel clock is inverted.
Regards,
Jeroen
[1] http://www.glyn.de/data/glyn/media/doc/43wvf1g-0.pdf
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[U-Boot] [PATCH v2 3/8] mmc: sunxi: Add support for sun8i (A23)
The Allwinner A23 SoC has reset controls like the A31 (sun6i).
The FIFO address is also the same as sun6i.
Re-use code added for sun6i.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Ian Campbell i...@hellion.org.uk
---
arch/arm/include/asm/arch-sunxi/mmc.h | 2 +-
drivers/mmc/sunxi_mmc.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h
b/arch/arm/include/asm/arch-sunxi/mmc.h
index 70d7875..8a21674 100644
--- a/arch/arm/include/asm/arch-sunxi/mmc.h
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -43,7 +43,7 @@ struct sunxi_mmc {
u32 chda; /* 0x90 */
u32 cbda; /* 0x94 */
u32 res1[26];
-#if defined(CONFIG_SUN6I)
+#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I)
u32 res2[64];
#endif
u32 fifo; /* 0x100 (0x200 on sun6i) FIFO access address */
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index d3b1039..16592e3 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -75,7 +75,7 @@ static int mmc_clk_io_on(int sdc_no)
/* config ahb clock */
setbits_le32(ccm-ahb_gate0, 1 AHB_GATE_OFFSET_MMC(sdc_no));
-#if defined(CONFIG_SUN6I)
+#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I)
/* unassert reset */
setbits_le32(ccm-ahb_reset0_cfg, 1 AHB_RESET_OFFSET_MMC(sdc_no));
#endif
--
2.1.1
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[U-Boot] [PATCH v2 1/8] ARM: sunxi: Add sun8i (A23) UART0 pin mux support
UART0 pin muxes on the A23 have a different function value.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Ian Campbell i...@hellion.org.uk
---
arch/arm/include/asm/arch-sunxi/gpio.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include/asm/arch-sunxi/gpio.h
index 59122db..7e2b169 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -127,8 +127,14 @@ enum sunxi_gpio_number {
#define SUNXI_GPF0_SDC02
#define SUNXI_GPF2_SDC02
+
+#ifdef CONFIG_SUN8I
+#define SUNXI_GPF2_UART0_TX3
+#define SUNXI_GPF4_UART0_RX3
+#else
#define SUNXI_GPF2_UART0_TX4
#define SUNXI_GPF4_UART0_RX4
+#endif
#define SUN4I_GPG0_SDC14
--
2.1.1
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[U-Boot] [PATCH v2 4/8] ARM: sunxi: Add basic A23 support
The basic blocks of the A23 are similar to the A31 (sun6i). Re-use
sun6i code for initial clock, gpio, and uart setup.
There is no SPL support for A23, as we do not have any documentation
or sample code for DRAM initialization.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Ian Campbell i...@hellion.org.uk
---
arch/arm/Kconfig| 3 +++
arch/arm/cpu/armv7/sunxi/Makefile | 2 ++
arch/arm/cpu/armv7/sunxi/board.c| 3 ++-
arch/arm/cpu/armv7/sunxi/cpu_info.c | 2 ++
arch/arm/include/asm/arch-sunxi/clock.h | 2 +-
board/sunxi/Kconfig | 3 ++-
include/configs/sun8i.h | 23 +++
7 files changed, 35 insertions(+), 3 deletions(-)
create mode 100644 include/configs/sun8i.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8bcb7e3..cff7ad9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -450,6 +450,9 @@ config TARGET_SUN6I
config TARGET_SUN7I
bool Support sun7i
+config TARGET_SUN8I
+ bool Support sun8i
+
config TARGET_SNOWBALL
bool Support snowball
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile
b/arch/arm/cpu/armv7/sunxi/Makefile
index 2a42dca..24f1dae 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -12,10 +12,12 @@ obj-y += board.o
obj-y += clock.o
obj-y += pinmux.o
obj-$(CONFIG_SUN6I)+= prcm.o
+obj-$(CONFIG_SUN8I)+= prcm.o
obj-$(CONFIG_SUN4I)+= clock_sun4i.o
obj-$(CONFIG_SUN5I)+= clock_sun4i.o
obj-$(CONFIG_SUN6I)+= clock_sun6i.o
obj-$(CONFIG_SUN7I)+= clock_sun4i.o
+obj-$(CONFIG_SUN8I)+= clock_sun6i.o
ifndef CONFIG_SPL_BUILD
obj-y += cpu_info.o
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 29d45b6..61c1ba9 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -100,7 +100,8 @@ void reset_cpu(ulong addr)
/* do some early init */
void s_init(void)
{
-#if !defined CONFIG_SPL_BUILD (defined CONFIG_SUN7I || defined CONFIG_SUN6I)
+#if !defined CONFIG_SPL_BUILD (defined CONFIG_SUN7I || \
+ defined CONFIG_SUN6I || defined CONFIG_SUN8I)
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
asm volatile(
mrc p15, 0, r0, c1, c0, 1\n
diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c
b/arch/arm/cpu/armv7/sunxi/cpu_info.c
index 40c4e13..4f2a09c 100644
--- a/arch/arm/cpu/armv7/sunxi/cpu_info.c
+++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c
@@ -27,6 +27,8 @@ int print_cpuinfo(void)
puts(CPU: Allwinner A31 (SUN6I)\n);
#elif defined CONFIG_SUN7I
puts(CPU: Allwinner A20 (SUN7I)\n);
+#elif defined CONFIG_SUN8I
+ puts(CPU: Allwinner A23 (SUN8I)\n);
#else
#warning Please update cpu_info.c with correct CPU information
puts(CPU: SUNXI Family\n);
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h
b/arch/arm/include/asm/arch-sunxi/clock.h
index 8f5d860..012c2af 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -15,7 +15,7 @@
#define CLK_GATE_CLOSE 0x0
/* clock control module regs definition */
-#ifdef CONFIG_SUN6I
+#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I)
#include asm/arch/clock_sun6i.h
#else
#include asm/arch/clock_sun4i.h
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 4ac562c..7fe9005 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN6I || TARGET_SUN7I
+if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN6I || TARGET_SUN7I || TARGET_SUN8I
config SYS_CONFIG_NAME
string
@@ -6,6 +6,7 @@ config SYS_CONFIG_NAME
default sun5i if TARGET_SUN5I
default sun6i if TARGET_SUN5I
default sun7i if TARGET_SUN7I
+ default sun8i if TARGET_SUN8I
config SYS_CPU
default armv7
diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h
new file mode 100644
index 000..1c1a7cd
--- /dev/null
+++ b/include/configs/sun8i.h
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2014 Chen-Yu Tsai w...@csie.org
+ *
+ * Configuration settings for the Allwinner A23 (sun8i) CPU
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * A23 specific configuration
+ */
+#define CONFIG_SUN8I /* sun8i SoC generation */
+#define CONFIG_SYS_PROMPT sun8i#
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include configs/sunxi-common.h
+
+#endif /* __CONFIG_H */
--
2.1.1
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[U-Boot] [PATCH v2 7/8] ARM: sunxi: Add support for using R_UART as console
The A23 only has UART0 muxed with MMC0. Some of the boards we
encountered expose R_UART as a set of pads.
Add support for R_UART so we can have a console while using mmc.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Ian Campbell i...@hellion.org.uk
---
arch/arm/cpu/armv7/sunxi/board.c | 4
arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 6 ++
arch/arm/include/asm/arch-sunxi/cpu.h | 1 +
arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++
include/configs/sunxi-common.h | 1 +
5 files changed, 15 insertions(+)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 61c1ba9..aeb2c2f 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -75,6 +75,10 @@ int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 5 defined(CONFIG_SUN8I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX);
+ sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
#else
#error Unsupported console port number. Please fix pin mux settings in board.c
#endif
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index 8387b93..1eae976 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -13,6 +13,7 @@
#include common.h
#include asm/io.h
#include asm/arch/clock.h
+#include asm/arch/prcm.h
#include asm/arch/sys_proto.h
void clock_init_uart(void)
@@ -20,6 +21,7 @@ void clock_init_uart(void)
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+#if CONFIG_CONS_INDEX 5
/* uart clock source is apb2 */
writel(APB2_CLK_SRC_OSC24M|
APB2_CLK_RATE_N_1|
@@ -35,6 +37,10 @@ void clock_init_uart(void)
setbits_le32(ccm-apb2_reset_cfg,
1 (APB2_RESET_UART_SHIFT +
CONFIG_CONS_INDEX - 1));
+#else
+ /* enable R_PIO and R_UART clocks, and de-assert resets */
+ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
+#endif
/* Dup with clock_init_safe(), drop once sun6i SPL support lands */
writel(PLL6_CFG_DEFAULT, ccm-pll6_cfg);
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h
b/arch/arm/include/asm/arch-sunxi/cpu.h
index 313e6c8..0de79a0 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -111,6 +111,7 @@
#define SUNXI_AVG_BASE 0x01ea
#define SUNXI_PRCM_BASE0x01f01400
+#define SUNXI_R_UART_BASE 0x01f02800
#define SUNXI_R_PIO_BASE 0x01f02c00
#define SUNXI_P2WI_BASE0x01f03400
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include/asm/arch-sunxi/gpio.h
index de7a86a..7bb6499 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -172,6 +172,9 @@ enum sunxi_gpio_number {
#define SUN4I_GPI4_SDC32
+#define SUN8I_GPL2_R_UART_TX 2
+#define SUN8I_GPL3_R_UART_RX 2
+
/* GPIO pin pull-up/down config */
#define SUNXI_GPIO_PULL_DISABLE0
#define SUNXI_GPIO_PULL_UP 1
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 6ba9df6..97fd9e2 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -42,6 +42,7 @@
#define CONFIG_SYS_NS16550_COM2SUNXI_UART1_BASE
#define CONFIG_SYS_NS16550_COM3SUNXI_UART2_BASE
#define CONFIG_SYS_NS16550_COM4SUNXI_UART3_BASE
+#define CONFIG_SYS_NS16550_COM5SUNXI_R_UART_BASE
/* DRAM Base */
#define CONFIG_SYS_SDRAM_BASE 0x4000
--
2.1.1
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[U-Boot] [PATCH v2 8/8] ARM: sunxi: Add Ippo-q8h-v5 A23 tablet board defconfig
Ippo q8h is a series of A23 tablet boards. This defconfig is for v5 of these boards, though for u-boot purposes they are mostly the same. See: http://linux-sunxi.org/Ippo_q8h Signed-off-by: Chen-Yu Tsai w...@csie.org Acked-by: Ian Campbell i...@hellion.org.uk --- board/sunxi/MAINTAINERS| 5 + configs/Ippo_q8h_defconfig | 4 2 files changed, 9 insertions(+) create mode 100644 configs/Ippo_q8h_defconfig diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 7afe45e..febd126 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -50,3 +50,8 @@ COLOMBUS BOARD M: Maxime Ripard maxime.rip...@free-electrons.com S: Maintained F: configs/Colombus_defconfig + +IPPO-Q8H-V5 BOARD +M: CHen-Yu Tsai w...@csie.org +S: Maintained +F: configs/Ippo_q8h_v5_defconfig diff --git a/configs/Ippo_q8h_defconfig b/configs/Ippo_q8h_defconfig new file mode 100644 index 000..781f137 --- /dev/null +++ b/configs/Ippo_q8h_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS=IPPO_Q8H_V5,CONS_INDEX=5 +CONFIG_ARM=y +CONFIG_TARGET_SUN8I=y +CONFIG_DEFAULT_DEVICE_TREE=sun8i-a23-ippo-q8h-v5.dtb -- 2.1.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 6/8] ARM: sunxi: Allow specifying module in prcm apb0 init function
The prcm apb0 controls multiple modules. Allow specifying which
modules to enable clocks and de-assert resets so the function
can be reused.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Ian Campbell i...@hellion.org.uk
---
arch/arm/cpu/armv7/sunxi/prcm.c| 12 +++-
arch/arm/include/asm/arch-sunxi/prcm.h | 2 +-
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/prcm.c b/arch/arm/cpu/armv7/sunxi/prcm.c
index 7b3ee89..19b4938 100644
--- a/arch/arm/cpu/armv7/sunxi/prcm.c
+++ b/arch/arm/cpu/armv7/sunxi/prcm.c
@@ -21,13 +21,15 @@
#include asm/arch/prcm.h
#include asm/arch/sys_proto.h
-void prcm_init_apb0(void)
+/* APB0 clock gate and reset bit offsets are the same. */
+void prcm_apb0_enable(u32 flags)
{
struct sunxi_prcm_reg *prcm =
(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
- setbits_le32(prcm-apb0_gate, PRCM_APB0_GATE_P2WI |
- PRCM_APB0_GATE_PIO);
- setbits_le32(prcm-apb0_reset, PRCM_APB0_RESET_P2WI |
- PRCM_APB0_RESET_PIO);
+ /* open the clock for module */
+ setbits_le32(prcm-apb0_gate, flags);
+
+ /* deassert reset for module */
+ setbits_le32(prcm-apb0_reset, flags);
}
diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h
b/arch/arm/include/asm/arch-sunxi/prcm.h
index 1b40f09..3d3bfa6 100644
--- a/arch/arm/include/asm/arch-sunxi/prcm.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -233,6 +233,6 @@ struct sunxi_prcm_reg {
u32 dram_tst; /* 0x190 */
};
-void prcm_init_apb0(void);
+void prcm_apb0_enable(u32 flags);
#endif /* __ASSEMBLY__ */
#endif /* _PRCM_H */
--
2.1.1
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Re: [U-Boot] Mini Summit 2014 Followup / Transcript of Open Discussion
Hello Michal, Hi Detlev On 10/17/2014 05:02 PM, Detlev Zundel wrote: Hi, it was a pleasure for me to meet so many of you this Monday in Düsseldorf at the ELCE. As many as 17 current custodians and 2 prospective new custodians were present at the event: Hans de Goede - Sunxi Alexey Brodkin - ARC Marek Vasut - USB Scott Wood - NAND Joe Hershberger - Networking Anatolij Gustschin - Video Heiko Schocher - I2C Stefano Babic - ARM i.MX Stefan Roese - PowerPC 4xx, CFI flash Wolfgang Denk - PowerPC 8xx, 82xx, 85xx, 5xxx, 7xx, 74xx Lukasz Majewski - DFU, OneNAND Tom Rini - Master of the git tree Pantelis Antoniou - MMC Daniel Schwierzek - MIPS Masahiro Yamada - Uniphier, Kconfig / Kbuild Simon Glass - x86, Driver model, patman, buildman Nobuhiro Iwamatsu - SH architecture Vince Bridgers - SoCFPGA (soon) Przemyslaw Marczak - PMIC (soon) Not for full day but + Michal Simek - Microblaze architecture, ARM Zynq Thanks for adding yourself in - the names above were the custodians present during the introductory part so very likely you were not there from the beginning. [...] The page is topped with a picture of the participants of the discussion round in the evening. I started adding the names of the people that gave me explicit approval to do so but I would like to extend this list somewhat further. Whenever there is an NA without a question mark, then I know the name and will fill it in when I get the approval. If there is a question mark behind it then I'm unsure and would be glad to get some help _in addition_ to the approval ;) Feel free to identify me. Thanks, done. As promised, here are my notes that I took during the evening discussion - feel free to follow-up on individual items by cutting out the rest of the mail: 8-8- * Open Discussion ** ARM core vs ARM SoC custodianship Collection of patches should go to mainline in one bunch, rather than splitting them for every custodian repository. Individual custodians can ack parts of such a series. This should be the default - custodians should only pick up individual bits when those bits are pretty isolated. I don't think this was an agreement to be honest. I tried to use the word should and not must to allow for case by case decisions, but I think there was an agreement on the direction of the proposal. Merge early and merge often is golden rule for new SoCs. None is simply working on NAND when you don't have core SoC support or serial console. It means preferred way is to merge sensible patch series from start and then extend it to the drivers exactly how you do your SoC bringup. If you have bigger series touching some areas you need to get ack from custodian or you can be asked to split that series. I believe we are in sync here. Best wishes Detlev -- (7) It is always something (7a) (corollary). Good, Fast, Cheap: Pick any two (you can't have all three). -- The Twelve Networking Truths (RFC 1925) -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: d...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] git bisect failed
Hi Anatolij 2014-10-21 21:53 GMT+02:00 Anatolij Gustschin ag...@denx.de: Hi Christian, On Tue, 21 Oct 2014 13:43:36 +0200 Christian Gmeiner christian.gmei...@gmail.com wrote: Hi all. Finally I got basic board support for OT1200 into upstream, but the last released version fails to detect SPI flash (read only ff's). The good one is commit 39d0973300b83c08f3f5047245ebf1de883b31f2 and the bad one is c43fd23cf619856b0763a64a6a3bcf3663058c49 $ git log 39d097330..c43fd23c drivers/spi/mxc_spi.c An other git command detail I have learned today - thanks! commit 155fa9af95ac5be857a7327e7a968a296e60d4c8 Author: Nikita Kiryanov nik...@compulab.co.il Date: Wed Aug 20 15:08:50 2014 +0300 spi: mxc: fix sf probe when using mxc_spi MXC SPI driver has a feature whereas a GPIO line can be used to force CS high across multiple transactions. This is set up by embedding the GPIO information in the CS value: cs = (cs | gpio 8) This merge of cs and gpio data into one value breaks the sf probe command: if the use of gpio is required, invoking sf probe cs will not work, because the CS argument doesn't have the GPIO information in it. Instead, the user must use sf probe cs | gpio 8. For example, if bank 2 gpio 30 is used to force cs high on cs 0, bus 0, then instead of typing sf probe 0 the user now must type sf probe 15872. This is inconsistent with the description of the sf probe command, and forces the user to be aware of implementaiton details. Fix this by introducing a new board function: board_spi_cs_gpio(), which will accept a naked CS value, and provide the driver with the relevant GPIO, if one is necessary. Cc: Eric Nelson eric.nel...@boundarydevices.com Cc: Eric Benard e...@eukrea.com Cc: Fabio Estevam fabio.este...@freescale.com Cc: Tim Harvey thar...@gateworks.com Cc: Stefano Babic sba...@denx.de Cc: Tom Rini tr...@ti.com Cc: Marek Vasut ma...@denx.de Reviewed-by: Marek Vasut ma...@denx.de Signed-off-by: Nikita Kiryanov nik...@compulab.co.il Reviewed-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com Does it work if you revert 155fa9af ? That is the bad commit - I will send a patch to fix it at board level. Thanks a lot! -- Christian Gmeiner, MSc https://soundcloud.com/christian-gmeiner ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/7] dm: serial: use Driver Model for UniPhier serial driver
This commit converts UniPhier on-chip serial driver to driver model. Since UniPhier SoCs do not have Device Tree support, some board files should be added under arch/arm/cpu/armv7/uniphier/ph1-*/ directories. (Device Tree support for UniPhier platform is still under way.) Now the base address and master clock frequency are passed from platform data, so CONFIG_SYS_UNIPHIER_SERIAL_BASE* and CONFIG_SYS_UNIPHIER_UART_CLK should be removed. Tested on UniPhier PH1-LD4 ref board. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com --- arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile | 1 + arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c | 15 ++ arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile | 1 + arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c | 15 ++ arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile | 1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c | 15 ++ arch/arm/include/asm/arch-uniphier/platdevice.h | 24 +++ configs/ph1_ld4_defconfig | 2 + configs/ph1_pro4_defconfig| 2 + configs/ph1_sld8_defconfig| 2 + drivers/serial/serial_uniphier.c | 199 -- include/configs/ph1_ld4.h | 2 - include/configs/ph1_pro4.h| 2 - include/configs/ph1_sld8.h| 2 - include/configs/uniphier-common.h | 7 +- include/dm/platform_data/serial-uniphier.h| 18 ++ 16 files changed, 172 insertions(+), 136 deletions(-) create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c create mode 100644 arch/arm/include/asm/arch-uniphier/platdevice.h create mode 100644 include/dm/platform_data/serial-uniphier.h diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile index b385e19..781b511 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile @@ -3,6 +3,7 @@ # obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o +obj-y += platdevice.o obj-y += boot-mode.o obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \ sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c new file mode 100644 index 000..0047223 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada yamad...@jp.panasonic.com + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#include asm/arch/platdevice.h + +#define UART_MASTER_CLK36864000 + +SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK) +SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) +SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) +SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile index 712afd1..e11f4f6 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile @@ -3,6 +3,7 @@ # obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o +obj-y += platdevice.o obj-y += boot-mode.o obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o sbc_init.o \ sg_init.o pll_init.o clkrst_init.o pinctrl.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c new file mode 100644 index 000..6da921e --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada yamad...@jp.panasonic.com + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#include asm/arch/platdevice.h + +#define UART_MASTER_CLK73728000 + +SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK) +SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) +SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) +SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile index b385e19..781b511 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile @@ -3,6 +3,7 @@ # obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o +obj-y += platdevice.o obj-y += boot-mode.o obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \ sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c new file mode 100644 index 000..59d054a --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c @@
[U-Boot] [PATCH 1/7] dm: serial: fix a bug of console putc
Without this commit, functions such as printf(), puts() stop working
after the console is ready (= after GD_FLG_DEVINIT is set in
console_init_r() function).
The function serial_putc() is called to print a character before the
console is available, while serial_stub_putc() is used on the console.
The cause of the problem is that the error handling of ops-putc
handler is missing from serial_stub_putc(); it should behave
like serial_putc().
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
drivers/serial/serial-uclass.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 6dde4ea..163308b 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -127,8 +127,13 @@ void serial_stub_putc(struct stdio_dev *sdev, const char
ch)
{
struct udevice *dev = sdev-priv;
struct dm_serial_ops *ops = serial_get_ops(dev);
+ int err;
- ops-putc(dev, ch);
+ do {
+ err = ops-putc(cur_dev, ch);
+ } while (err == -EAGAIN);
+ if (ch == '\n')
+ serial_putc('\r');
}
void serial_stub_puts(struct stdio_dev *sdev, const char *str)
--
1.9.1
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[U-Boot] [PATCH 0/7] dm-serial: bug fix and refactoring and conversion of Uniphier serial
1/7: bug fix of console serial 2/7 - 3/7: cleanup 4/7: prepare some Kconfig entries 5/7 - 7/7: convert UniPhier serial driver and some cleanups Simon, As I promised before, here is the conversion of driver/serial/serial_uniphier.c into driver model. It has taken some time because I have had a hard time to find 1/7 bug. BTW, lowlevel-debug patches were really helpful to debug driver-model serial. http://patchwork.ozlabs.org/patch/384612/ http://patchwork.ozlabs.org/patch/384615/ http://patchwork.ozlabs.org/patch/384613/ http://patchwork.ozlabs.org/patch/384611/ It is generally very difficult to test our boards in situations where UART is not working. This series uses: http://patchwork.ozlabs.org/patch/397088/ as a prerequisite. Masahiro Yamada (7): dm: serial: fix a bug of console putc serial: add static directive to local functions dm: serial: consolidate common code dm: add entries to Kconfig dm: serial: use Driver Model for UniPhier serial driver serial: uniphier: move CONFIG_UNIPHIER_SERIAL to Kconfig serial: remove uniphier_serial_initialize() call arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile | 1 + arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c | 15 ++ arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile | 1 + arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c | 15 ++ arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile | 1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c | 15 ++ arch/arm/include/asm/arch-uniphier/platdevice.h | 24 +++ configs/ph1_ld4_defconfig | 3 + configs/ph1_pro4_defconfig| 3 + configs/ph1_sld8_defconfig| 3 + drivers/core/Kconfig | 6 + drivers/gpio/Kconfig | 6 + drivers/serial/Kconfig| 12 ++ drivers/serial/serial-uclass.c| 93 +- drivers/serial/serial.c | 2 - drivers/serial/serial_ns16550.c | 21 +-- drivers/serial/serial_s3c24x0.c | 10 +- drivers/serial/serial_uniphier.c | 199 -- include/common.h | 7 - include/configs/ph1_ld4.h | 6 +- include/configs/ph1_pro4.h| 6 +- include/configs/ph1_sld8.h| 6 +- include/configs/uniphier-common.h | 7 +- include/dm/platform_data/serial-uniphier.h| 18 ++ 24 files changed, 261 insertions(+), 219 deletions(-) create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c create mode 100644 arch/arm/include/asm/arch-uniphier/platdevice.h create mode 100644 include/dm/platform_data/serial-uniphier.h -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 7/7] serial: remove uniphier_serial_initialize() call
The UniPhier serial driver has been converted to driver model. Let's remove uniphier_serial_initialize() call from the old serial driver framework. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com --- drivers/serial/serial.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 82fbbd9..bbe60af 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -157,7 +157,6 @@ serial_initfunc(sh_serial_initialize); serial_initfunc(arm_dcc_initialize); serial_initfunc(mxs_auart_initialize); serial_initfunc(arc_serial_initialize); -serial_initfunc(uniphier_serial_initialize); /** * serial_register() - Register serial driver with serial driver core @@ -251,7 +250,6 @@ void serial_initialize(void) arm_dcc_initialize(); mxs_auart_initialize(); arc_serial_initialize(); - uniphier_serial_initialize(); serial_assign(default_serial_console()-name); } -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/7] dm: serial: consolidate common code
Before the console is available, the functions serial_*()
are used, while serial_stub_*() are called after the console
is ready.
Functions in those two groups are almost the same except
how udevice is passed; serial_*() pass cur_dev whereas
serial_stub_*() pass sdev-priv.
This commit merges the duplicated code; common lines are put into
_serlal_*().
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
drivers/serial/serial-uclass.c | 98 --
1 file changed, 47 insertions(+), 51 deletions(-)
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 163308b..6ee097d 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -71,52 +71,72 @@ void serial_initialize(void)
serial_find_console_or_panic();
}
-void serial_putc(char ch)
+static void _serial_putc(struct udevice *dev, const char ch)
{
- struct dm_serial_ops *ops = serial_get_ops(cur_dev);
- int err;
+ struct dm_serial_ops *ops = serial_get_ops(dev);
+ int res;
do {
- err = ops-putc(cur_dev, ch);
- } while (err == -EAGAIN);
+ res = ops-putc(cur_dev, ch);
+ } while (res == -EAGAIN);
if (ch == '\n')
- serial_putc('\r');
+ _serial_putc(dev, '\r');
}
-void serial_setbrg(void)
+static void _serial_puts(struct udevice *dev, const char *str)
{
- struct dm_serial_ops *ops = serial_get_ops(cur_dev);
-
- if (ops-setbrg)
- ops-setbrg(cur_dev, gd-baudrate);
+ while (*str)
+ _serial_putc(dev, *str++);
}
-void serial_puts(const char *str)
+static int _serial_getc(struct udevice *dev)
{
- while (*str)
- serial_putc(*str++);
+ struct dm_serial_ops *ops = serial_get_ops(dev);
+ int res;
+
+ do {
+ res = ops-getc(dev);
+ } while (res == -EAGAIN);
+
+ return res = 0 ? res : 0;
}
-int serial_tstc(void)
+static int _serial_tstc(struct udevice *dev)
{
- struct dm_serial_ops *ops = serial_get_ops(cur_dev);
+ struct dm_serial_ops *ops = serial_get_ops(dev);
if (ops-pending)
- return ops-pending(cur_dev, true);
+ return ops-pending(dev, true);
return 1;
}
+void serial_putc(char ch)
+{
+ _serial_putc(cur_dev, ch);
+}
+
+void serial_puts(const char *str)
+{
+ _serial_puts(cur_dev, str);
+}
+
int serial_getc(void)
{
- struct dm_serial_ops *ops = serial_get_ops(cur_dev);
- int err;
+ return _serial_getc(cur_dev);
+}
- do {
- err = ops-getc(cur_dev);
- } while (err == -EAGAIN);
+int serial_tstc(void)
+{
+ return _serial_tstc(cur_dev);
+}
+
+void serial_setbrg(void)
+{
+ struct dm_serial_ops *ops = serial_get_ops(cur_dev);
- return err = 0 ? err : 0;
+ if (ops-setbrg)
+ ops-setbrg(cur_dev, gd-baudrate);
}
void serial_stdio_init(void)
@@ -125,46 +145,22 @@ void serial_stdio_init(void)
void serial_stub_putc(struct stdio_dev *sdev, const char ch)
{
- struct udevice *dev = sdev-priv;
- struct dm_serial_ops *ops = serial_get_ops(dev);
- int err;
-
- do {
- err = ops-putc(cur_dev, ch);
- } while (err == -EAGAIN);
- if (ch == '\n')
- serial_putc('\r');
+ _serial_putc(sdev-priv, ch);
}
void serial_stub_puts(struct stdio_dev *sdev, const char *str)
{
- while (*str)
- serial_stub_putc(sdev, *str++);
+ _serial_puts(sdev-priv, str);
}
int serial_stub_getc(struct stdio_dev *sdev)
{
- struct udevice *dev = sdev-priv;
- struct dm_serial_ops *ops = serial_get_ops(dev);
-
- int err;
-
- do {
- err = ops-getc(dev);
- } while (err == -EAGAIN);
-
- return err = 0 ? err : 0;
+ return _serial_getc(sdev-priv);
}
int serial_stub_tstc(struct stdio_dev *sdev)
{
- struct udevice *dev = sdev-priv;
- struct dm_serial_ops *ops = serial_get_ops(dev);
-
- if (ops-pending)
- return ops-pending(dev, true);
-
- return 1;
+ return _serial_tstc(sdev-priv);
}
static int serial_post_probe(struct udevice *dev)
--
1.9.1
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[U-Boot] [PATCH 4/7] dm: add entries to Kconfig
Create entries of CONFIG_DM, CONFIG_DM_SERIAL, CONFIG_DM_GPIO. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com --- drivers/core/Kconfig | 6 ++ drivers/gpio/Kconfig | 6 ++ drivers/serial/Kconfig | 6 ++ 3 files changed, 18 insertions(+) diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index e69de29..d2799dc 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -0,0 +1,6 @@ +config DM + bool Enable Driver Model + depends on !SPL_BUILD + help + This config option enables Driver Model. + To use legacy drivers, say N. diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index e69de29..d21302f 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -0,0 +1,6 @@ +config DM_GPIO + bool Enable Driver Model for GPIO drivers + depends on DM + help + If you want to use driver model for GPIO drivers, say Y. + To use legacy GPIO drivers, say N. diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index e69de29..6a392ba 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -0,0 +1,6 @@ +config DM_SERIAL + bool Enable Driver Model for serial drivers + depends on DM + help + If you want to use driver model for serial drivers, say Y. + To use legacy serial drivers, say N. -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/7] serial: add static directive to local functions
The functions _serial_putc, _serial_putc_raw, _serial_puts,
_serial_getc, _serial_tstc, _serial_setbrg are defined and used
locally in each of serial_ns16550.c and serial_s3c24x0.c.
Add static directive to them and remove declarations from
include/common.h.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
drivers/serial/serial_ns16550.c | 21 +++--
drivers/serial/serial_s3c24x0.c | 10 +-
include/common.h| 7 ---
3 files changed, 12 insertions(+), 26 deletions(-)
diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index 632da4c..799ef6a 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -119,8 +119,7 @@ static NS16550_t serial_ports[6] = {
.puts = eserial##port##_puts, \
}
-void
-_serial_putc(const char c,const int port)
+static void _serial_putc(const char c, const int port)
{
if (c == '\n')
NS16550_putc(PORT, '\r');
@@ -128,35 +127,29 @@ _serial_putc(const char c,const int port)
NS16550_putc(PORT, c);
}
-void
-_serial_putc_raw(const char c,const int port)
+static void _serial_putc_raw(const char c, const int port)
{
NS16550_putc(PORT, c);
}
-void
-_serial_puts (const char *s,const int port)
+static void _serial_puts(const char *s, const int port)
{
while (*s) {
- _serial_putc (*s++,port);
+ _serial_putc(*s++, port);
}
}
-
-int
-_serial_getc(const int port)
+static int _serial_getc(const int port)
{
return NS16550_getc(PORT);
}
-int
-_serial_tstc(const int port)
+static int _serial_tstc(const int port)
{
return NS16550_tstc(PORT);
}
-void
-_serial_setbrg (const int port)
+static void _serial_setbrg(const int port)
{
int clock_divisor;
diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c
index c07f4c9..7afc504 100644
--- a/drivers/serial/serial_s3c24x0.c
+++ b/drivers/serial/serial_s3c24x0.c
@@ -69,7 +69,7 @@ DECLARE_GLOBAL_DATA_PTR;
static int hwflow;
#endif
-void _serial_setbrg(const int dev_index)
+static void _serial_setbrg(const int dev_index)
{
struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
unsigned int reg = 0;
@@ -131,7 +131,7 @@ static int serial_init_dev(const int dev_index)
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int _serial_getc(const int dev_index)
+static int _serial_getc(const int dev_index)
{
struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
@@ -181,7 +181,7 @@ void enable_putc(void)
/*
* Output a single byte to the serial port.
*/
-void _serial_putc(const char c, const int dev_index)
+static void _serial_putc(const char c, const int dev_index)
{
struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
#ifdef CONFIG_MODEM_SUPPORT
@@ -212,7 +212,7 @@ static inline void serial_putc_dev(unsigned int dev_index,
const char c)
/*
* Test whether a character is in the RX buffer
*/
-int _serial_tstc(const int dev_index)
+static int _serial_tstc(const int dev_index)
{
struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
@@ -224,7 +224,7 @@ static inline int serial_tstc_dev(unsigned int dev_index)
return _serial_tstc(dev_index);
}
-void _serial_puts(const char *s, const int dev_index)
+static void _serial_puts(const char *s, const int dev_index)
{
while (*s) {
_serial_putc(*s++, dev_index);
diff --git a/include/common.h b/include/common.h
index d5020c8..bcf6c7e 100644
--- a/include/common.h
+++ b/include/common.h
@@ -636,13 +636,6 @@ struct stdio_dev;
int serial_stub_getc(struct stdio_dev *sdev);
int serial_stub_tstc(struct stdio_dev *sdev);
-void _serial_setbrg (const int);
-void _serial_putc (const char, const int);
-void _serial_putc_raw(const char, const int);
-void _serial_puts (const char *, const int);
-int_serial_getc (const int);
-int_serial_tstc (const int);
-
/* $(CPU)/speed.c */
intget_clocks (void);
intget_clocks_866 (void);
--
1.9.1
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[U-Boot] [PATCH 6/7] serial: uniphier: move CONFIG_UNIPHIER_SERIAL to Kconfig
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com --- configs/ph1_ld4_defconfig | 1 + configs/ph1_pro4_defconfig | 1 + configs/ph1_sld8_defconfig | 1 + drivers/serial/Kconfig | 6 ++ include/configs/ph1_ld4.h | 4 +--- include/configs/ph1_pro4.h | 4 +--- include/configs/ph1_sld8.h | 4 +--- 7 files changed, 12 insertions(+), 9 deletions(-) diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig index c8404f8..e6aba42 100644 --- a/configs/ph1_ld4_defconfig +++ b/configs/ph1_ld4_defconfig @@ -7,4 +7,5 @@ CONFIG_NAND_DENALI=y CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 CONFIG_DM_SERIAL=y +CONFIG_UNIPHIER_SERIAL=y S:CONFIG_SPL_NAND_DENALI=y diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig index 5c051e3..334ec4b 100644 --- a/configs/ph1_pro4_defconfig +++ b/configs/ph1_pro4_defconfig @@ -7,4 +7,5 @@ CONFIG_NAND_DENALI=y CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 CONFIG_DM_SERIAL=y +CONFIG_UNIPHIER_SERIAL=y S:CONFIG_SPL_NAND_DENALI=y diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig index 2c636e6..4e8f354 100644 --- a/configs/ph1_sld8_defconfig +++ b/configs/ph1_sld8_defconfig @@ -7,4 +7,5 @@ CONFIG_NAND_DENALI=y CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 CONFIG_DM_SERIAL=y +CONFIG_UNIPHIER_SERIAL=y S:CONFIG_SPL_NAND_DENALI=y diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 6a392ba..a0b6e02 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -4,3 +4,9 @@ config DM_SERIAL help If you want to use driver model for serial drivers, say Y. To use legacy serial drivers, say N. + +config UNIPHIER_SERIAL + bool UniPhier on-chip UART support + depends on ARCH_UNIPHIER DM_SERIAL + help + Support for the on-chip UARTs on the Panasonic UniPhier platform. diff --git a/include/configs/ph1_ld4.h b/include/configs/ph1_ld4.h index a546865..005a853 100644 --- a/include/configs/ph1_ld4.h +++ b/include/configs/ph1_ld4.h @@ -28,9 +28,7 @@ * SoC UART : enable CONFIG_UNIPHIER_SERIAL * On-board UART: enable CONFIG_SYS_NS16550_SERIAL */ -#if 1 -#define CONFIG_UNIPHIER_SERIAL -#else +#if 0 #define CONFIG_SYS_NS16550_SERIAL #endif diff --git a/include/configs/ph1_pro4.h b/include/configs/ph1_pro4.h index 85c14ba..7dd6fd2 100644 --- a/include/configs/ph1_pro4.h +++ b/include/configs/ph1_pro4.h @@ -28,9 +28,7 @@ * SoC UART : enable CONFIG_UNIPHIER_SERIAL * On-board UART: enable CONFIG_SYS_NS16550_SERIAL */ -#if 1 -#define CONFIG_UNIPHIER_SERIAL -#else +#if 0 #define CONFIG_SYS_NS16550_SERIAL #endif diff --git a/include/configs/ph1_sld8.h b/include/configs/ph1_sld8.h index 41e2299..1062aac 100644 --- a/include/configs/ph1_sld8.h +++ b/include/configs/ph1_sld8.h @@ -28,9 +28,7 @@ * SoC UART : enable CONFIG_UNIPHIER_SERIAL * On-board UART: enable CONFIG_SYS_NS16550_SERIAL */ -#if 1 -#define CONFIG_UNIPHIER_SERIAL -#else +#if 0 #define CONFIG_SYS_NS16550_SERIAL #endif -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Revert sunxi: dram: Use divisor P=1 for PLL5
On Wed, 2014-10-22 at 10:35 +0200, Hans de Goede wrote: Hi, On 10/22/2014 10:14 AM, Ian Campbell wrote: On Tue, 2014-10-21 at 16:58 -0400, Tom Rini wrote: We should be doing things right, in mainline. To bring up a different example, on TI OMAP4 parts at least for a long time in order to use mainline U-Boot on older kernels you had to manually add CONFIG_SOMETHING_OR_ANOTHER to enable additional clocks/mux that the old kernels had incorrectly relied on U-Boot to set. If we must do strange things to support old and incorrect but in the wild kernels we need to (a) make it opt-in (easier now with Kconfig!) and (b) schedule a removal of the hack all the same. A Kconfig option does sound like a reasonable compromise. Ok, I will look into this, my plan for now is to call it OLD_KERNEL_COMPAT, so that if we come across more cases like this we've one config option for them, rather then a ton of small isolated config options. Is it particular to old kernels as such, or is it more to do with Allwinner SDK (and derived) kernels? Is it worth trying to keep workarounds for such kernels separated from workarounds for old mainline kernels? Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Revert sunxi: dram: Use divisor P=1 for PLL5
Hi, On 10/22/2014 11:19 AM, Ian Campbell wrote: On Wed, 2014-10-22 at 10:35 +0200, Hans de Goede wrote: Hi, On 10/22/2014 10:14 AM, Ian Campbell wrote: On Tue, 2014-10-21 at 16:58 -0400, Tom Rini wrote: We should be doing things right, in mainline. To bring up a different example, on TI OMAP4 parts at least for a long time in order to use mainline U-Boot on older kernels you had to manually add CONFIG_SOMETHING_OR_ANOTHER to enable additional clocks/mux that the old kernels had incorrectly relied on U-Boot to set. If we must do strange things to support old and incorrect but in the wild kernels we need to (a) make it opt-in (easier now with Kconfig!) and (b) schedule a removal of the hack all the same. A Kconfig option does sound like a reasonable compromise. Ok, I will look into this, my plan for now is to call it OLD_KERNEL_COMPAT, so that if we come across more cases like this we've one config option for them, rather then a ton of small isolated config options. Is it particular to old kernels as such, or is it more to do with Allwinner SDK (and derived) kernels? Is it worth trying to keep workarounds for such kernels separated from workarounds for old mainline kernels? AFAIK the first mainline kernels with sunxi support are recent enough that they don't need any workarounds. TBH I don't think differentiating between the 2 brings us anything. Regards, Hans ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] ot1200: fix sf detection
Commit 155fa9af95ac5be857a7327e7a968a296e60d4c8 changed the way
to define a GPIO line, which can be used to force CS high
across multiple transactions. In order to fix sf detection
change board code to make use of board_spi_cs_gpio(..).
Signed-off-by: Christian Gmeiner christian.gmei...@gmail.com
---
board/bachmann/ot1200/ot1200.c | 5 +
include/configs/ot1200.h | 2 +-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c
index 0d5ede5..2962e0c 100644
--- a/board/bachmann/ot1200/ot1200.c
+++ b/board/bachmann/ot1200/ot1200.c
@@ -98,6 +98,11 @@ static void setup_iomux_spi(void)
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
}
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 2 cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1;
+}
+
int board_early_init_f(void)
{
setup_iomux_uart();
diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
index 071880f..d7696bd 100644
--- a/include/configs/ot1200.h
+++ b/include/configs/ot1200.h
@@ -47,7 +47,7 @@
#define CONFIG_SPI_FLASH_SST
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 2
-#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(1, 3)8))
+#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 2500
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
--
1.9.3
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Re: [U-Boot] [PATCH] ot1200: fix sf detection
On 22/10/2014 11:29, Christian Gmeiner wrote:
Commit 155fa9af95ac5be857a7327e7a968a296e60d4c8 changed the way
to define a GPIO line, which can be used to force CS high
across multiple transactions. In order to fix sf detection
change board code to make use of board_spi_cs_gpio(..).
Signed-off-by: Christian Gmeiner christian.gmei...@gmail.com
---
board/bachmann/ot1200/ot1200.c | 5 +
include/configs/ot1200.h | 2 +-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c
index 0d5ede5..2962e0c 100644
--- a/board/bachmann/ot1200/ot1200.c
+++ b/board/bachmann/ot1200/ot1200.c
@@ -98,6 +98,11 @@ static void setup_iomux_spi(void)
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
}
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 2 cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1;
+}
+
int board_early_init_f(void)
{
setup_iomux_uart();
diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
index 071880f..d7696bd 100644
--- a/include/configs/ot1200.h
+++ b/include/configs/ot1200.h
@@ -47,7 +47,7 @@
#define CONFIG_SPI_FLASH_SST
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 2
-#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(1, 3)8))
+#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 2500
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
Acked-by: Stefano Babic sba...@denx.de
Best regards,
Stefano Babic
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=
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Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
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Re: [U-Boot] [PATCH] Revert sunxi: dram: Use divisor P=1 for PLL5
On Wed, 2014-10-22 at 11:26 +0200, Hans de Goede wrote: Hi, On 10/22/2014 11:19 AM, Ian Campbell wrote: On Wed, 2014-10-22 at 10:35 +0200, Hans de Goede wrote: Hi, On 10/22/2014 10:14 AM, Ian Campbell wrote: On Tue, 2014-10-21 at 16:58 -0400, Tom Rini wrote: We should be doing things right, in mainline. To bring up a different example, on TI OMAP4 parts at least for a long time in order to use mainline U-Boot on older kernels you had to manually add CONFIG_SOMETHING_OR_ANOTHER to enable additional clocks/mux that the old kernels had incorrectly relied on U-Boot to set. If we must do strange things to support old and incorrect but in the wild kernels we need to (a) make it opt-in (easier now with Kconfig!) and (b) schedule a removal of the hack all the same. A Kconfig option does sound like a reasonable compromise. Ok, I will look into this, my plan for now is to call it OLD_KERNEL_COMPAT, so that if we come across more cases like this we've one config option for them, rather then a ton of small isolated config options. Is it particular to old kernels as such, or is it more to do with Allwinner SDK (and derived) kernels? Is it worth trying to keep workarounds for such kernels separated from workarounds for old mainline kernels? AFAIK the first mainline kernels with sunxi support are recent enough that they don't need any workarounds. TBH I don't think differentiating between the 2 brings us anything. OK. Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 12/14] dm: omap: serial: Add driver model support
Hi Simon,
One minor comment from me.
On Mon, 22 Sep 2014 09:48:52 -0600
Simon Glass s...@chromium.org wrote:
+
+U_BOOT_DRIVER(serial_omap_ns16550) = {
+ .name = serial_omap,
+ .id = UCLASS_SERIAL,
+#ifdef CONFIG_OF_CONTROL
+ .of_match = omap_serial_ids,
+ .ofdata_to_platdata = omap_serial_ofdata_to_platdata,
+#endif
+ .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+ .priv_auto_alloc_size = sizeof(struct NS16550),
+ .probe = ns16550_serial_probe,
+ .ops= ns16550_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
U_BOOT_DRIVER(serial_omap_ns16550) = {
.name = serial_omap,
.id = UCLASS_SERIAL,
.of_match = of_match_ptr(omap_serial_ids),
.ofdata_to_platdata = of_match_ptr(omap_serial_ofdata_to_platdata),
.platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
.priv_auto_alloc_size = sizeof(struct NS16550),
.probe = ns16550_serial_probe,
.ops= ns16550_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
};
is cleaner
though you need to apply the following first:
http://patchwork.ozlabs.org/patch/397088/
Best Regards
Masahiro Yamada
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Re: [U-Boot] [PATCH v2 2/3] arm: relocate the exception vectors
Hi Albert, On Tue, 21 Oct 2014 16:05:25 +0200 Albert ARIBAUD albert.u.b...@aribaud.net wrote: Hi Masahiro, On Tue, 21 Oct 2014 14:41:14 +0900, Masahiro Yamada yamad...@jp.panasonic.com wrote: I have a question: You are covering only arm1176 and armv7. What about arm1136? I am not sure, but arm1136 and arm1176 both belong to ARMv6 generation? If so, does arm1136 have VBAR register, doesn't it? ARM1136 is ARMv6 but does not have VBAR. Its vectors can only be at 0x or 0x (see page 3-65 of the ARM1136 ARM r1p5, DDI0211K). Sorry, I did not know this. Just disregard my comment, please. Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/3] arm: relocate the exception vectors
Hi Albert, On Tue, 21 Oct 2014 15:54:51 +0200 Albert ARIBAUD albert.u.b...@aribaud.net wrote: Hi Georges, On Mon, 20 Oct 2014 23:08:30 +0200, Georges Savoundararadj savou...@gmail.com wrote: Hi Albert, Le 15/10/2014 00:11, Albert ARIBAUD a ecrit : Hi Georges, On Tue, 14 Oct 2014 22:02:00 +0200, Georges Savoundararadj savou...@gmail.com wrote: Hi Albert, Hi Masahiro, (putting Masahiro in Cc: just in case) As my issue is related to Kconfig, I would like you to give me your opinions. Le 11/10/2014 12:47, Albert ARIBAUD a ecrit : Hi Georges, On Sat, 27 Sep 2014 21:48:10 +0200, Georges Savoundararadj savou...@gmail.com wrote: This commit relocates the exception vectors. As ARM1176 and ARMv7 have the security extensions, it uses VBAR. For the other ARM processors, it copies the relocated exception vectors to the correct address: 0x or 0x. Signed-off-by: Georges Savoundararadj savou...@gmail.com Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Warren twar...@nvidia.com --- This patch needs some tests because it impacts many boards. I have tested it with my raspberry pi in the two cases: using VBAR and using the copied exception vectors. Changes in v2: - Relocate exception vectors also on processors which do not support security extensions - Reword the commit message arch/arm/cpu/armv7/start.S | 6 -- arch/arm/lib/relocate.S| 30 ++ 2 files changed, 30 insertions(+), 6 deletions(-) diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index fedd7c8..fdc05b9 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -81,12 +81,6 @@ ENTRY(c_runtime_cpu_setup) mcr p15, 0, r0, c7, c10, 4 @ DSB mcr p15, 0, r0, c7, c5, 4 @ ISB #endif -/* - * Move vector table - */ - /* Set vector address in CP15 VBAR register */ - ldr r0, =_start - mcr p15, 0, r0, c12, c0, 0 @Set VBAR bx lr diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S index 8035251..88a478e 100644 --- a/arch/arm/lib/relocate.S +++ b/arch/arm/lib/relocate.S @@ -6,6 +6,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include asm-offsets.h +#include config.h #include linux/linkage.h /* @@ -52,6 +54,34 @@ fixnext: cmp r2, r3 blo fixloop + /* + * Relocate the exception vectors + */ +#if (defined(CONFIG_ARM1176) || defined(CONFIG_ARMV7)) I would prefer a single CONFIG_HAS_VBAR symbol defined through Kconfig. 1) Actually, there is no Kconfig entry such as config ARM1176 nor config ARMV7 in U-Boot, unlike in Linux (arch/arm/mm/Kconfig). If there were such entries, we would simply do like the following (in arch/arm/Kconfig): config HAS_VBAR bool config ARM1176 select HAS_VBAR config ARMV7 select HAS_VBAR Should we go in this direction? It is the cleanest way to use Kconfig but it requires some work in order to convert all #define CONFIG_cpu into Kconfig entries. 2) Otherwise, we can insert a select HAS_VBAR in all boards that have a ARM1176 or a ARMv7 processor in arch/arm/Kconfig. It is not logical but this is what has been done with the Kconfig entry ARM64. And, it does not require much change. 3) The last thing we can do is as follows: config HAS_VBAR bool depends on SYS_CPU = arm1176 || SYS_CPU = armv7 default y CONFIG_HAS_VBAR will be defined if SYS_CPU are arm1176 or armv7. It does not require much change as well but, I think, it is bad code. What do you think is the best way to introduce CONFIG_HAS_VBAR symbol? (1, 2 or 3) I believe you have already sorted the options in order of decreasing 'quality' -- 1 being the best option, and 3 being the worst... Indeed option 1 would be the best and cleanest, and it could possibly open the way for other per-CPU options. We could try and limit the effort to converting only ARM1176 and ARMV7 and leaving other CONFIG_cpu #define'd until some later point in the future, but experience shows that such half-hearted attempts are never completed. Amicalement, I am currently trying to implement solution 1. only for ARM1176 and ARMV7 but I wonder if this work worth the effort just for one CPU feature. Do you expect more CPU feature like HAS_VBAR coming in the future? I add the following lines in arch/arm/Kconfig: config HAS_VBAR bool config ARM1176 bool select HAS_VBAR config ARMV7 bool select HAS_VBAR config SYS_CPU default
[U-Boot] [PATCH] ot1200: add sata support
One of the possible boot devices can be sata. Signed-off-by: Christian Gmeiner christian.gmei...@gmail.com --- board/bachmann/ot1200/ot1200.c | 5 + 1 file changed, 5 insertions(+) diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c index 0d5ede5..6d51231 100644 --- a/board/bachmann/ot1200/ot1200.c +++ b/board/bachmann/ot1200/ot1200.c @@ -12,6 +12,7 @@ #include malloc.h #include asm/arch/mx6-pins.h #include asm/imx-common/iomux-v3.h +#include asm/imx-common/sata.h #include asm/imx-common/mxc_i2c.h #include asm/imx-common/boot_mode.h #include asm/arch/crm_regs.h @@ -225,6 +226,10 @@ int board_init(void) /* enable ecspi3 clocks */ enable_cspi_clock(1, 2); +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif + return 0; } -- 1.9.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] ARM: at91 series: convert to generic board
Signed-off-by: Bo Shen voice.s...@atmel.com --- include/configs/at91rm9200ek.h | 2 ++ include/configs/at91sam9260ek.h | 2 ++ include/configs/at91sam9261ek.h | 2 ++ 3 files changed, 6 insertions(+) diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h index a30c016..735c82a 100644 --- a/include/configs/at91rm9200ek.h +++ b/include/configs/at91rm9200ek.h @@ -61,6 +61,8 @@ #define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD + /* * Memory Configuration */ diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 73917b0..0f6ef31 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -48,6 +48,8 @@ #define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD + /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY/* required until (g)pio is fixed */ #define CONFIG_AT91_GPIO diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 226f8c1..2cc0b8b 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -33,6 +33,8 @@ #define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_ATMEL_LEGACY #define CONFIG_SYS_TEXT_BASE 0x21f0 -- 2.1.0.24.g4109c28 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ot1200: fix sf detection
Hi all, On Wed, 22 Oct 2014 11:29:51 +0200 Christian Gmeiner christian.gmei...@gmail.com wrote: Commit 155fa9af95ac5be857a7327e7a968a296e60d4c8 changed the way to define a GPIO line, which can be used to force CS high across multiple transactions. In order to fix sf detection change board code to make use of board_spi_cs_gpio(..). Signed-off-by: Christian Gmeiner christian.gmei...@gmail.com --- board/bachmann/ot1200/ot1200.c | 5 + include/configs/ot1200.h | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) There are another two board that might be affected: $ grep --exclude=ot1200.h -r SF_DEFAULT_CS include/configs/ | grep IMX_GPIO_NR include/configs/aristainetos.h:#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 20)8)) include/configs/tqma6.h:#define CONFIG_SF_DEFAULT_CS(0 | (IMX_GPIO_NR(3, 19) 8)) So, I'm CC'ing board maintainers, please test/fix them too. Thanks! Anatolij ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 03/20] arm: marvell: Move arch-kirkwood/spi.h to arch-mvebu/spi.h
This move makes it possible to use this kirkwood SPI driver from other
MVEBU platforms as well. This will be used by the upcoming Armada XP
support.
Signed-off-by: Stefan Roese s...@denx.de
Reviewed-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Tested-by: Luka Perkov l...@openwrt.org
Acked-by: Prafulla Wadaskar prafu...@marvell.com
---
Changes in v4: None
Changes in v3:
- Added Acked-by from Prafulla to all Kirkwood patches
- Added Tested-by from Luka
- Added Reviewed-by from Jagannadha
Changes in v2: None
arch/arm/include/asm/{arch-kirkwood = arch-mvebu}/spi.h | 0
drivers/spi/kirkwood_spi.c | 2 +-
2 files changed, 1 insertion(+), 1 deletion(-)
rename arch/arm/include/asm/{arch-kirkwood = arch-mvebu}/spi.h (100%)
diff --git a/arch/arm/include/asm/arch-kirkwood/spi.h
b/arch/arm/include/asm/arch-mvebu/spi.h
similarity index 100%
rename from arch/arm/include/asm/arch-kirkwood/spi.h
rename to arch/arm/include/asm/arch-mvebu/spi.h
diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
index de0e914..9710f12 100644
--- a/drivers/spi/kirkwood_spi.c
+++ b/drivers/spi/kirkwood_spi.c
@@ -13,8 +13,8 @@
#include spi.h
#include asm/io.h
#include asm/arch/soc.h
-#include asm/arch/spi.h
#include asm/arch/mpp.h
+#include asm/arch-mvebu/spi.h
static struct kwspi_registers *spireg = (struct kwspi_registers *)KW_SPI_BASE;
--
2.1.2
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[U-Boot] [PATCH v4 0/20] Add Marvell Armada XP MV78460 SoC support
This patch series adds support for the Marvell Armada XP SoC's. Specifically the MV78460. Basic support for the db-78460-bp evaluation board is added. Supporting the following interfaces: - UART - SPI (including SPI NOR flash) - I2C - Ethernet (neta) While doing this port, I tried to consolidate common Marvell code into the arch/arm/mvebu-common directory. This directory should be used to collect more common code for the MVEBU SoC's (Dove, Kirkwood, Armada 370, Armada 380, Armada XP). I started with Kirkwood and some of its interfaces. Dove is definitely a candidate to move some of its code into thise directory as well. Because of the renaming of some functions from kirkwood to mvebu (to make them better usable on other MVEBU SoCs), this patch series not only touches the ARM SoC specific files (in arch/arm/...). But also some device drivers (e.g. SPI, I2C). Separating these driver specific patches into different patches that are not depending on this ARM patch series seems hard if not impossible. Thats why I would really like to get this patch series to get applied completely be one custodian. Not sure if this could / should go through Tom directly? Only if all the subsystem custodians have given their Acked-by ... of course. Testing on Kirkwood based boards would be greatly appreciated. So anyone with access to some of those board, please give this patch series a try. I really hope that I didn't break anything while merging some of the code into the common mvebu directory. Please note that this Armada XP port still requires the Binary Header (bin_hdr) from the Marvell U-Boot tree to be included as a binary blob into the resulting image (u-boot.kwb) that can be booted by the MVEBU BootROM. This binary bin_hdr is usually responsible for the DDR3 controller configuration and the DDR3 training. One way to extract this bin_hdr binary from an existing Marvell boot image right now is to use the kwbimage tool from Barebox. Please refer to the documentation thats available there for more details. v4 status: Some SPI patches are now in mainline pulled by Jagan. Some others are still pending. But this is because of their dependancy on other platform files. As its mostly remaning stuff (kirkwood - mvebu) to make things more generic. Tom, how do you feel about this patch series? Its been abround for quite some time now. And I would really like to see it applied to mainline. Prafulla has acked all Kirkwood related patches. Heiko the I2C patch. Jagan the I2C stuff. If you feel its okay, then please pull the complete patch-series directly. Or should I prepare a git branch for you to pull from? Thanks, Stefan Changes in v4: - Unused SDRAM windows are now disabled in update_sdram_window_sizes() Changes in v3: - Added Acked-by from Prafulla to all Kirkwood patches - Added Tested-by from Luka - Added Acked-by from Prafulla to all Kirkwood patches - Added Tested-by from Luka - Added newly introduced driver drivers/mmc/mvebu_mmc.c - Added Acked-by from Prafulla to all Kirkwood patches - Added Tested-by from Luka - Added Reviewed-by from Jagannadha - Added Acked-by from Prafulla to all Kirkwood patches - Added Tested-by from Luka - Added Tested-by from Luka - Added Acked-by from Prafulla to all Kirkwood patches - Added Tested-by from Luka - Added Reviewed-by from Jagannadha - Added Acked-by from Prafulla to all Kirkwood patches - Added Tested-by from Luka - Added Acked-by from Prafulla to all Kirkwood patches - Added Tested-by from Luka - Added Reviewed-by from Jagannadha - Added Acked-by from Prafulla to all Kirkwood patches - Added Tested-by from Luka - Added Tested-by from Luka - Added Tested-by from Luka - Added Acked-by from Heiko - Added Tested-by from Luka - Added Tested-by from Luka - Rebased on current top-of-tree (git ID a1263632) - Rebased on current top-of-tree (git ID a1263632) Changes in v2: - Fixed issue in mbus_dt_setup_win() to also assign remappable windows - Made mbus_dt_setup_win() non-static, so that it can be called from other files for board specific mbus window configuration - Renamed target from db-78460-bp to db-mv784mp-gp as this matches the real eval board name - Added optional '-a' parameter to use the timings for Armada XP, as they are incompatibel with the currently used ones for Kirkwood (etc). - Rebased on latest U-Boot version already including the Kconfig support switch. - Removed patch [PATCH v1 21/25] arm: kirkwood: Use mvebu new common mbus API as this breaks Kirkwood booting. This needs to be resolved at some time, but I don't have access to a Kirkwood based board with JTAG BDI access to debug it right now. Till somebody fixes this issue, lets just remove it from this series for now. - Added basic support for the maxBCM MV78460 based board Stefan Roese (20): arm: kirkwood: Move some SoC files into new arch/arm/mvebu-common arm: marvell: Move arch/kirkwood.h to arch/soc.h arm: marvell: Move arch-kirkwood/spi.h to arch-mvebu/spi.h arm: marvell: Rework
[U-Boot] [PATCH v4 07/20] arm: marvell: Extract kirkwood gpio functions into new common file gpio.c
This makes is possible to use those gpio functions from other MVEBU SoC's as
well.
Signed-off-by: Stefan Roese s...@denx.de
Tested-by: Luka Perkov l...@openwrt.org
Acked-by: Prafulla Wadaskar prafu...@marvell.com
---
Changes in v4: None
Changes in v3:
- Added Acked-by from Prafulla to all Kirkwood patches
- Added Tested-by from Luka
Changes in v2: None
arch/arm/cpu/arm926ejs/kirkwood/cpu.c | 17 --
arch/arm/include/asm/arch-kirkwood/cpu.h| 2 +-
arch/arm/include/asm/arch-kirkwood/gpio.h | 16 ++---
arch/arm/include/asm/arch-kirkwood/soc.h| 4 ++--
arch/arm/mvebu-common/Makefile | 1 +
arch/arm/mvebu-common/gpio.c| 30 +
board/LaCie/net2big_v2/net2big_v2.c | 4 ++--
board/LaCie/netspace_v2/netspace_v2.c | 4 ++--
board/LaCie/wireless_space/wireless_space.c | 4 ++--
board/Marvell/dreamplug/dreamplug.c | 6 ++---
board/Marvell/guruplug/guruplug.c | 6 ++---
board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c | 6 ++---
board/Marvell/openrd/openrd.c | 6 ++---
board/Marvell/rd6281a/rd6281a.c | 6 ++---
board/Marvell/sheevaplug/sheevaplug.c | 6 ++---
board/Seagate/dockstar/dockstar.c | 8 +++
board/Seagate/goflexhome/goflexhome.c | 8 +++
board/buffalo/lsxl/lsxl.c | 6 ++---
board/cloudengines/pogo_e02/pogo_e02.c | 6 ++---
board/d-link/dns325/dns325.c| 4 ++--
board/iomega/iconnect/iconnect.c| 6 ++---
board/karo/tk71/tk71.c | 6 ++---
board/keymile/km_arm/km_arm.c | 4 ++--
board/raidsonic/ib62x0/ib62x0.c | 6 ++---
24 files changed, 93 insertions(+), 79 deletions(-)
create mode 100644 arch/arm/mvebu-common/gpio.c
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
index 75d3799..ea835fc 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
@@ -140,23 +140,6 @@ int kw_config_adr_windows(void)
}
/*
- * kw_config_gpio - GPIO configuration
- */
-void kw_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, u32 gpp0_oe, u32 gpp1_oe)
-{
- struct kwgpio_registers *gpio0reg =
- (struct kwgpio_registers *)KW_GPIO0_BASE;
- struct kwgpio_registers *gpio1reg =
- (struct kwgpio_registers *)KW_GPIO1_BASE;
-
- /* Init GPIOS to default values as per board requirement */
- writel(gpp0_oe_val, gpio0reg-dout);
- writel(gpp1_oe_val, gpio1reg-dout);
- writel(gpp0_oe, gpio0reg-oe);
- writel(gpp1_oe, gpio1reg-oe);
-}
-
-/*
* kw_config_mpp - Multi-Purpose Pins Functionality configuration
*
* Each MPP can be configured to different functionality through
diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h
b/arch/arm/include/asm/arch-kirkwood/cpu.h
index 97daa40..5900a15 100644
--- a/arch/arm/include/asm/arch-kirkwood/cpu.h
+++ b/arch/arm/include/asm/arch-kirkwood/cpu.h
@@ -144,7 +144,7 @@ unsigned int kw_sdram_bar(enum memory_bank bank);
unsigned int kw_sdram_bs(enum memory_bank bank);
void kw_sdram_size_adjust(enum memory_bank bank);
int kw_config_adr_windows(void);
-void kw_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
+void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
unsigned int gpp0_oe, unsigned int gpp1_oe);
int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15,
unsigned int mpp16_23, unsigned int mpp24_31,
diff --git a/arch/arm/include/asm/arch-kirkwood/gpio.h
b/arch/arm/include/asm/arch-kirkwood/gpio.h
index 5f4d786..aa8c5da 100644
--- a/arch/arm/include/asm/arch-kirkwood/gpio.h
+++ b/arch/arm/include/asm/arch-kirkwood/gpio.h
@@ -21,14 +21,14 @@
#define GPIO_MAX 50
#define GPIO_OFF(pin) (((pin) 5) ? 0x0040 : 0x)
-#define GPIO_OUT(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x00)
-#define GPIO_IO_CONF(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x04)
-#define GPIO_BLINK_EN(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x08)
-#define GPIO_IN_POL(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x0c)
-#define GPIO_DATA_IN(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x10)
-#define GPIO_EDGE_CAUSE(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x14)
-#define GPIO_EDGE_MASK(pin)(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x18)
-#define GPIO_LEVEL_MASK(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x1c)
+#define GPIO_OUT(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x00)
+#define GPIO_IO_CONF(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x04)
+#define GPIO_BLINK_EN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x08)
+#define GPIO_IN_POL(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x0c)
+#define GPIO_DATA_IN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x10)
+#define GPIO_EDGE_CAUSE(pin)
[U-Boot] [PATCH v4 05/20] arm: mvebu: Add common mbus functions to use on Marvell SoCs
These mbus functions are ported from Barebox. The Barebox version is
ported from Linux. These functions will be first used by the upcoming
Armada XP support. Later other Marvell SoC's will be adopted to use
these functions as well (Kirkwood, Orion).
Signed-off-by: Stefan Roese s...@denx.de
Tested-by: Luka Perkov l...@openwrt.org
---
Changes in v4: None
Changes in v3:
- Added Tested-by from Luka
Changes in v2:
- Fixed issue in mbus_dt_setup_win() to also assign remappable windows
- Made mbus_dt_setup_win() non-static, so that it can be called from
other files for board specific mbus window configuration
arch/arm/mvebu-common/Makefile | 1 +
arch/arm/mvebu-common/mbus.c | 471 +
include/linux/mbus.h | 73 +++
3 files changed, 545 insertions(+)
create mode 100644 arch/arm/mvebu-common/mbus.c
create mode 100644 include/linux/mbus.h
diff --git a/arch/arm/mvebu-common/Makefile b/arch/arm/mvebu-common/Makefile
index 4d20d2c..391a125 100644
--- a/arch/arm/mvebu-common/Makefile
+++ b/arch/arm/mvebu-common/Makefile
@@ -7,4 +7,5 @@
#
obj-y = dram.o
+obj-$(CONFIG_ARMADA_XP) += mbus.o
obj-y += timer.o
diff --git a/arch/arm/mvebu-common/mbus.c b/arch/arm/mvebu-common/mbus.c
new file mode 100644
index 000..05c9ef2
--- /dev/null
+++ b/arch/arm/mvebu-common/mbus.c
@@ -0,0 +1,471 @@
+/*
+ * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
+ * 370/XP, Dove, Orion5x and MV78xx0)
+ *
+ * Ported from the Barebox version to U-Boot by:
+ * Stefan Roese s...@denx.de
+ *
+ * The Barebox version is:
+ * Sebastian Hesselbarth sebastian.hesselba...@gmail.com
+ *
+ * based on mbus driver from Linux
+ * (C) Copyright 2008 Marvell Semiconductor
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ *
+ * The Marvell EBU SoCs have a configurable physical address space:
+ * the physical address at which certain devices (PCIe, NOR, NAND,
+ * etc.) sit can be configured. The configuration takes place through
+ * two sets of registers:
+ *
+ * - One to configure the access of the CPU to the devices. Depending
+ * on the families, there are between 8 and 20 configurable windows,
+ * each can be use to create a physical memory window that maps to a
+ * specific device. Devices are identified by a tuple (target,
+ * attribute).
+ *
+ * - One to configure the access to the CPU to the SDRAM. There are
+ * either 2 (for Dove) or 4 (for other families) windows to map the
+ * SDRAM into the physical address space.
+ *
+ * This driver:
+ *
+ * - Reads out the SDRAM address decoding windows at initialization
+ * time, and fills the mbus_dram_info structure with these
+ * informations. The exported function mv_mbus_dram_info() allow
+ * device drivers to get those informations related to the SDRAM
+ * address decoding windows. This is because devices also have their
+ * own windows (configured through registers that are part of each
+ * device register space), and therefore the drivers for Marvell
+ * devices have to configure those device - SDRAM windows to ensure
+ * that DMA works properly.
+ *
+ * - Provides an API for platform code or device drivers to
+ * dynamically add or remove address decoding windows for the CPU -
+ * device accesses. This API is mvebu_mbus_add_window_by_id(),
+ * mvebu_mbus_add_window_remap_by_id() and
+ * mvebu_mbus_del_window().
+ */
+
+#include common.h
+#include asm/errno.h
+#include asm/io.h
+#include asm/arch/cpu.h
+#include asm/arch/soc.h
+#include linux/mbus.h
+
+#define BIT(nr)(1UL (nr))
+
+/* DDR target is the same on all platforms */
+#define TARGET_DDR 0
+
+/* CPU Address Decode Windows registers */
+#define WIN_CTRL_OFF 0x
+#define WIN_CTRL_ENABLE BIT(0)
+#define WIN_CTRL_TGT_MASK 0xf0
+#define WIN_CTRL_TGT_SHIFT4
+#define WIN_CTRL_ATTR_MASK0xff00
+#define WIN_CTRL_ATTR_SHIFT 8
+#define WIN_CTRL_SIZE_MASK0x
+#define WIN_CTRL_SIZE_SHIFT 16
+#define WIN_BASE_OFF 0x0004
+#define WIN_BASE_LOW 0x
+#define WIN_BASE_HIGH 0xf
+#define WIN_REMAP_LO_OFF 0x0008
+#define WIN_REMAP_LOW 0x
+#define WIN_REMAP_HI_OFF 0x000c
+
+#define ATTR_HW_COHERENCY (0x1 4)
+
+#define DDR_BASE_CS_OFF(n) (0x + ((n) 3))
+#define DDR_BASE_CS_HIGH_MASK 0xf
+#define DDR_BASE_CS_LOW_MASK 0xff00
+#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) 3))
+#define DDR_SIZE_ENABLED BIT(0)
+#define DDR_SIZE_CS_MASK 0x1c
+#define DDR_SIZE_CS_SHIFT 2
+#define DDR_SIZE_MASK 0xff00
+
+#define DOVE_DDR_BASE_CS_OFF(n) ((n) 4)
+
+struct mvebu_mbus_state;
+
+struct mvebu_mbus_soc_data {
+ unsigned int num_wins;
+ unsigned int num_remappable_wins;
+ unsigned int (*win_cfg_offset)(const int win);
+ void (*setup_cpu_target)(struct mvebu_mbus_state *s);
+};
+
+struct mvebu_mbus_state mbus_state
+
[U-Boot] [PATCH v4 18/20] tools: Compile kwboot for Marvell Armada XP as those SoCs are now supported
Signed-off-by: Stefan Roese s...@denx.de Tested-by: Luka Perkov l...@openwrt.org --- Changes in v4: None Changes in v3: None Changes in v2: None tools/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/Makefile b/tools/Makefile index 2b05b20..3b95964 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -140,6 +140,7 @@ ubsha1-objs := os_support.o ubsha1.o lib/sha1.o HOSTCFLAGS_ubsha1.o := -pedantic hostprogs-$(CONFIG_KIRKWOOD) += kwboot +hostprogs-$(CONFIG_ARMADA_XP) += kwboot hostprogs-y += proftool hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela -- 2.1.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 17/20] tools/kwboot: Sync with latest barebox version to support Armada XP
The barebox version of the kwboot tool has evolved a bit. To support
Armada XP and Dove. Additionally a few minor fixes have been applied.
So lets sync with the latest barebox version.
Please note that the main difference between both versions now is, that
the U-Boot version still supports the -p option, to dynamically patch
an image for UART boot mode. I didn't test it now though.
Signed-off-by: Stefan Roese s...@denx.de
Tested-by: Luka Perkov l...@openwrt.org
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Added optional '-a' parameter to use the timings for Armada XP, as they
are incompatibel with the currently used ones for Kirkwood (etc).
tools/kwboot.c | 111 +
1 file changed, 97 insertions(+), 14 deletions(-)
diff --git a/tools/kwboot.c b/tools/kwboot.c
index e773f01..1368b4c 100644
--- a/tools/kwboot.c
+++ b/tools/kwboot.c
@@ -1,5 +1,6 @@
/*
- * Boot a Marvell Kirkwood SoC, with Xmodem over UART0.
+ * Boot a Marvell SoC, with Xmodem over UART0.
+ * supports Kirkwood, Dove, Armada 370, Armada XP
*
* (c) 2012 Daniel Stodden daniel.stod...@gmail.com
*
@@ -37,9 +38,18 @@ static unsigned char kwboot_msg_boot[] = {
0xBB, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77
};
+static unsigned char kwboot_msg_debug[] = {
+ 0xDD, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77
+};
+
+/* Defines known to work on Kirkwood */
#define KWBOOT_MSG_REQ_DELAY 10 /* ms */
#define KWBOOT_MSG_RSP_TIMEO 50 /* ms */
+/* Defines known to work on Armada XP */
+#define KWBOOT_MSG_REQ_DELAY_AXP 1000 /* ms */
+#define KWBOOT_MSG_RSP_TIMEO_AXP 1000 /* ms */
+
/*
* Xmodem Transfers
*/
@@ -62,6 +72,9 @@ struct kwboot_block {
static int kwboot_verbose;
+static int msg_req_delay = KWBOOT_MSG_REQ_DELAY;
+static int msg_rsp_timeo = KWBOOT_MSG_RSP_TIMEO;
+
static void
kwboot_printv(const char *fmt, ...)
{
@@ -184,6 +197,9 @@ kwboot_tty_send(int fd, const void *buf, size_t len)
int rc;
ssize_t n;
+ if (!buf)
+ return 0;
+
rc = -1;
do {
@@ -268,7 +284,10 @@ kwboot_bootmsg(int tty, void *msg)
int rc;
char c;
- kwboot_printv(Sending boot message. Please reboot the target...);
+ if (msg == NULL)
+ kwboot_printv(Please reboot the target into UART boot
mode...);
+ else
+ kwboot_printv(Sending boot message. Please reboot the
target...);
do {
rc = tcflush(tty, TCIOFLUSH);
@@ -277,11 +296,11 @@ kwboot_bootmsg(int tty, void *msg)
rc = kwboot_tty_send(tty, msg, 8);
if (rc) {
- usleep(KWBOOT_MSG_REQ_DELAY * 1000);
+ usleep(msg_req_delay * 1000);
continue;
}
- rc = kwboot_tty_recv(tty, c, 1, KWBOOT_MSG_RSP_TIMEO);
+ rc = kwboot_tty_recv(tty, c, 1, msg_rsp_timeo);
kwboot_spinner();
@@ -293,6 +312,37 @@ kwboot_bootmsg(int tty, void *msg)
}
static int
+kwboot_debugmsg(int tty, void *msg)
+{
+ int rc;
+
+ kwboot_printv(Sending debug message. Please reboot the target...);
+
+ do {
+ char buf[16];
+
+ rc = tcflush(tty, TCIOFLUSH);
+ if (rc)
+ break;
+
+ rc = kwboot_tty_send(tty, msg, 8);
+ if (rc) {
+ usleep(msg_req_delay * 1000);
+ continue;
+ }
+
+ rc = kwboot_tty_recv(tty, buf, 16, msg_rsp_timeo);
+
+ kwboot_spinner();
+
+ } while (rc);
+
+ kwboot_printv(\n);
+
+ return rc;
+}
+
+static int
kwboot_xm_makeblock(struct kwboot_block *block, const void *data,
size_t size, int pnum)
{
@@ -300,6 +350,7 @@ kwboot_xm_makeblock(struct kwboot_block *block, const void
*data,
size_t n;
int i;
+ block-soh = SOH;
block-pnum = pnum;
block-_pnum = ~block-pnum;
@@ -326,9 +377,15 @@ kwboot_xm_sendblock(int fd, struct kwboot_block *block)
if (rc)
break;
- rc = kwboot_tty_recv(fd, c, 1, KWBOOT_BLK_RSP_TIMEO);
- if (rc)
- break;
+ do {
+ rc = kwboot_tty_recv(fd, c, 1, KWBOOT_BLK_RSP_TIMEO);
+ if (rc)
+ break;
+
+ if (c != ACK c != NAK c != CAN)
+ printf(%c, c);
+
+ } while (c != ACK c != NAK c != CAN);
if (c != ACK)
kwboot_progress(-1, '+');
@@ -511,7 +568,6 @@ kwboot_mmap_image(const char *path, size_t *size, int prot)
void *img;
rc = -1;
- fd = -1;
img = NULL;
fd = open(path, O_RDONLY);
@@ -601,11 +657,16 @@ static void
[U-Boot] [PATCH v4 04/20] arm: marvell: Rework timer.c to make it usable for other MVEBU platforms
This patch does the following:
- Rename defines and registers to not use kirkwood
- Remove unused defines
- Use clrsetbits() accessor functions
- Coding style cleanup
- Clear 25MHZ bit in timer controller register init for Armada XP
There is no functional change for kirkwood. At least not intentionally.
This will be used by the upcoming Armada XP support.
Signed-off-by: Stefan Roese s...@denx.de
Tested-by: Luka Perkov l...@openwrt.org
Acked-by: Prafulla Wadaskar prafu...@marvell.com
---
Changes in v4: None
Changes in v3:
- Added Acked-by from Prafulla to all Kirkwood patches
- Added Tested-by from Luka
Changes in v2: None
arch/arm/include/asm/arch-kirkwood/soc.h | 2 +-
arch/arm/mvebu-common/timer.c| 90 ++--
2 files changed, 41 insertions(+), 51 deletions(-)
diff --git a/arch/arm/include/asm/arch-kirkwood/soc.h
b/arch/arm/include/asm/arch-kirkwood/soc.h
index 3ea51d7..29fb2d9 100644
--- a/arch/arm/include/asm/arch-kirkwood/soc.h
+++ b/arch/arm/include/asm/arch-kirkwood/soc.h
@@ -33,7 +33,7 @@
#define KW_SPI_BASE(KW_REGISTER(0x10600))
#define KW_CPU_WIN_BASE(KW_REGISTER(0x2))
#define KW_CPU_REG_BASE(KW_REGISTER(0x20100))
-#define KW_TIMER_BASE (KW_REGISTER(0x20300))
+#define MVEBU_TIMER_BASE (KW_REGISTER(0x20300))
#define KW_REG_PCIE_BASE (KW_REGISTER(0x4))
#define KW_USB20_BASE (KW_REGISTER(0x5))
#define KW_EGIGA0_BASE (KW_REGISTER(0x72000))
diff --git a/arch/arm/mvebu-common/timer.c b/arch/arm/mvebu-common/timer.c
index b7aa645..40c4bc2 100644
--- a/arch/arm/mvebu-common/timer.c
+++ b/arch/arm/mvebu-common/timer.c
@@ -9,73 +9,66 @@
#include asm/io.h
#include asm/arch/soc.h
-#define UBOOT_CNTR 0 /* counter to use for uboot timer */
-
-/* Timer reload and current value registers */
-struct kwtmr_val {
- u32 reload; /* Timer reload reg */
- u32 val;/* Timer value reg */
-};
-
-/* Timer registers */
-struct kwtmr_registers {
- u32 ctrl; /* Timer control reg */
- u32 pad[3];
- struct kwtmr_val tmr[2];
- u32 wdt_reload;
- u32 wdt_val;
-};
-
-struct kwtmr_registers *kwtmr_regs = (struct kwtmr_registers *)KW_TIMER_BASE;
+#define UBOOT_CNTR 0 /* counter to use for U-Boot timer */
/*
* ARM Timers Registers Map
*/
-#define CNTMR_CTRL_REG kwtmr_regs-ctrl
-#define CNTMR_RELOAD_REG(tmrnum) kwtmr_regs-tmr[tmrnum].reload
-#define CNTMR_VAL_REG(tmrnum) kwtmr_regs-tmr[tmrnum].val
+#define CNTMR_CTRL_REG tmr_regs-ctrl
+#define CNTMR_RELOAD_REG(tmrnum) tmr_regs-tmr[tmrnum].reload
+#define CNTMR_VAL_REG(tmrnum) tmr_regs-tmr[tmrnum].val
/*
* ARM Timers Control Register
* CPU_TIMERS_CTRL_REG (CTCR)
*/
#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
-#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 CTCR_ARM_TIMER_EN_OFFS)
#define CTCR_ARM_TIMER_EN(cntr)(1
CTCR_ARM_TIMER_EN_OFFS(cntr))
-#define CTCR_ARM_TIMER_DIS(cntr) (0 CTCR_ARM_TIMER_EN_OFFS(cntr))
#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
-#define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 1)
#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 CTCR_ARM_TIMER_AUTO_OFFS(cntr))
-#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 CTCR_ARM_TIMER_AUTO_OFFS(cntr))
-/*
- * ARM Timer\Watchdog Reload Register
- * CNTMR_RELOAD_REG (TRR)
- */
-#define TRG_ARM_TIMER_REL_OFFS 0
-#define TRG_ARM_TIMER_REL_MASK 0x
+/* Only Armada XP have the 25MHz enable bit (Kirkwood doesn't) */
+#if defined(CONFIG_ARMADA_XP)
+#define CTCR_ARM_TIMER_25MHZ_OFFS(cntr)(cntr + 11)
+#define CTCR_ARM_TIMER_25MHZ(cntr) (1 CTCR_ARM_TIMER_25MHZ_OFFS(cntr))
+#else
+#define CTCR_ARM_TIMER_25MHZ(cntr) 0
+#endif
-/*
- * ARM Timer\Watchdog Register
- * CNTMR_VAL_REG (TVRG)
- */
-#define TVR_ARM_TIMER_OFFS 0
-#define TVR_ARM_TIMER_MASK 0x
-#define TVR_ARM_TIMER_MAX 0x
#define TIMER_LOAD_VAL 0x
-#define READ_TIMER (readl(CNTMR_VAL_REG(UBOOT_CNTR)) /
\
-(CONFIG_SYS_TCLK / 1000))
+#define timestamp gd-arch.tbl
+#define lastdecgd-arch.lastinc
+
+/* Timer reload and current value registers */
+struct kwtmr_val {
+ u32 reload; /* Timer reload reg */
+ u32 val;/* Timer value reg */
+};
+
+/* Timer registers */
+struct kwtmr_registers {
+ u32 ctrl; /* Timer control reg */
+ u32 pad[3];
+ struct kwtmr_val tmr[4];
+ u32 wdt_reload;
+ u32 wdt_val;
+};
DECLARE_GLOBAL_DATA_PTR;
-#define timestamp gd-arch.tbl
-#define lastdec gd-arch.lastinc
+static struct kwtmr_registers *tmr_regs =
+ (struct kwtmr_registers
[U-Boot] [PATCH v4 12/20] i2c: mvtwsi: Add support for Marvell Armada XP
To support the Armada XP SoC, we just need to include the correct header. Signed-off-by: Stefan Roese s...@denx.de Acked-by: Heiko Schocher h...@denx.de Tested-by: Luka Perkov l...@openwrt.org --- Changes in v4: None Changes in v3: - Added Tested-by from Luka - Added Acked-by from Heiko Changes in v2: None drivers/i2c/mvtwsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index a2deae6..9b2ca1e 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -20,7 +20,7 @@ #if defined(CONFIG_ORION5X) #include asm/arch/orion5x.h -#elif defined(CONFIG_KIRKWOOD) +#elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARMADA_XP)) #include asm/arch/soc.h #elif defined(CONFIG_SUNXI) #include asm/arch/i2c.h -- 2.1.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 08/20] spi: kirkwood_spi.c: Change KW_SPI_BASE to MVEBU_SPI_BASE
This makes is possible to use this SPI driver from other MVEBU SoC's as well. As the upcoming Armada XP support will do. Signed-off-by: Stefan Roese s...@denx.de Reviewed-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com Tested-by: Luka Perkov l...@openwrt.org Acked-by: Prafulla Wadaskar prafu...@marvell.com --- Changes in v4: None Changes in v3: - Added Acked-by from Prafulla to all Kirkwood patches - Added Tested-by from Luka - Added Reviewed-by from Jagannadha Changes in v2: None arch/arm/include/asm/arch-kirkwood/soc.h | 2 +- drivers/spi/kirkwood_spi.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-kirkwood/soc.h b/arch/arm/include/asm/arch-kirkwood/soc.h index 332cc24..4ef32c7 100644 --- a/arch/arm/include/asm/arch-kirkwood/soc.h +++ b/arch/arm/include/asm/arch-kirkwood/soc.h @@ -30,7 +30,7 @@ #define MVEBU_GPIO1_BASE (KW_REGISTER(0x10140)) #define KW_RTC_BASE(KW_REGISTER(0x10300)) #define KW_NANDF_BASE (KW_REGISTER(0x10418)) -#define KW_SPI_BASE(KW_REGISTER(0x10600)) +#define MVEBU_SPI_BASE (KW_REGISTER(0x10600)) #define KW_CPU_WIN_BASE(KW_REGISTER(0x2)) #define KW_CPU_REG_BASE(KW_REGISTER(0x20100)) #define MVEBU_TIMER_BASE (KW_REGISTER(0x20300)) diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index ce2ba96..e7b0982 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -18,7 +18,8 @@ #endif #include asm/arch-mvebu/spi.h -static struct kwspi_registers *spireg = (struct kwspi_registers *)KW_SPI_BASE; +static struct kwspi_registers *spireg = + (struct kwspi_registers *)MVEBU_SPI_BASE; #ifdef CONFIG_KIRKWOOD static u32 cs_spi_mpp_back[2]; -- 2.1.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 14/20] arm: armada-xp: Add basic support for the Marvell DB-MV784MP-GP board
This patch adds basic support for the Marvell DB-MV784MP-GP evaulation board. This is the first board that uses the recently created Armada XP 78460 SoC support. Signed-off-by: Stefan Roese s...@denx.de Tested-by: Luka Perkov l...@openwrt.org --- Changes in v4: None Changes in v3: - Added Tested-by from Luka - Rebased on current top-of-tree (git ID a1263632) Changes in v2: - Renamed target from db-78460-bp to db-mv784mp-gp as this matches the real eval board name arch/arm/Kconfig| 4 + board/Marvell/db-mv784mp-gp/Kconfig | 23 ++ board/Marvell/db-mv784mp-gp/MAINTAINERS | 6 ++ board/Marvell/db-mv784mp-gp/Makefile| 7 ++ board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c | 120 board/Marvell/db-mv784mp-gp/kwbimage.cfg| 12 +++ configs/db-mv784mp-gp_defconfig | 2 + include/configs/db-mv784mp-gp.h | 68 8 files changed, 242 insertions(+) create mode 100644 board/Marvell/db-mv784mp-gp/Kconfig create mode 100644 board/Marvell/db-mv784mp-gp/MAINTAINERS create mode 100644 board/Marvell/db-mv784mp-gp/Makefile create mode 100644 board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c create mode 100644 board/Marvell/db-mv784mp-gp/kwbimage.cfg create mode 100644 configs/db-mv784mp-gp_defconfig create mode 100644 include/configs/db-mv784mp-gp.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 72558b8..13ab831 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -141,6 +141,9 @@ config ARCH_DAVINCI config KIRKWOOD bool Marvell Kirkwood +config TARGET_DB_MV784MP_GP + bool Support db-mv784mp-gp + config TARGET_DEVKIT3250 bool Support devkit3250 @@ -567,6 +570,7 @@ source board/BuS/eb_cpux9k2/Kconfig source board/BuS/vl_ma2sc/Kconfig source board/CarMediaLab/flea3/Kconfig source board/Marvell/aspenite/Kconfig +source board/Marvell/db-mv784mp-gp/Kconfig source board/Marvell/dkb/Kconfig source board/Marvell/gplugd/Kconfig source board/afeb9260/Kconfig diff --git a/board/Marvell/db-mv784mp-gp/Kconfig b/board/Marvell/db-mv784mp-gp/Kconfig new file mode 100644 index 000..f94a444 --- /dev/null +++ b/board/Marvell/db-mv784mp-gp/Kconfig @@ -0,0 +1,23 @@ +if TARGET_DB_MV784MP_GP + +config SYS_CPU + string + default armv7 + +config SYS_BOARD + string + default db-mv784mp-gp + +config SYS_VENDOR + string + default Marvell + +config SYS_SOC + string + default armada-xp + +config SYS_CONFIG_NAME + string + default db-mv784mp-gp + +endif diff --git a/board/Marvell/db-mv784mp-gp/MAINTAINERS b/board/Marvell/db-mv784mp-gp/MAINTAINERS new file mode 100644 index 000..a095f89 --- /dev/null +++ b/board/Marvell/db-mv784mp-gp/MAINTAINERS @@ -0,0 +1,6 @@ +DB_MV784MP_GP BOARD +M: Stefan Roese s...@denx.de +S: Maintained +F: board/Marvell/db-mv784mp-gp/ +F: include/configs/db-mv784mp-gp.h +F: configs/db-mv784mp-gp_defconfig diff --git a/board/Marvell/db-mv784mp-gp/Makefile b/board/Marvell/db-mv784mp-gp/Makefile new file mode 100644 index 000..8f5a7fb --- /dev/null +++ b/board/Marvell/db-mv784mp-gp/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2014 Stefan Roese s...@denx.de +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := db-mv784mp-gp.o diff --git a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c new file mode 100644 index 000..b3dae89 --- /dev/null +++ b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2014 Stefan Roese s...@denx.de + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#include common.h +#include miiphy.h +#include asm/io.h +#include asm/arch/cpu.h +#include asm/arch/soc.h + +DECLARE_GLOBAL_DATA_PTR; + +#define BIT(nr)(1UL (nr)) + +#define ETH_PHY_CTRL_REG 0 +#define ETH_PHY_CTRL_POWER_DOWN_BIT11 +#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 ETH_PHY_CTRL_POWER_DOWN_BIT) + +/* + * Those values and defines are taken from the Marvell U-Boot version + * u-boot-2011.12-2014_T1.0 for the board rd78460gp aka + * RD-AXP-GP rev 1.0. + * + * GPPs + * MPP#NAMEIN/OUT + * -- + * 21 SW_Reset_ OUT + * 25 Phy_Int#IN + * 28 SDI_WP IN + * 29 SDI_Status IN + * 54-61 On GPP Connector? + * 62 Switch InterruptIN + * 63-65 Reserved from SW Board ? + * 66 SW_BRD connectedIN + */ +#define RD_78460_GP_GPP_OUT_ENA_LOW(~(BIT(21) | BIT(20))) +#define RD_78460_GP_GPP_OUT_ENA_MID(~(BIT(26) | BIT(27))) +#define RD_78460_GP_GPP_OUT_ENA_HIGH (~(0x0)) + +#define RD_78460_GP_GPP_OUT_VAL_LOW(BIT(21) | BIT(20)) +#define RD_78460_GP_GPP_OUT_VAL_MID(BIT(26) | BIT(27)) +#define RD_78460_GP_GPP_OUT_VAL_HIGH 0x0 + +int
[U-Boot] [PATCH v4 09/20] arm: kirkwood: Change naming of dram functions from km_foo() to mvebu_foo()
Additionally the SDRAM address decoding register address is not hard coded
in the C code any more. A define is introduced for this base address.
This makes is possible to use those gpio functions from other MVEBU SoC's
as well.
Signed-off-by: Stefan Roese s...@denx.de
Tested-by: Luka Perkov l...@openwrt.org
Acked-by: Prafulla Wadaskar prafu...@marvell.com
---
Changes in v4: None
Changes in v3:
- Added Acked-by from Prafulla to all Kirkwood patches
- Added Tested-by from Luka
Changes in v2: None
arch/arm/include/asm/arch-kirkwood/cpu.h| 6 +--
arch/arm/include/asm/arch-kirkwood/soc.h| 1 +
arch/arm/mvebu-common/dram.c| 53 +
board/LaCie/net2big_v2/net2big_v2.c | 2 +-
board/LaCie/netspace_v2/netspace_v2.c | 2 +-
board/LaCie/wireless_space/wireless_space.c | 2 +-
board/Marvell/dreamplug/dreamplug.c | 2 +-
board/Marvell/guruplug/guruplug.c | 2 +-
board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c | 2 +-
board/Marvell/openrd/openrd.c | 2 +-
board/Marvell/rd6281a/rd6281a.c | 2 +-
board/Marvell/sheevaplug/sheevaplug.c | 2 +-
board/Seagate/dockstar/dockstar.c | 2 +-
board/Seagate/goflexhome/goflexhome.c | 2 +-
board/buffalo/lsxl/lsxl.c | 2 +-
board/cloudengines/pogo_e02/pogo_e02.c | 2 +-
board/d-link/dns325/dns325.c| 2 +-
board/iomega/iconnect/iconnect.c| 2 +-
board/karo/tk71/tk71.c | 2 +-
board/keymile/km_arm/km_arm.c | 4 +-
board/raidsonic/ib62x0/ib62x0.c | 2 +-
21 files changed, 50 insertions(+), 48 deletions(-)
diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h
b/arch/arm/include/asm/arch-kirkwood/cpu.h
index 5900a15..926d347 100644
--- a/arch/arm/include/asm/arch-kirkwood/cpu.h
+++ b/arch/arm/include/asm/arch-kirkwood/cpu.h
@@ -140,9 +140,9 @@ struct kwgpio_registers {
* functions
*/
unsigned char get_random_hex(void);
-unsigned int kw_sdram_bar(enum memory_bank bank);
-unsigned int kw_sdram_bs(enum memory_bank bank);
-void kw_sdram_size_adjust(enum memory_bank bank);
+unsigned int mvebu_sdram_bar(enum memory_bank bank);
+unsigned int mvebu_sdram_bs(enum memory_bank bank);
+void mvebu_sdram_size_adjust(enum memory_bank bank);
int kw_config_adr_windows(void);
void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
unsigned int gpp0_oe, unsigned int gpp1_oe);
diff --git a/arch/arm/include/asm/arch-kirkwood/soc.h
b/arch/arm/include/asm/arch-kirkwood/soc.h
index 4ef32c7..58ed71b 100644
--- a/arch/arm/include/asm/arch-kirkwood/soc.h
+++ b/arch/arm/include/asm/arch-kirkwood/soc.h
@@ -22,6 +22,7 @@
#define KW_REG_UNDOC_0x1470(KW_REGISTER(0x1470))
#define KW_REG_UNDOC_0x1478(KW_REGISTER(0x1478))
+#define MVEBU_SDRAM_BASE (KW_REGISTER(0x1500))
#define KW_TWSI_BASE (KW_REGISTER(0x11000))
#define KW_UART0_BASE (KW_REGISTER(0x12000))
#define KW_UART1_BASE (KW_REGISTER(0x12100))
diff --git a/arch/arm/mvebu-common/dram.c b/arch/arm/mvebu-common/dram.c
index e468136..db18791 100644
--- a/arch/arm/mvebu-common/dram.c
+++ b/arch/arm/mvebu-common/dram.c
@@ -14,27 +14,27 @@
DECLARE_GLOBAL_DATA_PTR;
-struct kw_sdram_bank {
+struct sdram_bank {
u32 win_bar;
u32 win_sz;
};
-struct kw_sdram_addr_dec {
- struct kw_sdram_banksdram_bank[4];
+struct sdram_addr_dec {
+ struct sdram_bank sdram_bank[4];
};
-#define KW_REG_CPUCS_WIN_ENABLE(1 0)
-#define KW_REG_CPUCS_WIN_WR_PROTECT(1 1)
-#define KW_REG_CPUCS_WIN_WIN0_CS(x)(((x) 0x3) 2)
-#define KW_REG_CPUCS_WIN_SIZE(x) (((x) 0xff) 24)
+#define REG_CPUCS_WIN_ENABLE (1 0)
+#define REG_CPUCS_WIN_WR_PROTECT (1 1)
+#define REG_CPUCS_WIN_WIN0_CS(x) (((x) 0x3) 2)
+#define REG_CPUCS_WIN_SIZE(x) (((x) 0xff) 24)
/*
- * kw_sdram_bar - reads SDRAM Base Address Register
+ * mvebu_sdram_bar - reads SDRAM Base Address Register
*/
-u32 kw_sdram_bar(enum memory_bank bank)
+u32 mvebu_sdram_bar(enum memory_bank bank)
{
- struct kw_sdram_addr_dec *base =
- (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
+ struct sdram_addr_dec *base =
+ (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
u32 result = 0;
u32 enable = 0x01 readl(base-sdram_bank[bank].win_sz);
@@ -46,31 +46,31 @@ u32 kw_sdram_bar(enum memory_bank bank)
}
/*
- * kw_sdram_bs_set - writes SDRAM Bank size
+ * mvebu_sdram_bs_set - writes SDRAM Bank size
*/
-static void kw_sdram_bs_set(enum memory_bank bank, u32 size)
+static void mvebu_sdram_bs_set(enum memory_bank bank, u32 size)
{
- struct kw_sdram_addr_dec *base =
- (struct kw_sdram_addr_dec
[U-Boot] [PATCH v4 02/20] arm: marvell: Move arch/kirkwood.h to arch/soc.h
This move makes is possible to use this header not only from kirkwood
platforms but from all Marvell mvebu platforms.
Signed-off-by: Stefan Roese s...@denx.de
Tested-by: Luka Perkov l...@openwrt.org
Acked-by: Prafulla Wadaskar prafu...@marvell.com
---
Changes in v4: None
Changes in v3:
- Added Acked-by from Prafulla to all Kirkwood patches
- Added Tested-by from Luka
- Added newly introduced driver drivers/mmc/mvebu_mmc.c
Changes in v2: None
arch/arm/cpu/arm926ejs/kirkwood/cpu.c| 2 +-
arch/arm/cpu/arm926ejs/kirkwood/mpp.c| 2 +-
arch/arm/include/asm/arch-kirkwood/config.h | 2 +-
arch/arm/include/asm/arch-kirkwood/{kirkwood.h = soc.h} | 0
arch/arm/mvebu-common/dram.c | 2 +-
arch/arm/mvebu-common/timer.c| 2 +-
board/LaCie/net2big_v2/net2big_v2.c | 2 +-
board/LaCie/netspace_v2/netspace_v2.c| 2 +-
board/LaCie/wireless_space/wireless_space.c | 2 +-
board/Marvell/dreamplug/dreamplug.c | 2 +-
board/Marvell/guruplug/guruplug.c| 2 +-
board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c | 2 +-
board/Marvell/openrd/openrd.c| 2 +-
board/Marvell/rd6281a/rd6281a.c | 2 +-
board/Marvell/sheevaplug/sheevaplug.c| 2 +-
board/Seagate/dockstar/dockstar.c| 2 +-
board/Seagate/goflexhome/goflexhome.c| 2 +-
board/buffalo/lsxl/lsxl.c| 2 +-
board/cloudengines/pogo_e02/pogo_e02.c | 2 +-
board/d-link/dns325/dns325.c | 2 +-
board/iomega/iconnect/iconnect.c | 2 +-
board/karo/tk71/tk71.c | 2 +-
board/keymile/km_arm/km_arm.c| 2 +-
board/raidsonic/ib62x0/ib62x0.c | 2 +-
drivers/block/mvsata_ide.c | 2 +-
drivers/gpio/kw_gpio.c | 2 +-
drivers/i2c/mvtwsi.c | 2 +-
drivers/mmc/mvebu_mmc.c | 2 +-
drivers/mtd/nand/kirkwood_nand.c | 2 +-
drivers/net/mvgbe.c | 2 +-
drivers/rtc/mvrtc.h | 2 +-
drivers/spi/kirkwood_spi.c | 2 +-
drivers/usb/host/ehci-marvell.c | 2 +-
33 files changed, 32 insertions(+), 32 deletions(-)
rename arch/arm/include/asm/arch-kirkwood/{kirkwood.h = soc.h} (100%)
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
index 881e2de..75d3799 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
@@ -12,7 +12,7 @@
#include u-boot/md5.h
#include asm/io.h
#include asm/arch/cpu.h
-#include asm/arch/kirkwood.h
+#include asm/arch/soc.h
#include mvebu_mmc.h
#define BUFLEN 16
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c
b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c
index 0ba6f09..7222504 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c
@@ -12,7 +12,7 @@
#include common.h
#include asm/io.h
#include asm/arch/cpu.h
-#include asm/arch/kirkwood.h
+#include asm/arch/soc.h
#include asm/arch/mpp.h
static u32 kirkwood_variant(void)
diff --git a/arch/arm/include/asm/arch-kirkwood/config.h
b/arch/arm/include/asm/arch-kirkwood/config.h
index f7bfa0e..ccc8e4e 100644
--- a/arch/arm/include/asm/arch-kirkwood/config.h
+++ b/arch/arm/include/asm/arch-kirkwood/config.h
@@ -23,7 +23,7 @@
#error SOC Name not defined
#endif /* CONFIG_KW88F6281 */
-#include asm/arch/kirkwood.h
+#include asm/arch/soc.h
#define CONFIG_ARM926EJS 1 /* Basic Architecture */
#define CONFIG_SYS_CACHELINE_SIZE 32
/* default Dcache Line length for kirkwood */
diff --git a/arch/arm/include/asm/arch-kirkwood/kirkwood.h
b/arch/arm/include/asm/arch-kirkwood/soc.h
similarity index 100%
rename from arch/arm/include/asm/arch-kirkwood/kirkwood.h
rename to arch/arm/include/asm/arch-kirkwood/soc.h
diff --git a/arch/arm/mvebu-common/dram.c b/arch/arm/mvebu-common/dram.c
index bb5989b..e468136 100644
--- a/arch/arm/mvebu-common/dram.c
+++ b/arch/arm/mvebu-common/dram.c
@@ -10,7 +10,7 @@
#include common.h
#include asm/io.h
#include asm/arch/cpu.h
-#include asm/arch/kirkwood.h
+#include asm/arch/soc.h
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/mvebu-common/timer.c b/arch/arm/mvebu-common/timer.c
index a08f4a1..b7aa645 100644
--- a/arch/arm/mvebu-common/timer.c
+++ b/arch/arm/mvebu-common/timer.c
@@ -7,7 +7,7 @@
#include common.h
#include asm/io.h
-#include asm/arch/kirkwood.h
+#include asm/arch/soc.h
#define UBOOT_CNTR 0 /* counter to use for uboot
[U-Boot] [PATCH v4 10/20] net: mvneta.c: Add support for the ethernet controller of the Marvell Armada XP SoC
This patch adds support for the NETA ethernet controller which is integrated in the Marvell Armada XP SoC's. This port is based on the Linux driver which has been stripped of the in U-Boot unused portions. Tested on the Marvell MV78460 eval board db-78460-bp. Signed-off-by: Stefan Roese s...@denx.de Cc: Joe Hershberger joe.hershber...@gmail.com Tested-by: Luka Perkov l...@openwrt.org --- Changes in v4: None Changes in v3: - Added Tested-by from Luka Changes in v2: None drivers/net/Makefile |1 + drivers/net/mvneta.c | 1653 ++ include/netdev.h |1 + 3 files changed, 1655 insertions(+) create mode 100644 drivers/net/mvneta.c diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 2c4dd7c..fb0cf8c 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o obj-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o obj-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o obj-$(CONFIG_MVGBE) += mvgbe.o +obj-$(CONFIG_MVNETA) += mvneta.o obj-$(CONFIG_NATSEMI) += natsemi.o obj-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o obj-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c new file mode 100644 index 000..a2a69b4 --- /dev/null +++ b/drivers/net/mvneta.c @@ -0,0 +1,1653 @@ +/* + * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. + * + * U-Boot version: + * Copyright (C) 2014 Stefan Roese s...@denx.de + * + * Based on the Linux version which is: + * Copyright (C) 2012 Marvell + * + * Rami Rosen ros...@marvell.com + * Thomas Petazzoni thomas.petazz...@free-electrons.com + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#include common.h +#include net.h +#include netdev.h +#include config.h +#include malloc.h +#include asm/io.h +#include asm/errno.h +#include phy.h +#include miiphy.h +#include watchdog.h +#include asm/arch/cpu.h +#include asm/arch/soc.h +#include linux/compat.h +#include linux/mbus.h + +#if !defined(CONFIG_PHYLIB) +# error Marvell mvneta requires PHYLIB +#endif + +/* Some linux - U-Boot compatibility stuff */ +#define netdev_err(dev, fmt, args...) \ + printf(fmt, ##args) +#define netdev_warn(dev, fmt, args...) \ + printf(fmt, ##args) +#define netdev_info(dev, fmt, args...) \ + printf(fmt, ##args) + +#define CONFIG_NR_CPUS 1 +#define BIT(nr)(1UL (nr)) +#define ETH_HLEN 14 /* Total octets in header */ + +/* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */ +#define WRAP (2 + ETH_HLEN + 4 + 32) +#define MTU1500 +#define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN)) + +#define MVNETA_SMI_TIMEOUT 1 + +/* Registers */ +#define MVNETA_RXQ_CONFIG_REG(q)(0x1400 + ((q) 2)) +#define MVNETA_RXQ_HW_BUF_ALLOCBIT(1) +#define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf 8) +#define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) 8) +#define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) 2)) +#define MVNETA_RXQ_NON_OCCUPIED(v) ((v) 16) +#define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) 2)) +#define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) 2)) +#define MVNETA_RXQ_BUF_SIZE_SHIFT 19 +#define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff 19) +#define MVNETA_RXQ_STATUS_REG(q)(0x14e0 + ((q) 2)) +#define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff +#define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) 2)) +#define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 +#define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX255 +#define MVNETA_PORT_RX_RESET0x1cc0 +#define MVNETA_PORT_RX_DMA_RESET BIT(0) +#define MVNETA_PHY_ADDR 0x2000 +#define MVNETA_PHY_ADDR_MASK 0x1f +#define MVNETA_SMI 0x2004 +#define MVNETA_PHY_REG_MASK0x1f +/* SMI register fields */ +#define MVNETA_SMI_DATA_OFFS 0 /* Data */ +#define MVNETA_SMI_DATA_MASK (0x MVNETA_SMI_DATA_OFFS) +#define MVNETA_SMI_DEV_ADDR_OFFS 16 /* PHY device address */ +#define MVNETA_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/ +#define MVNETA_SMI_OPCODE_OFFS 26 /* Write/Read opcode */ +#define MVNETA_SMI_OPCODE_READ (1 MVNETA_SMI_OPCODE_OFFS) +#define MVNETA_SMI_READ_VALID (1 27) /* Read Valid */ +#define MVNETA_SMI_BUSY(1 28) /* Busy */ +#define MVNETA_MBUS_RETRY 0x2010 +#define MVNETA_UNIT_INTR_CAUSE 0x2080 +#define MVNETA_UNIT_CONTROL 0x20B0 +#define MVNETA_PHY_POLLING_ENABLE BIT(1) +#define
[U-Boot] [PATCH v4 16/20] arm: kirkwood: Remove some dead code from cpu.c
All those functions removed with this patch are not accessed at all. So lets
remove them.
Signed-off-by: Stefan Roese s...@denx.de
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/arm926ejs/kirkwood/cpu.c | 55 ---
1 file changed, 55 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
index ea835fc..9e412bb 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
@@ -9,14 +9,11 @@
#include common.h
#include netdev.h
#include asm/cache.h
-#include u-boot/md5.h
#include asm/io.h
#include asm/arch/cpu.h
#include asm/arch/soc.h
#include mvebu_mmc.h
-#define BUFLEN 16
-
void reset_cpu(unsigned long ignored)
{
struct kwcpu_registers *cpureg =
@@ -30,31 +27,6 @@ void reset_cpu(unsigned long ignored)
}
/*
- * Generates Ramdom hex number reading some time varient system registers
- * and using md5 algorithm
- */
-unsigned char get_random_hex(void)
-{
- int i;
- u32 inbuf[BUFLEN];
- u8 outbuf[BUFLEN];
-
- /*
-* in case of 88F6281/88F6282/88F6192 A0,
-* Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470
-* Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are
-* reserved regs and does not have names at this moment
-* (no errata available)
-*/
- writel(readl(KW_REG_UNDOC_0x1478) ~(1 7), KW_REG_UNDOC_0x1478);
- for (i = 0; i BUFLEN; i++) {
- inbuf[i] = readl(KW_REG_UNDOC_0x1470);
- }
- md5((u8 *) inbuf, (BUFLEN * sizeof(u32)), outbuf);
- return outbuf[outbuf[7] % 0x0f];
-}
-
-/*
* Window Size
* Used with the Base register to set the address window size and location.
* Must be programmed from LSB to MSB as sequence of ones followed by
@@ -140,33 +112,6 @@ int kw_config_adr_windows(void)
}
/*
- * kw_config_mpp - Multi-Purpose Pins Functionality configuration
- *
- * Each MPP can be configured to different functionality through
- * MPP control register, ref (sec 6.1 of kirkwood h/w specification)
- *
- * There are maximum 64 Multi-Pourpose Pins on Kirkwood
- * Each MPP functionality can be configuration by a 4bit value
- * of MPP control reg, the value and associated functionality depends
- * upon used SoC varient
- */
-int kw_config_mpp(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23, u32 mpp24_31,
- u32 mpp32_39, u32 mpp40_47, u32 mpp48_55)
-{
- u32 *mppreg = (u32 *) KW_MPP_BASE;
-
- /* program mpp registers */
- writel(mpp0_7, mppreg[0]);
- writel(mpp8_15, mppreg[1]);
- writel(mpp16_23, mppreg[2]);
- writel(mpp24_31, mppreg[3]);
- writel(mpp32_39, mppreg[4]);
- writel(mpp40_47, mppreg[5]);
- writel(mpp48_55, mppreg[6]);
- return 0;
-}
-
-/*
* SYSRSTn Duration Counter Support
*
* Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
--
2.1.2
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 19/20] tools: kwbimage: Add image version 1 support for Armada XP / 370
This patch integrates the Barebox version of this kwbimage.c file into
U-Boot. As this version supports the image version 1 type for the
Armada XP / 370 SoCs.
It was easier to integrate the existing and known to be working Barebox
source than to update the current U-Boot version to support this
v1 image header format. Now all Marvell MVEBU SoCs are supported:
Image type 0: Kirkwood Dove
Image type 1: Armada 370 Armada XP
Please note that the current v1 support has this restuction (same as
has Barebox version):
Not implemented: support for the register headers and secure headers
in v1 images
Tested on Marvell DB-78460-BP eval board.
Signed-off-by: Stefan Roese s...@denx.de
Tested-by: Luka Perkov l...@openwrt.org
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
tools/kwbimage.c | 1050 --
1 file changed, 782 insertions(+), 268 deletions(-)
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index 109d616..1120e9b 100644
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -1,364 +1,805 @@
/*
- * (C) Copyright 2008
- * Marvell Semiconductor www.marvell.com
- * Written-by: Prafulla Wadaskar prafu...@marvell.com
+ * Image manipulator for Marvell SoCs
+ * supports Kirkwood, Dove, Armada 370, and Armada XP
+ *
+ * (C) Copyright 2013 Thomas Petazzoni
+ * thomas.petazz...@free-electrons.com
*
* SPDX-License-Identifier:GPL-2.0+
+ *
+ * Not implemented: support for the register headers and secure
+ * headers in v1 images
*/
#include imagetool.h
#include image.h
+#include stdint.h
#include kwbimage.h
-/*
- * Supported commands for configuration file
- */
-static table_entry_t kwbimage_cmds[] = {
- {CMD_BOOT_FROM, BOOT_FROM,boot command, },
- {CMD_NAND_ECC_MODE, NAND_ECC_MODE,NAND mode,},
- {CMD_NAND_PAGE_SIZE,NAND_PAGE_SIZE, NAND size,},
- {CMD_SATA_PIO_MODE, SATA_PIO_MODE,SATA mode,},
- {CMD_DDR_INIT_DELAY,DDR_INIT_DELAY, DDR init dly, },
- {CMD_DATA, DATA, Reg Write Data, },
- {CMD_INVALID, , , },
+#define ALIGN_SUP(x, a) (((x) + (a - 1)) ~(a - 1))
+
+/* Structure of the main header, version 0 (Kirkwood, Dove) */
+struct main_hdr_v0 {
+ uint8_t blockid; /*0 */
+ uint8_t nandeccmode; /*1 */
+ uint16_t nandpagesize; /*2-3 */
+ uint32_t blocksize; /*4-7 */
+ uint32_t rsvd1; /*8-11 */
+ uint32_t srcaddr; /*12-15 */
+ uint32_t destaddr; /*16-19 */
+ uint32_t execaddr; /*20-23 */
+ uint8_t satapiomode; /*24*/
+ uint8_t rsvd3; /*25*/
+ uint16_t ddrinitdelay; /*26-27 */
+ uint16_t rsvd2; /*28-29 */
+ uint8_t ext; /*30*/
+ uint8_t checksum; /*31*/
+};
+
+struct ext_hdr_v0_reg {
+ uint32_t raddr;
+ uint32_t rdata;
+};
+
+#define EXT_HDR_V0_REG_COUNT ((0x1dc - 0x20) / sizeof(struct ext_hdr_v0_reg))
+
+struct ext_hdr_v0 {
+ uint32_t offset;
+ uint8_t reserved[0x20 - sizeof(uint32_t)];
+ struct ext_hdr_v0_reg rcfg[EXT_HDR_V0_REG_COUNT];
+ uint8_t reserved2[7];
+ uint8_t checksum;
+};
+
+/* Structure of the main header, version 1 (Armada 370, Armada XP) */
+struct main_hdr_v1 {
+ uint8_t blockid; /* 0 */
+ uint8_t reserved1; /* 1 */
+ uint16_t reserved2; /* 2-3 */
+ uint32_t blocksize; /* 4-7 */
+ uint8_t version; /* 8 */
+ uint8_t headersz_msb; /* 9 */
+ uint16_t headersz_lsb; /* A-B */
+ uint32_t srcaddr; /* C-F */
+ uint32_t destaddr; /* 10-13 */
+ uint32_t execaddr; /* 14-17 */
+ uint8_t reserved3; /* 18 */
+ uint8_t nandblocksize; /* 19 */
+ uint8_t nandbadblklocation;/* 1A */
+ uint8_t reserved4; /* 1B */
+ uint16_t reserved5; /* 1C-1D */
+ uint8_t ext; /* 1E */
+ uint8_t checksum; /* 1F */
};
/*
- * Supported Boot options for configuration file
+ * Header for the optional headers, version 1 (Armada 370, Armada XP)
*/
-static table_entry_t kwbimage_bootops[] = {
- {IBR_HDR_SPI_ID,spi, SPI Flash,},
- {IBR_HDR_NAND_ID, nand, NAND Flash, },
- {IBR_HDR_SATA_ID, sata, Sata port,},
- {IBR_HDR_PEX_ID,pex, PCIe port,},
- {IBR_HDR_UART_ID, uart, Serial port, },
- {-1,, Invalid, },
+struct opt_hdr_v1
[U-Boot] [PATCH v4 13/20] arm: armada-xp: Add basic support for Marvell Armada XP SoC
This basic support for the Marvell Armada XP is base on the existing kirkwood
support. Which has been generatized by moving some common files into
common marvell locations.
This is in preparation for the upcoming Armada XP MV78460 support.
Signed-off-by: Stefan Roese s...@denx.de
Tested-by: Luka Perkov l...@openwrt.org
---
Changes in v4:
- Unused SDRAM windows are now disabled in update_sdram_window_sizes()
Changes in v3:
- Added Tested-by from Luka
Changes in v2: None
Makefile | 2 +-
arch/arm/cpu/armv7/armada-xp/Makefile| 7 +
arch/arm/cpu/armv7/armada-xp/cpu.c | 193 +++
arch/arm/include/asm/arch-armada-xp/config.h | 82
arch/arm/include/asm/arch-armada-xp/cpu.h| 107 +++
arch/arm/include/asm/arch-armada-xp/soc.h| 57
6 files changed, 447 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/armada-xp/Makefile
create mode 100644 arch/arm/cpu/armv7/armada-xp/cpu.c
create mode 100644 arch/arm/include/asm/arch-armada-xp/config.h
create mode 100644 arch/arm/include/asm/arch-armada-xp/cpu.h
create mode 100644 arch/arm/include/asm/arch-armada-xp/soc.h
diff --git a/Makefile b/Makefile
index 4d54bd2..25161e6 100644
--- a/Makefile
+++ b/Makefile
@@ -652,7 +652,7 @@ ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs
vf610))
libs-y += arch/$(ARCH)/imx-common/
endif
-ifneq (,$(filter $(SOC), kirkwood))
+ifneq (,$(filter $(SOC), armada-xp kirkwood))
libs-y += arch/$(ARCH)/mvebu-common/
endif
diff --git a/arch/arm/cpu/armv7/armada-xp/Makefile
b/arch/arm/cpu/armv7/armada-xp/Makefile
new file mode 100644
index 000..885dcee
--- /dev/null
+++ b/arch/arm/cpu/armv7/armada-xp/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2014 Stefan Roese s...@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = cpu.o
diff --git a/arch/arm/cpu/armv7/armada-xp/cpu.c
b/arch/arm/cpu/armv7/armada-xp/cpu.c
new file mode 100644
index 000..1cf70a9
--- /dev/null
+++ b/arch/arm/cpu/armv7/armada-xp/cpu.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright (C) 2014 Stefan Roese s...@denx.de
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include netdev.h
+#include asm/io.h
+#include asm/arch/cpu.h
+#include asm/arch/soc.h
+
+#define DDR_BASE_CS_OFF(n) (0x + ((n) 3))
+#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) 3))
+
+static struct mbus_win windows[] = {
+ /* PCIE MEM address space */
+ { DEFADR_PCI_MEM, 256 20, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_MEM },
+
+ /* PCIE IO address space */
+ { DEFADR_PCI_IO, 64 10, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_IO },
+
+ /* SPI */
+ { DEFADR_SPIF, 8 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
+ CPU_ATTR_SPIFLASH },
+
+ /* NOR */
+ { DEFADR_BOOTROM, 8 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
+ CPU_ATTR_BOOTROM },
+};
+
+void reset_cpu(unsigned long ignored)
+{
+ struct mvebu_system_registers *reg =
+ (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
+
+ writel(readl(reg-rstoutn_mask) | 1, reg-rstoutn_mask);
+ writel(readl(reg-sys_soft_rst) | 1, reg-sys_soft_rst);
+ while (1)
+ ;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ u16 devid = (readl(MVEBU_REG_PCIE_DEVID) 16) 0x;
+ u8 revid = readl(MVEBU_REG_PCIE_REVID) 0xff;
+
+ puts(SoC: );
+
+ switch (devid) {
+ case SOC_MV78460_ID:
+ puts(MV78460-);
+ break;
+ default:
+ puts(Unknown-);
+ break;
+ }
+
+ switch (revid) {
+ case 1:
+ puts(A0\n);
+ break;
+ case 2:
+ puts(B0\n);
+ break;
+ default:
+ puts(??\n);
+ break;
+ }
+
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+/*
+ * This function initialize Controller DRAM Fastpath windows.
+ * It takes the CS size information from the 0x1500 scratch registers
+ * and sets the correct windows sizes and base addresses accordingly.
+ *
+ * These values are set in the scratch registers by the Marvell
+ * DDR3 training code, which is executed by the BootROM before the
+ * main payload (U-Boot) is executed. This training code is currently
+ * only available in the Marvell U-Boot version. It needs to be
+ * ported to mainline U-Boot SPL at some point.
+ */
+static void update_sdram_window_sizes(void)
+{
+ u64 base = 0;
+ u32 size, temp;
+ int i;
+
+ for (i = 0; i SDRAM_MAX_CS; i++) {
+ size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) SDRAM_ADDR_MASK;
+ if (size != 0) {
+ size |= ~(SDRAM_ADDR_MASK);
+
+ /* Set Base Address */
+ temp = (base 0xFF00ll) | ((base 32) 0xF);
+ writel(temp, MVEBU_SDRAM_BASE +
[U-Boot] [PATCH v4 06/20] spi: kirkwood_spi.c: Compile MPP (pin-mux) only for kirkwood SoC's
Compile the pin multiplexing only on Kirkwood platforms. As the
Armada XP doesn't need it.
Signed-off-by: Stefan Roese s...@denx.de
Reviewed-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Tested-by: Luka Perkov l...@openwrt.org
Acked-by: Prafulla Wadaskar prafu...@marvell.com
---
Changes in v4: None
Changes in v3:
- Added Acked-by from Prafulla to all Kirkwood patches
- Added Tested-by from Luka
- Added Reviewed-by from Jagannadha
Changes in v2: None
drivers/spi/kirkwood_spi.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
index 9710f12..ce2ba96 100644
--- a/drivers/spi/kirkwood_spi.c
+++ b/drivers/spi/kirkwood_spi.c
@@ -13,22 +13,28 @@
#include spi.h
#include asm/io.h
#include asm/arch/soc.h
+#ifdef CONFIG_KIRKWOOD
#include asm/arch/mpp.h
+#endif
#include asm/arch-mvebu/spi.h
static struct kwspi_registers *spireg = (struct kwspi_registers *)KW_SPI_BASE;
+#ifdef CONFIG_KIRKWOOD
static u32 cs_spi_mpp_back[2];
+#endif
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct spi_slave *slave;
u32 data;
+#ifdef CONFIG_KIRKWOOD
static const u32 kwspi_mpp_config[2][2] = {
{ MPP0_SPI_SCn, 0 }, /* if cs == 0 */
{ MPP7_SPI_SCn, 0 } /* if cs != 0 */
};
+#endif
if (!spi_cs_is_valid(bus, cs))
return NULL;
@@ -51,15 +57,19 @@ struct spi_slave *spi_setup_slave(unsigned int bus,
unsigned int cs,
writel(KWSPI_SMEMRDIRQ, spireg-irq_cause);
writel(KWSPI_IRQMASK, spireg-irq_mask);
+#ifdef CONFIG_KIRKWOOD
/* program mpp registers to select SPI_CSn */
kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back);
+#endif
return slave;
}
void spi_free_slave(struct spi_slave *slave)
{
+#ifdef CONFIG_KIRKWOOD
kirkwood_mpp_conf(cs_spi_mpp_back, NULL);
+#endif
free(slave);
}
--
2.1.2
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[U-Boot] [PATCH v4 11/20] net: phy.h: Make PHY autonegotiation timeout configurable
The Marvell MV78460 eval board DB-78460-BP seems to need a longer
PHY autonegotiation timeout than the standard 4 seconds. So lets
make this timeout configurable. If not defined in the board config
header the original 4000ms is used.
Signed-off-by: Stefan Roese s...@denx.de
Cc: Joe Hershberger joe.hershber...@gmail.com
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
include/phy.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/phy.h b/include/phy.h
index 2fcc328..b495077 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -32,7 +32,9 @@
#define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \
SUPPORTED_1baseT_Full)
+#ifndef PHY_ANEG_TIMEOUT
#define PHY_ANEG_TIMEOUT 4000
+#endif
typedef enum {
--
2.1.2
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[U-Boot] [PATCH v4 01/20] arm: kirkwood: Move some SoC files into new arch/arm/mvebu-common
By moving some kirkwood files into a Marvell common directory, those files
can be used by other Marvell platforms as well. The name mvebu is taken
from the Linux kernel source tree. It has been chosen there to represent
the SoC's from the Marvell EBU (Engineering Business Unit). Those SoC's
currently are:
Armada 370/375/XP, Dove, mv78xx0, Kirkwood, Orion5x
This will be used by the upcoming Armada XP (MV78460) platform support.
Signed-off-by: Stefan Roese s...@denx.de
Tested-by: Luka Perkov l...@openwrt.org
Acked-by: Prafulla Wadaskar prafu...@marvell.com
---
Changes in v4: None
Changes in v3:
- Added Acked-by from Prafulla to all Kirkwood patches
- Added Tested-by from Luka
Changes in v2: None
Makefile | 4
arch/arm/cpu/arm926ejs/kirkwood/Makefile | 4 +---
arch/arm/mvebu-common/Makefile| 10 ++
arch/arm/{cpu/arm926ejs/kirkwood = mvebu-common}/dram.c | 8 +++-
arch/arm/{cpu/arm926ejs/kirkwood = mvebu-common}/timer.c | 0
5 files changed, 22 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/mvebu-common/Makefile
rename arch/arm/{cpu/arm926ejs/kirkwood = mvebu-common}/dram.c (91%)
rename arch/arm/{cpu/arm926ejs/kirkwood = mvebu-common}/timer.c (100%)
diff --git a/Makefile b/Makefile
index 99097e1..4d54bd2 100644
--- a/Makefile
+++ b/Makefile
@@ -652,6 +652,10 @@ ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs
vf610))
libs-y += arch/$(ARCH)/imx-common/
endif
+ifneq (,$(filter $(SOC), kirkwood))
+libs-y += arch/$(ARCH)/mvebu-common/
+endif
+
libs-$(CONFIG_ARM) += arch/arm/cpu/
libs-$(CONFIG_PPC) += arch/powerpc/cpu/
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Makefile
b/arch/arm/cpu/arm926ejs/kirkwood/Makefile
index c230ce8..df4756e 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/Makefile
+++ b/arch/arm/cpu/arm926ejs/kirkwood/Makefile
@@ -7,7 +7,5 @@
#
obj-y = cpu.o
-obj-y += dram.o
-obj-y += mpp.o
-obj-y += timer.o
obj-y += cache.o
+obj-y += mpp.o
diff --git a/arch/arm/mvebu-common/Makefile b/arch/arm/mvebu-common/Makefile
new file mode 100644
index 000..4d20d2c
--- /dev/null
+++ b/arch/arm/mvebu-common/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor www.marvell.com
+# Written-by: Prafulla Wadaskar prafu...@marvell.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = dram.o
+obj-y += timer.o
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/dram.c
b/arch/arm/mvebu-common/dram.c
similarity index 91%
rename from arch/arm/cpu/arm926ejs/kirkwood/dram.c
rename to arch/arm/mvebu-common/dram.c
index d73ae47..bb5989b 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/dram.c
+++ b/arch/arm/mvebu-common/dram.c
@@ -110,7 +110,13 @@ int dram_init(void)
if (gd-bd-bi_dram[i].start != gd-ram_size)
break;
- gd-ram_size += gd-bd-bi_dram[i].size;
+ /*
+* Don't report more than 3GiB of SDRAM, otherwise there is no
+* address space left for the internal registers etc.
+*/
+ if ((gd-ram_size + gd-bd-bi_dram[i].size != 0)
+ (gd-ram_size + gd-bd-bi_dram[i].size = (3 30)))
+ gd-ram_size += gd-bd-bi_dram[i].size;
}
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/timer.c
b/arch/arm/mvebu-common/timer.c
similarity index 100%
rename from arch/arm/cpu/arm926ejs/kirkwood/timer.c
rename to arch/arm/mvebu-common/timer.c
--
2.1.2
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[U-Boot] [PATCH v4 20/20] Makefile: Add CONFIG_BUILD_TARGET to automatically build an special image
Add target to build it automatically upon make / MAKEALL. This can/should be set by board / cpu specific headers if a special U-Boot image is required for this SoC / board. E.g. used by Marvell Armada XP to automatically build the u-boot.kwb target. Signed-off-by: Stefan Roese s...@denx.de Cc: Masahiro Yamada yamad...@jp.panasonic.com --- Changes in v4: None Changes in v3: None Changes in v2: - Rebased on latest U-Boot version already including the Kconfig support switch. - Removed patch [PATCH v1 21/25] arm: kirkwood: Use mvebu new common mbus API as this breaks Kirkwood booting. This needs to be resolved at some time, but I don't have access to a Kirkwood based board with JTAG BDI access to debug it right now. Till somebody fixes this issue, lets just remove it from this series for now. - Added basic support for the maxBCM MV78460 based board Makefile | 5 + README | 8 2 files changed, 13 insertions(+) diff --git a/Makefile b/Makefile index 25161e6..bd0f45e 100644 --- a/Makefile +++ b/Makefile @@ -758,6 +758,11 @@ endif endif endif +# Add optional build target if defined in board/cpu/soc headers +ifneq ($(CONFIG_BUILD_TARGET),) +ALL-y += $(CONFIG_BUILD_TARGET:%=%) +endif + LDFLAGS_u-boot += $(LDFLAGS_FINAL) ifneq ($(CONFIG_SYS_TEXT_BASE),) LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE) diff --git a/README b/README index 19abe20..ac00a97 100644 --- a/README +++ b/README @@ -2722,6 +2722,14 @@ CBFS (Coreboot Filesystem) support 200 ms. - Configuration Management: + CONFIG_BUILD_TARGET + + Some SoCs need special image types (e.g. U-Boot binary + with a special header) as build targets. By defining + CONFIG_BUILD_TARGET in the SoC / board header, this + special image will be automatically built upon calling + make / MAKEALL. + CONFIG_IDENT_STRING If defined, this string will be added to the U-Boot -- 2.1.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 15/20] arm: armada-xp: Add basic support for the maxBCM board
The maxBCM board is equipped with the Marvell Armada-XP MV78460 SoC. It
integrates an SPI NOR flash and an Marvell 88E6185 switch.
Signed-off-by: Stefan Roese s...@denx.de
---
Changes in v4: None
Changes in v3:
- Rebased on current top-of-tree (git ID a1263632)
Changes in v2: None
arch/arm/Kconfig | 4 +++
board/maxbcm/Kconfig | 19
board/maxbcm/MAINTAINERS | 6
board/maxbcm/Makefile | 7 +
board/maxbcm/kwbimage.cfg | 12
board/maxbcm/maxbcm.c | 77 +++
configs/maxbcm_defconfig | 2 ++
include/configs/maxbcm.h | 68 +
8 files changed, 195 insertions(+)
create mode 100644 board/maxbcm/Kconfig
create mode 100644 board/maxbcm/MAINTAINERS
create mode 100644 board/maxbcm/Makefile
create mode 100644 board/maxbcm/kwbimage.cfg
create mode 100644 board/maxbcm/maxbcm.c
create mode 100644 configs/maxbcm_defconfig
create mode 100644 include/configs/maxbcm.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 13ab831..109d49f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -144,6 +144,9 @@ config KIRKWOOD
config TARGET_DB_MV784MP_GP
bool Support db-mv784mp-gp
+config TARGET_MAXBCM
+ bool Support maxbcm
+
config TARGET_DEVKIT3250
bool Support devkit3250
@@ -652,6 +655,7 @@ source board/jornada/Kconfig
source board/karo/tx25/Kconfig
source board/logicpd/imx27lite/Kconfig
source board/logicpd/imx31_litekit/Kconfig
+source board/maxbcm/Kconfig
source board/mpl/vcma9/Kconfig
source board/olimex/mx23_olinuxino/Kconfig
source board/palmld/Kconfig
diff --git a/board/maxbcm/Kconfig b/board/maxbcm/Kconfig
new file mode 100644
index 000..d34e2ab
--- /dev/null
+++ b/board/maxbcm/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_MAXBCM
+
+config SYS_CPU
+ string
+ default armv7
+
+config SYS_BOARD
+ string
+ default maxbcm
+
+config SYS_SOC
+ string
+ default armada-xp
+
+config SYS_CONFIG_NAME
+ string
+ default maxbcm
+
+endif
diff --git a/board/maxbcm/MAINTAINERS b/board/maxbcm/MAINTAINERS
new file mode 100644
index 000..3c8af21
--- /dev/null
+++ b/board/maxbcm/MAINTAINERS
@@ -0,0 +1,6 @@
+MAXBCM BOARD
+M: Stefan Roese s...@denx.de
+S: Maintained
+F: board/maxbcm/
+F: include/configs/maxbcm.h
+F: configs/maxbcm_defconfig
diff --git a/board/maxbcm/Makefile b/board/maxbcm/Makefile
new file mode 100644
index 000..37c17d6
--- /dev/null
+++ b/board/maxbcm/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2014 Stefan Roese s...@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := maxbcm.o
diff --git a/board/maxbcm/kwbimage.cfg b/board/maxbcm/kwbimage.cfg
new file mode 100644
index 000..5a3bc67
--- /dev/null
+++ b/board/maxbcm/kwbimage.cfg
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2014 Stefan Roese s...@denx.de
+#
+
+# Armada XP uses version 1 image format
+VERSION1
+
+# Boot Media configurations
+BOOT_FROM spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY board/maxbcm/binary.0 005b 0068
diff --git a/board/maxbcm/maxbcm.c b/board/maxbcm/maxbcm.c
new file mode 100644
index 000..7fc83ee
--- /dev/null
+++ b/board/maxbcm/maxbcm.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2014 Stefan Roese s...@denx.de
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include miiphy.h
+#include asm/io.h
+#include asm/arch/cpu.h
+#include asm/arch/soc.h
+#include linux/mbus.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Base addresses for the external device chip selects */
+#define DEV_CS0_BASE 0xe000
+#define DEV_CS1_BASE 0xe100
+#define DEV_CS2_BASE 0xe200
+#define DEV_CS3_BASE 0xe300
+
+/* Needed for dynamic (board-specific) mbus configuration */
+extern struct mvebu_mbus_state mbus_state;
+
+int board_early_init_f(void)
+{
+ /*
+* Don't configure MPP (pin multiplexing) and GPIO here,
+* its already done in bin_hdr
+*/
+
+ /*
+* Setup some board specific mbus address windows
+*/
+ mbus_dt_setup_win(mbus_state, DEV_CS0_BASE, 16 20,
+ CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS0);
+ mbus_dt_setup_win(mbus_state, DEV_CS1_BASE, 16 20,
+ CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1);
+ mbus_dt_setup_win(mbus_state, DEV_CS2_BASE, 16 20,
+ CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS2);
+ mbus_dt_setup_win(mbus_state, DEV_CS3_BASE, 16 20,
+ CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS3);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd-bd-bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts(Board: maxBCM\n);
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and
Re: [U-Boot] make help talks about starred targets when nothing is starred
On Tue, 21 Oct 2014 16:23:24 -0400 (EDT) Robert P. J. Day rpj...@crashcourse.ca wrote: running make help concludes with the claim: Execute make or make all to build all targets marked with [*] but i see no make targets marked that way -- i suspect that was just a copy and paste from the kernel Makefile, yes? rday Yes. I think at least u-boot - Build the bare u-boot should be marked with * (although u-boot.bin and some other SoC-specific boot images are generally created.) Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] generic-board: make compile-time noise for non-generic boards
Commit 0f605c1501f6 (Start the deprecation process for generic board) added a run-time warning message. Let's be noisier for non-generic boards to inform the dead line of the conversion. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com Acked-by: Marek Vasut ma...@denx.de Cc: Tom Rini tr...@ti.com Cc: Simon Glass s...@chromium.org --- Changes in v2: - Mention to see doc/README.generic-board Makefile | 7 +++ 1 file changed, 7 insertions(+) diff --git a/Makefile b/Makefile index 99097e1..b28edcc 100644 --- a/Makefile +++ b/Makefile @@ -775,6 +775,13 @@ quiet_cmd_pad_cat = CAT $@ cmd_pad_cat = $(cmd_objcopy) $(append) || rm -f $@ all: $(ALL-y) +ifneq ($(CONFIG_SYS_GENERIC_BOARD),y) + @echo 2 = WARNING == + @echo 2 Please convert this board to generic board. + @echo 2 Otherwise it will be removed by the end of 2014. + @echo 2 See doc/README.generic-board for further information + @echo 2 +endif PHONY += dtbs dtbs dts/dt.dtb: checkdtc u-boot -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] nand: reinstate lazy bad block scanning
Commit ff94bc40af3481d47546595ba73c136de6af6929
(mtd, ubi, ubifs: resync with Linux-3.14)
accidentally reverted part of the commit
13f0fd94e3cae6f8a0d9fba5d367e311edc8ebde
(NAND: Scan bad blocks lazily.).
Reinstate the change as by commit
fb49454b1b6c7c6e238ac3c0b1e302e73eb1a1ea
(nand: reinstate lazy bad block scanning)
Signed-off-by: Rostislav Lisovy lis...@merica.cz
---
drivers/mtd/nand/nand_base.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 0b6e7ee..70e780c 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -634,6 +634,11 @@ static int nand_block_checkbad(struct mtd_info *mtd,
loff_t ofs, int getchip,
{
struct nand_chip *chip = mtd-priv;
+ if (!(chip-options NAND_BBT_SCANNED)) {
+ chip-scan_bbt(mtd);
+ chip-options |= NAND_BBT_SCANNED;
+ }
+
if (!chip-bbt)
return chip-block_bad(mtd, ofs, getchip);
@@ -4322,10 +4327,9 @@ int nand_scan_tail(struct mtd_info *mtd)
/* Check, if we should skip the bad block table scan */
if (chip-options NAND_SKIP_BBTSCAN)
- return 0;
+ chip-options |= NAND_BBT_SCANNED;
- /* Build bad block table */
- return chip-scan_bbt(mtd);
+ return 0;
}
EXPORT_SYMBOL(nand_scan_tail);
--
1.9.1
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Re: [U-Boot] [PATCH] mx6sabresd: Add Seiko WVGA panel support
Hi Jeroen, On Wed, Oct 22, 2014 at 6:47 AM, Jeroen Hofstee jer...@myspectrum.nl wrote: If [1] is a datasheet for this lcd, you likely want to add #include ../drivers/video/mxcfb.h .sync = FB_SYNC_CLK_LAT_FALL, Or something similar, since the data is sampled on the falling edge of the pixel clock / the pixel clock is inverted. We don't need this special FB_SYNC_CLK_LAT_FALL anymore. Please see this thread: http://driverdev.linuxdriverproject.org/pipermail/driverdev-devel/2013-October/042747.html ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] arm: mx6: add support for TBS2910 Matrix ARM miniPC
Hi Stefano!
On 10/22/14 10:36, Stefano Babic wrote:
Hi Soeren,
On 21/10/2014 19:54, Soeren Moch wrote:
This is also copied from sabresd. Can we factorize in some way ?
I can, and probably should, simplify this code. But in fact this code
is wrong, and in the same way for many imx6q boards (e.g. sabresd,
wandboard, nitrogen6x,...).
That makes things only worse. Duplicating the code, we have an
additional board with bad / wrong code.
This code configures the external video clock (LDB_DIx clock). This
clock is hardcoded to have 65MHz in drivers/video/ipu_common.c:ldb_clk.
But in fact the clock rate is configured to 75.42MHz (528MHz/7) on all
boards. So the display does not show 1024x768@60Hz as configured, but
something similar to 1024x768@70Hz (not VESA compliant), which much
monitors can handle, but on other monitors there are problems.
(one out of tree monitors works for me).
Ok, understood.
My intention was to get this initial support for tbs2910 merged with the
(wrong) code from sabresd used as template, and later to discuss how to
cleanup this code.
Do you prefer a simplified version of this code for the initial patch?
Maybe this is the best approach: you can at the beginning drop support
for video, an let your board be merged without wrong code. Then we can
discuss about fixing the wrong clock as shared code, letting that all
boards take advantage for that.
U-Boot without video support is useless for me. So I will try to
setup the video clock correctly in a new version of this patch.
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+int board_eth_init(bd_t *bis)
+{
+setup_iomux_enet();
+setup_pcie();
+
+return cpu_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+setup_iomux_uart();
+#ifdef CONFIG_VIDEO_IPUV3
+setup_display();
I do not understand why setup_display() should be called at this point.
Generally, board_early_init_f() is called to setup iomux for peripherals
needed before relocation, as uart, letting the rest of the setup in
board_init(). Why do you need here ?
In fact this was also copied from sabresd/wandboard/nitrogen6x.
My assumption was, that the clocks must be configured before the
ipu is initialized.
That is correct, but ipu is initialized by video_init() after
board_init() is called. Generally, board_early_init() is responsible for
setup some initial peripherals, for example the iomux for uart or for
RAM controller. The common initialization is then put into board_init().
I am expecting that you have no issues by moving setup_display() in the
board_init() function.
You are right here, there is no problem with setup_display() in board_init().
So I wonder why all imx6q boards have setup_display() in board_early_init(),
you even committed such code for mx6qsabreauto yesterday.
Best regards,
Soeren Moch
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Re: [U-Boot] [PATCH v3 6/6] sunxi: Kconfig: Unify sunxi Kconfig code
Hi, On 10/21/2014 09:03 PM, Ian Campbell wrote: On Sun, 2014-10-12 at 22:17 +0100, Ian Campbell wrote: -if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN6I || TARGET_SUN7I + default sun4i if TARGET_SUN4I + default sun5i if TARGET_SUN5I + default sun6i if TARGET_SUN5I There is a typo here which is apparent with MAKEALL -s sunxi, since it causes Colombus_defconfig not to build. Patch is below but given the breakage is only in u-boot-sunxi.git#next right now I think it would be better to fold it into the original patch. Good catch thanks, I've squashed this into the original commit and done a forced push to u-boot-sunxi/next with this. Regards, Hans ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Relocation issue - need help!
Hi,
I'm trying to track down a syntax error issue that gets triggered
when erasing the U-Boot image in NOR flash. Symptoms look like this:
= print update
update=protect off 0xfc00 +${filesize};erase 0xfc00
+${filesize};cp.b 20 0xfc00 ${filesize};protect on 0xfc00
+${filesize}
= run update
Un-Protected 2 sectors
.. done
Erased 2 sectors
syntax error
Protected 2 sectors
= run update
syntax error
git bisect found commit 199adb6 common/misc: sparse fixes as
culprit; breaking this down further showed a single line in
common/cli_hush.c to trigger the problem. This patch fixes it:
---
common/cli_hush.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/cli_hush.c b/common/cli_hush.c
index 38da5a0..5bbcfe6 100644
--- a/common/cli_hush.c
+++ b/common/cli_hush.c
@@ -3127,7 +3127,7 @@ static void mapset(const unsigned char *set, int code)
for (s=set; *s; s++) map[*s] = code;
}
-static void update_ifs_map(void)
+void update_ifs_map(void)
{
/* char *ifs and char map[256] are both globals. */
ifs = (uchar *)getenv(IFS);
--
1.8.3.1
But I still have bad feelings - symptoms indicate that this is
actually a relocation issue, as it only gets triggered when erasing
the U-Boot image in NOR flash, so probably there are still pointers to
data in NOR being used. This patch here is not suited to fix the
original cause of this issue. But then, I do not see where there
might be a relocation problem. To be sure I even verified that ifs
and map[] are really in RAM all the time.
Has anybody an idea how to further track this down? Or is the patch
above actually a real fix? If so, why?
Best regards,
Wolfgang Denk
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
Old programmers never die, they just branch to a new address.
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[U-Boot] [U-boot] [Patch] ARM: cmd_clock: generalize command usage description
The usage description of commands refers to headers of sources,
that is not correct. This patch is intended to fix it.
Also generalize code in order to reduce SoC dependent #ifdefs.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
Based on
[U-boot] [Patch v2] keystone: usb: add support of usb xhci
https://patchwork.ozlabs.org/patch/386506
arch/arm/cpu/armv7/keystone/cmd_clock.c | 24 -
arch/arm/include/asm/arch-keystone/clock-k2e.h | 43 +++---
arch/arm/include/asm/arch-keystone/clock-k2hk.h | 47 +
arch/arm/include/asm/arch-keystone/clock.h | 8 +
4 files changed, 61 insertions(+), 61 deletions(-)
diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c
b/arch/arm/cpu/armv7/keystone/cmd_clock.c
index d97c95b..af1b701 100644
--- a/arch/arm/cpu/armv7/keystone/cmd_clock.c
+++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c
@@ -58,20 +58,11 @@ pll_cmd_usage:
return cmd_usage(cmdtp);
}
-#ifdef CONFIG_SOC_K2HK
-U_BOOT_CMD(
- pllset, 5, 0, do_pll_cmd,
- set pll multiplier and pre divider,
- pa|arm|ddr3a|ddr3b mult div OD\n
-);
-#endif
-#ifdef CONFIG_SOC_K2E
U_BOOT_CMD(
pllset, 5, 0, do_pll_cmd,
set pll multiplier and pre divider,
- pa|ddr3 mult div OD\n
+ PLLSET_CMD_LIST mult div OD\n
);
-#endif
int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
@@ -95,12 +86,8 @@ U_BOOT_CMD(
getclk, 2, 0, do_getclk_cmd,
get clock rate,
clk index\n
-#ifdef CONFIG_SOC_K2HK
- See the 'enum clk_e' in the clock-k2hk.h for clk indexes\n
-#endif
-#ifdef CONFIG_SOC_K2E
- See the 'enum clk_e' in the clock-k2e.h for clk indexes\n
-#endif
+ The indexes for clocks:\n
+ CLOCK_INDEXES_LIST
);
int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -141,5 +128,8 @@ U_BOOT_CMD(
psc,3, 0, do_psc_cmd,
enable/disable psc module os disable domain,
mod/domain index en|di|domain\n
- See the hardware.h for Power and Sleep Controller (PSC) Domains\n
+ Intended to control Power and Sleep Controller (PSC) domains and\n
+ modules. The module or domain index exectly corresponds to ones\n
+ listed in official TRM. For instance, to enable MSMC RAM clock\n
+ domain use command: psc 14 en.\n
);
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2e.h
b/arch/arm/include/asm/arch-keystone/clock-k2e.h
index df33a78..d013b83 100644
--- a/arch/arm/include/asm/arch-keystone/clock-k2e.h
+++ b/arch/arm/include/asm/arch-keystone/clock-k2e.h
@@ -25,27 +25,28 @@ enum ext_clk_e {
extern unsigned int external_clk[ext_clk_count];
-enum clk_e {
- core_pll_clk,
- pass_pll_clk,
- ddr3_pll_clk,
- sys_clk0_clk,
- sys_clk0_1_clk,
- sys_clk0_2_clk,
- sys_clk0_3_clk,
- sys_clk0_4_clk,
- sys_clk0_6_clk,
- sys_clk0_8_clk,
- sys_clk0_12_clk,
- sys_clk0_24_clk,
- sys_clk1_clk,
- sys_clk1_3_clk,
- sys_clk1_4_clk,
- sys_clk1_6_clk,
- sys_clk1_12_clk,
- sys_clk2_clk,
- sys_clk3_clk
-};
+#define CLK_LIST(CLK)\
+ CLK(0, core_pll_clk)\
+ CLK(1, pass_pll_clk)\
+ CLK(2, ddr3_pll_clk)\
+ CLK(3, sys_clk0_clk)\
+ CLK(4, sys_clk0_1_clk)\
+ CLK(5, sys_clk0_2_clk)\
+ CLK(6, sys_clk0_3_clk)\
+ CLK(7, sys_clk0_4_clk)\
+ CLK(8, sys_clk0_6_clk)\
+ CLK(9, sys_clk0_8_clk)\
+ CLK(10, sys_clk0_12_clk)\
+ CLK(11, sys_clk0_24_clk)\
+ CLK(12, sys_clk1_clk)\
+ CLK(13, sys_clk1_3_clk)\
+ CLK(14, sys_clk1_4_clk)\
+ CLK(15, sys_clk1_6_clk)\
+ CLK(16, sys_clk1_12_clk)\
+ CLK(17, sys_clk2_clk)\
+ CLK(18, sys_clk3_clk)
+
+#define PLLSET_CMD_LISTpa|ddr3
#define KS2_CLK1_6 sys_clk0_6_clk
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2hk.h
b/arch/arm/include/asm/arch-keystone/clock-k2hk.h
index bdb869b..f28d5f0 100644
--- a/arch/arm/include/asm/arch-keystone/clock-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/clock-k2hk.h
@@ -28,29 +28,30 @@ enum ext_clk_e {
extern unsigned int external_clk[ext_clk_count];
-enum clk_e {
- core_pll_clk,
- pass_pll_clk,
- tetris_pll_clk,
- ddr3a_pll_clk,
- ddr3b_pll_clk,
- sys_clk0_clk,
- sys_clk0_1_clk,
- sys_clk0_2_clk,
- sys_clk0_3_clk,
- sys_clk0_4_clk,
- sys_clk0_6_clk,
- sys_clk0_8_clk,
- sys_clk0_12_clk,
- sys_clk0_24_clk,
- sys_clk1_clk,
- sys_clk1_3_clk,
- sys_clk1_4_clk,
- sys_clk1_6_clk,
- sys_clk1_12_clk,
- sys_clk2_clk,
- sys_clk3_clk
-};
+#define CLK_LIST(CLK)\
+ CLK(0, core_pll_clk)\
+ CLK(1, pass_pll_clk)\
+ CLK(2, tetris_pll_clk)\
+ CLK(3, ddr3a_pll_clk)\
+ CLK(4, ddr3b_pll_clk)\
+ CLK(5, sys_clk0_clk)\
+
Re: [U-Boot] [PATCH] mx6sabresd: Add Seiko WVGA panel support
Hello Fabio, On 22-10-14 14:15, Fabio Estevam wrote: Hi Jeroen, On Wed, Oct 22, 2014 at 6:47 AM, Jeroen Hofstee jer...@myspectrum.nl wrote: If [1] is a datasheet for this lcd, you likely want to add #include ../drivers/video/mxcfb.h .sync = FB_SYNC_CLK_LAT_FALL, Or something similar, since the data is sampled on the falling edge of the pixel clock / the pixel clock is inverted. We don't need this special FB_SYNC_CLK_LAT_FALL anymore. Please see this thread: http://driverdev.linuxdriverproject.org/pipermail/driverdev-devel/2013-October/042747.html Did you check this with a scope? I am quite sure I needed to do this for u-boot v2014.10 still, but I don't have the board available now to double check. Regards, Jeroen ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mx6sabresd: Add Seiko WVGA panel support
On Wed, Oct 22, 2014 at 11:07 AM, Jeroen Hofstee jer...@myspectrum.nl wrote: Did you check this with a scope? I am quite sure I needed to do this for u-boot v2014.10 still, but I don't have the board available now to double check. I didn't check it with the scope. If I add FB_SYNC_CLK_LAT_FALL then I get a completely bad image in the display. Regards, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mx6sabresd: Add Seiko WVGA panel support
On 22-10-14 15:10, Fabio Estevam wrote: On Wed, Oct 22, 2014 at 11:07 AM, Jeroen Hofstee jer...@myspectrum.nl wrote: Did you check this with a scope? I am quite sure I needed to do this for u-boot v2014.10 still, but I don't have the board available now to double check. I didn't check it with the scope. If I add FB_SYNC_CLK_LAT_FALL then I get a completely bad image in the display. Regards, Fabio Estevam ok, thanks. If I will have a better look why I needed to set this once I have a chance. Regards, Jeroen ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ot1200: fix sf detection
On 22/10/14 12:29, Christian Gmeiner wrote:
Commit 155fa9af95ac5be857a7327e7a968a296e60d4c8 changed the way
to define a GPIO line, which can be used to force CS high
across multiple transactions. In order to fix sf detection
change board code to make use of board_spi_cs_gpio(..).
Signed-off-by: Christian Gmeiner christian.gmei...@gmail.com
---
board/bachmann/ot1200/ot1200.c | 5 +
include/configs/ot1200.h | 2 +-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c
index 0d5ede5..2962e0c 100644
--- a/board/bachmann/ot1200/ot1200.c
+++ b/board/bachmann/ot1200/ot1200.c
@@ -98,6 +98,11 @@ static void setup_iomux_spi(void)
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
}
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 2 cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1;
+}
+
int board_early_init_f(void)
{
setup_iomux_uart();
diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
index 071880f..d7696bd 100644
--- a/include/configs/ot1200.h
+++ b/include/configs/ot1200.h
@@ -47,7 +47,7 @@
#define CONFIG_SPI_FLASH_SST
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 2
-#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(1, 3)8))
+#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 2500
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
Acked-by: Nikita Kiryanov nik...@compulab.co.il
--
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Nikita Kiryanov
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[U-Boot] [RFC] fs: make it possible to read the filesystem UUID
Some filesystems have a UUID stored in its superblock. To
allow using root=UUID=... for the kernel command line we
need a way to read-out the filesystem UUID. This is what this
patch tries to do.
Keep in mind that this patch is an RFC and I hope to get some
feedback on this patch.
This is what blkid under linux gives me:
/dev/sdh1: LABEL=data UUID=b6995cec-97e2-48b8-94dc-8ba7afc92bac TYPE=ext4
PARTUUID=43f21f0e-01
/dev/sdh2: LABEL=rfs UUID=8d020de7-c75e-4674-948e-f7838a931b02 TYPE=ext4
PARTUUID=43f21f0e-02
And here is the output from u-boot:
= sata init
AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
flags: ncq stag pm led clo only pmp pio slum part
SATA Device Info:
S/N: 60059798A114
Product model number: SFCA4096H1BR4TO-I-MS-236-STD
Firmware version: 20111021
Capacity: 7793856 sectors
= fs_uuid sata 0:1 ; print fs_uuid; fs_uuid sata 0:2 ; print fs_uuid
fs_uuid=b6995cec-97e2-48b8-94dc-8ba7afc92bac
fs_uuid=8d020de7-c75e-4674-948e-f7838a931b02
Signed-off-by: Christian Gmeiner christian.gmei...@gmail.com
---
common/Makefile | 1 +
common/cmd_fs_uuid.c | 23 +++
fs/ext4/ext4_common.c | 9 +
fs/fs.c | 28
include/ext4fs.h | 1 +
include/fs.h | 2 ++
6 files changed, 64 insertions(+)
create mode 100644 common/cmd_fs_uuid.c
diff --git a/common/Makefile b/common/Makefile
index b19d379..d5d3315 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -188,6 +188,7 @@ obj-y += usb.o usb_hub.o
obj-$(CONFIG_USB_STORAGE) += usb_storage.o
endif
obj-$(CONFIG_CMD_FASTBOOT) += cmd_fastboot.o
+obj-$(CONFIG_CMD_FS_UUID) += cmd_fs_uuid.o
obj-$(CONFIG_CMD_USB_MASS_STORAGE) += cmd_usb_mass_storage.o
obj-$(CONFIG_CMD_THOR_DOWNLOAD) += cmd_thordown.o
diff --git a/common/cmd_fs_uuid.c b/common/cmd_fs_uuid.c
new file mode 100644
index 000..3af9518
--- /dev/null
+++ b/common/cmd_fs_uuid.c
@@ -0,0 +1,23 @@
+/*
+ * cmd_fs_uuid.c -- fs_uuid command
+ *
+ * Copyright (C) 2014, Bachmann electronic GmbH
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include command.h
+#include fs.h
+
+static int do_fs_uuid_wrapper(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
+{
+ return do_fs_uuid(cmdtp, flag, argc, argv, FS_TYPE_ANY);
+}
+
+U_BOOT_CMD(
+ fs_uuid,3, 0, do_fs_uuid_wrapper,
+ filesystem UUDI related commands,
+ interface dev:part\n
+ - print filesystem UUID\n
+);
diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index 33d69c9..926b6c6 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -2246,3 +2246,12 @@ fail:
return 0;
}
+
+void ext4fs_uuid(char *uuid_str)
+{
+ if (ext4fs_root == NULL)
+ return;
+
+ uuid_bin_to_str((unsigned char *)ext4fs_root-sblock.unique_id,
uuid_str,
+ UUID_STR_FORMAT_STD);
+}
diff --git a/fs/fs.c b/fs/fs.c
index dd680f3..f8c6d64 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -85,6 +85,7 @@ struct fstype_info {
int (*size)(const char *filename);
int (*read)(const char *filename, void *buf, int offset, int len);
int (*write)(const char *filename, void *buf, int offset, int len);
+ void (*uuid)(char *uuid_str);
void (*close)(void);
};
@@ -113,6 +114,7 @@ static struct fstype_info fstypes[] = {
.size = ext4fs_size,
.read = ext4_read_file,
.write = fs_write_unsupported,
+ .uuid = ext4fs_uuid,
},
#endif
#ifdef CONFIG_SANDBOX
@@ -206,6 +208,14 @@ static void fs_close(void)
fs_type = FS_TYPE_ANY;
}
+void fs_uuid(char *uuid_str)
+{
+ struct fstype_info *info = fs_get_info(fs_type);
+
+ if (info-uuid)
+ info-uuid(uuid_str);
+}
+
int fs_ls(const char *dirname)
{
int ret;
@@ -289,6 +299,24 @@ int fs_write(const char *filename, ulong addr, int offset,
int len)
return ret;
}
+int do_fs_uuid(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+ int fstype)
+{
+ char uuid[37];
+ memset(uuid, 0, sizeof(uuid));
+
+ if (argc != 3)
+ return CMD_RET_USAGE;
+
+ if (fs_set_blk_dev(argv[1], argv[2], fstype))
+ return 1;
+
+ fs_uuid(uuid);
+ setenv(fs_uuid, uuid);
+
+ return 0;
+}
+
int do_size(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
int fstype)
{
diff --git a/include/ext4fs.h b/include/ext4fs.h
index 6c419f3..4011370 100644
--- a/include/ext4fs.h
+++ b/include/ext4fs.h
@@ -132,6 +132,7 @@ struct ext_filesystem *get_fs(void);
int ext4fs_open(const char *filename);
int ext4fs_read(char *buf, unsigned len);
int ext4fs_mount(unsigned part_length);
+void ext4fs_uuid(char *uuid_str);
void ext4fs_close(void);
void ext4fs_reinit_global(void);
int ext4fs_ls(const char *dirname);
diff --git a/include/fs.h b/include/fs.h
index 06a45f2..1956b67 100644
---
[U-Boot] [U-boot] [Patch v6 5/6] keystone2: enable OSR clock domain for K2L SoC
From: Hao Zhang hzh...@ti.com
This patches enables the On-chip Shared Ram clock domain for K2L SoC.
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/cpu/armv7/keystone/init.c| 51 +++
arch/arm/include/asm/arch-keystone/hardware-k2l.h | 24 +++
arch/arm/include/asm/arch-keystone/hardware.h | 1 +
3 files changed, 76 insertions(+)
diff --git a/arch/arm/cpu/armv7/keystone/init.c
b/arch/arm/cpu/armv7/keystone/init.c
index 62081b7..c2b9478 100644
--- a/arch/arm/cpu/armv7/keystone/init.c
+++ b/arch/arm/cpu/armv7/keystone/init.c
@@ -13,6 +13,7 @@
#include asm/arch/msmc.h
#include asm/arch/clock.h
#include asm/arch/hardware.h
+#include asm/arch/psc_defs.h
void chip_configuration_unlock(void)
{
@@ -20,6 +21,53 @@ void chip_configuration_unlock(void)
__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
}
+#ifdef CONFIG_SOC_K2L
+void osr_init(void)
+{
+ u32 i;
+ u32 j;
+ u32 val;
+ u32 base = KS2_OSR_CFG_BASE;
+ u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
+
+ /* Enable the OSR clock domain */
+ psc_enable_module(KS2_LPSC_OSR);
+
+ /* Disable OSR ECC check for all the ram banks */
+ for (i = 0; i KS2_OSR_NUM_RAM_BANKS; i++) {
+ val = i | KS2_OSR_ECC_VEC_TRIG_RD |
+ (KS2_OSR_ECC_CTRL KS2_OSR_ECC_VEC_RD_ADDR_SH);
+
+ writel(val , base + KS2_OSR_ECC_VEC);
+
+ /**
+* wait till read is done.
+* Print should be added after earlyprintk support is added.
+*/
+ for (j = 0; j 1; j++) {
+ val = readl(base + KS2_OSR_ECC_VEC);
+ if (val KS2_OSR_ECC_VEC_RD_DONE)
+ break;
+ }
+
+ ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
+ KS2_OSR_ECC_CTRL_CHK;
+
+ writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
+ writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
+ }
+
+ /* Reset OSR memory to all zeros */
+ for (i = 0; i KS2_OSR_SIZE; i += 4)
+ writel(0, KS2_OSR_DATA_BASE + i);
+
+ /* Enable OSR ECC check for all the ram banks */
+ for (i = 0; i KS2_OSR_NUM_RAM_BANKS; i++)
+ writel(ecc_ctrl[i] |
+ KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
+}
+#endif
+
int arch_cpu_init(void)
{
chip_configuration_unlock();
@@ -32,6 +80,9 @@ int arch_cpu_init(void)
#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1);
#endif
+#ifdef CONFIG_SOC_K2L
+ osr_init();
+#endif
/*
* just initialise the COM2 port so that TI specific
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2l.h
b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
index c1fa3af..05532ad 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2l.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
@@ -60,6 +60,30 @@
#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3
#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D
+/* OSR */
+#define KS2_OSR_DATA_BASE 0x7000 /* OSR data base */
+#define KS2_OSR_CFG_BASE 0x02348c00 /* OSR config base */
+#define KS2_OSR_ECC_VEC0x08/* ECC Vector
reg */
+#define KS2_OSR_ECC_CTRL 0x14/* ECC control reg */
+
+/* OSR ECC Vector register */
+#define KS2_OSR_ECC_VEC_TRIG_RDBIT(15) /* trigger a
read op */
+#define KS2_OSR_ECC_VEC_RD_DONEBIT(24) /* read
complete */
+
+#define KS2_OSR_ECC_VEC_RAM_ID_SH 0 /* RAM ID shift */
+#define KS2_OSR_ECC_VEC_RD_ADDR_SH 16 /* read address shift */
+
+/* OSR ECC control register */
+#define KS2_OSR_ECC_CTRL_ENBIT(0) /* ECC enable bit */
+#define KS2_OSR_ECC_CTRL_CHK BIT(1) /* ECC check bit */
+#define KS2_OSR_ECC_CTRL_RMW BIT(2) /* ECC check bit */
+
+/* Number of OSR RAM banks */
+#define KS2_OSR_NUM_RAM_BANKS 4
+
+/* OSR memory size */
+#define KS2_OSR_SIZE 0x10
+
/* Number of DSP cores */
#define KS2_NUM_DSPS 4
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h
b/arch/arm/include/asm/arch-keystone/hardware.h
index 295c6b0..08a7c70 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -142,6 +142,7 @@ typedef volatile unsigned int *dv_reg_p;
/* MSMC control */
#define KS2_MSMC_CTRL_BASE 0x0bc0
+#define KS2_MSMC_DATA_BASE 0x0c00
#define KS2_MSMC_SEGMENT_TETRIS8
#define KS2_MSMC_SEGMENT_NETCP 9
#define KS2_MSMC_SEGMENT_QM_PDSP 10
--
1.8.3.2
[U-Boot] [U-boot] [Patch v6 4/6] ARM: keystone2: spl: move board specific code
From: Hao Zhang hzh...@ti.com
The initialization of PLLs is a part of board specific code, so
move it appropriate places.
Acked-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/cpu/armv7/keystone/Makefile | 1 -
arch/arm/cpu/armv7/keystone/spl.c| 53
arch/arm/include/asm/arch-keystone/spl.h | 12
board/ti/ks2_evm/board.c | 19
board/ti/ks2_evm/board.h | 1 +
board/ti/ks2_evm/board_k2e.c | 11 +++
board/ti/ks2_evm/board_k2hk.c| 12
7 files changed, 43 insertions(+), 66 deletions(-)
delete mode 100644 arch/arm/cpu/armv7/keystone/spl.c
delete mode 100644 arch/arm/include/asm/arch-keystone/spl.h
diff --git a/arch/arm/cpu/armv7/keystone/Makefile
b/arch/arm/cpu/armv7/keystone/Makefile
index 4750371..57f6ea6 100644
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ b/arch/arm/cpu/armv7/keystone/Makefile
@@ -14,6 +14,5 @@ obj-$(CONFIG_SOC_K2L) += clock-k2l.o
obj-y += cmd_clock.o
obj-y += cmd_mon.o
obj-y += msmc.o
-obj-$(CONFIG_SPL_BUILD)+= spl.o
obj-y += ddr3.o
obj-y += keystone.o
diff --git a/arch/arm/cpu/armv7/keystone/spl.c
b/arch/arm/cpu/armv7/keystone/spl.c
deleted file mode 100644
index d4b0e9b..000
--- a/arch/arm/cpu/armv7/keystone/spl.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * common spl init code
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, www.ti.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include common.h
-#include config.h
-#include ns16550.h
-#include malloc.h
-#include spl.h
-#include spi_flash.h
-
-#include asm/u-boot.h
-#include asm/utils.h
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_K2HK_EVM
-static struct pll_init_data spl_pll_config[] = {
- CORE_PLL_799,
- TETRIS_PLL_500,
-};
-#endif
-
-#ifdef CONFIG_K2E_EVM
-static struct pll_init_data spl_pll_config[] = {
- CORE_PLL_800,
-};
-#endif
-
-void spl_init_keystone_plls(void)
-{
- init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
-}
-
-void spl_board_init(void)
-{
- spl_init_keystone_plls();
- preloader_console_init();
-}
-
-u32 spl_boot_device(void)
-{
-#if defined(CONFIG_SPL_SPI_LOAD)
- return BOOT_DEVICE_SPI;
-#else
- puts(Unknown boot device\n);
- hang();
-#endif
-}
diff --git a/arch/arm/include/asm/arch-keystone/spl.h
b/arch/arm/include/asm/arch-keystone/spl.h
deleted file mode 100644
index a7102d5..000
--- a/arch/arm/include/asm/arch-keystone/spl.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * (C) Copyright 2012-2014
- * Texas Instruments, www.ti.com
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-#ifndef _ASM_ARCH_SPL_H_
-#define _ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_SPI2
-
-#endif
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index dfe7be6..c07d284 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -9,6 +9,7 @@
#include board.h
#include common.h
+#include spl.h
#include exports.h
#include fdt_support.h
#include asm/arch/ddr3.h
@@ -83,6 +84,24 @@ int board_eth_init(bd_t *bis)
}
#endif
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+ spl_init_keystone_plls();
+ preloader_console_init();
+}
+
+u32 spl_boot_device(void)
+{
+#if defined(CONFIG_SPL_SPI_LOAD)
+ return BOOT_DEVICE_SPI;
+#else
+ puts(Unknown boot device\n);
+ hang();
+#endif
+}
+#endif
+
#if defined(CONFIG_OF_LIBFDT) defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
diff --git a/board/ti/ks2_evm/board.h b/board/ti/ks2_evm/board.h
index d91ef73..7a613ac 100644
--- a/board/ti/ks2_evm/board.h
+++ b/board/ti/ks2_evm/board.h
@@ -15,5 +15,6 @@
extern struct eth_priv_t eth_priv_cfg[];
int get_num_eth_ports(void);
+void spl_init_keystone_plls(void);
#endif
diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c
index 5472a43..810a8e2 100644
--- a/board/ti/ks2_evm/board_k2e.c
+++ b/board/ti/ks2_evm/board_k2e.c
@@ -52,3 +52,14 @@ int board_early_init_f(void)
return 0;
}
#endif
+
+#ifdef CONFIG_SPL_BUILD
+static struct pll_init_data spl_pll_config[] = {
+ CORE_PLL_800,
+};
+
+void spl_init_keystone_plls(void)
+{
+ init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
+}
+#endif
diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c
index 6fb3d21..d7dd292 100644
--- a/board/ti/ks2_evm/board_k2hk.c
+++ b/board/ti/ks2_evm/board_k2hk.c
@@ -100,3 +100,15 @@ int board_early_init_f(void)
return 0;
}
#endif
+
+#ifdef CONFIG_SPL_BUILD
+static struct pll_init_data spl_pll_config[] = {
+ CORE_PLL_799,
+ TETRIS_PLL_500,
+};
+
+void spl_init_keystone_plls(void)
+{
+ init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
+}
+#endif
--
1.8.3.2
___
U-Boot mailing list
U-Boot@lists.denx.de
[U-Boot] [U-boot] [Patch v6 2/6] keystone2: clock: add K2L clock definitions and commands
From: Hao Zhang hzh...@ti.com
This patch adds clock definitions and commands to support Keystone II
K2L SOC.
Acked-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/cpu/armv7/keystone/Makefile | 1 +
arch/arm/cpu/armv7/keystone/clock-k2l.c| 138 +
arch/arm/include/asm/arch-keystone/clock-k2l.h | 89
arch/arm/include/asm/arch-keystone/clock.h | 4 +
4 files changed, 232 insertions(+)
create mode 100644 arch/arm/cpu/armv7/keystone/clock-k2l.c
create mode 100644 arch/arm/include/asm/arch-keystone/clock-k2l.h
diff --git a/arch/arm/cpu/armv7/keystone/Makefile
b/arch/arm/cpu/armv7/keystone/Makefile
index 3d8fb70..4750371 100644
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ b/arch/arm/cpu/armv7/keystone/Makefile
@@ -10,6 +10,7 @@ obj-y += psc.o
obj-y += clock.o
obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
obj-$(CONFIG_SOC_K2E) += clock-k2e.o
+obj-$(CONFIG_SOC_K2L) += clock-k2l.o
obj-y += cmd_clock.o
obj-y += cmd_mon.o
obj-y += msmc.o
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2l.c
b/arch/arm/cpu/armv7/keystone/clock-k2l.c
new file mode 100644
index 000..1c5e4d5
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/clock-k2l.c
@@ -0,0 +1,138 @@
+/*
+ * Keystone2: get clk rate for K2L
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/arch/clock.h
+#include asm/arch/clock_defs.h
+
+const struct keystone_pll_regs keystone_pll_regs[] = {
+ [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+ [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+ [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
+ [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+};
+
+int dev_speeds[] = {
+ SPD800,
+ SPD1000,
+ SPD1200,
+ SPD800,
+ SPD800,
+ SPD800,
+ SPD800,
+ SPD800,
+ SPD1200,
+ SPD1000,
+ SPD800,
+ SPD800,
+ SPD800,
+};
+
+int arm_speeds[] = {
+ SPD800,
+ SPD1000,
+ SPD1200,
+ SPD1350,
+ SPD1400,
+ SPD800,
+ SPD1400,
+ SPD1350,
+ SPD1200,
+ SPD1000,
+ SPD800,
+ SPD800,
+ SPD800,
+};
+
+/**
+ * pll_freq_get - get pll frequency
+ * Fout = Fref * NF(mult) / NR(prediv) / OD
+ * @pll: pll identifier
+ */
+static unsigned long pll_freq_get(int pll)
+{
+ unsigned long mult = 1, prediv = 1, output_div = 2;
+ unsigned long ret;
+ u32 tmp, reg;
+
+ if (pll == CORE_PLL) {
+ ret = external_clk[sys_clk];
+ if (pllctl_reg_read(pll, ctl) PLLCTL_PLLEN) {
+ /* PLL mode */
+ tmp = __raw_readl(KS2_MAINPLLCTL0);
+ prediv = (tmp PLL_DIV_MASK) + 1;
+ mult = (((tmp PLLM_MULT_HI_SMASK) 6) |
+ (pllctl_reg_read(pll, mult)
+ PLLM_MULT_LO_MASK)) + 1;
+ output_div = ((pllctl_reg_read(pll, secctl)
+ PLL_CLKOD_SHIFT) PLL_CLKOD_MASK) + 1;
+
+ ret = ret / prediv / output_div * mult;
+ }
+ } else {
+ switch (pll) {
+ case PASS_PLL:
+ ret = external_clk[pa_clk];
+ reg = KS2_PASSPLLCTL0;
+ break;
+ case TETRIS_PLL:
+ ret = external_clk[tetris_clk];
+ reg = KS2_ARMPLLCTL0;
+ break;
+ case DDR3_PLL:
+ ret = external_clk[ddr3_clk];
+ reg = KS2_DDR3APLLCTL0;
+ break;
+ default:
+ return 0;
+ }
+
+ tmp = __raw_readl(reg);
+ if (!(tmp PLLCTL_BYPASS)) {
+ /* Bypass disabled */
+ prediv = (tmp PLL_DIV_MASK) + 1;
+ mult = ((tmp PLL_MULT_SHIFT) PLL_MULT_MASK) + 1;
+ output_div = ((tmp PLL_CLKOD_SHIFT)
+ PLL_CLKOD_MASK) + 1;
+ ret = ((ret / prediv) * mult) / output_div;
+ }
+ }
+
+ return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+ switch (clk) {
+ case core_pll_clk: return pll_freq_get(CORE_PLL);
+ case pass_pll_clk: return pll_freq_get(PASS_PLL);
+ case tetris_pll_clk:return pll_freq_get(TETRIS_PLL);
+ case ddr3_pll_clk: return pll_freq_get(DDR3_PLL);
+ case sys_clk0_1_clk:
+ case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
+ case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
[U-Boot] [U-boot] [Patch v6 0/6] keystone2: add k2l SoC and k2l_evm board support
This patch series adds Keystone II Lamar (K2L) SoC and k2l_evm board support. Based on [U-Boot,U-boot] ARM: cmd_clock: generalize command usage description http://patchwork.ozlabs.org/patch/402102/ v6..v5 - keystone2: clock: add K2L clock definitions and commands update according to changes made by [U-Boot,U-boot] ARM: cmd_clock: generalize command usage description http://patchwork.ozlabs.org/patch/402102/ - keystone2: msmc: add MSMC cache coherency support for K2L SOC added definitions for msmc segment numbers v5..v4 - ARM: keystone2: spl: move board specific code this patch replace ARM: keystone2: spl: add K2L SoC support as result of moving board specific code to board directory. v4..v3 - keystone2: k2l-evm: add board support remove dimm name reading v3..v2 - keystone2: k2l-evm: add board support Add maintainers information Enable SPL by default v2..v1 Rebased according to changes of c338f09e965a300ddd78af73e86c4af4c9464ce4 keystone: kconfig: move board select menu and common settings Hao Zhang (6): ARM: keystone2: add K2L device hardware definitions keystone2: clock: add K2L clock definitions and commands keystone2: msmc: add MSMC cache coherency support for K2L SOC ARM: keystone2: spl: move board specific code keystone2: enable OSR clock domain for K2L SoC keystone2: k2l-evm: add board support arch/arm/cpu/armv7/keystone/Kconfig| 3 + arch/arm/cpu/armv7/keystone/Makefile | 2 +- arch/arm/cpu/armv7/keystone/clock-k2l.c| 138 + arch/arm/cpu/armv7/keystone/init.c | 63 +- arch/arm/cpu/armv7/keystone/spl.c | 53 arch/arm/include/asm/arch-keystone/clock-k2l.h | 95 ++ arch/arm/include/asm/arch-keystone/clock.h | 4 + arch/arm/include/asm/arch-keystone/hardware-k2e.h | 3 + arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 2 - arch/arm/include/asm/arch-keystone/hardware-k2l.h | 101 +++ arch/arm/include/asm/arch-keystone/hardware.h | 24 +++- arch/arm/include/asm/arch-keystone/spl.h | 12 -- board/ti/ks2_evm/Kconfig | 16 +++ board/ti/ks2_evm/MAINTAINERS | 2 + board/ti/ks2_evm/Makefile | 2 + board/ti/ks2_evm/board.c | 19 +++ board/ti/ks2_evm/board.h | 1 + board/ti/ks2_evm/board_k2e.c | 11 ++ board/ti/ks2_evm/board_k2hk.c | 12 ++ board/ti/ks2_evm/board_k2l.c | 72 +++ board/ti/ks2_evm/ddr3_cfg.c| 36 ++ board/ti/ks2_evm/ddr3_cfg.h| 3 + board/ti/ks2_evm/ddr3_k2l.c| 38 ++ configs/k2l_evm_defconfig | 4 + include/configs/k2l_evm.h | 37 ++ 25 files changed, 676 insertions(+), 77 deletions(-) create mode 100644 arch/arm/cpu/armv7/keystone/clock-k2l.c delete mode 100644 arch/arm/cpu/armv7/keystone/spl.c create mode 100644 arch/arm/include/asm/arch-keystone/clock-k2l.h create mode 100644 arch/arm/include/asm/arch-keystone/hardware-k2l.h delete mode 100644 arch/arm/include/asm/arch-keystone/spl.h create mode 100644 board/ti/ks2_evm/board_k2l.c create mode 100644 board/ti/ks2_evm/ddr3_k2l.c create mode 100644 configs/k2l_evm_defconfig create mode 100644 include/configs/k2l_evm.h -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch v6 1/6] ARM: keystone2: add K2L device hardware definitions
From: Hao Zhang hzh...@ti.com
This patch adds hardware definitions specific to Keystone II
Lamar (K2L) SoC.
Acked-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 2 -
arch/arm/include/asm/arch-keystone/hardware-k2l.h | 74 ++
arch/arm/include/asm/arch-keystone/hardware.h | 13
3 files changed, 87 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/include/asm/arch-keystone/hardware-k2l.h
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
index 43c2c42..2db806c 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
@@ -10,8 +10,6 @@
#ifndef __ASM_ARCH_HARDWARE_K2HK_H
#define __ASM_ARCH_HARDWARE_K2HK_H
-#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
-
#define KS2_ARM_PLL_EN BIT(13)
/* PA SS Registers */
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2l.h
b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
new file mode 100644
index 000..3402d0c
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
@@ -0,0 +1,74 @@
+/*
+ * K2L: SoC definitions
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_K2L_H
+#define __ASM_ARCH_HARDWARE_K2L_H
+
+#define KS2_ARM_PLL_EN BIT(13)
+
+/* PA SS Registers */
+#define KS2_PASS_BASE 0x2600
+
+/* Power and Sleep Controller (PSC) Domains */
+#define KS2_LPSC_MOD 0
+#define KS2_LPSC_DFE_IQN_SYS 1
+#define KS2_LPSC_USB 2
+#define KS2_LPSC_EMIF25_SPI3
+#define KS2_LPSC_TSIP 4
+#define KS2_LPSC_DEBUGSS_TRC 5
+#define KS2_LPSC_TETB_TRC 6
+#define KS2_LPSC_PKTPROC 7
+#define KS2_LPSC_PAKS2_LPSC_PKTPROC
+#define KS2_LPSC_SGMII 8
+#define KS2_LPSC_CPGMACKS2_LPSC_SGMII
+#define KS2_LPSC_CRYPTO9
+#define KS2_LPSC_PCIE0 10
+#define KS2_LPSC_PCIE1 11
+#define KS2_LPSC_JESD_MISC 12
+#define KS2_LPSC_CHIP_SRSS 13
+#define KS2_LPSC_MSMC 14
+#define KS2_LPSC_GEM_1 16
+#define KS2_LPSC_GEM_2 17
+#define KS2_LPSC_GEM_3 18
+#define KS2_LPSC_EMIF4F_DDR3 23
+#define KS2_LPSC_TAC 25
+#define KS2_LPSC_RAC 26
+#define KS2_LPSC_DDUC4X_CFR2X_BB 27
+#define KS2_LPSC_FFTC_A28
+#define KS2_LPSC_OSR 34
+#define KS2_LPSC_TCP3D_0 35
+#define KS2_LPSC_TCP3D_1 37
+#define KS2_LPSC_VCP2X4_A 39
+#define KS2_LPSC_VCP2X4_B 40
+#define KS2_LPSC_VCP2X4_C 41
+#define KS2_LPSC_VCP2X4_D 42
+#define KS2_LPSC_BCP 47
+#define KS2_LPSC_DPD4X 48
+#define KS2_LPSC_FFTC_B49
+#define KS2_LPSC_IQN_AIL 50
+
+/* Chip Interrupt Controller */
+#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3
+#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D
+
+/* Number of DSP cores */
+#define KS2_NUM_DSPS 4
+
+/* NETCP pktdma */
+#define KS2_NETCP_PDMA_CTRL_BASE 0x26186000
+#define KS2_NETCP_PDMA_TX_BASE 0x26187000
+#define KS2_NETCP_PDMA_TX_CH_NUM 21
+#define KS2_NETCP_PDMA_RX_BASE 0x26188000
+#define KS2_NETCP_PDMA_RX_CH_NUM 91
+#define KS2_NETCP_PDMA_SCHED_BASE 0x26186100
+#define KS2_NETCP_PDMA_RX_FLOW_BASE0x26189000
+#define KS2_NETCP_PDMA_RX_FLOW_NUM 96
+#define KS2_NETCP_PDMA_TX_SND_QUEUE896
+
+#endif /* __ASM_ARCH_HARDWARE_K2L_H */
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h
b/arch/arm/include/asm/arch-keystone/hardware.h
index c1642a5..adae69e 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -143,6 +143,7 @@ typedef volatile unsigned int *dv_reg_p;
/* Device speed */
#define KS2_REV1_DEVSPEED (KS2_DEVICE_STATE_CTRL_BASE + 0xc98)
#define KS2_EFUSE_BOOTROM (KS2_DEVICE_STATE_CTRL_BASE + 0xc90)
+#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
/* Queue manager */
#define KS2_QM_BASE_ADDRESS0x23a8
@@ -177,6 +178,10 @@ typedef volatile unsigned int *dv_reg_p;
#include asm/arch/hardware-k2e.h
#endif
+#ifdef CONFIG_SOC_K2L
+#include asm/arch/hardware-k2l.h
+#endif
+
#ifndef __ASSEMBLY__
static inline int cpu_is_k2hk(void)
{
@@ -194,6 +199,14 @@ static inline int cpu_is_k2e(void)
return (part_no == 0xb9a6) ? 1 : 0;
}
[U-Boot] [U-boot] [Patch v6 3/6] keystone2: msmc: add MSMC cache coherency support for K2L SOC
From: Hao Zhang hzh...@ti.com This patch adds Keystone II Lamar (K2L) SoC specific definitions to support MSMC cache coherency. Acked-by: Vitaly Andrianov vita...@ti.com Signed-off-by: Hao Zhang hzh...@ti.com Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- arch/arm/cpu/armv7/keystone/init.c| 12 ++-- arch/arm/include/asm/arch-keystone/hardware-k2e.h | 3 +++ arch/arm/include/asm/arch-keystone/hardware-k2l.h | 3 +++ arch/arm/include/asm/arch-keystone/hardware.h | 10 +++--- 4 files changed, 19 insertions(+), 9 deletions(-) diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c index a8f8aee..62081b7 100644 --- a/arch/arm/cpu/armv7/keystone/init.c +++ b/arch/arm/cpu/armv7/keystone/init.c @@ -25,12 +25,12 @@ int arch_cpu_init(void) chip_configuration_unlock(); icache_enable(); - msmc_share_all_segments(8); /* TETRIS */ - msmc_share_all_segments(9); /* NETCP */ - msmc_share_all_segments(10); /* QM PDSP */ - msmc_share_all_segments(11); /* PCIE 0 */ -#ifdef CONFIG_SOC_K2E - msmc_share_all_segments(13); /* PCIE 1 */ + msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS); + msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP); + msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP); + msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0); +#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) + msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1); #endif /* diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2e.h b/arch/arm/include/asm/arch-keystone/hardware-k2e.h index 62172a4..a70c184 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2e.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2e.h @@ -34,6 +34,9 @@ #define KS2_LPSC_PCIE_127 #define KS2_LPSC_XGE 50 +/* MSMC */ +#define KS2_MSMC_SEGMENT_PCIE1 13 + /* Chip Interrupt Controller */ #define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */ #define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */ diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2l.h b/arch/arm/include/asm/arch-keystone/hardware-k2l.h index 3402d0c..c1fa3af 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2l.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2l.h @@ -53,6 +53,9 @@ #define KS2_LPSC_FFTC_B49 #define KS2_LPSC_IQN_AIL 50 +/* MSMC */ +#define KS2_MSMC_SEGMENT_PCIE1 14 + /* Chip Interrupt Controller */ #define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3 #define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h index adae69e..295c6b0 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -140,6 +140,13 @@ typedef volatile unsigned int *dv_reg_p; /* Flag from ks2_debug options to check if DSPs need to stay ON */ #define DBG_LEAVE_DSPS_ON 0x1 +/* MSMC control */ +#define KS2_MSMC_CTRL_BASE 0x0bc0 +#define KS2_MSMC_SEGMENT_TETRIS8 +#define KS2_MSMC_SEGMENT_NETCP 9 +#define KS2_MSMC_SEGMENT_QM_PDSP 10 +#define KS2_MSMC_SEGMENT_PCIE0 11 + /* Device speed */ #define KS2_REV1_DEVSPEED (KS2_DEVICE_STATE_CTRL_BASE + 0xc98) #define KS2_EFUSE_BOOTROM (KS2_DEVICE_STATE_CTRL_BASE + 0xc90) @@ -161,9 +168,6 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_QM_REGION_NUM 64 #define KS2_QM_QPOOL_NUM 4000 -/* MSMC control */ -#define KS2_MSMC_CTRL_BASE 0x0bc0 - /* USB */ #define KS2_USB_SS_BASE0x0268 #define KS2_USB_HOST_XHCI_BASE (KS2_USB_SS_BASE + 0x1) -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch v6 6/6] keystone2: k2l-evm: add board support
From: Hao Zhang hzh...@ti.com
This patch adds Keystone II Lammar (K2L) EVM board support.
Acked-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/cpu/armv7/keystone/Kconfig| 3 ++
arch/arm/include/asm/arch-keystone/clock-k2l.h | 6 +++
board/ti/ks2_evm/Kconfig | 16 ++
board/ti/ks2_evm/MAINTAINERS | 2 +
board/ti/ks2_evm/Makefile | 2 +
board/ti/ks2_evm/board_k2l.c | 72 ++
board/ti/ks2_evm/ddr3_cfg.c| 36 +
board/ti/ks2_evm/ddr3_cfg.h| 3 ++
board/ti/ks2_evm/ddr3_k2l.c| 38 ++
configs/k2l_evm_defconfig | 4 ++
include/configs/k2l_evm.h | 37 +
11 files changed, 219 insertions(+)
create mode 100644 board/ti/ks2_evm/board_k2l.c
create mode 100644 board/ti/ks2_evm/ddr3_k2l.c
create mode 100644 configs/k2l_evm_defconfig
create mode 100644 include/configs/k2l_evm.h
diff --git a/arch/arm/cpu/armv7/keystone/Kconfig
b/arch/arm/cpu/armv7/keystone/Kconfig
index 24d0cbe..91211fd 100644
--- a/arch/arm/cpu/armv7/keystone/Kconfig
+++ b/arch/arm/cpu/armv7/keystone/Kconfig
@@ -9,6 +9,9 @@ config TARGET_K2HK_EVM
config TARGET_K2E_EVM
bool TI Keystone 2 Edison EVM
+config TARGET_K2L_EVM
+ bool TI Keystone 2 Lamar EVM
+
endchoice
config SYS_CPU
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2l.h
b/arch/arm/include/asm/arch-keystone/clock-k2l.h
index ad2e407..bb9a5c4 100644
--- a/arch/arm/include/asm/arch-keystone/clock-k2l.h
+++ b/arch/arm/include/asm/arch-keystone/clock-k2l.h
@@ -70,7 +70,9 @@ enum {
#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
+#define CORE_PLL_1000 {CORE_PLL, 114, 7, 2}
#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2}
+#define CORE_PLL_1198 {CORE_PLL, 39, 2, 2}
#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2}
#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2}
#define PASS_PLL_983 {PASS_PLL, 16, 1, 2}
@@ -79,8 +81,12 @@ enum {
#define TETRIS_PLL_737 {TETRIS_PLL, 12, 1, 2}
#define TETRIS_PLL_799 {TETRIS_PLL, 13, 1, 2}
#define TETRIS_PLL_983 {TETRIS_PLL, 16, 1, 2}
+#define TETRIS_PLL_1000{TETRIS_PLL, 114, 7, 2}
#define TETRIS_PLL_1167{TETRIS_PLL, 19, 1, 2}
+#define TETRIS_PLL_1198{TETRIS_PLL, 39, 2, 2}
#define TETRIS_PLL_1228{TETRIS_PLL, 20, 1, 2}
+#define TETRIS_PLL_1352{TETRIS_PLL, 22, 1, 2}
+#define TETRIS_PLL_1401{TETRIS_PLL, 114, 5, 2}
#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2}
#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4}
#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}
diff --git a/board/ti/ks2_evm/Kconfig b/board/ti/ks2_evm/Kconfig
index 3108782..36c31ff 100644
--- a/board/ti/ks2_evm/Kconfig
+++ b/board/ti/ks2_evm/Kconfig
@@ -29,3 +29,19 @@ config SYS_CONFIG_NAME
default k2hk_evm
endif
+
+if TARGET_K2L_EVM
+
+config SYS_BOARD
+ string
+ default ks2_evm
+
+config SYS_VENDOR
+ string
+ default ti
+
+config SYS_CONFIG_NAME
+ string
+ default k2l_evm
+
+endif
diff --git a/board/ti/ks2_evm/MAINTAINERS b/board/ti/ks2_evm/MAINTAINERS
index 595a80a..87c36c9 100644
--- a/board/ti/ks2_evm/MAINTAINERS
+++ b/board/ti/ks2_evm/MAINTAINERS
@@ -6,3 +6,5 @@ F: include/configs/k2hk_evm.h
F: configs/k2hk_evm_defconfig
F: include/configs/k2e_evm.h
F: configs/k2e_evm_defconfig
+F: include/configs/k2l_evm.h
+F: configs/k2l_evm_defconfig
diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile
index 00f1164..071dbee 100644
--- a/board/ti/ks2_evm/Makefile
+++ b/board/ti/ks2_evm/Makefile
@@ -11,3 +11,5 @@ obj-$(CONFIG_K2HK_EVM) += board_k2hk.o
obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o
obj-$(CONFIG_K2E_EVM) += board_k2e.o
obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o
+obj-$(CONFIG_K2L_EVM) += board_k2l.o
+obj-$(CONFIG_K2L_EVM) += ddr3_k2l.o
diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c
new file mode 100644
index 000..559d20c
--- /dev/null
+++ b/board/ti/ks2_evm/board_k2l.c
@@ -0,0 +1,72 @@
+/*
+ * K2L EVM : Board initialization
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/arch/ddr3.h
+#include asm/arch/hardware.h
+#include asm/ti-common/ti-aemif.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int external_clk[ext_clk_count] = {
+ [sys_clk] = 12288,
+ [alt_core_clk] = 1,
+ [pa_clk]= 12288,
+ [tetris_clk]= 12288,
+ [ddr3_clk] = 1,
+ [pcie_clk] = 1,
+ [sgmii_clk] = 15625,
+ [usb_clk] = 1,
+};
+
+static struct pll_init_data core_pll_config[] = {
+ CORE_PLL_799,
+ CORE_PLL_1000,
+
Re: [U-Boot] Relocation issue - need help!
I had exactly the same behaviour some time ago and tracked it down to
this (and posted it on the mailing list, but sadly got no feedback):
In my latest u-boot builds I had some strange behaviour that I finally
tracked down to not fixed up flash addresses in relocated u-boot.
These addresses come from symbols in the .data.rel.ro.local section
that is not handled by u-boot linker scripts at the moment.
Some background on relro: http://www.airs.com/blog/archives/189
Joerg Albert already inquired about this on the gcc ML:
https://gcc.gnu.org/ml/gcc-help/2014-02/msg00017.html and he already
suggested a solution:
https://gcc.gnu.org/ml/gcc-help/2014-02/msg00054.html
So there a three things to notice:
1. Do not use gcc 4.8 and u-boot at the moment.
2. You might not notice that you have a problem until you erase u-boot
from flash (and get your cache flushed).
3. Handling relro properly should be on the TODO-List
Maybe this is already common knowledge an maybe somebody is already
working on this - but I did not notice yet. So in this case: sorry for
the noise :)
2014-10-22 14:39 GMT+02:00 Wolfgang Denk w...@denx.de:
Hi,
I'm trying to track down a syntax error issue that gets triggered
when erasing the U-Boot image in NOR flash. Symptoms look like this:
= print update
update=protect off 0xfc00 +${filesize};erase 0xfc00
+${filesize};cp.b 20 0xfc00 ${filesize};protect on 0xfc00
+${filesize}
= run update
Un-Protected 2 sectors
.. done
Erased 2 sectors
syntax error
Protected 2 sectors
= run update
syntax error
git bisect found commit 199adb6 common/misc: sparse fixes as
culprit; breaking this down further showed a single line in
common/cli_hush.c to trigger the problem. This patch fixes it:
---
common/cli_hush.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/cli_hush.c b/common/cli_hush.c
index 38da5a0..5bbcfe6 100644
--- a/common/cli_hush.c
+++ b/common/cli_hush.c
@@ -3127,7 +3127,7 @@ static void mapset(const unsigned char *set, int code)
for (s=set; *s; s++) map[*s] = code;
}
-static void update_ifs_map(void)
+void update_ifs_map(void)
{
/* char *ifs and char map[256] are both globals. */
ifs = (uchar *)getenv(IFS);
--
1.8.3.1
But I still have bad feelings - symptoms indicate that this is
actually a relocation issue, as it only gets triggered when erasing
the U-Boot image in NOR flash, so probably there are still pointers to
data in NOR being used. This patch here is not suited to fix the
original cause of this issue. But then, I do not see where there
might be a relocation problem. To be sure I even verified that ifs
and map[] are really in RAM all the time.
Has anybody an idea how to further track this down? Or is the patch
above actually a real fix? If so, why?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
Old programmers never die, they just branch to a new address.
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[U-Boot] [PATCH 3/3] sunxi: Add CONFIG_OLD_KERNEL_COMPAT Kconfig option
Add a Kconfig option which users can select when they want to boot older kernels, e.g. the linux-sunxi 3.4 kernels. For now this just forces the pll5 p value to 1 (divide by 2) as that is what those kernels are hardcoded too, in the future this may enable further workarounds. Signed-off-by: Hans de Goede hdego...@redhat.com --- arch/arm/cpu/armv7/sunxi/dram.c | 4 board/sunxi/Kconfig | 7 +++ 2 files changed, 11 insertions(+) diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c index 0cbcf57..c0dc456 100644 --- a/arch/arm/cpu/armv7/sunxi/dram.c +++ b/arch/arm/cpu/armv7/sunxi/dram.c @@ -293,6 +293,10 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk) reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2)); reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); } +#ifdef CONFIG_OLD_KERNEL_COMPAT + /* Old kernels are hardcoded to P=1 (divide by 2) */ + reg_val |= CCM_PLL5_CTRL_P(1); +#endif reg_val = ~CCM_PLL5_CTRL_VCO_GAIN; /* PLL VCO Gain off */ reg_val |= CCM_PLL5_CTRL_EN;/* PLL On */ writel(reg_val, ccm-pll5_cfg); diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 66261fc..0331088 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -19,6 +19,13 @@ config SYS_SOC config FDTFILE string Default fdtfile env setting for this board +config OLD_KERNEL_COMPAT + boolean Enable workarounds for booting old kernels + default n + ---help--- + Set this to enable various workarounds for old kernels, this results in + sub-optimal settings for newer kernels, only enable if needed. + config MMC0_CD_PIN string Card detect pin for mmc0 default -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] sunxi: Add clock_get_pll5p() function
This is a preparation patch for making the pll5 p divisor configurable
through Kconfig.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/clock_sun4i.c| 11 +++
arch/arm/include/asm/arch-sunxi/clock.h | 1 +
arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 3 +++
3 files changed, 15 insertions(+)
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
index ecbdb01..4a0d64f 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
@@ -180,6 +180,17 @@ void clock_set_pll1(unsigned int hz)
}
#endif
+unsigned int clock_get_pll5p(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ uint32_t rval = readl(ccm-pll5_cfg);
+ int n = ((rval CCM_PLL5_CTRL_N_MASK) CCM_PLL5_CTRL_N_SHIFT);
+ int k = ((rval CCM_PLL5_CTRL_K_MASK) CCM_PLL5_CTRL_K_SHIFT) + 1;
+ int p = ((rval CCM_PLL5_CTRL_P_MASK) CCM_PLL5_CTRL_P_SHIFT);
+ return (2400 * n * k) p;
+}
+
unsigned int clock_get_pll6(void)
{
struct sunxi_ccm_reg *const ccm =
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h
b/arch/arm/include/asm/arch-sunxi/clock.h
index 8f5d860..9775c85 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -25,6 +25,7 @@
int clock_init(void);
int clock_twi_onoff(int port, int state);
void clock_set_pll1(unsigned int hz);
+unsigned int clock_get_pll5p(void);
unsigned int clock_get_pll6(void);
void clock_init_safe(void);
void clock_init_uart(void);
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index 1ba997a..90af8e2 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -199,13 +199,16 @@ struct sunxi_ccm_reg {
#define CCM_PLL5_CTRL_M1_MASK CCM_PLL5_CTRL_M1(0x3)
#define CCM_PLL5_CTRL_M1_X(n) ((n) - 1)
#define CCM_PLL5_CTRL_K(n) (((n) 0x3) 4)
+#define CCM_PLL5_CTRL_K_SHIFT 4
#define CCM_PLL5_CTRL_K_MASK CCM_PLL5_CTRL_K(0x3)
#define CCM_PLL5_CTRL_K_X(n) ((n) - 1)
#define CCM_PLL5_CTRL_LDO (0x1 7)
#define CCM_PLL5_CTRL_N(n) (((n) 0x1f) 8)
+#define CCM_PLL5_CTRL_N_SHIFT 8
#define CCM_PLL5_CTRL_N_MASK CCM_PLL5_CTRL_N(0x1f)
#define CCM_PLL5_CTRL_N_X(n) (n)
#define CCM_PLL5_CTRL_P(n) (((n) 0x3) 16)
+#define CCM_PLL5_CTRL_P_SHIFT 16
#define CCM_PLL5_CTRL_P_MASK CCM_PLL5_CTRL_P(0x3)
#define CCM_PLL5_CTRL_P_X(n) ((n) - 1)
#define CCM_PLL5_CTRL_BW (0x1 18)
--
2.1.0
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[U-Boot] [PATCH 2/3] sunxi: dram: Use clock_get_pll5p to calculate mbus, rather then hardcoding
This is a preparation patch for making the pll5 p divisor configurable
through Kconfig.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/dram.c | 32 ++--
1 file changed, 14 insertions(+), 18 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index 584f742..0cbcf57 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -252,15 +252,9 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
{
u32 reg_val;
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- /* PLL5P and PLL6 are the potential clock sources for MBUS */
- u32 pll6x_div, pll5p_div;
- u32 pll6x_clk = clock_get_pll6() / 100;
- u32 pll5p_clk = clk / 24 * 48;
+ u32 pll5p_clk, pll6x_clk;
+ u32 pll5p_div, pll6x_div;
u32 pll5p_rate, pll6x_rate;
-#ifdef CONFIG_SUN7I
- pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */
-#endif
/* setup DRAM PLL */
reg_val = readl(ccm-pll5_cfg);
@@ -269,32 +263,27 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
reg_val = ~CCM_PLL5_CTRL_N_MASK; /* set N to 0 (x0) */
reg_val = ~CCM_PLL5_CTRL_P_MASK; /* set P to 0 (x1) */
if (clk = 540 clk 552) {
- /* dram = 540MHz, pll5p = 1080MHz */
- pll5p_clk = 1080;
+ /* dram = 540MHz */
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15));
} else if (clk = 512 clk 528) {
- /* dram = 512MHz, pll5p = 1536MHz */
- pll5p_clk = 1536;
+ /* dram = 512MHz */
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(4));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16));
} else if (clk = 496 clk 504) {
- /* dram = 496MHz, pll5p = 1488MHz */
- pll5p_clk = 1488;
+ /* dram = 496MHz */
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31));
} else if (clk = 468 clk 480) {
- /* dram = 468MHz, pll5p = 936MHz */
- pll5p_clk = 936;
+ /* dram = 468MHz */
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13));
} else if (clk = 396 clk 408) {
- /* dram = 396MHz, pll5p = 792MHz */
- pll5p_clk = 792;
+ /* dram = 396MHz */
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11));
@@ -322,6 +311,13 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
/* setup MBUS clock */
if (!mbus_clk)
mbus_clk = 300;
+
+ /* PLL5P and PLL6 are the potential clock sources for MBUS */
+ pll6x_clk = clock_get_pll6() / 100;
+#ifdef CONFIG_SUN7I
+ pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */
+#endif
+ pll5p_clk = clock_get_pll5p() / 100;
pll6x_div = DIV_ROUND_UP(pll6x_clk, mbus_clk);
pll5p_div = DIV_ROUND_UP(pll5p_clk, mbus_clk);
pll6x_rate = pll6x_clk / pll6x_div;
--
2.1.0
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[U-Boot] [PATCH v2] ARM: bootm: Allow booting in secure mode on hyp capable systems
Older Linux kernels will not properly boot in hype mode, add support for a
bootm_boot_mode environment variable, which when set to sec will cause
u-boot to boot in secure mode even when build with non-sec (and hyp) support.
Signed-off-by: Hans de Goede hdego...@redhat.com
Acked-by: Marc Zyngier marc.zyng...@arm.com
Acked-by: Siarhei Siamashka siarhei.siamas...@gmail.com
--
Changes in v2:
-Allow changing the default boot mode to secure through defining
CONFIG_ARMV7_SEC_BY_DEFAULT, this is useful for archs which have a Kconfig
option for compatibility with older kernels
---
arch/arm/lib/bootm.c | 31 ++-
1 file changed, 26 insertions(+), 5 deletions(-)
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 39fe7a1..ff0170a 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -235,6 +235,26 @@ static void boot_prep_linux(bootm_headers_t *images)
}
}
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+static bool boot_nonsec(void)
+{
+ char *s = getenv(bootm_boot_mode);
+#ifdef CONFIG_ARMV7_SEC_BY_DEFAULT
+ bool nonsec = false;
+#else
+ bool nonsec = true;
+#endif
+
+ if (s !strcmp(s, sec))
+ nonsec = false;
+
+ if (s !strcmp(s, nonsec))
+ nonsec = true;
+
+ return nonsec;
+}
+#endif
+
/* Subcommand: GO */
static void boot_jump_linux(bootm_headers_t *images, int flag)
{
@@ -283,12 +303,13 @@ static void boot_jump_linux(bootm_headers_t *images, int
flag)
if (!fake) {
#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
- armv7_init_nonsec();
- secure_ram_addr(_do_nonsec_entry)(kernel_entry,
- 0, machid, r2);
-#else
- kernel_entry(0, machid, r2);
+ if (boot_nonsec()) {
+ armv7_init_nonsec();
+ secure_ram_addr(_do_nonsec_entry)(kernel_entry,
+ 0, machid, r2);
+ }
#endif
+ kernel_entry(0, machid, r2);
}
#endif
}
--
2.1.0
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[U-Boot] [PATCH] sun7i: Set CONFIG_ARMV7_SEC_BY_DEFAULT when CONFIG_OLD_KERNEL_COMPAT is set
Old kernels cannot handle booting in non-secure (hyp) mode, so when CONFIG_OLD_KERNEL_COMPAT is set, also set CONFIG_ARMV7_SEC_BY_DEFAULT. Note that whether to booting secure or non-secure can always be overriden using the bootm_boot_mode environment variable. Signed-off-by: Hans de Goede hdego...@redhat.com --- include/configs/sun7i.h | 4 1 file changed, 4 insertions(+) diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h index 966cbd8..4a864b2 100644 --- a/include/configs/sun7i.h +++ b/include/configs/sun7i.h @@ -35,6 +35,10 @@ #define CONFIG_ARMV7_PSCI 1 #define CONFIG_ARMV7_PSCI_NR_CPUS 2 #define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE +#ifdef CONFIG_OLD_KERNEL_COMPAT +#define CONFIG_ARMV7_SEC_BY_DEFAULT1 +#endif + #define CONFIG_SYS_CLK_FREQ2400 /* -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-boot] [Patch v4 2/6] keystone2: clock: add K2L clock definitions and commands
On 10/20/2014 06:55 PM, Tom Rini wrote:
On Mon, Oct 20, 2014 at 06:41:29PM +0300, Ivan Khoronzhuk wrote:
On 10/20/2014 06:13 PM, Tom Rini wrote:
On Wed, Oct 15, 2014 at 02:55:28AM +0300, Ivan Khoronzhuk wrote:
From: Hao Zhang hzh...@ti.com
This patch adds clock definitions and commands to support Keystone II
K2L SOC.
Acked-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
[snip]
diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c
b/arch/arm/cpu/armv7/keystone/cmd_clock.c
index d97c95b..9204887 100644
--- a/arch/arm/cpu/armv7/keystone/cmd_clock.c
+++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c
@@ -72,6 +72,13 @@ U_BOOT_CMD(
pa|ddr3 mult div OD\n
);
#endif
+#ifdef CONFIG_SOC_K2L
+U_BOOT_CMD(
+ pllset, 5, 0, do_pll_cmd,
+ set pll multiplier and pre divider,
+ pa|arm|ddr3 mult div OD\n
+);
+#endif
int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
@@ -101,6 +108,9 @@ U_BOOT_CMD(
#ifdef CONFIG_SOC_K2E
See the 'enum clk_e' in the clock-k2e.h for clk indexes\n
#endif
+#ifdef CONFIG_SOC_K2L
+ See the 'enum clk_e' in the clock-k2l.h for clk indexes\n
+#endif
);
I'm not going to block on all of this duplication, but we need to think
how to do this cleaner so that the next K2 variant doesn't expand this
mess further. Thanks!
I'll correct it to one line:
See the 'enum clk_e' in the clock-k2*.h for clk indexes\n
That helps the second hunk, but still leaves the first. At some point,
even, we shouldn't say go modify file foo in the binary, that belongs
in board documentation. Like I said, this needs a little bit of
thinking.
Tom,
the series is updated according to your propositions:
[U-boot] [Patch v6 0/6] keystone2: add k2l SoC and k2l_evm board support
https://www.mail-archive.com/u-boot@lists.denx.de/msg150727.html
It's based on patch that corrects command usage descriptions:
[U-Boot,U-boot] ARM: cmd_clock: generalize command usage description
http://patchwork.ozlabs.org/patch/402102/
I've sent it separately to not mix it with K2L support series.
Thanks!
--
Regards,
Ivan Khoronzhuk
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Re: [U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms
On Sun, Sep 28, 2014 at 04:59:45PM +0800, yuantian.t...@freescale.com wrote:
From: Tang Yuantian yuantian.t...@freescale.com
When Freescale QorIQ SoCs wake up from deep sleep, control is
passed to the primary core that starts executing uboot. After
re-initialized some IP blocks, like DDRC, kernel will take
responsibility to continue to restore environment it leaves before.
This patch adds the deep sleep framework support for all Freescale
QorIQ platforms that use generic_board configuation.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
common/board_f.c | 10 +
drivers/ddr/fsl/arm_ddr_gen3.c | 48
+-
include/fsl_ddr_sdram.h| 2 ++
include/fsl_sleep.h| 32
4 files changed, 87 insertions(+), 5 deletions(-)
create mode 100644 include/fsl_sleep.h
diff --git a/common/board_f.c b/common/board_f.c
index e6aa298..b736d29 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -56,6 +56,9 @@
#endif
#include dm/root.h
#include linux/compiler.h
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#include fsl_sleep.h
+#endif
/*
* Pointer to initial global data area
@@ -921,6 +924,9 @@ static init_fnc_t init_sequence_f[] = {
#if defined(CONFIG_MIPS) || defined(CONFIG_PPC)
init_func_ram,
#endif
+#ifdef CONFIG_FSL_DEEP_SLEEP
+ fsl_dp_resume,
+#endif
Is there not an existing hook you can use here instead? Is misc_init_f
too early? If we're going to add a new hook in here, it needs to be
somewhat generically named, with the requirements of the system spelled
out. Some TI parts have a (setting aside marketing-speak) similar
function and I believe the U-Boot patches for that use an existing hook
to notice what happened and do what's needed. Thanks!
--
Tom
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[U-Boot] [U-boot] [Patch v4 2/4] soc: keystone_serdes: enhance to use cmu/comlane/lane specific configurations
From: Hao Zhang hzh...@ti.com
Enhance the driver to use cmu/comlane/lane specific configurations
instead of 1 big array of configuration.
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 3 +
arch/arm/include/asm/arch-keystone/hardware.h | 3 +
drivers/soc/keystone/keystone_serdes.c | 166 +++--
include/configs/ks2_evm.h | 4 +
4 files changed, 94 insertions(+), 82 deletions(-)
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
index 706b21d..28de3f5 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
@@ -79,6 +79,9 @@
#define KS2_DDR3B_EMIF_DATA_BASE 0x6000
#define KS2_DDR3B_DDRPHYC 0x02328000
+/* SGMII SerDes */
+#define KS2_LANES_PER_SGMII_SERDES 4
+
/* Number of DSP cores */
#define KS2_NUM_DSPS 8
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h
b/arch/arm/include/asm/arch-keystone/hardware.h
index 0441b29..6e2e939 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -177,6 +177,9 @@ typedef volatile unsigned int *dv_reg_p;
#define KS2_MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
+/* SGMII SerDes */
+#define KS2_SGMII_SERDES_BASE 0x0232a000
+
#ifdef CONFIG_SOC_K2HK
#include asm/arch/hardware-k2hk.h
#endif
diff --git a/drivers/soc/keystone/keystone_serdes.c
b/drivers/soc/keystone/keystone_serdes.c
index dc4e78d..3632c22 100644
--- a/drivers/soc/keystone/keystone_serdes.c
+++ b/drivers/soc/keystone/keystone_serdes.c
@@ -9,92 +9,94 @@
#include common.h
+#define SERDES_LANE_REGS(x)(0x0200 + (0x200 * (x)))
+
+struct serdes_cfg {
+ u32 ofs;
+ u32 val;
+ u32 mask;
+};
+
+static struct serdes_cfg cfg_cmu_156p25m_5g[] = {
+ {0x, 0x0080, 0x},
+ {0x0014, 0x8282, 0x},
+ {0x0060, 0x00142438, 0x00ff},
+ {0x0064, 0x00c3c700, 0x0000},
+ {0x0078, 0xc000, 0xff00}
+};
+
+static struct serdes_cfg cfg_comlane_156p25m_5g[] = {
+ {0x0a00, 0x0800, 0xff00},
+ {0x0a08, 0x38a2, 0x},
+ {0x0a30, 0x008a8a00, 0x0000},
+ {0x0a84, 0x0600, 0xff00},
+ {0x0a94, 0x1000, 0xff00},
+ {0x0aa0, 0x8100, 0xff00},
+ {0x0abc, 0xff00, 0xff00},
+ {0x0ac0, 0x008b, 0x00ff},
+ {0x0b08, 0x583f, 0x},
+ {0x0b0c, 0x004e, 0x00ff}
+};
+
+static struct serdes_cfg cfg_lane_156p25mhz_5g[] = {
+ {0x0004, 0x3880, 0xffff},
+ {0x0008, 0x, 0x00ff},
+ {0x000c, 0x0200, 0xff00},
+ {0x0010, 0x1b00, 0xff00},
+ {0x0014, 0x6fb8, 0x},
+ {0x0018, 0x758000e4, 0x00ff},
+ {0x00ac, 0x4400, 0xff00},
+ {0x002c, 0x00100800, 0x0000},
+ {0x0080, 0x00820082, 0x00ff00ff},
+ {0x0084, 0x1d0f0385, 0x}
+
+};
+
+static inline void ks2_serdes_rmw(u32 addr, u32 value, u32 mask)
+{
+ writel(((readl(addr) (~mask)) | (value mask)), addr);
+}
+
+static void ks2_serdes_cfg_setup(u32 base, struct serdes_cfg *cfg, u32 size)
+{
+ u32 i;
+
+ for (i = 0; i size; i++)
+ ks2_serdes_rmw(base + cfg[i].ofs, cfg[i].val, cfg[i].mask);
+}
+
+static void ks2_serdes_lane_config(u32 base, struct serdes_cfg *cfg_lane,
+ u32 size, u32 lane)
+{
+ u32 i;
+
+ for (i = 0; i size; i++)
+ ks2_serdes_rmw(base + cfg_lane[i].ofs + SERDES_LANE_REGS(lane),
+ cfg_lane[i].val, cfg_lane[i].mask);
+}
+
+static int ks2_serdes_init_156p25m_5g(u32 base, u32 num_lanes)
+{
+ u32 i;
+
+ ks2_serdes_cfg_setup(base, cfg_cmu_156p25m_5g,
+ARRAY_SIZE(cfg_cmu_156p25m_5g));
+ ks2_serdes_cfg_setup(base, cfg_comlane_156p25m_5g,
+ARRAY_SIZE(cfg_comlane_156p25m_5g));
+
+ for (i = 0; i num_lanes; i++)
+ ks2_serdes_lane_config(base, cfg_lane_156p25mhz_5g,
+ ARRAY_SIZE(cfg_lane_156p25mhz_5g), i);
+
+ return 0;
+}
+
void ks2_serdes_sgmii_156p25mhz_setup(void)
{
unsigned int cnt;
- /*
-* configure Serializer/Deserializer (SerDes) hardware. SerDes IP
-* hardware vendor published only register addresses and their values
-* to be used for configuring SerDes. So had to use hardcoded values
-* below.
-*/
- clrsetbits_le32(0x0232a000, 0x, 0x0080);
- clrsetbits_le32(0x0232a014, 0x, 0x8282);
- clrsetbits_le32(0x0232a060, 0x00ff, 0x00142438);
-
[U-Boot] [U-boot] [Patch v4 0/4] keystone2: serdes: add seredes driver
This patch series adds serdes driver, moving it from keystone_net driver. Based on [U-boot] [Patch v2 0/5] keystone2: generalize keystone_net driver usage http://u-boot.10912.n7.nabble.com/U-boot-Patch-v2-0-5-keystone2-generalize- keystone-net-driver-usage-td190624.html v4..v3: - soc: keystone_serdes: create a separate SGMII SerDes driver squashed with soc: add soc specific drivers directory v3..v1: just rebase. Hao Zhang (2): soc: keystone_serdes: enhance to use cmu/comlane/lane specific configurations soc: keystone_serdes: generalize to be used by other sub systems Ivan Khoronzhuk (2): soc: keystone_serdes: create a separate SGMII SerDes driver soc: keystone_serdes: generalize configuration mechanism arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 3 + arch/arm/include/asm/arch-keystone/hardware.h | 3 + arch/arm/include/asm/ti-common/keystone_serdes.h | 55 ++ drivers/Makefile | 2 + drivers/net/keystone_net.c | 154 ++- drivers/soc/Makefile | 5 + drivers/soc/keystone/Makefile | 1 + drivers/soc/keystone/keystone_serdes.c | 210 + include/configs/k2hk_evm.h | 3 + include/configs/ks2_evm.h | 6 +- 10 files changed, 303 insertions(+), 139 deletions(-) create mode 100644 arch/arm/include/asm/ti-common/keystone_serdes.h create mode 100644 drivers/soc/Makefile create mode 100644 drivers/soc/keystone/Makefile create mode 100644 drivers/soc/keystone/keystone_serdes.c -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch v4 4/4] soc: keystone_serdes: generalize configuration mechanism
The cmu, comlane, lane configuration mechanism are similar for sub
systems as well such as PCI or sRIO, but they have different values
based on input clock and output bus rate. According to this compact
driver to simplify adding different configuration settings based
on clock and rate.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
drivers/soc/keystone/keystone_serdes.c | 112 +++--
1 file changed, 65 insertions(+), 47 deletions(-)
diff --git a/drivers/soc/keystone/keystone_serdes.c
b/drivers/soc/keystone/keystone_serdes.c
index 84ed9ba..dd5eac9 100644
--- a/drivers/soc/keystone/keystone_serdes.c
+++ b/drivers/soc/keystone/keystone_serdes.c
@@ -29,12 +29,24 @@
#define SERDES_LANE_LOOPBACK BIT(30)
#define SERDES_LANE_EN_VAL(x, y, z)(x[y] | (z 26) | (z 10))
+#define SERDES_CMU_CFG_NUM 5
+#define SERDES_COMLANE_CFG_NUM 10
+#define SERDES_LANE_CFG_NUM10
+
struct serdes_cfg {
u32 ofs;
u32 val;
u32 mask;
};
+struct cfg_entry {
+ enum ks2_serdes_clock clk;
+ enum ks2_serdes_rate rate;
+ struct serdes_cfg cmu[SERDES_CMU_CFG_NUM];
+ struct serdes_cfg comlane[SERDES_COMLANE_CFG_NUM];
+ struct serdes_cfg lane[SERDES_LANE_CFG_NUM];
+};
+
/* SERDES PHY lane enable configuration value, indexed by PHY interface */
static u32 serdes_cfg_lane_enable[] = {
0xf000f0c0, /* SGMII */
@@ -47,39 +59,46 @@ static u32 serdes_cfg_pll_enable[] = {
0xee00, /* PCSR */
};
-static struct serdes_cfg cfg_cmu_156p25m_5g[] = {
- {0x, 0x0080, 0x},
- {0x0014, 0x8282, 0x},
- {0x0060, 0x00142438, 0x00ff},
- {0x0064, 0x00c3c700, 0x0000},
- {0x0078, 0xc000, 0xff00}
-};
-
-static struct serdes_cfg cfg_comlane_156p25m_5g[] = {
- {0x0a00, 0x0800, 0xff00},
- {0x0a08, 0x38a2, 0x},
- {0x0a30, 0x008a8a00, 0x0000},
- {0x0a84, 0x0600, 0xff00},
- {0x0a94, 0x1000, 0xff00},
- {0x0aa0, 0x8100, 0xff00},
- {0x0abc, 0xff00, 0xff00},
- {0x0ac0, 0x008b, 0x00ff},
- {0x0b08, 0x583f, 0x},
- {0x0b0c, 0x004e, 0x00ff}
-};
-
-static struct serdes_cfg cfg_lane_156p25mhz_5g[] = {
- {0x0004, 0x3880, 0xffff},
- {0x0008, 0x, 0x00ff},
- {0x000c, 0x0200, 0xff00},
- {0x0010, 0x1b00, 0xff00},
- {0x0014, 0x6fb8, 0x},
- {0x0018, 0x758000e4, 0x00ff},
- {0x00ac, 0x4400, 0xff00},
- {0x002c, 0x00100800, 0x0000},
- {0x0080, 0x00820082, 0x00ff00ff},
- {0x0084, 0x1d0f0385, 0x}
-
+/**
+ * Array to hold all possible serdes configurations.
+ * Combination for 5 clock settings and 6 baud rates.
+ */
+static struct cfg_entry cfgs[] = {
+ {
+ .clk = SERDES_CLOCK_156P25M,
+ .rate = SERDES_RATE_5G,
+ .cmu = {
+ {0x, 0x0080, 0x},
+ {0x0014, 0x8282, 0x},
+ {0x0060, 0x00142438, 0x00ff},
+ {0x0064, 0x00c3c700, 0x0000},
+ {0x0078, 0xc000, 0xff00}
+ },
+ .comlane = {
+ {0x0a00, 0x0800, 0xff00},
+ {0x0a08, 0x38a2, 0x},
+ {0x0a30, 0x008a8a00, 0x0000},
+ {0x0a84, 0x0600, 0xff00},
+ {0x0a94, 0x1000, 0xff00},
+ {0x0aa0, 0x8100, 0xff00},
+ {0x0abc, 0xff00, 0xff00},
+ {0x0ac0, 0x008b, 0x00ff},
+ {0x0b08, 0x583f, 0x},
+ {0x0b0c, 0x004e, 0x00ff}
+ },
+ .lane = {
+ {0x0004, 0x3880, 0xffff},
+ {0x0008, 0x, 0x00ff},
+ {0x000c, 0x0200, 0xff00},
+ {0x0010, 0x1b00, 0xff00},
+ {0x0014, 0x6fb8, 0x},
+ {0x0018, 0x758000e4, 0x00ff},
+ {0x00ac, 0x4400, 0xff00},
+ {0x002c, 0x00100800, 0x0000},
+ {0x0080, 0x00820082, 0x00ff00ff},
+ {0x0084, 0x1d0f0385, 0x}
+ },
+ },
};
static inline void ks2_serdes_rmw(u32 addr, u32 value, u32 mask)
@@ -105,18 +124,15 @@ static void ks2_serdes_lane_config(u32 base, struct
serdes_cfg *cfg_lane,
cfg_lane[i].val, cfg_lane[i].mask);
}
-static int ks2_serdes_init_156p25m_5g(u32 base, u32 num_lanes)
+static int ks2_serdes_init_cfg(u32 base, struct cfg_entry *cfg, u32
[U-Boot] [U-boot] [Patch v4 3/4] soc: keystone_serdes: generalize to be used by other sub systems
From: Hao Zhang hzh...@ti.com
SerDes driver is used by other sub systems like PCI, sRIO etc.
So modify it to be more general. The SerDes driver provides common
API's that can also be extended for other peripherals SerDes
configurations.
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/include/asm/ti-common/keystone_serdes.h | 42 +++-
drivers/net/keystone_net.c | 15 ++-
drivers/soc/keystone/keystone_serdes.c | 131 +--
include/configs/ks2_evm.h| 10 +-
4 files changed, 156 insertions(+), 42 deletions(-)
diff --git a/arch/arm/include/asm/ti-common/keystone_serdes.h
b/arch/arm/include/asm/ti-common/keystone_serdes.h
index 2e12b05..2e92411 100644
--- a/arch/arm/include/asm/ti-common/keystone_serdes.h
+++ b/arch/arm/include/asm/ti-common/keystone_serdes.h
@@ -10,6 +10,46 @@
#ifndef __TI_KEYSTONE_SERDES_H__
#define __TI_KEYSTONE_SERDES_H__
-void ks2_serdes_sgmii_156p25mhz_setup(void);
+/* SERDES Reference clock */
+enum ks2_serdes_clock {
+ SERDES_CLOCK_100M, /* 100 MHz */
+ SERDES_CLOCK_122P88M, /* 122.88 MHz */
+ SERDES_CLOCK_125M, /* 125 MHz */
+ SERDES_CLOCK_156P25M, /* 156.25 MHz */
+ SERDES_CLOCK_312P5M,/* 312.5 MHz */
+};
+
+/* SERDES Lane Baud Rate */
+enum ks2_serdes_rate {
+ SERDES_RATE_4P9152G,/* 4.9152 GBaud */
+ SERDES_RATE_5G, /* 5 GBaud */
+ SERDES_RATE_6P144G, /* 6.144 GBaud */
+ SERDES_RATE_6P25G, /* 6.25 GBaud */
+ SERDES_RATE_10p3125g, /* 10.3215 GBaud */
+ SERDES_RATE_12p5g, /* 12.5 GBaud */
+};
+
+/* SERDES Lane Rate Mode */
+enum ks2_serdes_rate_mode {
+ SERDES_FULL_RATE,
+ SERDES_HALF_RATE,
+ SERDES_QUARTER_RATE,
+};
+
+/* SERDES PHY TYPE */
+enum ks2_serdes_interface {
+ SERDES_PHY_SGMII,
+ SERDES_PHY_PCSR,/* XGE SERDES */
+};
+
+struct ks2_serdes {
+ enum ks2_serdes_clock clk;
+ enum ks2_serdes_rate rate;
+ enum ks2_serdes_rate_mode rate_mode;
+ enum ks2_serdes_interface intf;
+ u32 loopback;
+};
+
+int ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes);
#endif /* __TI_KEYSTONE_SERDES_H__ */
diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c
index 63f3361..8a45fbd 100644
--- a/drivers/net/keystone_net.c
+++ b/drivers/net/keystone_net.c
@@ -554,7 +554,20 @@ int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
return 0;
}
+struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
+ .clk = SERDES_CLOCK_156P25M,
+ .rate = SERDES_RATE_5G,
+ .rate_mode = SERDES_QUARTER_RATE,
+ .intf = SERDES_PHY_SGMII,
+ .loopback = 0,
+};
+
static void keystone2_net_serdes_setup(void)
{
- ks2_serdes_sgmii_156p25mhz_setup();
+ ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
+ ks2_serdes_sgmii_156p25mhz,
+ CONFIG_KSNET_SERDES_LANES_PER_SGMII);
+
+ /* wait till setup */
+ udelay(5000);
}
diff --git a/drivers/soc/keystone/keystone_serdes.c
b/drivers/soc/keystone/keystone_serdes.c
index 3632c22..84ed9ba 100644
--- a/drivers/soc/keystone/keystone_serdes.c
+++ b/drivers/soc/keystone/keystone_serdes.c
@@ -7,9 +7,27 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+#include errno.h
#include common.h
+#include asm/ti-common/keystone_serdes.h
+#define SERDES_CMU_REGS(x) (0x + (0x0c00 * (x)))
#define SERDES_LANE_REGS(x)(0x0200 + (0x200 * (x)))
+#define SERDES_COMLANE_REGS0x0a00
+#define SERDES_WIZ_REGS0x1fc0
+
+#define SERDES_CMU_REG_000(x) (SERDES_CMU_REGS(x) + 0x000)
+#define SERDES_CMU_REG_010(x) (SERDES_CMU_REGS(x) + 0x010)
+#define SERDES_COMLANE_REG_000 (SERDES_COMLANE_REGS + 0x000)
+#define SERDES_LANE_REG_000(x) (SERDES_LANE_REGS(x) + 0x000)
+#define SERDES_LANE_REG_028(x) (SERDES_LANE_REGS(x) + 0x028)
+#define SERDES_LANE_CTL_STATUS_REG(x) (SERDES_WIZ_REGS + 0x0020 + (4 * (x)))
+#define SERDES_PLL_CTL_REG (SERDES_WIZ_REGS + 0x0034)
+
+#define SERDES_RESET BIT(28)
+#define SERDES_LANE_RESET BIT(29)
+#define SERDES_LANE_LOOPBACK BIT(30)
+#define SERDES_LANE_EN_VAL(x, y, z)(x[y] | (z 26) | (z 10))
struct serdes_cfg {
u32 ofs;
@@ -17,6 +35,18 @@ struct serdes_cfg {
u32 mask;
};
+/* SERDES PHY lane enable configuration value, indexed by PHY interface */
+static u32 serdes_cfg_lane_enable[] = {
+ 0xf000f0c0, /* SGMII */
+ 0xf0e9f038, /* PCSR */
+};
+
+/* SERDES PHY PLL enable configuration value, indexed by PHY interface */
+static u32 serdes_cfg_pll_enable[] = {
+ 0xe000, /* SGMII */
+ 0xee00, /* PCSR */
+};
+
[U-Boot] [U-boot] [Patch v4 1/4] soc: keystone_serdes: create a separate SGMII SerDes driver
This patch split the Keystone II SGMII SerDes related code from
Ethernet driver and create a separate SGMII SerDes driver.
The SerDes driver can be used by others keystone subsystems
like PCI, sRIO, so move it to driver/soc/keystone directory.
Add soc specific drivers directory like in the Linux kernel.
It is going to be used by keysotone soc specific drivers.
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/include/asm/ti-common/keystone_serdes.h | 15 +++
drivers/Makefile | 2 +
drivers/net/keystone_net.c | 143 +--
drivers/soc/Makefile | 5 +
drivers/soc/keystone/Makefile| 1 +
drivers/soc/keystone/keystone_serdes.c | 127
include/configs/k2hk_evm.h | 3 +
7 files changed, 158 insertions(+), 138 deletions(-)
create mode 100644 arch/arm/include/asm/ti-common/keystone_serdes.h
create mode 100644 drivers/soc/Makefile
create mode 100644 drivers/soc/keystone/Makefile
create mode 100644 drivers/soc/keystone/keystone_serdes.c
diff --git a/arch/arm/include/asm/ti-common/keystone_serdes.h
b/arch/arm/include/asm/ti-common/keystone_serdes.h
new file mode 100644
index 000..2e12b05
--- /dev/null
+++ b/arch/arm/include/asm/ti-common/keystone_serdes.h
@@ -0,0 +1,15 @@
+/*
+ * Texas Instruments Keystone SerDes driver
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __TI_KEYSTONE_SERDES_H__
+#define __TI_KEYSTONE_SERDES_H__
+
+void ks2_serdes_sgmii_156p25mhz_setup(void);
+
+#endif /* __TI_KEYSTONE_SERDES_H__ */
diff --git a/drivers/Makefile b/drivers/Makefile
index b22b109..fc9b630 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -16,3 +16,5 @@ obj-y += watchdog/
obj-$(CONFIG_QE) += qe/
obj-y += memory/
obj-y += pwm/
+# SOC specific infrastructure drivers.
+obj-y += soc/
diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c
index 33197f9..63f3361 100644
--- a/drivers/net/keystone_net.c
+++ b/drivers/net/keystone_net.c
@@ -14,6 +14,7 @@
#include malloc.h
#include asm/ti-common/keystone_nav.h
#include asm/ti-common/keystone_net.h
+#include asm/ti-common/keystone_serdes.h
unsigned int emac_open;
static unsigned int sys_has_mdio = 1;
@@ -38,6 +39,7 @@ struct rx_buff_desc net_rx_buffs = {
};
static void keystone2_eth_mdio_enable(void);
+static void keystone2_net_serdes_setup(void);
static int gen_get_link_speed(int phy_addr);
@@ -406,7 +408,7 @@ static int keystone2_eth_open(struct eth_device *dev, bd_t
*bis)
sys_has_mdio =
(eth_priv-sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0;
- sgmii_serdes_setup_156p25mhz();
+ keystone2_net_serdes_setup();
if (sys_has_mdio)
keystone2_eth_mdio_enable();
@@ -552,142 +554,7 @@ int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
return 0;
}
-void sgmii_serdes_setup_156p25mhz(void)
+static void keystone2_net_serdes_setup(void)
{
- unsigned int cnt;
-
- /*
-* configure Serializer/Deserializer (SerDes) hardware. SerDes IP
-* hardware vendor published only register addresses and their values
-* to be used for configuring SerDes. So had to use hardcoded values
-* below.
-*/
- clrsetbits_le32(0x0232a000, 0x, 0x0080);
- clrsetbits_le32(0x0232a014, 0x, 0x8282);
- clrsetbits_le32(0x0232a060, 0x00ff, 0x00142438);
- clrsetbits_le32(0x0232a064, 0x0000, 0x00c3c700);
- clrsetbits_le32(0x0232a078, 0xff00, 0xc000);
-
- clrsetbits_le32(0x0232a204, 0xffff, 0x3880);
- clrsetbits_le32(0x0232a208, 0x00ff, 0x);
- clrsetbits_le32(0x0232a20c, 0xff00, 0x0200);
- clrsetbits_le32(0x0232a210, 0xff00, 0x1b00);
- clrsetbits_le32(0x0232a214, 0x, 0x6fb8);
- clrsetbits_le32(0x0232a218, 0x00ff, 0x758000e4);
- clrsetbits_le32(0x0232a2ac, 0xff00, 0x4400);
- clrsetbits_le32(0x0232a22c, 0x0000, 0x00200800);
- clrsetbits_le32(0x0232a280, 0x00ff00ff, 0x00820082);
- clrsetbits_le32(0x0232a284, 0x, 0x1d0f0385);
-
- clrsetbits_le32(0x0232a404, 0xffff, 0x3880);
- clrsetbits_le32(0x0232a408, 0x00ff, 0x);
- clrsetbits_le32(0x0232a40c, 0xff00, 0x0200);
- clrsetbits_le32(0x0232a410, 0xff00, 0x1b00);
- clrsetbits_le32(0x0232a414, 0x, 0x6fb8);
- clrsetbits_le32(0x0232a418, 0x00ff, 0x758000e4);
- clrsetbits_le32(0x0232a4ac, 0xff00, 0x4400);
- clrsetbits_le32(0x0232a42c, 0x0000, 0x00200800);
- clrsetbits_le32(0x0232a480, 0x00ff00ff, 0x00820082);
- clrsetbits_le32(0x0232a484, 0x, 0x1d0f0385);
-
-
Re: [U-Boot] [PATCH 1/2] arm: mx6: add support for TBS2910 Matrix ARM miniPC
Hi Soeren, On 22/10/2014 14:16, Soeren Moch wrote: U-Boot without video support is useless for me. So I will try to setup the video clock correctly in a new version of this patch. ok, fine with me. You are right here, there is no problem with setup_display() in board_init(). So I wonder why all imx6q boards have setup_display() in board_early_init(), you even committed such code for mx6qsabreauto yesterday. Well, after each review a code reveals new aspects. Anyway, this is not a big issue, but setting the display is not one thing that must be done very early. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch v3 2/4] ARM: keystone: msmc: extend functionality of SES
From: Vitaly Andrianov vita...@ti.com
Add functions to set/get SES PMAX values of Pivilege ID pair.
Also add msmc module definitions.
Acked-by: Murali Karicheri m-kariche...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/cpu/armv7/keystone/msmc.c| 26 +
arch/arm/include/asm/arch-keystone/hardware.h | 6 ++
arch/arm/include/asm/arch-keystone/msmc.h | 28 +++
3 files changed, 60 insertions(+)
diff --git a/arch/arm/cpu/armv7/keystone/msmc.c
b/arch/arm/cpu/armv7/keystone/msmc.c
index 7d8e597..7899141 100644
--- a/arch/arm/cpu/armv7/keystone/msmc.c
+++ b/arch/arm/cpu/armv7/keystone/msmc.c
@@ -66,3 +66,29 @@ void msmc_share_all_segments(int priv_id)
msmc-ses[priv_id][j].mpaxh = 0xff7ful;
}
}
+
+void msmc_map_ses_segment(int priv_id, int ses_pair,
+ u32 src_pfn, u32 dst_pfn, enum mpax_seg_size size)
+{
+ struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
+
+ msmc-ses[priv_id][ses_pair].mpaxh = src_pfn 12 |
+(size 0x1f) | 0x80;
+ msmc-ses[priv_id][ses_pair].mpaxl = dst_pfn 8 | 0x3f;
+}
+
+void msmc_get_ses_mpax(int priv_id, int ses_pair, u32 *mpax)
+{
+ struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
+
+ *mpax++ = msmc-ses[priv_id][ses_pair].mpaxl;
+ *mpax = msmc-ses[priv_id][ses_pair].mpaxh;
+}
+
+void msmc_set_ses_mpax(int priv_id, int ses_pair, u32 *mpax)
+{
+ struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
+
+ msmc-ses[priv_id][ses_pair].mpaxl = *mpax++;
+ msmc-ses[priv_id][ses_pair].mpaxh = *mpax;
+}
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h
b/arch/arm/include/asm/arch-keystone/hardware.h
index 6e2e939..8e0b879 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -148,6 +148,12 @@ typedef volatile unsigned int *dv_reg_p;
#define KS2_MSMC_SEGMENT_QM_PDSP 10
#define KS2_MSMC_SEGMENT_PCIE0 11
+/* MSMC segment size shift bits */
+#define KS2_MSMC_SEG_SIZE_SHIFT12
+#define KS2_MSMC_MAP_SEG_NUM (2 (30 - KS2_MSMC_SEG_SIZE_SHIFT))
+#define KS2_MSMC_DST_SEG_BASE (CONFIG_SYS_LPAE_SDRAM_BASE \
+ KS2_MSMC_SEG_SIZE_SHIFT)
+
/* Device speed */
#define KS2_REV1_DEVSPEED (KS2_DEVICE_STATE_CTRL_BASE + 0xc98)
#define KS2_EFUSE_BOOTROM (KS2_DEVICE_STATE_CTRL_BASE + 0xc90)
diff --git a/arch/arm/include/asm/arch-keystone/msmc.h
b/arch/arm/include/asm/arch-keystone/msmc.h
index c320db5..083f5ba 100644
--- a/arch/arm/include/asm/arch-keystone/msmc.h
+++ b/arch/arm/include/asm/arch-keystone/msmc.h
@@ -12,6 +12,34 @@
#include asm/arch/hardware.h
+enum mpax_seg_size {
+ MPAX_SEG_4K = 0x0b,
+ MPAX_SEG_8K,
+ MPAX_SEG_16K,
+ MPAX_SEG_32K,
+ MPAX_SEG_64K,
+ MPAX_SEG_128K,
+ MPAX_SEG_256K,
+ MPAX_SEG_512K,
+ MPAX_SEG_1M,
+ MPAX_SEG_2M,
+ MPAX_SEG_4M,
+ MPAX_SEG_8M,
+ MPAX_SEG_16M,
+ MPAX_SEG_32M,
+ MPAX_SEG_64M,
+ MPAX_SEG_128M,
+ MPAX_SEG_256M,
+ MPAX_SEG_512M,
+ MPAX_SEG_1G,
+ MPAX_SEG_2G,
+ MPAX_SEG_4G
+};
+
void msmc_share_all_segments(int priv_id);
+void msmc_get_ses_mpax(int priv_id, int ses_pair, u32 *mpax);
+void msmc_set_ses_mpax(int priv_id, int ses_pair, u32 *mpax);
+void msmc_map_ses_segment(int priv_id, int ses_pair,
+ u32 src_pfn, u32 dst_pfn, enum mpax_seg_size size);
#endif
--
1.8.3.2
___
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