[U-Boot] [PATCH] ARM: DRA7: emif: Fix DDR init sequence during warm reset
Unlike OMAP5, EMIF PHY used in DRA7 will be left in unknown state after
warm reset, emif needs to be configured to bring it back to a known
state. So configure EMIF during warm reset.
Reported-by: Roger Quadros
Signed-off-by: Lokesh Vutla
---
arch/arm/cpu/armv7/omap-common/emif-common.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c
b/arch/arm/cpu/armv7/omap-common/emif-common.c
index ca22c00..f5b22f6 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -1170,7 +1170,7 @@ static void do_sdram_init(u32 base)
* Changing the timing registers in EMIF can happen(going from one
* OPP to another)
*/
- if (!(in_sdram || warm_reset())) {
+ if (!in_sdram && (!warm_reset() || is_dra7xx())) {
if (emif_sdram_type(regs->sdram_config) ==
EMIF_SDRAM_TYPE_LPDDR2)
lpddr2_init(base, regs);
@@ -1178,7 +1178,7 @@ static void do_sdram_init(u32 base)
ddr3_init(base, regs);
}
if (warm_reset() && (emif_sdram_type(regs->sdram_config) ==
- EMIF_SDRAM_TYPE_DDR3)) {
+ EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) {
set_lpmode_selfrefresh(base);
emif_reset_phy(base);
omap5_ddr3_leveling(base, regs);
--
1.9.1
___
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Re: [U-Boot] [PATCH 2/2] arm/ls102xa: Add PSCI support for ls102xa
Should be marked for V2 version.
*V2*:
Nothing has changed.
Regards,
-Dongsheng
> -Original Message-
> From: Dongsheng Wang [mailto:dongsheng.w...@freescale.com]
> Sent: Thursday, June 04, 2015 12:01 PM
> To: Sun York-R58495
> Cc: i...@hellion.org.uk; hdego...@redhat.com; albert.u.b...@aribaud.net;
> jan.kis...@siemens.com; Jin Zhengxiong-R64188; Wang Huan-B18965; Zhao Chenhui-
> B35336; u-boot@lists.denx.de; Wang Dongsheng-B40534
> Subject: [PATCH 2/2] arm/ls102xa: Add PSCI support for ls102xa
>
> From: Wang Dongsheng
>
> Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform.
>
> Tested on LS1021AQDS, LS1021ATWR.
> Test CPU hotplug times: 60K
> Test kernel boot times: 1.2K
>
> Signed-off-by: Wang Dongsheng
>
> diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile
> b/arch/arm/cpu/armv7/ls102xa/Makefile
> index 2e6a207..2d55782 100644
> --- a/arch/arm/cpu/armv7/ls102xa/Makefile
> +++ b/arch/arm/cpu/armv7/ls102xa/Makefile
> @@ -12,3 +12,7 @@ obj-y += fsl_epu.o
> obj-$(CONFIG_OF_LIBFDT) += fdt.o
> obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
> obj-$(CONFIG_SPL) += spl.o
> +
> +ifdef CONFIG_ARMV7_PSCI
> +obj-y += psci.o
> +endif
> diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S
> b/arch/arm/cpu/armv7/ls102xa/psci.S
> new file mode 100644
> index 000..cf5cd48
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/ls102xa/psci.S
> @@ -0,0 +1,126 @@
> +/*
> + * Copyright 2015 Freescale Semiconductor, Inc.
> + * Author: Wang Dongsheng
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include
> +#include
> +
> +#include
> +#include #include
> +
> +#define SCFG_CORE0_SFT_RST 0x130
> +#define SCFG_CORESRENCR 0x204
> +
> +#define DCFG_CCSR_BRR 0x0E4
> +#define DCFG_CCSR_SCRATCHRW10x200
> +
> + .pushsection ._secure.text, "ax"
> +
> + .arch_extension sec
> +
> +#define ONE_MS (GENERIC_TIMER_CLK / 1000)
> +#define RESET_WAIT (30 * ONE_MS)
> +
> + @ r1 = target CPU
> + @ r2 = target PC
> +.globl psci_cpu_on
> +psci_cpu_on:
> + push{lr}
> +
> + @ Clear and Get the correct CPU number
> + @ r1 = 0xf01
> + and r1, r1, #0xff
> +
> + mov r0, r1
> + bl psci_get_cpu_stack_top
> + str r2, [r0]
> + dsb
> +
> + @ Get DCFG base address
> + movwr4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0x)
> + movtr4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
> +
> + @ Detect target CPU state
> + ldr r2, [r4, #DCFG_CCSR_BRR]
> + rev r2, r2
> + lsr r2, r2, r1
> + andsr2, r2, #1
> + beq holdoff_release
> +
> + @ Reset target CPU
> + @ Get SCFG base address
> + movwr0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0x)
> + movtr0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16)
> +
> + @ Enable CORE Soft Reset
> + movwr5, #0
> + movtr5, #(1 << 15)
> + rev r5, r5
> + str r5, [r0, #SCFG_CORESRENCR]
> +
> + @ Get CPUx offset register
> + mov r6, #0x4
> + mul r6, r6, r1
> + add r2, r0, r6
> +
> + @ Do reset on target CPU
> + movwr5, #0
> + movtr5, #(1 << 15)
> + rev r5, r5
> + str r5, [r2, #SCFG_CORE0_SFT_RST]
> +
> + @ Wait target CPU up
> + timer_wait r2, RESET_WAIT
> +
> + @ Disable CORE soft reset
> + mov r5, #0
> + str r5, [r0, #SCFG_CORESRENCR]
> +
> +holdoff_release:
> + @ Release on target CPU
> + ldr r2, [r4, #DCFG_CCSR_BRR]
> + mov r6, #1
> + lsl r6, r6, r1 @ 32 bytes per CPU
> +
> + rev r6, r6
> + orr r2, r2, r6
> + str r2, [r4, #DCFG_CCSR_BRR]
> +
> + @ Set secondary boot entry
> + ldr r6, =psci_cpu_entry
> + rev r6, r6
> + str r6, [r4, #DCFG_CCSR_SCRATCHRW1]
> +
> + isb
> + dsb
> +
> + @ Return
> + mov r0, #ARM_PSCI_RET_SUCCESS
> +
> + pop {lr}
> + bx lr
> +
> +.globl psci_cpu_off
> +psci_cpu_off:
> + bl psci_cpu_off_common
> +
> +1: wfi
> + b 1b
> +
> +.globl psci_arch_init
> +psci_arch_init:
> + mov r6, lr
> +
> + bl psci_get_cpu_id
> + bl psci_get_cpu_stack_top
> + mov sp, r0
> +
> + bx r6
> +
> + .globl psci_text_end
> +psci_text_end:
> + .popsection
> diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index
> ca913b0..7232cd9 100644
> --- a/include/configs/ls1021aqds.h
> +++ b/include/configs/ls1021aqds.h
> @@ -11,6 +11,8 @@
>
> #define CONFIG_LS102XA
>
> +#define CONFIG_ARMV7_PSCI
> +
> #define CONFIG_SYS_GENERIC_BOARD
>
> #define CONFIG_DISPLAY_CPUINFO
> diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index
> 6b6f2ba..b618be5 100644
> --- a/include/configs/ls1021atwr.h
> +++ b/include/configs/ls1021atwr.h
> @@ -11,6 +11,8 @@
>
> #define CONFIG_LS102XA
>
> +#define CONFIG_ARMV7_PSCI
> +
> #define CONFIG_SYS_GENER
Re: [U-Boot] [PATCH 1/2] ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.S
Hi all,
Sorry I was too busy recently, and I forgot to tag version information.
The patches should be marked for V2 version.
*V2*:
1. Retain the original author's Copyright.
2. Based on Chen-Yu Tsai's patch rebase this patch, factor out time_wait
Macro from psci_sun7i.S and psci_sun6i.S.
Regards,
-Dongsheng
> -Original Message-
> From: Dongsheng Wang [mailto:dongsheng.w...@freescale.com]
> Sent: Thursday, June 04, 2015 12:01 PM
> To: Sun York-R58495
> Cc: i...@hellion.org.uk; hdego...@redhat.com; albert.u.b...@aribaud.net;
> jan.kis...@siemens.com; Jin Zhengxiong-R64188; Wang Huan-B18965; Zhao Chenhui-
> B35336; u-boot@lists.denx.de; Wang Dongsheng-B40534
> Subject: [PATCH 1/2] ARMv7: Factor out reusable timer_wait from
> sunxi/psci_sun7i.S
>
> From: Wang Dongsheng
>
> timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted
> completely into a reusable armv7 generic timer. LS1021A will use it
> as well.
>
> Signed-off-by: Wang Dongsheng
>
> diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
> b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
> index d4cb51e..4ff46e4 100644
> --- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
> +++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
> @@ -18,6 +18,8 @@
> */
>
> #include
> +
> +#include
> #include
> #include
> #include
> @@ -43,26 +45,6 @@
> #define GICD_BASE 0x1c81000
> #define GICC_BASE 0x1c82000
>
> -.macro timer_wait reg, ticks
> - @ Program CNTP_TVAL
> - movw\reg, #(\ticks & 0x)
> - movt\reg, #(\ticks >> 16)
> - mcr p15, 0, \reg, c14, c2, 0
> - isb
> - @ Enable physical timer, mask interrupt
> - mov \reg, #3
> - mcr p15, 0, \reg, c14, c2, 1
> - @ Poll physical timer until ISTATUS is on
> -1: isb
> - mrc p15, 0, \reg, c14, c2, 1
> - ands\reg, \reg, #4
> - bne 1b
> - @ Disable timer
> - mov \reg, #0
> - mcr p15, 0, \reg, c14, c2, 1
> - isb
> -.endm
> -
> .globl psci_fiq_enter
> psci_fiq_enter:
> push{r0-r12}
> diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
> b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
> index bbfeec8..e15d587 100644
> --- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
> +++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
> @@ -18,6 +18,8 @@
> */
>
> #include
> +
> +#include
> #include
> #include
> #include
> @@ -43,26 +45,6 @@
> #define GICD_BASE 0x1c81000
> #define GICC_BASE 0x1c82000
>
> -.macro timer_wait reg, ticks
> - @ Program CNTP_TVAL
> - movw\reg, #(\ticks & 0x)
> - movt\reg, #(\ticks >> 16)
> - mcr p15, 0, \reg, c14, c2, 0
> - isb
> - @ Enable physical timer, mask interrupt
> - mov \reg, #3
> - mcr p15, 0, \reg, c14, c2, 1
> - @ Poll physical timer until ISTATUS is on
> -1: isb
> - mrc p15, 0, \reg, c14, c2, 1
> - ands\reg, \reg, #4
> - bne 1b
> - @ Disable timer
> - mov \reg, #0
> - mcr p15, 0, \reg, c14, c2, 1
> - isb
> -.endm
> -
> .globl psci_fiq_enter
> psci_fiq_enter:
> push{r0-r12}
> diff --git a/arch/arm/include/asm/arch-armv7/generictimer.h
> b/arch/arm/include/asm/arch-armv7/generictimer.h
> new file mode 100644
> index 000..0956d7c
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-armv7/generictimer.h
> @@ -0,0 +1,50 @@
> +/*
> + * Copyright (C) 2013 - ARM Ltd
> + * Author: Marc Zyngier
> + *
> + * Based on code by Carl van Schaik .
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see
[U-Boot] [PATCH 1/2] ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.S
From: Wang Dongsheng
timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted
completely into a reusable armv7 generic timer. LS1021A will use it
as well.
Signed-off-by: Wang Dongsheng
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index d4cb51e..4ff46e4 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -18,6 +18,8 @@
*/
#include
+
+#include
#include
#include
#include
@@ -43,26 +45,6 @@
#defineGICD_BASE 0x1c81000
#defineGICC_BASE 0x1c82000
-.macro timer_wait reg, ticks
- @ Program CNTP_TVAL
- movw\reg, #(\ticks & 0x)
- movt\reg, #(\ticks >> 16)
- mcr p15, 0, \reg, c14, c2, 0
- isb
- @ Enable physical timer, mask interrupt
- mov \reg, #3
- mcr p15, 0, \reg, c14, c2, 1
- @ Poll physical timer until ISTATUS is on
-1: isb
- mrc p15, 0, \reg, c14, c2, 1
- ands\reg, \reg, #4
- bne 1b
- @ Disable timer
- mov \reg, #0
- mcr p15, 0, \reg, c14, c2, 1
- isb
-.endm
-
.globl psci_fiq_enter
psci_fiq_enter:
push{r0-r12}
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
index bbfeec8..e15d587 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
@@ -18,6 +18,8 @@
*/
#include
+
+#include
#include
#include
#include
@@ -43,26 +45,6 @@
#defineGICD_BASE 0x1c81000
#defineGICC_BASE 0x1c82000
-.macro timer_wait reg, ticks
- @ Program CNTP_TVAL
- movw\reg, #(\ticks & 0x)
- movt\reg, #(\ticks >> 16)
- mcr p15, 0, \reg, c14, c2, 0
- isb
- @ Enable physical timer, mask interrupt
- mov \reg, #3
- mcr p15, 0, \reg, c14, c2, 1
- @ Poll physical timer until ISTATUS is on
-1: isb
- mrc p15, 0, \reg, c14, c2, 1
- ands\reg, \reg, #4
- bne 1b
- @ Disable timer
- mov \reg, #0
- mcr p15, 0, \reg, c14, c2, 1
- isb
-.endm
-
.globl psci_fiq_enter
psci_fiq_enter:
push{r0-r12}
diff --git a/arch/arm/include/asm/arch-armv7/generictimer.h
b/arch/arm/include/asm/arch-armv7/generictimer.h
new file mode 100644
index 000..0956d7c
--- /dev/null
+++ b/arch/arm/include/asm/arch-armv7/generictimer.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2013 - ARM Ltd
+ * Author: Marc Zyngier
+ *
+ * Based on code by Carl van Schaik .
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see
[U-Boot] [PATCH 2/2] arm/ls102xa: Add PSCI support for ls102xa
From: Wang Dongsheng
Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform.
Tested on LS1021AQDS, LS1021ATWR.
Test CPU hotplug times: 60K
Test kernel boot times: 1.2K
Signed-off-by: Wang Dongsheng
diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile
b/arch/arm/cpu/armv7/ls102xa/Makefile
index 2e6a207..2d55782 100644
--- a/arch/arm/cpu/armv7/ls102xa/Makefile
+++ b/arch/arm/cpu/armv7/ls102xa/Makefile
@@ -12,3 +12,7 @@ obj-y += fsl_epu.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
obj-$(CONFIG_SPL) += spl.o
+
+ifdef CONFIG_ARMV7_PSCI
+obj-y += psci.o
+endif
diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S
b/arch/arm/cpu/armv7/ls102xa/psci.S
new file mode 100644
index 000..cf5cd48
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -0,0 +1,126 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ * Author: Wang Dongsheng
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+
+#include
+#include
+#include
+
+#define SCFG_CORE0_SFT_RST 0x130
+#define SCFG_CORESRENCR 0x204
+
+#define DCFG_CCSR_BRR 0x0E4
+#define DCFG_CCSR_SCRATCHRW10x200
+
+ .pushsection ._secure.text, "ax"
+
+ .arch_extension sec
+
+#defineONE_MS (GENERIC_TIMER_CLK / 1000)
+#defineRESET_WAIT (30 * ONE_MS)
+
+ @ r1 = target CPU
+ @ r2 = target PC
+.globl psci_cpu_on
+psci_cpu_on:
+ push{lr}
+
+ @ Clear and Get the correct CPU number
+ @ r1 = 0xf01
+ and r1, r1, #0xff
+
+ mov r0, r1
+ bl psci_get_cpu_stack_top
+ str r2, [r0]
+ dsb
+
+ @ Get DCFG base address
+ movwr4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0x)
+ movtr4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
+
+ @ Detect target CPU state
+ ldr r2, [r4, #DCFG_CCSR_BRR]
+ rev r2, r2
+ lsr r2, r2, r1
+ andsr2, r2, #1
+ beq holdoff_release
+
+ @ Reset target CPU
+ @ Get SCFG base address
+ movwr0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0x)
+ movtr0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16)
+
+ @ Enable CORE Soft Reset
+ movwr5, #0
+ movtr5, #(1 << 15)
+ rev r5, r5
+ str r5, [r0, #SCFG_CORESRENCR]
+
+ @ Get CPUx offset register
+ mov r6, #0x4
+ mul r6, r6, r1
+ add r2, r0, r6
+
+ @ Do reset on target CPU
+ movwr5, #0
+ movtr5, #(1 << 15)
+ rev r5, r5
+ str r5, [r2, #SCFG_CORE0_SFT_RST]
+
+ @ Wait target CPU up
+ timer_wait r2, RESET_WAIT
+
+ @ Disable CORE soft reset
+ mov r5, #0
+ str r5, [r0, #SCFG_CORESRENCR]
+
+holdoff_release:
+ @ Release on target CPU
+ ldr r2, [r4, #DCFG_CCSR_BRR]
+ mov r6, #1
+ lsl r6, r6, r1 @ 32 bytes per CPU
+
+ rev r6, r6
+ orr r2, r2, r6
+ str r2, [r4, #DCFG_CCSR_BRR]
+
+ @ Set secondary boot entry
+ ldr r6, =psci_cpu_entry
+ rev r6, r6
+ str r6, [r4, #DCFG_CCSR_SCRATCHRW1]
+
+ isb
+ dsb
+
+ @ Return
+ mov r0, #ARM_PSCI_RET_SUCCESS
+
+ pop {lr}
+ bx lr
+
+.globl psci_cpu_off
+psci_cpu_off:
+ bl psci_cpu_off_common
+
+1: wfi
+ b 1b
+
+.globl psci_arch_init
+psci_arch_init:
+ mov r6, lr
+
+ bl psci_get_cpu_id
+ bl psci_get_cpu_stack_top
+ mov sp, r0
+
+ bx r6
+
+ .globl psci_text_end
+psci_text_end:
+ .popsection
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index ca913b0..7232cd9 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -11,6 +11,8 @@
#define CONFIG_LS102XA
+#define CONFIG_ARMV7_PSCI
+
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_CPUINFO
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 6b6f2ba..b618be5 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -11,6 +11,8 @@
#define CONFIG_LS102XA
+#define CONFIG_ARMV7_PSCI
+
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_CPUINFO
--
2.1.0.27.g96db324
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Re: [U-Boot] [RFC PATCH 2/2] x86: fsp: Move FspInitEntry call to board_init_f()
Hi Bin, On 3 June 2015 at 06:59, Andrew Bradford wrote: > On 06/03 07:17, Bin Meng wrote: >> Hi Andrew, >> >> On Wed, Jun 3, 2015 at 4:05 AM, Andrew Bradford >> wrote: >> > Hi Bin, >> > >> > On 06/01 20:31, Bin Meng wrote: >> >> The call to FspInitEntry is done in arch/x86/lib/fsp/fsp_car.S so far. >> >> It worked pretty well but looks not that good. Apart from doing too >> >> much work than just enabling CAR, it cannot read the configuration >> >> data from device tree at that time. Now we want to move it a little >> >> bit later as part of init_sequence_f[] being called by board_init_f(). >> >> This way it looks and works better in the U-Boot initialization path. >> >> >> >> Due to FSP's design, after calling FspInitEntry it will not return to >> >> its caller, instead it jumps to a continuation function which is given >> >> by bootloader with a new stack in system memory. The original stack in >> >> the CAR is gone, but its content is perserved by FSP and described by >> >> a bootloader temporary memory HOB. Technically we can recover anything >> >> we had before in the previous stack, but that is way too complicated. >> >> To make life much easier, in the FSP continuation routine we just >> >> simply call fsp_init_done() and jump back to car_init_ret() to redo >> >> the whole board_init_f() initialization, but this time with a non-zero >> >> HOB list pointer saved in U-Boot's global data so that we can bypass >> >> the FspInitEntry for the second time. >> >> >> >> Signed-off-by: Bin Meng >> >> >> >> --- >> >> >> >> arch/x86/cpu/start.S | 6 +- >> >> arch/x86/include/asm/u-boot-x86.h | 4 >> >> arch/x86/lib/fsp/fsp_car.S| 26 +- >> >> arch/x86/lib/fsp/fsp_common.c | 8 >> >> common/board_f.c | 3 +++ >> >> 5 files changed, 25 insertions(+), 22 deletions(-) >> >> >> >> diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S >> >> index 2e5f9da..00e585e 100644 >> >> --- a/arch/x86/cpu/start.S >> >> +++ b/arch/x86/cpu/start.S >> >> @@ -116,12 +116,16 @@ car_init_ret: >> >> rep stosb >> >> >> >> #ifdef CONFIG_HAVE_FSP >> >> + test%esi, %esi >> >> + jz skip_hob >> >> + >> >> /* Store HOB list */ >> >> movl%esp, %edx >> >> addl$GD_HOB_LIST, %edx >> >> movl%esi, (%edx) >> >> -#endif >> >> >> >> +skip_hob: >> >> +#endif >> >> /* Setup first parameter to setup_gdt, pointer to global_data */ >> >> movl%esp, %eax >> >> >> >> diff --git a/arch/x86/include/asm/u-boot-x86.h >> >> b/arch/x86/include/asm/u-boot-x86.h >> >> index faa5182..9ee4104 100644 >> >> --- a/arch/x86/include/asm/u-boot-x86.h >> >> +++ b/arch/x86/include/asm/u-boot-x86.h >> >> @@ -54,6 +54,10 @@ u32 isa_map_rom(u32 bus_addr, int size); >> >> /* arch/x86/lib/... */ >> >> int video_bios_init(void); >> >> >> >> +#ifdef CONFIG_HAVE_FSP >> >> +int x86_fsp_init(void); >> >> +#endif >> >> + >> >> void board_init_f_r_trampoline(ulong) __attribute__ ((noreturn)); >> >> void board_init_f_r(void) __attribute__ ((noreturn)); >> >> >> >> diff --git a/arch/x86/lib/fsp/fsp_car.S b/arch/x86/lib/fsp/fsp_car.S >> >> index 5e09568..afbf3f9 100644 >> >> --- a/arch/x86/lib/fsp/fsp_car.S >> >> +++ b/arch/x86/lib/fsp/fsp_car.S >> >> @@ -56,28 +56,10 @@ temp_ram_init_ret: >> >> >> >> /* stack grows down from top of CAR */ >> >> movl%edx, %esp >> >> + subl$4, %esp >> >> >> >> - /* >> >> - * TODO: >> >> - * >> >> - * According to FSP architecture spec, the fsp_init() will not >> >> return >> >> - * to its caller, instead it requires the bootloader to provide a >> >> - * so-called continuation function to pass into the FSP as a >> >> parameter >> >> - * of fsp_init, and fsp_init() will call that continuation function >> >> - * directly. >> >> - * >> >> - * The call to fsp_init() may need to be moved out of the car_init() >> >> - * to cpu_init_f() with the help of some inline assembly codes. >> >> - * Note there is another issue that fsp_init() will setup another >> >> stack >> >> - * using the fsp_init parameter stack_top after DRAM is initialized, >> >> - * which means any data on the previous stack (on the CAR) gets lost >> >> - * (ie: U-Boot global_data). FSP is supposed to support such >> >> scenario, >> >> - * however it does not work. This should be revisited in the future. >> >> - */ >> >> - movl$CONFIG_FSP_TEMP_RAM_ADDR, %eax >> >> - xorl%edx, %edx >> >> - xorl%ecx, %ecx >> >> - callfsp_init >> >> + xor %esi, %esi >> >> + jmp car_init_done >> >> >> >> .global fsp_init_done >> >> fsp_init_done: >> >> @@ -86,6 +68,8 @@ fsp_init_done: >> >>* Save eax to esi temporarily. >> >>*/ >> >> movl%eax, %esi >> >> + >> >> +car_init_done: >> >> /* >> >>* Re-initialize the ebp (BIST) to zero, as we already
Re: [U-Boot] Building u-boot.rom for Minnowboard
Hi John, On 3 June 2015 at 18:13, Bin Meng wrote: > Hi, > > On Thu, Jun 4, 2015 at 5:44 AM, John Hawley wrote: >> Ok some more data points. I tested with the FSP3 Gold that Saket built, >> and it continues to work on the A0, but it continues to not work on the >> A2 D0 board I have. I'm guessing this is something between the >> steppings in the CPU and the FSP, but I'm not sure. >> >> Adding Vincent to this, as I'm guessing there is something going on here >> with the interaction with the FSP (since it works on an A0 B3, but not >> an A2 D0) >> >> - John >> >> On 06/03/2015 01:24 PM, Saket Sinha wrote: >>> Hi, >>> I'm 99% sure that's the issue. try with FSP 3 gold." I am now trying to build the u-boot.rom from FSP 3 gold and would let you know about the results ASAP. >>> >>> u-boot.rom prepared from FSP3-Gold dowmloaded from >>> https://downloadcenter.intel.com/download/24496 doesn't work with the >>> minnowmax I have. >>> >>> Regards, >>> Saket Sinha >>> > > Given even with Simon's debug UART WIP patch, the A2 D0 board still > has nothing output, I suspect that the FspTempRamInit() call failed > due to the microcode loading. Could it be the problem that the > microcode passed to the FSP is a little bit old that it does not > support the D0 stepping. Can you try some newer version microcode to > see if there is any luck? I was using the Gold3 version. Is there a new microcode we could try? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] x86: baytrail: pci region 3 is not always mapped to end of ram
On Thu, Jun 4, 2015 at 12:37 AM, wrote: > From: Andrew Bradford > > Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFF > and additional SDRAM is mapped from 0x1 and up. There is a > physical memory hole from 0x8000 to 0x for other uses. > Because of this, PCI region 3 should only try to use up to the amount of > SDRAM or 0x8000, which ever is less. > > Signed-off-by: Andrew Bradford > --- > v3: Fix build breakage due to semicolon > v2: limit maximum size to lesser of SDRAM or 0x8000 > --- > arch/x86/cpu/baytrail/pci.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/x86/cpu/baytrail/pci.c b/arch/x86/cpu/baytrail/pci.c > index 6c291f9..48409de 100644 > --- a/arch/x86/cpu/baytrail/pci.c > +++ b/arch/x86/cpu/baytrail/pci.c > @@ -39,7 +39,7 @@ void board_pci_setup_hose(struct pci_controller *hose) > pci_set_region(hose->regions + 3, >0, >0, > - gd->ram_size, > + gd->ram_size < 0x8000 ? gd->ram_size : 0x8000, >PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); > > hose->region_count = 4; > -- Reviewed-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Building u-boot.rom for Minnowboard
Hi, On Thu, Jun 4, 2015 at 5:44 AM, John Hawley wrote: > Ok some more data points. I tested with the FSP3 Gold that Saket built, > and it continues to work on the A0, but it continues to not work on the > A2 D0 board I have. I'm guessing this is something between the > steppings in the CPU and the FSP, but I'm not sure. > > Adding Vincent to this, as I'm guessing there is something going on here > with the interaction with the FSP (since it works on an A0 B3, but not > an A2 D0) > > - John > > On 06/03/2015 01:24 PM, Saket Sinha wrote: >> Hi, >> >>> I'm 99% sure that's the issue. try with FSP 3 gold." >>> >>> I am now trying to build the u-boot.rom from FSP 3 gold and would let >>> you know about the results ASAP. >> >> u-boot.rom prepared from FSP3-Gold dowmloaded from >> https://downloadcenter.intel.com/download/24496 doesn't work with the >> minnowmax I have. >> >> Regards, >> Saket Sinha >> Given even with Simon's debug UART WIP patch, the A2 D0 board still has nothing output, I suspect that the FspTempRamInit() call failed due to the microcode loading. Could it be the problem that the microcode passed to the FSP is a little bit old that it does not support the D0 stepping. Can you try some newer version microcode to see if there is any luck? Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] sunxi: Select CONFIG_CMD_NET and CONFIG_CMD_SETEXPR by default
On Wed, Jun 3, 2015 at 5:26 PM, Tom Rini wrote: > On Wed, Jun 03, 2015 at 05:21:44PM -0500, Joe Hershberger wrote: >> Hi Tom, >> >> On Wed, Jun 3, 2015 at 5:12 PM, Tom Rini wrote: >> > On Wed, Jun 03, 2015 at 08:12:16PM +0200, Hans de Goede wrote: >> > >> >> Select CONFIG_CMD_NET and CONFIG_CMD_SETEXPR by default rather then >> >> needing to have this in every sunxi defconfig file. >> >> >> >> This also fixes the Merrii_A80_Optimus defconfig no longer building. >> >> >> >> Cc: Maxin B. John >> >> Reported-by: Maxin B. John >> >> Signed-off-by: Hans de Goede >> > >> > Joe? Masahiro? It feels like something has gone wrong with the >> > conversion here. Or do people need to get used to the defconfig files >> > being a non-trivial size? Or do we need some more default y if ... >> > lines around things? Or a few of the above? Thanks! >> >> It seems we should select good defaults. Maybe we should try to agree >> which way we should err. Make u-boot bigger by default, and boards >> that are limited can disable features? Or should we enable commands on >> boards that "need" a feature and keep u-boot slim by default? >> >> I don't like the half measure of defining a different default for one >> platform than another unless it is actually something inherent in the >> platform, and in that case it should be enabled by a "selects" under >> the platform Kconfig. >> >> I agree we want to have smaller defconfigs rather than bigger, but >> there are lots of features and many boards will not agree, so the >> defconfigs of many boards will have to contain something. > > The first thing that pops to mind is that if it used to be in > config_cmd_default.h it should be on by default and disabled when needed > (and this means we can be smart about CMD_FLASH / CMD_IMLS). Otherwise > we need to think hard on if something new should be on by default or > not. I have the gut feeling that things that depend on hardware existing (such as CMD_NET) should not be default. However, I guess if it's totally ubiquitous (such as CMD_MEMORY - though it's already in config_cmd_default.h) then it should be default just to shrink the defconfigs. Ian, you indicated that you thought CMD_NET should be a default since it is usually wanted. It seems that is generally the case. It looks like 94% of boards enable CMD_NET, which makes it pretty much ubiquitous. Perhaps that should be the metric for deciding (probably with flexibility for making an argument to the contrary)... if more that 80% (good enough water-mark?) of the boards enable a feature, then it should be the default? 50% would optimize for overall defconfig size... maybe that's better? -Joe ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] sunxi: Select CONFIG_CMD_NET and CONFIG_CMD_SETEXPR by default
On Wed, Jun 03, 2015 at 05:21:44PM -0500, Joe Hershberger wrote: > Hi Tom, > > On Wed, Jun 3, 2015 at 5:12 PM, Tom Rini wrote: > > On Wed, Jun 03, 2015 at 08:12:16PM +0200, Hans de Goede wrote: > > > >> Select CONFIG_CMD_NET and CONFIG_CMD_SETEXPR by default rather then > >> needing to have this in every sunxi defconfig file. > >> > >> This also fixes the Merrii_A80_Optimus defconfig no longer building. > >> > >> Cc: Maxin B. John > >> Reported-by: Maxin B. John > >> Signed-off-by: Hans de Goede > > > > Joe? Masahiro? It feels like something has gone wrong with the > > conversion here. Or do people need to get used to the defconfig files > > being a non-trivial size? Or do we need some more default y if ... > > lines around things? Or a few of the above? Thanks! > > It seems we should select good defaults. Maybe we should try to agree > which way we should err. Make u-boot bigger by default, and boards > that are limited can disable features? Or should we enable commands on > boards that "need" a feature and keep u-boot slim by default? > > I don't like the half measure of defining a different default for one > platform than another unless it is actually something inherent in the > platform, and in that case it should be enabled by a "selects" under > the platform Kconfig. > > I agree we want to have smaller defconfigs rather than bigger, but > there are lots of features and many boards will not agree, so the > defconfigs of many boards will have to contain something. The first thing that pops to mind is that if it used to be in config_cmd_default.h it should be on by default and disabled when needed (and this means we can be smart about CMD_FLASH / CMD_IMLS). Otherwise we need to think hard on if something new should be on by default or not. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] sunxi: Select CONFIG_CMD_NET and CONFIG_CMD_SETEXPR by default
Hi Tom, On Wed, Jun 3, 2015 at 5:12 PM, Tom Rini wrote: > On Wed, Jun 03, 2015 at 08:12:16PM +0200, Hans de Goede wrote: > >> Select CONFIG_CMD_NET and CONFIG_CMD_SETEXPR by default rather then >> needing to have this in every sunxi defconfig file. >> >> This also fixes the Merrii_A80_Optimus defconfig no longer building. >> >> Cc: Maxin B. John >> Reported-by: Maxin B. John >> Signed-off-by: Hans de Goede > > Joe? Masahiro? It feels like something has gone wrong with the > conversion here. Or do people need to get used to the defconfig files > being a non-trivial size? Or do we need some more default y if ... > lines around things? Or a few of the above? Thanks! It seems we should select good defaults. Maybe we should try to agree which way we should err. Make u-boot bigger by default, and boards that are limited can disable features? Or should we enable commands on boards that "need" a feature and keep u-boot slim by default? I don't like the half measure of defining a different default for one platform than another unless it is actually something inherent in the platform, and in that case it should be enabled by a "selects" under the platform Kconfig. I agree we want to have smaller defconfigs rather than bigger, but there are lots of features and many boards will not agree, so the defconfigs of many boards will have to contain something. -Joe ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] sunxi: Select CONFIG_CMD_NET and CONFIG_CMD_SETEXPR by default
On Wed, Jun 03, 2015 at 08:12:16PM +0200, Hans de Goede wrote: > Select CONFIG_CMD_NET and CONFIG_CMD_SETEXPR by default rather then > needing to have this in every sunxi defconfig file. > > This also fixes the Merrii_A80_Optimus defconfig no longer building. > > Cc: Maxin B. John > Reported-by: Maxin B. John > Signed-off-by: Hans de Goede Joe? Masahiro? It feels like something has gone wrong with the conversion here. Or do people need to get used to the defconfig files being a non-trivial size? Or do we need some more default y if ... lines around things? Or a few of the above? Thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Building u-boot.rom for Minnowboard
Ok some more data points. I tested with the FSP3 Gold that Saket built, and it continues to work on the A0, but it continues to not work on the A2 D0 board I have. I'm guessing this is something between the steppings in the CPU and the FSP, but I'm not sure. Adding Vincent to this, as I'm guessing there is something going on here with the interaction with the FSP (since it works on an A0 B3, but not an A2 D0) - John On 06/03/2015 01:24 PM, Saket Sinha wrote: > Hi, > >> I'm 99% sure that's the issue. try with FSP 3 gold." >> >> I am now trying to build the u-boot.rom from FSP 3 gold and would let >> you know about the results ASAP. > > u-boot.rom prepared from FSP3-Gold dowmloaded from > https://downloadcenter.intel.com/download/24496 doesn't work with the > minnowmax I have. > > Regards, > Saket Sinha > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Building u-boot.rom for Minnowboard
Hi, > I'm 99% sure that's the issue. try with FSP 3 gold." > > I am now trying to build the u-boot.rom from FSP 3 gold and would let > you know about the results ASAP. u-boot.rom prepared from FSP3-Gold dowmloaded from https://downloadcenter.intel.com/download/24496 doesn't work with the minnowmax I have. Regards, Saket Sinha ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] sunxi: Select CONFIG_CMD_NET and CONFIG_CMD_SETEXPR by default
On Wed, 2015-06-03 at 20:12 +0200, Hans de Goede wrote: > Select CONFIG_CMD_NET and CONFIG_CMD_SETEXPR by default rather then > needing to have this in every sunxi defconfig file. > > This also fixes the Merrii_A80_Optimus defconfig no longer building. > > Cc: Maxin B. John > Reported-by: Maxin B. John > Signed-off-by: Hans de Goede Seem like the sorts of things which ought to be default y at the actual definition, since they would usually be wanted I think, but anyway: Acked-by: Ian Campbell ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] sunxi: Add new Mele_A1000G_quad defconfig
On Wed, 2015-06-03 at 16:09 +0200, Hans de Goede wrote: > Ah yes the W: option in MAINTAINERS is indeed the best place to > stick URL-s, thanks for your input. Agreed. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Building u-boot.rom for Minnowboard
Hi Simon, >>> I might be able to create an image that prints out post_code() calls. > > I added a debug UART image here: > https://drive.google.com/folderview?id=0B7WYZbZ9zd-3flBfMEk3WHRSclJDWHFxOWlQTlBEUHg3aGM0aUZhLTdMYWVGbm9HNXNYTlU&usp=sharing > The results are identical as that of previous image. I still get no output on serial. Tried flashing the image with both falshrom(Linux) and Dediprog software(Windows). I even began to doubt my serial connection on Linux so switched to Teraterm on Windows but still no output on serial. > Are you able to progress by using qemu in the meantime? Yes. My first approach was to extract the acpi tables from fw_cfg. That is failing for u-boot but works for coreboot. I have discussed this issue with Bin. Now I am trying to write ACPI tables(i.e. builtin ACPI) for qemu-x86. This is case that should be generic and would be hit for minnowmax also. >>> Will wait to hear from John. Just had a word with John.he seems to get identical results as me for both the images that you shared. Would like to quote him - "so my suspicion is that Simon is building the firmware with a slightly older FSP specifically an FSP that doesn't support the newer stepping on the CPU. I just flashed the debug one on an A0 (ancient board obviously) and I get some output. I get nothing on my newer A2 w/ a D0 stepped CPU . All that needs to happen is to use a newer FSP. The board you have I'm pretty sure is an A2 board with a D0 stepping cpu. It's possible that Simon got his board long enough ago that he's got an A1 or A2 with a B3 stepping cpu I.E. that explains why it works for him, and not you. I'm 99% sure that's the issue. try with FSP 3 gold." I am now trying to build the u-boot.rom from FSP 3 gold and would let you know about the results ASAP. Regards, Saket Sinha ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] sunxi: Select CONFIG_CMD_NET and CONFIG_CMD_SETEXPR by default
Select CONFIG_CMD_NET and CONFIG_CMD_SETEXPR by default rather then needing to have this in every sunxi defconfig file. This also fixes the Merrii_A80_Optimus defconfig no longer building. Cc: Maxin B. John Reported-by: Maxin B. John Signed-off-by: Hans de Goede --- board/sunxi/Kconfig | 6 ++ configs/A10-OLinuXino-Lime_defconfig | 2 -- configs/A10s-OLinuXino-M_defconfig | 2 -- configs/A13-OLinuXinoM_defconfig | 2 -- configs/A13-OLinuXino_defconfig | 2 -- configs/A20-OLinuXino-Lime2_defconfig| 2 -- configs/A20-OLinuXino-Lime_defconfig | 2 -- configs/A20-OLinuXino_MICRO_defconfig| 2 -- configs/Ainol_AW1_defconfig | 2 -- configs/Ampe_A76_defconfig | 2 -- configs/Auxtek-T004_defconfig| 2 -- configs/Bananapi_defconfig | 2 -- configs/Bananapro_defconfig | 2 -- configs/CSQ_CS908_defconfig | 2 -- configs/Chuwi_V7_CW0825_defconfig| 2 -- configs/Colombus_defconfig | 2 -- configs/Cubieboard2_defconfig| 2 -- configs/Cubieboard_defconfig | 2 -- configs/Cubietruck_defconfig | 2 -- configs/Et_q8_v1_6_defconfig | 2 -- configs/Hummingbird_A31_defconfig| 2 -- configs/Hyundai_A7HD_defconfig | 2 -- configs/Ippo_q8h_v1_2_a33_1024x600_defconfig | 2 -- configs/Ippo_q8h_v1_2_defconfig | 2 -- configs/Ippo_q8h_v5_defconfig| 2 -- configs/Linksprite_pcDuino3_Nano_defconfig | 2 -- configs/Linksprite_pcDuino3_defconfig| 2 -- configs/Linksprite_pcDuino_defconfig | 2 -- configs/MK808C_defconfig | 2 -- configs/MSI_Primo73_defconfig| 2 -- configs/MSI_Primo81_defconfig| 2 -- configs/Marsboard_A10_defconfig | 2 -- configs/Mele_A1000_defconfig | 2 -- configs/Mele_I7_defconfig| 2 -- configs/Mele_M3_defconfig| 2 -- configs/Mele_M5_defconfig| 2 -- configs/Mele_M9_defconfig| 2 -- configs/Mini-X_defconfig | 2 -- configs/Orangepi_defconfig | 2 -- configs/Orangepi_mini_defconfig | 2 -- configs/TZX-Q8-713B7_defconfig | 2 -- configs/UTOO_P66_defconfig | 2 -- configs/Wexler_TAB7200_defconfig | 2 -- configs/Wits_Pro_A20_DKT_defconfig | 2 -- configs/Yones_Toptech_BD1078_defconfig | 2 -- configs/ba10_tv_box_defconfig| 2 -- configs/forfun_q88db_defconfig | 2 -- configs/ga10h_v1_1_defconfig | 2 -- configs/i12-tvbox_defconfig | 2 -- configs/iNet_3F_defconfig| 2 -- configs/iNet_3W_defconfig| 2 -- configs/iNet_86VS_defconfig | 2 -- configs/jesurun_q5_defconfig | 2 -- configs/mixtile_loftq_defconfig | 2 -- configs/mk802_a10s_defconfig | 2 -- configs/mk802_defconfig | 2 -- configs/mk802ii_defconfig| 2 -- configs/r7-tv-dongle_defconfig | 2 -- configs/sunxi_Gemei_G9_defconfig | 2 -- 59 files changed, 6 insertions(+), 116 deletions(-) diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index e744d4a..b2eca51 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -581,4 +581,10 @@ config DM_SERIAL config DM_USB default y if !USB_MUSB_SUNXI +config CMD_SETEXPR + default y + +config CMD_NET + default y + endif diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig index c46279e..971e11a 100644 --- a/configs/A10-OLinuXino-Lime_defconfig +++ b/configs/A10-OLinuXino-Lime_defconfig @@ -7,5 +7,3 @@ CONFIG_SYS_CLK_FREQ=91200 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime" CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI" -CONFIG_CMD_SETEXPR=y -CONFIG_CMD_NET=y diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig index 0fbc880..d4953aa 100644 --- a/configs/A10s-OLinuXino-M_defconfig +++ b/configs/A10s-OLinuXino-M_defconfig @@ -9,5 +9,3 @@ CONFIG_USB1_VBUS_PIN="PB10" CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-olinuxino-micro" CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,SUNXI_EMAC,USB_EHCI" -CONFIG_CMD_SETEXPR=y -CONFIG_CMD_NET=y diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig index 5d541b0..4bee362 100644 --- a/configs/A13-OLinuXinoM_defconfig +++ b/configs/A13-OLinuXinoM_defconfig @@ -13,5 +13,3 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino-micro" CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,USB_EHCI" -CONFIG_CM
Re: [U-Boot] [patch] armv7: better comment in start.S
Hello Pavel, On Wed, 8 Apr 2015 14:15:54 +0200, Pavel Machek wrote: > > Fix big/small letters in comment. > > Signed-off-by: Pavel Machek > > diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S > index 5ed0f45..1c7e6f0 100644 > --- a/arch/arm/cpu/armv7/start.S > +++ b/arch/arm/cpu/armv7/start.S > @@ -22,10 +22,9 @@ > * > * Startup Code (reset vector) > * > - * do important init only if we don't start from memory! > - * setup Memory and board specific bits prior to relocation. > - * relocate armboot to ram > - * setup stack > + * Do important init only if we don't start from memory! > + * Setup memory and board specific bits prior to relocation. > + * Relocate armboot to ram. Setup stack. > * > */ > > > > -- > (english) http://www.livejournal.com/~pavelmachek > (cesky, pictures) > http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html Applied to u-boot-arm/master, thanks! Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] gpio: lpc32xx: Use priv_data instead of platdata
Hello Axel,
On Tue, 14 Apr 2015 14:55:24 +0800, Axel Lin wrote:
> The LPC32XX GPIO driver platdata currently contains GPIO state information,
> which should go into priv_data. Thus rename lpc32xx_gpio_platdata to
> lpc32xx_gpio_priv and convert to use dev_get_priv() instead.
>
> Signed-off-by: Axel Lin
> ---
> v2: Update commit log to mention that using priv_data for runtime state
> which was stored in platdata.
> drivers/gpio/lpc32xx_gpio.c | 39 +++
> 1 file changed, 19 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpio/lpc32xx_gpio.c b/drivers/gpio/lpc32xx_gpio.c
> index 96b3125..8a9826e 100644
> --- a/drivers/gpio/lpc32xx_gpio.c
> +++ b/drivers/gpio/lpc32xx_gpio.c
> @@ -37,7 +37,7 @@
>
> #define LPC32XX_GPIOS 128
>
> -struct lpc32xx_gpio_platdata {
> +struct lpc32xx_gpio_priv {
> struct gpio_regs *regs;
> /* GPIO FUNCTION: SEE WARNING #2 */
> signed char function[LPC32XX_GPIOS];
> @@ -60,8 +60,8 @@ struct lpc32xx_gpio_platdata {
> static int lpc32xx_gpio_direction_input(struct udevice *dev, unsigned offset)
> {
> int port, mask;
> - struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev);
> - struct gpio_regs *regs = gpio_platdata->regs;
> + struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
> + struct gpio_regs *regs = gpio_priv->regs;
>
> port = GPIO_TO_PORT(offset);
> mask = GPIO_TO_MASK(offset);
> @@ -83,7 +83,7 @@ static int lpc32xx_gpio_direction_input(struct udevice
> *dev, unsigned offset)
> }
>
> /* GPIO FUNCTION: SEE WARNING #2 */
> - gpio_platdata->function[offset] = GPIOF_INPUT;
> + gpio_priv->function[offset] = GPIOF_INPUT;
>
> return 0;
> }
> @@ -95,8 +95,8 @@ static int lpc32xx_gpio_direction_input(struct udevice
> *dev, unsigned offset)
> static int lpc32xx_gpio_get_value(struct udevice *dev, unsigned offset)
> {
> int port, rank, mask, value;
> - struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev);
> - struct gpio_regs *regs = gpio_platdata->regs;
> + struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
> + struct gpio_regs *regs = gpio_priv->regs;
>
> port = GPIO_TO_PORT(offset);
>
> @@ -130,8 +130,8 @@ static int lpc32xx_gpio_get_value(struct udevice *dev,
> unsigned offset)
> static int gpio_set(struct udevice *dev, unsigned gpio)
> {
> int port, mask;
> - struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev);
> - struct gpio_regs *regs = gpio_platdata->regs;
> + struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
> + struct gpio_regs *regs = gpio_priv->regs;
>
> port = GPIO_TO_PORT(gpio);
> mask = GPIO_TO_MASK(gpio);
> @@ -162,8 +162,8 @@ static int gpio_set(struct udevice *dev, unsigned gpio)
> static int gpio_clr(struct udevice *dev, unsigned gpio)
> {
> int port, mask;
> - struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev);
> - struct gpio_regs *regs = gpio_platdata->regs;
> + struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
> + struct gpio_regs *regs = gpio_priv->regs;
>
> port = GPIO_TO_PORT(gpio);
> mask = GPIO_TO_MASK(gpio);
> @@ -208,8 +208,8 @@ static int lpc32xx_gpio_direction_output(struct udevice
> *dev, unsigned offset,
> int value)
> {
> int port, mask;
> - struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev);
> - struct gpio_regs *regs = gpio_platdata->regs;
> + struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
> + struct gpio_regs *regs = gpio_priv->regs;
>
> port = GPIO_TO_PORT(offset);
> mask = GPIO_TO_MASK(offset);
> @@ -231,7 +231,7 @@ static int lpc32xx_gpio_direction_output(struct udevice
> *dev, unsigned offset,
> }
>
> /* GPIO FUNCTION: SEE WARNING #2 */
> - gpio_platdata->function[offset] = GPIOF_OUTPUT;
> + gpio_priv->function[offset] = GPIOF_OUTPUT;
>
> return lpc32xx_gpio_set_value(dev, offset, value);
> }
> @@ -251,8 +251,8 @@ static int lpc32xx_gpio_direction_output(struct udevice
> *dev, unsigned offset,
>
> static int lpc32xx_gpio_get_function(struct udevice *dev, unsigned offset)
> {
> - struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev);
> - return gpio_platdata->function[offset];
> + struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
> + return gpio_priv->function[offset];
> }
>
> static const struct dm_gpio_ops gpio_lpc32xx_ops = {
> @@ -265,7 +265,7 @@ static const struct dm_gpio_ops gpio_lpc32xx_ops = {
>
> static int lpc32xx_gpio_probe(struct udevice *dev)
> {
> - struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev);
> + struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
> struct gpio_dev_priv *uc_priv = dev->uclass_priv;
>
> if (dev->of_offset == -1) {
> @@ -274,12 +274,11 @@ static int
[U-Boot] [RFC] [PATCH] omap-common: Common boot code OMAP3 support and cleanup
This patch introduces some changes to the omap common boot code, to allow the
omap3 to benefit from it, but also to clean it up drastically.
It was tested on an OMAP3 device booting from MMC.
Since this also affects OMAP4, OMAP5 and AM33xx devices, I'm looking forward
to having this tested on boards using those platforms. Since I do not own any
such device, I cannot do the testing on them myself.
While writing this patch, I came to learn about the boot device descriptor, as
mentioned in the "Device Initialization by ROM Code" part of the OMAP36xx TRM.
The booting parameter structure (for which the address is given in r0 by the
bootrom when starting the U-Boot SPL) holds the address of that device
descriptor, but I could not find any description of what its contents are.
However, it was apparently being used on != OMAP3 devices, so I just adapted
the same logic blindly and used the traditional switch/case for omap3.
That said, the OMAP3 also has this descriptor, so I tried to read it when
booting the U-Boot SPL from MMC. I got the following:
boot device descriptor at 0x4020fbc0
boot device descriptor device data at 0x4020f524
boot mode ends up being 4
Now I would be interested in precise documentation about the fields of that
descriptor (and that device data too) where the mmc boot mode is supposed to be
stored. The value on omap3 is not usable as-is, so it's either a wrong offset
or the mmc boot mode is not part of the structure on omap3.
If there is no reason to use a static switch/case for omap3, I'd much rather do
away with it. If not, I'd like to have certainty about that fact.
In order to list the various values held there, here is a diff that I applied.
I would be happy to get feedback from other omap platforms. It goes on top of
this patch:
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c
b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 3bd3f49..0ca3646 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -67,6 +67,7 @@ void save_omap_boot_params(void)
if ((boot_device >= MMC_BOOT_DEVICES_START) &&
(boot_device <= MMC_BOOT_DEVICES_END)) {
+/*
#ifdef CONFIG_OMAP34XX
switch (boot_device) {
case BOOT_DEVICE_MMC1:
@@ -77,18 +78,21 @@ void save_omap_boot_params(void)
break;
}
#else
+*/
boot_params = omap_boot_params->boot_device_descriptor;
+printf("boot device descriptor at 0x%x\n", boot_params);
if ((boot_params < NON_SECURE_SRAM_START) ||
(boot_params > NON_SECURE_SRAM_END))
return;
boot_params = *((u32 *)(boot_params + DEVICE_DATA_OFFSET));
+printf("boot device descriptor device data at 0x%x\n", boot_params);
if ((boot_params < NON_SECURE_SRAM_START) ||
(boot_params > NON_SECURE_SRAM_END))
return;
boot_mode = *((u32 *)(boot_params + BOOT_MODE_OFFSET));
-
+printf("boot mode ends up being %d\n", boot_mode);
if (boot_mode != MMCSD_MODE_FS &&
boot_mode != MMCSD_MODE_RAW)
#ifdef CONFIG_SUPPORT_EMMC_BOOT
@@ -96,7 +100,7 @@ void save_omap_boot_params(void)
#else
boot_mode = MMCSD_MODE_UNDEFINED;
#endif
-#endif
+//#endif
}
gd->arch.omap_boot_mode = boot_mode;
@@ -124,11 +128,12 @@ void spl_board_init(void)
* We cannot delay the saving further than this,
* to prevent overwrites.
*/
- save_omap_boot_params();
/* Prepare console output */
preloader_console_init();
+ save_omap_boot_params();
+
#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT)
gpmc_init();
#endif
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[U-Boot] [PATCH] omap-common: Common boot code OMAP3 support and cleanup
This introduces OMAP3 support for the common omap boot code, as well as a
major cleanup of the common omap boot code.
First, the omap_boot_parameters structure becomes platform-specific, since its
definition differs a bit across omap platforms. The offsets are removed as well
since it is U-Boot's coding style to use structures for mapping such kind of
data (in the sense that it is similar to registers). It is correct to assume
that romcode structure encoding is the same as U-Boot, given the description
of these structures in the TRMs.
The original address provided by the bootrom is passed to the U-Boot binary
instead of a duplicate of the structure stored in global data. This allows to
have only the relevant (boot device and mode) information stored in global data.
It is also expected that the address where the bootrom stores that information
is not overridden by the U-Boot SPL or U-Boot.
The save_omap_boot_params is expected to handle all special cases where the data
provided by the bootrom cannot be used as-is, so that spl_boot_device and
spl_boot_mode only return the data from global data.
Signed-off-by: Paul Kocialkowski
---
arch/arm/cpu/armv7/omap-common/Makefile| 2 -
arch/arm/cpu/armv7/omap-common/boot-common.c | 118 ++---
arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 2 -
arch/arm/cpu/armv7/omap3/board.c | 56
arch/arm/cpu/armv7/omap3/lowlevel_init.S | 10 ---
arch/arm/include/asm/arch-am33xx/omap.h| 11 +++
arch/arm/include/asm/arch-omap3/omap.h | 13 +++
arch/arm/include/asm/arch-omap3/sys_proto.h| 2 +
arch/arm/include/asm/arch-omap4/omap.h | 11 +++
arch/arm/include/asm/arch-omap5/omap.h | 12 +++
arch/arm/include/asm/global_data.h | 10 +--
arch/arm/include/asm/omap_boot.h | 34 ---
arch/arm/include/asm/omap_common.h | 9 ++
arch/arm/include/asm/ti-common/sys_proto.h | 2 +-
14 files changed, 130 insertions(+), 162 deletions(-)
delete mode 100644 arch/arm/include/asm/omap_boot.h
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile
b/arch/arm/cpu/armv7/omap-common/Makefile
index f3725b2..464a5d1 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -26,9 +26,7 @@ ifeq ($(CONFIG_SYS_DCACHE_OFF),)
obj-y += omap-cache.o
endif
-ifeq ($(CONFIG_OMAP34XX),)
obj-y += boot-common.o
-endif
obj-y += lowlevel_init.o
obj-y += mem-common.o
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c
b/arch/arm/cpu/armv7/omap-common/boot-common.c
index bbc6bed..3bd3f49 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -17,25 +17,26 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
void save_omap_boot_params(void)
{
- u32 rom_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
- u8 boot_device;
- u32 dev_desc, dev_data;
+ u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
+ struct omap_boot_parameters *omap_boot_params;
+ u32 boot_device;
+ u32 boot_mode;
- if ((rom_params < NON_SECURE_SRAM_START) ||
- (rom_params > NON_SECURE_SRAM_END))
+ if ((boot_params < NON_SECURE_SRAM_START) ||
+ (boot_params > NON_SECURE_SRAM_END))
return;
- /*
-* rom_params can be type casted to omap_boot_parameters and
-* used. But it not correct to assume that romcode structure
-* encoding would be same as u-boot. So use the defined offsets.
-*/
- boot_device = *((u8 *)(rom_params + BOOT_DEVICE_OFFSET));
+ omap_boot_params = (struct omap_boot_parameters *)boot_params;
+
+ /* Boot device */
+
+ boot_device = omap_boot_params->boot_device;
#if defined(BOOT_DEVICE_NAND_I2C)
/*
@@ -47,29 +48,6 @@ void save_omap_boot_params(void)
if (boot_device == BOOT_DEVICE_NAND_I2C)
boot_device = BOOT_DEVICE_NAND;
#endif
- gd->arch.omap_boot_params.omap_bootdevice = boot_device;
-
- gd->arch.omap_boot_params.ch_flags =
- *((u8 *)(rom_params + CH_FLAGS_OFFSET));
-
- if ((boot_device >= MMC_BOOT_DEVICES_START) &&
- (boot_device <= MMC_BOOT_DEVICES_END)) {
-#if !defined(CONFIG_AM33XX) && !defined(CONFIG_TI81XX) && \
- !defined(CONFIG_AM43XX)
- if ((omap_hw_init_context() ==
- OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)) {
- gd->arch.omap_boot_params.omap_bootmode =
- *((u8 *)(rom_params + BOOT_MODE_OFFSET));
- } else
-#endif
- {
- dev_desc = *((u32 *)(rom_params + DEV_DESC_PTR_OFFSET));
- dev_data = *((u32 *)(dev_desc + DEV_DATA_PTR_OFFSET));
- gd->arch.omap_boot_params.omap_bootmode =
-
[U-Boot] [PATCH] spl: spl_mmc: Minor cosmetics
This switches some printf calls to puts and avoids a test repetition.
Signed-off-by: Paul Kocialkowski
---
common/spl/spl_mmc.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index de495c0..f5ac844 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -43,13 +43,12 @@ static int mmc_load_image_raw_sector(struct mmc *mmc,
unsigned long sector)
(void *) spl_image.load_addr);
end:
+ if (count == 0) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
- if (count == 0)
- printf("spl: mmc block read error\n");
+ puts("spl: mmc block read error\n");
#endif
-
- if (count == 0)
return -1;
+ }
return 0;
}
@@ -63,7 +62,7 @@ static int mmc_load_image_raw_partition(struct mmc *mmc, int
partition)
err = get_partition_info(&mmc->block_dev, partition, &info);
if (err) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
- printf("spl: partition error\n");
+ puts("spl: partition error\n");
#endif
return -1;
}
@@ -83,7 +82,7 @@ static int mmc_load_image_raw_os(struct mmc *mmc)
(void *) CONFIG_SYS_SPL_ARGS_ADDR);
if (count == 0) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
- printf("spl: mmc block read error\n");
+ puts("spl: mmc block read error\n");
#endif
return -1;
}
--
1.9.1
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[U-Boot] [PATCH v3] x86: baytrail: pci region 3 is not always mapped to end of ram
From: Andrew Bradford Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFF and additional SDRAM is mapped from 0x1 and up. There is a physical memory hole from 0x8000 to 0x for other uses. Because of this, PCI region 3 should only try to use up to the amount of SDRAM or 0x8000, which ever is less. Signed-off-by: Andrew Bradford --- v3: Fix build breakage due to semicolon v2: limit maximum size to lesser of SDRAM or 0x8000 --- arch/x86/cpu/baytrail/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/cpu/baytrail/pci.c b/arch/x86/cpu/baytrail/pci.c index 6c291f9..48409de 100644 --- a/arch/x86/cpu/baytrail/pci.c +++ b/arch/x86/cpu/baytrail/pci.c @@ -39,7 +39,7 @@ void board_pci_setup_hose(struct pci_controller *hose) pci_set_region(hose->regions + 3, 0, 0, - gd->ram_size, + gd->ram_size < 0x8000 ? gd->ram_size : 0x8000, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose->region_count = 4; -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] x86: baytrail: pci region 3 is not always mapped to end of ram
On 06/03 12:18, and...@bradfordembedded.com wrote: > From: Andrew Bradford > > Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFF > and additional SDRAM is mapped from 0x1 and up. There is a > physical memory hole from 0x8000 to 0x for other uses. > Because of this, PCI region 3 should only try to use up to the amount of > SDRAM or 0x8000, which ever is less. > > Signed-off-by: Andrew Bradford > --- > v2: limit maximum size to lesser of SDRAM or 0x8000 > --- > arch/x86/cpu/baytrail/pci.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/x86/cpu/baytrail/pci.c b/arch/x86/cpu/baytrail/pci.c > index 6c291f9..53475e8 100644 > --- a/arch/x86/cpu/baytrail/pci.c > +++ b/arch/x86/cpu/baytrail/pci.c > @@ -39,7 +39,7 @@ void board_pci_setup_hose(struct pci_controller *hose) > pci_set_region(hose->regions + 3, > 0, > 0, > -gd->ram_size, > +gd->ram_size < 0x8000 ? gd->ram_size : 0x8000;, > PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); > > hose->region_count = 4; I'm very sorry, please disregard this! It does not actually build. I will fix and send a v3. Thanks, Andrew ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] x86: baytrail: pci region 3 is not always mapped to end of ram
From: Andrew Bradford Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFF and additional SDRAM is mapped from 0x1 and up. There is a physical memory hole from 0x8000 to 0x for other uses. Because of this, PCI region 3 should only try to use up to the amount of SDRAM or 0x8000, which ever is less. Signed-off-by: Andrew Bradford --- v2: limit maximum size to lesser of SDRAM or 0x8000 --- arch/x86/cpu/baytrail/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/cpu/baytrail/pci.c b/arch/x86/cpu/baytrail/pci.c index 6c291f9..53475e8 100644 --- a/arch/x86/cpu/baytrail/pci.c +++ b/arch/x86/cpu/baytrail/pci.c @@ -39,7 +39,7 @@ void board_pci_setup_hose(struct pci_controller *hose) pci_set_region(hose->regions + 3, 0, 0, - gd->ram_size, + gd->ram_size < 0x8000 ? gd->ram_size : 0x8000;, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose->region_count = 4; -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 2/3] net: fec_mxc: query mac address from environment
On Wed, Jun 03, 2015 at 09:05:23AM -0500, Joe Hershberger wrote:
> Hi Damien,
>
> On Tue, Jun 2, 2015 at 3:22 PM, Damien Riegel
> wrote:
> > The TS-4800 doesn't have its MAC address fused, therefore the
> > fec_mxc driver can not currently fetch it.
> >
> > This commit adds the capability to fetch the MAC address from
> > environment if not found in fuses.
> >
> > Signed-off-by: Damien Riegel
> > Cc: Stefano Babic
> > Cc: Joe Hershberger
> > ---
> > drivers/net/fec_mxc.c | 4
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
> > index 9225d37..a789ecc 100644
> > --- a/drivers/net/fec_mxc.c
> > +++ b/drivers/net/fec_mxc.c
> > @@ -1040,6 +1040,10 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t
> > base_addr,
> > if (!getenv("ethaddr"))
> > eth_setenv_enetaddr("ethaddr", ethaddr);
> > }
> > + else if (eth_getenv_enetaddr("ethaddr", ethaddr)) {
> > + debug("got MAC%d address from env: %pM\n", dev_id, ethaddr);
> > + memcpy(edev->enetaddr, ethaddr, 6);
> > + }
>
> This is not the appropriate way to handle this.
>
> The network stack should already be setting this for you. Line 696 in
> net/eth.c
>
> Is this attempting to fix a problem that you've observed?
I did my tests with Buildroot and the U-Boot version I used at that time
required this change. When rebasing and testing on master, I haven't
thought about checking if this patch was still useful.
But now, indeed, the network stack takes care of that for me, this
patch can be dropped.
--
Damien
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Re: [U-Boot] [PATCH 01/22][v2] armv8/ls2085ardb: Add eth & phy f/w loading support
On 05/28/2015 02:23 AM, Prabhakar Kushwaha wrote: > Add support for board eth initialization and support for loading phy > firmware. PHY firmware needs to be loaded from board_eth_init() because > all the MACs are not initialized by ldpaa_eth driver. > > Signed-off-by: pankaj chauhan > Signed-off-by: Prabhakar Kushwaha > --- > Changes for v2: Sending as it is for patch set > This set (v2) with [21/22 v3] is applied to fsl-qoriq next branch. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: phytec: pcm051: select board revision by Kconfig
On Wed, Jun 03, 2015 at 04:36:06PM +0200, Lars Poeschel wrote: > On Tue, Jun 02, 2015 at 10:34:34AM -0400, Tom Rini wrote: > > On Mon, Jun 01, 2015 at 05:09:11PM +0200, poesc...@lemonage.de wrote: > > > > > From: Lars Poeschel > > > > > > This add a Kconfig entry that allows to set the board revision in > > > menuconfig. So the deprecated CONFIG_SYS_EXTRA_OPTIONS is no longer > > > needed for this boad. > > > > > > Signed-off-by: Lars Poeschel > > > > I like the concept but CONFIG_REVx is way too generic. Can we maybe > > re-work things as CONFIG_TARGET_PCM051_REV1 / CONFIG_TARGET_PCM051_REV3 > > (and those select CONFIG_TARGET_PCM051) ? Masahiro? Thanks! > > Agree: CONFIG_REVx is too generic. I will send a version 2 of the patch, > but I don't understand why you want CONFIG_TARGET_PCM051_REV1 / > CONFIG_TARGET_PCM051_REV3 to select CONFIG_TARGET_PCM051. The > CONFIG_TARGET_PCM051_REVx's are inside an > > if TARGET_PCM051 > ... > endif > > That means, that CONFIG_TARGET_PCM051 must already be selected to make > the *_REVx's visible and selectable. Right. I mean since we must select one of these boards at build-time, why not just ask about them up-front in arch/arm/Kconfig as rev1/rev3, and then have the main symbol be a hidden one, ie roughly: config TARGET_PCM051 bool config TARGET_PCM051_REV1 bool "Enable pcm051 rev1" select TARGET_PCM051 help ... config TARGET_PCM051_REV3 bool "Enable pcm051 rev3" select TARGET_PCM051 help ... -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] Merrii_A80_Optimus: Fix build error
make Merrii_A80_Optimus_defconfig make fails with the following error: board/sunxi/built-in.o: In function `misc_init_r': /root/u-boot/board/sunxi/board.c:540: undefined reference to `eth_setenv_enetaddr' Enable CONFIG_CMD_NET in Merrii_A80_Optimus_defconfig to fix it. Signed-off-by: Maxin B. John --- configs/Merrii_A80_Optimus_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig index 6bd5273..b112596 100644 --- a/configs/Merrii_A80_Optimus_defconfig +++ b/configs/Merrii_A80_Optimus_defconfig @@ -9,3 +9,4 @@ CONFIG_MACH_SUN9I=y CONFIG_DRAM_CLK=360 CONFIG_DRAM_ZQ=123 CONFIG_SYS_CLK_FREQ=100800 +CONFIG_CMD_NET=y -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/6] armv8/cache: Fix page table creation
Hello Albert, On Thu, 16 Apr 2015 13:24:50 +0200, Albert ARIBAUD wrote: > Hello Thierry, > > I assume there will be a v2 series? > > (asking so that I can mark the series "Changes Requested") Ping. Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH] arm: Enable CONFIG_USE_ARCH_MEMSET/MEMCPY globally
Hello Tom, On Wed, 22 Apr 2015 09:49:55 -0400, Tom Rini wrote: > On Thu, Apr 16, 2015 at 09:30:14AM +0200, Albert ARIBAUD wrote: > > Hello Tom, > > > > On Tue, 3 Feb 2015 15:21:53 -0500, Tom Rini wrote: > > > - Move the obj- lines for memset.S/memcpy.S to outside of an SPL check > > > so that SPL can use them as well. > > > - Make sure memset() / memcpy() end up in a text.fn section for garbage > > > collection in SPL. > > > - Update examples/api/Makefile to get memset() again on ARM. > > > - Drop Y-MODEM SPL from am335x_evm and USB SPL so that it fits within > > > size constraints again. > > > - Always set CONFIG_USE_ARCH_MEMSET/MEMCPY on ARM && !ARM64 > > > > > > Cc: Albert Aribaud > > > Signed-off-by: Tom Rini > > > > Really small nitpick: the comment before the YMODEM undef is not that > > informative, and possibly unneeded if all space-saving undefs can be > > grouped under a single global comment. > > > > If there are no comments apart from mine, maybe we don't need this to > > be reposted as non-RFC, and I can directly apply it? > > Yes, if you'd be so kind as to re-word the commit message (and note that > I applied the fix for am335x_evm_usbspl build size already for other > reasons) that would be great! > > -- > Tom Applied to u-boot-arm/master, thanks! Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH] ARMv8: replace CONFIG_ARM64 with builtin __aarch64__
On Tue, 14 Apr 2015 10:34:46 +0200, Albert ARIBAUD wrote: > Hello feng...@phytium.com.cn, > > On Tue, 3 Feb 2015 16:10:25 +0800, feng...@phytium.com.cn > wrote: > > From: David Feng > > > > This patch replace CONFIG_ARM64 with gcc builtin __aarch64__. > > CONFIG_ARM64 is still needed in makefile and config.mk. > > Maybe them could be replace with something like *_V8 later. > > If CONFIG_ARM64 is still needed, then it will remain available, so > there is no /need/ to replace it in source code. There may be > an /interest/ in replacing it though, but it is not stated here. What > would this be? I don't think I got an answer to my question so far. Did I miss it? Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] x86: WIP: Enable debug UART for Minnowmax
Enable the debug UART and emit a single 'a' early in the init sequence to
show that it is working.
Unfortunately the debug UART implementation needs a stack to work. I cannot
seem to remove this limitation as the absolute 'jmp %eax' instruction goes
off into the weeds.
So this means that the character output cannot be any earlier than
car_init_ret, where memory is available for a stack.
Signed-off-by: Simon Glass
---
arch/x86/cpu/start.S| 4
configs/minnowmax_defconfig | 4
include/debug_uart.h| 20 ++--
3 files changed, 18 insertions(+), 10 deletions(-)
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index 2e5f9da..c6965b2 100644
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -109,6 +109,10 @@ car_init_ret:
andl$0xfff0, %esp
post_code(POST_START_STACK)
+ calldebug_uart_init
+ mov $'a', %eax
+ callprintch
+
/* Zero the global data since it won't happen later */
xorl%eax, %eax
movl$GENERATED_GBL_DATA_SIZE, %ecx
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index 744aca3..14e21fa 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -12,3 +12,7 @@ CONFIG_CMD_CPU=y
CONFIG_CMD_NET=y
CONFIG_OF_CONTROL=y
CONFIG_CPU=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_NS16550=y
+CONFIG_DEBUG_UART_BASE=0x3f8
+CONFIG_DEBUG_UART_CLOCK=1843200
diff --git a/include/debug_uart.h b/include/debug_uart.h
index f56797b..0acc91c 100644
--- a/include/debug_uart.h
+++ b/include/debug_uart.h
@@ -64,46 +64,46 @@ void debug_uart_init(void);
*
* @ch:Character to output
*/
-asmlinkage void printch(int ch);
+void printch(int ch);
/**
* printascii() - Output an ASCII string to the debug UART
*
* @str: String to output
*/
-asmlinkage void printascii(const char *str);
+void printascii(const char *str);
/**
* printhex2() - Output a 2-digit hex value
*
* @value: Value to output
*/
-asmlinkage void printhex2(uint value);
+void printhex2(uint value);
/**
* printhex4() - Output a 4-digit hex value
*
* @value: Value to output
*/
-asmlinkage void printhex4(uint value);
+void printhex4(uint value);
/**
* printhex8() - Output a 8-digit hex value
*
* @value: Value to output
*/
-asmlinkage void printhex8(uint value);
+void printhex8(uint value);
/*
* Now define some functions - this should be inserted into the serial driver
*/
#define DEBUG_UART_FUNCS \
- asmlinkage void printch(int ch) \
+ void printch(int ch) \
{ \
_debug_uart_putc(ch); \
} \
\
- asmlinkage void printascii(const char *str) \
+ void printascii(const char *str) \
{ \
while (*str) \
_debug_uart_putc(*str++); \
@@ -121,17 +121,17 @@ asmlinkage void printhex8(uint value);
printhex1(value >> (4 * digits)); \
} \
\
- asmlinkage void printhex2(uint value) \
+ void printhex2(uint value) \
{ \
printhex(value, 2); \
} \
\
- asmlinkage void printhex4(uint value) \
+ void printhex4(uint value) \
{ \
printhex(value, 4); \
} \
\
- asmlinkage void printhex8(uint value) \
+ void printhex8(uint value) \
{ \
printhex(value, 8); \
}
--
2.2.0.rc0.207.ga3a616c
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Re: [U-Boot] Building u-boot.rom for Minnowboard
Hi Saket, On 2 June 2015 at 11:02, Saket Sinha wrote: > Hi Simon, > >> >> Also do you know which MinnowMAX board you have? I think there are two >> versions. > > The pcb does not speak of any particular versions. > > I found there are two hardware revisions - > http://www.elinux.org/Minnowboard:Hardware_Revisions#MinnowMax > > But I would not be able to tell my minnowmax belongs to which revision > without the Multimeter and other stuff which currently I am not > possessing. > > Moreover, the changes are not of the nature to have stopped the u-boot > from booting. > >> >> I might be able to create an image that prints out post_code() calls. >> > > That would be a real help. > >> Will wait to hear from John. >> > > Same here. I added a debug UART image here: https://drive.google.com/folderview?id=0B7WYZbZ9zd-3flBfMEk3WHRSclJDWHFxOWlQTlBEUHg3aGM0aUZhLTdMYWVGbm9HNXNYTlU&usp=sharing I'll send the patch to the mailing list soon so you can build it. It should output an 'a' character after setting up the FSP. Are you able to progress by using qemu in the meantime? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: phytec: pcm051: select board revision by Kconfig
On Tue, Jun 02, 2015 at 10:34:34AM -0400, Tom Rini wrote: > On Mon, Jun 01, 2015 at 05:09:11PM +0200, poesc...@lemonage.de wrote: > > > From: Lars Poeschel > > > > This add a Kconfig entry that allows to set the board revision in > > menuconfig. So the deprecated CONFIG_SYS_EXTRA_OPTIONS is no longer > > needed for this boad. > > > > Signed-off-by: Lars Poeschel > > I like the concept but CONFIG_REVx is way too generic. Can we maybe > re-work things as CONFIG_TARGET_PCM051_REV1 / CONFIG_TARGET_PCM051_REV3 > (and those select CONFIG_TARGET_PCM051) ? Masahiro? Thanks! Agree: CONFIG_REVx is too generic. I will send a version 2 of the patch, but I don't understand why you want CONFIG_TARGET_PCM051_REV1 / CONFIG_TARGET_PCM051_REV3 to select CONFIG_TARGET_PCM051. The CONFIG_TARGET_PCM051_REVx's are inside an if TARGET_PCM051 ... endif That means, that CONFIG_TARGET_PCM051 must already be selected to make the *_REVx's visible and selectable. > > --- > > board/phytec/pcm051/Kconfig | 19 +++ > > configs/pcm051_rev1_defconfig | 2 +- > > configs/pcm051_rev3_defconfig | 2 +- > > 3 files changed, 21 insertions(+), 2 deletions(-) > > > > diff --git a/board/phytec/pcm051/Kconfig b/board/phytec/pcm051/Kconfig > > index 2cc0d88..c1071c6 100644 > > --- a/board/phytec/pcm051/Kconfig > > +++ b/board/phytec/pcm051/Kconfig > > @@ -12,4 +12,23 @@ config SYS_SOC > > config SYS_CONFIG_NAME > > default "pcm051" > > > > +choice > > +prompt "pcm051 revision select" > > +default REV3 > > + > > +config REV1 > > + bool "pcm051 revision 1 or 2" > > + help > > + If you have 1358.1 written on the pcb of your pcm051, you > > + have a revision 1 board. Likewise if you have 1358.2 on your > > + board, it is a revision 2 board and this entry is for you. > > + > > +config REV3 > > + bool "pcm051 revision 3" > > + help > > + If you have 1358.3 written on the pcb of your pcm051, you > > + have a revision 3 board and you have to select this entry. > > + > > +endchoice > > + > > endif > > diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig > > index af02b2f..0a28195 100644 > > --- a/configs/pcm051_rev1_defconfig > > +++ b/configs/pcm051_rev1_defconfig > > @@ -1,4 +1,4 @@ > > CONFIG_ARM=y > > CONFIG_TARGET_PCM051=y > > CONFIG_SPL=y > > -CONFIG_SYS_EXTRA_OPTIONS="REV1" > > +CONFIG_REV1=y > > diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig > > index 2a907d7..4ad49df 100644 > > --- a/configs/pcm051_rev3_defconfig > > +++ b/configs/pcm051_rev3_defconfig > > @@ -1,4 +1,4 @@ > > CONFIG_ARM=y > > CONFIG_TARGET_PCM051=y > > CONFIG_SPL=y > > -CONFIG_SYS_EXTRA_OPTIONS="REV3" > > +CONFIG_REV3=y > > -- > > 2.1.4 > > > > ___ > > U-Boot mailing list > > U-Boot@lists.denx.de > > http://lists.denx.de/mailman/listinfo/u-boot > > -- > Tom Regards, Lars ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/7] ARM: DRA7: Update DDR IO configuration
On Wed, Jun 03, 2015 at 02:43:26PM +0530, Lokesh Vutla wrote: > DDRIO_2 and LPDDR2CH1_1 registers are not present > for DRA7. So not configuring these registers for DRA7xx > > Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 7/7] ARM: DRA7: Update DDR IO registers
On Wed, Jun 03, 2015 at 02:43:27PM +0530, Lokesh Vutla wrote: > Update DDR IO register values. > > Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/7] ARM: DRA7: Add is_dra72x cpu check definition
On Wed, Jun 03, 2015 at 02:43:25PM +0530, Lokesh Vutla wrote: > A generic is_dra72x cpu check is useful for grouping > all the revisions under that. This is used in the > subsequent patches. > > Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/7] ARM: DRA72-evm: Enable HW leveling
On Wed, Jun 03, 2015 at 02:43:24PM +0530, Lokesh Vutla wrote: > Updating EMIF registers to enable HW leveling > on DRA72-evm. > Also updating the timing registers. > > Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/7] ARM: DRA7-evm: Enable HW leveling
On Wed, Jun 03, 2015 at 02:43:23PM +0530, Lokesh Vutla wrote: > Updating EMIF registers to enable HW leveling > on DRA7-evm. > > Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/7] ARM: BeagleBoard-X15: Enable HW leveling
On Wed, Jun 03, 2015 at 02:43:22PM +0530, Lokesh Vutla wrote: > Updating EMIF registers to enable HW leveling > on BeagleBoard-X15. > > Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/7] ARM: DRA7: DDR3: Add support for HW leveling
On Wed, Jun 03, 2015 at 02:43:21PM +0530, Lokesh Vutla wrote: > DRA7 EMIF supports Full leveling for DDR3. > Adding support for the Full leveling sequence. > > Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/7] ARM: DRA7: DDR3: Enable hw leveling
On Wed, Jun 03, 2015 at 02:43:20PM +0530, Lokesh Vutla wrote: > This series updates the DDR3 init sequence and adds support for > hw leveling for all DRA7 platforms. > > Tested memtest and reboot on DRA7-evm , DRA72-evm, BeagleBoard-x15 boards. For sanity sake, tested on omap5_uevm (but indeed, the code didn't change just a few related calling paths for that family). -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/8] usb:xhci:omap: Remove common dwc3 drv functions calls
On Fri, May 29, 2015 at 02:47:17PM +0530, Ramneek Mehresh wrote: > Remove all redundant dwc3 driver function calls that > are defined by dwc3 driver > > Signed-off-by: Ramneek Mehresh On an am43xx-gp-evm: Tested-by: Tom Rini Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/8] usb:xhci:keystone: Remove common dwc3 drv functions calls
On Fri, May 29, 2015 at 02:47:18PM +0530, Ramneek Mehresh wrote: > Remove all redundant dwc3 driver function calls that > are defined by dwc3 driver > > Signed-off-by: Ramneek Mehresh Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/8] arch:arm:fsl: Add XHCI support for LS1021A
On Fri, May 29, 2015 at 02:47:20PM +0530, Ramneek Mehresh wrote: > From: ramneek mehresh > > Add base register address information for USB > XHCI controller on LS1021A > > Signed-off-by: Ramneek Mehresh Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 7/8] include:configs:ls1021atwr: Enable USB IP support
On Fri, May 29, 2015 at 02:47:21PM +0530, Ramneek Mehresh wrote: > From: ramneek mehresh > > Enable USB IP support for both EHCI and XHCI for > ls1021atwr platform > > Signed-off-by: Ramneek Mehresh Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/8] drivers:usb:fsl: Add XHCI driver support
On Fri, May 29, 2015 at 02:47:19PM +0530, Ramneek Mehresh wrote: > From: ramneek mehresh > > Add xhci driver support for all FSL socs > > Signed-off-by: Ramneek Mehresh Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 8/8] include:configs:ls1021aqds: Enable USB IP support
On Fri, May 29, 2015 at 02:47:22PM +0530, Ramneek Mehresh wrote: > From: ramneek mehresh > > Enable USB IP support for both EHCI and XHCI for > ls1021aqds platform > > Signed-off-by: Ramneek Mehresh Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] sunxi: Add new Mele_A1000G_quad defconfig
Hi, On 03-06-15 14:52, Tom Rini wrote: On Wed, Jun 03, 2015 at 08:49:04AM +0100, Ian Campbell wrote: On Tue, 2015-06-02 at 09:07 +0200, Hans de Goede wrote: So if there is no way to store this info in the defconfigs lets just leave it out and will point people to the wiki. Would it be totally mad to have a string CONFIG_BOARD_URL containing a URL (e.g. to the relevant wiki page) which was printed on boot i.e. in a "Board Info: http://"; type thing and/or in the help output? This started off as a thought on abusing Kconfig to somehow allow some of this info to remain, but just that would be a step too far IMHO, but if it also serves a (somewhat) practical purpose, then, maybe? (I'm not convinced myself, but thought I'd mention it). Ah, MAINTAINERS can help here. Checking out the kernel's copy: Descriptions of section entries: P: Person (obsolete) M: Mail patches to: FullName L: Mailing list that is relevant to this area W: Web-page with status/info ... Ah yes the W: option in MAINTAINERS is indeed the best place to stick URL-s, thanks for your input. Regards, Hans ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/8] usb:xhci:exynos: Remove common dwc3 drv functions calls
On Fri, May 29, 2015 at 02:47:16PM +0530, Ramneek Mehresh wrote: > Remove all redundant dwc3 driver function calls that > are defined by dwc3 driver > > Signed-off-by: Ramneek Mehresh Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] board/BuR/common: fix netconsole
On Thu, May 28, 2015 at 04:41:54PM +0200, Hannes Schmelzer wrote: > netconsole had become defective over time and cleanups. > Because the feature is used very rarely nobody did take notice about this > defect. > > With this patch the resulting syntax error on call will be fixed. > > Signed-off-by: Hannes Schmelzer > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/8] drivers:usb:dwc3: Add DWC3 controller driver support
On Fri, May 29, 2015 at 02:47:15PM +0530, Ramneek Mehresh wrote: > Add support for DWC3 XHCI controller driver > > Signed-off-by: Ramneek Mehresh Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 2/3] net: fec_mxc: query mac address from environment
Hi Damien,
On Tue, Jun 2, 2015 at 3:22 PM, Damien Riegel
wrote:
> The TS-4800 doesn't have its MAC address fused, therefore the
> fec_mxc driver can not currently fetch it.
>
> This commit adds the capability to fetch the MAC address from
> environment if not found in fuses.
>
> Signed-off-by: Damien Riegel
> Cc: Stefano Babic
> Cc: Joe Hershberger
> ---
> drivers/net/fec_mxc.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
> index 9225d37..a789ecc 100644
> --- a/drivers/net/fec_mxc.c
> +++ b/drivers/net/fec_mxc.c
> @@ -1040,6 +1040,10 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t
> base_addr,
> if (!getenv("ethaddr"))
> eth_setenv_enetaddr("ethaddr", ethaddr);
> }
> + else if (eth_getenv_enetaddr("ethaddr", ethaddr)) {
> + debug("got MAC%d address from env: %pM\n", dev_id, ethaddr);
> + memcpy(edev->enetaddr, ethaddr, 6);
> + }
This is not the appropriate way to handle this.
The network stack should already be setting this for you. Line 696 in net/eth.c
Is this attempting to fix a problem that you've observed?
Thanks,
-Joe
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Re: [U-Boot] [PATCH] x86: qemu: Add CMD_NET to qemu-x86_defconfig
Hi Simon, On Wed, Jun 3, 2015 at 2:38 AM, Simon Glass wrote: > Hi Bin, > > On 2 June 2015 at 08:41, Bin Meng wrote: >> Hi Simon, >> >> On Tue, Jun 2, 2015 at 6:44 PM, Bin Meng wrote: >>> Hi Simon, >>> >>> On Tue, Jun 2, 2015 at 6:40 PM, Bin Meng wrote: The following error is observed on QEMU x86. => print ipaddr ipaddr=192.168.178.66 => ping 192.168.178.1 *** ERROR: `ipaddr' not set ping failed; host 192.168.178.1 is not alive The issue was introduced in commit fd30563. Adding CMD_NET to defconfig resolves this. Also reorder the config options to match the order in Kconfig. Signed-off-by: Bin Meng --- configs/qemu-x86_defconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index a5251b5..07b5176 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -1,9 +1,9 @@ CONFIG_X86=y CONFIG_VENDOR_EMULATION=y CONFIG_TARGET_QEMU_X86=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_CMD_NET=y CONFIG_OF_CONTROL=y -CONFIG_OF_SEPARATE=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_111=y -CONFIG_GENERATE_PIRQ_TABLE=y -- >>> >>> After Joe's pull request [1] get applied by Tom, you can rebase >>> u-boot-x86/testing branch and apply this one to fix the qemu >>> networking issue. Thanks! >>> >>> [1] http://patchwork.ozlabs.org/patch/479136/ >>> >> >> I see Joe's pull request has been applied, but sorry I've noticed that >> this patch has some dependencies on the qemu v2 patch series I am >> working on. Please ignore this and I will resend it as part of my qemu >> v2 patch series soon. Sorry about that. > > OK I have it setting in x86/testing. Please let me know what commits > need changing, etc. > Please check this v2 series: http://patchwork.ozlabs.org/patch/479745/ It is rebased on u-boot-x86/master. Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 2/2] x86: fsp: Move FspInitEntry call to board_init_f()
On 06/03 07:17, Bin Meng wrote: > Hi Andrew, > > On Wed, Jun 3, 2015 at 4:05 AM, Andrew Bradford > wrote: > > Hi Bin, > > > > On 06/01 20:31, Bin Meng wrote: > >> The call to FspInitEntry is done in arch/x86/lib/fsp/fsp_car.S so far. > >> It worked pretty well but looks not that good. Apart from doing too > >> much work than just enabling CAR, it cannot read the configuration > >> data from device tree at that time. Now we want to move it a little > >> bit later as part of init_sequence_f[] being called by board_init_f(). > >> This way it looks and works better in the U-Boot initialization path. > >> > >> Due to FSP's design, after calling FspInitEntry it will not return to > >> its caller, instead it jumps to a continuation function which is given > >> by bootloader with a new stack in system memory. The original stack in > >> the CAR is gone, but its content is perserved by FSP and described by > >> a bootloader temporary memory HOB. Technically we can recover anything > >> we had before in the previous stack, but that is way too complicated. > >> To make life much easier, in the FSP continuation routine we just > >> simply call fsp_init_done() and jump back to car_init_ret() to redo > >> the whole board_init_f() initialization, but this time with a non-zero > >> HOB list pointer saved in U-Boot's global data so that we can bypass > >> the FspInitEntry for the second time. > >> > >> Signed-off-by: Bin Meng > >> > >> --- > >> > >> arch/x86/cpu/start.S | 6 +- > >> arch/x86/include/asm/u-boot-x86.h | 4 > >> arch/x86/lib/fsp/fsp_car.S| 26 +- > >> arch/x86/lib/fsp/fsp_common.c | 8 > >> common/board_f.c | 3 +++ > >> 5 files changed, 25 insertions(+), 22 deletions(-) > >> > >> diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S > >> index 2e5f9da..00e585e 100644 > >> --- a/arch/x86/cpu/start.S > >> +++ b/arch/x86/cpu/start.S > >> @@ -116,12 +116,16 @@ car_init_ret: > >> rep stosb > >> > >> #ifdef CONFIG_HAVE_FSP > >> + test%esi, %esi > >> + jz skip_hob > >> + > >> /* Store HOB list */ > >> movl%esp, %edx > >> addl$GD_HOB_LIST, %edx > >> movl%esi, (%edx) > >> -#endif > >> > >> +skip_hob: > >> +#endif > >> /* Setup first parameter to setup_gdt, pointer to global_data */ > >> movl%esp, %eax > >> > >> diff --git a/arch/x86/include/asm/u-boot-x86.h > >> b/arch/x86/include/asm/u-boot-x86.h > >> index faa5182..9ee4104 100644 > >> --- a/arch/x86/include/asm/u-boot-x86.h > >> +++ b/arch/x86/include/asm/u-boot-x86.h > >> @@ -54,6 +54,10 @@ u32 isa_map_rom(u32 bus_addr, int size); > >> /* arch/x86/lib/... */ > >> int video_bios_init(void); > >> > >> +#ifdef CONFIG_HAVE_FSP > >> +int x86_fsp_init(void); > >> +#endif > >> + > >> void board_init_f_r_trampoline(ulong) __attribute__ ((noreturn)); > >> void board_init_f_r(void) __attribute__ ((noreturn)); > >> > >> diff --git a/arch/x86/lib/fsp/fsp_car.S b/arch/x86/lib/fsp/fsp_car.S > >> index 5e09568..afbf3f9 100644 > >> --- a/arch/x86/lib/fsp/fsp_car.S > >> +++ b/arch/x86/lib/fsp/fsp_car.S > >> @@ -56,28 +56,10 @@ temp_ram_init_ret: > >> > >> /* stack grows down from top of CAR */ > >> movl%edx, %esp > >> + subl$4, %esp > >> > >> - /* > >> - * TODO: > >> - * > >> - * According to FSP architecture spec, the fsp_init() will not return > >> - * to its caller, instead it requires the bootloader to provide a > >> - * so-called continuation function to pass into the FSP as a > >> parameter > >> - * of fsp_init, and fsp_init() will call that continuation function > >> - * directly. > >> - * > >> - * The call to fsp_init() may need to be moved out of the car_init() > >> - * to cpu_init_f() with the help of some inline assembly codes. > >> - * Note there is another issue that fsp_init() will setup another > >> stack > >> - * using the fsp_init parameter stack_top after DRAM is initialized, > >> - * which means any data on the previous stack (on the CAR) gets lost > >> - * (ie: U-Boot global_data). FSP is supposed to support such > >> scenario, > >> - * however it does not work. This should be revisited in the future. > >> - */ > >> - movl$CONFIG_FSP_TEMP_RAM_ADDR, %eax > >> - xorl%edx, %edx > >> - xorl%ecx, %ecx > >> - callfsp_init > >> + xor %esi, %esi > >> + jmp car_init_done > >> > >> .global fsp_init_done > >> fsp_init_done: > >> @@ -86,6 +68,8 @@ fsp_init_done: > >>* Save eax to esi temporarily. > >>*/ > >> movl%eax, %esi > >> + > >> +car_init_done: > >> /* > >>* Re-initialize the ebp (BIST) to zero, as we already reach here > >>* which means we passed BIST testing before. > >> diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c > >> index 001494d..5b25632 100644 > >>
Re: [U-Boot] [PATCH] sunxi: Add new Mele_A1000G_quad defconfig
On Wed, Jun 03, 2015 at 08:49:04AM +0100, Ian Campbell wrote: > On Tue, 2015-06-02 at 09:07 +0200, Hans de Goede wrote: > > So if there is no way to store this info in the defconfigs lets > > just leave it out and will point people to the wiki. > > Would it be totally mad to have a string CONFIG_BOARD_URL containing a > URL (e.g. to the relevant wiki page) which was printed on boot i.e. in a > "Board Info: http://"; type thing and/or in the help output? > > This started off as a thought on abusing Kconfig to somehow allow some > of this info to remain, but just that would be a step too far IMHO, but > if it also serves a (somewhat) practical purpose, then, maybe? > > (I'm not convinced myself, but thought I'd mention it). Ah, MAINTAINERS can help here. Checking out the kernel's copy: Descriptions of section entries: P: Person (obsolete) M: Mail patches to: FullName L: Mailing list that is relevant to this area W: Web-page with status/info ... -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] ARM: DRA7xx: EMIF: Fix DLL_CALIB_CTRL register
When DLL_CALIB_INTERVAL is set, an extra delay is added
which is not required and it consumes EMIF bandwidth.
So making the DLL_CALIB_CTRL[8:0]DLL_CALIB_INTERVAL bits to 0.
Signed-off-by: Lokesh Vutla
---
arch/arm/cpu/armv7/omap5/sdram.c | 4 ++--
board/ti/beagle_x15/board.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 3022b9e..cf4452d 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -146,7 +146,7 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1
= {
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
- .read_idle_ctrl = 0x00050001,
+ .read_idle_ctrl = 0x0005,
.zq_config = 0x0007190B,
.temp_alert_config = 0x,
.emif_ddr_phy_ctlr_1_init = 0x0024400B,
@@ -171,7 +171,7 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1
= {
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
- .read_idle_ctrl = 0x00050001,
+ .read_idle_ctrl = 0x0005,
.zq_config = 0x0007190B,
.temp_alert_config = 0x,
.emif_ddr_phy_ctlr_1_init = 0x0024400B,
diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c
index 76654c8..f2ad13d 100644
--- a/board/ti/beagle_x15/board.c
+++ b/board/ti/beagle_x15/board.c
@@ -52,7 +52,7 @@ static const struct emif_regs
beagle_x15_emif1_ddr3_532mhz_emif_regs = {
.sdram_tim1 = 0xceef266b,
.sdram_tim2 = 0x328f7fda,
.sdram_tim3 = 0x027f88a8,
- .read_idle_ctrl = 0x00050001,
+ .read_idle_ctrl = 0x0005,
.zq_config = 0x0007190b,
.temp_alert_config = 0x,
.emif_ddr_phy_ctlr_1_init = 0x0024400b,
@@ -120,7 +120,7 @@ static const struct emif_regs
beagle_x15_emif2_ddr3_532mhz_emif_regs = {
.sdram_tim1 = 0xceef266b,
.sdram_tim2 = 0x328f7fda,
.sdram_tim3 = 0x027f88a8,
- .read_idle_ctrl = 0x00050001,
+ .read_idle_ctrl = 0x0005,
.zq_config = 0x0007190b,
.temp_alert_config = 0x,
.emif_ddr_phy_ctlr_1_init = 0x0024400b,
--
1.9.1
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Re: [U-Boot] [PATCH] ARM: DRA7xx: EMIF: Fix DLL_CALIB_CTRL register
On Wednesday 03 June 2015 04:17 PM, Lokesh Vutla wrote:
> When DLL_CALIB_INTERVAL is set, an extra delay is added
> which is not required and it consumes EMIF bandwidth.
> So making the DLL_CALIB_CTRL[8:0]DLL_CALIB_INTERVAL bits to 0.
I missed updating on emif2 for beagle-x15. Ill send a v2 for this.
Thanks and regards,
Lokesh
>
> Signed-off-by: Lokesh Vutla
> ---
> arch/arm/cpu/armv7/omap5/sdram.c | 4 ++--
> board/ti/beagle_x15/board.c | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/omap5/sdram.c
> b/arch/arm/cpu/armv7/omap5/sdram.c
> index 3022b9e..cf4452d 100644
> --- a/arch/arm/cpu/armv7/omap5/sdram.c
> +++ b/arch/arm/cpu/armv7/omap5/sdram.c
> @@ -146,7 +146,7 @@ const struct emif_regs
> emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
> .sdram_tim1 = 0xCCCF36B3,
> .sdram_tim2 = 0x308F7FDA,
> .sdram_tim3 = 0x027F88A8,
> - .read_idle_ctrl = 0x00050001,
> + .read_idle_ctrl = 0x0005,
> .zq_config = 0x0007190B,
> .temp_alert_config = 0x,
> .emif_ddr_phy_ctlr_1_init = 0x0024400B,
> @@ -171,7 +171,7 @@ const struct emif_regs
> emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
> .sdram_tim1 = 0xCCCF36B3,
> .sdram_tim2 = 0x308F7FDA,
> .sdram_tim3 = 0x027F88A8,
> - .read_idle_ctrl = 0x00050001,
> + .read_idle_ctrl = 0x0005,
> .zq_config = 0x0007190B,
> .temp_alert_config = 0x,
> .emif_ddr_phy_ctlr_1_init = 0x0024400B,
> diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c
> index 124a1d3..ac48607 100644
> --- a/board/ti/beagle_x15/board.c
> +++ b/board/ti/beagle_x15/board.c
> @@ -52,7 +52,7 @@ static const struct emif_regs
> beagle_x15_emif1_ddr3_532mhz_emif_regs = {
> .sdram_tim1 = 0xceef266b,
> .sdram_tim2 = 0x328f7fda,
> .sdram_tim3 = 0x027f88a8,
> - .read_idle_ctrl = 0x00050001,
> + .read_idle_ctrl = 0x0005,
> .zq_config = 0x0007190b,
> .temp_alert_config = 0x,
> .emif_ddr_phy_ctlr_1_init = 0x0024400b,
>
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[U-Boot] [PATCH] ARM: DRA7xx: EMIF: Fix DLL_CALIB_CTRL register
When DLL_CALIB_INTERVAL is set, an extra delay is added
which is not required and it consumes EMIF bandwidth.
So making the DLL_CALIB_CTRL[8:0]DLL_CALIB_INTERVAL bits to 0.
Signed-off-by: Lokesh Vutla
---
arch/arm/cpu/armv7/omap5/sdram.c | 4 ++--
board/ti/beagle_x15/board.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 3022b9e..cf4452d 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -146,7 +146,7 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1
= {
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
- .read_idle_ctrl = 0x00050001,
+ .read_idle_ctrl = 0x0005,
.zq_config = 0x0007190B,
.temp_alert_config = 0x,
.emif_ddr_phy_ctlr_1_init = 0x0024400B,
@@ -171,7 +171,7 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1
= {
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
- .read_idle_ctrl = 0x00050001,
+ .read_idle_ctrl = 0x0005,
.zq_config = 0x0007190B,
.temp_alert_config = 0x,
.emif_ddr_phy_ctlr_1_init = 0x0024400B,
diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c
index 124a1d3..ac48607 100644
--- a/board/ti/beagle_x15/board.c
+++ b/board/ti/beagle_x15/board.c
@@ -52,7 +52,7 @@ static const struct emif_regs
beagle_x15_emif1_ddr3_532mhz_emif_regs = {
.sdram_tim1 = 0xceef266b,
.sdram_tim2 = 0x328f7fda,
.sdram_tim3 = 0x027f88a8,
- .read_idle_ctrl = 0x00050001,
+ .read_idle_ctrl = 0x0005,
.zq_config = 0x0007190b,
.temp_alert_config = 0x,
.emif_ddr_phy_ctlr_1_init = 0x0024400b,
--
1.9.1
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[U-Boot] [PATCH 2/2] ot1200: setup i2c bus 1 in setup_iomux_i2c()
On this bus there is a EEPROM containing EDID and ddr3
calibration information.
Signed-off-by: Christian Gmeiner
---
board/bachmann/ot1200/ot1200.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c
index a33d496..2237b7a 100644
--- a/board/bachmann/ot1200/ot1200.c
+++ b/board/bachmann/ot1200/ot1200.c
@@ -122,6 +122,20 @@ static void setup_iomux_features(void)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C2 - EEPROM */
+static struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
+ .gp = IMX_GPIO_NR(2, 30)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
+ .gp = IMX_GPIO_NR(3, 16)
+ }
+};
+
/* I2C3 - IO expander */
static struct i2c_pads_info i2c_pad_info2 = {
.scl = {
@@ -138,6 +152,7 @@ static struct i2c_pads_info i2c_pad_info2 = {
static void setup_iomux_i2c(void)
{
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
}
--
2.1.0
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[U-Boot] [PATCH 1/2] ot1200: setup i2c bus in board_early_init_f(..)
Make it possible to use the i2c bus in SPL.
Signed-off-by: Christian Gmeiner
---
board/bachmann/ot1200/ot1200.c | 40 ++--
1 file changed, 22 insertions(+), 18 deletions(-)
diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c
index e434ed9..a33d496 100644
--- a/board/bachmann/ot1200/ot1200.c
+++ b/board/bachmann/ot1200/ot1200.c
@@ -120,6 +120,27 @@ static void setup_iomux_features(void)
ARRAY_SIZE(feature_pads));
}
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+/* I2C3 - IO expander */
+static struct i2c_pads_info i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
+ .gp = IMX_GPIO_NR(3, 17)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
+ .gp = IMX_GPIO_NR(3, 18)
+ }
+};
+
+static void setup_iomux_i2c(void)
+{
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+}
+
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -151,6 +172,7 @@ int board_early_init_f(void)
setup_iomux_uart();
setup_iomux_spi();
+ setup_iomux_i2c();
setup_iomux_features();
return 0;
@@ -236,22 +258,6 @@ int board_mmc_init(bd_t *bis)
return 0;
}
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-/* I2C3 - IO expander */
-static struct i2c_pads_info i2c_pad_info2 = {
- .scl = {
- .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
- .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
- .gp = IMX_GPIO_NR(3, 17)
- },
- .sda = {
- .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
- .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
- .gp = IMX_GPIO_NR(3, 18)
- }
-};
-
static iomux_v3_cfg_t const pwm_pad[] = {
MX6_PAD_SD1_CMD__PWM4_OUT | MUX_PAD_CTRL(OUTPUT_40OHM),
};
@@ -315,8 +321,6 @@ int board_init(void)
backlight_lcd_off();
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
-
leds_on();
#ifdef CONFIG_CMD_SATA
--
2.1.0
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[U-Boot] [PATCH v1 06/12] arm: mvebu: Disable L2 cache before enabling d-cache
L2 cache may still be enabled by the BootROM. We need to first disable
it before enabling d-cache support.
Signed-off-by: Stefan Roese
---
arch/arm/mach-mvebu/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index b687422..767336c 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -7,6 +7,7 @@
#include
#include
#include
+#include
#include
#include
@@ -258,6 +259,13 @@ int cpu_eth_init(bd_t *bis)
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
+ struct pl310_regs *const pl310 =
+ (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
+ /* First disable L2 cache - may still be enable from BootROM */
+ if (mvebu_soc_family() == MVEBU_SOC_A38X)
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
/* Avoid problem with e.g. neta ethernet driver */
invalidate_dcache_all();
--
2.4.2
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[U-Boot] [PATCH v1 07/12] Makefile: Fix mvebu build target to use SPL load and exe-address
The u-boot-spl.kwb build target needs the SPL text-base (CONFIG_SPL_TEXT_BASE) as load and execution address. Signed-off-by: Stefan Roese --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 14f782e..13ff552 100644 --- a/Makefile +++ b/Makefile @@ -886,7 +886,7 @@ MKIMAGEFLAGS_u-boot.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \ -T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) MKIMAGEFLAGS_u-boot-spl.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \ - -T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) + -T kwbimage -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \ -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage -- 2.4.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1 00/12] Add SPL support including DDR init for Marvell Armada 38x
This patch-set adds the DDR3 setup and training code taken from the Marvell
U-Boot repository. This code used to be included as a binary (bin_hdr) into
the A38x boot image. Not linked with the main U-Boot. With this code
addition and the also included SERDES / PHY setup code, the Armada 38x
support in mainline U-Boot is finally self-contained. So the complete image
for booting can be built from mainline U-Boot. Without any additional
external inclusion.
Tested on Marvell Armada 38x DB-88F6820-GP using onboard soldered SDRAM.
Thanks,
Stefan
Kevin Smith (1):
tools/kwbimage.c: Correct header size for SPI boot
Stefan Roese (11):
tools/kwboot: Add parameters to set delay and timeout via cmdline
arm: mvebu: Use default reg base address for SPL on A38x
arm: mvebu: spl.c: Add call to board_early_init_f()
arm: mvebu: Disable MMU before changing register base address
arm: mvebu: Disable L2 cache before enabling d-cache
Makefile: Fix mvebu build target to use SPL load and exe-address
arm: mvebu: serdes: Move Armada XP SERDES / PHY init code into new
directory
arm: mvebu: Add Armada 38x SERDES / PHY init code from Marvell bin_hdr
arm: mvebu: drivers/ddr: Move Armada XP DDR init code into new
directory
arm: mvebu: Add Armada 38x DDR3 training code from Marvell bin_hdr
arm: mvebu: db-88f6820: Add SPL support with DDR init code
Makefile |2 +-
arch/arm/mach-mvebu/Makefile |4 +-
arch/arm/mach-mvebu/cpu.c | 26 +
arch/arm/mach-mvebu/include/mach/cpu.h |2 +-
arch/arm/mach-mvebu/include/mach/soc.h | 10 +
arch/arm/mach-mvebu/serdes/a38x/Makefile | 10 +
arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c | 347 +++
arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h | 82 +
.../serdes/a38x/high_speed_env_spec-38x.c | 158 ++
.../mach-mvebu/serdes/a38x/high_speed_env_spec.c | 2228 +
.../mach-mvebu/serdes/a38x/high_speed_env_spec.h | 251 ++
.../serdes/a38x/high_speed_topology_spec-38x.c | 1009
.../serdes/a38x/high_speed_topology_spec.h | 124 +
arch/arm/mach-mvebu/serdes/a38x/seq_exec.c | 170 ++
arch/arm/mach-mvebu/serdes/a38x/seq_exec.h | 65 +
arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c | 388 +++
arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h | 372 +++
arch/arm/mach-mvebu/serdes/{ => axp}/Makefile |0
.../mach-mvebu/serdes/{ => axp}/board_env_spec.h |0
.../serdes/{ => axp}/high_speed_env_lib.c |0
.../serdes/{ => axp}/high_speed_env_spec.c |0
.../serdes/{ => axp}/high_speed_env_spec.h |2 +-
arch/arm/mach-mvebu/spl.c |7 +
board/Marvell/db-88f6820-gp/README | 18 +
board/Marvell/db-88f6820-gp/db-88f6820-gp.c| 31 +
board/Marvell/db-88f6820-gp/kwbimage.cfg |2 +-
board/maxbcm/maxbcm.c |2 +-
configs/db-88f6820-gp_defconfig|1 +
drivers/ddr/marvell/a38x/Makefile | 19 +
drivers/ddr/marvell/a38x/ddr3_a38x.c | 741 ++
drivers/ddr/marvell/a38x/ddr3_a38x.h | 98 +
drivers/ddr/marvell/a38x/ddr3_a38x_mc_static.h | 226 ++
drivers/ddr/marvell/a38x/ddr3_a38x_topology.h | 22 +
drivers/ddr/marvell/a38x/ddr3_a38x_training.c | 40 +
drivers/ddr/marvell/a38x/ddr3_debug.c | 1551
drivers/ddr/marvell/a38x/ddr3_hws_hw_training.c| 148 ++
drivers/ddr/marvell/a38x/ddr3_hws_hw_training.h| 49 +
.../ddr/marvell/a38x/ddr3_hws_hw_training_def.h| 472
drivers/ddr/marvell/a38x/ddr3_hws_sil_training.h | 17 +
drivers/ddr/marvell/a38x/ddr3_init.c | 852 +++
drivers/ddr/marvell/a38x/ddr3_init.h | 395 +++
drivers/ddr/marvell/a38x/ddr3_logging_def.h| 101 +
drivers/ddr/marvell/a38x/ddr3_patterns_64bit.h | 924 +++
drivers/ddr/marvell/a38x/ddr3_topology_def.h | 76 +
drivers/ddr/marvell/a38x/ddr3_training.c | 2644
drivers/ddr/marvell/a38x/ddr3_training_bist.c | 289 +++
.../marvell/a38x/ddr3_training_centralization.c| 714 ++
drivers/ddr/marvell/a38x/ddr3_training_db.c| 652 +
drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c | 686 +
drivers/ddr/marvell/a38x/ddr3_training_hw_algo.h | 14 +
drivers/ddr/marvell/a38x/ddr3_training_ip.h| 180 ++
drivers/ddr/marvell/a38x/ddr3_training_ip_bist.h | 54 +
.../marvell/a38x/ddr3_training_ip_centralization.h | 15 +
drivers/ddr/marvell/a38x/ddr3_training_ip_db.h | 34 +
drivers/ddr/marvell/a38x/ddr3_training_ip_def.h| 173 ++
drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c | 1354 ++
drivers/ddr/marvell/a38x/ddr3_training_ip_engine.h | 85 +
drivers/ddr/marvell/a38x/ddr3_trainin
[U-Boot] [PATCH v1 12/12] arm: mvebu: db-88f6820: Add SPL support with DDR init code
This patch adds SPL support for the Marvell DB-88F6820-GP board.
With this change, the bin_hdr from the original Marvell U-boot
is not needed any more on this board. The sources from bin_hdr
(SERDES/PHY and DDR setup) are now integrated in mainline
U-Boot. And this patch enables them for this board.
Signed-off-by: Stefan Roese
---
board/Marvell/db-88f6820-gp/README | 18 +++
board/Marvell/db-88f6820-gp/db-88f6820-gp.c | 31 +
board/Marvell/db-88f6820-gp/kwbimage.cfg| 2 +-
configs/db-88f6820-gp_defconfig | 1 +
include/configs/db-88f6820-gp.h | 35 +
5 files changed, 86 insertions(+), 1 deletion(-)
create mode 100644 board/Marvell/db-88f6820-gp/README
diff --git a/board/Marvell/db-88f6820-gp/README
b/board/Marvell/db-88f6820-gp/README
new file mode 100644
index 000..9bea5b3
--- /dev/null
+++ b/board/Marvell/db-88f6820-gp/README
@@ -0,0 +1,18 @@
+Update from original Marvell U-Boot to mainline U-Boot:
+---
+
+The resulting image including the SPL binary with the
+full DDR setup is "u-boot-spl.kwb".
+
+To update the SPI NOR flash, please use the following
+command:
+
+=> sf probe;tftpboot 200 db-88f6820-gp/u-boot-spl.kwb;\
+sf update 200 0 6
+
+Note that the original Marvell U-Boot seems to have
+problems with the "sf update" command. This does not
+work reliable. So here this command should be used:
+
+=> sf probe;tftpboot 200 db-88f6820-gp/u-boot-spl.kwb;\
+sf erase 0 6;sf write 200 0 6
diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
index 51ac495..e661fa1 100644
--- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
+++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
@@ -11,6 +11,8 @@
#include
#include
+#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
+
DECLARE_GLOBAL_DATA_PTR;
#define BIT(nr)(1UL << (nr))
@@ -54,6 +56,35 @@ static struct marvell_io_exp io_exp[] = {
{ 0x21, 3, 0xC0 } /* Output Data, register#1 */
};
+/*
+ * Define the DDR layout / topology here in the board file. This will
+ * be used by the DDR3 init code in the SPL U-Boot version to configure
+ * the DDR3 controller.
+ */
+static struct hws_topology_map board_topology_map = {
+ 0x1, /* active interfaces */
+ /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+ { { { {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0} },
+ SPEED_BIN_DDR_1866L,/* speed_bin */
+ BUS_WIDTH_8,/* memory_width */
+ MEM_4G, /* mem_size */
+ DDR_FREQ_800, /* frequency */
+ 0, 0, /* cas_l cas_wl */
+ HWS_TEMP_LOW} },/* temperature */
+ 5, /* Num Of Bus Per Interface*/
+ BUS_MASK_32BIT /* Busses mask */
+};
+
+struct hws_topology_map *ddr3_get_topology_map(void)
+{
+ /* Return the board topology as defined in the board code */
+ return &board_topology_map;
+}
+
int board_early_init_f(void)
{
/* Configure MPP */
diff --git a/board/Marvell/db-88f6820-gp/kwbimage.cfg
b/board/Marvell/db-88f6820-gp/kwbimage.cfg
index e812454..cc05792 100644
--- a/board/Marvell/db-88f6820-gp/kwbimage.cfg
+++ b/board/Marvell/db-88f6820-gp/kwbimage.cfg
@@ -9,4 +9,4 @@ VERSION 1
BOOT_FROM spi
# Binary Header (bin_hdr) with DDR3 training code
-BINARY board/Marvell/db-88f6820-gp/binary.0 005b 0068
+BINARY spl/u-boot-spl.bin 005b 0068
diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig
index 5f53522..eac2f86 100644
--- a/configs/db-88f6820-gp_defconfig
+++ b/configs/db-88f6820-gp_defconfig
@@ -1,3 +1,4 @@
+CONFIG_SPL=y
CONFIG_ARM=y
CONFIG_TARGET_DB_88F6820_GP=y
CONFIG_CMD_NET=y
diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h
index 12a24ce..6280274 100644
--- a/include/configs/db-88f6820-gp.h
+++ b/include/configs/db-88f6820-gp.h
@@ -11,6 +11,7 @@
* High Level Configuration Options (easy to change)
*/
#define CONFIG_ARMADA_XP /* SOC Family Name */
+#define CONFIG_ARMADA_38X
#define CONFIG_DB_88F6820_GP /* Board target name for DDR training */
#define CONFIG_SYS_L2_PL310
@@ -63,6 +64,40 @@
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
#define CONFIG_SYS_ALT_MEMTEST
+/* SPL */
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_SIZE(140 << 10)
+#define CONFIG_SPL_TEXT_BASE 0x4030
+#define CONFIG_SPL_MAX_SIZE(CONFIG_SPL_SIZE - 0x0030)
+
+#define CONFIG_SPL_BSS_START_ADDR (0x4000 + CONFIG_SPL_SIZE)
+#define CONFIG_SPL_BSS_MAX_SIZE
[U-Boot] [PATCH v1 08/12] arm: mvebu: serdes: Move Armada XP SERDES / PHY init code into new directory
With the upcoming addition of the Armada 38x SPL support, which is not
compatible to the Armada XP SERDES init code, we need to introduce a new
directory infrastructure. So lets move the AXP serdes init code into
a new directory. This way the A38x code can be added in a clean way.
Signed-off-by: Stefan Roese
---
arch/arm/mach-mvebu/Makefile | 3 ++-
arch/arm/mach-mvebu/serdes/{ => axp}/Makefile | 0
arch/arm/mach-mvebu/serdes/{ => axp}/board_env_spec.h | 0
arch/arm/mach-mvebu/serdes/{ => axp}/high_speed_env_lib.c | 0
arch/arm/mach-mvebu/serdes/{ => axp}/high_speed_env_spec.c | 0
arch/arm/mach-mvebu/serdes/{ => axp}/high_speed_env_spec.h | 0
6 files changed, 2 insertions(+), 1 deletion(-)
rename arch/arm/mach-mvebu/serdes/{ => axp}/Makefile (100%)
rename arch/arm/mach-mvebu/serdes/{ => axp}/board_env_spec.h (100%)
rename arch/arm/mach-mvebu/serdes/{ => axp}/high_speed_env_lib.c (100%)
rename arch/arm/mach-mvebu/serdes/{ => axp}/high_speed_env_spec.c (100%)
rename arch/arm/mach-mvebu/serdes/{ => axp}/high_speed_env_spec.h (100%)
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 4f477cd..9cdbefd 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -20,5 +20,6 @@ obj-y += timer.o
obj-$(CONFIG_SPL_BUILD) += spl.o
obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o
-obj-y += serdes/
+obj-$(CONFIG_SYS_MVEBU_DDR_AXP)+= serdes/axp/
+
endif
diff --git a/arch/arm/mach-mvebu/serdes/Makefile
b/arch/arm/mach-mvebu/serdes/axp/Makefile
similarity index 100%
rename from arch/arm/mach-mvebu/serdes/Makefile
rename to arch/arm/mach-mvebu/serdes/axp/Makefile
diff --git a/arch/arm/mach-mvebu/serdes/board_env_spec.h
b/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h
similarity index 100%
rename from arch/arm/mach-mvebu/serdes/board_env_spec.h
rename to arch/arm/mach-mvebu/serdes/axp/board_env_spec.h
diff --git a/arch/arm/mach-mvebu/serdes/high_speed_env_lib.c
b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
similarity index 100%
rename from arch/arm/mach-mvebu/serdes/high_speed_env_lib.c
rename to arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
diff --git a/arch/arm/mach-mvebu/serdes/high_speed_env_spec.c
b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.c
similarity index 100%
rename from arch/arm/mach-mvebu/serdes/high_speed_env_spec.c
rename to arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.c
diff --git a/arch/arm/mach-mvebu/serdes/high_speed_env_spec.h
b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h
similarity index 100%
rename from arch/arm/mach-mvebu/serdes/high_speed_env_spec.h
rename to arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h
--
2.4.2
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[U-Boot] [PATCH v1 10/12] arm: mvebu: drivers/ddr: Move Armada XP DDR init code into new directory
With the upcoming addition of the Armada 38x DDR support, which is not
compatible to the Armada XP DDR init code, we need to introduce a new
directory infrastructure. To support multiple Marvell DDR controller.
This will be the new structure:
drivers/ddr/marvell/axp
Supporting Armada XP (AXP) devices (and perhaps Armada 370)
drivers/ddr/marvell/a38x
Supporting Armada 38x devices (and perhaps Armada 39x)
Signed-off-by: Stefan Roese
---
arch/arm/mach-mvebu/include/mach/cpu.h| 2 +-
arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h | 2 +-
board/maxbcm/maxbcm.c | 2 +-
drivers/ddr/{mvebu => marvell/axp}/Makefile | 0
drivers/ddr/{mvebu => marvell/axp}/ddr3_axp.h | 0
drivers/ddr/{mvebu => marvell/axp}/ddr3_axp_config.h | 0
drivers/ddr/{mvebu => marvell/axp}/ddr3_axp_mc_static.h | 0
drivers/ddr/{mvebu => marvell/axp}/ddr3_axp_training_static.h | 0
drivers/ddr/{mvebu => marvell/axp}/ddr3_axp_vars.h| 0
drivers/ddr/{mvebu => marvell/axp}/ddr3_dfs.c | 0
drivers/ddr/{mvebu => marvell/axp}/ddr3_dqs.c | 0
drivers/ddr/{mvebu => marvell/axp}/ddr3_hw_training.c | 0
drivers/ddr/{mvebu => marvell/axp}/ddr3_hw_training.h | 0
drivers/ddr/{mvebu => marvell/axp}/ddr3_init.c| 0
drivers/ddr/{mvebu => marvell/axp}/ddr3_init.h| 0
drivers/ddr/{mvebu => marvell/axp}/ddr3_patterns_64bit.h | 0
drivers/ddr/{mvebu => marvell/axp}/ddr3_pbs.c | 0
drivers/ddr/{mvebu => marvell/axp}/ddr3_read_leveling.c | 0
drivers/ddr/{mvebu => marvell/axp}/ddr3_sdram.c | 0
drivers/ddr/{mvebu => marvell/axp}/ddr3_spd.c | 0
drivers/ddr/{mvebu => marvell/axp}/ddr3_write_leveling.c | 0
drivers/ddr/{mvebu => marvell/axp}/xor.c | 0
drivers/ddr/{mvebu => marvell/axp}/xor.h | 0
drivers/ddr/{mvebu => marvell/axp}/xor_regs.h | 0
include/configs/db-mv784mp-gp.h | 2 +-
include/configs/maxbcm.h | 2 +-
scripts/Makefile.spl | 2 +-
27 files changed, 6 insertions(+), 6 deletions(-)
rename drivers/ddr/{mvebu => marvell/axp}/Makefile (100%)
rename drivers/ddr/{mvebu => marvell/axp}/ddr3_axp.h (100%)
rename drivers/ddr/{mvebu => marvell/axp}/ddr3_axp_config.h (100%)
rename drivers/ddr/{mvebu => marvell/axp}/ddr3_axp_mc_static.h (100%)
rename drivers/ddr/{mvebu => marvell/axp}/ddr3_axp_training_static.h (100%)
rename drivers/ddr/{mvebu => marvell/axp}/ddr3_axp_vars.h (100%)
rename drivers/ddr/{mvebu => marvell/axp}/ddr3_dfs.c (100%)
rename drivers/ddr/{mvebu => marvell/axp}/ddr3_dqs.c (100%)
rename drivers/ddr/{mvebu => marvell/axp}/ddr3_hw_training.c (100%)
rename drivers/ddr/{mvebu => marvell/axp}/ddr3_hw_training.h (100%)
rename drivers/ddr/{mvebu => marvell/axp}/ddr3_init.c (100%)
rename drivers/ddr/{mvebu => marvell/axp}/ddr3_init.h (100%)
rename drivers/ddr/{mvebu => marvell/axp}/ddr3_patterns_64bit.h (100%)
rename drivers/ddr/{mvebu => marvell/axp}/ddr3_pbs.c (100%)
rename drivers/ddr/{mvebu => marvell/axp}/ddr3_read_leveling.c (100%)
rename drivers/ddr/{mvebu => marvell/axp}/ddr3_sdram.c (100%)
rename drivers/ddr/{mvebu => marvell/axp}/ddr3_spd.c (100%)
rename drivers/ddr/{mvebu => marvell/axp}/ddr3_write_leveling.c (100%)
rename drivers/ddr/{mvebu => marvell/axp}/xor.c (100%)
rename drivers/ddr/{mvebu => marvell/axp}/xor.h (100%)
rename drivers/ddr/{mvebu => marvell/axp}/xor_regs.h (100%)
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h
b/arch/arm/mach-mvebu/include/mach/cpu.h
index 3b48460..45f3397 100644
--- a/arch/arm/mach-mvebu/include/mach/cpu.h
+++ b/arch/arm/mach-mvebu/include/mach/cpu.h
@@ -123,7 +123,7 @@ int serdes_phy_config(void);
/*
* DDR3 init / training code ported from Marvell bin_hdr. Now
* available in mainline U-Boot in:
- * drivers/ddr/mvebu/
+ * drivers/ddr/marvell
*/
int ddr3_init(void);
#endif /* __ASSEMBLY__ */
diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h
b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h
index e5aa1b0..e10574e 100644
--- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h
+++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h
@@ -7,7 +7,7 @@
#ifndef __HIGHSPEED_ENV_SPEC_H
#define __HIGHSPEED_ENV_SPEC_H
-#include "../../../drivers/ddr/mvebu/ddr3_hw_training.h"
+#include "../../../drivers/ddr/marvell/axp/ddr3_hw_training.h"
typedef enum {
SERDES_UNIT_UNCONNECTED = 0x0,
diff --git a/board/maxbcm/maxbcm.c b/board/maxbcm/maxbcm.c
index 2fbb90c..a7ce837 100644
--- a/board/maxbcm/maxbcm.c
+++ b/board/maxbcm/maxbcm.c
@@ -11,7 +11,7 @@
#include
#include
-#include "../drivers/ddr/mvebu/ddr3_hw_training.h"
+#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
[U-Boot] [PATCH v1 03/12] arm: mvebu: Use default reg base address for SPL on A38x
On A38x switching the regs base address without running from SDRAM doesn't seem to work. So let the SPL still use the default base address and switch to the new address in the mail u-boot later. Signed-off-by: Stefan Roese --- arch/arm/mach-mvebu/include/mach/soc.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 0a9307c..d07e462 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -28,7 +28,17 @@ /* SOC specific definations */ #define INTREG_BASE0xd000 #define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080) +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SYS_MVEBU_DDR_A38X) +/* + * On A38x switching the regs base address without running from + * SDRAM doesn't seem to work. So let the SPL still use the + * default base address and switch to the new address in the + * main u-boot later. + */ +#define SOC_REGS_PHY_BASE 0xd000 +#else #define SOC_REGS_PHY_BASE 0xf100 +#endif #define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x) #define MVEBU_SDRAM_SCRATCH(MVEBU_REGISTER(0x01504)) -- 2.4.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1 05/12] arm: mvebu: Disable MMU before changing register base address
Only with disabled MMU its possible to switch the base register address on
Armada 38x. Without this the SDRAM located at >= 0x4000. is also not
accessible, as its still locked to cache.
Signed-off-by: Stefan Roese
---
arch/arm/mach-mvebu/cpu.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 04681fc..b687422 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -159,9 +159,27 @@ static void update_sdram_window_sizes(void)
}
}
+void mmu_disable(void)
+{
+ asm volatile(
+ "mrc p15, 0, r0, c1, c0, 0\n"
+ "bic r0, #1\n"
+ "mcr p15, 0, r0, c1, c0, 0\n");
+}
+
#ifdef CONFIG_ARCH_CPU_INIT
int arch_cpu_init(void)
{
+#ifndef CONFIG_SPL_BUILD
+ /*
+* Only with disabled MMU its possible to switch the base
+* register address on Armada 38x. Without this the SDRAM
+* located at >= 0x4000. is also not accessible, as its
+* still locked to cache.
+*/
+ mmu_disable();
+#endif
+
/* Linux expects the internal registers to be at 0xf100 */
writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
--
2.4.2
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[U-Boot] [PATCH v1 02/12] tools/kwboot: Add parameters to set delay and timeout via cmdline
To support the Armada 38x, new values for the request-delay and the
response-timeout are needed. As the values already implemented in
this tool (for Kirkwood and Armada XP) don't seem to work here.
To make this more flexible, lets add make those 2 parameters
configurable via the cmdline. Here the new parameters:
-q : use specific request-delay
-s : use specific response-timeout
For the Marvell DB-88F6820 these values are known to work:
One board:
-q 2 -s 1
2nd board:
-q 5 -s 5
So this seems to be even board specific. But with this patch now
those values can be specified and tested via the cmdline.
Signed-off-by: Stefan Roese
Cc: Kevin Smith
Cc: Dirk Eibach
Cc: Luka Perkov
---
tools/kwboot.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/tools/kwboot.c b/tools/kwboot.c
index 1368b4c..af7a6ee 100644
--- a/tools/kwboot.c
+++ b/tools/kwboot.c
@@ -657,7 +657,7 @@ static void
kwboot_usage(FILE *stream, char *progname)
{
fprintf(stream,
- "Usage: %s [-d | -a | -b | -D ] [ -t ] [-B
] \n",
+ "Usage: %s [-d | -a | -q | -s | -b
| -D ] [ -t ] [-B ] \n",
progname);
fprintf(stream, "\n");
fprintf(stream,
@@ -667,6 +667,8 @@ kwboot_usage(FILE *stream, char *progname)
" -D : boot without preamble (Dove)\n");
fprintf(stream, " -d: enter debug mode\n");
fprintf(stream, " -a: use timings for Armada XP\n");
+ fprintf(stream, " -q : use specific request-delay\n");
+ fprintf(stream, " -s : use specific response-timeout\n");
fprintf(stream, "\n");
fprintf(stream, " -t: mini terminal\n");
fprintf(stream, "\n");
@@ -699,7 +701,7 @@ main(int argc, char **argv)
kwboot_verbose = isatty(STDOUT_FILENO);
do {
- int c = getopt(argc, argv, "hb:ptaB:dD:");
+ int c = getopt(argc, argv, "hb:ptaB:dD:q:s:");
if (c < 0)
break;
@@ -731,6 +733,14 @@ main(int argc, char **argv)
msg_rsp_timeo = KWBOOT_MSG_RSP_TIMEO_AXP;
break;
+ case 'q':
+ msg_req_delay = atoi(optarg);
+ break;
+
+ case 's':
+ msg_rsp_timeo = atoi(optarg);
+ break;
+
case 'B':
speed = kwboot_tty_speed(atoi(optarg));
if (speed == -1)
--
2.4.2
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[U-Boot] [PATCH v1 04/12] arm: mvebu: spl.c: Add call to board_early_init_f()
Pin muxing needs to be done before UART output, since on A38x the UART pins need some re-muxing for output to work. Signed-off-by: Stefan Roese --- arch/arm/mach-mvebu/spl.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index 402e520..2df25aa 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -26,6 +26,13 @@ void board_init_f(ulong dummy) /* Linux expects the internal registers to be at 0xf100 */ arch_cpu_init(); + /* +* Pin muxing needs to be done before UART output, since +* on A38x the UART pins need some re-muxing for output +* to work. +*/ + board_early_init_f(); + preloader_console_init(); /* First init the serdes PHY's */ -- 2.4.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1 01/12] tools/kwbimage.c: Correct header size for SPI boot
From: Kevin Smith
If defined, the macro CONFIG_SYS_SPI_U_BOOT_OFFS allows a board
to specify the offset of the payload image into the kwb image
file. This value was being used to locate the image, but was not
used in the "header size" field of the main header. Move the
use of this macro into the function that returns the header size
so that the same value is used in all places.
Signed-off-by: Kevin Smith
Signed-off-by: Stefan Roese
---
tools/kwbimage.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index 9540e7e..1ff17ca 100644
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -420,6 +420,18 @@ static size_t image_headersz_v1(struct image_tool_params
*params,
*hasext = 1;
}
+#if defined(CONFIG_SYS_SPI_U_BOOT_OFFS)
+ if (headersz > CONFIG_SYS_SPI_U_BOOT_OFFS) {
+ fprintf(stderr, "Error: Image header (incl. SPL image) too
big!\n");
+ fprintf(stderr, "header=0x%x
CONFIG_SYS_SPI_U_BOOT_OFFS=0x%x!\n",
+ (int)headersz, CONFIG_SYS_SPI_U_BOOT_OFFS);
+ fprintf(stderr, "Increase CONFIG_SYS_SPI_U_BOOT_OFFS!\n");
+ return 0;
+ } else {
+ headersz = CONFIG_SYS_SPI_U_BOOT_OFFS;
+ }
+#endif
+
/*
* The payload should be aligned on some reasonable
* boundary
@@ -869,16 +881,6 @@ static int kwbimage_generate(struct image_tool_params
*params,
sizeof(struct ext_hdr_v0);
} else {
alloc_len = image_headersz_v1(params, NULL);
-#if defined(CONFIG_SYS_SPI_U_BOOT_OFFS)
- if (alloc_len > CONFIG_SYS_SPI_U_BOOT_OFFS) {
- fprintf(stderr, "Error: Image header (incl. SPL image)
too big!\n");
- fprintf(stderr, "header=0x%x
CONFIG_SYS_SPI_U_BOOT_OFFS=0x%x!\n",
- alloc_len, CONFIG_SYS_SPI_U_BOOT_OFFS);
- fprintf(stderr, "Increase
CONFIG_SYS_SPI_U_BOOT_OFFS!\n");
- } else {
- alloc_len = CONFIG_SYS_SPI_U_BOOT_OFFS;
- }
-#endif
}
hdr = malloc(alloc_len);
--
2.4.2
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[U-Boot] [PATCH 2/7] ARM: BeagleBoard-X15: Enable HW leveling
Updating EMIF registers to enable HW leveling
on BeagleBoard-X15.
Signed-off-by: Lokesh Vutla
---
board/ti/beagle_x15/board.c | 26 ++
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c
index 75dd8e8..76654c8 100644
--- a/board/ti/beagle_x15/board.c
+++ b/board/ti/beagle_x15/board.c
@@ -55,15 +55,15 @@ static const struct emif_regs
beagle_x15_emif1_ddr3_532mhz_emif_regs = {
.read_idle_ctrl = 0x00050001,
.zq_config = 0x0007190b,
.temp_alert_config = 0x,
- .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
- .emif_ddr_phy_ctlr_1= 0x0e24400a,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400b,
+ .emif_ddr_phy_ctlr_1= 0x0e24400b,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00740074,
.emif_ddr_ext_phy_ctrl_3 = 0x00780078,
.emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
.emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
.emif_rd_wr_lvl_rmp_win = 0x,
- .emif_rd_wr_lvl_rmp_ctl = 0x,
+ .emif_rd_wr_lvl_rmp_ctl = 0x8000,
.emif_rd_wr_lvl_ctl = 0x,
.emif_rd_wr_exec_thresh = 0x0305
};
@@ -103,7 +103,12 @@ static const u32
beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
0x00400040,
0x00400040,
0x00400040,
- 0x00400040
+ 0x00400040,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0
};
static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
@@ -118,15 +123,15 @@ static const struct emif_regs
beagle_x15_emif2_ddr3_532mhz_emif_regs = {
.read_idle_ctrl = 0x00050001,
.zq_config = 0x0007190b,
.temp_alert_config = 0x,
- .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
- .emif_ddr_phy_ctlr_1= 0x0e24400a,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400b,
+ .emif_ddr_phy_ctlr_1= 0x0e24400b,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00820082,
.emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
.emif_ddr_ext_phy_ctrl_4 = 0x00800080,
.emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
.emif_rd_wr_lvl_rmp_win = 0x,
- .emif_rd_wr_lvl_rmp_ctl = 0x,
+ .emif_rd_wr_lvl_rmp_ctl = 0x8000,
.emif_rd_wr_lvl_ctl = 0x,
.emif_rd_wr_exec_thresh = 0x0305
};
@@ -163,7 +168,12 @@ static const u32
beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
0x00400040,
0x00400040,
0x00400040,
- 0x00400040
+ 0x00400040,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0
};
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
--
1.9.1
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[U-Boot] [PATCH 7/7] ARM: DRA7: Update DDR IO registers
Update DDR IO register values.
Signed-off-by: Lokesh Vutla
---
arch/arm/cpu/armv7/omap5/hw_data.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index b9734fe..6de5974 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -578,11 +578,11 @@ const struct ctrl_ioregs ioregs_dra7xx_es1 = {
.ctrl_ddrch = 0x40404040,
.ctrl_lpddr2ch = 0x40404040,
.ctrl_ddr3ch = 0x80808080,
- .ctrl_ddrio_0 = 0xA2084210,
- .ctrl_ddrio_1 = 0x84210840,
+ .ctrl_ddrio_0 = 0x00094A40,
+ .ctrl_ddrio_1 = 0x04A52000,
.ctrl_ddrio_2 = 0x8421,
- .ctrl_emif_sdram_config_ext = 0x0001C1A7,
- .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
+ .ctrl_emif_sdram_config_ext = 0x0001C127,
+ .ctrl_emif_sdram_config_ext_final = 0x0001C127,
.ctrl_ddr_ctrl_ext_0 = 0xA200,
};
@@ -590,11 +590,11 @@ const struct ctrl_ioregs ioregs_dra72x_es1 = {
.ctrl_ddrch = 0x40404040,
.ctrl_lpddr2ch = 0x40404040,
.ctrl_ddr3ch = 0x60606080,
- .ctrl_ddrio_0 = 0xA2084210,
- .ctrl_ddrio_1 = 0x84210840,
+ .ctrl_ddrio_0 = 0x00094A40,
+ .ctrl_ddrio_1 = 0x04A52000,
.ctrl_ddrio_2 = 0x8421,
- .ctrl_emif_sdram_config_ext = 0x0001C1A7,
- .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
+ .ctrl_emif_sdram_config_ext = 0x0001C127,
+ .ctrl_emif_sdram_config_ext_final = 0x0001C127,
.ctrl_ddr_ctrl_ext_0 = 0xA200,
};
--
1.9.1
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[U-Boot] [PATCH 3/7] ARM: DRA7-evm: Enable HW leveling
Updating EMIF registers to enable HW leveling
on DRA7-evm.
Signed-off-by: Lokesh Vutla
---
arch/arm/cpu/armv7/omap5/sdram.c | 22 --
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 2e23852..942a80a 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -149,15 +149,15 @@ const struct emif_regs
emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
.read_idle_ctrl = 0x00050001,
.zq_config = 0x0007190B,
.temp_alert_config = 0x,
- .emif_ddr_phy_ctlr_1_init = 0x0E24400A,
- .emif_ddr_phy_ctlr_1= 0x0E24400A,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400B,
+ .emif_ddr_phy_ctlr_1= 0x0E24400B,
.emif_ddr_ext_phy_ctrl_1= 0x10040100,
.emif_ddr_ext_phy_ctrl_2= 0x00910091,
.emif_ddr_ext_phy_ctrl_3= 0x00950095,
.emif_ddr_ext_phy_ctrl_4= 0x009B009B,
.emif_ddr_ext_phy_ctrl_5= 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x,
- .emif_rd_wr_lvl_rmp_ctl = 0x,
+ .emif_rd_wr_lvl_rmp_ctl = 0x8000,
.emif_rd_wr_lvl_ctl = 0x,
.emif_rd_wr_exec_thresh = 0x0305
};
@@ -174,15 +174,15 @@ const struct emif_regs
emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
.read_idle_ctrl = 0x00050001,
.zq_config = 0x0007190B,
.temp_alert_config = 0x,
- .emif_ddr_phy_ctlr_1_init = 0x0E24400A,
- .emif_ddr_phy_ctlr_1= 0x0E24400A,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400B,
+ .emif_ddr_phy_ctlr_1= 0x0E24400B,
.emif_ddr_ext_phy_ctrl_1= 0x10040100,
.emif_ddr_ext_phy_ctrl_2= 0x00910091,
.emif_ddr_ext_phy_ctrl_3= 0x00950095,
.emif_ddr_ext_phy_ctrl_4= 0x009B009B,
.emif_ddr_ext_phy_ctrl_5= 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x,
- .emif_rd_wr_lvl_rmp_ctl = 0x,
+ .emif_rd_wr_lvl_rmp_ctl = 0x8000,
.emif_rd_wr_lvl_ctl = 0x,
.emif_rd_wr_exec_thresh = 0x0305
};
@@ -453,6 +453,11 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
0x0,
0x0,
0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
0x0
};
@@ -488,6 +493,11 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
0x0,
0x0,
0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
0x0
};
--
1.9.1
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[U-Boot] [PATCH 6/7] ARM: DRA7: Update DDR IO configuration
DDRIO_2 and LPDDR2CH1_1 registers are not present
for DRA7. So not configuring these registers for DRA7xx
Signed-off-by: Lokesh Vutla
---
arch/arm/cpu/armv7/omap5/hwinit.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c
b/arch/arm/cpu/armv7/omap5/hwinit.c
index 8d6b59e..03c2b97 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -75,16 +75,20 @@ static void io_settings_ddr3(void)
writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
- writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
+
+ if (!is_dra7xx()) {
+ writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
+ writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
+ }
/* omap5432 does not use lpddr2 */
writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
- writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
writel(ioregs->ctrl_emif_sdram_config_ext,
(*ctrl)->control_emif1_sdram_config_ext);
- writel(ioregs->ctrl_emif_sdram_config_ext,
- (*ctrl)->control_emif2_sdram_config_ext);
+ if (!is_dra72x())
+ writel(ioregs->ctrl_emif_sdram_config_ext,
+ (*ctrl)->control_emif2_sdram_config_ext);
if (is_omap54xx()) {
/* Disable DLL select */
--
1.9.1
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[U-Boot] [PATCH 5/7] ARM: DRA7: Add is_dra72x cpu check definition
A generic is_dra72x cpu check is useful for grouping
all the revisions under that. This is used in the
subsequent patches.
Signed-off-by: Lokesh Vutla
---
arch/arm/include/asm/omap_common.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/include/asm/omap_common.h
b/arch/arm/include/asm/omap_common.h
index 123c84f..3387c1d 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -617,12 +617,19 @@ static inline u8 is_omap54xx(void)
}
#define DRA7XX 0x0700
+#define DRA72X 0x0720
static inline u8 is_dra7xx(void)
{
extern u32 *const omap_si_rev;
return ((*omap_si_rev & 0xFF00) == DRA7XX);
}
+
+static inline u8 is_dra72x(void)
+{
+ extern u32 *const omap_si_rev;
+ return (*omap_si_rev & 0xFFF0) == DRA72X;
+}
#endif
/*
--
1.9.1
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[U-Boot] [PATCH 4/7] ARM: DRA72-evm: Enable HW leveling
Updating EMIF registers to enable HW leveling
on DRA72-evm.
Also updating the timing registers.
Signed-off-by: Lokesh Vutla
---
arch/arm/cpu/armv7/omap5/sdram.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 942a80a..3022b9e 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -191,15 +191,15 @@ const struct emif_regs
emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
.sdram_config_init = 0x61862B32,
.sdram_config = 0x61862B32,
.sdram_config2 = 0x0800,
- .ref_ctrl = 0x493E,
+ .ref_ctrl = 0x514C,
.ref_ctrl_final = 0x144A,
.sdram_tim1 = 0xD113781C,
- .sdram_tim2 = 0x308F7FE3,
- .sdram_tim3 = 0x009F86A8,
+ .sdram_tim2 = 0x305A7FDA,
+ .sdram_tim3 = 0x409F86A8,
.read_idle_ctrl = 0x0005,
- .zq_config = 0x0007190B,
+ .zq_config = 0x5007190B,
.temp_alert_config = 0x,
- .emif_ddr_phy_ctlr_1_init = 0x0E24400D,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400D,
.emif_ddr_phy_ctlr_1= 0x0E24400D,
.emif_ddr_ext_phy_ctrl_1= 0x10040100,
.emif_ddr_ext_phy_ctrl_2= 0x00A400A4,
@@ -207,7 +207,7 @@ const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1
= {
.emif_ddr_ext_phy_ctrl_4= 0x00B000B0,
.emif_ddr_ext_phy_ctrl_5= 0x00B000B0,
.emif_rd_wr_lvl_rmp_win = 0x,
- .emif_rd_wr_lvl_rmp_ctl = 0x,
+ .emif_rd_wr_lvl_rmp_ctl = 0x8000,
.emif_rd_wr_lvl_ctl = 0x,
.emif_rd_wr_exec_thresh = 0x0305
};
@@ -533,6 +533,11 @@ dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = {
0x0,
0x0,
0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
0x0
};
--
1.9.1
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[U-Boot] [PATCH 1/7] ARM: DRA7: DDR3: Add support for HW leveling
DRA7 EMIF supports Full leveling for DDR3.
Adding support for the Full leveling sequence.
Signed-off-by: Lokesh Vutla
---
arch/arm/cpu/armv7/omap-common/emif-common.c | 146 +++
arch/arm/cpu/armv7/omap5/sdram.c | 76 +-
arch/arm/include/asm/emif.h | 9 ++
board/ti/beagle_x15/board.c | 15 ++-
4 files changed, 220 insertions(+), 26 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c
b/arch/arm/cpu/armv7/omap-common/emif-common.c
index c01a98f..3ee4695 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -242,13 +242,122 @@ static void omap5_ddr3_leveling(u32 base, const struct
emif_regs *regs)
__udelay(130);
}
-static void ddr3_leveling(u32 base, const struct emif_regs *regs)
+static void update_hwleveling_output(u32 base, const struct emif_regs *regs)
{
- if (is_omap54xx())
- omap5_ddr3_leveling(base, regs);
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+ u32 *emif_ext_phy_ctrl_reg, *emif_phy_status;
+ u32 reg, i;
+
+ emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7];
+
+ /* Update PHY_REG_RDDQS_RATIO */
+ emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7;
+ for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) {
+ reg = readl(emif_phy_status++);
+ writel(reg, emif_ext_phy_ctrl_reg++);
+ writel(reg, emif_ext_phy_ctrl_reg++);
+ }
+
+ /* Update PHY_REG_FIFO_WE_SLAVE_RATIO */
+ emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2;
+ for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) {
+ reg = readl(emif_phy_status++);
+ writel(reg, emif_ext_phy_ctrl_reg++);
+ writel(reg, emif_ext_phy_ctrl_reg++);
+ }
+
+ /* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */
+ emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12;
+ for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) {
+ reg = readl(emif_phy_status++);
+ writel(reg, emif_ext_phy_ctrl_reg++);
+ writel(reg, emif_ext_phy_ctrl_reg++);
+ }
+
+ /* Disable Leveling */
+ writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
+ writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
+ writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
}
-static void ddr3_init(u32 base, const struct emif_regs *regs)
+static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+ /* Clear Error Status */
+ clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36,
+ EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
+ EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
+
+ clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36_shdw,
+ EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
+ EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
+
+ /* Disable refreshed before leveling */
+ clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT,
+ EMIF_REG_INITREF_DIS_SHIFT);
+
+ /* Start Full leveling */
+ writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
+
+ __udelay(300);
+
+ /* Check for leveling timeout */
+ if (readl(&emif->emif_status) & EMIF_REG_LEVELING_TO_MASK) {
+ printf("Leveling timeout on EMIF%d\n", emif_num(base));
+ return;
+ }
+
+ /* Enable refreshes after leveling */
+ clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT);
+
+ debug("HW leveling success\n");
+ /*
+* Update slave ratios in EXT_PHY_CTRLx registers
+* as per HW leveling output
+*/
+ update_hwleveling_output(base, regs);
+}
+
+static void dra7_ddr3_init(u32 base, const struct emif_regs *regs)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+ if (warm_reset())
+ emif_reset_phy(base);
+ do_ext_phy_settings(base, regs);
+
+ writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK,
+ &emif->emif_sdram_ref_ctrl);
+ /* Update timing registers */
+ writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
+ writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
+ writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
+
+ writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config);
+ writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
+ writel(regs->zq_config, &emif->emif_zq_config);
+ writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
+ writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
+ writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl);
+
+ writel(regs->
[U-Boot] [PATCH 0/7] ARM: DRA7: DDR3: Enable hw leveling
This series updates the DDR3 init sequence and adds support for hw leveling for all DRA7 platforms. Tested memtest and reboot on DRA7-evm , DRA72-evm, BeagleBoard-x15 boards. Lokesh Vutla (7): ARM: DRA7: DDR3: Add support for HW leveling ARM: BeagleBoard-X15: Enable HW leveling ARM: DRA7-evm: Enable HW leveling ARM: DRA72-evm: Enable HW leveling ARM: DRA7: Add is_dra72x cpu check definition ARM: DRA7: Update DDR IO configuration ARM: DRA7: Update DDR IO registers arch/arm/cpu/armv7/omap-common/emif-common.c | 146 +++ arch/arm/cpu/armv7/omap5/hw_data.c | 16 +-- arch/arm/cpu/armv7/omap5/hwinit.c| 12 ++- arch/arm/cpu/armv7/omap5/sdram.c | 115 ++--- arch/arm/include/asm/emif.h | 9 ++ arch/arm/include/asm/omap_common.h | 7 ++ board/ti/beagle_x15/board.c | 41 ++-- 7 files changed, 288 insertions(+), 58 deletions(-) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] net: macb: add gmac multi-queue support
This patch refer to linux kernel commit: d8b763e1e79f
net/macb: add TX multiqueue support for gem
by: Cyrille Pitchen
1. macb driver will check the register to find how many queues support for
this chip.
2. Then as we only use queue0 for tx, so we will set up all other queues
use a dummy descriptor, which USED bit is set. So those queues are not used.
Signed-off-by: Josh Wu
---
drivers/net/macb.c | 33 +
drivers/net/macb.h | 9 +
2 files changed, 42 insertions(+)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index f949161..a5c1880 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -54,6 +54,7 @@ struct macb_dma_desc {
#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
#define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
#define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
+#define MACB_TX_DUMMY_DMA_DESC_SIZE(DMA_DESC_BYTES(1))
#define RXADDR_USED0x0001
#define RXADDR_WRAP0x0002
@@ -93,6 +94,9 @@ struct macb_device {
unsigned long rx_ring_dma;
unsigned long tx_ring_dma;
+ struct macb_dma_desc*dummy_desc;
+ unsigned long dummy_desc_dma;
+
const struct device *dev;
struct eth_device netdev;
unsigned short phy_addr;
@@ -525,6 +529,30 @@ static int macb_phy_init(struct macb_device *macb)
return 1;
}
+static int gmac_init_multi_queues(struct macb_device *macb)
+{
+ int i, num_queues = 1;
+ u32 queue_mask;
+
+ /* bit 0 is never set but queue 0 always exists */
+ queue_mask = gem_readl(macb, DCFG6) & 0xff;
+ queue_mask |= 0x1;
+
+ for (i = 1; i < MACB_MAX_QUEUES; i++)
+ if (queue_mask & (1 << i))
+ num_queues++;
+
+ macb->dummy_desc->ctrl = TXBUF_USED;
+ macb->dummy_desc->addr = 0;
+ flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
+ MACB_TX_DUMMY_DMA_DESC_SIZE);
+
+ for (i = 1; i < num_queues; i++)
+ gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1);
+
+ return 0;
+}
+
static int macb_init(struct eth_device *netdev, bd_t *bd)
{
struct macb_device *macb = to_macb(netdev);
@@ -565,6 +593,9 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
macb_writel(macb, TBQP, macb->tx_ring_dma);
if (macb_is_gem(macb)) {
+ /* Check the multi queue and initialize the queue for tx */
+ gmac_init_multi_queues(macb);
+
/*
* When the GMAC IP with GE feature, this bit is used to
* select interface between RGMII and GMII.
@@ -712,6 +743,8 @@ int macb_eth_initialize(int id, void *regs, unsigned int
phy_addr)
&macb->rx_ring_dma);
macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
&macb->tx_ring_dma);
+ macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
+ &macb->dummy_desc_dma);
/* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
diff --git a/drivers/net/macb.h b/drivers/net/macb.h
index 06f7c66..5bb48f4 100644
--- a/drivers/net/macb.h
+++ b/drivers/net/macb.h
@@ -60,6 +60,13 @@
/* GEM specific register offsets */
#define GEM_DCFG1 0x0280
+#define GEM_DCFG6 0x0294
+
+#define MACB_MAX_QUEUES8
+
+/* GEM specific multi queues register offset */
+/* hw_q can be 0~7 */
+#define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
/* Bitfields in NCR */
#define MACB_LB_OFFSET 0
@@ -309,5 +316,7 @@
readl((port)->regs + GEM_##reg)
#define gem_writel(port, reg, value) \
writel((value), (port)->regs + GEM_##reg)
+#define gem_writel_queue_TBQP(port, value, queue_num) \
+ writel((value), (port)->regs + GEM_TBQP(queue_num))
#endif /* __DRIVERS_MACB_H__ */
--
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Re: [U-Boot] [PATCH] sunxi: Add new Mele_A1000G_quad defconfig
Hi, On 03-06-15 09:49, Ian Campbell wrote: On Tue, 2015-06-02 at 09:07 +0200, Hans de Goede wrote: So if there is no way to store this info in the defconfigs lets just leave it out and will point people to the wiki. Would it be totally mad to have a string CONFIG_BOARD_URL containing a URL (e.g. to the relevant wiki page) which was printed on boot i.e. in a "Board Info: http://"; type thing and/or in the help output? This started off as a thought on abusing Kconfig to somehow allow some of this info to remain, but just that would be a step too far IMHO, but if it also serves a (somewhat) practical purpose, then, maybe? (I'm not convinced myself, but thought I'd mention it). Interesting idea, I would not be against this, either at a global or at a sunxi level, Tom ? Regards, Hans ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] sunxi: Add new Mele_A1000G_quad defconfig
On Tue, 2015-06-02 at 09:07 +0200, Hans de Goede wrote: > So if there is no way to store this info in the defconfigs lets > just leave it out and will point people to the wiki. Would it be totally mad to have a string CONFIG_BOARD_URL containing a URL (e.g. to the relevant wiki page) which was printed on boot i.e. in a "Board Info: http://"; type thing and/or in the help output? This started off as a thought on abusing Kconfig to somehow allow some of this info to remain, but just that would be a step too far IMHO, but if it also serves a (somewhat) practical purpose, then, maybe? (I'm not convinced myself, but thought I'd mention it). Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] sunxi: gpio: Add "allwinner, sun8i-a33-pinctrl"
On Tue, 2015-06-02 at 22:10 +0200, Hans de Goede wrote: > Add "allwinner,sun8i-a33-pinctrl", this is used by the latest upstream > linux sunxi dts files. > > Signed-off-by: Hans de Goede All four: Acked-by: Ian Campbell ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/4] sunxi: Add a proper dts file for the ga10h a33 based tablet
Hi,
On 02-06-15 22:10, Hans de Goede wrote:
Add and use a proper dts for the ga10h a33 based tablet, as
submitted upstream.
Note this just got accepted upstream.
Regards,
Hans
Signed-off-by: Hans de Goede
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/sun8i-a33-ga10h-v1.1.dts | 142 ++
configs/ga10h_v1_1_defconfig | 2 +-
3 files changed, 144 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/sun8i-a33-ga10h-v1.1.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 501fe77..7c9043f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -127,6 +127,7 @@ dtb-$(CONFIG_MACH_SUN8I_A23) += \
sun8i-a23-ippo-q8h-v1.2.dtb
dtb-$(CONFIG_MACH_SUN8I_A33) += \
sun8i-a33-et-q8-v1.6.dtb \
+ sun8i-a33-ga10h-v1.1.dtb \
sun8i-a33-ippo-q8h-v1.2-lcd1024x600.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
diff --git a/arch/arm/dts/sun8i-a33-ga10h-v1.1.dts
b/arch/arm/dts/sun8i-a33-ga10h-v1.1.dts
new file mode 100644
index 000..1aefc67
--- /dev/null
+++ b/arch/arm/dts/sun8i-a33-ga10h-v1.1.dts
@@ -0,0 +1,142 @@
+/*
+ * Copyright 2015 Hans de Goede
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a33.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include
+#include
+#include
+
+/ {
+ model = "Allwinner GA10H Quad Core Tablet (v1.1)";
+ compatible = "allwinner,ga10h-v1.1", "allwinner,sun8i-a33";
+
+ aliases {
+ serial0 = &r_uart;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&lradc {
+ vref-supply = <®_vcc3v0>;
+ status = "okay";
+
+ button@200 {
+ label = "Volume Up";
+ linux,code = ;
+ channel = <0>;
+ voltage = <20>;
+ };
+
+ button@400 {
+ label = "Volume Down";
+ linux,code = ;
+ channel = <0>;
+ voltage = <40>;
+ };
+
+ button@600 {
+ label = "Back";
+ linux,code = ;
+ channel = <0>;
+ voltage = <60>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8h>;
+ vmmc-supply = <®_vcc3v0>;
+ bus-width = <4>;
+ cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&pio {
+ mmc0_cd_pin_q8h: mmc0_cd_pin@0 {
+ allwinner,pins = "PB4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = ;
+ allwinner,pull = ;
+ };
+};
+
+&r_uart {
+ pinctrl-names =
Re: [U-Boot] [PATCH 2/2] Revert "break build if it would produce broken binary"
On Tue 2015-06-02 13:13:05, Tom Rini wrote: > On Tue, Jun 02, 2015 at 11:08:21AM -0600, Simon Glass wrote: > > > The root cause of this problem should now be fixed. > > > > This reverts commit a6a4c542d316b3401f0840ac5378743191bca851. > > Signed-off-by: Simon Glass > > Thanks for digging into all of this! Pavel, can you confirm that with > these two applied things work still? Thanks! For series: Acked-by: Pavel Machek Tested-by: Pavel Machek Thanks, Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
