Re: [U-Boot] [PATCH RESEND 0/7] spi: cadence_qspi: optimize & fix indirect rd-writes
Hi Vikas, On 18.06.2015 20:05, Vikas MANOCHA wrote: >> $ make -s -j10 >> Error: arch/arm/dts/socfpga.dtsi:637.5-6 syntax error FATAL ERROR: Unable >> to parse input tree >> Error: arch/arm/dts/socfpga.dtsi:637.5-6 syntax error FATAL ERROR: Unable >> to parse input tree >> make[2]: *** [arch/arm/dts/socfpga_arria5_socdk.dtb] Error 1 >> make[2]: *** Waiting for unfinished jobs >> make[2]: *** [arch/arm/dts/socfpga_cyclone5_socdk.dtb] Error 1 >> Error: arch/arm/dts/socfpga.dtsi:637.5-6 syntax error FATAL ERROR: Unable >> to parse input tree >> make[2]: *** [arch/arm/dts/socfpga_cyclone5_socrates.dtb] Error 1 >> >> The socfpga.dtsi has incorrect syntax. Here a quick fix for this - please add >> this to your next version. And please also compile-test for e.g. socrates. > > You are right, semicolon has to be replaced with comma. I will fix it > in next version & do the compile-test also. And please also take care of the correct indentation. >> >> $ gd >> diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index >> a2a2029..448870e 100644 >> --- a/arch/arm/dts/socfpga.dtsi >> +++ b/arch/arm/dts/socfpga.dtsi >> @@ -633,8 +633,8 @@ >> #address-cells = <1>; >> #size-cells = <0>; >> reg = <0xff705000 0x1000>, >> - <0xffa0 0x1000>; >> - <0x 0x0010>; >> + <0xffa0 0x1000>, >> + <0x 0x0010>; >> interrupts = <0 151 4>; >> clocks = <&qspi_clk>; >> ext-decoder = <0>; /* external decoder */ >> >> >> Okay. After installing the resulting image on the SoCrates, I get the >> following >> error while reading from SD-card: >> >> => sf probe >> SF: Detected N25Q256 with page size 256 Bytes, erase size 4 KiB, total 32 MiB >> SF: Warning - Only lower 16MiB accessible, Full access #define >> CONFIG_SPI_FLASH_BAR => sf read 10 0 10 >> QSPI: indirect completion status error with reg 0x000c >> SF: 1048576 bytes @ 0x0 Read: ERROR >> >> So there seems to be something breaking the SoCFPGA Cadence QSPI >> support. Any idea whats going wrong here? > > It means indirect read was not successful. Can you please: > > - please check if "sf write" is also causing some error or is working > fine. Same error. > - git bisect or cherry-pick to find out which patch is breaking the > read functionality. This one is the first introducing this breakage: spi: cadence_qspi: fix base trigger address & transfer start address Here the output from the complete patchset with DEBUG enabled: => sf probe cadence_spi_ofdata_to_platdata: regbase=ff705000 flashbase=ffa0 trigger_base= max-frequency=50 page-size=256 cadence_qspi_apb_config_baudrate_div: ref_clk 4Hz sclk 100Hz Div 0xf cadence_qspi_apb_config_baudrate_div: ref_clk 4Hz sclk 100Hz Div 0xf cadence_qspi_apb_config_baudrate_div: ref_clk 4Hz sclk 50Hz Div 0xf SF: Read data capture delay calibrated to 7 (0 - 15) cadence_spi_set_speed: speed=100 cadence_spi_xfer: len=1 [bytes] cadence_qspi_apb_chipselect : chipselect 0 decode 0 cadence_spi_xfer: len=5 [bytes] cadence_qspi_apb_chipselect : chipselect 0 decode 0 SF: Detected N25Q256 with page size 256 Bytes, erase size 4 KiB, total 32 MiB SF: Warning - Only lower 16MiB accessible, Full access #define CONFIG_SPI_FLASH_BAR cadence_qspi_apb_config_baudrate_div: ref_clk 4Hz sclk 100Hz Div 0xf cadence_spi_set_speed: speed=100 => sf read 20 10 1 cadence_spi_xfer: len=5 [bytes] cadence_qspi_apb_chipselect : chipselect 0 decode 0 cadence_spi_xfer: len=65536 [bytes] cadence_qspi_apb_chipselect : chipselect 0 decode 0 QSPI: indirect completion status error with reg 0x000c SF: 65536 bytes @ 0x10 Read: ERROR HTP. Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 12/15] x86: Generate a valid MultiProcessor (MP) table
On Thu, Jun 18, 2015 at 4:17 PM, Bin Meng wrote:
> Implement write_mp_table() to create a minimal working MP table.
> This includes an MP floating table, a configuration table header
> and all of the 5 base configuration table entries. The I/O interrupt
> assignment table entry is created based on the same information used
> in the creation of PIRQ routing table from device tree. A check
> duplicated entry logic is applied to prevent writing multiple I/O
> interrupt entries with the same information.
>
> Use a Kconfig option GENERATE_MP_TABLE to tell U-Boot whether we
> need actually write the MP table at the F seg, just like we did for
> PIRQ routing and SFI tables. With MP table existence, linux kernel
> will switch to I/O APIC and local APIC to process all the peripheral
> interrupts instead of 8259 PICs. This takes full advantage of the
> multicore hardware and the SMP kernel.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - Avoid using u16 and u8 in parameters
> - Add a comment block for check_dup_entry()
> - Return and check error codes of mptable_add_intsrc()
> - Remove __weak for write_mp_table()
>
[snip]
> +u32 write_mp_table(u32 addr)
> +{
> + struct mp_config_table *mc;
> + int ioapic_id, ioapic_ver;
> + int bus_isa = 0xff;
> + int ret;
> + u32 end;
> +
> + /* 16 byte align the table address */
> + addr = ALIGN(addr, 16);
> +
> + /* Write floating table */
> + mc = mp_write_floating_table((struct mp_floating_table *)addr);
> +
> + /* Write configuration table header */
> + mp_config_table_init(mc);
> +
> + /* Write processor entry */
> + mp_write_processor(mc);
> +
> + /* Write bus entry */
> + mp_write_bus(mc, bus_isa, BUSTYPE_ISA);
> +
> + /* Write I/O APIC entry */
> + ioapic_id = io_apic_read(IO_APIC_ID) >> 24;
> + ioapic_ver = io_apic_read(IO_APIC_VER) & 0xff;
> + mp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
> +
> + /* Write I/O interrupt assignment entry */
> + ret = mptable_add_intsrc(mc, bus_isa, ioapic_id);
> + if (!ret)
Sorry, the logic is wrong here. Should be if (ret)
> + debug("Failed to write I/O interrupt assignment table\n");
> +
> + /* Write local interrupt assignment entry */
> + mptable_add_lintsrc(mc, bus_isa);
> +
> + /* Finalize the MP table */
> + end = mptable_finalize(mc);
> +
> + return end;
> +}
[snip]
Regards,
Bin
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Re: [U-Boot] MinnowBoard Max uboot
Hi Tom, On Thu, Jun 18, 2015 at 9:07 PM, Beaman, Thomas wrote: > Hi Bin, > > After adding CONFIG_SFI=y to the kernel config, I was able to see both CPUs > in the kernel boot, but now the kernel hangs at boot time. It did not hang > when CONFIG_SFI was not set. and if I boot the CONFIG_SFI=y kernel using EFI > BIOS it does not hang either. I have repeated the test a few times with the > same results each time. I have enclosed the kernel boot log if you can see > anything, or have any more suggestions. > > Thanks, > Tom > > *** kernel bootlog * > > U-Boot 2015.07-rc2 (Jun 10 2015 - 09:48:35 -0400) > gcc (GCC) 4.8.3 20140911 (Red Hat 4.8.3-9) > GNU ld version 2.23.52.0.1-16.el7 20130226 > > bootargs= root=/dev/ram rw ramdisk_size=30 console=ttyS0,115200 Can you try typing 'run ramboot' on the U-Boot shell to load linux kernel? Or below ... > Using RTL8169#0 device > TFTP from server 10.40.101.102; our IP address is 10.40.101.212 > Filename 'atom_64/kernel'. > Load address: 0x1000 > Loading: ## 5.6 MiB > 3.6 MiB/s > done > Bytes transferred = 5861312 (596fc0 hex) > Using RTL8169#0 device > TFTP from server 10.40.101.102; our IP address is 10.40.101.212 > Filename 'atom_64/ramdisk'. > Load address: 0x2000 > Loading: ## 29.1 MiB > 3.6 MiB/s > done > Bytes transferred = 30497951 (1d15c9f hex) > Valid Boot Flag > Setup Size = 0x3e00 > Magic signature found > Using boot protocol version 2.0c > Linux kernel version 3.10.62-ltsi-WR6.0.0.20_standard (tbeaman@wocket) #1 SMP > PREEMPT Wed Jun 17 15:19:47 EDT 2015 > Building boot_params at 0x0009 > Loading bzImage at address 10 (5845440 bytes) > Magic signature found > Initial RAM disk at linear address 0x2000, size 67108864 bytes > Kernel command line: " root=/dev/ram rw ramdisk_size=30 > console=ttyS0,115200" Or append acpi=off to the kernel command line manually, to see how it goes. [snip] Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Fix default env includes to fix sandbox build
On Wed, Jun 17, 2015 at 04:58:32PM +0100, Peter Robinson wrote: > defconfig and sandbox fails to build due to a with with the following error: > > error: expected '}' before > 'BOOT_TARGET_DEVICES_references_HOST_without_CONFIG_SANDBOX' > CONFIG_EXTRA_ENV_SETTINGS > > Based on the responaes below to the thread add linux/kconfig.h higher in th > includes > and drop the now unneeded autoconf.h lower down to ensure the default > environment is > included correctly > > http://lists.denx.de/pipermail/u-boot/2015-June/216849.html > > Signed-off-by: Peter Robinson Reworded the commit message and applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] board/BuR/tseries: remove lpj= from environment-variable
On Thu, Jun 11, 2015 at 12:31:54PM +0200, Hannes Petermaier wrote: > since we have now various processor-speeds it isn't useful anymore to > preinitialize kernels-delay loop. > > Rather we want the kernel to calibrate it on every boot. > This wastes around 80ms boottime but is compatible to all CPU-speeds. > > Signed-off-by: Hannes Schmelzer Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] board/BuR/common: support timer5 for pwm-backlight
On Thu, Jun 11, 2015 at 12:25:43PM +0200, Hannes Petermaier wrote: > in future we support yet another b&r am335x based board, where Timer 5 is > wired to backlight-driver. > > So we introduce a new driver-type '2' to setup timer5 instead timer6. > > Signed-off-by: Hannes Schmelzer > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] fix: samsung: common: autoboot.cmd: Correct itbcfg definition
On Wed, Jun 17, 2015 at 12:49:23PM +0200, Łukasz Majewski wrote: > This fix is necessary to avoid booting the default ITB configuration. > > Signed-off-by: Lukasz Majewski Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] mmc_write.c: Make mmc_berase do 32bit safe 64bit math
On Thu, Jun 11, 2015 at 08:53:31PM -0400, Tom Rini wrote: > We want to see if the requested start or total block count are > unaligned. We discard the whole numbers and only care about the > remainder. Update the code to use div_u64_rem here and add a comment. > > Cc: Hans de Goede > Cc: Pantelis Antoniou > Cc: Bernhard Nortmann > Reported-by: Simon Glass > Signed-off-by: Tom Rini > Tested-by: Bernhard Nortmann > Reviewed-by: Hans de Goede Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ti: am335x/am437x/omap5 devices: Fix breakage when CONFIG_CMD_NET is not used
On Wed, Jun 10, 2015 at 08:54:02AM -0500, Cooper Jr., Franklin wrote: > Currently there is no default value for NETARGS if CONFIG_CMD_NET=y isn't set. > This results in build errors which was first discovered when trying to run > make env. > > By defining a blank NETARGS these errors can be avoided. > > Signed-off-by: Franklin S Cooper Jr > Tested-by: Maxin B. John > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] spl: spl_mmc: Minor cosmetics
On Wed, Jun 03, 2015 at 06:48:51PM +0200, Paul Kocialkowski wrote: > This switches some printf calls to puts and avoids a test repetition. > > Signed-off-by: Paul Kocialkowski Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] CPCI4052: Remove CONFIG_SYS_LONGHELP
On Tue, Jun 02, 2015 at 11:12:20AM -0400, Tom Rini wrote: > With the change to make sure that CONFIG_CMD_NET is enabled this board > no longer fits into the linker script: > > powerpc-linux-ld.bfd: section .resetvec loaded at [fffc,] > overlaps section .u_boot_list loaded at [ff58,0723] > powerpc-linux-ld.bfd: u-boot: section .resetvec lma 0xfffc adjusted to > 0x724 > powerpc-linux-ld.bfd: u-boot: section `.resetvec' can't be allocated in > segment 0 > LOAD: .data.init .text .rodata .reloc .data .u_boot_list .resetvec > powerpc-linux-ld.bfd: final link failed: File truncated > > Drop CONFIG_SYS_LONGHELP to free up space. > > Cc: Matthias Fuchs > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 2/2] spl: spl_mmc: MMC boot mode provisions checks
On Mon, Jun 08, 2015 at 11:05:09PM +0200, Paul Kocialkowski wrote: > This allows using only one of either raw or fs mode for SPL mmc boot, without > the need to have provisions for the other. In particular, a device may have > U-Boot installed on a file system on the mmc, without ever needing to read > U-Boot from raw memory. Thus, there is no reason to provide a sector or > partition for raw mode. This allows this behaviour and still provides a robust > fallback mechanism in case provisions for both modes are defined. > > Signed-off-by: Paul Kocialkowski Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 3/3] boards: tam3517-common: enable gpmc prefetch mode
On Sat, May 30, 2015 at 10:11:25AM +0200, Jeroen Hofstee wrote: > Since the tam3517 base board has a 16bit wide nand connected to > the gpmc, enable the prefetch mode, since that is now supported. > > Cc: Scott Wood > Cc: Tom Rini > Cc: pekon gupta > Cc: Nishanth Menon > Cc: Daniel Mack > Cc: Tapani Utriainen > > Signed-off-by: Jeroen Hofstee > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 2/3] mtd: OMAP: Enable GPMC prefetch mode for 16 bit access
On Sat, May 30, 2015 at 10:11:24AM +0200, Jeroen Hofstee wrote: > commit c316f57 "mtd: OMAP: Enable GPMC prefetch mode" only enabled > prefetch mode for 8 bit nand access, this adds 16 bit as well. > > Cc: Scott Wood > Cc: Tom Rini > Cc: Daniel Mack > > Signed-off-by: Jeroen Hofstee > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-sunxi master
On Thu, Jun 18, 2015 at 12:01:58PM +0200, Hans de Goede wrote: > Hi Tom, > > Please pull u-boot-sunxi/master into master for a few small fixes. > > The following changes since commit 0d3f732fd2ba679b4498541f075d1b1bdbea3935: > > Merge git://git.denx.de/u-boot-usb (2015-06-15 20:45:50 -0400) > > are available in the git repository at: > > http://git.denx.de/u-boot-sunxi.git master > > for you to fetch changes up to 24e741269605ff7f073e83294852dd16edcd22c0: > > MSI_Primo81_defconfig: enable USB OTG port and keyboard support (2015-06-17 > 15:31:20 +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 1/3] omap_gpmc: move prefetch out of CONFIG_NAND_OMAP_ELM
On Sat, May 30, 2015 at 10:11:23AM +0200, Jeroen Hofstee wrote: > The prefech mode is a feature of the gpmc, not the ELM. An am3517 > does not have an elm, but can do prefeches, so move the code out > of the CONFIG_NAND_OMAP_ELM ifdef. > > Cc: Scott Wood > Cc: Tom Rini > Cc: Daniel Mack > > Signed-off-by: Jeroen Hofstee > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: cache-cp15: Make sure EAE is not enabled
Hello,
any news on this one?
Thanks,
Tomeu
On 30 April 2015 at 09:23, Sjoerd Simons wrote:
> +Albert, +Marek,
>
> On Tue, 2015-04-28 at 14:21 +0200, Tomeu Vizoso wrote:
>> This could happen if we are being chainloaded by Coreboot with LPAE
>> enabled, as is the case on the Tegra-based Chromebooks.
>>
>> Signed-off-by: Tomeu Vizoso
>
> From the documentation of recent ARM cores it looks like 0 is the reset
> value for that register, so explicitly ensuring it has that value seems
> sane. I'm wary of giving a reviewed-by though as i don't know that part
> of u-boot well enough to say it's the right spot.
>
> However, as we're now using successfully using a Nyan big board with
> this u-boot patch in kernelci[0] i can happily say:
>
> Tested-By: Sjoerd Simons
>
> 0: http://kernelci.org/boot/tegra124-nyan-big/
>
>
>> ---
>> arch/arm/lib/cache-cp15.c | 4
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
>> index 0291afa..78fb429 100644
>> --- a/arch/arm/lib/cache-cp15.c
>> +++ b/arch/arm/lib/cache-cp15.c
>> @@ -96,6 +96,10 @@ static inline void mmu_setup(void)
>> dram_bank_mmu_setup(i);
>> }
>>
>> + /* Make sure EAE is not enabled */
>> + asm volatile("mcr p15, 0, %0, c2, c0, 2"
>> + : : "r" (0) : "memory");
>> +
>> /* Copy the page table address to cp15 */
>> asm volatile("mcr p15, 0, %0, c2, c0, 0"
>>: : "r" (gd->arch.tlb_addr) : "memory");
>
>
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[U-Boot] [PATCH 1/2] usb: ehci: Properly deal with data toggle for interrupt endpoints
Without this we loose every other interrupt packet. We never noticed this
because with keyboards the packets which we were loosing would normally
be key release packets.
But now that we do keyrepeat in software instead of relying on the hid
idle functionality, missing a release will result in key repeat triggering.
This commit fixes this.
Signed-off-by: Hans de Goede
---
drivers/usb/host/ehci-hcd.c | 26 +++---
1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 1e5a6e2..bf02221 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -1214,6 +1214,7 @@ static int _ehci_submit_control_msg(struct usb_device
*dev, unsigned long pipe,
struct int_queue {
int elementsize;
+ unsigned long pipe;
struct QH *first;
struct QH *current;
struct QH *last;
@@ -1269,7 +1270,7 @@ static struct int_queue *_ehci_create_int_queue(struct
usb_device *dev,
{
struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
struct int_queue *result = NULL;
- int i;
+ uint32_t i, toggle;
/*
* Interrupt transfers requiring several transactions are not supported
@@ -1309,6 +1310,7 @@ static struct int_queue *_ehci_create_int_queue(struct
usb_device *dev,
goto fail1;
}
result->elementsize = elementsize;
+ result->pipe = pipe;
result->first = memalign(USB_DMA_MINALIGN,
sizeof(struct QH) * queuesize);
if (!result->first) {
@@ -1326,6 +1328,8 @@ static struct int_queue *_ehci_create_int_queue(struct
usb_device *dev,
memset(result->first, 0, sizeof(struct QH) * queuesize);
memset(result->tds, 0, sizeof(struct qTD) * queuesize);
+ toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
+
for (i = 0; i < queuesize; i++) {
struct QH *qh = result->first + i;
struct qTD *td = result->tds + i;
@@ -1357,7 +1361,9 @@ static struct int_queue *_ehci_create_int_queue(struct
usb_device *dev,
td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
debug("communication direction is '%s'\n",
usb_pipein(pipe) ? "in" : "out");
- td->qt_token = cpu_to_hc32((elementsize << 16) |
+ td->qt_token = cpu_to_hc32(
+ QT_TOKEN_DT(toggle) |
+ (elementsize << 16) |
((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */
0x80); /* active */
td->qt_buffer[0] =
@@ -1372,6 +1378,7 @@ static struct int_queue *_ehci_create_int_queue(struct
usb_device *dev,
cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff);
*buf = buffer + i * elementsize;
+ toggle ^= 1;
}
flush_dcache_range((unsigned long)buffer,
@@ -1426,6 +1433,8 @@ static void *_ehci_poll_int_queue(struct usb_device *dev,
{
struct QH *cur = queue->current;
struct qTD *cur_td;
+ uint32_t token, toggle;
+ unsigned long pipe = queue->pipe;
/* depleted queue */
if (cur == NULL) {
@@ -1436,12 +1445,15 @@ static void *_ehci_poll_int_queue(struct usb_device
*dev,
cur_td = &queue->tds[queue->current - queue->first];
invalidate_dcache_range((unsigned long)cur_td,
ALIGN_END_ADDR(struct qTD, cur_td, 1));
- if (QT_TOKEN_GET_STATUS(hc32_to_cpu(cur_td->qt_token)) &
- QT_TOKEN_STATUS_ACTIVE) {
- debug("Exit poll_int_queue with no completed intr transfer.
token is %x\n",
- hc32_to_cpu(cur_td->qt_token));
+ token = hc32_to_cpu(cur_td->qt_token);
+ if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE) {
+ debug("Exit poll_int_queue with no completed intr transfer.
token is %x\n", token);
return NULL;
}
+
+ toggle = QT_TOKEN_GET_DT(token);
+ usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), toggle);
+
if (!(cur->qh_link & QH_LINK_TERMINATE))
queue->current++;
else
@@ -1452,7 +1464,7 @@ static void *_ehci_poll_int_queue(struct usb_device *dev,
queue->elementsize));
debug("Exit poll_int_queue with completed intr transfer. token is %x at
%p (first at %p)\n",
- hc32_to_cpu(cur_td->qt_token), cur, queue->first);
+ token, cur, queue->first);
return cur->buffer;
}
--
2.4.3
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[U-Boot] [PATCH 0/2] usb: 2 keyboard fixes for v2015.07
Hi Marek, While working on enabling the musb device-model support on more sunxi boards, I noticed a problem with usb-keyboards when plugged into an usb-2 hub and thus connected via the ehci code. In the scenario of a usb-kbd connected to an ehci controller, combined with using CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE (*), an ehci code bug triggers which causes every other usb interrupt packet to get lost due to a data toggle mismatch. We've had this bug for a long time, loosing the key release packets most of the time, which did not matter, until my recent usb-kbd keyrepeat changes. The first patch in this series fixes this, the second patch is a better safe then sorry patch I wrote while working on this. Can you please queue both of these up for merging into v2015.07 ? Thanks & Regards, Hans *) Which AFAIK sofar is only used by sunxi... ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] usb: kbd: Disable idle input reports when we do not need them
When we're polling and thus handling key-repeat in software, make sure
to disable idle reports, some keyboards may have these enabled by default
messing up our software keyrepeat.
Signed-off-by: Hans de Goede
---
common/usb_kbd.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index 49bfc09..e2af67d 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -460,10 +460,12 @@ static int usb_kbd_probe(struct usb_device *dev, unsigned
int ifnum)
/* We found a USB Keyboard, install it. */
usb_set_protocol(dev, iface->desc.bInterfaceNumber, 0);
+ debug("USB KBD: found set idle...\n");
#if !defined(CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP) && \
!defined(CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE)
- debug("USB KBD: found set idle...\n");
usb_set_idle(dev, iface->desc.bInterfaceNumber, REPEAT_RATE / 4, 0);
+#else
+ usb_set_idle(dev, iface->desc.bInterfaceNumber, 0, 0);
#endif
debug("USB KBD: enable interrupt pipe...\n");
--
2.4.3
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Re: [U-Boot] [PATCH RESEND 0/7] spi: cadence_qspi: optimize & fix indirect rd-writes
Thanks Stefan, > -Original Message- > From: Stefan Roese [mailto:s...@denx.de] > Sent: Thursday, June 18, 2015 5:02 AM > To: Vikas MANOCHA > Cc: u-boot@lists.denx.de; grmo...@opensource.altera.com; > dingu...@opensource.altera.com; jt...@openedev.com > Subject: Re: [PATCH RESEND 0/7] spi: cadence_qspi: optimize & fix indirect > rd-writes > > Hi Vikas, > > I finally got to testing your latest patchset. And have some comments / > problems: > > On 17.06.2015 04:14, Vikas Manocha wrote: > > This patchset: > > - removes sram polling while reading/writing from flash. > > - fixes trigger base & transfer start address register programming. > > This fix superseeds the previous patch "spi: cadence_qspi: Fix the > > indirect ahb trigger address setting" > > - adds support to get fifo width from device tree > > > > Vikas Manocha (7): > >spi: cadence_qspi: remove sram polling from flash read > >spi: cadence_qspi: read can be independent of fifo width > >spi: cadence_qspi: remove sram polling from flash write > >spi: cadence_qspi: move trigger base configuration in init > >spi: cadence_qspi: fix indirect read/write start address > >spi: cadence_qspi: fix base trigger address & transfer start address > >spi: cadence_qspi: get fifo width from device tree > > > > arch/arm/dts/socfpga.dtsi |2 + > > arch/arm/dts/stv0991.dts |4 +- > > drivers/spi/cadence_qspi.c | 14 ++-- > > drivers/spi/cadence_qspi.h |6 +- > > drivers/spi/cadence_qspi_apb.c | 140 > > ++--- > --- > > 5 files changed, 50 insertions(+), 116 deletions(-) > > With these patches applied, I see this compilation error: > > $ make -s -j10 > Error: arch/arm/dts/socfpga.dtsi:637.5-6 syntax error FATAL ERROR: Unable > to parse input tree > Error: arch/arm/dts/socfpga.dtsi:637.5-6 syntax error FATAL ERROR: Unable > to parse input tree > make[2]: *** [arch/arm/dts/socfpga_arria5_socdk.dtb] Error 1 > make[2]: *** Waiting for unfinished jobs > make[2]: *** [arch/arm/dts/socfpga_cyclone5_socdk.dtb] Error 1 > Error: arch/arm/dts/socfpga.dtsi:637.5-6 syntax error FATAL ERROR: Unable > to parse input tree > make[2]: *** [arch/arm/dts/socfpga_cyclone5_socrates.dtb] Error 1 > > The socfpga.dtsi has incorrect syntax. Here a quick fix for this - please add > this to your next version. And please also compile-test for e.g. socrates. You are right, semicolon has to be replaced with comma. I will fix it in next version & do the compile-test also. > > $ gd > diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index > a2a2029..448870e 100644 > --- a/arch/arm/dts/socfpga.dtsi > +++ b/arch/arm/dts/socfpga.dtsi > @@ -633,8 +633,8 @@ > #address-cells = <1>; > #size-cells = <0>; > reg = <0xff705000 0x1000>, > - <0xffa0 0x1000>; > - <0x 0x0010>; > + <0xffa0 0x1000>, > + <0x 0x0010>; > interrupts = <0 151 4>; > clocks = <&qspi_clk>; > ext-decoder = <0>; /* external decoder */ > > > Okay. After installing the resulting image on the SoCrates, I get the > following > error while reading from SD-card: > > => sf probe > SF: Detected N25Q256 with page size 256 Bytes, erase size 4 KiB, total 32 MiB > SF: Warning - Only lower 16MiB accessible, Full access #define > CONFIG_SPI_FLASH_BAR => sf read 10 0 10 > QSPI: indirect completion status error with reg 0x000c > SF: 1048576 bytes @ 0x0 Read: ERROR > > So there seems to be something breaking the SoCFPGA Cadence QSPI > support. Any idea whats going wrong here? It means indirect read was not successful. Can you please: - please check if "sf write" is also causing some error or is working fine. - git bisect or cherry-pick to find out which patch is breaking the read functionality. Rgds, Vikas > > Thanks, > Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] keystone2: use detected ddr3a size
On Mon, Jun 15, 2015 at 12:42:49PM -0400, Vitaly Andrianov wrote:
>
>
> On 06/15/2015 10:17 AM, Tom Rini wrote:
> >On Mon, Jun 15, 2015 at 08:48:01AM -0400, Vitaly Andrianov wrote:
> >
> >>KS2 u-boot detects the ddr3a size installed to EVM. The detected size can
> >>be used instead of environment variable. Because the ddr3 configuration is
> >>done before relocation we cannot use a global variable to pass the
> >>ddr3_size to ft_board_setup(). Instead we have to use the global data
> >>structure.
> >>
> >>Because KS2 u-boot works in 32 bit address space the existing ram_size
> >>global data filed cannot be used. The maximum, which the get_ram_size()
> >>can detect is 2GB only. This patch creates the ddr3_size filed in the
> >>arch_global_data structure, which is used for that purpose.
> >>
> >>Signed-off-by: Vitaly Andrianov
> >
> >So we've got a few possibilities here, yes? Since we have the ability
> >to change the DDR modules on the board and read the sizes in the SPD
> >information U-Boot is the place where the board can find out if we have
> >say 1GB or 2GB of memory and thus has to be the one to correctly
> >populate the device tree. So the "fix" that we're talking about for
> >Calxeda can't be applied here.
> >
> >But this also brings up http://patchwork.ozlabs.org/patch/281094/ (and
> >the follow-up of http://patchwork.ozlabs.org/patch/291219/ and
> >http://patchwork.ozlabs.org/patch/291247/) where no, we have a problem
> >that we need to fix.
> >
> Hi Tom,
>
> If I understand correctly the patches above are about changing long
> to unsigned long to accommodate possible 2GB of DDR size. Or to use
> phys_addr_t for 64bit architecture. Did I miss something?
No, but that is part of your actual problem. You have 2GB of DDR (or
more in some cases) that you want to report.
> The problem with KS2 platforms is that it is a 32 bit architecture
> which uses LPAE. So, the EVMs may have more than 2GB memory
> (typically 4 or 8 GB), but u-boot sees only 2GB maximum. That is
> what get_ram_size() can detect.
Right. So you're in the same problem area as the highbank board (and
some Tegra boards too I think).
> Also it is not always possible to use SPD data to detect the DDR
> size because not all EVMs use SODIMM. Some of them use DDR3 chips
> populated to the main board.
Right. But on the ones you added support for the SPD data to, you do,
right?
> Even if we uses SPD data, we detect the DDR3 size before relocation.
> So, I believe, instead of reading the SPD EEPROM and calculate the
> size again, it is easier just to pass the ddr3 size through the
> global_data.
Well we need to do something, certainly. The problem is that we need to
populate the device tree for the kernel with the correct amount of
memory. Today we have a system that essentially forces what we have
stored today in gd to be what we populate. This is wrong in the LPAE
case. In the case of highbank, something else has already correctly
populated the DT with the memory sizes and a patch has been made to say
"lets just set CONFIG_NR_DRAM_BANKS to 0 so we can avoid that 'fixup'".
This won't help Keystone as U-Boot is where we somehow know how much
memory there really is.
Today, a bit further down in board/ti/ks2_evm/board.c than this patch
shows you play some games to correct the DT node. And part of the
problem is that if we add "ddr3_size" to just the keystone DT we've made
a very specific work-around for this general problem. You're still
having to play games to know that you shoved a >32bit value into a 32bit
variable.
So yes, I think you need to structure the code such that you can call a
function to read the SPD information and see how big your memory is, and
then go poke arch/arm/lib/bootm-fdt.c::arch_fixup_fdt() to be something
like:
__weak void board_calc_memory_size(u64 *start, u64 *end)
{
.. current for-loop
}
int arch_fixup_fdt(void *blob)
{
board_calc_memory_size(&start, &end);
fdt_fixup_memory_banks(...);
...
}
And then have keystone fill in a board_calc_memory_size() and even
populate the real # of banks and such if you want.
--
Tom
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Re: [U-Boot] [PATCH v3 4/4] arm: ls102xa: Enable Driver Model SPI for ls1021atwr
Hi Jagan, On 18 June 2015 at 00:54, Jagan Teki wrote: > On 18 June 2015 at 07:50, Wang Haikun wrote: >> On 6/17/2015 8:30 PM, Simon Glass wrote: >>> Hi, >>> >>> On 17 June 2015 at 03:36, Bin Meng wrote: Hi Haikun, On Mon, May 18, 2015 at 9:25 PM, Haikun Wang wrote: > From: Haikun Wang > > Enable Driver Model SPI for ls1021atwr board. > DSPI and QSPI only be enabled when boot from QSPI. > DSPI and QSPI are compatible under Driver Model SPI. > > Signed-off-by: Haikun Wang > Change-Id: I6342807da7725ae8b678952117c8758c75a61d3d > Reviewed-on: http://git.am.freescale.net:8181/33447> >> Best regards, >> Wang Haikun >>> Is this URL Freescale internal? I cannot access it. >>> >>> Looks like it. BTW patman will remove these Gerrit tags automatically. >> Yes, it is our internal URL. >> I forget to remove it. >> It couldn't be better if it will be removed automatically. > > I will remove if something not remove automatically. > > Anyone have any comments on these patch-set, I'm planning to take these. > > https://patchwork.ozlabs.org/patch/473391/ > https://patchwork.ozlabs.org/patch/473392/ > https://patchwork.ozlabs.org/patch/473393/ > https://patchwork.ozlabs.org/patch/473394/ > I already reviewed the first two and they seem good to me. [snip] Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: cache-cp15: Make sure EAE is not enabled
Hi,
On 18 June 2015 at 01:19, Tomeu Vizoso wrote:
>
> Hello,
>
> any news on this one?
>
> Thanks,
>
> Tomeu
>
> On 30 April 2015 at 09:23, Sjoerd Simons
> wrote:
> > +Albert, +Marek,
> >
> > On Tue, 2015-04-28 at 14:21 +0200, Tomeu Vizoso wrote:
> >> This could happen if we are being chainloaded by Coreboot with LPAE
> >> enabled, as is the case on the Tegra-based Chromebooks.
> >>
> >> Signed-off-by: Tomeu Vizoso
> >
> > From the documentation of recent ARM cores it looks like 0 is the reset
> > value for that register, so explicitly ensuring it has that value seems
> > sane. I'm wary of giving a reviewed-by though as i don't know that part
> > of u-boot well enough to say it's the right spot.
> >
> > However, as we're now using successfully using a Nyan big board with
> > this u-boot patch in kernelci[0] i can happily say:
> >
> > Tested-By: Sjoerd Simons
> >
> > 0: http://kernelci.org/boot/tegra124-nyan-big/
> >
> >
> >> ---
> >> arch/arm/lib/cache-cp15.c | 4
> >> 1 file changed, 4 insertions(+)
> >>
> >> diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
> >> index 0291afa..78fb429 100644
> >> --- a/arch/arm/lib/cache-cp15.c
> >> +++ b/arch/arm/lib/cache-cp15.c
> >> @@ -96,6 +96,10 @@ static inline void mmu_setup(void)
> >> dram_bank_mmu_setup(i);
> >> }
> >>
> >> + /* Make sure EAE is not enabled */
> >> + asm volatile("mcr p15, 0, %0, c2, c0, 2"
> >> + : : "r" (0) : "memory");
> >> +
> >> /* Copy the page table address to cp15 */
> >> asm volatile("mcr p15, 0, %0, c2, c0, 0"
> >>: : "r" (gd->arch.tlb_addr) : "memory");
Does this apply to all ARM cores? Should it have #ifdef CONFIG_ARMV7 or similar?
Regards,
Simon
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Re: [U-Boot] MinnowBoard Max uboot
Hi Bin, After adding CONFIG_SFI=y to the kernel config, I was able to see both CPUs in the kernel boot, but now the kernel hangs at boot time. It did not hang when CONFIG_SFI was not set. and if I boot the CONFIG_SFI=y kernel using EFI BIOS it does not hang either. I have repeated the test a few times with the same results each time. I have enclosed the kernel boot log if you can see anything, or have any more suggestions. Thanks, Tom *** kernel bootlog * U-Boot 2015.07-rc2 (Jun 10 2015 - 09:48:35 -0400) gcc (GCC) 4.8.3 20140911 (Red Hat 4.8.3-9) GNU ld version 2.23.52.0.1-16.el7 20130226 bootargs= root=/dev/ram rw ramdisk_size=30 console=ttyS0,115200 Using RTL8169#0 device TFTP from server 10.40.101.102; our IP address is 10.40.101.212 Filename 'atom_64/kernel'. Load address: 0x1000 Loading: ## 5.6 MiB 3.6 MiB/s done Bytes transferred = 5861312 (596fc0 hex) Using RTL8169#0 device TFTP from server 10.40.101.102; our IP address is 10.40.101.212 Filename 'atom_64/ramdisk'. Load address: 0x2000 Loading: ## 29.1 MiB 3.6 MiB/s done Bytes transferred = 30497951 (1d15c9f hex) Valid Boot Flag Setup Size = 0x3e00 Magic signature found Using boot protocol version 2.0c Linux kernel version 3.10.62-ltsi-WR6.0.0.20_standard (tbeaman@wocket) #1 SMP PREEMPT Wed Jun 17 15:19:47 EDT 2015 Building boot_params at 0x0009 Loading bzImage at address 10 (5845440 bytes) Magic signature found Initial RAM disk at linear address 0x2000, size 67108864 bytes Kernel command line: " root=/dev/ram rw ramdisk_size=30 console=ttyS0,115200" Starting kernel ... Timer summary in microseconds: MarkElapsed Stage 0 0 reset 107,427107,427 board_init_r 1,946,048 1,838,621 id=64 1,948,082 2,034 id=65 1,954,410 6,328 main_loop 7,960,693 6,006,283 id=80 7,960,695 2 eth_start 7,960,825130 bootp_start 8,947,233986,408 bootp_stop 8,947,240 7 id=81 8,947,376136 id=82 8,967,941 20,565 tftp_start 10,541,240 1,573,299 id=84 10,541,242 2 tftp_done 18,606,478 8,065,236 start_kernel Accumulated time: 330,199 ahci 1,388,929 vesa display Initializing cgroup subsys cpuset Initializing cgroup subsys cpu Initializing cgroup subsys cpuacct Linux version 3.10.62-ltsi-WR6.0.0.20_standard (tbeaman@wocket) (gcc version 4.8.1 (Wind River Linux Sourcery CodeBench 4.8-44) ) #1 SMP PREEMPT Wed Jun 17 15:19:47 EDT 2015 Command line: root=/dev/ram rw ramdisk_size=30 console=ttyS0,115200 KERNEL supported cpus: Intel GenuineIntel AMD AuthenticAMD Centaur CentaurHauls e820: BIOS-provided physical RAM map: BIOS-e820: [mem 0x-0x0009] usable BIOS-e820: [mem 0x000a-0x000f] reserved BIOS-e820: [mem 0x0010-0x7adf] usable BIOS-e820: [mem 0x7ae0-0x7fff] reserved NX (Execute Disable) protection: active DMI not present or invalid. No AGP bridge found e820: last_pfn = 0x7ae00 max_arch_pfn = 0x4 x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106 __next_free_mem_range: Usage of MAX_NUMNODES is depricated. Use NUMA_NO_NODE instead Scanning 1 areas for low memory corruption init_memory_mapping: [mem 0x-0x000f] init_memory_mapping: [mem 0x7ac0-0x7adf] init_memory_mapping: [mem 0x7800-0x7abf] init_memory_mapping: [mem 0x0010-0x77ff] RAMDISK: [mem 0x2000-0x23ff] ACPI BIOS Bug: Error: A valid RSDP was not found (20130328/tbxfroot-218) No NUMA configuration found Faking a node at [mem 0x-0x7adf] Initmem setup node 0 [mem 0x-0x7adf] NODE_DATA [mem 0x7adfe000-0x7adf] Zone ranges: DMA [mem 0x1000-0x00ff] DMA32[mem 0x0100-0x] Normal empty Movable zone start for each node Early memory node ranges node 0: [mem 0x1000-0x0009] node 0: [mem 0x0010-0x7adf] x86/hpet: Will disable the HPET for this platform because it's not reliable SFI: Simple Firmware Interface v0.81 http://simplefirmware.org SFI: SYST F0070, 0030 (v1 U-Boot Table v1) SFI: CPUS F, 0020 (v1 U-Boot Table v1) SFI: APIC F0020, 0020 (v1 U-Boot Table v1) SFI: XSDT F0040, 0024 (v1 U-Boot Table v1) SFI: registering lapic[0] SFI: registering lapic[4] IOAPIC[0]: apic_id 0, version 32, address 0xfec0, GSI 0-86 smpboot: Allowing 2 CPUs, 0 hotplug CPUs PM: Registered nosave memory: 000a - 0010 e820: [mem 0x8000-0x] available for PCI devices setup_percpu: NR_CPUS:256 nr_cpumask_bits:256 nr_cpu_ids:2 nr_node_ids:1 PERCPU: Embedded 26 pages/cpu @88007aa0 s76352 r8192 d21952 u1048576 Built 1 zonelists in Node order, mobility grouping on. Total pages: 495313 Policy zone: DMA3
Re: [U-Boot] [PATCH 3/4] ARM: mmc: bcm283x: Remove get_timer_us() from mmc driver
On Thu, 18 Jun 2015 14:35:27 +0200, Marek Vasut wrote: > On Wednesday, June 17, 2015 at 06:13:03 PM, Jakub Kiciński wrote: > > On Wed, 17 Jun 2015 12:44:15 +0200, Marek Vasut wrote: > > > On Tuesday, June 16, 2015 at 05:44:06 AM, Stephen Warren wrote: > > > > On 05/04/2015 02:54 PM, Marek Vasut wrote: > > > > > The get_timer_us() function is something which is no longer > > > > > existing in case we use generic timer framework, so replace > > > > > it with get_timer(). > > > > > > > > Marek, > > > > > > > > This patch causes "saveenv" to got from almost no time to nearly 50s on > > > > my RPi model A+. Can you take a look at that please? > > > > > > Can you try the attached diff ? ;-/ I think I mistakenly used > > > get_timer(), which returns msecs instead of timer_get_us() which reports > > > usecs, sorry. > > > > I can confirm this solves the regression. > > That's not a regression, that was a bug ;-) Ach OK, I thought Stephen said that MMC used to be fast before the offending patch ;) Anyway I don't really know what's the difference and wikipedia says regression is a bug too so we may both be right :P ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] ARM: mmc: bcm283x: Remove get_timer_us() from mmc driver
On Wednesday, June 17, 2015 at 06:13:03 PM, Jakub Kiciński wrote: > On Wed, 17 Jun 2015 12:44:15 +0200, Marek Vasut wrote: > > On Tuesday, June 16, 2015 at 05:44:06 AM, Stephen Warren wrote: > > > On 05/04/2015 02:54 PM, Marek Vasut wrote: > > > > The get_timer_us() function is something which is no longer > > > > existing in case we use generic timer framework, so replace > > > > it with get_timer(). > > > > > > Marek, > > > > > > This patch causes "saveenv" to got from almost no time to nearly 50s on > > > my RPi model A+. Can you take a look at that please? > > > > Can you try the attached diff ? ;-/ I think I mistakenly used > > get_timer(), which returns msecs instead of timer_get_us() which reports > > usecs, sorry. > > I can confirm this solves the regression. That's not a regression, that was a bug ;-) Thanks for testing :) Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Very slow fatload on bcm2835
On Wednesday, June 17, 2015 at 03:44:41 PM, Jeroen Hofstee wrote: > Hello Marek, > > -while (get_timer(bcm_host->last_write) < bcm_host->twoticks_delay) > +while (timer_get_us() < bcm_host->last_write + > bcm_host->twoticks_delay) > ; > > Can this counter / the right side of the comparison not overflow? Yes it can -- what do you suggest to make it overflow-safe in this particular case ? Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Fix default env includes to fix sandbox build
On Thu, Jun 18, 2015 at 12:51 PM, Tom Rini wrote: > On Thu, Jun 18, 2015 at 11:04:59AM +0900, Masahiro Yamada wrote: > >> Hi Peter, >> >> >> The subject "Fix default env includes to fix sandbox build" sounds >> confusing to me. >> >> I can currently build sandbox because tools/env is not built by default. >> >> We hit this problem when we do "make env" or "make tools-all". > > Yes, I'll re-word slightly when pushing. Great, thanks, Peter >> >> >> >> >> 2015-06-18 0:58 GMT+09:00 Peter Robinson : >> > defconfig and sandbox fails to build due to a with with the following >> > error: >> > >> > error: expected '}' before >> > 'BOOT_TARGET_DEVICES_references_HOST_without_CONFIG_SANDBOX' >> > CONFIG_EXTRA_ENV_SETTINGS >> > >> > Based on the responaes below to the thread add linux/kconfig.h higher in >> > th includes >> > and drop the now unneeded autoconf.h lower down to ensure the default >> > environment is >> > included correctly >> > >> > http://lists.denx.de/pipermail/u-boot/2015-June/216849.html >> > >> > Signed-off-by: Peter Robinson >> > --- >> > tools/env/fw_env.h | 3 ++- >> > 1 file changed, 2 insertions(+), 1 deletion(-) >> > >> > diff --git a/tools/env/fw_env.h b/tools/env/fw_env.h >> > index d6faf34..60c0517 100644 >> > --- a/tools/env/fw_env.h >> > +++ b/tools/env/fw_env.h >> > @@ -6,6 +6,8 @@ >> > */ >> > >> > /* Pull in the current config to define the default environment */ >> > +#include >> > + >> > #ifndef __ASSEMBLY__ >> > #define __ASSEMBLY__ /* get only #defines from config.h */ >> > #include >> > @@ -13,7 +15,6 @@ >> > #else >> > #include >> > #endif >> > -#include >> > >> > /* >> > * To build the utility with the static configuration >> > -- >> > 2.4.3 >> >> >> -- >> Best Regards >> Masahiro Yamada >> ___ >> U-Boot mailing list >> U-Boot@lists.denx.de >> http://lists.denx.de/mailman/listinfo/u-boot > > -- > Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH RESEND 0/7] spi: cadence_qspi: optimize & fix indirect rd-writes
Hi Vikas, I finally got to testing your latest patchset. And have some comments / problems: On 17.06.2015 04:14, Vikas Manocha wrote: > This patchset: > - removes sram polling while reading/writing from flash. > - fixes trigger base & transfer start address register programming. This fix > superseeds the previous patch "spi: cadence_qspi: Fix the indirect ahb trigger > address setting" > - adds support to get fifo width from device tree > > Vikas Manocha (7): >spi: cadence_qspi: remove sram polling from flash read >spi: cadence_qspi: read can be independent of fifo width >spi: cadence_qspi: remove sram polling from flash write >spi: cadence_qspi: move trigger base configuration in init >spi: cadence_qspi: fix indirect read/write start address >spi: cadence_qspi: fix base trigger address & transfer start address >spi: cadence_qspi: get fifo width from device tree > > arch/arm/dts/socfpga.dtsi |2 + > arch/arm/dts/stv0991.dts |4 +- > drivers/spi/cadence_qspi.c | 14 ++-- > drivers/spi/cadence_qspi.h |6 +- > drivers/spi/cadence_qspi_apb.c | 140 > ++-- > 5 files changed, 50 insertions(+), 116 deletions(-) With these patches applied, I see this compilation error: $ make -s -j10 Error: arch/arm/dts/socfpga.dtsi:637.5-6 syntax error FATAL ERROR: Unable to parse input tree Error: arch/arm/dts/socfpga.dtsi:637.5-6 syntax error FATAL ERROR: Unable to parse input tree make[2]: *** [arch/arm/dts/socfpga_arria5_socdk.dtb] Error 1 make[2]: *** Waiting for unfinished jobs make[2]: *** [arch/arm/dts/socfpga_cyclone5_socdk.dtb] Error 1 Error: arch/arm/dts/socfpga.dtsi:637.5-6 syntax error FATAL ERROR: Unable to parse input tree make[2]: *** [arch/arm/dts/socfpga_cyclone5_socrates.dtb] Error 1 The socfpga.dtsi has incorrect syntax. Here a quick fix for this - please add this to your next version. And please also compile-test for e.g. socrates. $ gd diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index a2a2029..448870e 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -633,8 +633,8 @@ #address-cells = <1>; #size-cells = <0>; reg = <0xff705000 0x1000>, - <0xffa0 0x1000>; - <0x 0x0010>; + <0xffa0 0x1000>, + <0x 0x0010>; interrupts = <0 151 4>; clocks = <&qspi_clk>; ext-decoder = <0>; /* external decoder */ Okay. After installing the resulting image on the SoCrates, I get the following error while reading from SD-card: => sf probe SF: Detected N25Q256 with page size 256 Bytes, erase size 4 KiB, total 32 MiB SF: Warning - Only lower 16MiB accessible, Full access #define CONFIG_SPI_FLASH_BAR => sf read 10 0 10 QSPI: indirect completion status error with reg 0x000c SF: 1048576 bytes @ 0x0 Read: ERROR So there seems to be something breaking the SoCFPGA Cadence QSPI support. Any idea whats going wrong here? Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Fix default env includes to fix sandbox build
On Thu, Jun 18, 2015 at 11:04:59AM +0900, Masahiro Yamada wrote: > Hi Peter, > > > The subject "Fix default env includes to fix sandbox build" sounds > confusing to me. > > I can currently build sandbox because tools/env is not built by default. > > We hit this problem when we do "make env" or "make tools-all". Yes, I'll re-word slightly when pushing. > > > > > 2015-06-18 0:58 GMT+09:00 Peter Robinson : > > defconfig and sandbox fails to build due to a with with the following error: > > > > error: expected '}' before > > 'BOOT_TARGET_DEVICES_references_HOST_without_CONFIG_SANDBOX' > > CONFIG_EXTRA_ENV_SETTINGS > > > > Based on the responaes below to the thread add linux/kconfig.h higher in th > > includes > > and drop the now unneeded autoconf.h lower down to ensure the default > > environment is > > included correctly > > > > http://lists.denx.de/pipermail/u-boot/2015-June/216849.html > > > > Signed-off-by: Peter Robinson > > --- > > tools/env/fw_env.h | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/tools/env/fw_env.h b/tools/env/fw_env.h > > index d6faf34..60c0517 100644 > > --- a/tools/env/fw_env.h > > +++ b/tools/env/fw_env.h > > @@ -6,6 +6,8 @@ > > */ > > > > /* Pull in the current config to define the default environment */ > > +#include > > + > > #ifndef __ASSEMBLY__ > > #define __ASSEMBLY__ /* get only #defines from config.h */ > > #include > > @@ -13,7 +15,6 @@ > > #else > > #include > > #endif > > -#include > > > > /* > > * To build the utility with the static configuration > > -- > > 2.4.3 > > > -- > Best Regards > Masahiro Yamada > ___ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] arm/layerscape: Fix non-boot cpus cannot correctly fall in spin table
From: Wang Dongsheng
Bootrom will put cpus into WFE state when boot cpu release cpus, so
target cpu cannot correctly go to spin state.
Add 'sev' to wakeup non-boot cpu that hold on bootrom space, let target
cpu can fall into u-boot spin table.
Signed-off-by: Wang Dongsheng
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index 75f0d8c..1f82893 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -344,5 +344,13 @@ void smp_kick_all_cpus(void)
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
out_be32(&gur->brrl, 0x2);
+
+ /*
+* LS1 STANDBYWFE is not captured outside the ARM module in the soc.
+* So add a delay to wait bootrom execute WFE.
+*/
+ udelay(1);
+
+ asm volatile("sev");
}
#endif
--
2.1.0.27.g96db324
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[U-Boot] Please pull u-boot-sunxi master
Hi Tom, Please pull u-boot-sunxi/master into master for a few small fixes. The following changes since commit 0d3f732fd2ba679b4498541f075d1b1bdbea3935: Merge git://git.denx.de/u-boot-usb (2015-06-15 20:45:50 -0400) are available in the git repository at: http://git.denx.de/u-boot-sunxi.git master for you to fetch changes up to 24e741269605ff7f073e83294852dd16edcd22c0: MSI_Primo81_defconfig: enable USB OTG port and keyboard support (2015-06-17 15:31:20 +0200) Hans de Goede (3): sunxi: musb: Do not fully reset the controler from sunxi_musb_disable sunxi: musb: Remove unused sunxi_musb_exit method sun6i: cpu_reset: Do not return from cpu_reset() Karsten Merker (1): MSI_Primo81_defconfig: enable USB OTG port and keyboard support arch/arm/cpu/armv7/sunxi/board.c | 1 + configs/MSI_Primo81_defconfig| 4 ++ drivers/usb/musb-new/sunxi.c | 80 ++-- 3 files changed, 33 insertions(+), 52 deletions(-) Regards, Hans ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 14/15] x86: crownbay: Enable writing MP table
Enable writing MP table for Intel Crown Bay board. Signed-off-by: Bin Meng Acked-by: Simon Glass --- Changes in v2: None configs/crownbay_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index abf5e3c..e4edad0 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -5,6 +5,7 @@ CONFIG_TARGET_CROWNBAY=y CONFIG_SMP=y CONFIG_MAX_CPUS=2 CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_MP_TABLE=y CONFIG_CMD_CPU=y CONFIG_CMD_NET=y CONFIG_OF_CONTROL=y -- 1.8.2.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 15/15] x86: queensbay: Change PCIe root ports' interrupt routing
So far interrupt routing works pretty well for any on-chip devices on Intel Crown Bay. When inserting any PCIe card to any PCIe slot, Linux kernel is smart enough to do interrupt swizzling and figure out device's irq using its parent bridge's interrupt routing info all the way up to its root port. In U-Boot all PCIe root ports' interrupts were routed to PIRQ E/F/G/H before, while actually all PCIe downstream ports received INTx are routed to PIRQ A/B/C/D directly and not configurable. Now we change this mapping so that any external PCIe device can work correctly. Signed-off-by: Bin Meng --- Changes in v2: - New patch to change PCIe root ports' interrupt routing for queensbay arch/x86/cpu/queensbay/tnc.c | 13 +++-- arch/x86/dts/crownbay.dts| 20 2 files changed, 23 insertions(+), 10 deletions(-) diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c index 873de7b..d27b2d9 100644 --- a/arch/x86/cpu/queensbay/tnc.c +++ b/arch/x86/cpu/queensbay/tnc.c @@ -69,17 +69,18 @@ void cpu_irq_init(void) * Route TunnelCreek PCI device interrupt pin to PIRQ * * Since PCIe downstream ports received INTx are routed to PIRQ -* A/B/C/D directly and not configurable, we route internal PCI -* device's INTx to PIRQ E/F/G/H. +* A/B/C/D directly and not configurable, we have to route PCIe +* root ports' INTx to PIRQ A/B/C/D as well. For other devices +* on TunneCreek, route them to PIRQ E/F/G/H. */ writew(PIRQE, &rcba->d02ir); writew(PIRQF, &rcba->d03ir); writew(PIRQG, &rcba->d27ir); writew(PIRQH, &rcba->d31ir); - writew(PIRQE, &rcba->d23ir); - writew(PIRQF, &rcba->d24ir); - writew(PIRQG, &rcba->d25ir); - writew(PIRQH, &rcba->d26ir); + writew(PIRQA, &rcba->d23ir); + writew(PIRQB, &rcba->d24ir); + writew(PIRQC, &rcba->d25ir); + writew(PIRQD, &rcba->d26ir); } int arch_misc_init(void) diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index b77c65a..60da1f5 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -169,10 +169,22 @@ /* TunnelCreek PCI devices */ PCI_BDF(0, 2, 0) INTA PIRQE PCI_BDF(0, 3, 0) INTA PIRQF - PCI_BDF(0, 23, 0) INTA PIRQE - PCI_BDF(0, 24, 0) INTA PIRQF - PCI_BDF(0, 25, 0) INTA PIRQG - PCI_BDF(0, 26, 0) INTA PIRQH + PCI_BDF(0, 23, 0) INTA PIRQA + PCI_BDF(0, 23, 0) INTB PIRQB + PCI_BDF(0, 23, 0) INTC PIRQC + PCI_BDF(0, 23, 0) INTD PIRQD + PCI_BDF(0, 24, 0) INTA PIRQB + PCI_BDF(0, 24, 0) INTB PIRQC + PCI_BDF(0, 24, 0) INTC PIRQD + PCI_BDF(0, 24, 0) INTD PIRQA + PCI_BDF(0, 25, 0) INTA PIRQC + PCI_BDF(0, 25, 0) INTB PIRQD + PCI_BDF(0, 25, 0) INTC PIRQA + PCI_BDF(0, 25, 0) INTD PIRQB + PCI_BDF(0, 26, 0) INTA PIRQD + PCI_BDF(0, 26, 0) INTB PIRQA + PCI_BDF(0, 26, 0) INTC PIRQB + PCI_BDF(0, 26, 0) INTD PIRQC PCI_BDF(0, 27, 0) INTA PIRQG /* * Topcliff PCI devices -- 1.8.2.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 13/15] x86: Update README.x86 for SMP support
Document U-Boot multi-processor support as well as configuration tables like SFI and MP tables for SMP OS kernel. Signed-off-by: Bin Meng --- Changes in v2: - New patch to update README.x86 for SMP support doc/README.x86 | 13 + 1 file changed, 13 insertions(+) diff --git a/doc/README.x86 b/doc/README.x86 index c19f4a0..49d6e83 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -258,6 +258,17 @@ Modern CPUs usually require a special bit stream called microcode [6] to be loaded on the processor after power up in order to function properly. U-Boot has already integrated these as hex dumps in the source tree. +SMP Support +--- +On a multicore system, U-Boot is executed on the bootstrap processor (BSP). +Additional application processors (AP) can be brought up by U-Boot. In order to +have an SMP kernel to discover all of the available processors, U-Boot needs to +prepare configuration tables which contain the multi-CPUs information before +loading the OS kernel. Currently U-Boot supports generating two types of tables +for SMP, called Simple Firmware Interface (SFI) [7] and Multi-Processor (MP) [8] +tables. The writing of these two tables are controlled by two Kconfig options +GENERATE_SFI_TABLE and GENERATE_MP_TABLE. + Driver Model x86 has been converted to use driver model for serial and GPIO. @@ -362,3 +373,5 @@ References [4] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html [5] http://www.intel.com/fsp [6] http://en.wikipedia.org/wiki/Microcode +[7] http://simplefirmware.org +[8] http://www.intel.com/design/archives/processors/pro/docs/242016.htm -- 1.8.2.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 12/15] x86: Generate a valid MultiProcessor (MP) table
Implement write_mp_table() to create a minimal working MP table.
This includes an MP floating table, a configuration table header
and all of the 5 base configuration table entries. The I/O interrupt
assignment table entry is created based on the same information used
in the creation of PIRQ routing table from device tree. A check
duplicated entry logic is applied to prevent writing multiple I/O
interrupt entries with the same information.
Use a Kconfig option GENERATE_MP_TABLE to tell U-Boot whether we
need actually write the MP table at the F seg, just like we did for
PIRQ routing and SFI tables. With MP table existence, linux kernel
will switch to I/O APIC and local APIC to process all the peripheral
interrupts instead of 8259 PICs. This takes full advantage of the
multicore hardware and the SMP kernel.
Signed-off-by: Bin Meng
---
Changes in v2:
- Avoid using u16 and u8 in parameters
- Add a comment block for check_dup_entry()
- Return and check error codes of mptable_add_intsrc()
- Remove __weak for write_mp_table()
arch/x86/Kconfig | 9 +++
arch/x86/include/asm/mpspec.h | 10 +++
arch/x86/lib/mpspec.c | 157 ++
arch/x86/lib/tables.c | 5 ++
4 files changed, 181 insertions(+)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 1aeae9d..6b46ec4 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -319,6 +319,15 @@ config GENERATE_SFI_TABLE
For more information, see http://simplefirmware.org
+config GENERATE_MP_TABLE
+ bool "Generate an MP (Multi-Processor) table"
+ default n
+ help
+ Generate an MP (Multi-Processor) table for this board. The MP table
+ provides a way for the operating system to support for symmetric
+ multiprocessing as well as symmetric I/O interrupt handling with
+ the local APIC and I/O APIC.
+
endmenu
config MAX_PIRQ_LINKS
diff --git a/arch/x86/include/asm/mpspec.h b/arch/x86/include/asm/mpspec.h
index 849113a..efa9231 100644
--- a/arch/x86/include/asm/mpspec.h
+++ b/arch/x86/include/asm/mpspec.h
@@ -431,4 +431,14 @@ void mp_write_compat_address_space(struct mp_config_table
*mc, int busid,
*/
u32 mptable_finalize(struct mp_config_table *mc);
+/**
+ * write_mp_table() - Write MP table
+ *
+ * This writes MP table at a given address.
+ *
+ * @addr: start address to write MP table
+ * @return:end address of MP table
+ */
+u32 write_mp_table(u32 addr);
+
#endif /* __ASM_MPSPEC_H */
diff --git a/arch/x86/lib/mpspec.c b/arch/x86/lib/mpspec.c
index 26d1025..29dfb10 100644
--- a/arch/x86/lib/mpspec.c
+++ b/arch/x86/lib/mpspec.c
@@ -9,13 +9,18 @@
#include
#include
#include
+#include
+#include
#include
+#include
#include
#include
#include
#include
#include
+DECLARE_GLOBAL_DATA_PTR;
+
struct mp_config_table *mp_write_floating_table(struct mp_floating_table *mf)
{
u32 mc;
@@ -223,3 +228,155 @@ u32 mptable_finalize(struct mp_config_table *mc)
return end;
}
+
+static void mptable_add_isa_interrupts(struct mp_config_table *mc, int bus_isa,
+ int apicid, int external_int2)
+{
+ int i;
+
+ mp_write_intsrc(mc, external_int2 ? MP_INT : MP_EXTINT,
+ MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
+ bus_isa, 0, apicid, 0);
+ mp_write_intsrc(mc, MP_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
+ bus_isa, 1, apicid, 1);
+ mp_write_intsrc(mc, external_int2 ? MP_EXTINT : MP_INT,
+ MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
+ bus_isa, 0, apicid, 2);
+
+ for (i = 3; i < 16; i++)
+ mp_write_intsrc(mc, MP_INT,
+ MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
+ bus_isa, i, apicid, i);
+}
+
+/*
+ * Check duplicated I/O interrupt assignment table entry, to make sure
+ * there is only one entry with the given bus, device and interrupt pin.
+ */
+static bool check_dup_entry(struct mpc_config_intsrc *intsrc_base,
+ int entry_num, int bus, int device, int pin)
+{
+ struct mpc_config_intsrc *intsrc = intsrc_base;
+ int i;
+
+ for (i = 0; i < entry_num; i++) {
+ if (intsrc->mpc_srcbus == bus &&
+ intsrc->mpc_srcbusirq == ((device << 2) | (pin - 1)))
+ break;
+ intsrc++;
+ }
+
+ return (i == entry_num) ? false : true;
+}
+
+static int mptable_add_intsrc(struct mp_config_table *mc,
+ int bus_isa, int apicid)
+{
+ struct mpc_config_intsrc *intsrc_base;
+ int intsrc_entries = 0;
+ const void *blob = gd->fdt_blob;
+ int node;
+ int len, count;
+ const u32 *cell;
+ int i;
+
+ /* Legacy Interrupts */
+ debug("Writing ISA IRQs\n");
+ mptable_add_isa_interrupts(mc, b
[U-Boot] [PATCH v2 11/15] x86: Add MultiProcessor (MP) table APIs
The MP table provides a way for the operating system to support
for symmetric multiprocessing as well as symmetric I/O interrupt
handling with the local APIC and I/O APIC. We provide a bunch of
APIs for U-Boot to write the floating table, configuration table
header as well as base and extended table entries.
Signed-off-by: Bin Meng
---
Changes in v2:
- Avoid using u16 and u8 in parameters
- Create a helper routine of strncpy that pads with spaces
arch/x86/include/asm/mpspec.h | 434 ++
arch/x86/include/asm/tables.h | 14 ++
arch/x86/lib/Makefile | 1 +
arch/x86/lib/mpspec.c | 225 ++
arch/x86/lib/tables.c | 14 ++
5 files changed, 688 insertions(+)
create mode 100644 arch/x86/include/asm/mpspec.h
create mode 100644 arch/x86/lib/mpspec.c
diff --git a/arch/x86/include/asm/mpspec.h b/arch/x86/include/asm/mpspec.h
new file mode 100644
index 000..849113a
--- /dev/null
+++ b/arch/x86/include/asm/mpspec.h
@@ -0,0 +1,434 @@
+/*
+ * Copyright (C) 2015, Bin Meng
+ *
+ * Adapted from coreboot src/arch/x86/include/arch/smp/mpspec.h
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __ASM_MPSPEC_H
+#define __ASM_MPSPEC_H
+
+/*
+ * Structure definitions for SMP machines following the
+ * Intel MultiProcessor Specification 1.4
+ */
+
+#define MPSPEC_V14 4
+
+#define MPF_SIGNATURE "_MP_"
+
+struct mp_floating_table {
+ char mpf_signature[4]; /* "_MP_" */
+ u32 mpf_physptr;/* Configuration table address */
+ u8 mpf_length; /* Our length (paragraphs) */
+ u8 mpf_spec;/* Specification version */
+ u8 mpf_checksum;/* Checksum (makes sum 0) */
+ u8 mpf_feature1;/* Predefined or Unique configuration? */
+ u8 mpf_feature2;/* Bit7 set for IMCR/PIC */
+ u8 mpf_feature3;/* Unused (0) */
+ u8 mpf_feature4;/* Unused (0) */
+ u8 mpf_feature5;/* Unused (0) */
+};
+
+#define MPC_SIGNATURE "PCMP"
+
+struct mp_config_table {
+ char mpc_signature[4]; /* "PCMP" */
+ u16 mpc_length; /* Size of table */
+ u8 mpc_spec;/* Specification version */
+ u8 mpc_checksum;/* Checksum (makes sum 0) */
+ char mpc_oem[8];/* OEM ID */
+ char mpc_product[12]; /* Product ID */
+ u32 mpc_oemptr; /* OEM table address */
+ u16 mpc_oemsize;/* OEM table size */
+ u16 mpc_entry_count;/* Number of entries in the table */
+ u32 mpc_lapic; /* Local APIC address */
+ u16 mpe_length; /* Extended table size */
+ u8 mpe_checksum;/* Extended table checksum */
+ u8 reserved;
+};
+
+/* Base MP configuration table entry types */
+
+enum mp_base_config_entry_type {
+ MP_PROCESSOR,
+ MP_BUS,
+ MP_IOAPIC,
+ MP_INTSRC,
+ MP_LINTSRC
+};
+
+#define MPC_CPU_EN (1 << 0)
+#define MPC_CPU_BP (1 << 1)
+
+struct mpc_config_processor {
+ u8 mpc_type;
+ u8 mpc_apicid;
+ u8 mpc_apicver;
+ u8 mpc_cpuflag;
+ u32 mpc_cpusignature;
+ u32 mpc_cpufeature;
+ u32 mpc_reserved[2];
+};
+
+#define BUSTYPE_CBUS "CBUS "
+#define BUSTYPE_CBUSII "CBUSII"
+#define BUSTYPE_EISA "EISA "
+#define BUSTYPE_FUTURE "FUTURE"
+#define BUSTYPE_INTERN "INTERN"
+#define BUSTYPE_ISA"ISA "
+#define BUSTYPE_MBI"MBI "
+#define BUSTYPE_MBII "MBII "
+#define BUSTYPE_MCA"MCA "
+#define BUSTYPE_MPI"MPI "
+#define BUSTYPE_MPSA "MPSA "
+#define BUSTYPE_NUBUS "NUBUS "
+#define BUSTYPE_PCI"PCI "
+#define BUSTYPE_PCMCIA "PCMCIA"
+#define BUSTYPE_TC "TC"
+#define BUSTYPE_VL "VL"
+#define BUSTYPE_VME"VME "
+#define BUSTYPE_XPRESS "XPRESS"
+
+struct mpc_config_bus {
+ u8 mpc_type;
+ u8 mpc_busid;
+ u8 mpc_bustype[6];
+};
+
+#define MPC_APIC_USABLE(1 << 0)
+
+struct mpc_config_ioapic {
+ u8 mpc_type;
+ u8 mpc_apicid;
+ u8 mpc_apicver;
+ u8 mpc_flags;
+ u32 mpc_apicaddr;
+};
+
+enum mp_irq_source_types {
+ MP_INT,
+ MP_NMI,
+ MP_SMI,
+ MP_EXTINT
+};
+
+#define MP_IRQ_POLARITY_DEFAULT0x0
+#define MP_IRQ_POLARITY_HIGH 0x1
+#define MP_IRQ_POLARITY_LOW0x3
+#define MP_IRQ_POLARITY_MASK 0x3
+#define MP_IRQ_TRIGGER_DEFAULT 0x0
+#define MP_IRQ_TRIGGER_EDGE0x4
+#define MP_IRQ_TRIGGER_LEVEL 0xc
+#define MP_IRQ_TRIGGER_MASK0xc
+
+#define MP_APIC_ALL0xff
+
+struct mpc_config_intsrc {
+ u8 mpc_type;
+ u8 mpc_irqtype;
+ u16 mpc_irqflag;
+ u8 mpc_srcbus;
+ u8 mpc_srcbusirq;
+ u8 mpc_dstapic;
+ u8 mpc_dstirq;
+};
+
+struct mpc_config_lintsrc {
+ u8 mpc_type;
+ u8 mpc_irqtype;
+ u16 mpc_irqflag;
+ u8 mpc_srcbusid;
+ u8 mpc_srcbusirq;
+ u8 mpc_destapic;
+ u8 mpc_destlint;
+};
+
+/* Extended MP configur
[U-Boot] [PATCH v2 09/15] x86: Add I/O APIC register access routines
I/O APIC registers are addressed indirectly. Add io_apic_read() and
io_apic_write() routines to help register access. Two macros for I/O
APIC ID and version register offset are also added.
Signed-off-by: Bin Meng
---
Changes in v2:
- Do not use inline for register access
arch/x86/cpu/Makefile | 2 +-
arch/x86/cpu/ioapic.c | 21 +
arch/x86/include/asm/ioapic.h | 24
3 files changed, 46 insertions(+), 1 deletion(-)
create mode 100644 arch/x86/cpu/ioapic.c
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 48197fb..8a8e63e 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -19,7 +19,7 @@ obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/
obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
obj-$(CONFIG_INTEL_QUARK) += quark/
obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
-obj-y += irq.o lapic.o
+obj-y += irq.o lapic.o ioapic.o
obj-$(CONFIG_SMP) += mp_init.o
obj-y += mtrr.o
obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/x86/cpu/ioapic.c b/arch/x86/cpu/ioapic.c
new file mode 100644
index 000..112a9c6
--- /dev/null
+++ b/arch/x86/cpu/ioapic.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2015, Bin Meng
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+
+u32 io_apic_read(u32 reg)
+{
+ writel(reg, IO_APIC_INDEX);
+ return readl(IO_APIC_DATA);
+}
+
+void io_apic_write(u32 reg, u32 val)
+{
+ writel(reg, IO_APIC_INDEX);
+ writel(val, IO_APIC_DATA);
+}
diff --git a/arch/x86/include/asm/ioapic.h b/arch/x86/include/asm/ioapic.h
index f5d69db..77c443e 100644
--- a/arch/x86/include/asm/ioapic.h
+++ b/arch/x86/include/asm/ioapic.h
@@ -15,4 +15,28 @@
#define IO_APIC_INDEX (IO_APIC_ADDR + 0x00)
#define IO_APIC_DATA (IO_APIC_ADDR + 0x10)
+/* Indirect addressed register offset */
+#define IO_APIC_ID 0x00
+#define IO_APIC_VER0x01
+
+/**
+ * io_apic_read() - Read I/O APIC register
+ *
+ * This routine reads I/O APIC indirect addressed register.
+ *
+ * @reg: address of indirect addressed register
+ * @return:register value to read
+ */
+u32 io_apic_read(u32 reg);
+
+/**
+ * io_apic_write() - Write I/O APIC register
+ *
+ * This routine writes I/O APIC indirect addressed register.
+ *
+ * @reg: address of indirect addressed register
+ * @val: register value to write
+ */
+void io_apic_write(u32 reg, u32 val);
+
#endif
--
1.8.2.1
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[U-Boot] [PATCH v2 10/15] x86: Remove inline for lapic access routines
Remove inline for lapic access routines and expose lapic_read()
& lapic_write() as APIs to read/write lapic registers. Also move
stop_this_cpu() to mp_init.c as it has nothing to do with lapic.
Signed-off-by: Bin Meng
---
Changes in v2:
- New patch to remove inline for lapic access routines
arch/x86/cpu/lapic.c | 143 +--
arch/x86/cpu/mp_init.c | 27 +---
arch/x86/include/asm/lapic.h | 134 +++-
3 files changed, 153 insertions(+), 151 deletions(-)
diff --git a/arch/x86/cpu/lapic.c b/arch/x86/cpu/lapic.c
index 6769ae5..30d2313 100644
--- a/arch/x86/cpu/lapic.c
+++ b/arch/x86/cpu/lapic.c
@@ -8,9 +8,116 @@
*/
#include
+#include
#include
+#include
+#include
#include
+unsigned long lapic_read(unsigned long reg)
+{
+ return readl(LAPIC_DEFAULT_BASE + reg);
+}
+
+#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
+ sizeof(*(ptr
+
+struct __xchg_dummy{ unsigned long a[100]; };
+#define __xg(x)((struct __xchg_dummy *)(x))
+
+/*
+ * Note: no "lock" prefix even on SMP. xchg always implies lock anyway.
+ *
+ * Note 2: xchg has side effect, so that attribute volatile is necessary,
+ * but generally the primitive is invalid, *ptr is output argument.
+ */
+static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
+ int size)
+{
+ switch (size) {
+ case 1:
+ __asm__ __volatile__("xchgb %b0,%1"
+ : "=q" (x)
+ : "m" (*__xg(ptr)), "0" (x)
+ : "memory");
+ break;
+ case 2:
+ __asm__ __volatile__("xchgw %w0,%1"
+ : "=r" (x)
+ : "m" (*__xg(ptr)), "0" (x)
+ : "memory");
+ break;
+ case 4:
+ __asm__ __volatile__("xchgl %0,%1"
+ : "=r" (x)
+ : "m" (*__xg(ptr)), "0" (x)
+ : "memory");
+ break;
+ }
+
+ return x;
+}
+
+void lapic_write(unsigned long reg, unsigned long v)
+{
+ (void)xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE + reg), v);
+}
+
+void enable_lapic(void)
+{
+ msr_t msr;
+
+ msr = msr_read(MSR_IA32_APICBASE);
+ msr.hi &= 0xff00;
+ msr.lo |= MSR_IA32_APICBASE_ENABLE;
+ msr.lo &= ~MSR_IA32_APICBASE_BASE;
+ msr.lo |= LAPIC_DEFAULT_BASE;
+ msr_write(MSR_IA32_APICBASE, msr);
+}
+
+void disable_lapic(void)
+{
+ msr_t msr;
+
+ msr = msr_read(MSR_IA32_APICBASE);
+ msr.lo &= ~MSR_IA32_APICBASE_ENABLE;
+ msr_write(MSR_IA32_APICBASE, msr);
+}
+
+unsigned long lapicid(void)
+{
+ return lapic_read(LAPIC_ID) >> 24;
+}
+
+static void lapic_wait_icr_idle(void)
+{
+ do { } while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY);
+}
+
+int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
+{
+ int timeout;
+ unsigned long status;
+ int result;
+
+ lapic_wait_icr_idle();
+ lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
+ lapic_write(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
+
+ timeout = 0;
+ do {
+ status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
+ } while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000);
+
+ result = -1;
+ if (status == LAPIC_ICR_RR_VALID) {
+ *pvalue = lapic_read(LAPIC_RRR);
+ result = 0;
+ }
+
+ return result;
+}
+
void lapic_setup(void)
{
#ifdef CONFIG_SMP
@@ -21,26 +128,26 @@ void lapic_setup(void)
enable_lapic();
/* Set Task Priority to 'accept all' */
- lapic_write_around(LAPIC_TASKPRI,
- lapic_read_around(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK);
+ lapic_write(LAPIC_TASKPRI,
+ lapic_read(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK);
/* Put the local apic in virtual wire mode */
- lapic_write_around(LAPIC_SPIV, (lapic_read_around(LAPIC_SPIV) &
- ~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE);
- lapic_write_around(LAPIC_LVT0, (lapic_read_around(LAPIC_LVT0) &
- ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
- LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
- LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
- LAPIC_DELIVERY_MODE_MASK)) |
- (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
- LAPIC_DELIVERY_MODE_EXTINT));
- lapic_write_around(LAPIC_LVT1, (lapic_read_around(LAPIC_LVT1) &
- ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
- LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
- LAPIC_SE
[U-Boot] [PATCH v2 07/15] x86: Reduce PIRQ routing table size
There is no need to populate multiple irq info entries with the same
bus number and device number, but with different interrupt pin. We
can use the same entry to store all the 4 interrupt pin (INT A/B/C/D)
routing information to reduce the whole PIRQ routing table size.
Signed-off-by: Bin Meng
Acked-by: Simon Glass
---
Changes in v2:
- Avoid using u16 and u8 in parameters
arch/x86/cpu/irq.c | 65 ++
1 file changed, 56 insertions(+), 9 deletions(-)
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index df4300c..97dd000 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -58,17 +58,28 @@ void pirq_assign_irq(int link, u8 irq)
writeb(irq, irq_router.ibase + LINK_N2V(link, base));
}
-static inline void fill_irq_info(struct irq_info **slotp, int *entries, u8 bus,
-u8 device, u8 pin, u8 pirq)
+static struct irq_info *check_dup_entry(struct irq_info *slot_base,
+ int entry_num, int bus, int device)
{
- struct irq_info *slot = *slotp;
+ struct irq_info *slot = slot_base;
+ int i;
+
+ for (i = 0; i < entry_num; i++) {
+ if (slot->bus == bus && slot->devfn == (device << 3))
+ break;
+ slot++;
+ }
+ return (i == entry_num) ? NULL : slot;
+}
+
+static inline void fill_irq_info(struct irq_info *slot, int bus, int device,
+int pin, int pirq)
+{
slot->bus = bus;
slot->devfn = (device << 3) | 0;
slot->irq[pin - 1].link = LINK_N2V(pirq, irq_router.link_base);
slot->irq[pin - 1].bitmap = irq_router.irq_mask;
- (*entries)++;
- (*slotp)++;
}
__weak void cpu_irq_init(void)
@@ -84,7 +95,7 @@ static int create_pirq_routing_table(void)
int len, count;
const u32 *cell;
struct irq_routing_table *rt;
- struct irq_info *slot;
+ struct irq_info *slot, *slot_base;
int irq_entries = 0;
int i;
int ret;
@@ -167,7 +178,7 @@ static int create_pirq_routing_table(void)
rt->rtr_vendor = PCI_VENDOR_ID_INTEL;
rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31;
- slot = rt->slots;
+ slot_base = rt->slots;
/* Now fill in the irq_info entries in the PIRQ table */
for (i = 0; i < count; i++) {
@@ -181,8 +192,44 @@ static int create_pirq_routing_table(void)
i, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
PCI_FUNC(pr.bdf), 'A' + pr.pin - 1,
'A' + pr.pirq);
- fill_irq_info(&slot, &irq_entries, PCI_BUS(pr.bdf),
- PCI_DEV(pr.bdf), pr.pin, pr.pirq);
+
+ slot = check_dup_entry(slot_base, irq_entries,
+ PCI_BUS(pr.bdf), PCI_DEV(pr.bdf));
+ if (slot) {
+ debug("found entry for bus %d device %d, ",
+ PCI_BUS(pr.bdf), PCI_DEV(pr.bdf));
+
+ if (slot->irq[pr.pin - 1].link) {
+ debug("skipping\n");
+
+ /*
+* Sanity test on the routed PIRQ pin
+*
+* If they don't match, show a warning to tell
+* there might be something wrong with the PIRQ
+* routing information in the device tree.
+*/
+ if (slot->irq[pr.pin - 1].link !=
+ LINK_N2V(pr.pirq, irq_router.link_base))
+ debug("WARNING: Inconsistent PIRQ
routing information\n");
+
+ cell += sizeof(struct pirq_routing) /
+ sizeof(u32);
+ continue;
+ } else {
+ debug("writing INT%c\n", 'A' + pr.pin - 1);
+ fill_irq_info(slot, PCI_BUS(pr.bdf),
+ PCI_DEV(pr.bdf), pr.pin, pr.pirq);
+ cell += sizeof(struct pirq_routing) /
+ sizeof(u32);
+ continue;
+ }
+ }
+
+ slot = slot_base + irq_entries;
+ fill_irq_info(slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
+ pr.pin, pr.pirq);
+ irq_entries++;
cell += sizeof(struct pirq_routing) / sizeof(u32);
}
--
1.8.2.1
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[U-Boot] [PATCH v2 05/15] x86: Write correct bus number for the irq router
We should write correct bus number to the PIRQ routing table for the irq router from device tree, instead of hard-coded zero. Signed-off-by: Bin Meng Acked-by: Simon Glass --- Changes in v2: None arch/x86/cpu/irq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c index 74b89ad..7d5ccc1 100644 --- a/arch/x86/cpu/irq.c +++ b/arch/x86/cpu/irq.c @@ -161,7 +161,7 @@ static int create_pirq_routing_table(void) /* Populate the PIRQ table fields */ rt->signature = PIRQ_SIGNATURE; rt->version = PIRQ_VERSION; - rt->rtr_bus = 0; + rt->rtr_bus = PCI_BUS(irq_router.bdf); rt->rtr_devfn = (PCI_DEV(irq_router.bdf) << 3) | PCI_FUNC(irq_router.bdf); rt->rtr_vendor = PCI_VENDOR_ID_INTEL; -- 1.8.2.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 08/15] x86: Clean up ioapic header file
Remove all the dead/unused macros from asm/ioapic.h. Signed-off-by: Bin Meng Acked-by: Simon Glass --- Changes in v2: None arch/x86/include/asm/ioapic.h | 26 +++--- 1 file changed, 3 insertions(+), 23 deletions(-) diff --git a/arch/x86/include/asm/ioapic.h b/arch/x86/include/asm/ioapic.h index 699160f..f5d69db 100644 --- a/arch/x86/include/asm/ioapic.h +++ b/arch/x86/include/asm/ioapic.h @@ -10,29 +10,9 @@ #define __ASM_IOAPIC_H #define IO_APIC_ADDR 0xfec0 -#define IO_APIC_INDEX IO_APIC_ADDR -#define IO_APIC_DATA (IO_APIC_ADDR + 0x10) -#define IO_APIC_INTERRUPTS 24 - -#define ALL(0xff << 24) -#define NONE 0 -#define DISABLED (1 << 16) -#define ENABLED(0 << 16) -#define TRIGGER_EDGE (0 << 15) -#define TRIGGER_LEVEL (1 << 15) -#define POLARITY_HIGH (0 << 13) -#define POLARITY_LOW (1 << 13) -#define PHYSICAL_DEST (0 << 11) -#define LOGICAL_DEST (1 << 11) -#define ExtINT (7 << 8) -#define NMI(4 << 8) -#define SMI(2 << 8) -#define INT(1 << 8) -u32 io_apic_read(u32 ioapic_base, u32 reg); -void io_apic_write(u32 ioapic_base, u32 reg, u32 value); -void set_ioapic_id(u32 ioapic_base, u8 ioapic_id); -void setup_ioapic(u32 ioapic_base, u8 ioapic_id); -void clear_ioapic(u32 ioapic_base); +/* Direct addressed register */ +#define IO_APIC_INDEX (IO_APIC_ADDR + 0x00) +#define IO_APIC_DATA (IO_APIC_ADDR + 0x10) #endif -- 1.8.2.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 02/15] cmd: date: Change to use CONFIG_DM_RTC instead of CONFIG_DM_I2C
Currently CONFIG_DM_I2C is used in cmd_date.c for driver model,
but it should be actually CONFIG_DM_RTC.
Signed-off-by: Bin Meng
---
Changes in v2:
- New patch to change to use CONFIG_DM_RTC instead of CONFIG_DM_I2C
common/cmd_date.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/common/cmd_date.c b/common/cmd_date.c
index 61727e3..8714699 100644
--- a/common/cmd_date.c
+++ b/common/cmd_date.c
@@ -37,7 +37,7 @@ static int do_date(cmd_tbl_t *cmdtp, int flag, int argc, char
* const argv[])
int old_bus __maybe_unused;
/* switch to correct I2C bus */
-#ifdef CONFIG_DM_I2C
+#ifdef CONFIG_DM_RTC
struct udevice *dev;
rcode = uclass_get_device(UCLASS_RTC, 0, &dev);
@@ -57,7 +57,7 @@ static int do_date(cmd_tbl_t *cmdtp, int flag, int argc, char
* const argv[])
case 2: /* set date & time */
if (strcmp(argv[1],"reset") == 0) {
puts ("Reset RTC...\n");
-#ifdef CONFIG_DM_I2C
+#ifdef CONFIG_DM_RTC
rcode = dm_rtc_reset(dev);
if (!rcode)
rcode = dm_rtc_set(dev, &default_tm);
@@ -69,7 +69,7 @@ static int do_date(cmd_tbl_t *cmdtp, int flag, int argc, char
* const argv[])
puts("## Failed to set date after RTC reset\n");
} else {
/* initialize tm with current time */
-#ifdef CONFIG_DM_I2C
+#ifdef CONFIG_DM_RTC
rcode = dm_rtc_get(dev, &tm);
#else
rcode = rtc_get(&tm);
@@ -81,7 +81,7 @@ static int do_date(cmd_tbl_t *cmdtp, int flag, int argc, char
* const argv[])
break;
}
/* and write to RTC */
-#ifdef CONFIG_DM_I2C
+#ifdef CONFIG_DM_RTC
rcode = dm_rtc_set(dev, &tm);
#else
rcode = rtc_set(&tm);
@@ -96,7 +96,7 @@ static int do_date(cmd_tbl_t *cmdtp, int flag, int argc, char
* const argv[])
}
/* FALL TROUGH */
case 1: /* get date & time */
-#ifdef CONFIG_DM_I2C
+#ifdef CONFIG_DM_RTC
rcode = dm_rtc_get(dev, &tm);
#else
rcode = rtc_get(&tm);
@@ -120,7 +120,7 @@ static int do_date(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
/* switch back to original I2C bus */
#ifdef CONFIG_SYS_I2C
i2c_set_bus_num(old_bus);
-#elif !defined(CONFIG_DM_I2C)
+#elif !defined(CONFIG_DM_RTC)
I2C_SET_BUS(old_bus);
#endif
--
1.8.2.1
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[U-Boot] [PATCH v2 03/15] x86: crownbay: Enable DM RTC support
Add a RTC node in the device tree to enable DM RTC support.
Signed-off-by: Bin Meng
---
Changes in v2:
- New patch to enable DM RTC support for Crown Bay
arch/x86/dts/crownbay.dts | 1 +
arch/x86/dts/rtc.dtsi | 6 ++
configs/crownbay_defconfig | 1 +
3 files changed, 8 insertions(+)
create mode 100644 arch/x86/dts/rtc.dtsi
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index 1ec90cd..87ed0f4 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -10,6 +10,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
+/include/ "rtc.dtsi"
/ {
model = "Intel Crown Bay";
diff --git a/arch/x86/dts/rtc.dtsi b/arch/x86/dts/rtc.dtsi
new file mode 100644
index 000..93dacd7
--- /dev/null
+++ b/arch/x86/dts/rtc.dtsi
@@ -0,0 +1,6 @@
+/ {
+ rtc {
+ compatible = "motorola,mc146818";
+ reg = <0x70 2>;
+ };
+};
diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index d21177d..abf5e3c 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -9,3 +9,4 @@ CONFIG_CMD_CPU=y
CONFIG_CMD_NET=y
CONFIG_OF_CONTROL=y
CONFIG_CPU=y
+CONFIG_DM_RTC=y
--
1.8.2.1
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[U-Boot] [PATCH v2 06/15] x86: Ignore function number when writing PIRQ routing table
In fill_irq_info() pci device's function number is written into
the table, however this is not really necessary. The function
number can be anything as OS doesn't care about this field,
neither does the PIRQ routing specification. Change to always
writing 0 as the function number.
Signed-off-by: Bin Meng
Acked-by: Simon Glass
---
Changes in v2: None
arch/x86/cpu/irq.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index 7d5ccc1..df4300c 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -59,12 +59,12 @@ void pirq_assign_irq(int link, u8 irq)
}
static inline void fill_irq_info(struct irq_info **slotp, int *entries, u8 bus,
-u8 device, u8 func, u8 pin, u8 pirq)
+u8 device, u8 pin, u8 pirq)
{
struct irq_info *slot = *slotp;
slot->bus = bus;
- slot->devfn = (device << 3) | func;
+ slot->devfn = (device << 3) | 0;
slot->irq[pin - 1].link = LINK_N2V(pirq, irq_router.link_base);
slot->irq[pin - 1].bitmap = irq_router.irq_mask;
(*entries)++;
@@ -182,8 +182,7 @@ static int create_pirq_routing_table(void)
PCI_FUNC(pr.bdf), 'A' + pr.pin - 1,
'A' + pr.pirq);
fill_irq_info(&slot, &irq_entries, PCI_BUS(pr.bdf),
- PCI_DEV(pr.bdf), PCI_FUNC(pr.bdf),
- pr.pin, pr.pirq);
+ PCI_DEV(pr.bdf), pr.pin, pr.pirq);
cell += sizeof(struct pirq_routing) / sizeof(u32);
}
--
1.8.2.1
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[U-Boot] [PATCH v2 01/15] dm: rtc: Support mc146818 driver in driver model
Add driver model support to the mc146818 rtc driver. Also clean up
the driver a little bit for coding convention issues.
Signed-off-by: Bin Meng
---
Changes in v2:
- New patch to support mc146818 driver in driver model
drivers/rtc/mc146818.c | 312 -
1 file changed, 204 insertions(+), 108 deletions(-)
diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c
index 44857a6..363ade3 100644
--- a/drivers/rtc/mc146818.c
+++ b/drivers/rtc/mc146818.c
@@ -9,10 +9,9 @@
* Date & Time support for the MC146818 (PIXX4) RTC
*/
-/*#define DEBUG*/
-
#include
#include
+#include
#include
#if defined(__I386__) || defined(CONFIG_MALTA)
@@ -24,9 +23,9 @@
#if defined(CONFIG_CMD_DATE)
/* Set this to 1 to clear the CMOS RAM */
-#define CLEAR_CMOS 0
+#define CLEAR_CMOS 0
-#define RTC_PORT_MC146818 CONFIG_SYS_ISA_IO_BASE_ADDRESS + 0x70
+#define RTC_PORT_MC146818 CONFIG_SYS_ISA_IO_BASE_ADDRESS + 0x70
#define RTC_SECONDS0x00
#define RTC_SECONDS_ALARM 0x01
#define RTC_MINUTES0x02
@@ -37,10 +36,10 @@
#define RTC_DATE_OF_MONTH 0x07
#define RTC_MONTH 0x08
#define RTC_YEAR 0x09
-#define RTC_CONFIG_A 0x0A
-#define RTC_CONFIG_B 0x0B
-#define RTC_CONFIG_C 0x0C
-#define RTC_CONFIG_D 0x0D
+#define RTC_CONFIG_A 0x0a
+#define RTC_CONFIG_B 0x0b
+#define RTC_CONFIG_C 0x0c
+#define RTC_CONFIG_D 0x0d
#define RTC_REG_SIZE 0x80
#define RTC_CONFIG_A_REF_CLCK_32KHZ(1 << 5)
@@ -50,89 +49,7 @@
#define RTC_CONFIG_D_VALID_RAM_AND_TIME0x80
-/* - */
-
-int rtc_get (struct rtc_time *tmp)
-{
- uchar sec, min, hour, mday, wday, mon, year;
- /* here check if rtc can be accessed */
- while ((rtc_read8(RTC_CONFIG_A) & 0x80) == 0x80);
- sec = rtc_read8(RTC_SECONDS);
- min = rtc_read8(RTC_MINUTES);
- hour= rtc_read8(RTC_HOURS);
- mday= rtc_read8(RTC_DATE_OF_MONTH);
- wday= rtc_read8(RTC_DAY_OF_WEEK);
- mon = rtc_read8(RTC_MONTH);
- year= rtc_read8(RTC_YEAR);
-#ifdef RTC_DEBUG
- printf ( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
- "hr: %02x min: %02x sec: %02x\n",
- year, mon, mday, wday,
- hour, min, sec );
- printf ( "Alarms: month: %02x hour: %02x min: %02x sec: %02x\n",
- rtc_read8(RTC_CONFIG_D) & 0x3F,
- rtc_read8(RTC_HOURS_ALARM),
- rtc_read8(RTC_MINUTES_ALARM),
- rtc_read8(RTC_SECONDS_ALARM));
-#endif
- tmp->tm_sec = bcd2bin (sec & 0x7F);
- tmp->tm_min = bcd2bin (min & 0x7F);
- tmp->tm_hour = bcd2bin (hour & 0x3F);
- tmp->tm_mday = bcd2bin (mday & 0x3F);
- tmp->tm_mon = bcd2bin (mon & 0x1F);
- tmp->tm_year = bcd2bin (year);
- tmp->tm_wday = bcd2bin (wday & 0x07);
- if(tmp->tm_year<70)
- tmp->tm_year+=2000;
- else
- tmp->tm_year+=1900;
- tmp->tm_yday = 0;
- tmp->tm_isdst= 0;
-#ifdef RTC_DEBUG
- printf ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
- tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
- tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
-#endif
-
- return 0;
-}
-
-int rtc_set (struct rtc_time *tmp)
-{
-#ifdef RTC_DEBUG
- printf ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
- tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
- tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
-#endif
- rtc_write8(RTC_CONFIG_B, 0x82); /* disable the RTC to update the regs */
-
- rtc_write8(RTC_YEAR, bin2bcd(tmp->tm_year % 100));
- rtc_write8(RTC_MONTH, bin2bcd(tmp->tm_mon));
- rtc_write8(RTC_DAY_OF_WEEK, bin2bcd(tmp->tm_wday));
- rtc_write8(RTC_DATE_OF_MONTH, bin2bcd(tmp->tm_mday));
- rtc_write8(RTC_HOURS, bin2bcd(tmp->tm_hour));
- rtc_write8(RTC_MINUTES, bin2bcd(tmp->tm_min));
- rtc_write8(RTC_SECONDS, bin2bcd(tmp->tm_sec));
- rtc_write8(RTC_CONFIG_B, 0x02); /* enable the RTC to update the regs */
-
- return 0;
-}
-
-void rtc_reset (void)
-{
- rtc_write8(RTC_CONFIG_B, 0x82); /* disable the RTC to update the regs */
- rtc_write8(RTC_CONFIG_A, 0x20); /* Normal OP */
- rtc_write8(RTC_CONFIG_B, 0x00);
- rtc_write8(RTC_CONFIG_B, 0x00);
- rtc_write8(RTC_CONFIG_B, 0x02); /* enable the RTC to update the regs */
-}
-
-/* - */
-
-/*
- * use direct memory access
- */
-int rtc_read8(int reg)
+static int mc146818_read8(int reg)
{
#ifdef CONFIG_SYS_RTC_REG_BASE_ADDR
return in8(CONFIG_SYS_RTC_REG_BASE_ADDR + reg);
@@ -149,7 +66,7 @@ int rtc_read8(int reg)
#endif
[U-Boot] [PATCH v2 04/15] x86: queensbay: Correct Topcliff device irqs
There are 4 usb ports on the Intel Crown Bay board, 2 of which are connected to Topcliff usb host 0 and the other 2 connected to usb host 1. USB devices inserted in the ports connected to usb host 1 cannot get detected due to wrong IRQ assigned to the controller. Actually we need apply the PCI interrupt pin swizzling logic to all devices on the Topcliff chipset when configuring the PIRQ routing. This was observed on usb ports, but device 6 and 10 irqs are also wrong. Correct them all together. Signed-off-by: Bin Meng Acked-by: Simon Glass --- Changes in v2: None arch/x86/dts/crownbay.dts | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index 87ed0f4..b77c65a 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -180,29 +180,29 @@ * Note on the Crown Bay board, Topcliff chipset * is connected to TunnelCreek PCIe port 0, so * its bus number is 1 for its PCIe port and 2 -* for its PCI devices per U-Boot currnet PCI +* for its PCI devices per U-Boot current PCI * bus enumeration algorithm. */ PCI_BDF(1, 0, 0) INTA PIRQA PCI_BDF(2, 0, 1) INTA PIRQA PCI_BDF(2, 0, 2) INTA PIRQA - PCI_BDF(2, 2, 0) INTB PIRQB - PCI_BDF(2, 2, 1) INTB PIRQB - PCI_BDF(2, 2, 2) INTB PIRQB - PCI_BDF(2, 2, 3) INTB PIRQB - PCI_BDF(2, 2, 4) INTB PIRQB + PCI_BDF(2, 2, 0) INTB PIRQD + PCI_BDF(2, 2, 1) INTB PIRQD + PCI_BDF(2, 2, 2) INTB PIRQD + PCI_BDF(2, 2, 3) INTB PIRQD + PCI_BDF(2, 2, 4) INTB PIRQD PCI_BDF(2, 4, 0) INTC PIRQC PCI_BDF(2, 4, 1) INTC PIRQC - PCI_BDF(2, 6, 0) INTD PIRQD + PCI_BDF(2, 6, 0) INTD PIRQB PCI_BDF(2, 8, 0) INTA PIRQA PCI_BDF(2, 8, 1) INTA PIRQA PCI_BDF(2, 8, 2) INTA PIRQA PCI_BDF(2, 8, 3) INTA PIRQA - PCI_BDF(2, 10, 0) INTB PIRQB - PCI_BDF(2, 10, 1) INTB PIRQB - PCI_BDF(2, 10, 2) INTB PIRQB - PCI_BDF(2, 10, 3) INTB PIRQB - PCI_BDF(2, 10, 4) INTB PIRQB + PCI_BDF(2, 10, 0) INTB PIRQD + PCI_BDF(2, 10, 1) INTB PIRQD + PCI_BDF(2, 10, 2) INTB PIRQD + PCI_BDF(2, 10, 3) INTB PIRQD + PCI_BDF(2, 10, 4) INTB PIRQD PCI_BDF(2, 12, 0) INTC PIRQC PCI_BDF(2, 12, 1) INTC PIRQC PCI_BDF(2, 12, 2) INTC PIRQC -- 1.8.2.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
