[U-Boot] [PATCH] Tegra: Allow TZ writes to VPR aperature regs
VPR (Video Protect Region) may be reconfigured
from secure code in the kernel/OS. Set the
ALLOW_TZ_WRITE_ACCESS bit in REG_CTRL to allow
this. Also used common CONFIG option (CONFIG_LOCK_VPR)
in T124/T210 builds to enable VPR setup.
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/include/asm/arch-tegra124/mc.h | 2 ++
arch/arm/include/asm/arch-tegra210/mc.h | 2 ++
arch/arm/mach-tegra/Makefile| 4 +---
arch/arm/mach-tegra/vpr.c | 9 +++--
include/configs/tegra124-common.h | 3 +++
include/configs/tegra210-common.h | 3 +++
6 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra124/mc.h
b/arch/arm/include/asm/arch-tegra124/mc.h
index 37998a4..851e3df 100644
--- a/arch/arm/include/asm/arch-tegra124/mc.h
+++ b/arch/arm/include/asm/arch-tegra124/mc.h
@@ -78,5 +78,7 @@ struct mc_ctlr {
#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED(0 0)
#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 0)
+#define TEGRA_MC_VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS_DISABLED (0 1)
+#define TEGRA_MC_VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS_ENABLED (1 1)
#endif /* _TEGRA124_MC_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/mc.h
b/arch/arm/include/asm/arch-tegra210/mc.h
index 77e9aa5..2a20b47 100644
--- a/arch/arm/include/asm/arch-tegra210/mc.h
+++ b/arch/arm/include/asm/arch-tegra210/mc.h
@@ -68,5 +68,7 @@ struct mc_ctlr {
#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED(0 0)
#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 0)
+#define TEGRA_MC_VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS_DISABLED (0 1)
+#define TEGRA_MC_VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS_ENABLED (1 1)
#endif /* _TEGRA210_MC_H_ */
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 0db8ee0..8a42216 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -24,9 +24,7 @@ obj-y += pinmux-common.o
obj-y += powergate.o
obj-y += xusb-padctl.o
obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
-#TCW Fix this to use a common config switch (CONFIG_LOCK_VPR?)
-obj-$(CONFIG_TEGRA124) += vpr.o
-obj-$(CONFIG_TEGRA210) += vpr.o
+obj-$(CONFIG_LOCK_VPR) += vpr.o
obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
ifndef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-tegra/vpr.c b/arch/arm/mach-tegra/vpr.c
index f695811..091163e 100644
--- a/arch/arm/mach-tegra/vpr.c
+++ b/arch/arm/mach-tegra/vpr.c
@@ -21,14 +21,19 @@
#include asm/arch/tegra.h
#include asm/arch/mc.h
-/* Configures VPR. Right now, all we do is turn it off. */
+/*
+ * Configures VPR. Right now, all we do is turn it off.
+ * But we set ALLOW_TZ_WRITE_ACCESS so secure code
+ * in the kernel/OS can reconfig it later if needed.
+ */
void config_vpr(void)
{
struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
/* Turn VPR off */
writel(0, mc-mc_video_protect_size_mb);
- writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED,
+ writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED |
+ TEGRA_MC_VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS_ENABLED,
mc-mc_video_protect_reg_ctrl);
/* read back to ensure the write went through */
readl(mc-mc_video_protect_reg_ctrl);
diff --git a/include/configs/tegra124-common.h
b/include/configs/tegra124-common.h
index af7698d..e850a75 100644
--- a/include/configs/tegra124-common.h
+++ b/include/configs/tegra124-common.h
@@ -70,4 +70,7 @@
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
+/* Set up VPR (Video Protect Region) */
+#define CONFIG_LOCK_VPR
+
#endif /* _TEGRA124_COMMON_H_ */
diff --git a/include/configs/tegra210-common.h
b/include/configs/tegra210-common.h
index 0348d47..267beab 100644
--- a/include/configs/tegra210-common.h
+++ b/include/configs/tegra210-common.h
@@ -73,4 +73,7 @@
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
+/* Set up VPR (Video Protect Region) */
+#define CONFIG_LOCK_VPR
+
#endif /* _TEGRA210_COMMON_H_ */
--
1.8.2.1.610.g562af5b
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[U-Boot] [PATCH] T210: P2571: Turn CPU fan on
CPU board (E2530) has a fan - turn it on via GPIO to keep
the SoC cool.
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/mach-tegra/board2.c | 3 +++
board/nvidia/p2571/p2571.c | 12
2 files changed, 15 insertions(+)
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 36bcfb0..2927b4e 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -60,6 +60,7 @@ __weak void pin_mux_usb(void) {}
__weak void pin_mux_spi(void) {}
__weak void gpio_early_init_uart(void) {}
__weak void pin_mux_display(void) {}
+__weak void start_cpu_fan(void) {}
#if defined(CONFIG_TEGRA_NAND)
__weak void pin_mux_nand(void)
@@ -230,6 +231,8 @@ int board_late_init(void)
setenv(cpu_ns_mode, );
}
#endif
+ start_cpu_fan();
+
return 0;
}
diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c
index 842242c..4b0f973 100644
--- a/board/nvidia/p2571/p2571.c
+++ b/board/nvidia/p2571/p2571.c
@@ -9,6 +9,7 @@
#include i2c.h
#include asm/arch/gpio.h
#include asm/arch/pinmux.h
+#include asm/gpio.h
#include max77620_init.h
#include pinmux-config-p2571.h
@@ -49,3 +50,14 @@ void pinmux_init(void)
pinmux_config_drvgrp_table(p2571_drvgrps,
ARRAY_SIZE(p2571_drvgrps));
}
+
+/*
+ * Routine: start_cpu_fan
+ * Description: Enable/start PWM CPU fan on Foster-FFD
+ */
+void start_cpu_fan(void)
+{
+ /* GPIO_PE4 is PS_VDD_FAN_ENABLE */
+ gpio_request(GPIO_PE4, FAN_VDD);
+ gpio_direction_output(GPIO_PE4, 1);
+}
--
1.8.2.1.610.g562af5b
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[U-Boot] [PATCH] T210: P2571: Enable SD-card power via PMIC LDO2
This was done in the 32-bit AVP loader (SPL) but is
board-specific so should be moved to the CPU portion.
Signed-off-by: Tom Warren twar...@nvidia.com
---
board/nvidia/p2571/Makefile| 1 -
board/nvidia/p2571/max77620_init.c | 85 --
board/nvidia/p2571/max77620_init.h | 3 +-
board/nvidia/p2571/p2571.c | 22 ++
4 files changed, 24 insertions(+), 87 deletions(-)
delete mode 100644 board/nvidia/p2571/max77620_init.c
diff --git a/board/nvidia/p2571/Makefile b/board/nvidia/p2571/Makefile
index 223062e..627b7ef 100644
--- a/board/nvidia/p2571/Makefile
+++ b/board/nvidia/p2571/Makefile
@@ -5,5 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += max77620_init.o
obj-y += p2571.o
diff --git a/board/nvidia/p2571/max77620_init.c
b/board/nvidia/p2571/max77620_init.c
deleted file mode 100644
index ed8d4dc..000
--- a/board/nvidia/p2571/max77620_init.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2013-2015
- * NVIDIA Corporation www.nvidia.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include common.h
-#include asm/io.h
-#include asm/arch-tegra/tegra_i2c.h
-#include max77620_init.h
-
-/* MAX77620-PMIC-specific early init code - get CPU rails up, etc */
-
-void tegra_i2c_ll_write_addr(uint addr, uint config)
-{
- struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
-
- writel(addr, reg-cmd_addr0);
- writel(config, reg-cnfg);
-}
-
-void tegra_i2c_ll_write_data(uint data, uint config)
-{
- struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
-
- writel(data, reg-cmd_data1);
- writel(config, reg-cnfg);
-}
-
-void pmic_enable_cpu_vdd(void)
-{
- uint reg;
- debug(%s entry\n, __func__);
-
- /* Setup/Enable GPIO5 - VDD_CPU_REG_EN */
- debug(%s: Setting GPIO5 to enable CPU regulator\n, __func__);
- /* B3=1=logic high,B2=dontcare,B1=0=output,B0=1=push-pull */
- reg = 0x0900 | MAX77620_GPIO5_REG;
- tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
- udelay(10 * 1000);
-
- /* Setup/Enable GPIO1 - VDD_HDMI_5V0_BST_EN */
- debug(%s: Setting GPIO1 to enable HDMI\n, __func__);
- reg = 0x0900 | MAX77620_GPIO1_REG;
- tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
- udelay(10 * 1000);
-
- /* GPIO 0,1,5,6,7 = GPIO, 2,3,4 = alt mode */
- reg = 0x1C00 | MAX77620_AME_GPIO;
- tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
- udelay(10 * 1000);
-
- /* Disable SD1 Remote Sense, Set SD1 for LPDDR4 to 1.125v */
- debug(%s: Set SD1 for LPDDR4, disable SD1RS, voltage to 1.125v\n,
- __func__);
- /* bit1=0, SD1 remote sense disabled */
- reg = 0x0400 | MAX77620_CNFG2SD_REG;
- tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
- udelay(10 * 1000);
-
- /* SD1 output = 1.125V */
- reg = 0x2A00 | MAX77620_SD1_REG;
- tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
- udelay(10 * 1000);
-
- debug(%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n, __func__);
- /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
- reg = 0xF200 | MAX77620_CNFG1_L2_REG;
- tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
- udelay(10 * 1000);
-
- debug(%s: Set LDO1 for USB3 phy power to 1.05V??\n, __func__);
- /* 0xCA for 105v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
- reg = 0xCA00 | MAX77620_CNFG1_L1_REG;
- tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
- udelay(10 * 1000);
-}
diff --git a/board/nvidia/p2571/max77620_init.h
b/board/nvidia/p2571/max77620_init.h
index 9d5cce7..92c3719 100644
--- a/board/nvidia/p2571/max77620_init.h
+++ b/board/nvidia/p2571/max77620_init.h
@@ -10,7 +10,8 @@
/* MAX77620-PMIC-specific early init regs */
-#define MAX77620_I2C_ADDR 0x78/* or 0x3C 7-bit */
+#define MAX77620_I2C_ADDR 0x78
+#define MAX77620_I2C_ADDR_7BIT 0x3C
#define MAX77620_SD0_REG 0x16
#define MAX77620_SD1_REG 0x17
diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c
index fc710c1..842242c 100644
--- a/board/nvidia/p2571/p2571.c
+++ b/board/nvidia/p2571/p2571.c
@@ -6,10 +6,32 @@
*/
#include common.h
+#include i2c.h
#include asm/arch/gpio.h
#include asm/arch/pinmux.h
+#include max77620_init.h
#include pinmux-config-p2571.h
+void pin_mux_mmc(void)
+{
+ struct udevice *dev;
+ uchar val;
+ int ret;
+
+ /* Turn on MAX77620 LDO2 to 3.3V for SD card power */
+ debug(%s: Set LDO2
[U-Boot] [PATCH] T210: P2571: Restore USB gadget mode (ums)
The tegra-common-usb-gadget.h include was causing some build problems in ci_udc.c with a 64-bit gcc in an earlier version of the T210 patches, but it is working fine now, so restore it. Signed-off-by: Tom Warren twar...@nvidia.com --- include/configs/p2571.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/p2571.h b/include/configs/p2571.h index 77faf5f..d39fa2a 100644 --- a/include/configs/p2571.h +++ b/include/configs/p2571.h @@ -68,6 +68,7 @@ * TODO(twar...@nvidia.com) - add tegra-common-usb-gadget.h back * breaks 64-bit build in ci_udc.c */ +#include tegra-common-usb-gadget.h #include tegra-common-post.h #define COUNTER_FREQUENCY 3840 -- 1.8.2.1.610.g562af5b ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/2] arch: Make board selection choices optional
Hi Joe, On Wed, 2015-05-13 at 10:11 +0900, Masahiro Yamada wrote: Hi Joe, 2015-05-13 7:12 GMT+09:00 Tom Rini tr...@konsulko.com: diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index c044ad4..85fddd2 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -132,6 +132,7 @@ config ARC_CACHE_LINE_SHIFT choice prompt Target select + optional config TARGET_DUMMY bool Dummy target You do not need to add optional to the ARC board select because Alexey intentionally added TARGET_DUMMY to the top of the board select list. This is another solution to not lose any CONFIG_BOARD_ by savedefconfig although I personally prefer this idea very much. Looks like I discover an issue that happens with that change. If one attempts to do something like: --8-- yes | make oldconfig on defconfig --8-- (that trick is done by automated build frameworks like Buildroot that prefer to not do xxx_defconfig explicitly, but modify that defconfig and later expand it to a full-scale .config) target won't be set because on prompt you'll see something like that: --8-- Target select [N/y] (NEW) --8-- See default answer here is No! Which later on attempt to do a build causes: --8-- $ make scripts/kconfig/conf --silentoldconfig Kconfig # # configuration written to .config # CHK include/config.h UPD include/config.h GEN include/autoconf.mk In file included from ./include/common.h:18:0: include/config.h:5:22: fatal error: configs/.h: No such file or directory #include configs/.h ^ compilation terminated. scripts/Makefile.autoconf:72: recipe for target 'include/autoconf.mk' failed make[1]: *** [include/autoconf.mk] Error 1 --8-- If optional is removed from choice - prompt Target select then target is selected by default and build runs smoothly. Any thoughts on how to fix it? -Alexey ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V3 6/6] T210: Add support for 64-bit T210-based P2571 board
On 07/29/2015 05:07 AM, Thierry Reding wrote: On Tue, Jul 28, 2015 at 01:27:07PM -0600, Stephen Warren wrote: On 07/24/2015 04:01 PM, Tom Warren wrote: Based on Venice2, incorporates Stephen Warren's latest P2571 pinmux table. With Thierry Reding's 64-bit build fixes, this will build and and boot in 64-bit on my P2571 (when used with a 32-bit AVP loader). diff --git a/board/nvidia/p2571/max77620_init.c b/board/nvidia/p2571/max77620_init.c +void pmic_enable_cpu_vdd(void) This function is never called, or even linked into the binary. For previous Tegra SoCs, it was called from the SPL before booting the CCPLEX. Since there is no SPL for Tegra210, nothing calls this. + debug(%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n, __func__); + /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + reg = 0xF200 | MAX77620_CNFG1_L2_REG; + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); + tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); + udelay(10 * 1000); This explains why the SD card isn't working for me on p2371-2180; I guess the PMIC OTP on that board has this regulator disabled, and since this code never runs, it never gets turned on. If I manually turn it on using the i2c command, then mmc dev 1 works. For p2571, I think we should either delete this file entirely. Or, at least strip it down so that it's not touching global PMIC configuration but rather just enabling any non-CCPLEX rails that U-Boot might need such as SD card and USB, then rename the function and arrange for it to be called from somewhere. I'm not sure what a good name and call-site would be yet. Have you looked at my P2371 support patches? Specifically commit ARM: tegra: Add NVIDIA P2371 support has the board-level code that I've used to boot upstream on the device. There's a board_mmc_power_init() implementation which overrides the weak dummy provided in drivers/mmc/mmc.c. Do you have a git repo and branch link? I wasn't aware that U-Boot had been ported to either p2371, so I re-created the support for those boards yesterday for L4T's U-Boot, and I was planning to cherry-pick them into upstream U-Boot and retest that today. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/4] nand: lpc32xx: add hardware ECC support
On Wednesday, July 29, 2015 at 06:14:08 PM, slemieux.t...@gmail.com wrote:
Hi!
[...]
+#if defined(CONFIG_DMA_LPC32XX) !defined(CONFIG_SPL_BUILD)
+/* Prepares DMA descriptors for NAND RD/WR operations */
+/* If the size is 256 Bytes then it is assumed to be
+ * an OOB transfer */
+static void lpc32xx_nand_dma_configure(struct nand_chip *chip,
+const void *buffer, int size, int read)
+{
+ uint32_t i, dmasrc, ctrl, ecc_ctrl, oob_ctrl, dmadst;
+ void __iomem *base = chip-IO_ADDR_R;
+ uint32_t *ecc_gen = ecc_buffer;
+
+ /* CTRL descriptor entry for reading ECC
+ * Copy Multiple times to sync DMA with Flash Controller
+ */
+ ecc_ctrl = (0x5 |
+ DMAC_CHAN_SRC_BURST_1 |
+ DMAC_CHAN_DEST_BURST_1 |
+ DMAC_CHAN_SRC_WIDTH_32 |
+ DMAC_CHAN_DEST_WIDTH_32 |
+ DMAC_CHAN_DEST_AHB1);
The outer parenthesis are not needed.
+ /* CTRL descriptor entry for reading/writing Data */
+ ctrl = 64 | /* 256/4 */
+ DMAC_CHAN_SRC_BURST_4 |
+ DMAC_CHAN_DEST_BURST_4 |
+ DMAC_CHAN_SRC_WIDTH_32 |
+ DMAC_CHAN_DEST_WIDTH_32 |
+ DMAC_CHAN_DEST_AHB1;
[...]
+ for (i = 0; i size/256; i++) {
You might want to introduce a variable here to avoid this constant
dma_list[i*2]. Also, fix the datatypes to zap the insane casts all
around.
+ dmalist[i*2].dma_src = (read ? (dmasrc) : (dmasrc + (i*256)));
+ dmalist[i*2].dma_dest = (read ? (dmadst + (i*256)) : dmadst);
+ dmalist[i*2].next_lli = (uint32_t)dmalist[(i*2)+1];
+ dmalist[i*2].next_ctrl = ctrl;
+
+ dmalist[(i*2) + 1].dma_src =
+ (uint32_t)(base + offsetof(struct lpc32xx_nand_slc_regs,
+ecc));
+ dmalist[(i*2) + 1].dma_dest = (uint32_t)ecc_gen[i];
+ dmalist[(i*2) + 1].next_lli = (uint32_t)dmalist[(i*2)+2];
+ dmalist[(i*2) + 1].next_ctrl = ecc_ctrl;
+ }
+
+ if (i) { /* Data only transfer */
+ dmalist[(i*2) - 1].next_lli = 0;
+ dmalist[(i*2) - 1].next_ctrl |= DMAC_CHAN_INT_TC_EN;
+ return;
+ }
+
+ /* OOB only transfer */
+ if (read) {
+ dmasrc = (uint32_t)(base +
+ offsetof(struct lpc32xx_nand_slc_regs,
+ dma_data));
+ dmadst = (uint32_t)(buffer);
+ oob_ctrl |= DMAC_CHAN_DEST_AUTOINC;
+ } else {
+ dmadst = (uint32_t)(base +
+ offsetof(struct lpc32xx_nand_slc_regs,
+ dma_data));
+ dmasrc = (uint32_t)(buffer);
+ oob_ctrl |= DMAC_CHAN_SRC_AUTOINC;
+ }
+
+ /* Read/ Write Spare Area Data To/From Flash */
+ dmalist[i*2].dma_src = dmasrc;
+ dmalist[i*2].dma_dest = dmadst;
+ dmalist[i*2].next_lli = 0;
+ dmalist[i*2].next_ctrl = (oob_ctrl | DMAC_CHAN_INT_TC_EN);
+}
[...]
static void lpc32xx_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
+#if defined(CONFIG_DMA_LPC32XX) !defined(CONFIG_SPL_BUILD)
I'm not a big fan of those ifdefs -- why not use DMA even in SPL ?
+ lpc32xx_nand_xfer(mtd, buf, len, 1);
+#else
while (len-- 0)
*buf++ = readl(lpc32xx_nand_slc_regs-data);
+#endif
}
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Re: [U-Boot] [PATCH v2 1/4] dma: lpc32xx: add DMA driver
On Wednesday, July 29, 2015 at 06:14:07 PM, slemieux.t...@gmail.com wrote:
From: Sylvain Lemieux slemi...@tycoint.com
Incorporate DMA driver from legacy LPCLinux NXP BSP.
The files taken from the legacy patch are:
- lpc32xx DMA driver
- lpc3250 header file DMA registers definition.
The legacy driver was updated to integrate with the latest u-boot.
Signed-off-by: Sylvain Lemieux slemi...@tycoint.com
[...]
diff --git a/drivers/dma/lpc32xx_dma.c b/drivers/dma/lpc32xx_dma.c
new file mode 100644
index 000..feb16ce
--- /dev/null
+++ b/drivers/dma/lpc32xx_dma.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright (C) 2008-2015 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: LPC3250 DMA controller interface support functions
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/arch/dma.h
+#include asm/arch/cpu.h
+#include asm/arch/clk.h
+#include asm/arch/sys_proto.h
+#include asm/io.h
+
+/* Some optimization stuff */
+#ifndef unlikely
+#define likely(x)__builtin_expect(!!(x), 1)
+#define unlikely(x) __builtin_expect(!!(x), 0)
+#endif
This is defined in include/compiler.h
+/* bit position macro */
+#define _BIT(n) (0x1 (n))
Drop this as well please.
+/* DMA controller channel register structure */
+struct dmac_chan_reg {
+ uint32_t src_addr;
+ uint32_t dest_addr;
+ uint32_t lli;
+ uint32_t control;
+ uint32_t config_ch;
+ uint32_t reserved[3];
+};
+
+/* DMA controller register structures */
+struct dma_reg {
+ uint32_t int_stat;
+ uint32_t int_tc_stat;
+ uint32_t int_tc_clear;
+ uint32_t int_err_stat;
+ uint32_t int_err_clear;
+ uint32_t raw_tc_stat;
+ uint32_t raw_err_stat;
+ uint32_t chan_enable;
+ uint32_t sw_burst_req;
+ uint32_t sw_single_req;
+ uint32_t sw_last_burst_req;
+ uint32_t sw_last_single_req;
+ uint32_t config;
+ uint32_t sync;
+ uint32_t reserved[50];
+ struct dmac_chan_reg dma_chan[8];
+};
+
+/* Macro pointing to DMA registers */
+#define DMA_NO_OF_CHANNELS 8
+
+/* config register definitions */
+#define DMAC_CTRL_ENABLE (1 0) /* For enabling the DMA controller */
+
+static uint32_t alloc_ch;
+
+static struct dma_reg *dma = (struct dma_reg *)DMA_BASE;
+
+int lpc32xx_dma_get_channel(void)
+{
+ int i;
+ uint32_t status = 0;
+
+ if (!alloc_ch) { /* First time caller */
+ /* DMA clock are enable by lpc32xx_dma_init() and should
+ * be call by board board_early_init_f() function. */
+
+ /* Make sure DMA controller and all channels are disabled.
+ * Controller is in little-endian mode. Disable sync signals */
+ writel(0, dma-config);
+ writel(0, dma-sync);
+
+ /* Clear interrupt and error statuses */
+ writel(0xFF, dma-int_tc_clear);
+ writel(0xFF, dma-raw_tc_stat);
+ writel(0xFF, dma-int_err_clear);
+ writel(0xFF, dma-raw_err_stat);
+
+ /* Enable DMA controller */
+ writel(DMAC_CTRL_ENABLE, dma-config);
+ }
+
+ for (i = 0; i DMA_NO_OF_CHANNELS (status _BIT(i)); i++)
+ ;
I think you should look at ffs() and fls() in include/linux/bitops.h here.
[...]
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Re: [U-Boot] [PATCH v2 1/4] dma: lpc32xx: add DMA driver
On Wednesday, July 29, 2015 at 07:07:44 PM, LEMIEUX, SYLVAIN wrote: Hi Marek, Thanks for the feedback; I will look into it and submit an updated version once I get feedback for the other patches. Thanks :) Wait a bit for further feedback please . Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/4] nand: lpc32xx: add hardware ECC support
Hi Marek, Sylvain,
On 29.07.2015 19:50, Marek Vasut wrote:
On Wednesday, July 29, 2015 at 06:14:08 PM, slemieux.t...@gmail.com wrote:
[snip]
static void lpc32xx_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
+#if defined(CONFIG_DMA_LPC32XX) !defined(CONFIG_SPL_BUILD)
I'm not a big fan of those ifdefs -- why not use DMA even in SPL ?
I think the main reason is that DMA in SPL has not been tested yet.
If needed (?) the dependency between DMA and SPL may be described
separately, e.g.
+#if defined(CONFIG_DMA_LPC32XX) defined(CONFIG_SPL_BUILD)
+#warning DMA support in SPL image is not tested
+#endif
Regarding this particular #ifdef case I suppose just
+#if defined(CONFIG_DMA_LPC32XX)
is good enough here, either it is SPL or U-boot.
+lpc32xx_nand_xfer(mtd, buf, len, 1);
+#else
while (len-- 0)
*buf++ = readl(lpc32xx_nand_slc_regs-data);
+#endif
}
I would propose to add another pair of DMA specific
lpc32xx_read_buf()/lpc32xx_write_buf() functions chosen under
CONFIG_DMA_LPC32XX condition, this might improve readability.
--
With best wishes,
Vladimir
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Re: [U-Boot] Please pull u-boot-x86
On Tue, Jul 28, 2015 at 11:42:22AM -0600, Simon Glass wrote: Hi Tom, Here are some more PCI driver model improvements and better interrupt support on x86. The following changes since commit 66d10c18bf2c34698362b6fe1891bcc6e8755243: Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze (2015-07-28 11:31:21 -0400) are available in the git repository at: git://git.denx.de/u-boot-x86.git for you to fetch changes up to 488d19cbcace0b87a2d08881eab7356088198903: patman: add distutils based installer (2015-07-28 10:36:25 -0600) Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 4/4] usb: lpc32xx: add host USB driver
From: Sylvain Lemieux slemi...@tycoint.com
Incorporate USB driver from legacy LPCLinux NXP BSP.
The files taken from the legacy patch are:
- lpc32xx USB driver
- lpc3250 header file USB registers definition.
The legacy driver was updated to integrate with the latest u-boot.
Signed-off-by: Sylvain Lemieux slemi...@tycoint.com
---
Changes from v1 to v2:
* Addressed Marek's comments on LPC32xx USB driver:
- use get_timer() to handle timeout.
- Split USB and I2C driver.
* Updated LPC32xx I2C driver to support the I2C that is part
of the USB module.
* Removed ISP1301 USB transceiver I2C registers definition
that are not used.
* Use cpu initialization stop functions API instead of the board API.
Update to the legacy driver to integrate with the latest u-boot:
1) Fixed checkpatch script output in legacy code.
2) Use LPC32xx definition from cpu.h and clk.h.
3) Incorporate USB specific register definition from lpc3250.h
header file from legacy BSP patch from LPCLinux.
4) Use u-boot API for register access to remove the volatile
in register definition taken from lpc3250.h header file.
5) Update driver for latest u-boot USB API.
6) Use the peripheral clock to compute the I2C divider.
The legacy BSP patch (u-boot-2009.03_lpc32x0-v1.07.patch.tar.bz2)
was downloaded from the LPCLinux Web site.
arch/arm/include/asm/arch-lpc32xx/clk.h | 12 ++
drivers/i2c/lpc32xx_i2c.c | 20 ++-
drivers/usb/host/Makefile | 1 +
drivers/usb/host/ohci-lpc32xx.c | 245
4 files changed, 275 insertions(+), 3 deletions(-)
create mode 100644 drivers/usb/host/ohci-lpc32xx.c
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h
b/arch/arm/include/asm/arch-lpc32xx/clk.h
index 663f6bc..d21310e 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -167,6 +167,18 @@ struct clk_pm_regs {
/* SDRAMCLK register bits */
#define CLK_SDRAM_DDR_SEL (1 1)
+/* USB control register definitions */
+#define CLK_USBCTRL_PLL_STS(1 0)
+#define CLK_USBCTRL_FDBK_PLUS1(n) (((n) 0xFF) 1)
+#define CLK_USBCTRL_POSTDIV_2POW(n)(((n) 0x3) 11)
+#define CLK_USBCTRL_PLL_PWRUP (1 16)
+#define CLK_USBCTRL_CLK_EN1(1 17)
+#define CLK_USBCTRL_CLK_EN2(1 18)
+#define CLK_USBCTRL_BUS_KEEPER (0x1 19)
+#define CLK_USBCTRL_USBHSTND_EN(1 21)
+#define CLK_USBCTRL_USBDVND_EN (1 22)
+#define CLK_USBCTRL_HCLK_EN(1 24)
+
unsigned int get_sys_clk_rate(void);
unsigned int get_hclk_pll_rate(void);
unsigned int get_hclk_clk_div(void);
diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c
index 98106fa..be166b0 100644
--- a/drivers/i2c/lpc32xx_i2c.c
+++ b/drivers/i2c/lpc32xx_i2c.c
@@ -1,7 +1,7 @@
/*
* LPC32xx I2C interface driver
*
- * (C) Copyright 2014 DENX Software Engineering GmbH
+ * (C) Copyright 2014-2015 DENX Software Engineering GmbH
* Written-by: Albert ARIBAUD - 3ADEV albert.arib...@3adev.fr
*
* SPDX-License-Identifier:GPL-2.0+
@@ -60,7 +60,8 @@ struct lpc32xx_i2c_registers {
static struct lpc32xx_i2c_registers *lpc32xx_i2c[] = {
(struct lpc32xx_i2c_registers *)I2C1_BASE,
- (struct lpc32xx_i2c_registers *)I2C2_BASE
+ (struct lpc32xx_i2c_registers *)I2C2_BASE,
+ (struct lpc32xx_i2c_registers *)(USB_BASE + 0x300)
};
/* Set I2C bus speed */
@@ -68,11 +69,17 @@ static unsigned int lpc32xx_i2c_set_bus_speed(struct
i2c_adapter *adap,
unsigned int speed)
{
int half_period;
+ int clk_rate;
if (speed == 0)
return -EINVAL;
- half_period = (get_hclk_clk_rate() / speed) / 2;
+ if (adap-hwadapnr == 2)
+ /* OTG I2C clock source is different. */
+ clk_rate = get_periph_clk_rate();
+ else
+ clk_rate = get_hclk_clk_rate();
+ half_period = (clk_rate / speed) / 2;
if ((half_period 255) || (half_period 0))
return -EINVAL;
@@ -247,3 +254,10 @@ U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, _i2c_init,
lpc32xx_i2c_probe,
CONFIG_SYS_I2C_LPC32XX_SPEED,
CONFIG_SYS_I2C_LPC32XX_SLAVE,
1)
+
+U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2, _i2c_init, NULL,
+lpc32xx_i2c_read, lpc32xx_i2c_write,
+lpc32xx_i2c_set_bus_speed,
+10,
+0,
+2)
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 4d35d3e..9dfdc94 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_USB_SL811HS) += sl811-hcd.o
obj-$(CONFIG_USB_OHCI_S3C24XX) += ohci-s3c24xx.o
obj-$(CONFIG_USB_OHCI_EP93XX) += ohci-ep93xx.o
obj-$(CONFIG_USB_OHCI_SUNXI) += ohci-sunxi.o
+obj-$(CONFIG_USB_OHCI_LPC32XX) += ohci-lpc32xx.o
# echi
Re: [U-Boot] [PATCH] mpc85xx/T104xRDB: Remove vbank check redundant code
On 07/29/2015 01:31 AM, Jain Priyanka-B32167 wrote: -Original Message- From: Sun York-R58495 Sent: Tuesday, July 28, 2015 12:37 AM To: Jain Priyanka-B32167; u-boot@lists.denx.de Subject: Re: [PATCH] mpc85xx/T104xRDB: Remove vbank check redundant code On 05/17/2015 11:31 PM, Priyanka Jain wrote: sw variable in checkboard function is storing vbank value which can only take 4-bit value. So check of sw value for if greater than 7 is redundant. Signed-off-by: Priyanka Jain priyanka.j...@freescale.com --- board/freescale/t104xrdb/t104xrdb.c |5 + 1 files changed, 1 insertions(+), 4 deletions(-) diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index 9cd5e15..c34eea6 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -35,10 +35,7 @@ int checkboard(void) sw = CPLD_READ(flash_ctl_status); sw = ((sw CPLD_LBMAP_MASK) CPLD_LBMAP_SHIFT); - if (sw = 7) - printf(vBank: %d\n, sw); - else - printf(Unsupported Bank=%x\n, sw); + printf(vBank: %d\n, sw); return 0; } Priyanka, 4-bit variable can still have value bigger than 7. Is there other reason you want to remove it? [Jain Priyanka-B32167] Sorry, Its 3-bit variable. So cannot have value greater than 7. CPLD_LBMAP_MASK is 0x3f and CPLD_LBMAB_SHIFT is of value 3. So it is basically bits sw[5], sw[4], sw[3]. If it is 3-bit value, it makes sense. Can you update the commit message? York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V3 6/6] T210: Add support for 64-bit T210-based P2571 board
-Original Message- From: Thierry Reding Sent: Wednesday, July 29, 2015 4:08 AM To: Stephen Warren Cc: Tom Warren; u-boot@lists.denx.de; Stephen Warren; tomcwarren3...@gmail.com Subject: Re: [U-Boot] [PATCH V3 6/6] T210: Add support for 64-bit T210-based P2571 board On Tue, Jul 28, 2015 at 01:27:07PM -0600, Stephen Warren wrote: On 07/24/2015 04:01 PM, Tom Warren wrote: Based on Venice2, incorporates Stephen Warren's latest P2571 pinmux table. With Thierry Reding's 64-bit build fixes, this will build and and boot in 64-bit on my P2571 (when used with a 32-bit AVP loader). diff --git a/board/nvidia/p2571/max77620_init.c b/board/nvidia/p2571/max77620_init.c +void pmic_enable_cpu_vdd(void) This function is never called, or even linked into the binary. For previous Tegra SoCs, it was called from the SPL before booting the CCPLEX. Since there is no SPL for Tegra210, nothing calls this. + debug(%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n, __func__); + /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + reg = 0xF200 | MAX77620_CNFG1_L2_REG; + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); + tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); + udelay(10 * 1000); This explains why the SD card isn't working for me on p2371-2180; I guess the PMIC OTP on that board has this regulator disabled, and since this code never runs, it never gets turned on. If I manually turn it on using the i2c command, then mmc dev 1 works. For p2571, I think we should either delete this file entirely. Or, at least strip it down so that it's not touching global PMIC configuration but rather just enabling any non-CCPLEX rails that U-Boot might need such as SD card and USB, then rename the function and arrange for it to be called from somewhere. I'm not sure what a good name and call-site would be yet. Have you looked at my P2371 support patches? Specifically commit ARM: tegra: Add NVIDIA P2371 support has the board-level code that I've used to boot upstream on the device. There's a board_mmc_power_init() implementation which overrides the weak dummy provided in drivers/mmc/mmc.c. Thierry There's also pin_mux_mmc() which a few Tegra boards are already using. I have an implementation for P2571 that I'll be uploading soon for review. Tom -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 00/11] USB and sunxi Kconfig and config changes leading up to fastboot support
On Wednesday, July 29, 2015 at 04:41:53 PM, Hans de Goede wrote: Hi, Hi! On 29-07-15 15:32, Paul Kocialkowski wrote: This series is based off the following patch: * drivers: hierarchize drivers Kconfig menu that was sent to the list earlier. Please pick it up as well when merging this series. The entire series looks good to me: Acked-by: Hans de Goede hdego...@redhat.com Marek, since this consists of mostly generic USB chaages I think it would be best for you to pick up this entire series. No, was I really such a good kid that I can pick an entire series again ? :-) Oh my ... Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/4] dma: lpc32xx: add DMA driver
Hi Marek,
Thanks for the feedback;
I will look into it and submit an updated version once I get feedback
for the other patches.
From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Marek Vasut
On Wednesday, July 29, 2015 at 06:14:07 PM, slemieux.t...@gmail.com wrote:
From: Sylvain Lemieux slemi...@tycoint.com
Incorporate DMA driver from legacy LPCLinux NXP BSP.
The files taken from the legacy patch are:
- lpc32xx DMA driver
- lpc3250 header file DMA registers definition.
The legacy driver was updated to integrate with the latest u-boot.
Signed-off-by: Sylvain Lemieux slemi...@tycoint.com
[...]
diff --git a/drivers/dma/lpc32xx_dma.c b/drivers/dma/lpc32xx_dma.c
new file mode 100644
index 000..feb16ce
--- /dev/null
+++ b/drivers/dma/lpc32xx_dma.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright (C) 2008-2015 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: LPC3250 DMA controller interface support functions
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/arch/dma.h
+#include asm/arch/cpu.h
+#include asm/arch/clk.h
+#include asm/arch/sys_proto.h
+#include asm/io.h
+
+/* Some optimization stuff */
+#ifndef unlikely
+#define likely(x) __builtin_expect(!!(x), 1)
+#define unlikely(x)__builtin_expect(!!(x), 0)
+#endif
This is defined in include/compiler.h
+/* bit position macro */
+#define _BIT(n)(0x1 (n))
Drop this as well please.
+/* DMA controller channel register structure */
+struct dmac_chan_reg {
+ uint32_t src_addr;
+ uint32_t dest_addr;
+ uint32_t lli;
+ uint32_t control;
+ uint32_t config_ch;
+ uint32_t reserved[3];
+};
+
+/* DMA controller register structures */
+struct dma_reg {
+ uint32_t int_stat;
+ uint32_t int_tc_stat;
+ uint32_t int_tc_clear;
+ uint32_t int_err_stat;
+ uint32_t int_err_clear;
+ uint32_t raw_tc_stat;
+ uint32_t raw_err_stat;
+ uint32_t chan_enable;
+ uint32_t sw_burst_req;
+ uint32_t sw_single_req;
+ uint32_t sw_last_burst_req;
+ uint32_t sw_last_single_req;
+ uint32_t config;
+ uint32_t sync;
+ uint32_t reserved[50];
+ struct dmac_chan_reg dma_chan[8];
+};
+
+/* Macro pointing to DMA registers */
+#define DMA_NO_OF_CHANNELS 8
+
+/* config register definitions */
+#define DMAC_CTRL_ENABLE (1 0) /* For enabling the DMA controller */
+
+static uint32_t alloc_ch;
+
+static struct dma_reg *dma = (struct dma_reg *)DMA_BASE;
+
+int lpc32xx_dma_get_channel(void)
+{
+ int i;
+ uint32_t status = 0;
+
+ if (!alloc_ch) { /* First time caller */
+ /* DMA clock are enable by lpc32xx_dma_init() and should
+* be call by board board_early_init_f() function. */
+
+ /* Make sure DMA controller and all channels are disabled.
+* Controller is in little-endian mode. Disable sync signals */
+ writel(0, dma-config);
+ writel(0, dma-sync);
+
+ /* Clear interrupt and error statuses */
+ writel(0xFF, dma-int_tc_clear);
+ writel(0xFF, dma-raw_tc_stat);
+ writel(0xFF, dma-int_err_clear);
+ writel(0xFF, dma-raw_err_stat);
+
+ /* Enable DMA controller */
+ writel(DMAC_CTRL_ENABLE, dma-config);
+ }
+
+ for (i = 0; i DMA_NO_OF_CHANNELS (status _BIT(i)); i++)
+ ;
I think you should look at ffs() and fls() in include/linux/bitops.h here.
[...]
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[U-Boot] [PATCH v2 2/4] nand: lpc32xx: add hardware ECC support
From: Sylvain Lemieux slemi...@tycoint.com
Incorporate NAND SLC hardware ECC support from legacy
LPCLinux NXP BSP.
The code taken from the legacy patch are:
- lpc32xx SLC NAND driver (hardware ECC support)
- lpc3250 header file missing SLC NAND registers definition
The legacy driver code was updated to integrate with the
esisting NAND SLC driver.
Signed-off-by: Sylvain Lemieux slemi...@tycoint.com
---
Changes from v1 to v2:
* Moved the NAND SLC patch as the second patch of the series.
* As per discussion on mailing list with Vladimir,
incorporate NAND SLC hardware ECC support into the following
NAND SLC patch: https://patchwork.ozlabs.org/patch/497308/
* As per discussion on mailing list with Vladimir Albert,
add conditional compile option to build the original
NAND SLC code using software ECC for SPL build.
* Removed ECC layout for small page NAND from this patch.
Update to the legacy code to integrate with the NAND SLC patch:
1) Fixed checkpatch script output in legacy code.
2) Use u-boot API for register access to remove the volatile
in register definition taken from lpc3250.h header file.
3) Use register definition from the NAND SLC patch.
The legacy BSP patch (u-boot-2009.03_lpc32x0-v1.07.patch.tar.bz2)
was downloaded from the LPCLinux Web site.
drivers/mtd/nand/lpc32xx_nand_slc.c | 337
1 file changed, 337 insertions(+)
diff --git a/drivers/mtd/nand/lpc32xx_nand_slc.c
b/drivers/mtd/nand/lpc32xx_nand_slc.c
index 719a74d..b8b33e3 100644
--- a/drivers/mtd/nand/lpc32xx_nand_slc.c
+++ b/drivers/mtd/nand/lpc32xx_nand_slc.c
@@ -8,10 +8,25 @@
#include common.h
#include nand.h
+#include linux/mtd/nand_ecc.h
#include asm/errno.h
#include asm/io.h
#include asm/arch/clk.h
#include asm/arch/sys_proto.h
+#include asm/arch/dma.h
+#include asm/arch/cpu.h
+
+/* Provide default for ECC size / bytes / OOB size for large page)
+ * if target did not. */
+#if !defined(CONFIG_SYS_NAND_ECCSIZE)
+#define CONFIG_SYS_NAND_ECCSIZE 2048
+#endif
+#if !defined(CONFIG_SYS_NAND_ECCBYTES)
+#define CONFIG_SYS_NAND_ECCBYTES 24
+#endif
+#if !defined(CONFIG_SYS_NAND_OOBSIZE)
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#endif
struct lpc32xx_nand_slc_regs {
u32 data;
@@ -33,11 +48,18 @@ struct lpc32xx_nand_slc_regs {
/* CFG register */
#define CFG_CE_LOW (1 5)
+#define SLCCFG_DMA_ECC (1 4) /* Enable DMA ECC bit */
+#define SLCCFG_ECC_EN (1 3) /* ECC enable bit */
+#define SLCCFG_DMA_BURST (1 2) /* DMA burst bit */
+#define SLCCFG_DMA_DIR (1 1) /* DMA write(0)/read(1) bit */
/* CTRL register */
#define CTRL_SW_RESET (1 2)
+#define SLCCTRL_ECC_CLEAR (1 1) /* Reset ECC bit */
+#define SLCCTRL_DMA_START (1 0) /* Start DMA channel bit */
/* STAT register */
+#define SLCSTAT_DMA_FIFO (1 2) /* DMA FIFO has data bit */
#define STAT_NAND_READY(1 0)
/* INT_STAT register */
@@ -54,6 +76,47 @@ struct lpc32xx_nand_slc_regs {
#define TAC_R_HOLD(n) (max_t(uint32_t, (n), 0xF) 4)
#define TAC_R_SETUP(n) (max_t(uint32_t, (n), 0xF) 0)
+/* control register definitions */
+#define DMAC_CHAN_INT_TC_EN(1 31) /* channel terminal count interrupt */
+#define DMAC_CHAN_DEST_AUTOINC (1 27) /* automatic destination increment */
+#define DMAC_CHAN_SRC_AUTOINC (1 26) /* automatic source increment */
+#define DMAC_CHAN_DEST_AHB1(1 25) /* AHB1 master for dest. transfer */
+#define DMAC_CHAN_DEST_WIDTH_32(1 22) /* Destination data width
selection */
+#define DMAC_CHAN_SRC_WIDTH_32 (1 19) /* Source data width selection */
+#define DMAC_CHAN_DEST_BURST_1 0
+#define DMAC_CHAN_DEST_BURST_4 (1 15) /* Destination data burst size */
+#define DMAC_CHAN_SRC_BURST_1 0
+#define DMAC_CHAN_SRC_BURST_4 (1 12) /* Source data burst size */
+
+/* config_ch register definitions
+ * DMAC_CHAN_FLOW_D_xxx: flow control with DMA as the controller
+ * DMAC_DEST_PERIP: Macro for loading destination peripheral
+ * DMAC_SRC_PERIP: Macro for loading source peripheral */
+#define DMAC_CHAN_FLOW_D_M2P (0x1 11)
+#define DMAC_CHAN_FLOW_D_P2M (0x2 11)
+#define DMAC_DEST_PERIP(n) (((n) 0x1F) 6)
+#define DMAC_SRC_PERIP(n) (((n) 0x1F) 1)
+
+/* config_ch register definitions
+ * (source and destination peripheral ID numbers).
+ * These can be used with the DMAC_DEST_PERIP and DMAC_SRC_PERIP macros.*/
+#define DMA_PERID_NAND11
+
+/* Channel enable bit */
+#define DMAC_CHAN_ENABLE (1 0)
+
+#define NAND_LARGE_BLOCK_PAGE_SIZE 2048
+#define NAND_SMALL_BLOCK_PAGE_SIZE 512
+
+#if defined(CONFIG_DMA_LPC32XX) !defined(CONFIG_SPL_BUILD)
+/* DMA Descriptors
+ * For Large Block: 17 descriptors = ((16 Data and ECC Read) + 1 Spare Area)
+ * For Small Block: 5 descriptors = ((4 Data and ECC Read) + 1 Spare Area) */
+static dmac_ll_t dmalist[(CONFIG_SYS_NAND_ECCSIZE/256) * 2 + 1];
+static uint32_t ecc_buffer[8]; /* MAX ECC size */
+static int
[U-Boot] [PATCH v2 3/4] nand: lpc32xx: add ECC layout for small page NAND
From: Sylvain Lemieux slemi...@tycoint.com
Incorporate ECC layout for small page NAND from legacy
LPCLinux NXP BSP.
The code taken from the legacy patch is:
- lpc32xx SLC NAND driver (ECC layout for small page)
This layout is matching the lpc32xx NAND SLC Kernel driver:
https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/tree/drivers/mtd/nand/lpc32xx_slc.c?id=refs/tags/v4.1.3
Signed-off-by: Sylvain Lemieux slemi...@tycoint.com
---
Changes from v1 to v2:
* Move ECC layout for small page NAND into a separate patch.
The legacy BSP patch (u-boot-2009.03_lpc32x0-v1.07.patch.tar.bz2)
was downloaded from the LPCLinux Web site.
drivers/mtd/nand/lpc32xx_nand_slc.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/mtd/nand/lpc32xx_nand_slc.c
b/drivers/mtd/nand/lpc32xx_nand_slc.c
index b8b33e3..14f66dd 100644
--- a/drivers/mtd/nand/lpc32xx_nand_slc.c
+++ b/drivers/mtd/nand/lpc32xx_nand_slc.c
@@ -108,6 +108,19 @@ struct lpc32xx_nand_slc_regs {
#define NAND_LARGE_BLOCK_PAGE_SIZE 2048
#define NAND_SMALL_BLOCK_PAGE_SIZE 512
+/* NAND ECC Layout for small page NAND devices
+ * Note: For large page devices, the default layouts are used. */
+static struct nand_ecclayout lpc32xx_nand_oob_16 = {
+ .eccbytes = 6,
+ .eccpos = {10, 11, 12, 13, 14, 15},
+ .oobfree = {
+ {.offset = 0,
+. length = 4},
+ {.offset = 6,
+. length = 4}
+ }
+};
+
#if defined(CONFIG_DMA_LPC32XX) !defined(CONFIG_SPL_BUILD)
/* DMA Descriptors
* For Large Block: 17 descriptors = ((16 Data and ECC Read) + 1 Spare Area)
@@ -502,6 +515,9 @@ int board_nand_init(struct nand_chip *lpc32xx_chip)
#endif
lpc32xx_chip-ecc.strength = 1;
+ if (CONFIG_SYS_NAND_ECCSIZE != NAND_LARGE_BLOCK_PAGE_SIZE)
+ lpc32xx_chip-ecc.layout = lpc32xx_nand_oob_16;
+
#if defined(CONFIG_SYS_NAND_USE_FLASH_BBT)
lpc32xx_chip-bbt_options |= NAND_BBT_USE_FLASH;
#endif
--
1.8.3.1
___
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U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 0/4] lpc32xx: add legacy NXP BSP drivers
From: Sylvain Lemieux slemi...@tycoint.com This series of patches bring the legacy NXP LPC32xx BSP drivers SLC NAND (hardware ECC), DMA USB into the latest u-boot. Refer to each individual patches for details on the change done to integrate the driver into the latest u-boot. The legacy BSP patch (u-boot-2009.03_lpc32x0-v1.07.patch.tar.bz2) was downloaded from the LPCLinux Web site. The patch adding the LPC32xx MAC and SMSC RMII phy support should be applied first: - http://patchwork.ozlabs.org/patch/489100/ - http://patchwork.ozlabs.org/patch/489190/ - http://patchwork.ozlabs.org/patch/491419/ - http://patchwork.ozlabs.org/patch/491420/ The SLC NAND patch should be applied after: - https://patchwork.ozlabs.org/patch/497308/ The patch modifying the I2C to use the HCLK get API function should be applied after the SLC NAND patch: - https://patchwork.ozlabs.org/patch/500511/ The NAND driver was only tested for large page NAND. Potential test opportunity for small page NAND: - Since the equivalent of the legacy NXP BSP drivers are available (NAND SLC / DMA / Ethernet / USB), it will be nice if somebody using the PHY3250 development board can test small pafe NAND. - The remaining porting work to the latest u-boot include the migration of the board configuration files. Changes from v1 to v2: * Moved the DMA patch as the first patch of the series and the NAND SLC patch as thesecond one. * As per discussion on mailing list with Vladimir, incorporate NAND SLC hardware ECC support into the following NAND SLC patch: https://patchwork.ozlabs.org/patch/497308/ * As per discussion on mailing list with Vladimir Albert, add conditional compile option to build the original NAND SLC code using software ECC for SPL build. * Moved ECC layout for small page NAND in a separate patch. * Addressed Marek's comments on LPC32xx USB driver: - use get_timer() to handle timeout. - Split USB and I2C driver. * Updated LPC32xx I2C driver to support the I2C that is part of the USB module. * Removed ISP1301 USB transceiver I2C registers definition that are not used. * For the USB driver, use cpu initialization stop functions API instead of the board API. Note: I am sending the patches using slemieux.t...@gmail.com, until I can submit patch using my regular e-mail slemi...@tycoint.com. Sylvain Lemieux (4): dma: lpc32xx: add DMA driver nand: lpc32xx: add hardware ECC support nand: lpc32xx: add ECC layout for small page NAND usb: lpc32xx: add host USB driver arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 6 + arch/arm/include/asm/arch-lpc32xx/clk.h | 15 ++ arch/arm/include/asm/arch-lpc32xx/dma.h | 33 +++ arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 + drivers/dma/Makefile | 1 + drivers/dma/lpc32xx_dma.c | 153 +++ drivers/i2c/lpc32xx_i2c.c | 21 +- drivers/mtd/nand/lpc32xx_nand_slc.c | 351 ++ drivers/usb/host/Makefile | 1 + drivers/usb/host/ohci-lpc32xx.c | 245 ++ 10 files changed, 823 insertions(+), 4 deletions(-) create mode 100644 arch/arm/include/asm/arch-lpc32xx/dma.h create mode 100644 drivers/dma/lpc32xx_dma.c create mode 100644 drivers/usb/host/ohci-lpc32xx.c -- 1.8.3.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/4] dma: lpc32xx: add DMA driver
From: Sylvain Lemieux slemi...@tycoint.com
Incorporate DMA driver from legacy LPCLinux NXP BSP.
The files taken from the legacy patch are:
- lpc32xx DMA driver
- lpc3250 header file DMA registers definition.
The legacy driver was updated to integrate with the latest u-boot.
Signed-off-by: Sylvain Lemieux slemi...@tycoint.com
---
Changes from v1 to v2:
* Moved the DMA patch as the first patch of the series.
* The NAND SLC patch (link below) is applied before this
patch: https://patchwork.ozlabs.org/patch/497308/
Update to the legacy driver to integrate with the latest u-boot:
1) Fixed checkpatch script output in legacy code.
2) Use LPC32xx definition from cpu.h and clk.h.
3) Incorporate DMA specific register definition from lpc3250.h
header file from legacy BSP patch from LPCLinux.
4) Use u-boot API for register access to remove the volatile
in register definition taken from lpc3250.h header file.
5) Add DMA interface to dma.h.
6) Add dma clock control register bits (clk.h).
7) Add functions to initialize the DMA clock.
The legacy BSP patch (u-boot-2009.03_lpc32x0-v1.07.patch.tar.bz2)
was downloaded from the LPCLinux Web site.
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 6 +
arch/arm/include/asm/arch-lpc32xx/clk.h | 3 +
arch/arm/include/asm/arch-lpc32xx/dma.h | 33 ++
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/dma/Makefile | 1 +
drivers/dma/lpc32xx_dma.c | 153 ++
6 files changed, 197 insertions(+)
create mode 100644 arch/arm/include/asm/arch-lpc32xx/dma.h
create mode 100644 drivers/dma/lpc32xx_dma.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index c0c9c6c..0d2ef7a 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -65,6 +65,12 @@ void lpc32xx_slc_nand_init(void)
writel(CLK_NAND_SLC | CLK_NAND_SLC_SELECT, clk-flashclk_ctrl);
}
+void lpc32xx_dma_init(void)
+{
+ /* Enable DMA interface */
+ setbits_le32(clk-dmaclk_ctrl, DMA_CLK_ENABLE);
+}
+
void lpc32xx_i2c_init(unsigned int devnum)
{
/* Enable I2C interface */
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h
b/arch/arm/include/asm/arch-lpc32xx/clk.h
index 010211a..663f6bc 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -158,6 +158,9 @@ struct clk_pm_regs {
#define CLK_NAND_SLC_SELECT(1 2)
#define CLK_NAND_MLC_INT (1 5)
+/* DMA Clock Control Register bits */
+#define DMA_CLK_ENABLE (1 0)
+
/* SSP Clock Control Register bits */
#define CLK_SSP0_ENABLE_CLOCK (1 0)
diff --git a/arch/arm/include/asm/arch-lpc32xx/dma.h
b/arch/arm/include/asm/arch-lpc32xx/dma.h
new file mode 100644
index 000..7b467a2
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/dma.h
@@ -0,0 +1,33 @@
+/*
+ * LPC32xx DMA Controller Interface
+ *
+ * Copyright (C) 2008-2015 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr: Definitions for LPC3250 chip
+ * @References: NXP LPC3250 User's Guide
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _LPC32XX_DMA_H
+#define _LPC32XX_DMA_H
+
+#include common.h
+
+/* DMA linked list structure used with a channel's LLI register */
+typedef struct
+{
+ volatile uint32_t dma_src;
+ volatile uint32_t dma_dest;
+ volatile uint32_t next_lli;
+ volatile uint32_t next_ctrl;
+} dmac_ll_t;
+
+int lpc32xx_dma_get_channel(void);
+int lpc32xx_dma_start_xfer(int channel, const dmac_ll_t *desc, uint32_t
config);
+int lpc32xx_dma_wait_status(int channel);
+void lpc32xx_dma_put_channel(int channel);
+
+#endif /* _LPC32XX_DMA_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index 0845f83..7f997d9 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -13,6 +13,7 @@ void lpc32xx_uart_init(unsigned int uart_id);
void lpc32xx_mac_init(void);
void lpc32xx_mlc_nand_init(void);
void lpc32xx_slc_nand_init(void);
+void lpc32xx_dma_init(void);
void lpc32xx_i2c_init(unsigned int devnum);
void lpc32xx_ssp_init(void);
#if defined(CONFIG_SPL_BUILD)
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 4c8fcc2..f95fe70 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_APBH_DMA) += apbh_dma.o
obj-$(CONFIG_FSL_DMA) += fsl_dma.o
obj-$(CONFIG_TI_KSNAV) += keystone_nav.o keystone_nav_cfg.o
obj-$(CONFIG_TI_EDMA3) += ti-edma3.o
+obj-$(CONFIG_DMA_LPC32XX) += lpc32xx_dma.o
diff --git a/drivers/dma/lpc32xx_dma.c b/drivers/dma/lpc32xx_dma.c
new file mode 100644
index 000..feb16ce
--- /dev/null
+++ b/drivers/dma/lpc32xx_dma.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright (C) 2008-2015 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Kevin Wells
+ * @Descr:
[U-Boot] Driver for SD card in Odroid-X2
Hi community, my team and I are working on the implementation of a driver for SD cards in the ODROID-X2 (exynos4412). This driver we want to incorporate into the framework GenodeOS, but we have some doubts in implementation. Below I list a few: 1- We are implementing the controller DWMMC. This is the right controller to handle the SD card in the exynos4412? The SDHCI controller is most appropriate? 2- What exynos4412 SoC base address should be used for handling the SD card? 3- What is the IRQ associated with handling SD tajetas with DWMMC controller? 4- To use the DWMMC controller you need to configure GPIO ports? 5- What clocks should be initialized to handle SD cards? Anybody know any document that describes the initialization process of an SD card? We have been reviewing the implementation of the driver for the SD card in the U-Boot and Linux kernel, but have not resolved the questions above. Thank you for your help !! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] net: lpc32xx: add RMII phy mode support
From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Vladimir Zapolskiy Sent: 6-Jul-15 12:22 AM LPC32xx MAC and clock control configuration requires some minor quirks to deal with a phy connected by RMII. It's worth to mention that the kernel and legacy BSP from NXP sets SUPP_RESET_RMII == (1 11) bit, however the description of this bit is missing in shared LPC32x0 User Manual UM10326 Rev. 3, July 22, 2011 and in LPC32x0 Draft User Mannual Rev. 00.27, November 20, 2008, also in my tests an SMSC LAN8700 phy device connected over RMII seems to work correctly without touching this bit. Add support of RMII, if CONFIG_RMII is defined, this option is aligned with a number of boards, which already define the same config value. Signed-off-by: Vladimir Zapolskiy v...@mleia.com --- arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 7 ++- drivers/net/lpc32xx_eth.c| 20 +--- 2 files changed, 23 insertions(+), 4 deletions(-) Resent as the original tested by e-mail did not record on patchwork; I tested this patch and the 3 patches listed below using a Micrel KSZ8031RNL phy connected over RMII. Everything is working properly. - http://patchwork.ozlabs.org/patch/489100/ - http://patchwork.ozlabs.org/patch/489190/ - http://patchwork.ozlabs.org/patch/491419/ Tested-by: Sylvain Lemieux slemi...@tycoint.com This e-mail contains privileged and confidential information intended for the use of the addressees named above. If you are not the intended recipient of this e-mail, you are hereby notified that you must not disseminate, copy or take any action in respect of any information contained in it. If you have received this e-mail in error, please notify the sender immediately by e-mail and immediately destroy this e-mail and its attachments. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] ARM: tegra: Add p2371-0000 board
Stephen,
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Wednesday, July 29, 2015 12:49 PM
To: u-boot@lists.denx.de; Simon Glass; Tom Warren; Stephen Warren
Cc: Thierry Reding
Subject: [PATCH 2/2] ARM: tegra: Add p2371- board
From: Stephen Warren swar...@nvidia.com
Signed-off-by: Stephen Warren swar...@nvidia.com
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/tegra210-p2371-.dts | 59 +
arch/arm/mach-tegra/tegra210/Kconfig | 6 +
board/nvidia/p2371-/Kconfig| 12 +
board/nvidia/p2371-/MAINTAINERS| 6 +
board/nvidia/p2371-/Makefile | 8 +
board/nvidia/p2371-/p2371-.c | 48
board/nvidia/p2371-/pinmux-config-p2371-.h | 260
+
configs/p2371-_defconfig | 16 ++
include/configs/p2371-.h | 72 ++
10 files changed, 488 insertions(+)
create mode 100644 arch/arm/dts/tegra210-p2371-.dts
create mode 100644 board/nvidia/p2371-/Kconfig create mode 100644
board/nvidia/p2371-/MAINTAINERS
create mode 100644 board/nvidia/p2371-/Makefile create mode 100644
board/nvidia/p2371-/p2371-.c
create mode 100644 board/nvidia/p2371-/pinmux-config-p2371-.h
create mode 100644 configs/p2371-_defconfig create mode 100644
include/configs/p2371-.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index
d8e1841eb4d8..f61060fc92e5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -34,6 +34,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra124-nyan-big.dtb \
tegra124-venice2.dtb \
tegra210-e2220-1170.dtb \
+ tegra210-p2371-.dtb \
tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-sld3-ref.dtb \
diff --git a/arch/arm/dts/tegra210-p2371-.dts b/arch/arm/dts/tegra210-
p2371-.dts
new file mode 100644
index ..10172a23ad70
--- /dev/null
+++ b/arch/arm/dts/tegra210-p2371-.dts
@@ -0,0 +1,59 @@
+/dts-v1/;
+
+#include tegra210.dtsi
+
+/ {
+ model = NVIDIA P2371-;
+ compatible = nvidia,p2371-, nvidia,tegra210;
+
+ chosen {
+ stdout-path = uarta;
+ };
+
+ aliases {
+ i2c0 = /i2c@0,7000d000;
+ sdhci0 = /sdhci@0,700b0600;
+ sdhci1 = /sdhci@0,700b;
+ usb0 = /usb@0,7d00;
+ };
+
+ memory {
+ reg = 0x0 0x8000 0x0 0xc000;
+ };
+
+ sdhci@0,700b {
+ status = okay;
+ cd-gpios = gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW;
+ power-gpios = gpio TEGRA_GPIO(Z, 4)
GPIO_ACTIVE_HIGH;
+ bus-width = 4;
+ };
+
+ sdhci@0,700b0600 {
+ status = okay;
+ bus-width = 8;
+ };
+
+ i2c@0,7000d000 {
+ status = okay;
+ clock-frequency = 40;
+ };
+
+ usb@0,7d00 {
+ status = okay;
+ dr_mode = otg;
+ nvidia,vbus-gpio = gpio TEGRA_GPIO(CC, 4)
GPIO_ACTIVE_HIGH;
+ };
+
+ clocks {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ clk32k_in: clock@0 {
+ compatible = fixed-clock;
+ reg = 0;
+ #clock-cells = 0;
+ clock-frequency = 32768;
+ };
+ };
+};
diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-
tegra/tegra210/Kconfig
index 9633ba8c629e..895002c5942b 100644
--- a/arch/arm/mach-tegra/tegra210/Kconfig
+++ b/arch/arm/mach-tegra/tegra210/Kconfig
@@ -8,6 +8,11 @@ config TARGET_E2220_1170
help
E2220-1170 ERS
+config TARGET_P2371_
+ bool NVIDIA Tegra210 P2371- base board
+ help
+ P2371-
+
config TARGET_P2571
bool NVIDIA Tegra210 P2571 base board
help
@@ -19,6 +24,7 @@ config SYS_SOC
default tegra210
source board/nvidia/e2220-1170/Kconfig
+source board/nvidia/p2371-/Kconfig
source board/nvidia/p2571/Kconfig
endif
diff --git a/board/nvidia/p2371-/Kconfig b/board/nvidia/p2371-
/Kconfig new file mode 100644 index ..f94be12be1a0
--- /dev/null
+++ b/board/nvidia/p2371-/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_P2371_
+
+config SYS_BOARD
+ default p2371-
+
+config SYS_VENDOR
+ default nvidia
+
+config SYS_CONFIG_NAME
+ default p2371-
+
+endif
diff --git a/board/nvidia/p2371-/MAINTAINERS b/board/nvidia/p2371-
/MAINTAINERS
new file mode 100644
index ..e6d04bf7c5e1
--- /dev/null
+++ b/board/nvidia/p2371-/MAINTAINERS
@@ -0,0 +1,6 @@
+P2371- BOARD
+M: Tom Warren twar...@nvidia.com
Shouldn't
Re: [U-Boot] [PATCH v2 3/6] hi6553: Add register definition and bitfield header for 6553 pmic
Hi Simon, On 18 July 2015 at 15:37, Simon Glass s...@chromium.org wrote: Hi Peter, On 8 July 2015 at 09:57, Peter Griffin peter.grif...@linaro.org wrote: This pmic is used on the 96boards consumer edition HiKey board. Signed-off-by: Peter Griffin peter.grif...@linaro.org --- arch/arm/include/asm/arch-hi6220/hi6553.h | 75 +++ 1 file changed, 75 insertions(+) create mode 100644 arch/arm/include/asm/arch-hi6220/hi6553.h Should be in drivers/power/pmic I think. Also use struct for reg access. Should probably use the new PMIC uclass (we can convert it later if you don't have a device tree yet). OK I've converted it to a simple pmic driver in v3 patches. snip regards, Peter ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 2/8] dm: gpio: hi6220: Add a hi6220 GPIO driver model driver.
This patch adds support for the GPIO perif found on hi6220
SoC.
Signed-off-by: Peter Griffin peter.grif...@linaro.org
---
arch/arm/include/asm/arch-hi6220/gpio.h | 29 ++
drivers/gpio/Makefile | 2 +
drivers/gpio/hi6220_gpio.c | 95 +
3 files changed, 126 insertions(+)
create mode 100644 arch/arm/include/asm/arch-hi6220/gpio.h
create mode 100644 drivers/gpio/hi6220_gpio.c
diff --git a/arch/arm/include/asm/arch-hi6220/gpio.h
b/arch/arm/include/asm/arch-hi6220/gpio.h
new file mode 100644
index 000..98122a2
--- /dev/null
+++ b/arch/arm/include/asm/arch-hi6220/gpio.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2015 Linaro
+ * Peter Griffin peter.grif...@linaro.org
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _HI6220_GPIO_H_
+#define _HI6220_GPIO_H_
+
+#define HI6220_GPIO_BASE(bank) (((bank 4) ? 0xf8011000 : \
+ 0xf702 - 0x4000) + (0x1000 * bank))
+
+#define BIT(x) (1 (x))
+
+#define HI6220_GPIO_PER_BANK 8
+#define HI6220_GPIO_DIR0x400
+
+struct gpio_bank {
+ u8 *base; /* address of registers in physical memory */
+};
+
+/* Information about a GPIO bank */
+struct hikey_gpio_platdata {
+ int bank_index;
+ unsigned int base; /* address of registers in physical memory */
+};
+
+#endif /* _HI6220_GPIO_H_ */
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 5864850..b470bab 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -46,3 +46,5 @@ obj-$(CONFIG_LPC32XX_GPIO)+= lpc32xx_gpio.o
obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o
obj-$(CONFIG_ZYNQ_GPIO)+= zynq_gpio.o
obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o
+obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o
+
diff --git a/drivers/gpio/hi6220_gpio.c b/drivers/gpio/hi6220_gpio.c
new file mode 100644
index 000..3f41bff
--- /dev/null
+++ b/drivers/gpio/hi6220_gpio.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2015 Linaro
+ * Peter Griffin peter.grif...@linaro.org
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include dm.h
+#include asm/gpio.h
+#include asm/io.h
+#include errno.h
+
+static int hi6220_gpio_direction_input(struct udevice *dev, unsigned int gpio)
+{
+ struct gpio_bank *bank = dev_get_priv(dev);
+ u8 data;
+
+ data = readb(bank-base + HI6220_GPIO_DIR);
+ data = ~(1 gpio);
+ writeb(data, bank-base + HI6220_GPIO_DIR);
+
+ return 0;
+}
+
+static int hi6220_gpio_set_value(struct udevice *dev, unsigned gpio,
+ int value)
+{
+ struct gpio_bank *bank = dev_get_priv(dev);
+
+ writeb(!!value gpio, bank-base + (BIT(gpio + 2)));
+ return 0;
+}
+
+static int hi6220_gpio_direction_output(struct udevice *dev, unsigned gpio,
+ int value)
+{
+ struct gpio_bank *bank = dev_get_priv(dev);
+ u8 data;
+
+ data = readb(bank-base + HI6220_GPIO_DIR);
+ data |= 1 gpio;
+ writeb(data, bank-base + HI6220_GPIO_DIR);
+
+ hi6220_gpio_set_value(dev, gpio, value);
+
+ return 0;
+}
+
+static int hi6220_gpio_get_value(struct udevice *dev, unsigned gpio)
+{
+ struct gpio_bank *bank = dev_get_priv(dev);
+
+ return !!readb(bank-base + (BIT(gpio + 2)));
+}
+
+
+
+static const struct dm_gpio_ops gpio_hi6220_ops = {
+ .direction_input= hi6220_gpio_direction_input,
+ .direction_output = hi6220_gpio_direction_output,
+ .get_value = hi6220_gpio_get_value,
+ .set_value = hi6220_gpio_set_value,
+};
+
+static int hi6220_gpio_probe(struct udevice *dev)
+{
+ struct gpio_bank *bank = dev_get_priv(dev);
+ struct hikey_gpio_platdata *plat = dev_get_platdata(dev);
+ struct gpio_dev_priv *uc_priv = dev-uclass_priv;
+ char name[18], *str;
+
+ sprintf(name, GPIO%d_, plat-bank_index);
+
+ str = strdup(name);
+ if (!str)
+ return -ENOMEM;
+
+ uc_priv-bank_name = str;
+ uc_priv-gpio_count = HI6220_GPIO_PER_BANK;
+
+ bank-base = (u8 *)plat-base;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(gpio_hi6220) = {
+ .name = gpio_hi6220,
+ .id = UCLASS_GPIO,
+ .ops= gpio_hi6220_ops,
+ .probe = hi6220_gpio_probe,
+ .priv_auto_alloc_size = sizeof(struct gpio_bank),
+};
+
+
--
1.9.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 1/8] usb: dwc2: Call board_usb_init() from usb_lowlevel_init()
This patch makes the dwc2 controller like ehci / ohci / xhci controllers by calling the board_usb_init() function from usb_lowlevel_init. This can then be implemented by specific platforms to initialise their USB hardware (phys / clocks etc). Signed-off-by: Peter Griffin peter.grif...@linaro.org --- drivers/usb/host/dwc2.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c index eee60a2..ad35841 100644 --- a/drivers/usb/host/dwc2.c +++ b/drivers/usb/host/dwc2.c @@ -929,6 +929,10 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) root_hub_devnum = 0; + /* board dependant init */ + if (board_usb_init(index, USB_INIT_HOST)) + return -1; + snpsid = readl(regs-gsnpsid); printf(Core Release: %x.%03x\n, snpsid 12 0xf, snpsid 0xfff); -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 3/8] ARM: hi6220: Add register and bitfield definition header files.
This patch adds the header files which will be used in the subsquent
board / drivers to enable support for hi6220 hikey board.
Signed-off-by: Peter Griffin peter.grif...@linaro.org
---
arch/arm/include/asm/arch-hi6220/hi6220.h | 387 +++
.../include/asm/arch-hi6220/hi6220_regs_alwayson.h | 420 +
2 files changed, 807 insertions(+)
create mode 100644 arch/arm/include/asm/arch-hi6220/hi6220.h
create mode 100644 arch/arm/include/asm/arch-hi6220/hi6220_regs_alwayson.h
diff --git a/arch/arm/include/asm/arch-hi6220/hi6220.h
b/arch/arm/include/asm/arch-hi6220/hi6220.h
new file mode 100644
index 000..4b987c2
--- /dev/null
+++ b/arch/arm/include/asm/arch-hi6220/hi6220.h
@@ -0,0 +1,387 @@
+/*
+ * (C) Copyright 2015 Linaro
+ * Peter Griffin peter.grif...@linaro.org
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __HI6220_H__
+#define __HI6220_H__
+
+#include hi6220_regs_alwayson.h
+
+#define HI6220_MMC0_BASE 0xF723D000
+#define HI6220_MMC1_BASE 0xF723E000
+
+#define HI6220_PMUSSI_BASE 0xF800
+
+#define HI6220_PERI_BASE 0xF703
+
+struct peri_sc_periph_regs {
+ u32 ctrl1; /*0x0*/
+ u32 ctrl2;
+ u32 ctrl3;
+ u32 ctrl4;
+ u32 ctrl5;
+ u32 ctrl6;
+ u32 ctrl8;
+ u32 ctrl9;
+ u32 ctrl10;
+ u32 ctrl12;
+ u32 ctrl13;
+ u32 ctrl14;
+
+ u32 unknown_1[8];
+
+ u32 ddr_ctrl0; /*0x50*/
+
+ u32 unknown_2[16];
+
+ u32 stat1; /*0x94*/
+
+ u32 unknown_3[90];
+
+ u32 clk0_en;/*0x200*/
+ u32 clk0_dis;
+ u32 clk0_stat;
+
+ u32 unknown_4;
+
+ u32 clk1_en;/*0x210*/
+ u32 clk1_dis;
+ u32 clk1_stat;
+
+ u32 unknown_5;
+
+ u32 clk2_en;/*0x220*/
+ u32 clk2_dis;
+ u32 clk2_stat;
+
+ u32 unknown_6;
+
+ u32 clk3_en;/*0x230*/
+ u32 clk3_dis;
+ u32 clk3_stat;
+
+ u32 unknown_7;
+
+ u32 clk8_en;/*0x240*/
+ u32 clk8_dis;
+ u32 clk8_stat;
+
+ u32 unknown_8;
+
+ u32 clk9_en;/*0x250*/
+ u32 clk9_dis;
+ u32 clk9_stat;
+
+ u32 unknown_9;
+
+ u32 clk10_en; /*0x260*/
+ u32 clk10_dis;
+ u32 clk10_stat;
+
+ u32 unknown_10;
+
+ u32 clk12_en; /*0x270*/
+ u32 clk12_dis;
+ u32 clk12_stat;
+
+ u32 unknown_11[33];
+
+ u32 rst0_en;/*0x300*/
+ u32 rst0_dis;
+ u32 rst0_stat;
+
+ u32 unknown_12;
+
+ u32 rst1_en;/*0x310*/
+ u32 rst1_dis;
+ u32 rst1_stat;
+
+ u32 unknown_13;
+
+ u32 rst2_en;/*0x320*/
+ u32 rst2_dis;
+ u32 rst2_stat;
+
+ u32 unknown_14;
+
+ u32 rst3_en;/*0x330*/
+ u32 rst3_dis;
+ u32 rst3_stat;
+
+ u32 unknown_15;
+
+ u32 rst8_en;/*0x340*/
+ u32 rst8_dis;
+ u32 rst8_stat;
+
+ u32 unknown_16[45];
+
+ u32 clk0_sel; /*0x400*/
+
+ u32 unknown_17[36];
+
+ u32 clkcfg8bit1;/*0x494*/
+ u32 clkcfg8bit2;
+
+ u32 unknown_18[538];
+
+ u32 reserved8_addr; /*0xd04*/
+};
+
+
+/* CTRL1 bit definitions */
+
+#define PERI_CTRL1_ETR_AXI_CSYSREQ_N (1 0)
+#define PERI_CTRL1_HIFI_INT_MASK (1 1)
+#define PERI_CTRL1_HIFI_ALL_INT_MASK (1 2)
+#define PERI_CTRL1_ETR_AXI_CSYSREQ_N_MSK (1 16)
+#define PERI_CTRL1_HIFI_INT_MASK_MSK (1 17)
+#define PERI_CTRL1_HIFI_ALL_INT_MASK_MSK (1 18)
+
+
+/* CTRL2 bit definitions */
+
+#define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC0(1 0)
+#define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC1(1 2)
+#define PERI_CTRL2_NAND_SYS_MEM_SEL(1 6)
+#define PERI_CTRL2_G3D_DDRT_AXI_SEL(1 7)
+#define PERI_CTRL2_GU_MDM_BBP_TESTPIN_SEL (1 8)
+#define PERI_CTRL2_CODEC_SSI_MASTER_CHECK (1 9)
+#define PERI_CTRL2_FUNC_TEST_SOFT (1 12)
+#define PERI_CTRL2_CSSYS_TS_ENABLE (1 15)
+#define PERI_CTRL2_HIFI_RAMCTRL_S_EMA (1 16)
+#define PERI_CTRL2_HIFI_RAMCTRL_S_EMAW (1 20)
+#define PERI_CTRL2_HIFI_RAMCTRL_S_EMAS (1 22)
+#define PERI_CTRL2_HIFI_RAMCTRL_S_RET1N(1 26)
+#define PERI_CTRL2_HIFI_RAMCTRL_S_RET2N(1 27)
+#define PERI_CTRL2_HIFI_RAMCTRL_S_PGEN (1 28)
+
+/* CTRL3 bit definitions */
+
+#define PERI_CTRL3_HIFI_DDR_HARQMEM_ADDR (1 0)
+#define PERI_CTRL3_HIFI_HARQMEMRMP_EN (1 12)
+#define PERI_CTRL3_HARQMEM_SYS_MED_SEL (1 13)
+#define
[U-Boot] [PATCH v3 4/8] hisilicon: hi6220: Add a hi6220 pinmux driver.
This patch adds basic pinmux support for the hi6220 SoC,
which is found on the hikey board.
Signed-off-by: Peter Griffin peter.grif...@linaro.org
---
arch/arm/cpu/armv8/Makefile | 1 +
arch/arm/cpu/armv8/hisilicon/Makefile | 9 ++
arch/arm/cpu/armv8/hisilicon/pinmux.c | 184 ++
arch/arm/include/asm/arch-hi6220/periph.h | 30 +
arch/arm/include/asm/arch-hi6220/pinmux.h | 83 ++
5 files changed, 307 insertions(+)
create mode 100644 arch/arm/cpu/armv8/hisilicon/Makefile
create mode 100644 arch/arm/cpu/armv8/hisilicon/pinmux.c
create mode 100644 arch/arm/include/asm/arch-hi6220/periph.h
create mode 100644 arch/arm/include/asm/arch-hi6220/pinmux.h
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index dee5e25..c90e018 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -17,3 +17,4 @@ obj-y += transition.o
obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/
obj-$(CONFIG_TARGET_XILINX_ZYNQMP) += zynqmp/
+obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
diff --git a/arch/arm/cpu/armv8/hisilicon/Makefile
b/arch/arm/cpu/armv8/hisilicon/Makefile
new file mode 100644
index 000..552dbcf
--- /dev/null
+++ b/arch/arm/cpu/armv8/hisilicon/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2015 Linaro
+# Peter Griffin peter.grif...@linaro.org
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += pinmux.o
+
diff --git a/arch/arm/cpu/armv8/hisilicon/pinmux.c
b/arch/arm/cpu/armv8/hisilicon/pinmux.c
new file mode 100644
index 000..48e52ca
--- /dev/null
+++ b/arch/arm/cpu/armv8/hisilicon/pinmux.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2015 Linaro.
+ * Peter Griffin peter.grif...@linaro.org
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include fdtdec.h
+#include asm/gpio.h
+#include asm/io.h
+#include asm/arch/pinmux.h
+
+struct hi6220_pinmux0_regs *pmx0 =
+ (struct hi6220_pinmux0_regs *)HI6220_PINMUX0_BASE;
+
+struct hi6220_pinmux1_regs *pmx1 =
+ (struct hi6220_pinmux1_regs *)HI6220_PINMUX1_BASE;
+
+static void hi6220_uart_config(int peripheral)
+{
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ writel(MUX_M0, pmx0-iomg[48]); /* UART0_RXD */
+ writel(MUX_M0, pmx0-iomg[49]); /* UART0_TXD */
+
+ writel(DRIVE1_02MA | PULL_UP, pmx1-iocfg[49]); /* UART0_RXD */
+ writel(DRIVE1_02MA | PULL_UP, pmx1-iocfg[50]); /* UART0_TXD */
+ break;
+
+ case PERIPH_ID_UART1:
+ writel(MUX_M0, pmx0-iomg[50]); /* UART1_CTS_N */
+ writel(MUX_M0, pmx0-iomg[51]); /* UART1_RTS_N */
+ writel(MUX_M0, pmx0-iomg[52]); /* UART1_RXD */
+ writel(MUX_M0, pmx0-iomg[53]); /* UART1_TXD */
+
+ writel(DRIVE1_02MA | PULL_UP, pmx1-iocfg[51]); /*UART1_CTS_N*/
+ writel(DRIVE1_02MA | PULL_UP, pmx1-iocfg[53]); /* UART1_RXD */
+ writel(DRIVE1_02MA, pmx1-iocfg[52]); /* UART1_RTS_N */
+ writel(DRIVE1_02MA, pmx1-iocfg[54]); /* UART1_TXD */
+ break;
+
+ case PERIPH_ID_UART2:
+ writel(MUX_M0, pmx0-iomg[54]); /* UART2_CTS_N */
+ writel(MUX_M0, pmx0-iomg[55]); /* UART2_RTS_N */
+ writel(MUX_M0, pmx0-iomg[56]); /* UART2_RXD */
+ writel(MUX_M0, pmx0-iomg[57]); /* UART2_TXD */
+
+ writel(DRIVE1_02MA, pmx1-iocfg[55]); /* UART2_CTS_N */
+ writel(DRIVE1_02MA, pmx1-iocfg[56]); /* UART2_RTS_N */
+ writel(DRIVE1_02MA, pmx1-iocfg[57]); /* UART2_RXD */
+ writel(DRIVE1_02MA, pmx1-iocfg[58]); /* UART2_TXD */
+ break;
+
+ case PERIPH_ID_UART3:
+ writel(MUX_M1, pmx0-iomg[96]); /* UART3_CTS_N */
+ writel(MUX_M1, pmx0-iomg[97]); /* UART3_RTS_N */
+ writel(MUX_M1, pmx0-iomg[98]); /* UART3_RXD */
+ writel(MUX_M1, pmx0-iomg[99]); /* UART3_TXD */
+
+ /* UART3_TXD */
+ writel(DRIVE1_02MA | PULL_DOWN, pmx1-iocfg[100]);
+ /* UART3_RTS_N */
+ writel(DRIVE1_02MA | PULL_DOWN, pmx1-iocfg[101]);
+ /* UART3_RXD */
+ writel(DRIVE1_02MA | PULL_DOWN, pmx1-iocfg[102]);
+ /* UART3_TXD */
+ writel(DRIVE1_02MA | PULL_DOWN, pmx1-iocfg[103]);
+ break;
+
+ case PERIPH_ID_UART4:
+ writel(MUX_M1, pmx0-iomg[116]); /* UART4_CTS_N */
+ writel(MUX_M1, pmx0-iomg[117]); /* UART4_RTS_N */
+ writel(MUX_M1, pmx0-iomg[118]); /* UART4_RXD */
+ writel(MUX_M1, pmx0-iomg[119]); /* UART4_TXD */
+
+ /* UART4_CTS_N */
+ writel(DRIVE1_02MA | PULL_DOWN, pmx1-iocfg[120]);
+ /* UART4_RTS_N */
+ writel(DRIVE1_02MA | PULL_DOWN, pmx1-iocfg[121]);
+ /* UART4_RXD */
+ writel(DRIVE1_02MA | PULL_DOWN, pmx1-iocfg[122]);
+
[U-Boot] [PATCH v3 5/8] pmic: pmic_hi6553: Add a driver for the hi6553 pmic found on hikey board.
This adds a simple pmic driver for the hi6553 pmic which is used in
conjunction with the hi6220 SoC on the hikey board. Eventually this
driver will be updated to be a proper UCLASS PMIC driver which
can parse the voltages direct from device tree.
Signed-off-by: Peter Griffin peter.grif...@linaro.org
---
drivers/power/pmic/Makefile | 1 +
drivers/power/pmic/pmic_hi6553.c | 133 +++
include/power/hi6553_pmic.h | 79 +++
3 files changed, 213 insertions(+)
create mode 100644 drivers/power/pmic/pmic_hi6553.c
create mode 100644 include/power/hi6553_pmic.h
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index ae86f04..21e9535 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -20,3 +20,4 @@ obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
obj-$(CONFIG_POWER_TPS65218) += pmic_tps62362.o
obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
+obj-$(CONFIG_POWER_HI6553) += pmic_hi6553.o
diff --git a/drivers/power/pmic/pmic_hi6553.c b/drivers/power/pmic/pmic_hi6553.c
new file mode 100644
index 000..0af7987
--- /dev/null
+++ b/drivers/power/pmic/pmic_hi6553.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (C) 2015 Linaro
+ * Peter Griffin peter.grif...@linaro.org
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include asm/io.h
+#include common.h
+#include power/pmic.h
+#include power/max8997_muic.h
+#include power/hi6553_pmic.h
+#include errno.h
+
+u8 *pmussi_base;
+
+uint8_t hi6553_readb(u32 offset)
+{
+ return readb(pmussi_base + (offset 2));
+}
+
+void hi6553_writeb(u32 offset, uint8_t value)
+{
+ writeb(value, pmussi_base + (offset 2));
+}
+
+int pmic_reg_write(struct pmic *p, u32 reg, u32 val)
+{
+ if (check_reg(p, reg))
+ return -1;
+
+ hi6553_writeb(reg, (uint8_t)val);
+
+ return 0;
+}
+
+int pmic_reg_read(struct pmic *p, u32 reg, u32 *val)
+{
+ if (check_reg(p, reg))
+ return -1;
+
+ *val = (u32)hi6553_readb(reg);
+
+ return 0;
+}
+
+static void hi6553_init(void)
+{
+ int data;
+
+ hi6553_writeb(HI6553_PERI_EN_MARK, 0x1e);
+ hi6553_writeb(HI6553_NP_REG_ADJ1, 0);
+ data = HI6553_DISABLE6_XO_CLK_CONN | HI6553_DISABLE6_XO_CLK_NFC |
+ HI6553_DISABLE6_XO_CLK_RF1 | HI6553_DISABLE6_XO_CLK_RF2;
+ hi6553_writeb(HI6553_DISABLE6_XO_CLK, data);
+
+ /* configure BUCK0 BUCK1 */
+ hi6553_writeb(HI6553_BUCK01_CTRL2, 0x5e);
+ hi6553_writeb(HI6553_BUCK0_CTRL7, 0x10);
+ hi6553_writeb(HI6553_BUCK1_CTRL7, 0x10);
+ hi6553_writeb(HI6553_BUCK0_CTRL5, 0x1e);
+ hi6553_writeb(HI6553_BUCK1_CTRL5, 0x1e);
+ hi6553_writeb(HI6553_BUCK0_CTRL1, 0xfc);
+ hi6553_writeb(HI6553_BUCK1_CTRL1, 0xfc);
+
+ /* configure BUCK2 */
+ hi6553_writeb(HI6553_BUCK2_REG1, 0x4f);
+ hi6553_writeb(HI6553_BUCK2_REG5, 0x99);
+ hi6553_writeb(HI6553_BUCK2_REG6, 0x45);
+ mdelay(1);
+ hi6553_writeb(HI6553_VSET_BUCK2_ADJ, 0x22);
+ mdelay(1);
+
+ /* configure BUCK3 */
+ hi6553_writeb(HI6553_BUCK3_REG3, 0x02);
+ hi6553_writeb(HI6553_BUCK3_REG5, 0x99);
+ hi6553_writeb(HI6553_BUCK3_REG6, 0x41);
+ hi6553_writeb(HI6553_VSET_BUCK3_ADJ, 0x02);
+ mdelay(1);
+
+ /* configure BUCK4 */
+ hi6553_writeb(HI6553_BUCK4_REG2, 0x9a);
+ hi6553_writeb(HI6553_BUCK4_REG5, 0x99);
+ hi6553_writeb(HI6553_BUCK4_REG6, 0x45);
+
+ /* configure LDO20 */
+ hi6553_writeb(HI6553_LDO20_REG_ADJ, 0x50);
+
+ hi6553_writeb(HI6553_NP_REG_CHG, 0x0f);
+ hi6553_writeb(HI6553_CLK_TOP0, 0x06);
+ hi6553_writeb(HI6553_CLK_TOP3, 0xc0);
+ hi6553_writeb(HI6553_CLK_TOP4, 0x00);
+
+ /* configure LDO7 LDO10 for SD slot */
+ data = hi6553_readb(HI6553_LDO7_REG_ADJ);
+ data = (data 0xf8) | 0x2;
+ hi6553_writeb(HI6553_LDO7_REG_ADJ, data);
+ mdelay(5);
+ /* enable LDO7 */
+ hi6553_writeb(HI6553_ENABLE2_LDO1_8, 1 6);
+ mdelay(5);
+ data = hi6553_readb(HI6553_LDO10_REG_ADJ);
+ data = (data 0xf8) | 0x5;
+ hi6553_writeb(HI6553_LDO10_REG_ADJ, data);
+ mdelay(5);
+ /* enable LDO10 */
+ hi6553_writeb(HI6553_ENABLE3_LDO9_16, 1 1);
+ mdelay(5);
+
+ /* select 32.764KHz */
+ hi6553_writeb(HI6553_CLK19M2_600_586_EN, 0x01);
+}
+
+int power_hi6553_init(u8 *base)
+{
+ static const char name[] = HI6553 PMIC;
+ struct pmic *p = pmic_alloc();
+
+ if (!p) {
+ printf(%s: POWER allocation error!\n, __func__);
+ return -ENOMEM;
+ }
+
+ p-name = name;
+ p-interface = PMIC_NONE;
+ p-number_of_regs = 44;
+ pmussi_base = base;
+
+ hi6553_init();
+
+ puts(HI6553 PMIC init\n);
+
+ return 0;
+}
diff --git a/include/power/hi6553_pmic.h b/include/power/hi6553_pmic.h
new file mode 100644
index
[U-Boot] [PATCH v3 0/8] Add support for hi6220 SoC and HiKey 96boards CE board.
Hi Albert, This series adds support for the first 96boards consumer edition HiKey board. More information can be found about this board at the following link https://www.96boards.org/products/hikey/. This initial port adds support for: - 1) Serial 2) eMMC and sd card 3) USB 4) GPIO It has been tested with Arm Trusted Firmware running u-boot as the BL33 executable. Some instructions on exactly how to compile everything (l-loader, with Arm Trusted Firmware, which then loads u-boot) is documented in the README found in the board/hisilicon/hikey directory. A basic SoC datasheet can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf Board schematic can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ 96Boards-Hikey-Rev-A1.pdf A rather pleasant side effect of rebasing to v2015.07-rc2 is that the two main bugs with the v1 series (that I new about at least) are resolved. DHCP now works correctly, and USB mass storage devices are also enumerated). The plan is once basic support is merged to u-boot, and upstream Linux kernel has DT which supports GPIO, UART and MMC, we can migrate this u-boot port over to using DT for configuration. Changes since v2: - errno.h should go above malloc.h (Simon) - drop #ifdef CONFIG_DM_GPIO and add TODO (Simon) - remove gd-flags = 0; (Simon) - Remove icache_enable() (Simon / Rob) - Added a pinmux driver for hi6220 (Simon) - Added a pmic driver for hi6553 (Simon) - Convert to structs for register I/O (Simon) - Remove () around simple constants (Simon) - Update default bootcmd (Rob) - user kernel_addr_r etc in default env (Rob) - Various typo's (Rob) - use board_usb_init() to configure phy/clocks (Rob) - Remove some more unnecessary CONFIG_FS* options (Rob) - Update default kernel load address (Rob) - Update default kernel cmdline (Rob) Changes since v1: - Rename vendor to hisilicon not 96boards (Rob) - Get rid of aemv8a vexpress leftover (Rob) - Remove __weak on misc_init_r (Rob) - Remove unnecessary LINUX_BOOT_PARAM_ADDR (Rob) - COUNTER_FREQUENCY in decimal to avoid comment (Rob) - Remove leftover V2M* from vexpress (Rob) - Migrate configs/hikey.h over to use config_distro_defaults.h (Rob) - Remove custom u-boot prompt (Rob) - Enable icache - Remove custom delay function, as mdelay/udelay work fine (Rob) - Update CONFIG_SYS_LOAD_ADDR to 0x8 (Rob) - Use suggested macro for declaring gpio addresses (Marek) - Zap dead Macros (Marek) - Use calloc instead of malloc (Marek) - Reduce PHYS_RAM by 16Mb to accomodate OPTEE in latest ATF code (Peter) - Rebase on v2015.07-rc2 (Peter) - Add CONFIG_NET=y so that env callbacks work (Peter) - Add a README on how to build / flash u-boot (Simon) kind regards, Peter. Peter Griffin (8): usb: dwc2: Call board_usb_init() from usb_lowlevel_init() dm: gpio: hi6220: Add a hi6220 GPIO driver model driver. ARM: hi6220: Add register and bitfield definition header files. hisilicon: hi6220: Add a hi6220 pinmux driver. pmic: pmic_hi6553: Add a driver for the hi6553 pmic found on hikey board. mmc: hi6220_dw_mmc: Add hi6220 glue code for dw_mmc controller. ARM64: hikey: hi6220: Add u-boot support for the 96boards CE HiKey board. ARM64: hikey: Add a README for this board. arch/arm/Kconfig | 8 + arch/arm/cpu/armv8/Makefile| 1 + arch/arm/cpu/armv8/hisilicon/Makefile | 9 + arch/arm/cpu/armv8/hisilicon/pinmux.c | 184 + arch/arm/include/asm/arch-hi6220/dwmmc.h | 8 + arch/arm/include/asm/arch-hi6220/gpio.h| 29 ++ arch/arm/include/asm/arch-hi6220/hi6220.h | 387 +++ .../include/asm/arch-hi6220/hi6220_regs_alwayson.h | 420 + arch/arm/include/asm/arch-hi6220/periph.h | 30 ++ arch/arm/include/asm/arch-hi6220/pinmux.h | 83 board/hisilicon/hikey/Kconfig | 15 + board/hisilicon/hikey/Makefile | 8 + board/hisilicon/hikey/README | 160 board/hisilicon/hikey/hikey.c | 356 + configs/hikey_defconfig| 5 + drivers/gpio/Makefile | 2 + drivers/gpio/hi6220_gpio.c | 95 + drivers/mmc/Makefile | 1 + drivers/mmc/hi6220_dw_mmc.c| 56 +++ drivers/power/pmic/Makefile| 1 + drivers/power/pmic/pmic_hi6553.c | 133 +++ drivers/usb/host/dwc2.c| 4 + include/configs/hikey.h| 159 include/power/hi6553_pmic.h| 79 24 files changed, 2233 insertions(+) create mode 100644 arch/arm/cpu/armv8/hisilicon/Makefile create mode
Re: [U-Boot] [PATCH v2 2/6] ARM: hi6220: Add register and bitfield definition header files.
Hi Simon,
On 18 July 2015 at 15:37, Simon Glass s...@chromium.org wrote:
Hi Peter,
On 8 July 2015 at 09:57, Peter Griffin peter.grif...@linaro.org wrote:
This patch adds the header files which will be used in the subsquent
board / drivers to enable support for hi6220 hikey board.
Signed-off-by: Peter Griffin peter.grif...@linaro.org
---
arch/arm/include/asm/arch-hi6220/hi6220.h | 324
+++
.../include/asm/arch-hi6220/hi6220_regs_alwayson.h | 349
+
2 files changed, 673 insertions(+)
create mode 100644 arch/arm/include/asm/arch-hi6220/hi6220.h
create mode 100644
arch/arm/include/asm/arch-hi6220/hi6220_regs_alwayson.h
diff --git a/arch/arm/include/asm/arch-hi6220/hi6220.h
b/arch/arm/include/asm/arch-hi6220/hi6220.h
new file mode 100644
index 000..3ddec91
--- /dev/null
+++ b/arch/arm/include/asm/arch-hi6220/hi6220.h
@@ -0,0 +1,324 @@
+/*
+ * (C) Copyright 2015 Linaro
+ * Peter Griffin peter.grif...@linaro.org
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __HI6220_H__
+#define __HI6220_H__
+
+#include hi6220_regs_alwayson.h
+
+#define HI6220_MMC0_BASE 0xF723D000
+#define HI6220_MMC1_BASE 0xF723E000
+
+#define HI6220_PMUSSI_BASE 0xF800
+
+#define HI6220_PERI_BASE 0xF703
+
+#define PERI_SC_PERIPH_CTRL1 (HI6220_PERI_BASE +
0x000)
+
I think you should have:
struct peri_sc_regs {
u32 ctrl1;
u32 ctrl2;
...
};
U-Boot uses structs for I/O access.
Phew...I've converted it over to structs for register access.
It actually took quite a long time to do, but it all works again now :)
So it will be using structs for I/O access in V3.
regards,
Peter.
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[U-Boot] [PATCH v3 6/8] mmc: hi6220_dw_mmc: Add hi6220 glue code for dw_mmc controller.
This patch adds the glue code for hi6220 SoC which has 2x synopsis
dw_mmc controllers. This will be used by the hikey board support
in subsequent patches.
Signed-off-by: Peter Griffin peter.grif...@linaro.org
Reviewed-by: Simon Glass s...@chromium.org
---
arch/arm/include/asm/arch-hi6220/dwmmc.h | 8 +
drivers/mmc/Makefile | 1 +
drivers/mmc/hi6220_dw_mmc.c | 56
3 files changed, 65 insertions(+)
create mode 100644 arch/arm/include/asm/arch-hi6220/dwmmc.h
create mode 100644 drivers/mmc/hi6220_dw_mmc.c
diff --git a/arch/arm/include/asm/arch-hi6220/dwmmc.h
b/arch/arm/include/asm/arch-hi6220/dwmmc.h
new file mode 100644
index 000..c747383
--- /dev/null
+++ b/arch/arm/include/asm/arch-hi6220/dwmmc.h
@@ -0,0 +1,8 @@
+/*
+ * (C) Copyright 2015 Linaro
+ * Peter Griffin peter.grif...@linaro.org
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width);
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index ed73687..81a1a8f 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_BFIN_SDH) += bfin_sdh.o
obj-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
obj-$(CONFIG_DWMMC) += dw_mmc.o
obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o
+obj-$(CONFIG_HIKEY_DWMMC) += hi6220_dw_mmc.o
obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o
obj-$(CONFIG_FTSDC021) += ftsdc021_sdhci.o
diff --git a/drivers/mmc/hi6220_dw_mmc.c b/drivers/mmc/hi6220_dw_mmc.c
new file mode 100644
index 000..731458c
--- /dev/null
+++ b/drivers/mmc/hi6220_dw_mmc.c
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2015 Linaro
+ * peter.griffin peter.grif...@linaro.org
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include dwmmc.h
+#include malloc.h
+#include asm-generic/errno.h
+
+#defineDWMMC_MAX_CH_NUM4
+
+#defineDWMMC_MAX_FREQ 5000
+#defineDWMMC_MIN_FREQ 40
+
+/* Source clock is configured to 100MHz by ATF bl1*/
+#define MMC0_DEFAULT_FREQ 1
+
+static int hi6220_dwmci_core_init(struct dwmci_host *host, int index)
+{
+ host-name = HiKey DWMMC;
+
+ host-dev_index = index;
+
+ /* Add the mmc channel to be registered with mmc core */
+ if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
+ printf(DWMMC%d registration failed\n, index);
+ return -1;
+ }
+ return 0;
+}
+
+/*
+ * This function adds the mmc channel to be registered with mmc core.
+ * index - mmc channel number.
+ * regbase - register base address of mmc channel specified in 'index'.
+ * bus_width - operating bus width of mmc channel specified in 'index'.
+ */
+int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width)
+{
+ struct dwmci_host *host = NULL;
+
+ host = calloc(1, sizeof(struct dwmci_host));
+ if (!host) {
+ error(dwmci_host calloc failed!\n);
+ return -ENOMEM;
+ }
+
+ host-ioaddr = (void *)regbase;
+ host-buswidth = bus_width;
+ host-bus_hz = MMC0_DEFAULT_FREQ;
+
+ return hi6220_dwmci_core_init(host, index);
+}
--
1.9.1
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[U-Boot] [PATCH v3 8/8] ARM64: hikey: Add a README for this board.
To help others with compiling and flashing ATF and u-boot add a README for this board. Signed-off-by: Peter Griffin peter.grif...@linaro.org --- board/hisilicon/hikey/README | 160 +++ 1 file changed, 160 insertions(+) create mode 100644 board/hisilicon/hikey/README diff --git a/board/hisilicon/hikey/README b/board/hisilicon/hikey/README new file mode 100644 index 000..25c8143 --- /dev/null +++ b/board/hisilicon/hikey/README @@ -0,0 +1,160 @@ +Introduction + + +HiKey is the first certified 96Boards Consumer Edition board. The board/SoC has: - +* HiSilicon Kirin 6220 eight-core ARM Cortex-A53 64-bit SoC running at 1.2GHz. +* ARM Mali 450-MP4 GPU +* 1GB 800MHz LPDDR3 DRAM +* 4GB eMMC Flash Storage +* microSD +* 802.11a/b/g/n WiFi, Bluetooth + +The HiKey schematic can be found here: - +https://github.com/96boards/documentation/blob/master/hikey/96Boards-Hikey-Rev-A1.pdf + +A SoC datasheet can be found here: - +https://github.com/96boards/documentation/blob/master/hikey/ +Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf + +Currently the u-boot port supports: - +* USB +* eMMC +* SD card +* GPIO + +Compile u-boot +== + +make CROSS_COMPILE=aarch64-linux-gnu- hikey_config +make CROSS_COMPILE=aarch64-linux-gnu- + +ARM Trusted Firmware (ATF) l-loader += + +This u-boot port has been tested with l-loader, booting ATF, which then boots +u-boot as the bl33.bin executable. + +1. Get ATF source code +git clone https://github.com/96boards/arm-trusted-firmware.git + +2. Compile ATF I use the makefile here +http://people.linaro.org/~peter.griffin/hikey/hikey-u-boot-release_r1/build-tf.mak + +3. Get l-loader +git clone https://github.com/96boards/l-loader.git + +4. Make sym links to ATF bip / fip binaries +ln -s /home/griffinp/aarch64/bl1-hikey.bin bl1.bin +ln -s /home/griffinp/aarch64/fip-hikey.bin fip.bin + +arm-linux-gnueabihf-gcc -c -o start.o start.S +arm-linux-gnueabihf-gcc -c -o debug.o debug.S +arm-linux-gnueabihf-ld -Bstatic -Tl-loader.lds -Ttext 0xf9800800 start.o debug.o -o loader +arm-linux-gnueabihf-objcopy -O binary loader temp + +python gen_loader.py -o l-loader.bin --img_loader=temp --img_bl1=bl1.bin +sudo bash -x generate_ptable.sh +python gen_loader.py -o ptable.img --img_prm_ptable=prm_ptable.img --img_sec_ptable=sec_ptable.img + +These instructions are adapted from +https://github.com/96boards/documentation/wiki/HiKeyUEFI + +FLASHING + + +1. Connect jumper J2 to go into recovery mode and flash l-loader.bin with + fastboot using the hisi-idt.py utility + + git clone https://github.com/96boards/burn-boot.git + sudo python /home/griffinp/Software/hikey/burn-boot/hisi-idt.py -d /dev/ttyUSB0 --img1=/tmp/l-loader.bin + +2. Once LED 0 comes on solid, it should be detected as a fastboot device + (on some boards I've found this to be unreliable) + +sudo fastboot devices + +3. Flash the images +wget https://builds.96boards.org/releases/hikey/nvme.img +sudo fastboot flash ptable ptable.img +sudo fastboot flash fastboot fip.bin +sudo fastboot flash nvme nvme.img + +4. Disconnect jumper J2, and reset the board and you will now (hopefully) + have ATF, booting u-boot from eMMC. On 'new' boards I've had to do the + flashing twice in the past to avoid an ATF error. + +See working boot trace below: - + +debug EMMC boot: print init OK +debug EMMC boot: send RST_N . +debug EMMC boot: start eMMC boot.. +load fastboot1! +Switch to aarch64 mode. CPU0 executes at 0xf9801000! +NOTICE: Booting Trusted Firmware +NOTICE: BL1: v1.1(release):a0c0399 +NOTICE: BL1: Built : 13:23:48, May 22 2015 +NOTICE: succeed to init lpddr3 rank0 dram phy +INFO:lpddr3_freq_init, set ddrc 533mhz +INFO:init ddr3 rank0 +INFO:ddr3 rank1 init pass +INFO:lpddr3_freq_init, set ddrc 800mhz +INFO:init ddr3 rank0 +INFO:ddr3 rank1 init pass +INFO:Elpida DDR +NOTICE: BL1: Booting BL2 +INFO:[BDID] [fff91c18] midr: 0x410fd033 +INFO:[BDID] [fff91c1c] board type: 0 +INFO:[BDID] [fff91c20] board id: 0x2b +INFO:init_acpu_dvfs: pmic version 17 +INFO:init_acpu_dvfs: ACPU_CHIP_MAX_FREQ=0x186a00. +INFO:acpu_dvfs_volt_init: success! +INFO:acpu_dvfs_set_freq: support freq num is 5 +INFO:acpu_dvfs_set_freq: start prof is 0x4 +INFO:acpu_dvfs_set_freq: magic is 0x5a5ac5c5 +INFO:acpu_dvfs_set_freq: voltage: +INFO: - 0: 0x3a +INFO: - 1: 0x3a +INFO: - 2: 0x4a +INFO: - 3: 0x5b +INFO: - 4: 0x6b +NOTICE: acpu_dvfs_set_freq: set acpu freq success!NOTICE: BL2: v1.1(debug):a0c0399 +NOTICE: BL2: Built : 10:19:28, May 27 2015 +INFO:BL2: Loading BL3-0 +INFO:Using FIP +WARNING: Failed to access image 'bl30.bin' (-1) +ERROR: Failed to load BL3-0 (-1) +ERROR: Please burn mcu image: +ERROR: sudo fastboot flash mcuimage mcuimage.bin +INFO:BL2: TrustZone: protecting 16777216 bytes of memory at 0x3f00 +INFO:BL2:
[U-Boot] [PATCH v3 7/8] ARM64: hikey: hi6220: Add u-boot support for the 96boards CE HiKey board.
HiKey is the first 96boards consumer edition compliant board. It features a
hi6220
SoC which has eight ARM A53 cpu's.
This initial port adds support for: -
1) Serial
2) eMMC / SD card
3) USB
4) GPIO
It has been tested with Arm Trusted Firmware running u-boot as the BL33
executable.
Notes:
eMMC has been tested with basic reading of eMMC partition into DDR. I have not
tested writing / erasing. Due to lack of clock control it won't be
running in the most performant high speed mode.
SD card slot has been tested for reading and booting kernels into DDR.
It is also currently configured to save the u-boot environment to the
SD card.
USB has been tested with ASIX networking adapter to tftpboot kernels
into DDR. On v2015.07-rc2 dhcp now works, and also USB mass storage
are correctly enumerated.
GPIO has been tested using gpio toggle GPIO4_1-3 to flash the LEDs.
Basic SoC datasheet can be found here: -
https://github.com/96boards/documentation/blob/master/hikey/
Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf
Board schematic can be found here: -
https://github.com/96boards/documentation/blob/master/hikey/
96Boards-Hikey-Rev-A1.pdf
Signed-off-by: Peter Griffin peter.grif...@linaro.org
---
arch/arm/Kconfig | 8 +
board/hisilicon/hikey/Kconfig | 15 ++
board/hisilicon/hikey/Makefile | 8 +
board/hisilicon/hikey/hikey.c | 356 +
configs/hikey_defconfig| 5 +
include/configs/hikey.h| 159 ++
6 files changed, 551 insertions(+)
create mode 100644 board/hisilicon/hikey/Kconfig
create mode 100644 board/hisilicon/hikey/Makefile
create mode 100644 board/hisilicon/hikey/hikey.c
create mode 100644 configs/hikey_defconfig
create mode 100644 include/configs/hikey.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9908b43..767f0d8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -735,6 +735,13 @@ config TARGET_LS2085ARDB
development platform that supports the QorIQ LS2085A
Layerscape Architecture processor.
+config TARGET_HIKEY
+ bool Support HiKey 96boards Consumer Edition Platform
+ select ARM64
+ help
+ Support for HiKey 96boards platform. It features a HI6220
+ SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
+
config TARGET_LS1021AQDS
bool Support ls1021aqds
select CPU_V7
@@ -880,6 +887,7 @@ source board/Marvell/gplugd/Kconfig
source board/armadeus/apf27/Kconfig
source board/armltd/vexpress/Kconfig
source board/armltd/vexpress64/Kconfig
+source board/hisilicon/hikey/Kconfig
source board/bachmann/ot1200/Kconfig
source board/balloon3/Kconfig
source board/barco/platinum/Kconfig
diff --git a/board/hisilicon/hikey/Kconfig b/board/hisilicon/hikey/Kconfig
new file mode 100644
index 000..f7f1055
--- /dev/null
+++ b/board/hisilicon/hikey/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_HIKEY
+
+config SYS_BOARD
+ default hikey
+
+config SYS_VENDOR
+ default hisilicon
+
+config SYS_SOC
+ default hi6220
+
+config SYS_CONFIG_NAME
+ default hikey
+
+endif
diff --git a/board/hisilicon/hikey/Makefile b/board/hisilicon/hikey/Makefile
new file mode 100644
index 000..d4ec8c7
--- /dev/null
+++ b/board/hisilicon/hikey/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := hikey.o
diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c
new file mode 100644
index 000..8c1271b
--- /dev/null
+++ b/board/hisilicon/hikey/hikey.c
@@ -0,0 +1,356 @@
+/*
+ * (C) Copyright 2015 Linaro
+ * Peter Griffin peter.grif...@linaro.org
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include common.h
+#include dm.h
+#include errno.h
+#include malloc.h
+#include netdev.h
+#include asm/io.h
+#include usb.h
+#include power/hi6553_pmic.h
+#include asm-generic/gpio.h
+#include asm/arch/dwmmc.h
+#include asm/arch/gpio.h
+#include asm/arch/periph.h
+#include asm/arch/pinmux.h
+#include asm/arch/hi6220.h
+
+/*TODO drop this table in favour of device tree */
+static const struct hikey_gpio_platdata hi6220_gpio[] = {
+ { 0, HI6220_GPIO_BASE(0)},
+ { 1, HI6220_GPIO_BASE(1)},
+ { 2, HI6220_GPIO_BASE(2)},
+ { 3, HI6220_GPIO_BASE(3)},
+ { 4, HI6220_GPIO_BASE(4)},
+ { 5, HI6220_GPIO_BASE(5)},
+ { 6, HI6220_GPIO_BASE(6)},
+ { 7, HI6220_GPIO_BASE(7)},
+ { 8, HI6220_GPIO_BASE(8)},
+ { 9, HI6220_GPIO_BASE(9)},
+ { 10, HI6220_GPIO_BASE(10)},
+ { 11, HI6220_GPIO_BASE(11)},
+ { 12, HI6220_GPIO_BASE(12)},
+ { 13, HI6220_GPIO_BASE(13)},
+ { 14, HI6220_GPIO_BASE(14)},
+ { 15, HI6220_GPIO_BASE(15)},
+ { 16, HI6220_GPIO_BASE(16)},
+ { 17, HI6220_GPIO_BASE(17)},
+ { 18, HI6220_GPIO_BASE(18)},
+ { 19, HI6220_GPIO_BASE(19)},
+
+};
+
+U_BOOT_DEVICES(hi6220_gpios) = {
+ { gpio_hi6220,
Re: [U-Boot] [PATCH v2 5/6] ARM64: hikey: hi6220: Add u-boot support for the 96boards CE HiKey board.
Hi Rob,
On 16 July 2015 at 14:28, Rob Herring robherri...@gmail.com wrote:
On Wed, Jul 15, 2015 at 7:41 PM, Peter Griffin peter.grif...@linaro.org
wrote:
Hi Rob,
On Fri, 10 Jul 2015, Rob Herring wrote:
On Wed, Jul 8, 2015 at 10:57 AM, Peter Griffin
peter.grif...@linaro.org wrote:
HiKey is the first 96boards consumer edition compliant board. It
features a hi6220
SoC which has eight ARM A53 cpu's.
[...]
snip
You are probably going to want to setup multiple serial consoles
(debug + LS header). That can come later, but I've figured out how to
enable that if you are interested.
Yes I'm interested, please do let me know :)
See this commit:
https://git.linaro.org/people/rob.herring/u-boot.git/commitdiff/f1d0aef06ae7fe09793d46589bd94fa36c45bbc0
This may be 8250 specific and require more work for pl011 driver. The
mixture of 0 and 1 based indexing makes it fun too.
OK thanks for the pointer :) I'm waiting for one of Grants expansion boards
to be sent to me, so will try it out when it arrives.
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ kernel_name=Image\0 \
+ kernel_addr=0x000\0 \
Shouldn't this be 0x8 to avoid copying from 0x0 to 0x8.
I've updated this. Kernel boot time is much reduced with this and also
the
icache being enabled.
Also, this should be kernel_addr_r
Fixed in v3
+ fdt_name=hi6220-hikey.dtb\0 \
+ fdt_addr=0x030\0 \
and fdt_addr_r
Fixed in v3
+ max_fdt=0x10\0 \
I don't think this is needed.
Removed in V3
+ fdt_high=0x\0 \
+ initrd_high=0x\0 \
+
+/* Assume we boot with root on the first partition of a USB stick */
+#define CONFIG_BOOTARGSconsole=ttyAMA0,115200n8
/dev/mmcblk0p7 rw
/dev/mmcblk0p7 doesn't look right. You mean root=/dev/...?
Good spot, yes your right. Plus now you highlight it the comment above
also needs updating.
Will fix in V3.
+
+/* Copy the kernel and FDT to DRAM memory and boot */
+#define CONFIG_BOOTCOMMAND booti $kernel_addr_r - $fdt_addr_r
Don't you need to set these variables?
Also, don't you need to load the kernel and dtb first?
Yes, but I'm not sure quite what to make the default here. My personal
workflow is: -
usb start; dhcp; tftp $kernel_addr $kernel_name; tftp $fdt_addr
$fdt_name;
booti $kernel_addr - $fdt_addr
So I could use that unless you have a better idea?
Not really as everyone has their own preferences. I have some thing like
this:
#define CONFIG_BOOTCOMMAND \
while true; do \
mmc read ${fdt_addr_r} 0x1 0x1000; \
fastboot; \
mmc read ${fdt_addr_r} 0x1 0x1000; \
mmc read ${kernel_addr_r} 0x8000 0x8000 \
bootm ${kernel_addr_r} ${kernel_addr_r} ${fdt_addr_r}; \
done
This relies on fastboot doing USB cable detection and it exits if no
USB connection.
USB ethernet is as good a default as any. Otherwise reading Image and
dtb from the 1st or bootable partition (the default) would be
reasonable.
Thanks for sharing your setup, I've updated the bootcmd to be the USB
ethernet by default in the V3 patches.
+/* Preserve enviroment onto sd card */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 1
+#define CONFIG_SYS_MMC_ENV_PART0
Don't you have these reversed? The first MMC device is 0 and I think
partition numbering starts at 1.
Having CONFIG_SYS_MMC_ENV_DEV 1 was deliberate, as the first device is
eMMC, and
I don't have a official partition to save the u-boot enviroment in.
So as not to corrupt anything folks may have flashed into eMMC from the
official
builds I opted to save the u-boot env to SD card which is device 1.
Okay, but don't you have spare space in the partition with u-boot? I
have a single bootloader partition 1MB in size and the last 8? KB is
the env.
Good idea, I'd not thought of that and we could most likely do that if we
wanted. However I plan on sticking with u-boot env on the sd card for the
moment
as Tom pointed out it can be a bit more user friendly for a community board.
However that seems to have been working by luck with ENC_PART being 0,
and it was
actually corrupting the partition table of the SD card. Looking more
closely I think
what I should of used is
#define CONFIG_ENV_IS_IN_FAT
#define FAT_ENV_INTERFACE mmc
#define FAT_ENV_DEVICE_AND_PART 1:1
#define FAT_ENV_FILEuboot.env
This then saves the enviroment on a fat formatted SD card with the
filename
u-boot.env. This is what I plan on using for v3.
Maybe I should additionally request some space in the official eMMC
parition
table and then we could switch over
Re: [U-Boot] [PATCH v2 2/4] nand: lpc32xx: add hardware ECC support
Hi Vladimir, Marek,
Thanks for the feedback; see comments below.
From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Vladimir
Zapolskiy
Hi Marek, Sylvain,
On 29.07.2015 19:50, Marek Vasut wrote:
On Wednesday, July 29, 2015 at 06:14:08 PM, slemieux.t...@gmail.com wrote:
[snip]
static void lpc32xx_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
+#if defined(CONFIG_DMA_LPC32XX) !defined(CONFIG_SPL_BUILD)
I'm not a big fan of those ifdefs -- why not use DMA even in SPL ?
I think the main reason is that DMA in SPL has not been tested yet.
If needed (?) the dependency between DMA and SPL may be described
separately, e.g.
+#if defined(CONFIG_DMA_LPC32XX) defined(CONFIG_SPL_BUILD)
+#warning DMA support in SPL image is not tested
+#endif
Agree with Vladimir to add this change if everybody is OK with the change.
Regarding this particular #ifdef case I suppose just
+#if defined(CONFIG_DMA_LPC32XX)
is good enough here, either it is SPL or U-boot.
I agree with this change for the ifdef; is there any objection to this change?
+ lpc32xx_nand_xfer(mtd, buf, len, 1);
+#else
while (len-- 0)
*buf++ = readl(lpc32xx_nand_slc_regs-data);
+#endif
}
I would propose to add another pair of DMA specific
lpc32xx_read_buf()/lpc32xx_write_buf() functions chosen under
CONFIG_DMA_LPC32XX condition, this might improve readability.
I will do it; it will make the code more easy to read.
--
With best wishes,
Vladimir
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Re: [U-Boot] [PATCH v3 1/2] arch: Make board selection choices optional
Hi Joe, Masahiro-san, On Wed, 2015-07-29 at 20:25 +0300, Alexey Brodkin wrote: Hi Joe, On Wed, 2015-05-13 at 10:11 +0900, Masahiro Yamada wrote: Hi Joe, 2015-05-13 7:12 GMT+09:00 Tom Rini tr...@konsulko.com: diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index c044ad4..85fddd2 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -132,6 +132,7 @@ config ARC_CACHE_LINE_SHIFT choice prompt Target select + optional config TARGET_DUMMY bool Dummy target You do not need to add optional to the ARC board select because Alexey intentionally added TARGET_DUMMY to the top of the board select list. This is another solution to not lose any CONFIG_BOARD_ by savedefconfig although I personally prefer this idea very much. It looks like I'm not the only one suffering from that change. For UniPhier that issue was resolved by Masahiro with replacement of optional with explicit default option. And probably that's the way we'll need to go for all other affected Kconfigs. Still all proposals are more than welcome. -Alexey ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] ARM: tegra: Add p2371-0000 board
From: Stephen Warren swar...@nvidia.com
Signed-off-by: Stephen Warren swar...@nvidia.com
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/tegra210-p2371-.dts | 59 +
arch/arm/mach-tegra/tegra210/Kconfig | 6 +
board/nvidia/p2371-/Kconfig| 12 +
board/nvidia/p2371-/MAINTAINERS| 6 +
board/nvidia/p2371-/Makefile | 8 +
board/nvidia/p2371-/p2371-.c | 48
board/nvidia/p2371-/pinmux-config-p2371-.h | 260 +
configs/p2371-_defconfig | 16 ++
include/configs/p2371-.h | 72 ++
10 files changed, 488 insertions(+)
create mode 100644 arch/arm/dts/tegra210-p2371-.dts
create mode 100644 board/nvidia/p2371-/Kconfig
create mode 100644 board/nvidia/p2371-/MAINTAINERS
create mode 100644 board/nvidia/p2371-/Makefile
create mode 100644 board/nvidia/p2371-/p2371-.c
create mode 100644 board/nvidia/p2371-/pinmux-config-p2371-.h
create mode 100644 configs/p2371-_defconfig
create mode 100644 include/configs/p2371-.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d8e1841eb4d8..f61060fc92e5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -34,6 +34,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra124-nyan-big.dtb \
tegra124-venice2.dtb \
tegra210-e2220-1170.dtb \
+ tegra210-p2371-.dtb \
tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-sld3-ref.dtb \
diff --git a/arch/arm/dts/tegra210-p2371-.dts
b/arch/arm/dts/tegra210-p2371-.dts
new file mode 100644
index ..10172a23ad70
--- /dev/null
+++ b/arch/arm/dts/tegra210-p2371-.dts
@@ -0,0 +1,59 @@
+/dts-v1/;
+
+#include tegra210.dtsi
+
+/ {
+ model = NVIDIA P2371-;
+ compatible = nvidia,p2371-, nvidia,tegra210;
+
+ chosen {
+ stdout-path = uarta;
+ };
+
+ aliases {
+ i2c0 = /i2c@0,7000d000;
+ sdhci0 = /sdhci@0,700b0600;
+ sdhci1 = /sdhci@0,700b;
+ usb0 = /usb@0,7d00;
+ };
+
+ memory {
+ reg = 0x0 0x8000 0x0 0xc000;
+ };
+
+ sdhci@0,700b {
+ status = okay;
+ cd-gpios = gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW;
+ power-gpios = gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH;
+ bus-width = 4;
+ };
+
+ sdhci@0,700b0600 {
+ status = okay;
+ bus-width = 8;
+ };
+
+ i2c@0,7000d000 {
+ status = okay;
+ clock-frequency = 40;
+ };
+
+ usb@0,7d00 {
+ status = okay;
+ dr_mode = otg;
+ nvidia,vbus-gpio = gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH;
+ };
+
+ clocks {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ clk32k_in: clock@0 {
+ compatible = fixed-clock;
+ reg = 0;
+ #clock-cells = 0;
+ clock-frequency = 32768;
+ };
+ };
+};
diff --git a/arch/arm/mach-tegra/tegra210/Kconfig
b/arch/arm/mach-tegra/tegra210/Kconfig
index 9633ba8c629e..895002c5942b 100644
--- a/arch/arm/mach-tegra/tegra210/Kconfig
+++ b/arch/arm/mach-tegra/tegra210/Kconfig
@@ -8,6 +8,11 @@ config TARGET_E2220_1170
help
E2220-1170 ERS
+config TARGET_P2371_
+ bool NVIDIA Tegra210 P2371- base board
+ help
+ P2371-
+
config TARGET_P2571
bool NVIDIA Tegra210 P2571 base board
help
@@ -19,6 +24,7 @@ config SYS_SOC
default tegra210
source board/nvidia/e2220-1170/Kconfig
+source board/nvidia/p2371-/Kconfig
source board/nvidia/p2571/Kconfig
endif
diff --git a/board/nvidia/p2371-/Kconfig b/board/nvidia/p2371-/Kconfig
new file mode 100644
index ..f94be12be1a0
--- /dev/null
+++ b/board/nvidia/p2371-/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_P2371_
+
+config SYS_BOARD
+ default p2371-
+
+config SYS_VENDOR
+ default nvidia
+
+config SYS_CONFIG_NAME
+ default p2371-
+
+endif
diff --git a/board/nvidia/p2371-/MAINTAINERS
b/board/nvidia/p2371-/MAINTAINERS
new file mode 100644
index ..e6d04bf7c5e1
--- /dev/null
+++ b/board/nvidia/p2371-/MAINTAINERS
@@ -0,0 +1,6 @@
+P2371- BOARD
+M: Tom Warren twar...@nvidia.com
+S: Maintained
+F: board/nvidia/p2371-/
+F: include/configs/p2371-.h
+F: configs/p2371-_defconfig
diff --git a/board/nvidia/p2371-/Makefile b/board/nvidia/p2371-/Makefile
new file mode 100644
index ..9f580ae5b296
--- /dev/null
+++ b/board/nvidia/p2371-/Makefile
[U-Boot] [PATCH 1/2] ARM: tegra: Add e2220-1170 board
From: Stephen Warren swar...@nvidia.com
Signed-off-by: Stephen Warren swar...@nvidia.com
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/tegra210-e2220-1170.dts | 58 +
arch/arm/mach-tegra/tegra210/Kconfig | 6 +
board/nvidia/e2220-1170/Kconfig| 12 +
board/nvidia/e2220-1170/MAINTAINERS| 6 +
board/nvidia/e2220-1170/Makefile | 8 +
board/nvidia/e2220-1170/e2220-1170.c | 48
board/nvidia/e2220-1170/pinmux-config-e2220-1170.h | 269 +
configs/e2220-1170_defconfig | 16 ++
include/configs/e2220-1170.h | 72 ++
10 files changed, 496 insertions(+)
create mode 100644 arch/arm/dts/tegra210-e2220-1170.dts
create mode 100644 board/nvidia/e2220-1170/Kconfig
create mode 100644 board/nvidia/e2220-1170/MAINTAINERS
create mode 100644 board/nvidia/e2220-1170/Makefile
create mode 100644 board/nvidia/e2220-1170/e2220-1170.c
create mode 100644 board/nvidia/e2220-1170/pinmux-config-e2220-1170.h
create mode 100644 configs/e2220-1170_defconfig
create mode 100644 include/configs/e2220-1170.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ba6355379cba..d8e1841eb4d8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -33,6 +33,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra124-jetson-tk1.dtb \
tegra124-nyan-big.dtb \
tegra124-venice2.dtb \
+ tegra210-e2220-1170.dtb \
tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-sld3-ref.dtb \
diff --git a/arch/arm/dts/tegra210-e2220-1170.dts
b/arch/arm/dts/tegra210-e2220-1170.dts
new file mode 100644
index ..75efbba1061e
--- /dev/null
+++ b/arch/arm/dts/tegra210-e2220-1170.dts
@@ -0,0 +1,58 @@
+/dts-v1/;
+
+#include tegra210.dtsi
+
+/ {
+ model = NVIDIA E2220-1170;
+ compatible = nvidia,e2220-1170, nvidia,tegra210;
+
+ chosen {
+ stdout-path = uarta;
+ };
+
+ aliases {
+ i2c0 = /i2c@0,7000d000;
+ sdhci0 = /sdhci@0,700b0600;
+ sdhci1 = /sdhci@0,700b;
+ usb0 = /usb@0,7d00;
+ };
+
+ memory {
+ reg = 0x0 0x8000 0x0 0xc000;
+ };
+
+ sdhci@0,700b {
+ status = okay;
+ cd-gpios = gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW;
+ power-gpios = gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH;
+ bus-width = 4;
+ };
+
+ sdhci@0,700b0600 {
+ status = okay;
+ bus-width = 8;
+ };
+
+ i2c@0,7000d000 {
+ status = okay;
+ clock-frequency = 40;
+ };
+
+ usb@0,7d00 {
+ status = okay;
+ dr_mode = peripheral;
+ };
+
+ clocks {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ clk32k_in: clock@0 {
+ compatible = fixed-clock;
+ reg = 0;
+ #clock-cells = 0;
+ clock-frequency = 32768;
+ };
+ };
+};
diff --git a/arch/arm/mach-tegra/tegra210/Kconfig
b/arch/arm/mach-tegra/tegra210/Kconfig
index 147e6a83d722..9633ba8c629e 100644
--- a/arch/arm/mach-tegra/tegra210/Kconfig
+++ b/arch/arm/mach-tegra/tegra210/Kconfig
@@ -3,6 +3,11 @@ if TEGRA210
choice
prompt Tegra210 board select
+config TARGET_E2220_1170
+ bool NVIDIA Tegra210 E2220-1170 base board
+ help
+ E2220-1170 ERS
+
config TARGET_P2571
bool NVIDIA Tegra210 P2571 base board
help
@@ -13,6 +18,7 @@ endchoice
config SYS_SOC
default tegra210
+source board/nvidia/e2220-1170/Kconfig
source board/nvidia/p2571/Kconfig
endif
diff --git a/board/nvidia/e2220-1170/Kconfig b/board/nvidia/e2220-1170/Kconfig
new file mode 100644
index ..0a30f4936223
--- /dev/null
+++ b/board/nvidia/e2220-1170/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_E2220_1170
+
+config SYS_BOARD
+ default e2220-1170
+
+config SYS_VENDOR
+ default nvidia
+
+config SYS_CONFIG_NAME
+ default e2220-1170
+
+endif
diff --git a/board/nvidia/e2220-1170/MAINTAINERS
b/board/nvidia/e2220-1170/MAINTAINERS
new file mode 100644
index ..0abb37884018
--- /dev/null
+++ b/board/nvidia/e2220-1170/MAINTAINERS
@@ -0,0 +1,6 @@
+E2220-1170 BOARD
+M: Tom Warren twar...@nvidia.com
+S: Maintained
+F: board/nvidia/e2220-1170/
+F: include/configs/e2220-1170.h
+F: configs/e2220-1170_defconfig
diff --git a/board/nvidia/e2220-1170/Makefile b/board/nvidia/e2220-1170/Makefile
new file mode 100644
index ..c956b1972deb
--- /dev/null
+++ b/board/nvidia/e2220-1170/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2013-2015
+# NVIDIA Corporation www.nvidia.com
+#
+#
[U-Boot] [PATCH V2 2/2] ARM: tegra: Add p2371-0000 board
From: Stephen Warren swar...@nvidia.com
Signed-off-by: Stephen Warren swar...@nvidia.com
---
v2: Use named constants for PMIC I2C and register addresses.
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/tegra210-p2371-.dts | 59 +
arch/arm/mach-tegra/tegra210/Kconfig | 6 +
board/nvidia/p2371-/Kconfig| 12 +
board/nvidia/p2371-/MAINTAINERS| 6 +
board/nvidia/p2371-/Makefile | 8 +
board/nvidia/p2371-/p2371-.c | 51
board/nvidia/p2371-/pinmux-config-p2371-.h | 260 +
configs/p2371-_defconfig | 16 ++
include/configs/p2371-.h | 72 ++
10 files changed, 491 insertions(+)
create mode 100644 arch/arm/dts/tegra210-p2371-.dts
create mode 100644 board/nvidia/p2371-/Kconfig
create mode 100644 board/nvidia/p2371-/MAINTAINERS
create mode 100644 board/nvidia/p2371-/Makefile
create mode 100644 board/nvidia/p2371-/p2371-.c
create mode 100644 board/nvidia/p2371-/pinmux-config-p2371-.h
create mode 100644 configs/p2371-_defconfig
create mode 100644 include/configs/p2371-.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d8e1841eb4d8..f61060fc92e5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -34,6 +34,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra124-nyan-big.dtb \
tegra124-venice2.dtb \
tegra210-e2220-1170.dtb \
+ tegra210-p2371-.dtb \
tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-sld3-ref.dtb \
diff --git a/arch/arm/dts/tegra210-p2371-.dts
b/arch/arm/dts/tegra210-p2371-.dts
new file mode 100644
index ..10172a23ad70
--- /dev/null
+++ b/arch/arm/dts/tegra210-p2371-.dts
@@ -0,0 +1,59 @@
+/dts-v1/;
+
+#include tegra210.dtsi
+
+/ {
+ model = NVIDIA P2371-;
+ compatible = nvidia,p2371-, nvidia,tegra210;
+
+ chosen {
+ stdout-path = uarta;
+ };
+
+ aliases {
+ i2c0 = /i2c@0,7000d000;
+ sdhci0 = /sdhci@0,700b0600;
+ sdhci1 = /sdhci@0,700b;
+ usb0 = /usb@0,7d00;
+ };
+
+ memory {
+ reg = 0x0 0x8000 0x0 0xc000;
+ };
+
+ sdhci@0,700b {
+ status = okay;
+ cd-gpios = gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW;
+ power-gpios = gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH;
+ bus-width = 4;
+ };
+
+ sdhci@0,700b0600 {
+ status = okay;
+ bus-width = 8;
+ };
+
+ i2c@0,7000d000 {
+ status = okay;
+ clock-frequency = 40;
+ };
+
+ usb@0,7d00 {
+ status = okay;
+ dr_mode = otg;
+ nvidia,vbus-gpio = gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH;
+ };
+
+ clocks {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ clk32k_in: clock@0 {
+ compatible = fixed-clock;
+ reg = 0;
+ #clock-cells = 0;
+ clock-frequency = 32768;
+ };
+ };
+};
diff --git a/arch/arm/mach-tegra/tegra210/Kconfig
b/arch/arm/mach-tegra/tegra210/Kconfig
index 9633ba8c629e..895002c5942b 100644
--- a/arch/arm/mach-tegra/tegra210/Kconfig
+++ b/arch/arm/mach-tegra/tegra210/Kconfig
@@ -8,6 +8,11 @@ config TARGET_E2220_1170
help
E2220-1170 ERS
+config TARGET_P2371_
+ bool NVIDIA Tegra210 P2371- base board
+ help
+ P2371-
+
config TARGET_P2571
bool NVIDIA Tegra210 P2571 base board
help
@@ -19,6 +24,7 @@ config SYS_SOC
default tegra210
source board/nvidia/e2220-1170/Kconfig
+source board/nvidia/p2371-/Kconfig
source board/nvidia/p2571/Kconfig
endif
diff --git a/board/nvidia/p2371-/Kconfig b/board/nvidia/p2371-/Kconfig
new file mode 100644
index ..f94be12be1a0
--- /dev/null
+++ b/board/nvidia/p2371-/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_P2371_
+
+config SYS_BOARD
+ default p2371-
+
+config SYS_VENDOR
+ default nvidia
+
+config SYS_CONFIG_NAME
+ default p2371-
+
+endif
diff --git a/board/nvidia/p2371-/MAINTAINERS
b/board/nvidia/p2371-/MAINTAINERS
new file mode 100644
index ..e6d04bf7c5e1
--- /dev/null
+++ b/board/nvidia/p2371-/MAINTAINERS
@@ -0,0 +1,6 @@
+P2371- BOARD
+M: Tom Warren twar...@nvidia.com
+S: Maintained
+F: board/nvidia/p2371-/
+F: include/configs/p2371-.h
+F: configs/p2371-_defconfig
diff --git a/board/nvidia/p2371-/Makefile b/board/nvidia/p2371-/Makefile
new file mode 100644
index
[U-Boot] [PATCH V2 1/2] ARM: tegra: Add e2220-1170 board
From: Stephen Warren swar...@nvidia.com
Signed-off-by: Stephen Warren swar...@nvidia.com
---
v2: Use named constants for PMIC I2C and register addresses.
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/tegra210-e2220-1170.dts | 58 +
arch/arm/mach-tegra/tegra210/Kconfig | 6 +
board/nvidia/e2220-1170/Kconfig| 12 +
board/nvidia/e2220-1170/MAINTAINERS| 6 +
board/nvidia/e2220-1170/Makefile | 8 +
board/nvidia/e2220-1170/e2220-1170.c | 51
board/nvidia/e2220-1170/pinmux-config-e2220-1170.h | 269 +
configs/e2220-1170_defconfig | 16 ++
include/configs/e2220-1170.h | 72 ++
10 files changed, 499 insertions(+)
create mode 100644 arch/arm/dts/tegra210-e2220-1170.dts
create mode 100644 board/nvidia/e2220-1170/Kconfig
create mode 100644 board/nvidia/e2220-1170/MAINTAINERS
create mode 100644 board/nvidia/e2220-1170/Makefile
create mode 100644 board/nvidia/e2220-1170/e2220-1170.c
create mode 100644 board/nvidia/e2220-1170/pinmux-config-e2220-1170.h
create mode 100644 configs/e2220-1170_defconfig
create mode 100644 include/configs/e2220-1170.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ba6355379cba..d8e1841eb4d8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -33,6 +33,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra124-jetson-tk1.dtb \
tegra124-nyan-big.dtb \
tegra124-venice2.dtb \
+ tegra210-e2220-1170.dtb \
tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-sld3-ref.dtb \
diff --git a/arch/arm/dts/tegra210-e2220-1170.dts
b/arch/arm/dts/tegra210-e2220-1170.dts
new file mode 100644
index ..75efbba1061e
--- /dev/null
+++ b/arch/arm/dts/tegra210-e2220-1170.dts
@@ -0,0 +1,58 @@
+/dts-v1/;
+
+#include tegra210.dtsi
+
+/ {
+ model = NVIDIA E2220-1170;
+ compatible = nvidia,e2220-1170, nvidia,tegra210;
+
+ chosen {
+ stdout-path = uarta;
+ };
+
+ aliases {
+ i2c0 = /i2c@0,7000d000;
+ sdhci0 = /sdhci@0,700b0600;
+ sdhci1 = /sdhci@0,700b;
+ usb0 = /usb@0,7d00;
+ };
+
+ memory {
+ reg = 0x0 0x8000 0x0 0xc000;
+ };
+
+ sdhci@0,700b {
+ status = okay;
+ cd-gpios = gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW;
+ power-gpios = gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH;
+ bus-width = 4;
+ };
+
+ sdhci@0,700b0600 {
+ status = okay;
+ bus-width = 8;
+ };
+
+ i2c@0,7000d000 {
+ status = okay;
+ clock-frequency = 40;
+ };
+
+ usb@0,7d00 {
+ status = okay;
+ dr_mode = peripheral;
+ };
+
+ clocks {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ clk32k_in: clock@0 {
+ compatible = fixed-clock;
+ reg = 0;
+ #clock-cells = 0;
+ clock-frequency = 32768;
+ };
+ };
+};
diff --git a/arch/arm/mach-tegra/tegra210/Kconfig
b/arch/arm/mach-tegra/tegra210/Kconfig
index 147e6a83d722..9633ba8c629e 100644
--- a/arch/arm/mach-tegra/tegra210/Kconfig
+++ b/arch/arm/mach-tegra/tegra210/Kconfig
@@ -3,6 +3,11 @@ if TEGRA210
choice
prompt Tegra210 board select
+config TARGET_E2220_1170
+ bool NVIDIA Tegra210 E2220-1170 base board
+ help
+ E2220-1170 ERS
+
config TARGET_P2571
bool NVIDIA Tegra210 P2571 base board
help
@@ -13,6 +18,7 @@ endchoice
config SYS_SOC
default tegra210
+source board/nvidia/e2220-1170/Kconfig
source board/nvidia/p2571/Kconfig
endif
diff --git a/board/nvidia/e2220-1170/Kconfig b/board/nvidia/e2220-1170/Kconfig
new file mode 100644
index ..0a30f4936223
--- /dev/null
+++ b/board/nvidia/e2220-1170/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_E2220_1170
+
+config SYS_BOARD
+ default e2220-1170
+
+config SYS_VENDOR
+ default nvidia
+
+config SYS_CONFIG_NAME
+ default e2220-1170
+
+endif
diff --git a/board/nvidia/e2220-1170/MAINTAINERS
b/board/nvidia/e2220-1170/MAINTAINERS
new file mode 100644
index ..0abb37884018
--- /dev/null
+++ b/board/nvidia/e2220-1170/MAINTAINERS
@@ -0,0 +1,6 @@
+E2220-1170 BOARD
+M: Tom Warren twar...@nvidia.com
+S: Maintained
+F: board/nvidia/e2220-1170/
+F: include/configs/e2220-1170.h
+F: configs/e2220-1170_defconfig
diff --git a/board/nvidia/e2220-1170/Makefile b/board/nvidia/e2220-1170/Makefile
new file mode 100644
index ..c956b1972deb
--- /dev/null
+++ b/board/nvidia/e2220-1170/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright
Re: [U-Boot] [PATCH v4 2/4] nand: lpc32xx: add SLC NAND controller support
From: Scott Wood [mailto:scottw...@freescale.com] Sent: 27-Jul-15 9:24 PM On Sat, 2015-07-18 at 03:07 +0300, Vladimir Zapolskiy wrote: The change adds support of LPC32xx SLC NAND controller. LPC32xx SoC has two different mutually exclusive NAND controllers to communicate with single and multiple layer chips. This simple driver allows to specify NAND chip timings and defines custom read_buf()/write_buf() operations, because access to 8-bit data register must be 32-bit aligned. Support of hardware ECC calculation is not implemented (data correction is always done by software), since it requires a working DMA engine. The driver can be included to an SPL image. Signed-off-by: Vladimir Zapolskiy v...@mleia.com --- Changes from v3 to v4: * renamed lpc32xx_nand_slc_registers to lpc32xx_nand_slc_regs, * replaced non-leading tabs with spaces to get columned assignments, * removed leftover redundant type casts, * lpc32xx_nand_cmd_ctrl() sets address register iff (ctrl NAND_ALE). Changes from v2 to v3: * no changes, sent a non-rebased version by mistake. Changes from v1 to v2: * addressed Albert's and Scott's comments to LPC32xx SLC NAND driver: - removed unnecessary uint32_t casts in write_buf()/write_byte(), - removed IO_ADDR_[RW] assignment, this is done in nand.c for SPL and generally not needed for custom defined PIO interfaces in U-boot (with exception of simple NAND SPL, addressed by 1/4), - removed leftover declarations of HW ECC related bit fields, this should be added along with HW ECC support, - improved description of a reason why software ECC is selected, if DMA is unavailable (explicit reference to User Manual from NXP). Previous review can be found here: v3: http://lists.denx.de/pipermail/u-boot/2015-July/219431.html v2: http://lists.denx.de/pipermail/u-boot/2015-July/219422.html v1: http://lists.denx.de/pipermail/u-boot/2015-July/219095.html http://lists.denx.de/pipermail/u-boot/2015-July/219254.html arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 6 + arch/arm/include/asm/arch-lpc32xx/clk.h | 2 + arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/lpc32xx_nand_slc.c | 176 ++ 5 files changed, 186 insertions(+) create mode 100644 drivers/mtd/nand/lpc32xx_nand_slc.c Acked-by: Scott Wood scottw...@freescale.com -Scott Tested for large page NAND. Tested-by: Sylvain Lemieux slemi...@tycoint.com This e-mail contains privileged and confidential information intended for the use of the addressees named above. If you are not the intended recipient of this e-mail, you are hereby notified that you must not disseminate, copy or take any action in respect of any information contained in it. If you have received this e-mail in error, please notify the sender immediately by e-mail and immediately destroy this e-mail and its attachments. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] ARM: tegra: restrict usable RAM size further
From: Stephen Warren swar...@nvidia.com
Additionally, ARM64 devices typically run a secure monitor in EL3 and
U-Boot in EL2, and set up some secure RAM carve-outs to contain the EL3
code and data. These carve-outs are located at the top of 32-bit address
space. Restrict U-Boot's RAM usage to well below the location of those
carve-outs. Ideally, we would the secure monitor would inform U-Boot of
exactly which RAM it could use at run-time. However, I'm not sure how to
do that at present (and even if such a mechanism does exist, it would
likely not be generic across all forms of secure monitor).
Signed-off-by: Stephen Warren swar...@nvidia.com
---
arch/arm/mach-tegra/board2.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 36bcfb04c021..7842caaa5afb 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -287,11 +287,20 @@ void pad_init_mmc(struct mmc_host *host)
* 32-bits of the physical address space. Cap the maximum usable RAM area
* at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit
* boundary that most devices can address.
+ *
+ * Additionally, ARM64 devices typically run a secure monitor in EL3 and
+ * U-Boot in EL2, and set up some secure RAM carve-outs to contain the EL3
+ * code and data. These carve-outs are located at the top of 32-bit address
+ * space. Restrict U-Boot's RAM usage to well below the location of those
+ * carve-outs. Ideally, we would the secure monitor would inform U-Boot of
+ * exactly which RAM it could use at run-time. However, I'm not sure how to
+ * do that at present (and even if such a mechanism does exist, it would
+ * likely not be generic across all forms of secure monitor).
*/
ulong board_get_usable_ram_top(ulong total_size)
{
- if (gd-ram_top 0x1)
- return 0x1;
+ if (gd-ram_top 0xe000)
+ return 0xe000;
return gd-ram_top;
}
--
1.9.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.
Added PLL variables (dividers mask/shift, lock enable/detect, etc.)
to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X.
Used pllinfo struct in all clock functions, validated on T210.
Should be equivalent to prior code on T124/114/30/20 but needs test.
Corrections to divm mask vs shift and T20/30 divN masks thanks to
Marcel Ziswiler.
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/include/asm/arch-tegra/clk_rst.h | 32 +--
arch/arm/include/asm/arch-tegra/clock.h | 21 +
arch/arm/include/asm/arch-tegra210/clock-tables.h | 1 +
arch/arm/mach-tegra/clock.c | 108 --
arch/arm/mach-tegra/cpu.c | 18 ++--
arch/arm/mach-tegra/tegra114/clock.c | 57 +---
arch/arm/mach-tegra/tegra114/cpu.c| 39 +++-
arch/arm/mach-tegra/tegra124/clock.c | 44 -
arch/arm/mach-tegra/tegra124/cpu.c| 31 +++
arch/arm/mach-tegra/tegra20/clock.c | 32 +++
arch/arm/mach-tegra/tegra210/clock.c | 31 ++-
arch/arm/mach-tegra/tegra30/clock.c | 45 ++---
12 files changed, 285 insertions(+), 174 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h
b/arch/arm/include/asm/arch-tegra/clk_rst.h
index f690260..ee9436e 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -249,17 +249,6 @@ struct clk_rst_ctlr {
#define PLL_LOCK_SHIFT 27
#define PLL_LOCK_MASK (1U PLL_LOCK_SHIFT)
-#define PLL_DIVP_SHIFT 20
-#define PLL_DIVP_MASK (7U PLL_DIVP_SHIFT)
-/* Special case for T210 PLLU DIVP */
-#define PLLU_DIVP_SHIFT16
-
-#define PLL_DIVN_SHIFT 8
-#define PLL_DIVN_MASK (0x3ffU PLL_DIVN_SHIFT)
-
-#define PLL_DIVM_SHIFT 0
-#define PLL_DIVM_MASK (0x1f PLL_DIVM_SHIFT)
-
/* CLK_RST_CONTROLLER_PLLx_OUTx_0 */
#define PLL_OUT_RSTN (1 0)
#define PLL_OUT_CLKEN (1 1)
@@ -272,24 +261,6 @@ struct clk_rst_ctlr {
#define PLL_DCCON_SHIFT20
#define PLL_DCCON_MASK (1U PLL_DCCON_SHIFT)
-#define PLL_LOCK_ENABLE_SHIFT 18
-#define PLL_LOCK_ENABLE_MASK (1U PLL_LOCK_ENABLE_SHIFT)
-
-#define PLL_CPCON_SHIFT8
-#define PLL_CPCON_MASK (15U PLL_CPCON_SHIFT)
-
-#define PLL_LFCON_SHIFT4
-#define PLL_LFCON_MASK (15U PLL_LFCON_SHIFT)
-
-/* CPCON/LFCON replaced by KCP/KVCO in T210 PLLU */
-#define PLLU_KVCO_SHIFT24
-#define PLLU_KVCO_MASK (3U PLLU_KVCO_SHIFT)
-#define PLLU_KCP_SHIFT 25
-#define PLLU_KCP_MASK (1U PLLU_KCP_SHIFT)
-
-#define PLLU_VCO_FREQ_SHIFT20
-#define PLLU_VCO_FREQ_MASK (1U PLLU_VCO_FREQ_SHIFT)
-
#define PLLP_OUT1_OVR (1 2)
#define PLLP_OUT2_OVR (1 18)
#define PLLP_OUT3_OVR (1 2)
@@ -475,4 +446,7 @@ enum {
#define PLLDP_SS_CFG_UNDOCUMENTED (1 24)
#define PLLDP_SS_CFG_DITHER(1 28)
+/* CLK_RST_PLLD_MISC */
+#define PLLD_CLKENABLE 30
+
#endif /* _TEGRA_CLK_RST_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/clock.h
b/arch/arm/include/asm/arch-tegra/clock.h
index 2274b14..d570d7f 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -338,6 +338,27 @@ void arch_timer_init(void);
void tegra30_set_up_pllp(void);
+/* Number of PLL-based clocks (i.e. not OSC or 32KHz) */
+#define CLOCK_ID_PLL_COUNT (CLOCK_ID_COUNT - 2)
+
+struct clk_pll_info {
+ u32 m_shift:5; /* DIVM_SHIFT */
+ u32 n_shift:5; /* DIVN_SHIFT */
+ u32 p_shift:5; /* DIVP_SHIFT */
+ u32 kcp_shift:5;/* KCP/cpcon SHIFT */
+ u32 kvco_shift:5; /* KVCO/lfcon SHIFT */
+ u32 lock_ena:6; /* LOCK_ENABLE/EN_LOCKDET shift */
+ u32 rsvd:1;
+ u32 m_mask:10; /* DIVM_MASK */
+ u32 n_mask:12; /* DIVN_MASK */
+ u32 p_mask:10; /* DIVP_MASK or VCO_MASK */
+ u32 kcp_mask:10;/* KCP/CPCON MASK */
+ u32 kvco_mask:10; /* KVCO/LFCON MASK */
+ u32 lock_det:6; /* LOCK_DETECT/LOCKED shift */
+ u32 rsvd2:6;
+};
+extern struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT];
+
/**
* Enable output clock for external peripherals
*
diff --git a/arch/arm/include/asm/arch-tegra210/clock-tables.h
b/arch/arm/include/asm/arch-tegra210/clock-tables.h
index b62e070..175040d 100644
--- a/arch/arm/include/asm/arch-tegra210/clock-tables.h
+++ b/arch/arm/include/asm/arch-tegra210/clock-tables.h
@@ -25,6 +25,7 @@ enum clock_id {
CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
CLOCK_ID_EPCI,
CLOCK_ID_SFROM32KHZ,
+ CLOCK_ID_DP,
/* These are the base clocks (inputs to the Tegra SoC) */
CLOCK_ID_32KHZ,
diff --git
Re: [U-Boot] [PATCH] T210: P2571: Enable SD-card power via PMIC LDO2
On 07/29/2015 10:24 AM, Tom Warren wrote: This was done in the 32-bit AVP loader (SPL) but is board-specific so should be moved to the CPU portion. For: T210: P2571: Enable SD-card power via PMIC LDO2 T210: P2571: Restore USB gadget mode (ums) T210: P2571: Turn CPU fan on Acked-by: Stephen Warren swar...@nvidia.com (the line lengths in the commit messages are very short...) For: Tegra: Allow TZ writes to VPR aperature regs I need to learn/think some more to review that. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] Tegra: clocks: Add 38.4MHz OSC support for T210 use
Added 38.4MHz/48MHz entries to pll_x_table for CPU PLL. Needs
to be measured - should be close to 700MHz (1.4G/2).
Note that some freqs aren't in the PLLU table in T210 TRM
(13, 26MHz), so I used the 12MHz table entry for them. They
shouldn't be selected since they're not viable T210 OSC freqs.
Since there are now 2 new OSC defines, all tables (pll_x_table,
PLLU) had to increase by two entries, but since 38.4/48MHz are
not viable osc freqs on T20/30/114, etc, they're just set to 0.
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/include/asm/arch-tegra/clock.h | 2 ++
arch/arm/mach-tegra/clock.c | 13 +
arch/arm/mach-tegra/cpu.c | 12
arch/arm/mach-tegra/tegra210/clock.c| 8 ++--
drivers/usb/host/ehci-tegra.c | 18 +-
5 files changed, 42 insertions(+), 11 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra/clock.h
b/arch/arm/include/asm/arch-tegra/clock.h
index f9dd3c8..2274b14 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -16,6 +16,8 @@ enum clock_osc_freq {
CLOCK_OSC_FREQ_19_2,
CLOCK_OSC_FREQ_12_0,
CLOCK_OSC_FREQ_26_0,
+ CLOCK_OSC_FREQ_38_4,
+ CLOCK_OSC_FREQ_48_0,
CLOCK_OSC_FREQ_COUNT,
};
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 5d968d8..d0eebd2 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -44,6 +44,8 @@ static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
1920,
1200,
2600,
+ 3840,
+ 4800,
};
/* return 1 if a peripheral ID is in range */
@@ -620,17 +622,20 @@ int clock_verify(void)
void clock_init(void)
{
+ pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
- pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
+ pll_rate[CLOCK_ID_USB] = clock_get_rate(CLOCK_ID_USB);
pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY);
- pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
- pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
+ pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
+ pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
+
debug(Osc = %d\n, pll_rate[CLOCK_ID_OSC]);
+ debug(PLLC = %d\n, pll_rate[CLOCK_ID_CGENERAL]);
debug(PLLM = %d\n, pll_rate[CLOCK_ID_MEMORY]);
debug(PLLP = %d\n, pll_rate[CLOCK_ID_PERIPH]);
- debug(PLLC = %d\n, pll_rate[CLOCK_ID_CGENERAL]);
+ debug(PLLU = %d\n, pll_rate[CLOCK_ID_USB]);
debug(PLLD = %d\n, pll_rate[CLOCK_ID_DISPLAY]);
debug(PLLX = %d\n, pll_rate[CLOCK_ID_XCPU]);
}
diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c
index f7d45e8..b9391d6 100644
--- a/arch/arm/mach-tegra/cpu.c
+++ b/arch/arm/mach-tegra/cpu.c
@@ -67,6 +67,8 @@ struct clk_pll_table
tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
{ .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
{ .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
{ .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
+ { .n =0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz
(N/A) */
+ { .n =0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz
(N/A) */
},
/*
* T25: 1.2 GHz
@@ -83,6 +85,8 @@ struct clk_pll_table
tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
{ .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
{ .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
{ .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz
(N/A) */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz
(N/A) */
},
/*
* T30: 600 MHz
@@ -99,6 +103,8 @@ struct clk_pll_table
tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
{ .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
{ .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
{ .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz
(N/A) */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz
(N/A) */
},
/*
* T114: 700 MHz
@@ -114,6 +120,8 @@ struct clk_pll_table
tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
{ .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
Re: [U-Boot] [PATCH v3 1/8] usb: dwc2: Call board_usb_init() from usb_lowlevel_init()
On Thu, Jul 30, 2015 at 01:36:07AM +0200, Marek Vasut wrote: On Wednesday, July 29, 2015 at 11:39:29 PM, Peter Griffin wrote: This patch makes the dwc2 controller like ehci / ohci / xhci controllers by calling the board_usb_init() function from usb_lowlevel_init. This can then be implemented by specific platforms to initialise their USB hardware (phys / clocks etc). Signed-off-by: Peter Griffin peter.grif...@linaro.org Applied to u-boot-usb/master, thanks! Bah, can you please send me a PR sooner rather than later then so I can take the rest of the board in, assuming others ack the relevant parts :) Thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC] am33xx: add 600us wait in DDR3 initialization sequence
On Wed, Jul 29, 2015 at 11:57:26AM +, Egli, Samuel wrote: Hi James, thank you for your reply! -Original Message- From: Doublesin, James [mailto:double...@ti.com] Sent: Dienstag, 28. Juli 2015 21:59 To: Egli, Samuel; 'tr...@konsulko.com'; Balbi, Felipe Cc: 'u-boot@lists.denx.de'; 'h...@denx.de'; 'Stefan Roese'; Meier, Roger; Senn, Joerg; Belogolov, Oleg Subject: RE: [RFC] am33xx: add 600us wait in DDR3 initialization sequence Hi Samuel, I don't think these changes are necessary. I think your concern about the initialization steps is not correct. The first setting of the REF_CTRL (before SDRAM_CONFIG write) will be used by the EMIF controller to determine the delay between the rising edge of DDR_RESETn and DDR_CKE. We typically write a value of 0x3100 in REF_CTRL to achieve this, which comes from this formula: (16*SDRAM_REF_CTRL)/400MHz 500us That's interesting. This isn't really documented in the TRM. But I see ddr.c: ... if (regs-zq_config) writel(0x80003100, emif_reg[nr]-emif_sdram_ref_ctrl); ... Why does this depend on zq_config? While debugging I saw that we This part I can answer. We use the same functions on DDR2 and DDR3 and use the presence of zq_config in regs to know if this is a DDR2 or DDR3 setup. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/8] usb: dwc2: Call board_usb_init() from usb_lowlevel_init()
On Wednesday, July 29, 2015 at 11:39:29 PM, Peter Griffin wrote: This patch makes the dwc2 controller like ehci / ohci / xhci controllers by calling the board_usb_init() function from usb_lowlevel_init. This can then be implemented by specific platforms to initialise their USB hardware (phys / clocks etc). Signed-off-by: Peter Griffin peter.grif...@linaro.org Applied to u-boot-usb/master, thanks! Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] ARM: tegra: Add e2220-1170 board
Hi Stephen,
On 29 July 2015 at 13:48, Stephen Warren swar...@wwwdotorg.org wrote:
Commit message?
From: Stephen Warren swar...@nvidia.com
Signed-off-by: Stephen Warren swar...@nvidia.com
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/tegra210-e2220-1170.dts | 58 +
arch/arm/mach-tegra/tegra210/Kconfig | 6 +
board/nvidia/e2220-1170/Kconfig| 12 +
board/nvidia/e2220-1170/MAINTAINERS| 6 +
board/nvidia/e2220-1170/Makefile | 8 +
board/nvidia/e2220-1170/e2220-1170.c | 48
board/nvidia/e2220-1170/pinmux-config-e2220-1170.h | 269
+
configs/e2220-1170_defconfig | 16 ++
include/configs/e2220-1170.h | 72 ++
10 files changed, 496 insertions(+)
create mode 100644 arch/arm/dts/tegra210-e2220-1170.dts
create mode 100644 board/nvidia/e2220-1170/Kconfig
create mode 100644 board/nvidia/e2220-1170/MAINTAINERS
create mode 100644 board/nvidia/e2220-1170/Makefile
create mode 100644 board/nvidia/e2220-1170/e2220-1170.c
create mode 100644 board/nvidia/e2220-1170/pinmux-config-e2220-1170.h
create mode 100644 configs/e2220-1170_defconfig
create mode 100644 include/configs/e2220-1170.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ba6355379cba..d8e1841eb4d8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -33,6 +33,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra124-jetson-tk1.dtb \
tegra124-nyan-big.dtb \
tegra124-venice2.dtb \
+ tegra210-e2220-1170.dtb \
tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-sld3-ref.dtb \
diff --git a/arch/arm/dts/tegra210-e2220-1170.dts
b/arch/arm/dts/tegra210-e2220-1170.dts
new file mode 100644
index ..75efbba1061e
--- /dev/null
+++ b/arch/arm/dts/tegra210-e2220-1170.dts
@@ -0,0 +1,58 @@
+/dts-v1/;
+
+#include tegra210.dtsi
+
+/ {
+ model = NVIDIA E2220-1170;
+ compatible = nvidia,e2220-1170, nvidia,tegra210;
+
+ chosen {
+ stdout-path = uarta;
+ };
+
+ aliases {
+ i2c0 = /i2c@0,7000d000;
+ sdhci0 = /sdhci@0,700b0600;
+ sdhci1 = /sdhci@0,700b;
+ usb0 = /usb@0,7d00;
+ };
+
+ memory {
+ reg = 0x0 0x8000 0x0 0xc000;
+ };
+
+ sdhci@0,700b {
+ status = okay;
+ cd-gpios = gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW;
+ power-gpios = gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH;
+ bus-width = 4;
+ };
+
+ sdhci@0,700b0600 {
+ status = okay;
+ bus-width = 8;
+ };
+
+ i2c@0,7000d000 {
+ status = okay;
+ clock-frequency = 40;
+ };
+
+ usb@0,7d00 {
+ status = okay;
+ dr_mode = peripheral;
+ };
+
+ clocks {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ clk32k_in: clock@0 {
+ compatible = fixed-clock;
+ reg = 0;
+ #clock-cells = 0;
+ clock-frequency = 32768;
+ };
+ };
+};
diff --git a/arch/arm/mach-tegra/tegra210/Kconfig
b/arch/arm/mach-tegra/tegra210/Kconfig
index 147e6a83d722..9633ba8c629e 100644
--- a/arch/arm/mach-tegra/tegra210/Kconfig
+++ b/arch/arm/mach-tegra/tegra210/Kconfig
@@ -3,6 +3,11 @@ if TEGRA210
choice
prompt Tegra210 board select
+config TARGET_E2220_1170
+ bool NVIDIA Tegra210 E2220-1170 base board
+ help
+ E2220-1170 ERS
Er, description?
+
config TARGET_P2571
bool NVIDIA Tegra210 P2571 base board
help
@@ -13,6 +18,7 @@ endchoice
config SYS_SOC
default tegra210
+source board/nvidia/e2220-1170/Kconfig
source board/nvidia/p2571/Kconfig
endif
diff --git a/board/nvidia/e2220-1170/Kconfig b/board/nvidia/e2220-1170/Kconfig
new file mode 100644
index ..0a30f4936223
--- /dev/null
+++ b/board/nvidia/e2220-1170/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_E2220_1170
+
+config SYS_BOARD
+ default e2220-1170
+
+config SYS_VENDOR
+ default nvidia
+
+config SYS_CONFIG_NAME
+ default e2220-1170
+
+endif
diff --git a/board/nvidia/e2220-1170/MAINTAINERS
b/board/nvidia/e2220-1170/MAINTAINERS
new file mode 100644
index ..0abb37884018
--- /dev/null
+++ b/board/nvidia/e2220-1170/MAINTAINERS
@@ -0,0 +1,6 @@
+E2220-1170 BOARD
+M: Tom Warren twar...@nvidia.com
+S: Maintained
+F: board/nvidia/e2220-1170/
+F: include/configs/e2220-1170.h
+F: configs/e2220-1170_defconfig
diff --git
Re: [U-Boot] [PATCH V2 1/2] ARM: tegra: Add e2220-1170 board
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Wednesday, July 29, 2015 1:17 PM
To: u-boot@lists.denx.de; Simon Glass; Tom Warren; Stephen Warren
Cc: Thierry Reding
Subject: [PATCH V2 1/2] ARM: tegra: Add e2220-1170 board
From: Stephen Warren swar...@nvidia.com
Signed-off-by: Stephen Warren swar...@nvidia.com
---
v2: Use named constants for PMIC I2C and register addresses.
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/tegra210-e2220-1170.dts | 58 +
arch/arm/mach-tegra/tegra210/Kconfig | 6 +
board/nvidia/e2220-1170/Kconfig| 12 +
board/nvidia/e2220-1170/MAINTAINERS| 6 +
board/nvidia/e2220-1170/Makefile | 8 +
board/nvidia/e2220-1170/e2220-1170.c | 51
board/nvidia/e2220-1170/pinmux-config-e2220-1170.h | 269
+
configs/e2220-1170_defconfig | 16 ++
include/configs/e2220-1170.h | 72 ++
10 files changed, 499 insertions(+)
create mode 100644 arch/arm/dts/tegra210-e2220-1170.dts
create mode 100644 board/nvidia/e2220-1170/Kconfig create mode 100644
board/nvidia/e2220-1170/MAINTAINERS
create mode 100644 board/nvidia/e2220-1170/Makefile create mode 100644
board/nvidia/e2220-1170/e2220-1170.c
create mode 100644 board/nvidia/e2220-1170/pinmux-config-e2220-1170.h
create mode 100644 configs/e2220-1170_defconfig create mode 100644
include/configs/e2220-1170.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index
ba6355379cba..d8e1841eb4d8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -33,6 +33,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra124-jetson-tk1.dtb \
tegra124-nyan-big.dtb \
tegra124-venice2.dtb \
+ tegra210-e2220-1170.dtb \
tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-sld3-ref.dtb \
diff --git a/arch/arm/dts/tegra210-e2220-1170.dts b/arch/arm/dts/tegra210-
e2220-1170.dts
new file mode 100644
index ..75efbba1061e
--- /dev/null
+++ b/arch/arm/dts/tegra210-e2220-1170.dts
@@ -0,0 +1,58 @@
+/dts-v1/;
+
+#include tegra210.dtsi
+
+/ {
+ model = NVIDIA E2220-1170;
+ compatible = nvidia,e2220-1170, nvidia,tegra210;
+
+ chosen {
+ stdout-path = uarta;
+ };
+
+ aliases {
+ i2c0 = /i2c@0,7000d000;
+ sdhci0 = /sdhci@0,700b0600;
+ sdhci1 = /sdhci@0,700b;
+ usb0 = /usb@0,7d00;
+ };
+
+ memory {
+ reg = 0x0 0x8000 0x0 0xc000;
+ };
+
+ sdhci@0,700b {
+ status = okay;
+ cd-gpios = gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW;
+ power-gpios = gpio TEGRA_GPIO(Z, 4)
GPIO_ACTIVE_HIGH;
+ bus-width = 4;
+ };
+
+ sdhci@0,700b0600 {
+ status = okay;
+ bus-width = 8;
+ };
+
+ i2c@0,7000d000 {
+ status = okay;
+ clock-frequency = 40;
+ };
+
+ usb@0,7d00 {
+ status = okay;
+ dr_mode = peripheral;
+ };
+
+ clocks {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ clk32k_in: clock@0 {
+ compatible = fixed-clock;
+ reg = 0;
+ #clock-cells = 0;
+ clock-frequency = 32768;
+ };
+ };
+};
diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-
tegra/tegra210/Kconfig
index 147e6a83d722..9633ba8c629e 100644
--- a/arch/arm/mach-tegra/tegra210/Kconfig
+++ b/arch/arm/mach-tegra/tegra210/Kconfig
@@ -3,6 +3,11 @@ if TEGRA210
choice
prompt Tegra210 board select
+config TARGET_E2220_1170
+ bool NVIDIA Tegra210 E2220-1170 base board
+ help
+ E2220-1170 ERS
+
config TARGET_P2571
bool NVIDIA Tegra210 P2571 base board
help
@@ -13,6 +18,7 @@ endchoice
config SYS_SOC
default tegra210
+source board/nvidia/e2220-1170/Kconfig
source board/nvidia/p2571/Kconfig
endif
diff --git a/board/nvidia/e2220-1170/Kconfig b/board/nvidia/e2220-
1170/Kconfig new file mode 100644 index ..0a30f4936223
--- /dev/null
+++ b/board/nvidia/e2220-1170/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_E2220_1170
+
+config SYS_BOARD
+ default e2220-1170
+
+config SYS_VENDOR
+ default nvidia
+
+config SYS_CONFIG_NAME
+ default e2220-1170
+
+endif
diff --git a/board/nvidia/e2220-1170/MAINTAINERS b/board/nvidia/e2220-
1170/MAINTAINERS
new file mode 100644
index ..0abb37884018
--- /dev/null
+++ b/board/nvidia/e2220-1170/MAINTAINERS
@@ -0,0 +1,6 @@
+E2220-1170 BOARD
+M: Tom Warren twar...@nvidia.com
+S: Maintained
+F:
Re: [U-Boot] [RFC PATCH 1/7] pinctrl: add pinctrl framework
Hi Masahiro,
On 15 July 2015 at 02:16, Masahiro Yamada yamada.masah...@socionext.com wrote:
Now, a simple pinctrl patch is being proposed by Simon.
http://patchwork.ozlabs.org/patch/487801/
In the design above, as you see, the uclass is just like a wrapper layer
to invoke .request and .get_periph_id of low-level drivers.
In other words, it is Do-It-Yourself thing, so it is up to you how to identify
which peripheral is being handled in your .get_periph_id().
And here is one example for how a low-level pinctrl driver could be
implemented.
http://patchwork.ozlabs.org/patch/487874/
I'm sending some comments on this series since I think you are
planning to rework it. My plan is:
- you respin the series
- apply this series
- it should includes the 'simple' version added to the uclass and
perhaps a CONFIG to select whether the full pinctrl is available (can
be separate patches on top of what you have)
- work out what we are going to do about GPIO / pull-ups
Can/does this use exactly the same binding as Linux? Re the limitation
about not detecting conflicts, why is that? It seems that code could
be added for that, even if optional.
As you see in the thread, honestly, I do not like this approach.
It is true that you can implement .get_periph_id in your driver
better than parsing interrupts properties, but I guess
many drivers would follow the rockchip implmentation because
no helpful infrastructure is provided by the uclass (at least now).
Device trees describe hardwares in a way independent of software
that they are used with. So, identical device trees can be (should be)
used with U-Boot as well as Linux or whatever.
Thus, I want the pinctrl can be controllable by device trees in the same way
of Linux, that is, by parsing pinctrl-names and pinctrl-N properties.
Of course, it would be possible to do it in my own .get_periph_id,
but pinctrl-names and pinctrl-N are too generic to be done in each
low-level driver.
In this series, I'd like to propose to support it in the uclass, so that
we can easily reuse device trees for pinctrl.
Please put it on the table for discussion.
Let me explain how it works.
The basic idea is pretty much like Linux, but it has been much simplified
because full-support of the Linux's pinctrl is too much a burden for a
boot-loader.
Device Tree
---
To use pinctrl from each peripheral, add some properties in the device node.
pinctrl-names is a list of pin states. The default state is mandatory,
and it would probably be enough for U-Boot. But, in order to show how it
works,
say the example device supports two states: default and sleep.
In this case, the properties should be like this.
pinctrl-names = default, sleep;
And then, add as many pinctrl-N properties as the number of states.
pinctrl-0 = phandle to default config node;
pinctrl-1 = phandle to sleep config node;
Here, pinctrl-0, pinctrl-1 corresponds to default, sleep, respectively.
The config nodes are (direct or indirect) children of a pinctrl device.
To sum up, the device tree would be like this:
foo {
compatible = ...;
reg = ...;
pinctrl-names = default, sleep;
pinctrl-0 = foo_default_pin;
pinctrl-1 = foo_sleep_pin;
...
};
pinctrl {
compatible = ...;
reg = ...;
foo_default_pin: foo_default {
groups = ...;
functions = ...;
};
foo_sleep_pin: foo_sleep {
groups = ...;
functions = ...;
};
};
API
---
To set a device into a particular pin state, call
int pinctrl_set_state(struct udevice *dev, const char *state_name).
For example, if you want to set the foo device into the sleep state,
you can do like this:
struct udevice *foo_dev;
(device_get or whatever)
pinctrl_set_state(foo_dev, sleep);
When each device is probed, pinctrl_init() is invoked,
which initializes some pinctrl-specific parameters and set it into default
pin state. Because it is automatically done by the core of driver model,
when a device is probed, its pins are in the default state.
Implementation of low-level driver
--
Currently, two methods are supported in the pinctrl operation:
struct pinctrl_ops {
int (*pinmux_set) (struct udevice *dev, const char *group,
const char *function);
int (*pinconf_set) (struct udevice *dev, const char *group,
const char *conf_param, unsigned conf_arg);
};
They are used to change pin-mux, pin-conf, respectively.
If the pin-config node for the target pin-state is like this,
i2c_default_pin: i2c_default {
groups = i2c-0a;
functions = i2c-0;
};
Your pinmux_set() is called with i2c-0a for the group and i2c-0
for the function.
It is totally up to you what you do
Re: [U-Boot] [PATCH 1/2] ARM: tegra: Add e2220-1170 board
Simon,
I can respond to your Kconfig questions below.
-Original Message-
From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
Sent: Wednesday, July 29, 2015 4:02 PM
To: Stephen Warren
Cc: U-Boot Mailing List; Tom Warren; Stephen Warren; Thierry Reding
Subject: Re: [PATCH 1/2] ARM: tegra: Add e2220-1170 board
Hi Stephen,
On 29 July 2015 at 13:48, Stephen Warren swar...@wwwdotorg.org wrote:
Commit message?
From: Stephen Warren swar...@nvidia.com
Signed-off-by: Stephen Warren swar...@nvidia.com
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/tegra210-e2220-1170.dts | 58 +
arch/arm/mach-tegra/tegra210/Kconfig | 6 +
board/nvidia/e2220-1170/Kconfig| 12 +
board/nvidia/e2220-1170/MAINTAINERS| 6 +
board/nvidia/e2220-1170/Makefile | 8 +
board/nvidia/e2220-1170/e2220-1170.c | 48
board/nvidia/e2220-1170/pinmux-config-e2220-1170.h | 269
+
configs/e2220-1170_defconfig | 16 ++
include/configs/e2220-1170.h | 72 ++
10 files changed, 496 insertions(+)
create mode 100644 arch/arm/dts/tegra210-e2220-1170.dts
create mode 100644 board/nvidia/e2220-1170/Kconfig create mode
100644 board/nvidia/e2220-1170/MAINTAINERS
create mode 100644 board/nvidia/e2220-1170/Makefile create mode
100644 board/nvidia/e2220-1170/e2220-1170.c
create mode 100644 board/nvidia/e2220-1170/pinmux-config-e2220-1170.h
create mode 100644 configs/e2220-1170_defconfig create mode 100644
include/configs/e2220-1170.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index
ba6355379cba..d8e1841eb4d8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -33,6 +33,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra124-jetson-tk1.dtb \
tegra124-nyan-big.dtb \
tegra124-venice2.dtb \
+ tegra210-e2220-1170.dtb \
tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-sld3-ref.dtb \
diff --git a/arch/arm/dts/tegra210-e2220-1170.dts
b/arch/arm/dts/tegra210-e2220-1170.dts
new file mode 100644
index ..75efbba1061e
--- /dev/null
+++ b/arch/arm/dts/tegra210-e2220-1170.dts
@@ -0,0 +1,58 @@
+/dts-v1/;
+
+#include tegra210.dtsi
+
+/ {
+ model = NVIDIA E2220-1170;
+ compatible = nvidia,e2220-1170, nvidia,tegra210;
+
+ chosen {
+ stdout-path = uarta;
+ };
+
+ aliases {
+ i2c0 = /i2c@0,7000d000;
+ sdhci0 = /sdhci@0,700b0600;
+ sdhci1 = /sdhci@0,700b;
+ usb0 = /usb@0,7d00;
+ };
+
+ memory {
+ reg = 0x0 0x8000 0x0 0xc000;
+ };
+
+ sdhci@0,700b {
+ status = okay;
+ cd-gpios = gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW;
+ power-gpios = gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH;
+ bus-width = 4;
+ };
+
+ sdhci@0,700b0600 {
+ status = okay;
+ bus-width = 8;
+ };
+
+ i2c@0,7000d000 {
+ status = okay;
+ clock-frequency = 40;
+ };
+
+ usb@0,7d00 {
+ status = okay;
+ dr_mode = peripheral;
+ };
+
+ clocks {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ clk32k_in: clock@0 {
+ compatible = fixed-clock;
+ reg = 0;
+ #clock-cells = 0;
+ clock-frequency = 32768;
+ };
+ };
+};
diff --git a/arch/arm/mach-tegra/tegra210/Kconfig
b/arch/arm/mach-tegra/tegra210/Kconfig
index 147e6a83d722..9633ba8c629e 100644
--- a/arch/arm/mach-tegra/tegra210/Kconfig
+++ b/arch/arm/mach-tegra/tegra210/Kconfig
@@ -3,6 +3,11 @@ if TEGRA210
choice
prompt Tegra210 board select
+config TARGET_E2220_1170
+ bool NVIDIA Tegra210 E2220-1170 base board
+ help
+ E2220-1170 ERS
Er, description?
+
config TARGET_P2571
bool NVIDIA Tegra210 P2571 base board
help
@@ -13,6 +18,7 @@ endchoice
config SYS_SOC
default tegra210
+source board/nvidia/e2220-1170/Kconfig
source board/nvidia/p2571/Kconfig
endif
diff --git a/board/nvidia/e2220-1170/Kconfig
b/board/nvidia/e2220-1170/Kconfig new file mode 100644 index
..0a30f4936223
--- /dev/null
+++ b/board/nvidia/e2220-1170/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_E2220_1170
+
+config SYS_BOARD
+ default e2220-1170
+
+config SYS_VENDOR
+ default nvidia
Re: [U-Boot] [PATCH 28/55] dm: pmic: max77686: Support all BUCK regulators
Hi Przemyslaw, On 10 July 2015 at 05:53, Przemyslaw Marczak p.marc...@samsung.com wrote: Hello Simon, On 07/03/2015 02:16 AM, Simon Glass wrote: Add support for all BUCK regulators, now that the correct register is accessed for each. Signed-off-by: Simon Glass s...@chromium.org --- drivers/power/regulator/max77686.c | 10 +++--- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/power/regulator/max77686.c b/drivers/power/regulator/max77686.c index 21173fc..427b717 100644 --- a/drivers/power/regulator/max77686.c +++ b/drivers/power/regulator/max77686.c @@ -81,11 +81,7 @@ static int max77686_buck_volt2hex(int buck, int uV) /* hex = (uV - 60) / 12500; */ hex = (uV - MAX77686_BUCK_UV_LMIN) / MAX77686_BUCK_UV_LSTEP; hex_max = MAX77686_BUCK234_VOLT_MAX_HEX; - /** -* Those use voltage scaller - temporary not implemented -* so return just 0 -*/ - return -ENOSYS; + break; default: /* hex = (uV - 75) / 5; */ hex = (uV - MAX77686_BUCK_UV_HMIN) / MAX77686_BUCK_UV_HSTEP; @@ -379,11 +375,11 @@ static int max77686_buck_val(struct udevice *dev, int op, int *uV) case 2: case 3: case 4: - /* Those use voltage scallers - will support in the future */ mask = MAX77686_BUCK234_VOLT_MASK; - return -ENOSYS; + break; default: mask = MAX77686_BUCK_VOLT_MASK; + break; } ret = pmic_read(dev-parent, adr, val, 1); The bucks 2,3,4 can work in DVS mode, which allows select one of eight DVS regulators for each output. The default selection at power-on is DVS1 for each output, and it corresponds to the currently defined output register addresses. The selection can be done by six PMIC's GPIOs: - DVS1/2/3 - output selection: 0x0=DVS1...0x7=DVS8 - SELB2/3/4 - mode switch: 'DVS' or 'no DVS' Reading or writing the default registers is proper only in case: - for the default PMIC's power-up setting - may conflict with bl1/bl2 - when DVS1/2/3 GPIOs are set to LOW - DVS1 selected - SELB2/3/4 - are set to LOW - no DVS mode The documentation is poor, but if I good understand, the SELB is used as latch for the DVS selection. So the driver, could be unreliable for these outputs if it doesn't check the PMIC's GPIOs. It's quite confusing, since the PMIC, doesn't provide registers to check those GPIOs. It should be checked by the driver and can be delivered by device-tree. This is also confusing, since it depends on board design, because the PMIC's GPIOs can be connected to the SoCs GPIOs and also just pulled to POWER/GND signals. The documentation says, that those GPIOs should be set accordingly, and for example Odroid U3 has connected the SELB to VDD_IO(LDO3) power line, so actually this state can not be changed or can be changed by accident when changing the VDD_IO - which is HIGH at PMIC's power-up. The switching is impossible, since the VDD_IO line is shared with few other peripherals. In this case, maybe you should add config to allow use of the BUCK234 only for case in which DVS mode is disabled by board design (SELB2/3/4 set to LOW). This may also work, when the GPIOs of Exynos stays in the reset state. Then, using the default 'buck_out' registers: 0x14, 0x1e, 0x28 is reasonable. I don't see anything in the binding. I have added a comment in the driver to explain this limitation. However I haven't actually seen hardware that makes use of it. Are you saying that Odroid U3 does use it, or just that it has the lines connected up incorrectly? Did you tried measure the output voltage, after its change? No I have not measured it, only verified that the code looks correct. If you are able to do that I think it would be a good test. Regards, -- Przemyslaw Marczak Samsung RD Institute Poland Samsung Electronics p.marc...@samsung.com Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] driver model is not smp safe
Hi Simon, When adding x86 multi-cpu initialization on a board with 4 cores, I found: = cpu list 0: cpu@0 Genuine Intel(R) CPU @ 1.58GHz 1: cpu@1 Genuine Intel(R) CPU @ 1.58GHz 2: cpu@2 Genuine Intel(R) CPU @ 1.58GHz 2: cpu@3 Genuine Intel(R) CPU @ 1.58GHz cpu@2 and cpu@3 have the same sequence number, which indicates they are running parallelly to get the same sequence number. The call chain on an ap is: mp_init_cpu() - device_probe() - uclass_resolve_seq(). Apparently ap2 and ap3 are running at the same time to get the same number. Note so far all x86 boards that we have enabled x86 multi-cpu initialization on only have 2 cores, which will not expose such issue as there is no parallel execution among aps. What does this mean? - Driver model is not smp safe. But given U-Boot is a single-threaded environment, I don't think we want to add such support to driver model. OR: - We are using driver model incorrectly on x86 mp initialization codes. What do you think? Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 14/15] RFC: x86: minnowmax: Add interrupt routing setup
Hi Simon,
On Wed, Jul 29, 2015 at 9:08 AM, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Wed, Jul 29, 2015 at 8:48 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 28 July 2015 at 18:46, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Wed, Jul 29, 2015 at 8:42 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 28 July 2015 at 18:40, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Jul 28, 2015 at 7:58 PM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 28 July 2015 at 01:50, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Jul 28, 2015 at 5:47 AM, Simon Glass s...@chromium.org wrote:
At present minnowmax does not correct set up PCI interrupts. This
should be
done in U-Boot so that devices work correctly in Linux.
Note: This code needs to make use of the recent pirq_routing work. It
does
not seem to support all the required features, so this RFC will
hopefully
What features are missing in the existing PIRQ codes? When I did the
PIRQ support, I checked both TunnelCreek and BayTrail chipset
datasheet, and found the only difference seems to be the pci
configuration space vs. memory-mapped IBASE where the pci irq routing
registers reside.
I see that each PCI device can be assigned four routes, making up a
16-bit register. But the code I see in pirq_assign_req() only assigns
a single one, using a byte register.
No, the pci irq routing register is still a 8-bit register on
BayTrail, where pirq_assign_irq() programs. The 16-bit register you
mentioned should be done in the platform codes. See
arch/x86/cpu/queensbay/tnc.c::cpu_irq_init(). By the way actually we
can leave those register programmed as they have the optimized default
values for all pci devices after power up, unless we intentionally
want to change them.
What do you mean by 'leave those register programmed'?
I mean their default value is normally OK, like INTA maps PIRQA, INTB
maps PIRQB, INTC maps PIRQC and INTD maps PIRQD.
OK, so drop writing to the pirq registers?
You might need check if BayTrail FSP does any programming on these
registers. On Intel Crown Bay, I checked those values are the same
values as documented in the TunnelCreek datasheet.
Should I program the 16-bit registers? If so, I will need to extend
the device tree binding, won't I?
When I did the device tree binding changes, I did not convert these
registers to use device tree, because their offsets, not like the
routing registers as programmed in pirq_assign_irq(), is really
platform specific thing and does not seem to have a good formula to
calculate its offset (it varies from platform to platform). I
previously wanted to create some device bindings like below, but I
think they are really ugly so I did not go that way:
irq-router@1f,0 {
reg = 0xf800 0 0 0 0;
compatible = intel,irq-router;
..
dev0-intx-offset = 0x2040;
dev0-intx-value = PIRQA PIRQB PIRQC PIRQD;
dev2-intx-offset = 0x2048;
dev2-intx-value = PIRQA PIRQB PIRQC PIRQD;
dev4-intx-offset = 0x2060;
dev4-intx-value = PIRQA PIRQB PIRQC PIRQD;
dev26-intx-offset = 0x20a0;
dev26-intx-value = PIRQA PIRQB PIRQC PIRQD;
dev31-intx-offset = 0x20c0;
dev31-intx-value = PIRQA PIRQB PIRQC PIRQD;
..
Sorry I cannot find a better way to describe this in device tree, so I
chose to implement directly in the cpu_irq_init() to program these
registers.
Sorry my understanding is limited on this - and I'd like to use your
generic code if possible.
Yes, let's try to use the existing codes. If needed, we can have some
patches to support new platforms.
I just managed to get a BayTrail board (not MinnowMax) and will try to
first port U-Boot (assume it won't take much time) then see how PIRQ
looks like on this platform.
Regards,
Bin
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Re: [U-Boot] Request to host the patman project on kernel.org
Hi Simon, On Wed, Jul 29, 2015 at 6:04 AM, Simon Glass s...@chromium.org wrote: [Otavio and others. please weigh in with your comments] Hi, Patman is a patch management utility which supports Linux and U-Boot development. It is described briefly at [1] and documentation here [2]. name: patman project name: patman project website: none detailed project description: See [1] and [2] reason for wanting us to mirror: It currently resides in the U-Boot tree but it is easier for people to access as its own project than as a part of the U-Boot tree. It might become more accessible and widely as a tool if distros start packaging it. I'd like it to have a mailing list and a git repo. Mailing list aside what about good old github? I guess kernel.org lends a certain pedigree but GitHub is reasonably convenient and provides a few handy services like issue tracking and a web domain. Looks like it's even free to create an opensource organisation on it. Regards, Simon [1] https://lwn.net/Articles/643079/ [2] https://lkml.org/lkml/2015/5/3/95 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mpc85xx/T104xRDB: Remove vbank check redundant code
-Original Message- From: Sun York-R58495 Sent: Tuesday, July 28, 2015 12:37 AM To: Jain Priyanka-B32167; u-boot@lists.denx.de Subject: Re: [PATCH] mpc85xx/T104xRDB: Remove vbank check redundant code On 05/17/2015 11:31 PM, Priyanka Jain wrote: sw variable in checkboard function is storing vbank value which can only take 4-bit value. So check of sw value for if greater than 7 is redundant. Signed-off-by: Priyanka Jain priyanka.j...@freescale.com --- board/freescale/t104xrdb/t104xrdb.c |5 + 1 files changed, 1 insertions(+), 4 deletions(-) diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index 9cd5e15..c34eea6 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -35,10 +35,7 @@ int checkboard(void) sw = CPLD_READ(flash_ctl_status); sw = ((sw CPLD_LBMAP_MASK) CPLD_LBMAP_SHIFT); - if (sw = 7) - printf(vBank: %d\n, sw); - else - printf(Unsupported Bank=%x\n, sw); + printf(vBank: %d\n, sw); return 0; } Priyanka, 4-bit variable can still have value bigger than 7. Is there other reason you want to remove it? [Jain Priyanka-B32167] Sorry, Its 3-bit variable. So cannot have value greater than 7. CPLD_LBMAP_MASK is 0x3f and CPLD_LBMAB_SHIFT is of value 3. So it is basically bits sw[5], sw[4], sw[3]. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] patman: add distutils based installer
On Wed, Jul 29, 2015 at 10:28 AM, Simon Glass s...@chromium.org wrote: Hi Otavio, On 28 July 2015 at 12:06, Otavio Salvador otavio.salva...@ossystems.com.br wrote: On Tue, Jul 28, 2015 at 3:04 PM, Simon Glass s...@chromium.org wrote: On 28 July 2015 at 11:54, Otavio Salvador otavio.salva...@ossystems.com.br wrote: On Tue, Jul 28, 2015 at 2:48 PM, Simon Glass s...@chromium.org wrote: On 28 July 2015 at 11:45, Otavio Salvador otavio.salva...@ossystems.com.br wrote: On Tue, Jul 28, 2015 at 2:39 PM, Simon Glass s...@chromium.org wrote: On 23 July 2015 at 03:36, Chris Packham judge.pack...@gmail.com wrote: It could be treated the same way the git project treats gitk and git-gui. The sources are still included in the main project and distributed along with the rest of it but they are merged from an external upstream where the real development happens. The upstream project is also free to make releases on whatever schedule they determine (although these days there isn't much development going on in for gitk/git-gui). That sounds like a useful model. However there are so few patches to patman - is it worth it? Sure it is; I have asked it in past I think. I would like to have it in Debian, Arch and other linux distros and get more people using it to manage patch series. It is hard to explain it can be used for other project it being inside U-Boot source code. OK so if we do this, what's the best way to get a repo and a mailing list? I would try github or kernel.org if possible. I can't see mailing lists in github. Sure but it has issues and pull requests. Likely what we need. I've sent a request to kernel.org, and copied you. Great :-) It doesn't look like Greg is keen. I'll take a look at github. I should really read all my mail before starting to reply :). GitHub seems appropriate. As you've already identified having a mailing list is one thing missing, but perhaps given the low volume of changes it won't be missed (on a side note that was one of the useful things sourceforge could provide before they went evil). You could even go as far as setting up an organisation for patman (looks like there are a few other patman repositories). ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC] am33xx: add 600us wait in DDR3 initialization sequence
Hi Tom, -Original Message- From: Tom Rini [mailto:tr...@konsulko.com] Sent: Dienstag, 28. Juli 2015 16:42 To: Egli, Samuel Cc: 'double...@ti.com'; 'ba...@ti.com'; 'u-boot@lists.denx.de'; 'h...@denx.de'; 'Stefan Roese'; Meier, Roger; Senn, Joerg; Oleg Belogolov (o-belogo...@ti.com) Subject: Re: [RFC] am33xx: add 600us wait in DDR3 initialization sequence On Tue, Jul 28, 2015 at 02:31:42PM +, Egli, Samuel wrote: Hi all, me again. I was wondering, if somebody of you has time to check these changes? I would appreciate some feedback. Ultimately, it should also go upstream but my focus here is reviewing the content of these changes. Did you have a chance to look into the thing I mentioned in the other thread, about switching to arch/arm/cpu/armv7/arch_timer.c for am33xx? I tried to use arch_timer instead of .../omap-common/timer.c but it was not straight forward. Just enabling CONFIG_SYS_ARCH_TIMER wouldn't do the trick. Because of CONFIG_OMAP_COMMON we have automatically the omap timer built. Disabling CONFIG_OMAP_COMMON, however, breaks the build. So I couldn't go further. And wrt the EMIF changes, I'm hoping James can chime in since he knows that block inside and out :) [...] Thanks, Sam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V3 6/6] T210: Add support for 64-bit T210-based P2571 board
On Tue, Jul 28, 2015 at 01:27:07PM -0600, Stephen Warren wrote: On 07/24/2015 04:01 PM, Tom Warren wrote: Based on Venice2, incorporates Stephen Warren's latest P2571 pinmux table. With Thierry Reding's 64-bit build fixes, this will build and and boot in 64-bit on my P2571 (when used with a 32-bit AVP loader). diff --git a/board/nvidia/p2571/max77620_init.c b/board/nvidia/p2571/max77620_init.c +void pmic_enable_cpu_vdd(void) This function is never called, or even linked into the binary. For previous Tegra SoCs, it was called from the SPL before booting the CCPLEX. Since there is no SPL for Tegra210, nothing calls this. +debug(%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n, __func__); +/* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ +reg = 0xF200 | MAX77620_CNFG1_L2_REG; +tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); +tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); +udelay(10 * 1000); This explains why the SD card isn't working for me on p2371-2180; I guess the PMIC OTP on that board has this regulator disabled, and since this code never runs, it never gets turned on. If I manually turn it on using the i2c command, then mmc dev 1 works. For p2571, I think we should either delete this file entirely. Or, at least strip it down so that it's not touching global PMIC configuration but rather just enabling any non-CCPLEX rails that U-Boot might need such as SD card and USB, then rename the function and arrange for it to be called from somewhere. I'm not sure what a good name and call-site would be yet. Have you looked at my P2371 support patches? Specifically commit ARM: tegra: Add NVIDIA P2371 support has the board-level code that I've used to boot upstream on the device. There's a board_mmc_power_init() implementation which overrides the weak dummy provided in drivers/mmc/mmc.c. Thierry signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC] am33xx: add 600us wait in DDR3 initialization sequence
Hi James,
thank you for your reply!
-Original Message-
From: Doublesin, James [mailto:double...@ti.com]
Sent: Dienstag, 28. Juli 2015 21:59
To: Egli, Samuel; 'tr...@konsulko.com'; Balbi, Felipe
Cc: 'u-boot@lists.denx.de'; 'h...@denx.de'; 'Stefan Roese'; Meier, Roger;
Senn, Joerg; Belogolov, Oleg
Subject: RE: [RFC] am33xx: add 600us wait in DDR3 initialization sequence
Hi Samuel, I don't think these changes are necessary.
I think your concern about the initialization steps is not correct. The
first setting of the REF_CTRL (before SDRAM_CONFIG write) will be used by
the EMIF controller to determine the delay between the rising edge of
DDR_RESETn and DDR_CKE. We typically write a value of 0x3100 in REF_CTRL
to achieve this, which comes from this formula:
(16*SDRAM_REF_CTRL)/400MHz 500us
That's interesting. This isn't really documented in the TRM. But I see
ddr.c:
...
if (regs-zq_config)
writel(0x80003100, emif_reg[nr]-emif_sdram_ref_ctrl);
...
Why does this depend on zq_config? While debugging I saw that we
enter case writing 0x800031000. But the 500us are not waited.
This value will change for different frequencies, but for AM335x and
AM437x, the max freq is 400MHz. When SDRAM_CONFIG is written, the EMIF
controller will kick off a H/W sequence which will configure the memory,
Hmm, I'm confused now. In TRM (rev. L) there nothing written that a write
to SDRAM_CONFIG will trigger the sequence. However, it is written that a
write to SDRAM_REF_CTRL (spec. bits 29,28,26-24) will trigger sequence:
... A write to this field will cause the EMIF to start the SDRAM
initialization sequence. So documentation in TRM is seriously wrong?
and will use this setting for the proper RESET to CKE timing. Once that
is finished, another write to REF_CTRL to set the proper refresh rate will
be necessary.
A separate issue which we have seen does require a delay, however. We
have seen some timeout errors reported on the L3 bus as a result of this
EMIF sequence. This error does not result in any functional problem with
the EMIF initialization, but does result in one of the L3 error flags
being set. We have determined that this is a result of an EMIF access
immediately following the SDRAM_CONFIG write. The EMIF kicks back an
error while the H/W initialization sequence is still active, thus a delay
is required to eliminate this bus error. Again, functionally the EMIF
sequence will work without this delay, but to avoid the error flag, the
delay is needed.
Okay, but the code doesn't wait 1ms at any place. I can only say what
we experienced and measured on our am3352 based boards:
A delay at the end of ddr3 configuration was necessary in order to
make it work with the code how it is implemented now. And yes, the
order of magnitude of waiting was something like 1-2ms. But,
measuring the wait time showed that even with SDRAM_REF_CTRL=0x3100
the delay of 500us was not respected. It was something like ~180us
instead.
I conclude that my changes are not the way to go but some things
need to be changed. However, I'm a bit confused due to the contradictions
of your statements with the TRM.
I was talking with Oleg too and he pointed me to ddr_cofig.gel file
that's used with CCS. In the EMIF config sequence a 1 ms delay is
done too:
...
WR_MEM_32(base_addr + 0x0008, SDRAM_CONFIG);
/* If delay is not present, interconnect can throw a false error */
us_delay(1000);
...
So at least this 1ms delay needs to be added in ddr.c@
void config_sdram(const struct emif_regs *regs, int nr)
{
if (regs-zq_config) {
writel(regs-zq_config, emif_reg[nr]-emif_zq_config);
writel(regs-sdram_config, cstat-secure_emif_sdram_config);
writel(regs-sdram_config, emif_reg[nr]-emif_sdram_config);
writel(regs-ref_ctrl, emif_reg[nr]-emif_sdram_ref_ctrl);
writel(regs-ref_ctrl, emif_reg[nr]-emif_sdram_ref_ctrl_shdw);
}
writel(regs-ref_ctrl, emif_reg[nr]-emif_sdram_ref_ctrl);
writel(regs-ref_ctrl, emif_reg[nr]-emif_sdram_ref_ctrl_shdw);
writel(regs-sdram_config, emif_reg[nr]-emif_sdram_config);
}
But I don't understand why emif_sdram_config, emif_sdram_ref_ctrl and
emif_sdram_ref_ctrl_shdw should be written in if case twice?
Is there a reason for this?
So to summarize, the sequence should be:
-Configure all other EMIF registers
-Write SDRAM_REF_CTRL=0x3100
-Write SDRAM_CONFIG with appropriate value to kick off H/W initialization
of the DDR -wait 1ms (to avoid L3 timeout error) -Write SDRAM_REF_CTRL
with refresh rate value for your DDR
Regards ,
James Doublesin
-Original Message-
From: Egli, Samuel [mailto:samuel.e...@siemens.com]
Sent: Tuesday, July 28, 2015 9:32 AM
To: 'tr...@konsulko.com'; Doublesin, James; Balbi, Felipe
Cc: 'u-boot@lists.denx.de'; 'h...@denx.de'; 'Stefan Roese'; Meier, Roger;
Senn, Joerg; Belogolov, Oleg
Subject: [RFC]
[U-Boot] [PATCH] gitignore: Add defconfig and fdtgrep
Ignore defconfig and tools/fdtgrep. Signed-off-by: Bin Meng bmeng...@gmail.com --- .gitignore | 1 + tools/.gitignore | 1 + 2 files changed, 2 insertions(+) diff --git a/.gitignore b/.gitignore index a40c277..2eac68f 100644 --- a/.gitignore +++ b/.gitignore @@ -48,6 +48,7 @@ /LOG /spl/ /tpl/ +defconfig # # Generated include files diff --git a/tools/.gitignore b/tools/.gitignore index 9bc9fec..9fc231a 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -1,6 +1,7 @@ /atmel_pmecc_params /bmp_logo /envcrc +/fdtgrep /fit_check_sign /fit_info /gen_eth_addr -- 1.8.2.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 02/11] usb: Generic USB Kconfig option, that fits both host and gadget and comments
There is no particular reason why the USB Kconfig option should be specific to host mode. In prevision of adding MUSB host and gadget to Kconfig, this moves the title and help message of the USB Kconfig option to a more generic format. Adding comments to the usb Kconfig allows for a better separation and more readability in generated configs and in menuconfig. Signed-off-by: Paul Kocialkowski cont...@paulk.fr --- drivers/usb/Kconfig | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 89f2137..1addb00 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -1,11 +1,9 @@ # -# USB device configuration +# USB configuration # -menu USB support - -config USB - bool Support for Host-side USB +menuconfig USB + bool USB support ---help--- Universal Serial Bus (USB) is a specification for a serial bus subsystem which offers higher speeds and more features than the @@ -19,8 +17,10 @@ config USB such as scanners, keyboards, mice, modems, cameras, disks, flash memory, network links, and printers to the PC. - Say Y here if your computer has a host-side USB port and you want - to use USB devices. You then need to say Y to at least one of the + Say Y here if your device has an USB port, either host, peripheral or + dual-role. + + For an USB host port, you then need to say Y to at least one of the Host Controller Driver (HCD) options below. Choose a USB 1.1 controller, such as UHCI HCD support or OHCI HCD support, and EHCI HCD (USB 2.0) support except for older systems that @@ -55,6 +55,8 @@ source drivers/usb/host/Kconfig source drivers/usb/emul/Kconfig +comment USB peripherals + config USB_STORAGE bool USB Mass Storage support ---help--- @@ -62,5 +64,3 @@ config USB_STORAGE board's USB port. endif - -endmenu -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 03/11] usb: musb-new: CONFIG_MUSB prefix replacement with CONFIG_USB_MUSB
USB-related options are usually prefixed with CONFIG_USB and platform-specific
adaptation for the MUSB controller already have a CONFIG_USB_MUSB prefix, so
this switches all MUSB-related options to a CONFIG_USB_MUSB prefix, for
consistency.
Signed-off-by: Paul Kocialkowski cont...@paulk.fr
---
arch/arm/cpu/armv7/am33xx/board.c | 2 +-
arch/arm/include/asm/arch-sunxi/usb_phy.h | 2 +-
board/birdland/bav335x/board.c| 2 +-
board/compulab/cm_t3517/cm_t3517.c| 6 +++---
board/logicpd/am3517evm/am3517evm.c | 8
board/phytec/pcm051/board.c | 2 +-
board/siemens/draco/board.c | 2 +-
board/siemens/pxm2/board.c| 2 +-
board/siemens/rut/board.c | 2 +-
board/ti/am335x/board.c | 2 +-
board/ti/beagle/beagle.c | 8
board/vscom/baltos/board.c| 2 +-
drivers/usb/gadget/gadget_chips.h | 2 +-
drivers/usb/musb-new/Makefile | 6 +++---
drivers/usb/musb-new/musb_core.c | 12 ++--
drivers/usb/musb-new/musb_core.h | 4 ++--
drivers/usb/musb-new/musb_dma.h | 2 +-
drivers/usb/musb-new/musb_gadget.c| 4 ++--
drivers/usb/musb-new/musb_uboot.c | 12 ++--
drivers/usb/musb-new/sunxi.c | 6 +++---
drivers/usb/musb/Makefile | 4 ++--
drivers/usb/musb/musb_core.c | 8
drivers/usb/musb/musb_hcd.c | 6 +++---
drivers/usb/musb/musb_hcd.h | 4 ++--
include/configs/am335x_evm.h | 16
include/configs/am3517_crane.h| 14 +++---
include/configs/am3517_evm.h | 16
include/configs/baltos.h | 16
include/configs/bav335x.h | 16
include/configs/bf526-ezbrd.h | 4 ++--
include/configs/bf527-ezkit.h | 4 ++--
include/configs/bf548-ezkit.h | 4 ++--
include/configs/cam_enc_4xx.h | 2 +-
include/configs/cm_t35.h | 2 +-
include/configs/cm_t3517.h| 4 ++--
include/configs/da830evm.h| 10 +-
include/configs/davinci_dm355evm.h| 4 ++--
include/configs/davinci_dm365evm.h| 10 +-
include/configs/davinci_dvevm.h | 4 ++--
include/configs/kwb.h | 10 +-
include/configs/nokia_rx51.h | 4 ++--
include/configs/omap3_beagle.h| 4 ++--
include/configs/omap3_evm.h | 8
include/configs/omap3_evm_common.h| 8
include/configs/omap3_igep00x0.h | 2 +-
include/configs/omap3_mvblx.h | 2 +-
include/configs/omap3_zoom1.h | 2 +-
include/configs/pcm051.h | 12 ++--
include/configs/pengwyn.h | 12 ++--
include/configs/siemens-am33x-common.h| 14 +++---
include/configs/sunxi-common.h| 4 ++--
include/configs/ti_omap4_common.h | 2 +-
include/configs/tseries.h | 10 +-
include/usb.h | 4 ++--
54 files changed, 167 insertions(+), 167 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/board.c
b/arch/arm/cpu/armv7/am33xx/board.c
index 67bef23..377c611 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -124,7 +124,7 @@ int cpu_mmc_init(bd_t *bis)
#endif
/* AM33XX has two MUSB controllers which can be host or gadget */
-#if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) \
+#if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) \
(defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
diff --git a/arch/arm/include/asm/arch-sunxi/usb_phy.h
b/arch/arm/include/asm/arch-sunxi/usb_phy.h
index 17d31b8..cef6c98 100644
--- a/arch/arm/include/asm/arch-sunxi/usb_phy.h
+++ b/arch/arm/include/asm/arch-sunxi/usb_phy.h
@@ -21,7 +21,7 @@ int sunxi_usb_phy_id_detect(int index);
void sunxi_usb_phy_enable_squelch_detect(int index, int enable);
/* Not really phy related, but we have to declare this somewhere ... */
-#if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET)
+#if defined(CONFIG_USB_MUSB_HOST) || defined(CONFIG_USB_MUSB_GADGET)
void sunxi_musb_board_init(void);
#else
#define sunxi_musb_board_init()
diff --git a/board/birdland/bav335x/board.c b/board/birdland/bav335x/board.c
index 32ff7a4..67aca3c 100644
--- a/board/birdland/bav335x/board.c
+++ b/board/birdland/bav335x/board.c
@@ -363,7 +363,7 @@ static struct cpsw_platform_data cpsw_data = {
#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT))
\
defined(CONFIG_SPL_BUILD)) || \
((defined(CONFIG_DRIVER_TI_CPSW) || \
-
[U-Boot] [PATCH v2 04/11] usb: musb-new: Kconfig support for USB_MUSB_HOST and USB_MUSB_GADGET
Having MUSB_HOST and MUSB_GADGET in Kconfig allows more flexibility with regard to what Kconfig options to enable, such as USB_STORAGE or USB_KEYBOARD. Signed-off-by: Paul Kocialkowski cont...@paulk.fr --- drivers/usb/Kconfig | 2 ++ drivers/usb/musb-new/Kconfig | 14 ++ 2 files changed, 16 insertions(+) create mode 100644 drivers/usb/musb-new/Kconfig diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 1addb00..facf145 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -53,6 +53,8 @@ config DM_USB source drivers/usb/host/Kconfig +source drivers/usb/musb-new/Kconfig + source drivers/usb/emul/Kconfig comment USB peripherals diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig new file mode 100644 index 000..34a8474 --- /dev/null +++ b/drivers/usb/musb-new/Kconfig @@ -0,0 +1,14 @@ +# +# MUSB Controller Driver +# +comment MUSB Controller Driver + +config USB_MUSB_HOST + bool MUSB host mode support + help + Enables the MUSB USB dual-role controller in host mode. + +config USB_MUSB_GADGET + bool MUSB gadget mode support + help + Enables the MUSB USB dual-role controller in gadget mode. -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] gpio: UniPhier: add driver for UniPhier GPIO controller
Hi Masahiro,
On 28 July 2015 at 22:15, Masahiro Yamada yamada.masah...@socionext.com wrote:
The previous message was accidentally sent before I finish writing...
If there is a reason why you need different size registers in your
GPIO driver then I think it's fine to implement it that way. But in
general we should use structures IMO.
This hardware has only two registers in each bank. (DIR and DATA)
struct uniphier_gpio_bank {
u32 data;
u32 dir;
};
I could do this, but there is no good reason to do in this driver case.
The I/O access in this driver is already simple enough, i think.
OK I'll leave this up to you.
BTW is the decision to avoid having a driver for each bank is mostly
for memory space/efficiency? I notice that exynos has very much the
same pin numbering as Uniphier and it uses multiple devices.
Regards,
Simon
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[U-Boot] [U-Boot PATCH v2 04/10] ARM: OMAP5: Add support for disabling clocks in uboot
From: Kishon Vijay Abraham I kis...@ti.com
Add do_disable_clocks() to disable clock domains and module clocks.
These clocks are enabled using do_enable_clocks().
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Signed-off-by: Vignesh R vigne...@ti.com
---
arch/arm/cpu/armv7/omap-common/clocks-common.c | 53 ++
arch/arm/include/asm/omap_common.h | 4 ++
2 files changed, 57 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c
b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index c94a80781931..e28b79568d1d 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -648,6 +648,14 @@ static inline void enable_clock_domain(u32 const
clkctrl_reg, u32 enable_mode)
debug(Enable clock domain - %x\n, clkctrl_reg);
}
+static inline void disable_clock_domain(u32 const clkctrl_reg)
+{
+ clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
+ CD_CLKCTRL_CLKTRCTRL_SW_SLEEP
+ CD_CLKCTRL_CLKTRCTRL_SHIFT);
+ debug(Disable clock domain - %x\n, clkctrl_reg);
+}
+
static inline void wait_for_clk_enable(u32 clkctrl_addr)
{
u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
@@ -677,6 +685,34 @@ static inline void enable_clock_module(u32 const
clkctrl_addr, u32 enable_mode,
wait_for_clk_enable(clkctrl_addr);
}
+static inline void wait_for_clk_disable(u32 clkctrl_addr)
+{
+ u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL;
+ u32 bound = LDELAY;
+
+ while ((idlest != MODULE_CLKCTRL_IDLEST_DISABLED)) {
+ clkctrl = readl(clkctrl_addr);
+ idlest = (clkctrl MODULE_CLKCTRL_IDLEST_MASK)
+MODULE_CLKCTRL_IDLEST_SHIFT;
+ if (--bound == 0) {
+ printf(Clock disable failed for 0x%x idlest 0x%x\n,
+ clkctrl_addr, clkctrl);
+ return;
+ }
+ }
+}
+
+static inline void disable_clock_module(u32 const clkctrl_addr,
+ u32 wait_for_disable)
+{
+ clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
+ MODULE_CLKCTRL_MODULEMODE_SW_DISABLE
+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
+ debug(Disable clock module - %x\n, clkctrl_addr);
+ if (wait_for_disable)
+ wait_for_clk_disable(clkctrl_addr);
+}
+
void freq_update_core(void)
{
u32 freq_config1 = 0;
@@ -800,6 +836,23 @@ void do_enable_clocks(u32 const *clk_domains,
}
}
+void do_disable_clocks(u32 const *clk_domains,
+ u32 const *clk_modules_disable,
+ u8 wait_for_disable)
+{
+ u32 i, max = 100;
+
+
+ /* Clock modules that need to be put in SW_DISABLE */
+ for (i = 0; (i max) clk_modules_disable[i]; i++)
+ disable_clock_module(clk_modules_disable[i],
+wait_for_disable);
+
+ /* Put the clock domains in SW_SLEEP mode */
+ for (i = 0; (i max) clk_domains[i]; i++)
+ disable_clock_domain(clk_domains[i]);
+}
+
void prcm_init(void)
{
switch (omap_hw_init_context()) {
diff --git a/arch/arm/include/asm/omap_common.h
b/arch/arm/include/asm/omap_common.h
index 056affc3fabd..87cdaad1d60f 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -575,6 +575,10 @@ void do_enable_clocks(u32 const *clk_domains,
u32 const *clk_modules_explicit_en,
u8 wait_for_enable);
+void do_disable_clocks(u32 const *clk_domains,
+ u32 const *clk_modules_disable,
+ u8 wait_for_disable);
+
void setup_post_dividers(u32 const base,
const struct dpll_params *params);
u32 omap_ddr_clk(void);
--
2.5.0
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[U-Boot] [U-Boot PATCH v2 06/10] ARM: AM43XX: Add functions to enable and disable EDMA3 clocks
Adds functions to enable and disable edma3 clocks which can be invoked
by drivers using edma3 to control the clocks.
Signed-off-by: Vignesh R vigne...@ti.com
---
arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 36
1 file changed, 36 insertions(+)
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index b1c0025eebe8..4a410a21952e 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -134,3 +134,39 @@ void enable_basic_clocks(void)
/* For OPP100 the mac clock should be /5. */
writel(0x4, cmdpll-clkselmacclk);
}
+
+#ifdef CONFIG_TI_EDMA3
+void enable_edma3_clocks(void)
+{
+ u32 *const clk_domains_edma3[] = {
+ 0
+ };
+
+ u32 *const clk_modules_explicit_en_edma3[] = {
+ cmper-tpccclkctrl,
+ cmper-tptc0clkctrl,
+ 0
+ };
+
+ do_enable_clocks(clk_domains_edma3,
+clk_modules_explicit_en_edma3,
+1);
+}
+
+void disable_edma3_clocks(void)
+{
+ u32 *const clk_domains_edma3[] = {
+ 0
+ };
+
+ u32 *const clk_modules_disable_edma3[] = {
+ cmper-tpccclkctrl,
+ cmper-tptc0clkctrl,
+ 0
+ };
+
+ do_disable_clocks(clk_domains_edma3,
+ clk_modules_disable_edma3,
+ 1);
+}
+#endif
--
2.5.0
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[U-Boot] [U-Boot PATCH v2 10/10] ARM: dra7xx_evm: Enable EDMA3 in SPL to support DMA on qspi
Enable TI_EDMA3 and SPL_DMA support, so as to reduce boot time. With DMA enabled there is almost 3x improvement in read performance. This helps in reducing boot time in qspiboot mode Also add EDMA3 base address for DRA7XX and AM57XX. Signed-off-by: Vignesh R vigne...@ti.com --- arch/arm/include/asm/arch-omap5/hardware.h | 5 + include/configs/dra7xx_evm.h | 2 ++ 2 files changed, 7 insertions(+) diff --git a/arch/arm/include/asm/arch-omap5/hardware.h b/arch/arm/include/asm/arch-omap5/hardware.h index f7011b4e904a..a5bd60009289 100644 --- a/arch/arm/include/asm/arch-omap5/hardware.h +++ b/arch/arm/include/asm/arch-omap5/hardware.h @@ -23,4 +23,9 @@ /* GPMC Base address */ #define GPMC_BASE 0x5000 +/* EDMA3 Base address for DRA7XX and AM57XX */ +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) +#define EDMA3_BASE 0x4330 +#endif + #endif diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 74994479e60b..6e32de854619 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -166,6 +166,8 @@ /* SPI SPL */ #define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_DMA_SUPPORT +#define CONFIG_TI_EDMA3 #define CONFIG_SPL_SPI_LOAD #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x4 -- 2.5.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-Boot PATCH v2 08/10] dma: ti-edma3: Add helper function to support edma3 transfer
Signed-off-by: Vignesh R vigne...@ti.com
---
arch/arm/include/asm/ti-common/ti-edma3.h | 2 +
drivers/dma/ti-edma3.c| 78 +++
2 files changed, 80 insertions(+)
diff --git a/arch/arm/include/asm/ti-common/ti-edma3.h
b/arch/arm/include/asm/ti-common/ti-edma3.h
index 5adc1dac0e65..6a7a321c1bdf 100644
--- a/arch/arm/include/asm/ti-common/ti-edma3.h
+++ b/arch/arm/include/asm/ti-common/ti-edma3.h
@@ -117,5 +117,7 @@ void edma3_set_src_addr(u32 base, int slot, u32 src);
void edma3_set_transfer_params(u32 base, int slot, int acnt,
int bcnt, int ccnt, u16 bcnt_rld,
enum edma3_sync_dimension sync_mode);
+void edma3_transfer(unsigned long edma3_base_addr, unsigned int
+ edma_slot_num, void *dst, void *src, size_t len);
#endif
diff --git a/drivers/dma/ti-edma3.c b/drivers/dma/ti-edma3.c
index 8184ded9fa81..d6a427f2e21d 100644
--- a/drivers/dma/ti-edma3.c
+++ b/drivers/dma/ti-edma3.c
@@ -382,3 +382,81 @@ void qedma3_stop(u32 base, struct edma3_channel_config
*cfg)
/* Clear the channel map */
__raw_writel(0, base + EDMA3_QCHMAP(cfg-chnum));
}
+
+void edma3_transfer(unsigned long edma3_base_addr, unsigned int
+ edma_slot_num, void *dst, void *src, size_t len)
+{
+ struct edma3_slot_configslot;
+ struct edma3_channel_config edma_channel;
+ int b_cnt_value = 1;
+ int rem_bytes = 0;
+ int a_cnt_value = len;
+ unsigned intaddr = (unsigned int) (dst);
+ unsigned intmax_acnt = 0x7FFFU;
+
+ if (len max_acnt) {
+ b_cnt_value = (len / max_acnt);
+ rem_bytes = (len % max_acnt);
+ a_cnt_value = max_acnt;
+ }
+
+ slot.opt= 0;
+ slot.src= ((unsigned int) src);
+ slot.acnt = a_cnt_value;
+ slot.bcnt = b_cnt_value;
+ slot.ccnt = 1;
+ slot.src_bidx = a_cnt_value;
+ slot.dst_bidx = a_cnt_value;
+ slot.src_cidx = 0;
+ slot.dst_cidx = 0;
+ slot.link = EDMA3_PARSET_NULL_LINK;
+ slot.bcntrld= 0;
+ slot.opt= EDMA3_SLOPT_TRANS_COMP_INT_ENB |
+ EDMA3_SLOPT_COMP_CODE(0) |
+ EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC;
+
+ edma3_slot_configure(edma3_base_addr, edma_slot_num, slot);
+ edma_channel.slot = edma_slot_num;
+ edma_channel.chnum = 0;
+ edma_channel.complete_code = 0;
+/* set event trigger to dst update */
+ edma_channel.trigger_slot_word = EDMA3_TWORD(dst);
+
+ qedma3_start(edma3_base_addr, edma_channel);
+ edma3_set_dest_addr(edma3_base_addr, edma_channel.slot, addr);
+
+ while (edma3_check_for_transfer(edma3_base_addr, edma_channel))
+ ;
+ qedma3_stop(edma3_base_addr, edma_channel);
+
+ if (rem_bytes != 0) {
+ slot.opt= 0;
+ slot.src=
+ (b_cnt_value * max_acnt) + ((unsigned int) src);
+ slot.acnt = rem_bytes;
+ slot.bcnt = 1;
+ slot.ccnt = 1;
+ slot.src_bidx = rem_bytes;
+ slot.dst_bidx = rem_bytes;
+ slot.src_cidx = 0;
+ slot.dst_cidx = 0;
+ slot.link = EDMA3_PARSET_NULL_LINK;
+ slot.bcntrld= 0;
+ slot.opt= EDMA3_SLOPT_TRANS_COMP_INT_ENB |
+ EDMA3_SLOPT_COMP_CODE(0) |
+ EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC;
+ edma3_slot_configure(edma3_base_addr, edma_slot_num, slot);
+ edma_channel.slot = edma_slot_num;
+ edma_channel.chnum = 0;
+ edma_channel.complete_code = 0;
+ /* set event trigger to dst update */
+ edma_channel.trigger_slot_word = EDMA3_TWORD(dst);
+
+ qedma3_start(edma3_base_addr, edma_channel);
+ edma3_set_dest_addr(edma3_base_addr, edma_channel.slot, addr +
+ (max_acnt * b_cnt_value));
+ while (edma3_check_for_transfer(edma3_base_addr, edma_channel))
+ ;
+ qedma3_stop(edma3_base_addr, edma_channel);
+ }
+}
--
2.5.0
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[U-Boot] [U-Boot PATCH v2 09/10] spi: ti_qspi: Use DMA to read from qspi flash
ti_qspi uses memory map mode for faster read. Enabling DMA will increase
read speed by 3x @48MHz on DRA74 EVM.
Signed-off-by: Vignesh R vigne...@ti.com
---
drivers/spi/ti_qspi.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 3356c0f072e5..753d68980bd6 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -13,6 +13,8 @@
#include spi.h
#include asm/gpio.h
#include asm/omap_gpio.h
+#include asm/omap_common.h
+#include asm/ti-common/ti-edma3.h
/* ti qpsi register bit masks */
#define QSPI_TIMEOUT200
@@ -347,3 +349,24 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
const void *dout,
return 0;
}
+#ifdef CONFIG_TI_EDMA3
+void spi_flash_copy_mmap(void *data, void *offset, size_t len)
+{
+ unsigned intaddr = (unsigned int) (data);
+ unsigned intedma_slot_num = 1;
+
+ /* Invalidate the area, so no writeback into the RAM races with DMA */
+ invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
+
+ /* enable edma3 clocks */
+ enable_edma3_clocks();
+
+ /* Call edma3 api to do actual DMA transfer */
+ edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
+
+ /* disable edma3 clocks */
+ disable_edma3_clocks();
+
+ *((unsigned int *)offset) += len;
+}
+#endif
--
2.5.0
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[U-Boot] [U-Boot PATCH v2 07/10] sf: ops: Add spi_flash_copy_mmap function
From: Tom Rini tr...@ti.com
When doing a memory mapped copy we may have DMA available and thus need
to have this copy abstracted so that the driver can do it, rather than a
simple memcpy.
Signed-off-by: Tom Rini tr...@ti.com
Signed-off-by: Vignesh R vigne...@ti.com
---
drivers/mtd/spi/sf_ops.c | 8 +++-
include/spi.h| 3 +++
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 38592f518b72..900ec1f2a9ce 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -14,6 +14,7 @@
#include spi.h
#include spi_flash.h
#include watchdog.h
+#include linux/compiler.h
#include sf_internal.h
@@ -378,6 +379,11 @@ int spi_flash_read_common(struct spi_flash *flash, const
u8 *cmd,
return ret;
}
+void __weak spi_flash_copy_mmap(void *data, void *offset, size_t len)
+{
+ memcpy(data, offset, len);
+}
+
int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
@@ -394,7 +400,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
return ret;
}
spi_xfer(flash-spi, 0, NULL, NULL, SPI_XFER_MMAP);
- memcpy(data, flash-memory_map + offset, len);
+ spi_flash_copy_mmap(data, flash-memory_map + offset, len);
spi_xfer(flash-spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
spi_release_bus(flash-spi);
return 0;
diff --git a/include/spi.h b/include/spi.h
index 18362364cf0e..51fdfd6d7360 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -272,6 +272,9 @@ int spi_set_wordlen(struct spi_slave *slave, unsigned int
wordlen);
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags);
+/* Copy memory mapped data */
+void spi_flash_copy_mmap(void *data, void *offset, size_t len);
+
/**
* Determine if a SPI chipselect is valid.
* This function is provided by the board if the low-level SPI driver
--
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Re: [U-Boot] [RFC PATCH 1/7] pinctrl: add pinctrl framework
Hi Simon,
2015-07-30 11:06 GMT+09:00 Simon Glass s...@chromium.org:
Hi Masahiro,
On 15 July 2015 at 02:16, Masahiro Yamada yamada.masah...@socionext.com
wrote:
Now, a simple pinctrl patch is being proposed by Simon.
http://patchwork.ozlabs.org/patch/487801/
In the design above, as you see, the uclass is just like a wrapper layer
to invoke .request and .get_periph_id of low-level drivers.
In other words, it is Do-It-Yourself thing, so it is up to you how to
identify
which peripheral is being handled in your .get_periph_id().
And here is one example for how a low-level pinctrl driver could be
implemented.
http://patchwork.ozlabs.org/patch/487874/
I'm sending some comments on this series since I think you are
planning to rework it. My plan is:
- you respin the series
- apply this series
- it should includes the 'simple' version added to the uclass and
perhaps a CONFIG to select whether the full pinctrl is available (can
be separate patches on top of what you have)
- work out what we are going to do about GPIO / pull-ups
OK, I will do it.
Now I am pressed, so hopefully I will have some time this weekend.
Can/does this use exactly the same binding as Linux? Re the limitation
about not detecting conflicts, why is that? It seems that code could
be added for that, even if optional.
I think this series can use the same Generic-conf bindings as used in Linux.
Each driver is still allowed to use its own special bindings.
This version does not support it, but it should not be difficult.
To detect pin conflicts, the framework needs to know
which groups each pin belongs to.
For example, pin 10 is shared between I2C, UART, and SPI,
pin 20 is shared between MMC and NAND, etc.
In other words, low level drivers must have big pin group tables
like they have in Linux.
Most of pinctrl drivers in Linux are over 1000 lines.
I thought it was too much for U-Boot.
To support full features, the pinctrl-uclass would get much bigger.
Of course, we can make it optional with some CONFIG, but I wonder
if it is really needed.
As you see in the thread, honestly, I do not like this approach.
It is true that you can implement .get_periph_id in your driver
better than parsing interrupts properties, but I guess
many drivers would follow the rockchip implmentation because
no helpful infrastructure is provided by the uclass (at least now).
Device trees describe hardwares in a way independent of software
that they are used with. So, identical device trees can be (should be)
used with U-Boot as well as Linux or whatever.
Thus, I want the pinctrl can be controllable by device trees in the same way
of Linux, that is, by parsing pinctrl-names and pinctrl-N properties.
Of course, it would be possible to do it in my own .get_periph_id,
but pinctrl-names and pinctrl-N are too generic to be done in each
low-level driver.
In this series, I'd like to propose to support it in the uclass, so that
we can easily reuse device trees for pinctrl.
Please put it on the table for discussion.
Let me explain how it works.
The basic idea is pretty much like Linux, but it has been much simplified
because full-support of the Linux's pinctrl is too much a burden for a
boot-loader.
Device Tree
---
To use pinctrl from each peripheral, add some properties in the device node.
pinctrl-names is a list of pin states. The default state is mandatory,
and it would probably be enough for U-Boot. But, in order to show how it
works,
say the example device supports two states: default and sleep.
In this case, the properties should be like this.
pinctrl-names = default, sleep;
And then, add as many pinctrl-N properties as the number of states.
pinctrl-0 = phandle to default config node;
pinctrl-1 = phandle to sleep config node;
Here, pinctrl-0, pinctrl-1 corresponds to default, sleep, respectively.
The config nodes are (direct or indirect) children of a pinctrl device.
To sum up, the device tree would be like this:
foo {
compatible = ...;
reg = ...;
pinctrl-names = default, sleep;
pinctrl-0 = foo_default_pin;
pinctrl-1 = foo_sleep_pin;
...
};
pinctrl {
compatible = ...;
reg = ...;
foo_default_pin: foo_default {
groups = ...;
functions = ...;
};
foo_sleep_pin: foo_sleep {
groups = ...;
functions = ...;
};
};
API
---
To set a device into a particular pin state, call
int pinctrl_set_state(struct udevice *dev, const char *state_name).
For example, if you want to set the foo device into the sleep state,
you can do like this:
struct udevice *foo_dev;
(device_get or whatever)
pinctrl_set_state(foo_dev, sleep);
When each device is probed, pinctrl_init() is invoked,
which initializes some pinctrl-specific parameters and set it into default
Re: [U-Boot] [PATCH v2 4/4] usb: lpc32xx: add host USB driver
On Wednesday, July 29, 2015 at 06:14:10 PM, slemieux.t...@gmail.com wrote:
Hi!
From: Sylvain Lemieux slemi...@tycoint.com
Incorporate USB driver from legacy LPCLinux NXP BSP.
The files taken from the legacy patch are:
- lpc32xx USB driver
- lpc3250 header file USB registers definition.
The legacy driver was updated to integrate with the latest u-boot.
Signed-off-by: Sylvain Lemieux slemi...@tycoint.com
---
Changes from v1 to v2:
* Addressed Marek's comments on LPC32xx USB driver:
- use get_timer() to handle timeout.
- Split USB and I2C driver.
* Updated LPC32xx I2C driver to support the I2C that is part
of the USB module.
* Removed ISP1301 USB transceiver I2C registers definition
that are not used.
* Use cpu initialization stop functions API instead of the board API.
[...]
I like this , but please split the change to the i2c driver from the addition
of the USB driver into two separate patches.
unsigned int get_hclk_clk_div(void);
diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c
index 98106fa..be166b0 100644
--- a/drivers/i2c/lpc32xx_i2c.c
+++ b/drivers/i2c/lpc32xx_i2c.c
@@ -1,7 +1,7 @@
/*
* LPC32xx I2C interface driver
*
- * (C) Copyright 2014 DENX Software Engineering GmbH
+ * (C) Copyright 2014-2015 DENX Software Engineering GmbH
* Written-by: Albert ARIBAUD - 3ADEV albert.arib...@3adev.fr
*
* SPDX-License-Identifier: GPL-2.0+
[...]
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 4d35d3e..9dfdc94 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_USB_SL811HS) += sl811-hcd.o
obj-$(CONFIG_USB_OHCI_S3C24XX) += ohci-s3c24xx.o
obj-$(CONFIG_USB_OHCI_EP93XX) += ohci-ep93xx.o
obj-$(CONFIG_USB_OHCI_SUNXI) += ohci-sunxi.o
+obj-$(CONFIG_USB_OHCI_LPC32XX) += ohci-lpc32xx.o
# echi
obj-$(CONFIG_USB_EHCI) += ehci-hcd.o
diff --git a/drivers/usb/host/ohci-lpc32xx.c
b/drivers/usb/host/ohci-lpc32xx.c new file mode 100644
index 000..fb51d42
--- /dev/null
+++ b/drivers/usb/host/ohci-lpc32xx.c
@@ -0,0 +1,245 @@
+/*
+ * Copyright (C) 2008-2015 by NXP Semiconductors
+ * All rights reserved.
+ *
+ * @Author: Based on code by Kevin Wells
+ * @Descr: USB driver - Embedded Artists LPC3250 OEM Board support
functions + *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/cpu.h
+#include asm/arch/clk.h
+#include usb.h
+#include i2c.h
+
+
+/* OTG I2C controller module register structures */
+struct otgi2c_regs {
+ unsigned int otg_i2c_txrx; /* OTG I2C Tx/Rx Data FIFO */
+ unsigned int otg_i2c_stat; /* OTG I2C Status Register */
+ unsigned int otg_i2c_ctrl; /* OTG I2C Control Register */
+ unsigned int otg_i2c_clk_hi; /* OTG I2C Clock Divider high */
+ unsigned int otg_i2c_clk_lo; /* OTG I2C Clock Divider low */
+};
Please replace that unsigned int with u32, here we are certain that
the register is 4-byte big.
+/* OTG controller module register structures */
+struct otg_regs {
+ unsigned int reserved1[64];
+ unsigned int otg_int_sts;/* OTG int status register */
+ unsigned int otg_int_enab; /* OTG int enable register */
+ unsigned int otg_int_set;/* OTG int set register */
+ unsigned int otg_int_clr;/* OTG int clear register */
+ unsigned int otg_sts_ctrl; /* OTG status/control register */
+ unsigned int otg_timer; /* OTG timer register */
+ unsigned int reserved2[122];
+ struct otgi2c_regs otg_i2c;
+ unsigned int reserved3[824];
+ unsigned int otg_clk_ctrl; /* OTG clock control reg */
+ unsigned int otg_clk_sts;/* OTG clock status reg */
+};
+
+/* otg_sts_ctrl register definitions */
+#define OTG_HOST_EN (1 0) /* Enable host mode */
+
+/* otg_clk_ctrl and otg_clk_sts register definitions */
+#define OTG_CLK_AHB_EN (1 4) /* Enable AHB clock */
+#define OTG_CLK_OTG_EN (1 3) /* Enable OTG clock */
+#define OTG_CLK_I2C_EN (1 2) /* Enable I2C clock */
+#define OTG_CLK_HOST_EN (1 0) /* Enable host clock */
+
+/* UART control structure */
+struct uartctrl_regs {
+ unsigned int ctrl; /* General UART control register */
+ unsigned int clkmode; /* UART clock control register */
+ unsigned int loop; /* UART loopmode enable/disable */
+};
Huh? Is this an UART driver now ? :)
+/* UART ctrl register definitions */
+#define UART_U5_ROUTE_TO_USB (1 0)
+
+/* ISP1301 USB transceiver I2C registers */
+#define MC1_SPEED_REG(1 0)
+#define MC1_DAT_SE0 (1 2)
+#define MC1_UART_EN (1 6)
+
+#define MC2_SPD_SUSP_CTRL(1 1)
+#define MC2_BI_DI(1 2)
+#define MC2_PSW_EN (1 6)
+
+#define OTG1_DP_PULLUP
Re: [U-Boot] Pull request: u-boot-tegra/master, 2nd try
On Tue, Jul 28, 2015 at 10:56:22AM -0700, Tom Warren wrote: Tom, Please pull u-boot-tegra/master into U-Boot/master. Thierry's ARM timer patches have been updated. Thanks! ./MAKEALL -s tegra is OK (all 32-bit builds), and ./MAKEALL -a aarch64 is OK (includes p2571) The following changes since commit 26473945ad6667183296e7edee2a65edf31bb6f7: Merge branch 'master' of http://git.denx.de/u-boot-sunxi (2015-07-25 09:04:18 -0400) are available in the git repository at: git://git.denx.de/u-boot-tegra.git master for you to fetch changes up to 873e3ef90ba98c764af6e05251354332205b9d3a: T210: Add support for 64-bit T210-based P2571 board (2015-07-28 10:30:20 -0700) Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH][v2] mpc85xx/T104xRDB: Remove vbank check redundant code
sw variable in checkboard function is storing vbank value which can only take 3-bit value. So check of sw value for if greater than 7 is redundant. Signed-off-by: Priyanka Jain priyanka.j...@freescale.com --- Changes for v2: Corrected description to check is for 3-bit value board/freescale/t104xrdb/t104xrdb.c |5 + 1 files changed, 1 insertions(+), 4 deletions(-) diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index 9cd5e15..c34eea6 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -35,10 +35,7 @@ int checkboard(void) sw = CPLD_READ(flash_ctl_status); sw = ((sw CPLD_LBMAP_MASK) CPLD_LBMAP_SHIFT); - if (sw = 7) - printf(vBank: %d\n, sw); - else - printf(Unsupported Bank=%x\n, sw); + printf(vBank: %d\n, sw); return 0; } -- 1.7.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-Boot PATCH v2 02/10] env: use cache line aligned memory for flash read
From: Ravi Babu ravib...@ti.com
Use memalign() with ARCH_DMA_MINALIGN to allocate read buffers.
This is required because, flash drivers may use DMA for read operations
and may have to invalidate the buffer before read.
Signed-off-by: Ravi Babu ravib...@ti.com
Signed-off-by: Vignesh R vigne...@ti.com
---
common/env_sf.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/common/env_sf.c b/common/env_sf.c
index e928f5752cc7..940983124fbb 100644
--- a/common/env_sf.c
+++ b/common/env_sf.c
@@ -79,7 +79,7 @@ int saveenv(void)
if (CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE) {
saved_size = CONFIG_ENV_SECT_SIZE - CONFIG_ENV_SIZE;
saved_offset = env_new_offset + CONFIG_ENV_SIZE;
- saved_buffer = malloc(saved_size);
+ saved_buffer = memalign(ARCH_DMA_MINALIGN, saved_size);
if (!saved_buffer) {
ret = 1;
goto done;
@@ -142,9 +142,10 @@ void env_relocate_spec(void)
env_t *tmp_env2 = NULL;
env_t *ep = NULL;
- tmp_env1 = (env_t *)malloc(CONFIG_ENV_SIZE);
- tmp_env2 = (env_t *)malloc(CONFIG_ENV_SIZE);
-
+ tmp_env1 = (env_t *)memalign(ARCH_DMA_MINALIGN,
+ CONFIG_ENV_SIZE);
+ tmp_env2 = (env_t *)memalign(ARCH_DMA_MINALIGN,
+ CONFIG_ENV_SIZE);
if (!tmp_env1 || !tmp_env2) {
set_default_env(!malloc() failed);
goto out;
@@ -295,7 +296,7 @@ void env_relocate_spec(void)
int ret;
char *buf = NULL;
- buf = (char *)malloc(CONFIG_ENV_SIZE);
+ buf = (char *)memalign(ARCH_DMA_MINALIGN, CONFIG_ENV_SIZE);
env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
if (!env_flash) {
--
2.5.0
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[U-Boot] [U-Boot PATCH v2 03/10] ARM: AM43xx: Add support for disabling clocks in uboot
From: Kishon Vijay Abraham I kis...@ti.com
Add do_disable_clocks() to disable clock domains and module clocks.
These clocks are enabled using do_enable_clocks().
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Signed-off-by: Vignesh R vigne...@ti.com
---
arch/arm/cpu/armv7/am33xx/clock.c| 52
arch/arm/include/asm/arch-am33xx/clock.h | 1 +
2 files changed, 53 insertions(+)
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c
b/arch/arm/cpu/armv7/am33xx/clock.c
index ec7d46838b74..595c951ed245 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -144,6 +144,33 @@ static inline void enable_clock_module(u32 *const
clkctrl_addr, u32 enable_mode,
wait_for_clk_enable(clkctrl_addr);
}
+static inline void wait_for_clk_disable(u32 *clkctrl_addr)
+{
+ u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL;
+ u32 bound = LDELAY;
+
+ while ((idlest != MODULE_CLKCTRL_IDLEST_DISABLED)) {
+ clkctrl = readl(clkctrl_addr);
+ idlest = (clkctrl MODULE_CLKCTRL_IDLEST_MASK)
+ MODULE_CLKCTRL_IDLEST_SHIFT;
+ if (--bound == 0) {
+ printf(Clock disable failed for 0x%p idlest 0x%x\n,
+ clkctrl_addr, clkctrl);
+return;
+ }
+ }
+}
+static inline void disable_clock_module(u32 *const clkctrl_addr,
+ u32 wait_for_disable)
+{
+ clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
+ MODULE_CLKCTRL_MODULEMODE_SW_DISABLE
+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
+ debug(Disable clock module - %p\n, clkctrl_addr);
+ if (wait_for_disable)
+ wait_for_clk_disable(clkctrl_addr);
+}
+
static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
{
clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
@@ -151,6 +178,14 @@ static inline void enable_clock_domain(u32 *const
clkctrl_reg, u32 enable_mode)
debug(Enable clock domain - %p\n, clkctrl_reg);
}
+static inline void disable_clock_domain(u32 *const clkctrl_reg)
+{
+ clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
+ CD_CLKCTRL_CLKTRCTRL_SW_SLEEP
+ CD_CLKCTRL_CLKTRCTRL_SHIFT);
+ debug(Disable clock domain - %p\n, clkctrl_reg);
+}
+
void do_enable_clocks(u32 *const *clk_domains,
u32 *const *clk_modules_explicit_en, u8 wait_for_enable)
{
@@ -170,6 +205,23 @@ void do_enable_clocks(u32 *const *clk_domains,
};
}
+void do_disable_clocks(u32 *const *clk_domains,
+ u32 *const *clk_modules_disable,
+ u8 wait_for_disable)
+{
+ u32 i, max = 100;
+
+
+ /* Clock modules that need to be put in SW_DISABLE */
+ for (i = 0; (i max) clk_modules_disable[i]; i++)
+ disable_clock_module(clk_modules_disable[i],
+wait_for_disable);
+
+ /* Put the clock domains in SW_SLEEP mode */
+ for (i = 0; (i max) clk_domains[i]; i++)
+ disable_clock_domain(clk_domains[i]);
+}
+
/*
* Before scaling up the clocks we need to have the PMIC scale up the
* voltages first. This will be dependent on which PMIC is in use
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h
b/arch/arm/include/asm/arch-am33xx/clock.h
index 4af6b57e42f5..a6d2419fb843 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -112,5 +112,6 @@ void do_setup_dpll(const struct dpll_regs *, const struct
dpll_params *);
void prcm_init(void);
void enable_basic_clocks(void);
void do_enable_clocks(u32 *const *, u32 *const *, u8);
+void do_disable_clocks(u32 *const *, u32 *const *, u8);
#endif
--
2.5.0
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[U-Boot] [U-Boot PATCH v2 01/10] sf: allocate cache aligned buffers to copy from flash
From: Ravi Babu ravib...@ti.com
Use memalign() with ARCH_DMA_MINALIGN to allocate read buffers.
This is required because, flash drivers may use DMA for read operations
and may have to invalidate the buffer before read.
Signed-off-by: Ravi Babu ravib...@ti.com
Signed-off-by: Vignesh R vigne...@ti.com
---
common/cmd_sf.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index 3746e0d9644f..ac7f5dfb8181 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -223,7 +223,7 @@ static int spi_flash_update(struct spi_flash *flash, u32
offset,
if (end - buf = 200)
scale = (end - buf) / 100;
- cmp_buf = malloc(flash-sector_size);
+ cmp_buf = memalign(ARCH_DMA_MINALIGN, flash-sector_size);
if (cmp_buf) {
ulong last_update = get_timer(0);
@@ -484,12 +484,12 @@ static int do_spi_flash_test(int argc, char * const
argv[])
if (*argv[2] == 0 || *endp != 0)
return -1;
- vbuf = malloc(len);
+ vbuf = memalign(ARCH_DMA_MINALIGN, len);
if (!vbuf) {
printf(Cannot allocate memory (%lu bytes)\n, len);
return 1;
}
- buf = malloc(len);
+ buf = memalign(ARCH_DMA_MINALIGN, len);
if (!buf) {
free(vbuf);
printf(Cannot allocate memory (%lu bytes)\n, len);
--
2.5.0
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[U-Boot] [U-Boot PATCH v2 05/10] ARM: OMAP5: Add functions to enable and disable EDMA3 clocks
Adds functions to enable and disable edma3 clocks which can be invoked
by drivers using edma3 to control the clocks.
Signed-off-by: Vignesh R vigne...@ti.com
---
arch/arm/cpu/armv7/omap5/hw_data.c | 41
arch/arm/cpu/armv7/omap5/prcm-regs.c | 4
arch/arm/include/asm/omap_common.h | 9
3 files changed, 54 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index 3a723cace71a..33f92b7e225d 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -565,6 +565,47 @@ void enable_basic_uboot_clocks(void)
1);
}
+#ifdef CONFIG_TI_EDMA3
+void enable_edma3_clocks(void)
+{
+ u32 const clk_domains_edma3[] = {
+ 0
+ };
+
+ u32 const clk_modules_hw_auto_edma3[] = {
+ (*prcm)-cm_l3main1_tptc1_clkctrl,
+ (*prcm)-cm_l3main1_tptc2_clkctrl,
+ 0
+ };
+
+ u32 const clk_modules_explicit_en_edma3[] = {
+ 0
+ };
+
+ do_enable_clocks(clk_domains_edma3,
+clk_modules_hw_auto_edma3,
+clk_modules_explicit_en_edma3,
+1);
+}
+
+void disable_edma3_clocks(void)
+{
+ u32 const clk_domains_edma3[] = {
+ 0
+ };
+
+ u32 const clk_modules_disable_edma3[] = {
+ (*prcm)-cm_l3main1_tptc1_clkctrl,
+ (*prcm)-cm_l3main1_tptc2_clkctrl,
+ 0
+ };
+
+ do_disable_clocks(clk_domains_edma3,
+ clk_modules_disable_edma3,
+ 1);
+}
+#endif
+
const struct ctrl_ioregs ioregs_omap5430 = {
.ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
.ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c
b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index cd51fe7678be..d01ce88306ee 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -989,4 +989,8 @@ struct prcm_regs const dra7xx_prcm = {
.prm_abbldo_mpu_setup = 0x4AE07DDC,
.prm_abbldo_mpu_ctrl= 0x4AE07DE0,
+
+ /*l3main1 edma*/
+ .cm_l3main1_tptc1_clkctrl = 0x4a008778,
+ .cm_l3main1_tptc2_clkctrl = 0x4a008780,
};
diff --git a/arch/arm/include/asm/omap_common.h
b/arch/arm/include/asm/omap_common.h
index 87cdaad1d60f..3dbe9c53d202 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -349,6 +349,10 @@ struct prcm_regs {
/* IPU */
u32 cm_ipu_clkstctrl;
u32 cm_ipu_i2c5_clkctrl;
+
+ /*l3main1 edma*/
+ u32 cm_l3main1_tptc1_clkctrl;
+ u32 cm_l3main1_tptc2_clkctrl;
};
struct omap_sys_ctrl_regs {
@@ -598,6 +602,11 @@ void recalibrate_iodelay(void);
void omap_smc1(u32 service, u32 val);
+#ifdef CONFIG_TI_EDMA3
+void enable_edma3_clocks(void);
+void disable_edma3_clocks(void);
+#endif
+
/* ABB */
#define OMAP_ABB_NOMINAL_OPP 0
#define OMAP_ABB_FAST_OPP 1
--
2.5.0
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[U-Boot] [U-Boot PATCH v2 00/10] Enable edma support for ti-qspi
This patch series enables DMA for QSPI on dra7xx and am43xx. Patch 1 and 2 make sure the buffers are mem aligned for dma operation. Patch 3-6 add support for enabling and disabling of edma3 clocks on am43xx and dra7xx. Patch 7-9 add dma functionality to ti_qspi driver. Patch 10 enable edma3 support in dra7xx config files. Tested on DRA74 EVM: http://pastebin.ubuntu.com/11813977/ changes in v2: * Move edma related code to edma driver instead of handling it in ti-qspi driver. v1: https://www.mail-archive.com/u-boot@lists.denx.de/msg176479.html Kishon Vijay Abraham I (2): ARM: AM43xx: Add support for disabling clocks in uboot ARM: OMAP5: Add support for disabling clocks in uboot Ravi Babu (2): sf: allocate cache aligned buffers to copy from flash env: use cache line aligned memory for flash read Tom Rini (1): sf: ops: Add spi_flash_copy_mmap function Vignesh R (5): ARM: OMAP5: Add functions to enable and disable EDMA3 clocks ARM: AM43XX: Add functions to enable and disable EDMA3 clocks dma: ti-edma3: Add helper function to support edma3 transfer spi: ti_qspi: Use DMA to read from qspi flash ARM: dra7xx_evm: Enable EDMA3 in SPL to support DMA on qspi arch/arm/cpu/armv7/am33xx/clock.c | 52 + arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 36 arch/arm/cpu/armv7/omap-common/clocks-common.c | 53 + arch/arm/cpu/armv7/omap5/hw_data.c | 41 ++ arch/arm/cpu/armv7/omap5/prcm-regs.c | 4 ++ arch/arm/include/asm/arch-am33xx/clock.h | 1 + arch/arm/include/asm/arch-omap5/hardware.h | 5 ++ arch/arm/include/asm/omap_common.h | 13 + arch/arm/include/asm/ti-common/ti-edma3.h | 2 + common/cmd_sf.c| 6 +- common/env_sf.c| 11 ++-- drivers/dma/ti-edma3.c | 78 ++ drivers/mtd/spi/sf_ops.c | 8 ++- drivers/spi/ti_qspi.c | 23 include/configs/dra7xx_evm.h | 2 + include/spi.h | 3 + 16 files changed, 329 insertions(+), 9 deletions(-) -- 2.5.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 00/11] USB and sunxi Kconfig and config changes leading up to fastboot support
Hi, On 29-07-15 15:32, Paul Kocialkowski wrote: This series is based off the following patch: * drivers: hierarchize drivers Kconfig menu that was sent to the list earlier. Please pick it up as well when merging this series. The entire series looks good to me: Acked-by: Hans de Goede hdego...@redhat.com Marek, since this consists of mostly generic USB chaages I think it would be best for you to pick up this entire series. Regards, Hans ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] x86: baytrail: Configure FSP UPD from device tree
Hi Andrew, Simon,
On Wed, Jul 22, 2015 at 4:17 AM, Simon Glass s...@chromium.org wrote:
Hi Andrew,
On 10 July 2015 at 12:24, Andrew Bradford and...@bradfordembedded.com wrote:
Hi Simon,
On 07/10 06:53, Simon Glass wrote:
Hi,
On 8 July 2015 at 05:30, Andrew Bradford and...@bradfordembedded.com
wrote:
Hi Bin,
On 07/08 11:18, Bin Meng wrote:
Hi Andrew,
On Wed, Jul 8, 2015 at 3:16 AM, and...@bradfordembedded.com wrote:
From: Andrew Bradford andrew.bradf...@kodakalaris.com
Allow for configuration of FSP UPD from the device tree which will
override any settings which the FSP was built with itself if the device
tree settings exist, otherwise simply trust the FSP's defaults.
Modifies the MinnowMax board to transfer the FSP UPD hard-coded
settings
to the MinnowMax dts.
Signed-off-by: Andrew Bradford andrew.bradf...@kodakalaris.com
---
Changes from v1:
- Use - rather than _ in dt property names.
- Use Bay Trail for the formal name of the Intel product family.
- Use an fsp, prefix for dt property names for clarity.
- Fix minor code indentation issues.
- Create a dt subnode for the memory-down-params.
- Clarify documentation that dt overrides the FSP's config, so we don't
use booleans.
arch/x86/cpu/baytrail/fsp_configs.c| 188
+
arch/x86/dts/minnowmax.dts | 30
.../misc/intel,baytrail-fsp.txt| 119 +
include/fdtdec.h | 2 +
lib/fdtdec.c | 2 +
5 files changed, 311 insertions(+), 30 deletions(-)
create mode 100644
doc/device-tree-bindings/misc/intel,baytrail-fsp.txt
diff --git a/arch/x86/cpu/baytrail/fsp_configs.c
b/arch/x86/cpu/baytrail/fsp_configs.c
index 86b6926..fce76e6 100644
--- a/arch/x86/cpu/baytrail/fsp_configs.c
+++ b/arch/x86/cpu/baytrail/fsp_configs.c
@@ -1,14 +1,18 @@
/*
* Copyright (C) 2013, Intel Corporation
* Copyright (C) 2014, Bin Meng bmeng...@gmail.com
+ * Copyright (C) 2015, Kodak Alaris, Inc
*
* SPDX-License-Identifier:Intel
*/
#include common.h
+#include fdtdec.h
#include asm/arch/fsp/azalia.h
#include asm/fsp/fsp_support.h
+DECLARE_GLOBAL_DATA_PTR;
+
/* ALC262 Verb Table - 10EC0262 */
static const uint32_t verb_table_data13[] = {
/* Pin Complex (NID 0x11) */
@@ -116,41 +120,165 @@ const struct pch_azalia_config azalia_config = {
.reset_wait_timer_us = 300
};
+/**
+ * Update the FSP's UPD. The FSP itself can be configured for
defaults to
+ * store in UPD through Intel's GUI configurator but likely a
specific board
+ * will want to update these from u-boot, so allow for that via
device tree.
+ * If the device tree does not specify a setting, trust the FSP's
default.
+ */
void update_fsp_upd(struct upd_region *fsp_upd)
{
struct memory_down_data *mem;
+ const void *blob = gd-fdt_blob;
+ int node;
- /*
-* Configure everything here to avoid the poor hard-pressed
user
-* needing to run Intel's binary configuration tool. It may
also allow
-* us to support the 1GB single core variant easily.
-*
-* TODO(s...@chromium.org): Move to device tree
-*/
- fsp_upd-mrc_init_tseg_size = 8;
- fsp_upd-mrc_init_mmio_size = 0x800;
- fsp_upd-emmc_boot_mode = 0xff;
- fsp_upd-enable_sdio = 1;
- fsp_upd-enable_sdcard = 1;
- fsp_upd-enable_hsuart0 = 1;
fsp_upd-azalia_config_ptr = (uint32_t)azalia_config;
- fsp_upd-enable_i2_c0 = 0;
- fsp_upd-enable_i2_c2 = 0;
- fsp_upd-enable_i2_c3 = 0;
- fsp_upd-enable_i2_c4 = 0;
- fsp_upd-enable_xhci = 0;
- fsp_upd-igd_render_standby = 1;
+
+ node = fdtdec_next_compatible(blob, 0,
COMPAT_INTEL_BAYTRAIL_FSP);
+ if (node 0) {
+ debug(%s: Cannot find FSP node\n, __func__);
+ return;
+ }
+
+ fsp_upd-mrc_init_tseg_size = fdtdec_get_int(blob, node,
+
fsp,mrc-int-tseg-size,
mrc-int? Guess it is mrc-init.
Yes, thank you for catching this. Will fix in v3.
+
fsp_upd-mrc_init_tseg_size);
+ fsp_upd-mrc_init_mmio_size = fdtdec_get_int(blob, node,
+
fsp,mrc-init-mmio-size,
+
fsp_upd-mrc_init_mmio_size);
+ fsp_upd-mrc_init_spd_addr1 = fdtdec_get_int(blob, node,
+
fsp,mrc-init-spd-addr1,
+
[U-Boot] [PATCH v2 01/11] usb: USB_ARCH_HAS_HCD Kconfig option removal
The USB_ARCH_HAS_HCD currently serves no purpose and adds some confusion to the required Kconfig options that are required to have USB support. Dropping it makes things easier and doesn't break anything, since it was unused anyways. Signed-off-by: Paul Kocialkowski cont...@paulk.fr --- drivers/usb/Kconfig | 4 1 file changed, 4 deletions(-) diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 19b1b3d..89f2137 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -4,12 +4,8 @@ menu USB support -config USB_ARCH_HAS_HCD - def_bool y - config USB bool Support for Host-side USB - depends on USB_ARCH_HAS_HCD ---help--- Universal Serial Bus (USB) is a specification for a serial bus subsystem which offers higher speeds and more features than the -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 00/11] USB and sunxi Kconfig and config changes leading up to fastboot support
This series is based off the following patch: * drivers: hierarchize drivers Kconfig menu that was sent to the list earlier. Please pick it up as well when merging this series. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 06/11] usb: USB_HCD Kconfig option for host controllers
This introduces a (hidden) USB_HCD Kconfig option that is selected when an USB host controller is enabled. This will allow for selecting other options when such a controller is enabled. Signed-off-by: Paul Kocialkowski cont...@paulk.fr --- drivers/usb/Kconfig | 3 +++ drivers/usb/host/Kconfig | 2 ++ drivers/usb/musb-new/Kconfig | 1 + 3 files changed, 6 insertions(+) diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index facf145..4e9335f 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -51,6 +51,9 @@ config DM_USB declared with the U_BOOT_USB_DEVICE() macro and will be automatically probed when found on the bus. +config USB_HCD + bool + source drivers/usb/host/Kconfig source drivers/usb/musb-new/Kconfig diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 8705c7c..052def7 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -5,6 +5,7 @@ comment USB Host Controller Drivers config USB_XHCI_HCD bool xHCI HCD (USB 3.0) support + select USB_HCD ---help--- The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0 SuperSpeed host controller hardware. @@ -28,6 +29,7 @@ endif config USB_EHCI_HCD bool EHCI HCD (USB 2.0) support + select USB_HCD ---help--- The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0 high speed (480 Mbit/sec, 60 Mbyte/sec) host controller hardware. diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig index 0082ff8..3c680f7 100644 --- a/drivers/usb/musb-new/Kconfig +++ b/drivers/usb/musb-new/Kconfig @@ -5,6 +5,7 @@ comment MUSB Controller Driver config USB_MUSB_HOST bool MUSB host mode support + select USB_HCD help Enables the MUSB USB dual-role controller in host mode. -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 10/11] sunxi: MUSB gadget config provisions, with fastboot and USB mass storage support
This adds some config options to the sunxi-common config to enable the USB download gadget and the fastboot and USB mass storage functions. Signed-off-by: Paul Kocialkowski cont...@paulk.fr --- include/configs/sunxi-common.h | 30 ++ 1 file changed, 30 insertions(+) diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 7ed208c..edcacd5 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -329,6 +329,36 @@ extern int soft_i2c_gpio_scl; #define CONFIG_USB_MUSB_PIO_ONLY #endif +#ifdef CONFIG_USB_MUSB_GADGET +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW0 + +#define CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_USB_FUNCTION_FASTBOOT +#define CONFIG_USB_FUNCTION_MASS_STORAGE +#endif + +#ifdef CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_G_DNL_VENDOR_NUM0x1f3a +#define CONFIG_G_DNL_PRODUCT_NUM 0x1010 +#define CONFIG_G_DNL_MANUFACTURER Allwinner Technology +#endif + +#ifdef CONFIG_USB_FUNCTION_FASTBOOT +#define CONFIG_CMD_FASTBOOT +#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_FASTBOOT_BUF_SIZE 0x200 + +#define CONFIG_FASTBOOT_FLASH +#define CONFIG_FASTBOOT_FLASH_MMC_DEV 0 +#define CONFIG_EFI_PARTITION +#endif + +#ifdef CONFIG_USB_FUNCTION_MASS_STORAGE +#define CONFIG_CMD_USB_MASS_STORAGE +#endif + #ifdef CONFIG_USB_KEYBOARD #define CONFIG_CONSOLE_MUX #define CONFIG_PREBOOT -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 11/11] usb: USB storage-specific part ifdef in uclass
usb_stor_reset is only defined when USB storage support is enabled, thus the function is not declared when such support is missing. Signed-off-by: Paul Kocialkowski cont...@paulk.fr --- drivers/usb/host/usb-uclass.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c index c5d1e7f..b17a7d7 100644 --- a/drivers/usb/host/usb-uclass.c +++ b/drivers/usb/host/usb-uclass.c @@ -173,7 +173,9 @@ int usb_stop(void) uclass_foreach_dev(dev, uc) usb_emul_reset(dev); #endif +#ifdef CONFIG_USB_STORAGE usb_stor_reset(); +#endif usb_hub_reset(); uc_priv-companion_device_count = 0; usb_started = 0; -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 09/11] musb: sunxi: Force EP0 on re-enable
From: Maxime Ripard maxime.rip...@free-electrons.com Currently, the second use of a gadget will fail, while the first one works. Forcing the EP0 at every enable fix this issue. Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com --- drivers/usb/musb-new/sunxi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index 85ac28d..16a264a 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -200,6 +200,9 @@ static int sunxi_musb_enable(struct musb *musb) pr_debug(%s():\n, __func__); + musb_ep_select(musb-mregs, 0); + musb_writeb(musb-mregs, MUSB_FADDR, 0); + if (enabled) return 0; -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 05/11] sunxi: usb: USB_MUSB_SUNXI move to musb-new Kconfig
Now that the musb-new driver has a Kconfig, we can move Kconfig options to enable controllers to it, so that it's easier in e.g. menuconfig. In addition, this allows declaring support for USB_MUSB_HOST/GADGET in defconfigs instead of the USB_MUSB_SUNXI controller, that will get selected automatically when needed. Signed-off-by: Paul Kocialkowski cont...@paulk.fr --- board/sunxi/Kconfig | 9 - configs/Ainol_AW1_defconfig | 2 +- configs/Ampe_A76_defconfig | 2 +- configs/CSQ_CS908_defconfig | 2 +- configs/Chuwi_V7_CW0825_defconfig| 2 +- configs/Et_q8_v1_6_defconfig | 2 +- configs/Hyundai_A7HD_defconfig | 2 +- configs/Ippo_q8h_v1_2_a33_1024x600_defconfig | 2 +- configs/Ippo_q8h_v1_2_defconfig | 2 +- configs/Ippo_q8h_v5_defconfig| 2 +- configs/MSI_Primo81_defconfig| 2 +- configs/Mele_A1000G_quad_defconfig | 2 +- configs/Mini-X_defconfig | 2 +- configs/TZX-Q8-713B7_defconfig | 2 +- configs/UTOO_P66_defconfig | 2 +- configs/Yones_Toptech_BD1078_defconfig | 2 +- configs/ba10_tv_box_defconfig| 2 +- configs/forfun_q88db_defconfig | 2 +- configs/ga10h_v1_1_defconfig | 2 +- configs/iNet_3F_defconfig| 2 +- configs/iNet_3W_defconfig| 2 +- configs/iNet_86VS_defconfig | 2 +- drivers/usb/musb-new/Kconfig | 14 ++ 23 files changed, 35 insertions(+), 30 deletions(-) diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 441c880..e1c5e1d 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -539,15 +539,6 @@ config VIDEO_LCD_TL059WV5C0 endchoice -config USB_MUSB_SUNXI - bool Enable sunxi OTG / DRC USB controller in host mode - default n - ---help--- - Say y here to enable support for the sunxi OTG / DRC USB controller - used on almost all sunxi boards. Note currently u-boot can only have - one usb host controller enabled at a time, so enabling this on boards - which also use the ehci host controller will result in build errors. - config USB_KEYBOARD boolean Enable USB keyboard support default y diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig index e1262e6..ff7abfa 100644 --- a/configs/Ainol_AW1_defconfig +++ b/configs/Ainol_AW1_defconfig @@ -11,7 +11,7 @@ CONFIG_VIDEO_LCD_MODE=x:800,y:480,depth:18,pclk_khz:4,le:87,ri:112,up:38,lo CONFIG_VIDEO_LCD_POWER=PH8 CONFIG_VIDEO_LCD_BL_EN=PH7 CONFIG_VIDEO_LCD_BL_PWM=PB2 -CONFIG_USB_MUSB_SUNXI=y +CONFIG_USB_MUSB_HOST=y CONFIG_DEFAULT_DEVICE_TREE=sun7i-a20-ainol-aw1 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig index 2ee0307..1d36919 100644 --- a/configs/Ampe_A76_defconfig +++ b/configs/Ampe_A76_defconfig @@ -10,7 +10,7 @@ CONFIG_VIDEO_LCD_MODE=x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:82,up:22,lo: CONFIG_VIDEO_LCD_POWER=AXP0-0 CONFIG_VIDEO_LCD_BL_EN=AXP0-1 CONFIG_VIDEO_LCD_BL_PWM=PB2 -CONFIG_USB_MUSB_SUNXI=y +CONFIG_USB_MUSB_HOST=y CONFIG_DEFAULT_DEVICE_TREE=sun5i-a13-ampe-a76 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig index fe88a7b..7c8eca8 100644 --- a/configs/CSQ_CS908_defconfig +++ b/configs/CSQ_CS908_defconfig @@ -15,4 +15,4 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_AXP221_DLDO1_VOLT=3300 CONFIG_AXP221_ALDO1_VOLT=3300 CONFIG_USB_EHCI_HCD=y -CONFIG_USB_MUSB_SUNXI=y +CONFIG_USB_MUSB_HOST=y diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig index cb659c9..4011351 100644 --- a/configs/Chuwi_V7_CW0825_defconfig +++ b/configs/Chuwi_V7_CW0825_defconfig @@ -10,7 +10,7 @@ CONFIG_VIDEO_LCD_POWER=PH8 CONFIG_VIDEO_LCD_BL_EN=PH7 CONFIG_VIDEO_LCD_BL_PWM=PB2 CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y -CONFIG_USB_MUSB_SUNXI=y +CONFIG_USB_MUSB_HOST=y CONFIG_DEFAULT_DEVICE_TREE=sun4i-a10-chuwi-v7-cw0825 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y diff --git a/configs/Et_q8_v1_6_defconfig b/configs/Et_q8_v1_6_defconfig index 27833471..ca8db19 100644 --- a/configs/Et_q8_v1_6_defconfig +++ b/configs/Et_q8_v1_6_defconfig @@ -11,7 +11,7 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER=PH7 CONFIG_VIDEO_LCD_BL_EN=PH6 CONFIG_VIDEO_LCD_BL_PWM=PH0 -CONFIG_USB_MUSB_SUNXI=y +CONFIG_USB_MUSB_HOST=y CONFIG_DEFAULT_DEVICE_TREE=sun8i-a33-et-q8-v1.6 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig index 06fdd2a..065a3f9 100644 --- a/configs/Hyundai_A7HD_defconfig +++ b/configs/Hyundai_A7HD_defconfig @@ -12,7 +12,7 @@ CONFIG_VIDEO_LCD_BL_EN=PH9 CONFIG_VIDEO_LCD_BL_PWM=PB2 #
[U-Boot] [PATCH v2 07/11] usb: USB_KEYBOARD move to usb Kconfig and USB peripherals support on USB_HCD
The USB_KEYBOARD Kconfig is not specific to sunxi, so we can move it to the common USB Kconfig. In addition, USB_KEYBOARD and USB_STORAGE should be enabled when an USB host controller is enabled. Signed-off-by: Paul Kocialkowski cont...@paulk.fr --- arch/arm/Kconfig| 1 - board/sunxi/Kconfig | 8 drivers/usb/Kconfig | 12 3 files changed, 12 insertions(+), 9 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 36aa4e9..41f517d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -653,7 +653,6 @@ config ARCH_SUNXI select OF_SEPARATE select SPL_DISABLE_OF_CONTROL select USB - select USB_STORAGE config TARGET_SNOWBALL bool Support snowball diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index e1c5e1d..b156701 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -538,14 +538,6 @@ config VIDEO_LCD_TL059WV5C0 endchoice - -config USB_KEYBOARD - boolean Enable USB keyboard support - default y - ---help--- - Say Y here to add support for using a USB keyboard (typically used - in combination with a graphical console). - config GMAC_TX_DELAY int GMAC Transmit Clock Delay Chain default 0 diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 4e9335f..4e1f2fb 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -60,12 +60,24 @@ source drivers/usb/musb-new/Kconfig source drivers/usb/emul/Kconfig +if USB_HCD + comment USB peripherals config USB_STORAGE bool USB Mass Storage support + default y ---help--- Say Y here if you want to connect USB mass storage devices to your board's USB port. +config USB_KEYBOARD + boolean Enable USB keyboard support + default y + ---help--- + Say Y here to add support for using a USB keyboard (typically used + in combination with a graphical console). + +endif + endif -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 08/11] sunxi: config update to stick with Kconfig changes
Now that some things were updated in Kconfig, they should be reflected on the sunxi-common config too. Signed-off-by: Paul Kocialkowski cont...@paulk.fr --- include/configs/sunxi-common.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index c002342..7ed208c 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -318,7 +318,7 @@ extern int soft_i2c_gpio_scl; #define CONFIG_PHYLIB #endif -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #define CONFIG_USB_OHCI_NEW #define CONFIG_USB_OHCI_SUNXI #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 @@ -326,7 +326,6 @@ extern int soft_i2c_gpio_scl; #endif #ifdef CONFIG_USB_MUSB_SUNXI -#define CONFIG_USB_MUSB_HOST #define CONFIG_USB_MUSB_PIO_ONLY #endif @@ -379,7 +378,7 @@ extern int soft_i2c_gpio_scl; #define BOOT_TARGET_DEVICES_SCSI(func) #endif -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_STORAGE #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) #else #define BOOT_TARGET_DEVICES_USB(func) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] x86: baytrail: Configure FSP UPD from device tree
Hi Bin,
On 29 July 2015 at 08:08, Bin Meng bmeng...@gmail.com wrote:
Hi Andrew, Simon,
On Wed, Jul 22, 2015 at 4:17 AM, Simon Glass s...@chromium.org wrote:
Hi Andrew,
On 10 July 2015 at 12:24, Andrew Bradford and...@bradfordembedded.com
wrote:
Hi Simon,
On 07/10 06:53, Simon Glass wrote:
Hi,
On 8 July 2015 at 05:30, Andrew Bradford and...@bradfordembedded.com
wrote:
Hi Bin,
On 07/08 11:18, Bin Meng wrote:
Hi Andrew,
On Wed, Jul 8, 2015 at 3:16 AM, and...@bradfordembedded.com wrote:
From: Andrew Bradford andrew.bradf...@kodakalaris.com
Allow for configuration of FSP UPD from the device tree which will
override any settings which the FSP was built with itself if the
device
tree settings exist, otherwise simply trust the FSP's defaults.
Modifies the MinnowMax board to transfer the FSP UPD hard-coded
settings
to the MinnowMax dts.
Signed-off-by: Andrew Bradford andrew.bradf...@kodakalaris.com
---
Changes from v1:
- Use - rather than _ in dt property names.
- Use Bay Trail for the formal name of the Intel product family.
- Use an fsp, prefix for dt property names for clarity.
- Fix minor code indentation issues.
- Create a dt subnode for the memory-down-params.
- Clarify documentation that dt overrides the FSP's config, so we
don't
use booleans.
arch/x86/cpu/baytrail/fsp_configs.c| 188
+
arch/x86/dts/minnowmax.dts | 30
.../misc/intel,baytrail-fsp.txt| 119
+
include/fdtdec.h | 2 +
lib/fdtdec.c | 2 +
5 files changed, 311 insertions(+), 30 deletions(-)
create mode 100644
doc/device-tree-bindings/misc/intel,baytrail-fsp.txt
diff --git a/arch/x86/cpu/baytrail/fsp_configs.c
b/arch/x86/cpu/baytrail/fsp_configs.c
index 86b6926..fce76e6 100644
--- a/arch/x86/cpu/baytrail/fsp_configs.c
+++ b/arch/x86/cpu/baytrail/fsp_configs.c
@@ -1,14 +1,18 @@
/*
* Copyright (C) 2013, Intel Corporation
* Copyright (C) 2014, Bin Meng bmeng...@gmail.com
+ * Copyright (C) 2015, Kodak Alaris, Inc
*
* SPDX-License-Identifier:Intel
*/
#include common.h
+#include fdtdec.h
#include asm/arch/fsp/azalia.h
#include asm/fsp/fsp_support.h
+DECLARE_GLOBAL_DATA_PTR;
+
/* ALC262 Verb Table - 10EC0262 */
static const uint32_t verb_table_data13[] = {
/* Pin Complex (NID 0x11) */
@@ -116,41 +120,165 @@ const struct pch_azalia_config azalia_config =
{
.reset_wait_timer_us = 300
};
+/**
+ * Update the FSP's UPD. The FSP itself can be configured for
defaults to
+ * store in UPD through Intel's GUI configurator but likely a
specific board
+ * will want to update these from u-boot, so allow for that via
device tree.
+ * If the device tree does not specify a setting, trust the FSP's
default.
+ */
void update_fsp_upd(struct upd_region *fsp_upd)
{
struct memory_down_data *mem;
+ const void *blob = gd-fdt_blob;
+ int node;
- /*
-* Configure everything here to avoid the poor hard-pressed
user
-* needing to run Intel's binary configuration tool. It may
also allow
-* us to support the 1GB single core variant easily.
-*
-* TODO(s...@chromium.org): Move to device tree
-*/
- fsp_upd-mrc_init_tseg_size = 8;
- fsp_upd-mrc_init_mmio_size = 0x800;
- fsp_upd-emmc_boot_mode = 0xff;
- fsp_upd-enable_sdio = 1;
- fsp_upd-enable_sdcard = 1;
- fsp_upd-enable_hsuart0 = 1;
fsp_upd-azalia_config_ptr = (uint32_t)azalia_config;
- fsp_upd-enable_i2_c0 = 0;
- fsp_upd-enable_i2_c2 = 0;
- fsp_upd-enable_i2_c3 = 0;
- fsp_upd-enable_i2_c4 = 0;
- fsp_upd-enable_xhci = 0;
- fsp_upd-igd_render_standby = 1;
+
+ node = fdtdec_next_compatible(blob, 0,
COMPAT_INTEL_BAYTRAIL_FSP);
+ if (node 0) {
+ debug(%s: Cannot find FSP node\n, __func__);
+ return;
+ }
+
+ fsp_upd-mrc_init_tseg_size = fdtdec_get_int(blob, node,
+
fsp,mrc-int-tseg-size,
mrc-int? Guess it is mrc-init.
Yes, thank you for catching this. Will fix in v3.
+
fsp_upd-mrc_init_tseg_size);
+ fsp_upd-mrc_init_mmio_size = fdtdec_get_int(blob, node,
+
fsp,mrc-init-mmio-size,
+
fsp_upd-mrc_init_mmio_size);
+ fsp_upd-mrc_init_spd_addr1 = fdtdec_get_int(blob, node,
+
