[U-Boot] [PATCH 1/2] clk: add static qualifier to local functions
Signed-off-by: Masahiro Yamada
---
drivers/clk/clk_rk3036.c | 2 +-
drivers/clk/clk_rk3288.c | 2 +-
drivers/clk/clk_sandbox.c | 5 +++--
3 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/clk_rk3036.c b/drivers/clk/clk_rk3036.c
index 6c802b6..f650810 100644
--- a/drivers/clk/clk_rk3036.c
+++ b/drivers/clk/clk_rk3036.c
@@ -314,7 +314,7 @@ static ulong rk3036_clk_set_rate(struct udevice *dev, ulong
rate)
return 0;
}
-ulong rk3036_set_periph_rate(struct udevice *dev, int periph, ulong rate)
+static ulong rk3036_set_periph_rate(struct udevice *dev, int periph, ulong
rate)
{
struct rk3036_clk_priv *priv = dev_get_priv(dev);
ulong new_rate;
diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c
index 54d4930..0172ad1 100644
--- a/drivers/clk/clk_rk3288.c
+++ b/drivers/clk/clk_rk3288.c
@@ -508,7 +508,7 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru,
uint clk_general_rate,
return rockchip_spi_get_clk(cru, clk_general_rate, periph);
}
-ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong rate)
+static ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong
rate)
{
struct rk3288_clk_priv *priv = dev_get_priv(dev);
ulong new_rate;
diff --git a/drivers/clk/clk_sandbox.c b/drivers/clk/clk_sandbox.c
index 058225a..367130f 100644
--- a/drivers/clk/clk_sandbox.c
+++ b/drivers/clk/clk_sandbox.c
@@ -32,7 +32,7 @@ static ulong sandbox_clk_set_rate(struct udevice *dev, ulong
rate)
return 0;
}
-ulong sandbox_get_periph_rate(struct udevice *dev, int periph)
+static ulong sandbox_get_periph_rate(struct udevice *dev, int periph)
{
struct sandbox_clk_priv *priv = dev_get_priv(dev);
@@ -41,7 +41,8 @@ ulong sandbox_get_periph_rate(struct udevice *dev, int periph)
return priv->periph_rate[periph];
}
-ulong sandbox_set_periph_rate(struct udevice *dev, int periph, ulong rate)
+static ulong sandbox_set_periph_rate(struct udevice *dev, int periph,
+ulong rate)
{
struct sandbox_clk_priv *priv = dev_get_priv(dev);
ulong old_rate;
--
1.9.1
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[U-Boot] [PATCH 2/2] clk: change the type of return value to long
The comments in include/clk.h state "or -ve error code" for these
functions, and actually the functions return negative error code
here and there. Returning unsigned value is not suitable.
Signed-off-by: Masahiro Yamada
---
drivers/clk/clk-uclass.c | 8
drivers/clk/clk_rk3036.c | 6 +++---
drivers/clk/clk_rk3288.c | 6 +++---
drivers/clk/clk_sandbox.c | 9 -
include/clk.h | 16
5 files changed, 22 insertions(+), 23 deletions(-)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 73dfd7d..a5bef59 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -12,7 +12,7 @@
#include
#include
-ulong clk_get_rate(struct udevice *dev)
+long clk_get_rate(struct udevice *dev)
{
struct clk_ops *ops = clk_get_ops(dev);
@@ -22,7 +22,7 @@ ulong clk_get_rate(struct udevice *dev)
return ops->get_rate(dev);
}
-ulong clk_set_rate(struct udevice *dev, ulong rate)
+long clk_set_rate(struct udevice *dev, ulong rate)
{
struct clk_ops *ops = clk_get_ops(dev);
@@ -32,7 +32,7 @@ ulong clk_set_rate(struct udevice *dev, ulong rate)
return ops->set_rate(dev, rate);
}
-ulong clk_get_periph_rate(struct udevice *dev, int periph)
+long clk_get_periph_rate(struct udevice *dev, int periph)
{
struct clk_ops *ops = clk_get_ops(dev);
@@ -42,7 +42,7 @@ ulong clk_get_periph_rate(struct udevice *dev, int periph)
return ops->get_periph_rate(dev, periph);
}
-ulong clk_set_periph_rate(struct udevice *dev, int periph, ulong rate)
+long clk_set_periph_rate(struct udevice *dev, int periph, ulong rate)
{
struct clk_ops *ops = clk_get_ops(dev);
diff --git a/drivers/clk/clk_rk3036.c b/drivers/clk/clk_rk3036.c
index f650810..8613123 100644
--- a/drivers/clk/clk_rk3036.c
+++ b/drivers/clk/clk_rk3036.c
@@ -298,7 +298,7 @@ static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru,
uint clk_general_rate,
return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
}
-static ulong rk3036_clk_get_rate(struct udevice *dev)
+static long rk3036_clk_get_rate(struct udevice *dev)
{
struct rk3036_clk_plat *plat = dev_get_platdata(dev);
struct rk3036_clk_priv *priv = dev_get_priv(dev);
@@ -307,14 +307,14 @@ static ulong rk3036_clk_get_rate(struct udevice *dev)
return rkclk_pll_get_rate(priv->cru, plat->clk_id);
}
-static ulong rk3036_clk_set_rate(struct udevice *dev, ulong rate)
+static long rk3036_clk_set_rate(struct udevice *dev, ulong rate)
{
debug("%s\n", dev->name);
return 0;
}
-static ulong rk3036_set_periph_rate(struct udevice *dev, int periph, ulong
rate)
+static long rk3036_set_periph_rate(struct udevice *dev, int periph, ulong rate)
{
struct rk3036_clk_priv *priv = dev_get_priv(dev);
ulong new_rate;
diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c
index 0172ad1..8ed0bff 100644
--- a/drivers/clk/clk_rk3288.c
+++ b/drivers/clk/clk_rk3288.c
@@ -337,7 +337,7 @@ static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
}
}
-static ulong rk3288_clk_get_rate(struct udevice *dev)
+static long rk3288_clk_get_rate(struct udevice *dev)
{
struct rk3288_clk_plat *plat = dev_get_platdata(dev);
struct rk3288_clk_priv *priv = dev_get_priv(dev);
@@ -346,7 +346,7 @@ static ulong rk3288_clk_get_rate(struct udevice *dev)
return rkclk_pll_get_rate(priv->cru, plat->clk_id);
}
-static ulong rk3288_clk_set_rate(struct udevice *dev, ulong rate)
+static long rk3288_clk_set_rate(struct udevice *dev, ulong rate)
{
struct rk3288_clk_plat *plat = dev_get_platdata(dev);
struct rk3288_clk_priv *priv = dev_get_priv(dev);
@@ -508,7 +508,7 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru,
uint clk_general_rate,
return rockchip_spi_get_clk(cru, clk_general_rate, periph);
}
-static ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong
rate)
+static long rk3288_set_periph_rate(struct udevice *dev, int periph, ulong rate)
{
struct rk3288_clk_priv *priv = dev_get_priv(dev);
ulong new_rate;
diff --git a/drivers/clk/clk_sandbox.c b/drivers/clk/clk_sandbox.c
index 367130f..0ff4605 100644
--- a/drivers/clk/clk_sandbox.c
+++ b/drivers/clk/clk_sandbox.c
@@ -15,14 +15,14 @@ struct sandbox_clk_priv {
ulong periph_rate[PERIPH_ID_COUNT];
};
-static ulong sandbox_clk_get_rate(struct udevice *dev)
+static long sandbox_clk_get_rate(struct udevice *dev)
{
struct sandbox_clk_priv *priv = dev_get_priv(dev);
return priv->rate;
}
-static ulong sandbox_clk_set_rate(struct udevice *dev, ulong rate)
+static long sandbox_clk_set_rate(struct udevice *dev, ulong rate)
{
struct sandbox_clk_priv *priv = dev_get_priv(dev);
@@ -32,7 +32,7 @@ static ulong sandbox_clk_set_rate(struct udevice *dev, ulong
rate)
return 0;
}
-static ulong sandbox_get_periph_rate(struct udevice *dev, int periph)
+static l
[U-Boot] [PATCH] clk: move Kconfig options into sub-menu
Signed-off-by: Masahiro Yamada --- drivers/clk/Kconfig | 4 1 file changed, 4 insertions(+) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 890f22f..9fcde39 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -1,3 +1,5 @@ +menu "Clock" + config CLK bool "Enable clock driver support" depends on DM @@ -17,3 +19,5 @@ config SPL_CLK SPL, enable this option. It might provide a cleaner interface to setting up clocks within SPL, and allows the same drivers to be used as U-Boot proper. + +endmenu -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/8] Convert lpuart serial driver to driver model
Hi Bhuvanchandra, On Tue, Jan 12, 2016 at 2:43 PM, Bhuvanchandra DV wrote: > Hi Bin, > > > On 01/12/2016 11:05 AM, Bin Meng wrote: >> >> Hi Bhuvanchandra, >> >> On Tue, Jan 12, 2016 at 12:28 PM, Bhuvanchandra DV >> wrote: >>> >>> - Convert lpuart driver to driver model and remove the legacy code. >>> - Update Toradex Colibri VF50/VF61 serial support with driver model. >>> - Update Freescale vf610twr serial support with driver model. >>> - Update Freescale ls1021atwr serial support with driver model. >>> - Update Phytec pcm052 serial support with driver model. >>> - Tested the driver on Toradex Colibri VF50/VF61 hardware. >>> - Compile checked board files for vf610twr, ls1021atwr and pcm052 >>>since I don't have access to such hardware at my end. Reviewers >>>and testers welcome! >>> >>> Bhuvanchandra DV (8): >>>dm: lpuart: Add driver model support for the serial driver >>>colibri_vf: Update enabling lpuart support with driver model >>>arm: vf610twr: Add driver model support >>>vf610twr: Update enabling lpuart with driver model >>>arm: ls102xa: Add driver model support >>>ls1021x: Update enabling lpuart with driver model >>>arm: pcm052: Enable driver model support >>>pcm052: Update enabling lpuart support with driver model >>> >>> arch/arm/include/asm/arch-ls102xa/serial.h | 16 >>> arch/arm/include/asm/arch-vf610/serial.h | 16 >>> board/freescale/ls1021atwr/ls1021atwr.c| 15 ++- >>> board/freescale/vf610twr/vf610twr.c| 13 +++ >>> board/phytec/pcm052/pcm052.c | 13 +++ >>> board/toradex/colibri_vf/colibri_vf.c | 13 +++ >>> configs/ls1021atwr_nor_lpuart_defconfig| 1 + >>> configs/pcm052_defconfig | 1 + >>> configs/vf610twr_defconfig | 1 + >>> configs/vf610twr_nand_defconfig| 1 + >>> drivers/serial/Kconfig | 6 ++ >>> drivers/serial/serial_lpuart.c | 148 >>> +++-- >>> include/configs/colibri_vf.h | 6 +- >>> include/configs/ls1021atwr.h | 1 + >>> include/configs/pcm052.h | 6 +- >>> include/configs/vf610twr.h | 6 +- >>> 16 files changed, 180 insertions(+), 83 deletions(-) >>> create mode 100644 arch/arm/include/asm/arch-ls102xa/serial.h >>> create mode 100644 arch/arm/include/asm/arch-vf610/serial.h >>> >>> -- >> >> >> Please see existing patch series @ >> http://patchwork.ozlabs.org/patch/561855/. You can drop the ls102xa >> changes and rebase your patch series on top of that. Thanks! > > > We are not aware of this patch set, sorry! about that. You want me to drop > only the ls102xa changes? How about the changes/updates to the lpuart > driver? should i update them with your device tree support stuff and rebase > the remaining patch set along with your Signed-off-by tag ? > Any suggestions ? > I believe you can: - Drop the LPUART DM conversion patch in your series, which was already done - Drop the ls1021atwr changes, which was already done - Do the similar changes to all other boards in your series, by following ls1021atwr changes in my series - There is no need to add my SOB tag in your series as I was actually not doing anything :) Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/5] power: axp818: Remove duplicate register definition macros
Some of the register definitions are duplicated. Drop them. Signed-off-by: Chen-Yu Tsai --- include/axp818.h | 8 1 file changed, 8 deletions(-) diff --git a/include/axp818.h b/include/axp818.h index 1dc6456..46d05ad 100644 --- a/include/axp818.h +++ b/include/axp818.h @@ -32,13 +32,6 @@ #define AXP818_OUTPUT_CTRL3_ALDO2_EN (1 << 6) #define AXP818_OUTPUT_CTRL3_ALDO3_EN (1 << 7) -#define AXP818_DCDC1_CTRL 0x20 -#define AXP818_DCDC2_CTRL 0x21 -#define AXP818_DCDC3_CTRL 0x22 -#define AXP818_DCDC4_CTRL 0x23 -#define AXP818_DCDC5_CTRL 0x24 -#define AXP818_DCDC6_CTRL 0x25 - #define AXP818_DLDO1_CTRL 0x15 #define AXP818_DLDO2_CTRL 0x16 #define AXP818_DLDO3_CTRL 0x17 @@ -46,7 +39,6 @@ #define AXP818_ELDO1_CTRL 0x19 #define AXP818_ELDO2_CTRL 0x1a #define AXP818_ELDO3_CTRL 0x1b -#define AXP818_ELDO3_CTRL 0x1b #define AXP818_FLDO1_CTRL 0x1c #define AXP818_FLDO2_3_CTRL0x1d #define AXP818_DCDC1_CTRL 0x20 -- 2.6.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/5] sunxi: power: axp818: Enable support for ALDOs
Previously, AXP818 ALDO support was partially added to Kconfig, but
never enabled in the board file, nor properly set or configured in
Kconfig. The boards continue to work because the AXP818 is designed
to pair with the A83T/H8, and the default voltages match the reference
design's requirements.
Signed-off-by: Chen-Yu Tsai
---
board/sunxi/board.c| 8 +++-
drivers/power/Kconfig | 13 ++---
drivers/power/axp818.c | 37 +
3 files changed, 50 insertions(+), 8 deletions(-)
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 85f01fd..e0ff650 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -446,20 +446,18 @@ void sunxi_board_init(void)
power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
#endif
-#ifdef CONFIG_AXP221_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
#endif
-#ifndef CONFIG_AXP818_POWER
power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
-#endif
-#if !defined(CONFIG_AXP152_POWER) && !defined(CONFIG_AXP818_POWER)
+#if !defined(CONFIG_AXP152_POWER)
power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
#endif
#ifdef CONFIG_AXP209_POWER
power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
#endif
-#ifdef CONFIG_AXP221_POWER
+#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP818_POWER)
power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 6f61763..e91a5c0 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -118,20 +118,24 @@ config AXP_DCDC5_VOLT
config AXP_ALDO1_VOLT
int "axp pmic (a)ldo1 voltage"
- depends on AXP221_POWER
+ depends on AXP221_POWER || AXP818_POWER
default 0 if MACH_SUN6I
+ default 1800 if MACH_SUN8I_A83T
default 3000 if MACH_SUN8I
---help---
Set the voltage (mV) to program the axp pmic aldo1 at, set to 0 to
disable aldo1.
On A31 boards aldo1 is often used to power the wifi module.
On A23 / A33 boards aldo1 is used for VCC-IO and should be 3.0V.
+ On A83T / H8 boards aldo1 is used for MIPI CSI, DSI, HDMI, EFUSE, and
+ should be 1.8V.
config AXP_ALDO2_VOLT
int "axp pmic (a)ldo2 voltage"
depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP818_POWER
default 3000 if AXP152_POWER || AXP209_POWER
default 0 if MACH_SUN6I
+ default 1800 if MACH_SUN8I_A83T
default 2500 if MACH_SUN8I
---help---
Set the voltage (mV) to program the axp pmic aldo2 at, set to 0 to
@@ -140,18 +144,21 @@ config AXP_ALDO2_VOLT
On A31 boards aldo2 is typically unused and should be disabled.
On A31 boards aldo2 may be used for LPDDR2 then it should be 1.8V.
On A23 / A33 boards aldo2 is used for VDD-DLL and should be 2.5V.
+ On A83T / H8 boards aldo2 powers VDD-DLL, VCC18-PLL, CPVDD, VDD18-ADC,
+ LPDDR2, and the codec. It should be 1.8V.
config AXP_ALDO3_VOLT
int "axp pmic (a)ldo3 voltage"
depends on AXP209_POWER || AXP221_POWER || AXP818_POWER
- default 0 if AXP209_POWER || AXP818_POWER
+ default 0 if AXP209_POWER
default 3000 if MACH_SUN6I || MACH_SUN8I
---help---
Set the voltage (mV) to program the axp pmic aldo3 at, set to 0 to
disable aldo3.
On A10(s) / A13 / A20 boards aldo3 should be 2.8V.
On A23 / A31 / A33 boards aldo3 is VCC-PLL and AVCC and should be 3.0V.
- On A83T aldo3 is used for LVDS, DSI, MIPI, HDMI, etc.
+ On A83T / H8 boards aldo3 is AVCC, VCC-PL, and VCC-LED, and should be
+ 3.0V.
config AXP_ALDO4_VOLT
int "axp pmic (a)ldo4 voltage"
diff --git a/drivers/power/axp818.c b/drivers/power/axp818.c
index 3119b64..e885d02 100644
--- a/drivers/power/axp818.c
+++ b/drivers/power/axp818.c
@@ -110,6 +110,43 @@ int axp_set_dcdc5(unsigned int mvolt)
AXP818_OUTPUT_CTRL1_DCDC5_EN);
}
+int axp_set_aldo(int aldo_num, unsigned int mvolt)
+{
+ int ret;
+ u8 cfg;
+
+ if (aldo_num < 1 || aldo_num > 3)
+ return -EINVAL;
+
+ if (mvolt == 0)
+ return pmic_bus_clrbits(AXP818_OUTPUT_CTRL3,
+ AXP818_OUTPUT_CTRL3_ALDO1_EN << (aldo_num - 1));
+
+ cfg = axp818_mvolt_to_cfg(mvolt, 700, 3300, 100);
+ ret = pmic_bus_write(AXP818_ALDO1_CTRL + (aldo_num - 1), cfg);
+ if (ret)
+ return ret;
+
+ return pmic_bus_setbits(AXP818_OUTPUT_CTRL3,
+ AXP818_OUTPUT_CTRL3_ALDO1_EN << (aldo_num - 1));
+}
+
+/* TODO: re-work other AXP drivers to consolidate ALDO functions. */
+int axp_set_aldo1(unsigned int mvolt)
+{
+ return axp_set_al
[U-Boot] [PATCH 2/5] power: axp: merge separate DLDO functions into 1
Instead of one function for each DLDO regulator, make 1 function that
takes an extra "index". Since the control bits for the DLDO regulators
are contiguous, this makes the function very simple. This removes a lot
of duplicate code.
Signed-off-by: Chen-Yu Tsai
---
board/sunxi/board.c| 8 ++---
drivers/power/axp221.c | 88 --
include/axp_pmic.h | 5 +--
3 files changed, 25 insertions(+), 76 deletions(-)
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 386e2e0..85f01fd 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -460,10 +460,10 @@ void sunxi_board_init(void)
#endif
#ifdef CONFIG_AXP221_POWER
- power_failed |= axp_set_dldo1(CONFIG_AXP_DLDO1_VOLT);
- power_failed |= axp_set_dldo2(CONFIG_AXP_DLDO2_VOLT);
- power_failed |= axp_set_dldo3(CONFIG_AXP_DLDO3_VOLT);
- power_failed |= axp_set_dldo4(CONFIG_AXP_DLDO4_VOLT);
+ power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
+ power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
+ power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
+ power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
diff --git a/drivers/power/axp221.c b/drivers/power/axp221.c
index 65802e4..e0cbf79 100644
--- a/drivers/power/axp221.c
+++ b/drivers/power/axp221.c
@@ -115,74 +115,6 @@ int axp_set_dcdc5(unsigned int mvolt)
AXP221_OUTPUT_CTRL1_DCDC5_EN);
}
-int axp_set_dldo1(unsigned int mvolt)
-{
- int ret;
- u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
-
- if (mvolt == 0)
- return pmic_bus_clrbits(AXP221_OUTPUT_CTRL2,
- AXP221_OUTPUT_CTRL2_DLDO1_EN);
-
- ret = pmic_bus_write(AXP221_DLDO1_CTRL, cfg);
- if (ret)
- return ret;
-
- return pmic_bus_setbits(AXP221_OUTPUT_CTRL2,
- AXP221_OUTPUT_CTRL2_DLDO1_EN);
-}
-
-int axp_set_dldo2(unsigned int mvolt)
-{
- int ret;
- u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
-
- if (mvolt == 0)
- return pmic_bus_clrbits(AXP221_OUTPUT_CTRL2,
- AXP221_OUTPUT_CTRL2_DLDO2_EN);
-
- ret = pmic_bus_write(AXP221_DLDO2_CTRL, cfg);
- if (ret)
- return ret;
-
- return pmic_bus_setbits(AXP221_OUTPUT_CTRL2,
- AXP221_OUTPUT_CTRL2_DLDO2_EN);
-}
-
-int axp_set_dldo3(unsigned int mvolt)
-{
- int ret;
- u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
-
- if (mvolt == 0)
- return pmic_bus_clrbits(AXP221_OUTPUT_CTRL2,
- AXP221_OUTPUT_CTRL2_DLDO3_EN);
-
- ret = pmic_bus_write(AXP221_DLDO3_CTRL, cfg);
- if (ret)
- return ret;
-
- return pmic_bus_setbits(AXP221_OUTPUT_CTRL2,
- AXP221_OUTPUT_CTRL2_DLDO3_EN);
-}
-
-int axp_set_dldo4(unsigned int mvolt)
-{
- int ret;
- u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
-
- if (mvolt == 0)
- return pmic_bus_clrbits(AXP221_OUTPUT_CTRL2,
- AXP221_OUTPUT_CTRL2_DLDO4_EN);
-
- ret = pmic_bus_write(AXP221_DLDO4_CTRL, cfg);
- if (ret)
- return ret;
-
- return pmic_bus_setbits(AXP221_OUTPUT_CTRL2,
- AXP221_OUTPUT_CTRL2_DLDO4_EN);
-}
-
int axp_set_aldo1(unsigned int mvolt)
{
int ret;
@@ -234,6 +166,26 @@ int axp_set_aldo3(unsigned int mvolt)
AXP221_OUTPUT_CTRL3_ALDO3_EN);
}
+int axp_set_dldo(int dldo_num, unsigned int mvolt)
+{
+ u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
+ int ret;
+
+ if (dldo_num < 1 || dldo_num > 4)
+ return -EINVAL;
+
+ if (mvolt == 0)
+ return pmic_bus_clrbits(AXP221_OUTPUT_CTRL2,
+ AXP221_OUTPUT_CTRL2_DLDO1_EN << (dldo_num - 1));
+
+ ret = pmic_bus_write(AXP221_DLDO1_CTRL + (dldo_num - 1), cfg);
+ if (ret)
+ return ret;
+
+ return pmic_bus_setbits(AXP221_OUTPUT_CTRL2,
+ AXP221_OUTPUT_CTRL2_DLDO1_EN << (dldo_num - 1));
+}
+
int axp_set_eldo(int eldo_num, unsigned int mvolt)
{
int ret;
diff --git a/include/axp_pmic.h b/include/axp_pmic.h
index 3b01c49..0f14683 100644
--- a/include/axp_pmic.h
+++ b/include/axp_pmic.h
@@ -29,10 +29,7 @@ int axp_set_aldo1(unsigned int mvolt);
int axp_set_aldo2(unsigned int mvolt);
int axp_set_aldo3(unsigned int mvolt);
int axp_set_aldo4(unsigned int mvolt);
-int axp_set_dldo1(unsigned int mvolt);
-int axp_set_dldo2(unsigned int mvolt);
-int axp_set_dldo3(unsigned int mvolt);
-i
[U-Boot] [PATCH 3/5] power: axp818: Add support for DLDO and ELDO regulators
AXP818 provides an array of LDOs to provide power to various peripherals.
None of these regulators are critical.
Signed-off-by: Chen-Yu Tsai
---
drivers/power/Kconfig | 12 ++--
drivers/power/axp818.c | 44
2 files changed, 50 insertions(+), 6 deletions(-)
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index e86dd72..6f61763 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -164,7 +164,7 @@ config AXP_ALDO4_VOLT
config AXP_DLDO1_VOLT
int "axp pmic dldo1 voltage"
- depends on AXP221_POWER
+ depends on AXP221_POWER || AXP818_POWER
default 0
---help---
Set the voltage (mV) to program the axp pmic dldo1 at, set to 0 to
@@ -174,7 +174,7 @@ config AXP_DLDO1_VOLT
config AXP_DLDO2_VOLT
int "axp pmic dldo2 voltage"
- depends on AXP221_POWER
+ depends on AXP221_POWER || AXP818_POWER
default 0
---help---
Set the voltage (mV) to program the axp pmic dldo2 at, set to 0 to
@@ -182,7 +182,7 @@ config AXP_DLDO2_VOLT
config AXP_DLDO3_VOLT
int "axp pmic dldo3 voltage"
- depends on AXP221_POWER
+ depends on AXP221_POWER || AXP818_POWER
default 0
---help---
Set the voltage (mV) to program the axp pmic dldo3 at, set to 0 to
@@ -198,7 +198,7 @@ config AXP_DLDO4_VOLT
config AXP_ELDO1_VOLT
int "axp pmic eldo1 voltage"
- depends on AXP221_POWER
+ depends on AXP221_POWER || AXP818_POWER
default 0
---help---
Set the voltage (mV) to program the axp pmic eldo1 at, set to 0 to
@@ -206,7 +206,7 @@ config AXP_ELDO1_VOLT
config AXP_ELDO2_VOLT
int "axp pmic eldo2 voltage"
- depends on AXP221_POWER
+ depends on AXP221_POWER || AXP818_POWER
default 0
---help---
Set the voltage (mV) to program the axp pmic eldo2 at, set to 0 to
@@ -214,7 +214,7 @@ config AXP_ELDO2_VOLT
config AXP_ELDO3_VOLT
int "axp pmic eldo3 voltage"
- depends on AXP221_POWER
+ depends on AXP221_POWER || AXP818_POWER
default 0
---help---
Set the voltage (mV) to program the axp pmic eldo3 at, set to 0 to
diff --git a/drivers/power/axp818.c b/drivers/power/axp818.c
index 4b21a83..3119b64 100644
--- a/drivers/power/axp818.c
+++ b/drivers/power/axp818.c
@@ -110,6 +110,50 @@ int axp_set_dcdc5(unsigned int mvolt)
AXP818_OUTPUT_CTRL1_DCDC5_EN);
}
+int axp_set_dldo(int dldo_num, unsigned int mvolt)
+{
+ int ret;
+ u8 cfg;
+
+ if (dldo_num < 1 || dldo_num > 4)
+ return -EINVAL;
+
+ if (mvolt == 0)
+ return pmic_bus_clrbits(AXP818_OUTPUT_CTRL2,
+ AXP818_OUTPUT_CTRL2_DLDO1_EN << (dldo_num - 1));
+
+ cfg = axp818_mvolt_to_cfg(mvolt, 700, 3300, 100);
+ if (dldo_num == 2 && mvolt > 3300)
+ cfg += 1 + axp818_mvolt_to_cfg(mvolt, 3400, 4200, 200);
+ ret = pmic_bus_write(AXP818_ELDO1_CTRL + (dldo_num - 1), cfg);
+ if (ret)
+ return ret;
+
+ return pmic_bus_setbits(AXP818_OUTPUT_CTRL2,
+ AXP818_OUTPUT_CTRL2_DLDO1_EN << (dldo_num - 1));
+}
+
+int axp_set_eldo(int eldo_num, unsigned int mvolt)
+{
+ int ret;
+ u8 cfg;
+
+ if (eldo_num < 1 || eldo_num > 3)
+ return -EINVAL;
+
+ if (mvolt == 0)
+ return pmic_bus_clrbits(AXP818_OUTPUT_CTRL2,
+ AXP818_OUTPUT_CTRL2_ELDO1_EN << (eldo_num - 1));
+
+ cfg = axp818_mvolt_to_cfg(mvolt, 700, 1900, 50);
+ ret = pmic_bus_write(AXP818_ELDO1_CTRL + (eldo_num - 1), cfg);
+ if (ret)
+ return ret;
+
+ return pmic_bus_setbits(AXP818_OUTPUT_CTRL2,
+ AXP818_OUTPUT_CTRL2_ELDO1_EN << (eldo_num - 1));
+}
+
int axp_init(void)
{
u8 axp_chip_id;
--
2.6.4
___
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U-Boot@lists.denx.de
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[U-Boot] [PATCH 4/5] sunxi: h8_homlet_v2: Drop LDO settings from defconfig
The LDO settings in this defconfig are either wrong (ALDOs must not be 0) or the same as Kconfig defaults. Signed-off-by: Chen-Yu Tsai --- configs/h8_homlet_v2_defconfig | 3 --- 1 file changed, 3 deletions(-) diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig index dc2809a..ecd04a6 100644 --- a/configs/h8_homlet_v2_defconfig +++ b/configs/h8_homlet_v2_defconfig @@ -19,6 +19,3 @@ CONFIG_AXP_DCDC2_VOLT=900 CONFIG_AXP_DCDC3_VOLT=900 CONFIG_AXP_DCDC4_VOLT=0 CONFIG_AXP_DCDC5_VOLT=1500 -CONFIG_AXP_ALDO2_VOLT=0 -CONFIG_AXP_ALDO3_VOLT=0 -CONFIG_AXP_DLDO4_VOLT=0 -- 2.6.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/5] sunxi: power: axp818: Support ALDO/DLDO/ELDOs
Hi everyone, This series adds proper support for ALDO/DLDO/ELDOs on AXP818. FLDOs aren't covered yet, though the hardware defaults should work nicely with sane hardware. ALDO functions aren't consolidated or cleaned up either. Patch 1 cleans up the axp818 header. Patch 2 merges the separate axp221 dldo functions into 1. Patch 3 adds support for axp818's dldos and eldos. Patch 4 drops the LDO voltages from h8_homlet_v2_defconfig. These match the defaults. Patch 5 adds support for axp818's aldos. Regards ChenYu Chen-Yu Tsai (5): power: axp818: Remove duplicate register definition macros power: axp: merge separate DLDO functions into 1 power: axp818: Add support for DLDO and ELDO regulators sunxi: h8_homlet_v2: Drop LDO settings from defconfig sunxi: power: axp818: Enable support for ALDOs board/sunxi/board.c| 16 configs/h8_homlet_v2_defconfig | 3 -- drivers/power/Kconfig | 25 +++- drivers/power/axp221.c | 88 ++ drivers/power/axp818.c | 81 ++ include/axp818.h | 8 include/axp_pmic.h | 5 +-- 7 files changed, 125 insertions(+), 101 deletions(-) -- 2.6.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/8] Convert lpuart serial driver to driver model
Hi Bin, On 01/12/2016 11:05 AM, Bin Meng wrote: Hi Bhuvanchandra, On Tue, Jan 12, 2016 at 12:28 PM, Bhuvanchandra DV wrote: - Convert lpuart driver to driver model and remove the legacy code. - Update Toradex Colibri VF50/VF61 serial support with driver model. - Update Freescale vf610twr serial support with driver model. - Update Freescale ls1021atwr serial support with driver model. - Update Phytec pcm052 serial support with driver model. - Tested the driver on Toradex Colibri VF50/VF61 hardware. - Compile checked board files for vf610twr, ls1021atwr and pcm052 since I don't have access to such hardware at my end. Reviewers and testers welcome! Bhuvanchandra DV (8): dm: lpuart: Add driver model support for the serial driver colibri_vf: Update enabling lpuart support with driver model arm: vf610twr: Add driver model support vf610twr: Update enabling lpuart with driver model arm: ls102xa: Add driver model support ls1021x: Update enabling lpuart with driver model arm: pcm052: Enable driver model support pcm052: Update enabling lpuart support with driver model arch/arm/include/asm/arch-ls102xa/serial.h | 16 arch/arm/include/asm/arch-vf610/serial.h | 16 board/freescale/ls1021atwr/ls1021atwr.c| 15 ++- board/freescale/vf610twr/vf610twr.c| 13 +++ board/phytec/pcm052/pcm052.c | 13 +++ board/toradex/colibri_vf/colibri_vf.c | 13 +++ configs/ls1021atwr_nor_lpuart_defconfig| 1 + configs/pcm052_defconfig | 1 + configs/vf610twr_defconfig | 1 + configs/vf610twr_nand_defconfig| 1 + drivers/serial/Kconfig | 6 ++ drivers/serial/serial_lpuart.c | 148 +++-- include/configs/colibri_vf.h | 6 +- include/configs/ls1021atwr.h | 1 + include/configs/pcm052.h | 6 +- include/configs/vf610twr.h | 6 +- 16 files changed, 180 insertions(+), 83 deletions(-) create mode 100644 arch/arm/include/asm/arch-ls102xa/serial.h create mode 100644 arch/arm/include/asm/arch-vf610/serial.h -- Please see existing patch series @ http://patchwork.ozlabs.org/patch/561855/. You can drop the ls102xa changes and rebase your patch series on top of that. Thanks! We are not aware of this patch set, sorry! about that. You want me to drop only the ls102xa changes? How about the changes/updates to the lpuart driver? should i update them with your device tree support stuff and rebase the remaining patch set along with your Signed-off-by tag ? Any suggestions ? Regards, Bin -- Best regards, Bhuvan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 13/17] net: tsec: Add driver model ethernet support
This adds driver model support to Freescale TSEC ethernet driver.
Signed-off-by: Bin Meng
---
drivers/net/tsec.c | 186 +
include/tsec.h | 10 +++
2 files changed, 196 insertions(+)
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 7e8bc68..18b44f6 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -10,6 +10,7 @@
#include
#include
+#include
#include
#include
#include
@@ -21,6 +22,7 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifndef CONFIG_DM_ETH
/* Default initializations for TSEC controllers. */
static struct tsec_info_struct tsec_info[] = {
@@ -46,6 +48,7 @@ static struct tsec_info_struct tsec_info[] = {
STD_TSEC_INFO(4), /* TSEC4 */
#endif
};
+#endif /* CONFIG_DM_ETH */
#define TBIANA_SETTINGS ( \
TBIANA_ASYMMETRIC_PAUSE \
@@ -98,7 +101,11 @@ static void tsec_configure_serdes(struct tsec_private *priv)
* for PowerPC (tm) is usually the case) in the register holds
* the entry.
*/
+#ifndef CONFIG_DM_ETH
static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
+#else
+static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int set)
+#endif
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
struct tsec __iomem *regs = priv->regs;
@@ -225,7 +232,11 @@ static void adjust_link(struct tsec_private *priv, struct
phy_device *phydev)
* do the same. Presumably, this would be zero if there were no
* errors
*/
+#ifndef CONFIG_DM_ETH
static int tsec_send(struct eth_device *dev, void *packet, int length)
+#else
+static int tsec_send(struct udevice *dev, void *packet, int length)
+#endif
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
struct tsec __iomem *regs = priv->regs;
@@ -268,6 +279,7 @@ static int tsec_send(struct eth_device *dev, void *packet,
int length)
return result;
}
+#ifndef CONFIG_DM_ETH
static int tsec_recv(struct eth_device *dev)
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
@@ -302,9 +314,61 @@ static int tsec_recv(struct eth_device *dev)
return -1;
}
+#else
+static int tsec_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct tsec_private *priv = (struct tsec_private *)dev->priv;
+ struct tsec __iomem *regs = priv->regs;
+ int ret = -1;
+
+ if (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
+ int length = in_be16(&priv->rxbd[priv->rx_idx].length);
+ uint16_t status = in_be16(&priv->rxbd[priv->rx_idx].status);
+ uint32_t buf;
+
+ /* Send the packet up if there were no errors */
+ if (!(status & RXBD_STATS)) {
+ buf = in_be32(&priv->rxbd[priv->rx_idx].bufptr);
+ *packetp = (uchar *)buf;
+ ret = length - 4;
+ } else {
+ printf("Got error %x\n", (status & RXBD_STATS));
+ }
+ }
+
+ if (in_be32(®s->ievent) & IEVENT_BSY) {
+ out_be32(®s->ievent, IEVENT_BSY);
+ out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
+ }
+
+ return ret;
+}
+
+static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ struct tsec_private *priv = (struct tsec_private *)dev->priv;
+ uint16_t status;
+
+ out_be16(&priv->rxbd[priv->rx_idx].length, 0);
+
+ status = RXBD_EMPTY;
+ /* Set the wrap bit if this is the last element in the list */
+ if ((priv->rx_idx + 1) == PKTBUFSRX)
+ status |= RXBD_WRAP;
+ out_be16(&priv->rxbd[priv->rx_idx].status, status);
+
+ priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
+
+ return 0;
+}
+#endif
/* Stop the interface */
+#ifndef CONFIG_DM_ETH
static void tsec_halt(struct eth_device *dev)
+#else
+static void tsec_halt(struct udevice *dev)
+#endif
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
struct tsec __iomem *regs = priv->regs;
@@ -467,9 +531,16 @@ static void startup_tsec(struct tsec_private *priv)
* that it returns success if the link is up, failure otherwise.
* This allows U-Boot to find the first active controller.
*/
+#ifndef CONFIG_DM_ETH
static int tsec_init(struct eth_device *dev, bd_t * bd)
+#else
+static int tsec_init(struct udevice *dev)
+#endif
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
+#ifdef CONFIG_DM_ETH
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+#endif
struct tsec __iomem *regs = priv->regs;
u32 tempval;
int ret;
@@ -489,12 +560,21 @@ static int tsec_init(struct eth_device *dev, bd_t * bd)
* order (BE), MACnADDR1 is set to 0xCDAB7856 and
* MACnADDR2 is set to 0x3412.
*/
+#ifndef CONFIG_DM_ETH
tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) |
(dev->enetaddr[3] <<
[U-Boot] [PATCH 17/17] arm: ls1021atwr: Convert to use driver model TSEC driver
Now that we have added driver model support to the TSEC driver,
convert ls1021atwr board to use it.
This depends on previous DM series for ls1021atwr:
http://patchwork.ozlabs.org/patch/561855/
Signed-off-by: Bin Meng
---
arch/arm/cpu/armv7/ls102xa/cpu.c| 2 +-
arch/arm/cpu/armv7/ls102xa/fdt.c| 10 ++
arch/arm/dts/ls1021a-twr.dts| 20
arch/arm/dts/ls1021a.dtsi | 18 --
board/freescale/ls1021atwr/ls1021atwr.c | 2 +-
configs/ls1021atwr_nor_defconfig| 2 +-
configs/ls1021atwr_nor_lpuart_defconfig | 2 +-
include/configs/ls1021atwr.h| 4
8 files changed, 54 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index 2f0df65..ee6b5ea 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -297,7 +297,7 @@ int cpu_mmc_init(bd_t *bis)
int cpu_eth_init(bd_t *bis)
{
-#ifdef CONFIG_TSEC_ENET
+#if defined(CONFIG_TSEC_ENET) && !defined(CONFIG_DM_ETH)
tsec_standard_init(bis);
#endif
diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c
index ae5e794..0a4944e 100644
--- a/arch/arm/cpu/armv7/ls102xa/fdt.c
+++ b/arch/arm/cpu/armv7/ls102xa/fdt.c
@@ -5,6 +5,7 @@
*/
#include
+#include
#include
#include
#include
@@ -22,7 +23,11 @@ DECLARE_GLOBAL_DATA_PTR;
void ft_fixup_enet_phy_connect_type(void *fdt)
{
+#ifndef CONFIG_DM_ETH
struct eth_device *dev;
+#else
+ struct udevice *dev;
+#endif
struct tsec_private *priv;
const char *enet_path, *phy_path;
char enet[16];
@@ -30,7 +35,12 @@ void ft_fixup_enet_phy_connect_type(void *fdt)
int phy_node;
int i = 0;
uint32_t ph;
+#ifndef CONFIG_DM_ETH
char *name[3] = { "eTSEC1", "eTSEC2", "eTSEC3" };
+#else
+ char *name[3] = { "ethernet@2d1", "ethernet@2d5",
+ "ethernet@2d9" };
+#endif
for (; i < ARRAY_SIZE(name); i++) {
dev = eth_get_dev_by_name(name[i]);
diff --git a/arch/arm/dts/ls1021a-twr.dts b/arch/arm/dts/ls1021a-twr.dts
index deabb12..2bfeb14 100644
--- a/arch/arm/dts/ls1021a-twr.dts
+++ b/arch/arm/dts/ls1021a-twr.dts
@@ -57,6 +57,26 @@
};
};
+&enet0 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&sgmii_phy2>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet1 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&sgmii_phy0>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet2 {
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii-id";
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
};
diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index ee0e554..2ecb345 100644
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -352,13 +352,27 @@
};
mdio0: mdio@2d24000 {
- compatible = "gianfar";
- device_type = "mdio";
+ compatible = "fsl,tsec-mdio";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2d24000 0x4000>;
};
+ enet0: ethernet@2d1 {
+ compatible = "fsl,tsec";
+ reg = <0x2d1 0x1000>;
+ };
+
+ enet1: ethernet@2d5 {
+ compatible = "fsl,tsec";
+ reg = <0x2d5 0x1000>;
+ };
+
+ enet2: ethernet@2d9 {
+ compatible = "fsl,tsec";
+ reg = <0x2d9 0x1000>;
+ };
+
usb@860 {
compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
reg = <0x860 0x1000>;
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c
b/board/freescale/ls1021atwr/ls1021atwr.c
index f82e567..d4d0cb9 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -245,7 +245,7 @@ int board_mmc_init(bd_t *bis)
int board_eth_init(bd_t *bis)
{
-#ifdef CONFIG_TSEC_ENET
+#if defined(CONFIG_TSEC_ENET) && !defined(CONFIG_DM_ETH)
struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[4];
int num = 0;
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index ddda0b8..1c8d2c1 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -5,5 +5,5 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr"
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
-CONFIG_NETDEVICES=y
+CONFIG_DM_ETH=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig
b/configs/ls1021atwr_nor_lpuart_defconfig
index 3564736..aec5bf3 100644
--- a/configs/ls1021atwr_nor_lpuart_defconfig
++
[U-Boot] [PATCH 14/17] net: tsec: Use priv->tbiaddr to initialize TBI PHY address
Add a new member 'tbiaddr' to tsec_private struct. For non-DM driver,
it is initialized as CONFIG_SYS_TBIPA_VALUE, but for DM driver, we
can get this from device tree. Update the bindings doc as well.
Signed-off-by: Bin Meng
---
doc/device-tree-bindings/net/fsl-tsec-phy.txt | 21 +
drivers/net/tsec.c| 13 -
include/tsec.h| 1 +
3 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/doc/device-tree-bindings/net/fsl-tsec-phy.txt
b/doc/device-tree-bindings/net/fsl-tsec-phy.txt
index dbe91aa..c5bf48c 100644
--- a/doc/device-tree-bindings/net/fsl-tsec-phy.txt
+++ b/doc/device-tree-bindings/net/fsl-tsec-phy.txt
@@ -41,3 +41,24 @@ Example:
reg = <0>;
};
};
+
+* TBI Internal MDIO bus
+
+As of this writing, every tsec is associated with an internal TBI PHY.
+This PHY is accessed through the local MDIO bus. These buses are defined
+similarly to the mdio buses. The TBI PHYs underneath them are similar to
+normal PHYs, but the reg property is considered instructive, rather than
+descriptive. The reg property should be chosen so it doesn't interfere
+with other PHYs on the bus. The TBI PHYs are referred to by a "tbi-handle"
+property under the tsec node, which has a similar meaning of "phy-handle".
+
+Example:
+ ethernet@24000 {
+ phy-handle = <&tbi1>;
+ };
+
+ mdio@24520 {
+ tbi1: tbi-phy@1f {
+ reg = <0x1f>;
+ };
+ };
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 18b44f6..025e7a7 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -658,7 +658,7 @@ static int init_phy(struct tsec_private *priv)
supported |= SUPPORTED_1000baseT_Full;
/* Assign a Physical address to the TBI */
- out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
+ out_be32(®s->tbipa, priv->tbiaddr);
priv->interface = tsec_get_interface(priv);
@@ -707,6 +707,7 @@ static int tsec_initialize(bd_t *bis, struct
tsec_info_struct *tsec_info)
priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
priv->phyaddr = tsec_info->phyaddr;
+ priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
priv->flags = tsec_info->flags;
sprintf(dev->name, tsec_info->devname);
@@ -801,6 +802,16 @@ int tsec_probe(struct udevice *dev)
return -ENOENT;
}
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
+ "tbi-handle");
+ if (offset > 0) {
+ reg = fdtdec_get_int(gd->fdt_blob, offset, "reg",
+CONFIG_SYS_TBIPA_VALUE);
+ priv->tbiaddr = reg;
+ } else {
+ priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
+ }
+
phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset,
"phy-connection-type", NULL);
if (phy_mode)
diff --git a/include/tsec.h b/include/tsec.h
index 88ce964..fb27edf 100644
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -402,6 +402,7 @@ struct tsec_private {
phy_interface_t interface;
struct mii_dev *bus;
uint phyaddr;
+ uint tbiaddr;
char mii_devname[16];
u32 flags;
uint rx_idx;/* index of the current RX buffer */
--
1.8.2.1
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[U-Boot] [PATCH 16/17] arm: ls1021atwr: Disable CONFIG_E1000 temporarily
Before we switch to use driver model ethernet support, disable CONFIG_E1000 temporarily as with driver model ethernet, E1000 driver depends on driver model PCI which is not ready on this board yet. Signed-off-by: Bin Meng --- configs/ls1021atwr_nor_defconfig| 1 - configs/ls1021atwr_nor_lpuart_defconfig | 1 - 2 files changed, 2 deletions(-) diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index 2b79443..ddda0b8 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -6,5 +6,4 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr" CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_NETDEVICES=y -CONFIG_E1000=y CONFIG_SYS_NS16550=y diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index 5346359..3564736 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -7,5 +7,4 @@ CONFIG_SYS_EXTRA_OPTIONS="LPUART" CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_NETDEVICES=y -CONFIG_E1000=y CONFIG_FSL_LPUART=y -- 1.8.2.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 11/17] net: tsec: Use tsec_private pointer as the parameter for internal routines
For internal routines like redundant_init(), startup_tsec() and
init_phy(), change to use tsec_private pointer as the parameter.
Signed-off-by: Bin Meng
---
drivers/net/tsec.c | 23 +++
include/tsec.h | 1 +
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index ea2363e..7e8bc68 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -328,9 +328,8 @@ static void tsec_halt(struct eth_device *dev)
* of the eTSEC port initialization sequence,
* the eTSEC Rx logic may not be properly initialized.
*/
-void redundant_init(struct eth_device *dev)
+void redundant_init(struct tsec_private *priv)
{
- struct tsec_private *priv = dev->priv;
struct tsec __iomem *regs = priv->regs;
uint t, count = 0;
int fail = 1;
@@ -365,14 +364,14 @@ void redundant_init(struct eth_device *dev)
do {
uint16_t status;
- tsec_send(dev, (void *)pkt, sizeof(pkt));
+ tsec_send(priv->dev, (void *)pkt, sizeof(pkt));
/* Wait for buffer to be received */
for (t = 0;
in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY;
t++) {
if (t >= 10 * TOUT_LOOP) {
- printf("%s: tsec: rx error\n", dev->name);
+ printf("%s: tsec: rx error\n", priv->dev->name);
break;
}
}
@@ -412,9 +411,8 @@ void redundant_init(struct eth_device *dev)
* Set up the buffers and their descriptors, and bring up the
* interface
*/
-static void startup_tsec(struct eth_device *dev)
+static void startup_tsec(struct tsec_private *priv)
{
- struct tsec_private *priv = (struct tsec_private *)dev->priv;
struct tsec __iomem *regs = priv->regs;
uint16_t status;
int i;
@@ -451,7 +449,7 @@ static void startup_tsec(struct eth_device *dev)
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
svr = get_svr();
if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
- redundant_init(dev);
+ redundant_init(priv);
#endif
/* Enable Transmit and Receive */
setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
@@ -504,7 +502,7 @@ static int tsec_init(struct eth_device *dev, bd_t * bd)
init_registers(regs);
/* Ready the device for tx/rx */
- startup_tsec(dev);
+ startup_tsec(priv);
/* Start up the PHY */
ret = phy_startup(priv->phydev);
@@ -567,9 +565,8 @@ static phy_interface_t tsec_get_interface(struct
tsec_private *priv)
* properly. If the PHY is not recognized, then return 0
* (failure). Otherwise, return 1
*/
-static int init_phy(struct eth_device *dev)
+static int init_phy(struct tsec_private *priv)
{
- struct tsec_private *priv = (struct tsec_private *)dev->priv;
struct phy_device *phydev;
struct tsec __iomem *regs = priv->regs;
u32 supported = (SUPPORTED_10baseT_Half |
@@ -588,7 +585,8 @@ static int init_phy(struct eth_device *dev)
if (priv->interface == PHY_INTERFACE_MODE_SGMII)
tsec_configure_serdes(priv);
- phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
+ phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
+priv->interface);
if (!phydev)
return 0;
@@ -633,6 +631,7 @@ static int tsec_initialize(bd_t *bis, struct
tsec_info_struct *tsec_info)
sprintf(dev->name, tsec_info->devname);
priv->interface = tsec_info->interface;
priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
+ priv->dev = dev;
dev->iobase = 0;
dev->priv = priv;
dev->init = tsec_init;
@@ -655,7 +654,7 @@ static int tsec_initialize(bd_t *bis, struct
tsec_info_struct *tsec_info)
clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
/* Try to initialize PHY here, and return */
- return init_phy(dev);
+ return init_phy(priv);
}
/*
diff --git a/include/tsec.h b/include/tsec.h
index 7200229..e8b03d6 100644
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -402,6 +402,7 @@ struct tsec_private {
u32 flags;
uint rx_idx;/* index of the current RX buffer */
uint tx_idx;/* index of the current TX buffer */
+ struct eth_device *dev;
};
struct tsec_info_struct {
--
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[U-Boot] [PATCH 12/17] doc: dt-bindings: Describe Freescale TSEC ethernet controller
Adapted from the same file name in the kernel device tree bindings
documentation, to use with U-Boot.
Signed-off-by: Bin Meng
---
doc/device-tree-bindings/net/fsl-tsec-phy.txt | 43 +++
1 file changed, 43 insertions(+)
create mode 100644 doc/device-tree-bindings/net/fsl-tsec-phy.txt
diff --git a/doc/device-tree-bindings/net/fsl-tsec-phy.txt
b/doc/device-tree-bindings/net/fsl-tsec-phy.txt
new file mode 100644
index 000..dbe91aa
--- /dev/null
+++ b/doc/device-tree-bindings/net/fsl-tsec-phy.txt
@@ -0,0 +1,43 @@
+* TSEC-compatible ethernet nodes
+
+Properties:
+
+ - compatible : Should be "fsl,tsec"
+ - reg : Offset and length of the register set for the device
+ - phy-handle : See ethernet.txt file in the same directory.
+ - phy-connection-type : See ethernet.txt file in the same directory. This
+property is only really needed if the connection is of type "rgmii-id",
+"rgmii-rxid" and "rgmii-txid" as all other connection types are detected
+by hardware.
+
+Example:
+ ethernet@24000 {
+ compatible = "fsl,tsec";
+ reg = <0x24000 0x1000>;
+ phy-handle = <&phy0>;
+ phy-connection-type = "sgmii";
+ };
+
+Child nodes of the TSEC controller are typically the individual PHY devices
+connected via the MDIO bus (sometimes the MDIO bus controller is separate).
+
+* MDIO IO device
+
+The MDIO is a bus to which the PHY devices are connected. For each
+device that exists on this bus, a PHY node should be created.
+
+Required properties:
+ - compatible : Should define the compatible device type for the
+mdio. Currently supported string/device is "fsl,tsec-mdio".
+ - reg : Offset and length of the register set for the device
+
+Example:
+
+ mdio@24520 {
+ compatible = "fsl,tsec-mdio";
+ reg = <0x24520 0x20>;
+
+ ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
--
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[U-Boot] [PATCH 15/17] arm: ls102xa: Rewrite the logic of ft_fixup_enet_phy_connect_type()
eth_get_dev_by_index() is an API which is not available in driver
model. Use eth_get_dev_by_name() instead, which can also simplifly
the code logic a little bit.
Signed-off-by: Bin Meng
---
arch/arm/cpu/armv7/ls102xa/fdt.c | 16 ++--
1 file changed, 6 insertions(+), 10 deletions(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c
index 856abed..ae5e794 100644
--- a/arch/arm/cpu/armv7/ls102xa/fdt.c
+++ b/arch/arm/cpu/armv7/ls102xa/fdt.c
@@ -30,17 +30,13 @@ void ft_fixup_enet_phy_connect_type(void *fdt)
int phy_node;
int i = 0;
uint32_t ph;
+ char *name[3] = { "eTSEC1", "eTSEC2", "eTSEC3" };
- while ((dev = eth_get_dev_by_index(i++)) != NULL) {
- if (strstr(dev->name, "eTSEC1")) {
- strcpy(enet, "ethernet0");
- strcpy(phy, "enet0_rgmii_phy");
- } else if (strstr(dev->name, "eTSEC2")) {
- strcpy(enet, "ethernet1");
- strcpy(phy, "enet1_rgmii_phy");
- } else if (strstr(dev->name, "eTSEC3")) {
- strcpy(enet, "ethernet2");
- strcpy(phy, "enet2_rgmii_phy");
+ for (; i < ARRAY_SIZE(name); i++) {
+ dev = eth_get_dev_by_name(name[i]);
+ if (dev) {
+ sprintf(enet, "ethernet%d", i);
+ sprintf(phy, "enet%d_rgmii_phy", i);
} else {
continue;
}
--
1.8.2.1
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[U-Boot] [PATCH 08/17] net: tsec: Move rx_idx and tx_idx to struct tsec_private
At present rx_idx and tx_idx are declared as static variables
in the driver codes. To support multiple interfaces, move it to
struct tsec_private.
Signed-off-by: Bin Meng
---
drivers/net/tsec.c | 54 ++
include/tsec.h | 2 ++
2 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 4aeb387..943c4b3 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -23,9 +23,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define TX_BUF_CNT 2
-static uint rx_idx;/* index of the current RX buffer */
-static uint tx_idx;/* index of the current TX buffer */
-
#ifdef __GNUC__
static struct txbd8 __iomem txbd[TX_BUF_CNT] __aligned(8);
static struct rxbd8 __iomem rxbd[PKTBUFSRX] __aligned(8);
@@ -280,22 +277,23 @@ void redundant_init(struct eth_device *dev)
tsec_send(dev, (void *)pkt, sizeof(pkt));
/* Wait for buffer to be received */
- for (t = 0; in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY; t++) {
+ for (t = 0; in_be16(&rxbd[priv->rx_idx].status) & RXBD_EMPTY;
+t++) {
if (t >= 10 * TOUT_LOOP) {
printf("%s: tsec: rx error\n", dev->name);
break;
}
}
- if (!memcmp(pkt, (void *)net_rx_packets[rx_idx], sizeof(pkt)))
+ if (!memcmp(pkt, net_rx_packets[priv->rx_idx], sizeof(pkt)))
fail = 0;
- out_be16(&rxbd[rx_idx].length, 0);
+ out_be16(&rxbd[priv->rx_idx].length, 0);
status = RXBD_EMPTY;
- if ((rx_idx + 1) == PKTBUFSRX)
+ if ((priv->rx_idx + 1) == PKTBUFSRX)
status |= RXBD_WRAP;
- out_be16(&rxbd[rx_idx].status, status);
- rx_idx = (rx_idx + 1) % PKTBUFSRX;
+ out_be16(&rxbd[priv->rx_idx].status, status);
+ priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
if (in_be32(®s->ievent) & IEVENT_BSY) {
out_be32(®s->ievent, IEVENT_BSY);
@@ -330,8 +328,8 @@ static void startup_tsec(struct eth_device *dev)
int i;
/* reset the indices to zero */
- rx_idx = 0;
- tx_idx = 0;
+ priv->rx_idx = 0;
+ priv->tx_idx = 0;
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
uint svr;
#endif
@@ -388,32 +386,32 @@ static int tsec_send(struct eth_device *dev, void
*packet, int length)
int i;
/* Find an empty buffer descriptor */
- for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) {
+ for (i = 0; in_be16(&txbd[priv->tx_idx].status) & TXBD_READY; i++) {
if (i >= TOUT_LOOP) {
debug("%s: tsec: tx buffers full\n", dev->name);
return result;
}
}
- out_be32(&txbd[tx_idx].bufptr, (u32)packet);
- out_be16(&txbd[tx_idx].length, length);
- status = in_be16(&txbd[tx_idx].status);
- out_be16(&txbd[tx_idx].status, status |
+ out_be32(&txbd[priv->tx_idx].bufptr, (u32)packet);
+ out_be16(&txbd[priv->tx_idx].length, length);
+ status = in_be16(&txbd[priv->tx_idx].status);
+ out_be16(&txbd[priv->tx_idx].status, status |
(TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
/* Tell the DMA to go */
out_be32(®s->tstat, TSTAT_CLEAR_THALT);
/* Wait for buffer to be transmitted */
- for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) {
+ for (i = 0; in_be16(&txbd[priv->tx_idx].status) & TXBD_READY; i++) {
if (i >= TOUT_LOOP) {
debug("%s: tsec: tx error\n", dev->name);
return result;
}
}
- tx_idx = (tx_idx + 1) % TX_BUF_CNT;
- result = in_be16(&txbd[tx_idx].status) & TXBD_STATS;
+ priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT;
+ result = in_be16(&txbd[priv->tx_idx].status) & TXBD_STATS;
return result;
}
@@ -423,26 +421,26 @@ static int tsec_recv(struct eth_device *dev)
struct tsec_private *priv = (struct tsec_private *)dev->priv;
struct tsec __iomem *regs = priv->regs;
- while (!(in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY)) {
- int length = in_be16(&rxbd[rx_idx].length);
- uint16_t status = in_be16(&rxbd[rx_idx].status);
+ while (!(in_be16(&rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
+ int length = in_be16(&rxbd[priv->rx_idx].length);
+ uint16_t status = in_be16(&rxbd[priv->rx_idx].status);
+ uchar *packet = net_rx_packets[priv->rx_idx];
/* Send the packet up if there were no errors */
if (!(status & RXBD_STATS))
- net_process_r
[U-Boot] [PATCH 10/17] net: tsec: Adjust orders to avoid forward declaration of tsec_send()
Adjust static functions in a proper order so that forward declaration
of tsec_send() can be avoided.
Signed-off-by: Bin Meng
---
drivers/net/tsec.c | 208 ++---
1 file changed, 103 insertions(+), 105 deletions(-)
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 9a3b1a9..ea2363e 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -21,8 +21,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static int tsec_send(struct eth_device *dev, void *packet, int length);
-
/* Default initializations for TSEC controllers. */
static struct tsec_info_struct tsec_info[] = {
@@ -221,6 +219,109 @@ static void adjust_link(struct tsec_private *priv, struct
phy_device *phydev)
(phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
}
+/*
+ * This returns the status bits of the device. The return value
+ * is never checked, and this is what the 8260 driver did, so we
+ * do the same. Presumably, this would be zero if there were no
+ * errors
+ */
+static int tsec_send(struct eth_device *dev, void *packet, int length)
+{
+ struct tsec_private *priv = (struct tsec_private *)dev->priv;
+ struct tsec __iomem *regs = priv->regs;
+ uint16_t status;
+ int result = 0;
+ int i;
+
+ /* Find an empty buffer descriptor */
+ for (i = 0;
+in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
+i++) {
+ if (i >= TOUT_LOOP) {
+ debug("%s: tsec: tx buffers full\n", dev->name);
+ return result;
+ }
+ }
+
+ out_be32(&priv->txbd[priv->tx_idx].bufptr, (u32)packet);
+ out_be16(&priv->txbd[priv->tx_idx].length, length);
+ status = in_be16(&priv->txbd[priv->tx_idx].status);
+ out_be16(&priv->txbd[priv->tx_idx].status, status |
+ (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
+
+ /* Tell the DMA to go */
+ out_be32(®s->tstat, TSTAT_CLEAR_THALT);
+
+ /* Wait for buffer to be transmitted */
+ for (i = 0;
+in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
+i++) {
+ if (i >= TOUT_LOOP) {
+ debug("%s: tsec: tx error\n", dev->name);
+ return result;
+ }
+ }
+
+ priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT;
+ result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS;
+
+ return result;
+}
+
+static int tsec_recv(struct eth_device *dev)
+{
+ struct tsec_private *priv = (struct tsec_private *)dev->priv;
+ struct tsec __iomem *regs = priv->regs;
+
+ while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
+ int length = in_be16(&priv->rxbd[priv->rx_idx].length);
+ uint16_t status = in_be16(&priv->rxbd[priv->rx_idx].status);
+ uchar *packet = net_rx_packets[priv->rx_idx];
+
+ /* Send the packet up if there were no errors */
+ if (!(status & RXBD_STATS))
+ net_process_received_packet(packet, length - 4);
+ else
+ printf("Got error %x\n", (status & RXBD_STATS));
+
+ out_be16(&priv->rxbd[priv->rx_idx].length, 0);
+
+ status = RXBD_EMPTY;
+ /* Set the wrap bit if this is the last element in the list */
+ if ((priv->rx_idx + 1) == PKTBUFSRX)
+ status |= RXBD_WRAP;
+ out_be16(&priv->rxbd[priv->rx_idx].status, status);
+
+ priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
+ }
+
+ if (in_be32(®s->ievent) & IEVENT_BSY) {
+ out_be32(®s->ievent, IEVENT_BSY);
+ out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
+ }
+
+ return -1;
+}
+
+/* Stop the interface */
+static void tsec_halt(struct eth_device *dev)
+{
+ struct tsec_private *priv = (struct tsec_private *)dev->priv;
+ struct tsec __iomem *regs = priv->regs;
+
+ clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+ setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+
+ while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
+ != (IEVENT_GRSC | IEVENT_GTSC))
+ ;
+
+ clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
+
+ /* Shut down the PHY, as needed */
+ phy_shutdown(priv->phydev);
+}
+
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
/*
* When MACCFG1[Rx_EN] is enabled during system boot as part
@@ -363,109 +464,6 @@ static void startup_tsec(struct eth_device *dev)
}
/*
- * This returns the status bits of the device. The return value
- * is never checked, and this is what the 8260 driver did, so we
- * do the same. Presumably, this would be zero if there were no
- * errors
- */
-static int tsec_send(struct eth_device *dev, void *packet, int length)
-{
- struct tsec_private *priv = (struct tse
[U-Boot] [PATCH 02/17] powerpc: c29xpcie: Do not wrap pci_eth_init() with CONFIG_TSEC_ENET
The call to pci_eth_init() should not be wrapped with CONFIG_TSEC_ENET.
Signed-off-by: Bin Meng
---
board/freescale/c29xpcie/c29xpcie.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/c29xpcie/c29xpcie.c
b/board/freescale/c29xpcie/c29xpcie.c
index f42d373..e325b4d 100644
--- a/board/freescale/c29xpcie/c29xpcie.c
+++ b/board/freescale/c29xpcie/c29xpcie.c
@@ -83,9 +83,9 @@ void pci_init_board(void)
}
#endif /* ifdef CONFIG_PCI */
-#ifdef CONFIG_TSEC_ENET
int board_eth_init(bd_t *bis)
{
+#ifdef CONFIG_TSEC_ENET
struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[2];
int num = 0;
@@ -110,10 +110,10 @@ int board_eth_init(bd_t *bis)
fsl_pq_mdio_init(bis, &mdio_info);
tsec_eth_init(bis, tsec_info, num);
+#endif
return pci_eth_init(bis);
}
-#endif
#if defined(CONFIG_OF_BOARD_SETUP)
void fdt_del_sec(void *blob, int offset)
--
1.8.2.1
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[U-Boot] [PATCH 03/17] powerpc: mpc8572ds: Do not wrap pci_eth_init() with CONFIG_TSEC_ENET
The call to pci_eth_init() should not be wrapped with CONFIG_TSEC_ENET.
Signed-off-by: Bin Meng
---
board/freescale/mpc8572ds/mpc8572ds.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c
b/board/freescale/mpc8572ds/mpc8572ds.c
index 3f68cf4..ed6836a 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -171,9 +171,9 @@ int board_early_init_r(void)
return 0;
}
-#ifdef CONFIG_TSEC_ENET
int board_eth_init(bd_t *bis)
{
+#ifdef CONFIG_TSEC_ENET
struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[4];
int num = 0;
@@ -226,10 +226,10 @@ int board_eth_init(bd_t *bis)
fsl_pq_mdio_init(bis, &mdio_info);
tsec_eth_init(bis, tsec_info, num);
+#endif
return pci_eth_init(bis);
}
-#endif
#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
--
1.8.2.1
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[U-Boot] [PATCH 05/17] powerpc: p1010rdb: Do not wrap pci_eth_init() with CONFIG_TSEC_ENET
The call to pci_eth_init() should not be wrapped with CONFIG_TSEC_ENET.
Signed-off-by: Bin Meng
---
board/freescale/p1010rdb/p1010rdb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/p1010rdb/p1010rdb.c
b/board/freescale/p1010rdb/p1010rdb.c
index ebffe9a..1ae1540 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -326,9 +326,9 @@ int checkboard(void)
return 0;
}
-#ifdef CONFIG_TSEC_ENET
int board_eth_init(bd_t *bis)
{
+#ifdef CONFIG_TSEC_ENET
struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[4];
struct cpu_type *cpu;
@@ -362,10 +362,10 @@ int board_eth_init(bd_t *bis)
fsl_pq_mdio_init(bis, &mdio_info);
tsec_eth_init(bis, tsec_info, num);
+#endif
return pci_eth_init(bis);
}
-#endif
#if defined(CONFIG_OF_BOARD_SETUP)
void fdt_del_flexcan(void *blob)
--
1.8.2.1
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[U-Boot] [PATCH 06/17] arm: ls1021atwr: Do not wrap pci_eth_init() with CONFIG_TSEC_ENET
The call to pci_eth_init() should not be wrapped with CONFIG_TSEC_ENET.
Signed-off-by: Bin Meng
---
board/freescale/ls1021atwr/ls1021atwr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c
b/board/freescale/ls1021atwr/ls1021atwr.c
index 8eaff5f..f82e567 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -243,9 +243,9 @@ int board_mmc_init(bd_t *bis)
}
#endif
-#ifdef CONFIG_TSEC_ENET
int board_eth_init(bd_t *bis)
{
+#ifdef CONFIG_TSEC_ENET
struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[4];
int num = 0;
@@ -280,10 +280,10 @@ int board_eth_init(bd_t *bis)
fsl_pq_mdio_init(bis, &mdio_info);
tsec_eth_init(bis, tsec_info, num);
+#endif
return pci_eth_init(bis);
}
-#endif
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
int config_serdes_mux(void)
--
1.8.2.1
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[U-Boot] [PATCH 09/17] net: tsec: Move rxbd and txbd to struct tsec_private
rxbd and txbd are declared static with 8 byte alignment requirement,
but they can be put into struct tsec_private as well and are natually
aligned to 8 byte.
Signed-off-by: Bin Meng
---
drivers/net/tsec.c | 69 +-
include/tsec.h | 4
2 files changed, 36 insertions(+), 37 deletions(-)
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 943c4b3..9a3b1a9 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -21,16 +21,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#define TX_BUF_CNT 2
-
-#ifdef __GNUC__
-static struct txbd8 __iomem txbd[TX_BUF_CNT] __aligned(8);
-static struct rxbd8 __iomem rxbd[PKTBUFSRX] __aligned(8);
-
-#else
-#error "rtx must be 64-bit aligned"
-#endif
-
static int tsec_send(struct eth_device *dev, void *packet, int length);
/* Default initializations for TSEC controllers. */
@@ -277,7 +267,8 @@ void redundant_init(struct eth_device *dev)
tsec_send(dev, (void *)pkt, sizeof(pkt));
/* Wait for buffer to be received */
- for (t = 0; in_be16(&rxbd[priv->rx_idx].status) & RXBD_EMPTY;
+ for (t = 0;
+in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY;
t++) {
if (t >= 10 * TOUT_LOOP) {
printf("%s: tsec: rx error\n", dev->name);
@@ -288,11 +279,11 @@ void redundant_init(struct eth_device *dev)
if (!memcmp(pkt, net_rx_packets[priv->rx_idx], sizeof(pkt)))
fail = 0;
- out_be16(&rxbd[priv->rx_idx].length, 0);
+ out_be16(&priv->rxbd[priv->rx_idx].length, 0);
status = RXBD_EMPTY;
if ((priv->rx_idx + 1) == PKTBUFSRX)
status |= RXBD_WRAP;
- out_be16(&rxbd[priv->rx_idx].status, status);
+ out_be16(&priv->rxbd[priv->rx_idx].status, status);
priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
if (in_be32(®s->ievent) & IEVENT_BSY) {
@@ -335,26 +326,26 @@ static void startup_tsec(struct eth_device *dev)
#endif
/* Point to the buffer descriptors */
- out_be32(®s->tbase, (u32)&txbd[0]);
- out_be32(®s->rbase, (u32)&rxbd[0]);
+ out_be32(®s->tbase, (u32)&priv->txbd[0]);
+ out_be32(®s->rbase, (u32)&priv->rxbd[0]);
/* Initialize the Rx Buffer descriptors */
for (i = 0; i < PKTBUFSRX; i++) {
- out_be16(&rxbd[i].status, RXBD_EMPTY);
- out_be16(&rxbd[i].length, 0);
- out_be32(&rxbd[i].bufptr, (u32)net_rx_packets[i]);
+ out_be16(&priv->rxbd[i].status, RXBD_EMPTY);
+ out_be16(&priv->rxbd[i].length, 0);
+ out_be32(&priv->rxbd[i].bufptr, (u32)net_rx_packets[i]);
}
- status = in_be16(&rxbd[PKTBUFSRX - 1].status);
- out_be16(&rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
+ status = in_be16(&priv->rxbd[PKTBUFSRX - 1].status);
+ out_be16(&priv->rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
/* Initialize the TX Buffer Descriptors */
for (i = 0; i < TX_BUF_CNT; i++) {
- out_be16(&txbd[i].status, 0);
- out_be16(&txbd[i].length, 0);
- out_be32(&txbd[i].bufptr, 0);
+ out_be16(&priv->txbd[i].status, 0);
+ out_be16(&priv->txbd[i].length, 0);
+ out_be32(&priv->txbd[i].bufptr, 0);
}
- status = in_be16(&txbd[TX_BUF_CNT - 1].status);
- out_be16(&txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
+ status = in_be16(&priv->txbd[TX_BUF_CNT - 1].status);
+ out_be16(&priv->txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
svr = get_svr();
@@ -386,24 +377,28 @@ static int tsec_send(struct eth_device *dev, void
*packet, int length)
int i;
/* Find an empty buffer descriptor */
- for (i = 0; in_be16(&txbd[priv->tx_idx].status) & TXBD_READY; i++) {
+ for (i = 0;
+in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
+i++) {
if (i >= TOUT_LOOP) {
debug("%s: tsec: tx buffers full\n", dev->name);
return result;
}
}
- out_be32(&txbd[priv->tx_idx].bufptr, (u32)packet);
- out_be16(&txbd[priv->tx_idx].length, length);
- status = in_be16(&txbd[priv->tx_idx].status);
- out_be16(&txbd[priv->tx_idx].status, status |
+ out_be32(&priv->txbd[priv->tx_idx].bufptr, (u32)packet);
+ out_be16(&priv->txbd[priv->tx_idx].length, length);
+ status = in_be16(&priv->txbd[priv->tx_idx].status);
+ out_be16(&priv->txbd[priv->tx_idx].status, status |
(TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
/* Tell the DMA to go */
out_be32(®s->tstat, TSTAT_CLEAR_THALT);
[U-Boot] [PATCH 04/17] powerpc: mpc8548cds: Do not wrap pci_eth_init() with CONFIG_TSEC_ENET
The call to pci_eth_init() should not be wrapped with CONFIG_TSEC_ENET.
Signed-off-by: Bin Meng
---
board/freescale/mpc8548cds/mpc8548cds.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c
b/board/freescale/mpc8548cds/mpc8548cds.c
index ca9b43c..de76d36 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -301,9 +301,9 @@ void configure_rgmii(void)
return;
}
-#ifdef CONFIG_TSEC_ENET
int board_eth_init(bd_t *bis)
{
+#ifdef CONFIG_TSEC_ENET
struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[4];
int num = 0;
@@ -345,10 +345,10 @@ int board_eth_init(bd_t *bis)
tsec_eth_init(bis, tsec_info, num);
configure_rgmii();
+#endif
return pci_eth_init(bis);
}
-#endif
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_pci_setup(void *blob, bd_t *bd)
--
1.8.2.1
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[U-Boot] [PATCH 07/17] net: tsec: fsl_mdio: Fix several cosmetic issues
Clean up the tsec and fsl_mdio driver codes a little bit, by:
- Fix misuse of tab and space here and there
- Use correct multi-line comment format
- Replace license identifier to GPL-2.0+
Signed-off-by: Bin Meng
---
drivers/net/fsl_mdio.c | 4 ++--
drivers/net/tsec.c | 61 --
include/fsl_mdio.h | 7 +++---
include/tsec.h | 51 ++---
4 files changed, 62 insertions(+), 61 deletions(-)
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index d6b181b..ae3d035 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c
@@ -5,6 +5,7 @@
*
* SPDX-License-Identifier:GPL-2.0+
*/
+
#include
#include
#include
@@ -32,8 +33,7 @@ int tsec_local_mdio_read(struct tsec_mii_mng __iomem
*phyregs, int port_addr,
int value;
int timeout = 100;
- /* Put the address of the phy, and the register
-* number into MIIMADD */
+ /* Put the address of the phy, and the register number into MIIMADD */
out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f));
/* Clear the command register, and wait */
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 4bdc188..4aeb387 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -1,14 +1,11 @@
/*
* Freescale Three Speed Ethernet Controller driver
*
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
* Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
* (C) Copyright 2003, Motorola, Inc.
* author Andy Fleming
*
+ * SPDX-License-Identifier:GPL-2.0+
*/
#include
@@ -84,8 +81,10 @@ static struct tsec_info_struct tsec_info[] = {
/* Configure the TBI for SGMII operation */
static void tsec_configure_serdes(struct tsec_private *priv)
{
- /* Access TBI PHY registers at given TSEC register offset as opposed
-* to the register offset used for external PHY accesses */
+ /*
+* Access TBI PHY registers at given TSEC register offset as opposed
+* to the register offset used for external PHY accesses
+*/
tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
0, TBI_ANA, TBIANA_SETTINGS);
tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
@@ -100,7 +99,8 @@ static void tsec_configure_serdes(struct tsec_private *priv)
/* Set the appropriate hash bit for the given addr */
-/* The algorithm works like so:
+/*
+ * The algorithm works like so:
* 1) Take the Destination Address (ie the multicast address), and
* do a CRC on it (little endian), and reverse the bits of the
* result.
@@ -111,9 +111,9 @@ static void tsec_configure_serdes(struct tsec_private *priv)
* hash index which gaddr register to use, and the 5 other bits
* indicate which bit (assuming an IBM numbering scheme, which
* for PowerPC (tm) is usually the case) in the register holds
- * the entry. */
-static int
-tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
+ * the entry.
+ */
+static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
struct tsec __iomem *regs = priv->regs;
@@ -135,7 +135,8 @@ tsec_mcast_addr(struct eth_device *dev, const u8
*mcast_mac, u8 set)
}
#endif /* Multicast TFTP ? */
-/* Initialized required registers to appropriate values, zeroing
+/*
+ * Initialized required registers to appropriate values, zeroing
* those we don't care about (unless zero is bad, in which case,
* choose a more appropriate value)
*/
@@ -181,7 +182,8 @@ static void init_registers(struct tsec __iomem *regs)
}
-/* Configure maccfg2 based on negotiated speed and duplex
+/*
+ * Configure maccfg2 based on negotiated speed and duplex
* reported by PHY handling code
*/
static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
@@ -212,7 +214,8 @@ static void adjust_link(struct tsec_private *priv, struct
phy_device *phydev)
case 10:
maccfg2 |= MACCFG2_MII;
- /* Set R100 bit in all modes although
+ /*
+* Set R100 bit in all modes although
* it is only used in RGMII mode
*/
if (phydev->speed == 100)
@@ -315,7 +318,8 @@ void redundant_init(struct eth_device *dev)
}
#endif
-/* Set up the buffers and their descriptors, and bring up the
+/*
+ * Set up the buffers and their descriptors, and bring up the
* interface
*/
static void startup_tsec(struct eth_device *dev)
@@ -369,9 +373,10 @@ static void startup_tsec(struct eth_device *dev)
clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
}
-/* This returns the status bits of the device. The return value
+/*
+ * This returns the status bits of the dev
[U-Boot] [PATCH 01/17] powerpc: bsc9132qds: Do not wrap pci_eth_init() with CONFIG_TSEC_ENET
The call to pci_eth_init() should not be wrapped with CONFIG_TSEC_ENET.
Signed-off-by: Bin Meng
---
board/freescale/bsc9132qds/bsc9132qds.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/bsc9132qds/bsc9132qds.c
b/board/freescale/bsc9132qds/bsc9132qds.c
index 586dacc..71a7bb5 100644
--- a/board/freescale/bsc9132qds/bsc9132qds.c
+++ b/board/freescale/bsc9132qds/bsc9132qds.c
@@ -227,9 +227,9 @@ int checkboard(void)
return 0;
}
-#ifdef CONFIG_TSEC_ENET
int board_eth_init(bd_t *bis)
{
+#ifdef CONFIG_TSEC_ENET
struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[4];
int num = 0;
@@ -250,6 +250,7 @@ int board_eth_init(bd_t *bis)
fsl_pq_mdio_init(bis, &mdio_info);
tsec_eth_init(bis, tsec_info, num);
+#endif
#ifdef CONFIG_PCI
pci_eth_init(bis);
@@ -257,7 +258,6 @@ int board_eth_init(bd_t *bis)
return 0;
}
-#endif
#define USBMUX_SEL_MASK0xc0
#define USBMUX_SEL_UART2 0xc0
--
1.8.2.1
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[U-Boot] [PATCH 00/17] arm: ls1021atwr: Convert to use driver model TSEC driver
This series adds driver model ethernet support to the Freescale TSEC ethernet driver and convert ls1021atwr board to use it. Enable the support in the ls1021atwr_nor_defconfig and ls1021atwr_nor_lpuart_defconfig configurations. Bin Meng (17): powerpc: bsc9132qds: Do not wrap pci_eth_init() with CONFIG_TSEC_ENET powerpc: c29xpcie: Do not wrap pci_eth_init() with CONFIG_TSEC_ENET powerpc: mpc8572ds: Do not wrap pci_eth_init() with CONFIG_TSEC_ENET powerpc: mpc8548cds: Do not wrap pci_eth_init() with CONFIG_TSEC_ENET powerpc: p1010rdb: Do not wrap pci_eth_init() with CONFIG_TSEC_ENET arm: ls1021atwr: Do not wrap pci_eth_init() with CONFIG_TSEC_ENET net: tsec: fsl_mdio: Fix several cosmetic issues net: tsec: Move rx_idx and tx_idx to struct tsec_private net: tsec: Move rxbd and txbd to struct tsec_private net: tsec: Adjust orders to avoid forward declaration of tsec_send() net: tsec: Use tsec_private pointer as the parameter for internal routines doc: dt-bindings: Describe Freescale TSEC ethernet controller net: tsec: Add driver model ethernet support net: tsec: Use priv->tbiaddr to initialize TBI PHY address arm: ls102xa: Rewrite the logic of ft_fixup_enet_phy_connect_type() arm: ls1021atwr: Disable CONFIG_E1000 temporarily arm: ls1021atwr: Convert to use driver model TSEC driver arch/arm/cpu/armv7/ls102xa/cpu.c | 2 +- arch/arm/cpu/armv7/ls102xa/fdt.c | 26 +- arch/arm/dts/ls1021a-twr.dts | 20 + arch/arm/dts/ls1021a.dtsi | 18 +- board/freescale/bsc9132qds/bsc9132qds.c | 4 +- board/freescale/c29xpcie/c29xpcie.c | 4 +- board/freescale/ls1021atwr/ls1021atwr.c | 4 +- board/freescale/mpc8548cds/mpc8548cds.c | 4 +- board/freescale/mpc8572ds/mpc8572ds.c | 4 +- board/freescale/p1010rdb/p1010rdb.c | 4 +- configs/ls1021atwr_nor_defconfig | 3 +- configs/ls1021atwr_nor_lpuart_defconfig | 3 +- doc/device-tree-bindings/net/fsl-tsec-phy.txt | 64 +++ drivers/net/fsl_mdio.c| 4 +- drivers/net/tsec.c| 536 ++ include/configs/ls1021atwr.h | 4 + include/fsl_mdio.h| 7 +- include/tsec.h| 69 ++-- 18 files changed, 546 insertions(+), 234 deletions(-) create mode 100644 doc/device-tree-bindings/net/fsl-tsec-phy.txt -- 1.8.2.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/8] Convert lpuart serial driver to driver model
Hi Bhuvanchandra, On Tue, Jan 12, 2016 at 12:28 PM, Bhuvanchandra DV wrote: > - Convert lpuart driver to driver model and remove the legacy code. > - Update Toradex Colibri VF50/VF61 serial support with driver model. > - Update Freescale vf610twr serial support with driver model. > - Update Freescale ls1021atwr serial support with driver model. > - Update Phytec pcm052 serial support with driver model. > - Tested the driver on Toradex Colibri VF50/VF61 hardware. > - Compile checked board files for vf610twr, ls1021atwr and pcm052 > since I don't have access to such hardware at my end. Reviewers > and testers welcome! > > Bhuvanchandra DV (8): > dm: lpuart: Add driver model support for the serial driver > colibri_vf: Update enabling lpuart support with driver model > arm: vf610twr: Add driver model support > vf610twr: Update enabling lpuart with driver model > arm: ls102xa: Add driver model support > ls1021x: Update enabling lpuart with driver model > arm: pcm052: Enable driver model support > pcm052: Update enabling lpuart support with driver model > > arch/arm/include/asm/arch-ls102xa/serial.h | 16 > arch/arm/include/asm/arch-vf610/serial.h | 16 > board/freescale/ls1021atwr/ls1021atwr.c| 15 ++- > board/freescale/vf610twr/vf610twr.c| 13 +++ > board/phytec/pcm052/pcm052.c | 13 +++ > board/toradex/colibri_vf/colibri_vf.c | 13 +++ > configs/ls1021atwr_nor_lpuart_defconfig| 1 + > configs/pcm052_defconfig | 1 + > configs/vf610twr_defconfig | 1 + > configs/vf610twr_nand_defconfig| 1 + > drivers/serial/Kconfig | 6 ++ > drivers/serial/serial_lpuart.c | 148 > +++-- > include/configs/colibri_vf.h | 6 +- > include/configs/ls1021atwr.h | 1 + > include/configs/pcm052.h | 6 +- > include/configs/vf610twr.h | 6 +- > 16 files changed, 180 insertions(+), 83 deletions(-) > create mode 100644 arch/arm/include/asm/arch-ls102xa/serial.h > create mode 100644 arch/arm/include/asm/arch-vf610/serial.h > > -- Please see existing patch series @ http://patchwork.ozlabs.org/patch/561855/. You can drop the ls102xa changes and rebase your patch series on top of that. Thanks! Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 6/8] ls1021x: Update enabling lpuart with driver model
Signed-off-by: Bhuvanchandra DV
---
arch/arm/include/asm/arch-ls102xa/serial.h | 16
board/freescale/ls1021atwr/ls1021atwr.c| 15 ++-
include/configs/ls1021atwr.h | 1 +
3 files changed, 31 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/include/asm/arch-ls102xa/serial.h
diff --git a/arch/arm/include/asm/arch-ls102xa/serial.h
b/arch/arm/include/asm/arch-ls102xa/serial.h
new file mode 100644
index 000..8a99149
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/serial.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2016 Toradex, Inc.
+ *
+ * Author: Bhuvanchandra DV
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _LPUART32_SERIAL_H
+#define _LPUART32_SERIAL_H
+
+struct lpuart_serial_platdata {
+ uint32_t base_addr;
+};
+
+#endif
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c
b/board/freescale/ls1021atwr/ls1021atwr.c
index 8eaff5f..6d3977f 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -5,10 +5,13 @@
*/
#include
+#include
#include
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -31,7 +34,6 @@
#include "../../../drivers/qe/qe.h"
#endif
-
DECLARE_GLOBAL_DATA_PTR;
#define VERSION_MASK 0x00FF
@@ -793,3 +795,14 @@ U_BOOT_CMD(
"\nWARNING: If you aren't familiar with the setting of serdes, don't
try to change anything!\n"
);
#endif
+
+#ifdef CONFIG_FSL_LPUART
+static struct lpuart_serial_platdata lpuart_serial_plat = {
+ .base_addr = LPUART_BASE,
+};
+
+U_BOOT_DEVICE(lpuart_serial) = {
+ .name = "serial_lpuart32",
+ .platdata = &lpuart_serial_plat,
+};
+#endif
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index c12ba3a..896c419 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -266,6 +266,7 @@
* Serial Port
*/
#ifdef CONFIG_LPUART
+#define CONFIG_DM_SERIAL
#define CONFIG_FSL_LPUART
#define CONFIG_LPUART_32B_REG
#else
--
2.7.0
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[U-Boot] [PATCH 3/8] arm: vf610twr: Enable driver model support
Signed-off-by: Bhuvanchandra DV --- configs/vf610twr_defconfig | 1 + configs/vf610twr_nand_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/vf610twr_defconfig b/configs/vf610twr_defconfig index dc8df5c..46b4e00 100644 --- a/configs/vf610twr_defconfig +++ b/configs/vf610twr_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_VF610TWR=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_MMC" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_DM=y CONFIG_NAND_VF610_NFC=y CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_SPI_FLASH=y diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig index 98880f3..d244459 100644 --- a/configs/vf610twr_nand_defconfig +++ b/configs/vf610twr_nand_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_VF610TWR=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_NAND" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_DM=y CONFIG_NAND_VF610_NFC=y CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_SPI_FLASH=y -- 2.7.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/8] colibri_vf: Update enabling lpuart support with driver model
Signed-off-by: Bhuvanchandra DV
---
board/toradex/colibri_vf/colibri_vf.c | 13 +
include/configs/colibri_vf.h | 6 +++---
2 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/board/toradex/colibri_vf/colibri_vf.c
b/board/toradex/colibri_vf/colibri_vf.c
index c65ccb3..76bc51c 100644
--- a/board/toradex/colibri_vf/colibri_vf.c
+++ b/board/toradex/colibri_vf/colibri_vf.c
@@ -8,12 +8,14 @@
*/
#include
+#include
#include
#include
#include
#include
#include
#include
+#include
#include
#include
#include
@@ -586,3 +588,14 @@ int board_usb_phy_mode(int port)
}
}
#endif
+
+#ifdef CONFIG_FSL_LPUART
+static struct lpuart_serial_platdata lpuart_serial_plat = {
+ .base_addr = UART0_BASE,
+};
+
+U_BOOT_DEVICE(lpuart_serial) = {
+ .name = "serial_lpuart",
+ .platdata = &lpuart_serial_plat,
+};
+#endif
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 708c79a..6ecfdb2 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -36,15 +36,15 @@
#define CONFIG_BOARD_EARLY_INIT_F
+/* UART support */
+#define CONFIG_DM_SERIAL
#define CONFIG_FSL_LPUART
-#define LPUART_BASEUART0_BASE
+#define CONFIG_BAUDRATE115200
/* Allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_VERSION_VARIABLE
-#define CONFIG_SYS_UART_PORT (0)
-#define CONFIG_BAUDRATE115200
#define CONFIG_CMD_ASKENV
/* NAND support */
--
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[U-Boot] [PATCH 5/8] arm: ls102xa: Enable driver model support
Signed-off-by: Bhuvanchandra DV --- configs/ls1021atwr_nor_lpuart_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index d7afca9..d52181b 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -2,5 +2,6 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y CONFIG_SYS_EXTRA_OPTIONS="LPUART" # CONFIG_CMD_SETEXPR is not set +CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y -- 2.7.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 8/8] pcm052: Update enabling lpuart support with driver model
Signed-off-by: Bhuvanchandra DV
---
board/phytec/pcm052/pcm052.c | 13 +
include/configs/pcm052.h | 6 +++---
2 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c
index e4f61e1..3f2ed38 100644
--- a/board/phytec/pcm052/pcm052.c
+++ b/board/phytec/pcm052/pcm052.c
@@ -5,12 +5,14 @@
*/
#include
+#include
#include
#include
#include
#include
#include
#include
+#include
#include
#include
#include
@@ -513,3 +515,14 @@ int checkboard(void)
return 0;
}
+
+#ifdef CONFIG_FSL_LPUART
+static struct lpuart_serial_platdata lpuart_serial_plat = {
+ .base_addr = UART1_BASE,
+};
+
+U_BOOT_DEVICE(lpuart_serial) = {
+ .name = "serial_lpuart",
+ .platdata = &lpuart_serial_plat,
+};
+#endif
diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
index b851bba..bd3992f 100644
--- a/include/configs/pcm052.h
+++ b/include/configs/pcm052.h
@@ -27,13 +27,13 @@
#define CONFIG_BOARD_EARLY_INIT_F
+/* UART support */
+#define CONFIG_DM_SERIAL
#define CONFIG_FSL_LPUART
-#define LPUART_BASEUART1_BASE
+#define CONFIG_BAUDRATE115200
/* Allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_UART_PORT (1)
-#define CONFIG_BAUDRATE115200
#undef CONFIG_CMD_IMLS
--
2.7.0
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[U-Boot] [PATCH 4/8] vf610twr: Update enabling lpuart with driver model
Signed-off-by: Bhuvanchandra DV
---
board/freescale/vf610twr/vf610twr.c | 13 +
include/configs/vf610twr.h | 6 +++---
2 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/board/freescale/vf610twr/vf610twr.c
b/board/freescale/vf610twr/vf610twr.c
index 37b241d..3ca0094 100644
--- a/board/freescale/vf610twr/vf610twr.c
+++ b/board/freescale/vf610twr/vf610twr.c
@@ -5,12 +5,14 @@
*/
#include
+#include
#include
#include
#include
#include
#include
#include
+#include
#include
#include
#include
@@ -385,3 +387,14 @@ int checkboard(void)
return 0;
}
+
+#ifdef CONFIG_FSL_LPUART
+static struct lpuart_serial_platdata lpuart_serial_plat = {
+ .base_addr = UART1_BASE,
+};
+
+U_BOOT_DEVICE(lpuart_serial) = {
+ .name = "serial_lpuart",
+ .platdata = &lpuart_serial_plat,
+};
+#endif
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index 34df6f0..fd898c0 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -34,13 +34,13 @@
#define CONFIG_BOARD_EARLY_INIT_F
+/* UART support */
+#define CONFIG_DM_SERIAL
#define CONFIG_FSL_LPUART
-#define LPUART_BASEUART1_BASE
+#define CONFIG_BAUDRATE115200
/* Allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_UART_PORT (1)
-#define CONFIG_BAUDRATE115200
/* NAND support */
#define CONFIG_CMD_NAND
--
2.7.0
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[U-Boot] [PATCH 1/8] dm: lpuart: Add driver model support for the serial driver
Convert lpuart driver to driver model and remove the legacy code.
Signed-off-by: Bhuvanchandra DV
---
arch/arm/include/asm/arch-vf610/serial.h | 16
drivers/serial/Kconfig | 6 ++
drivers/serial/serial_lpuart.c | 148 ---
3 files changed, 97 insertions(+), 73 deletions(-)
create mode 100644 arch/arm/include/asm/arch-vf610/serial.h
diff --git a/arch/arm/include/asm/arch-vf610/serial.h
b/arch/arm/include/asm/arch-vf610/serial.h
new file mode 100644
index 000..e9ab552
--- /dev/null
+++ b/arch/arm/include/asm/arch-vf610/serial.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2016 Toradex, Inc.
+ *
+ * Author: Bhuvanchandra DV
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _LPUART_SERIAL_H
+#define _LPUART_SERIAL_H
+
+struct lpuart_serial_platdata {
+ uint32_t base_addr;
+};
+
+#endif
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 1fc287e..56a06a7 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -223,4 +223,10 @@ config UNIPHIER_SERIAL
If you have a UniPhier based board and want to use the on-chip
serial ports, say Y to this option. If unsure, say N.
+config FSL_LPUART
+ bool "Freescale lpuart serial port support"
+ depends on DM_SERIAL
+ help
+ Support for the on-chip lpuart on some Freescale SOCs.
+
endmenu
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index 63fc388..4724f42 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -5,12 +5,14 @@
*/
#include
+#include
#include
#include
#include
#include
#include
#include
+#include
#define US1_TDRE(1 << 7)
#define US1_RDRF(1 << 5)
@@ -47,26 +49,35 @@
DECLARE_GLOBAL_DATA_PTR;
-struct lpuart_fsl *base = (struct lpuart_fsl *)LPUART_BASE;
+struct lpuart_serial_priv {
+ struct lpuart_fsl *lpuart_base;
+};
#ifndef CONFIG_LPUART_32B_REG
-static void lpuart_serial_setbrg(void)
+int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
{
+ struct lpuart_serial_priv *priv = dev_get_priv(dev);
+ struct lpuart_fsl *base = priv->lpuart_base;
u32 clk = mxc_get_clock(MXC_UART_CLK);
u16 sbr;
if (!gd->baudrate)
- gd->baudrate = CONFIG_BAUDRATE;
+ gd->baudrate = baudrate;
sbr = (u16)(clk / (16 * gd->baudrate));
/* place adjustment later - n/32 BRFA */
__raw_writeb(sbr >> 8, &base->ubdh);
__raw_writeb(sbr & 0xff, &base->ubdl);
+
+ return 0;
}
-static int lpuart_serial_getc(void)
+static int lpuart_serial_getc(struct udevice *dev)
{
+ struct lpuart_serial_priv *priv = dev_get_priv(dev);
+ struct lpuart_fsl *base = priv->lpuart_base;
+
while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
WATCHDOG_RESET();
@@ -75,8 +86,11 @@ static int lpuart_serial_getc(void)
return __raw_readb(&base->ud);
}
-static void lpuart_serial_putc(const char c)
+static int lpuart_serial_putc(struct udevice *dev, const char c)
{
+ struct lpuart_serial_priv *priv = dev_get_priv(dev);
+ struct lpuart_fsl *base = priv->lpuart_base;
+
if (c == '\n')
serial_putc('\r');
@@ -84,24 +98,15 @@ static void lpuart_serial_putc(const char c)
WATCHDOG_RESET();
__raw_writeb(c, &base->ud);
-}
-
-/*
- * Test whether a character is in the RX buffer
- */
-static int lpuart_serial_tstc(void)
-{
- if (__raw_readb(&base->urcfifo) == 0)
- return 0;
- return 1;
+ return 0;
}
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*/
-static int lpuart_serial_init(void)
+static int lpuart_serial_init(struct lpuart_fsl *base)
{
u8 ctrl;
@@ -118,29 +123,15 @@ static int lpuart_serial_init(void)
__raw_writeb(0x0, &base->utwfifo);
__raw_writeb(0x1, &base->urwfifo);
__raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
-
- /* provide data bits, parity, stop bit, etc */
-
- serial_setbrg();
-
__raw_writeb(UC2_RE | UC2_TE, &base->uc2);
return 0;
}
-
-static struct serial_device lpuart_serial_drv = {
- .name = "lpuart_serial",
- .start = lpuart_serial_init,
- .stop = NULL,
- .setbrg = lpuart_serial_setbrg,
- .putc = lpuart_serial_putc,
- .puts = default_serial_puts,
- .getc = lpuart_serial_getc,
- .tstc = lpuart_serial_tstc,
-};
-#else
-static void lpuart32_serial_setbrg(void)
+#else /* CONFIG_LPUART_32B_REG */
+int lpuart32_serial_setbrg(struct udevice *dev, int baudrate)
{
+ struct lpuart_serial_priv *priv = dev_get_priv(dev);
+ struct lpuart_fsl *base = priv->lpuart_base;
u32 clk = CONFIG_SYS_CLK_FREQ;
u32 sbr;
@@ -151,10 +142,14 @@ static void lpuart32_serial
[U-Boot] [PATCH 7/8] arm: pcm052: Enable driver model support
Signed-off-by: Bhuvanchandra DV --- configs/pcm052_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig index 9125645..12fdc0c 100644 --- a/configs/pcm052_defconfig +++ b/configs/pcm052_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_PCM052=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg,ENV_IS_IN_NAND" +CONFIG_DM=y CONFIG_NAND_VF610_NFC=y CONFIG_SYS_NAND_BUSWIDTH_16BIT=y -- 2.7.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/8] Convert lpuart serial driver to driver model
- Convert lpuart driver to driver model and remove the legacy code. - Update Toradex Colibri VF50/VF61 serial support with driver model. - Update Freescale vf610twr serial support with driver model. - Update Freescale ls1021atwr serial support with driver model. - Update Phytec pcm052 serial support with driver model. - Tested the driver on Toradex Colibri VF50/VF61 hardware. - Compile checked board files for vf610twr, ls1021atwr and pcm052 since I don't have access to such hardware at my end. Reviewers and testers welcome! Bhuvanchandra DV (8): dm: lpuart: Add driver model support for the serial driver colibri_vf: Update enabling lpuart support with driver model arm: vf610twr: Add driver model support vf610twr: Update enabling lpuart with driver model arm: ls102xa: Add driver model support ls1021x: Update enabling lpuart with driver model arm: pcm052: Enable driver model support pcm052: Update enabling lpuart support with driver model arch/arm/include/asm/arch-ls102xa/serial.h | 16 arch/arm/include/asm/arch-vf610/serial.h | 16 board/freescale/ls1021atwr/ls1021atwr.c| 15 ++- board/freescale/vf610twr/vf610twr.c| 13 +++ board/phytec/pcm052/pcm052.c | 13 +++ board/toradex/colibri_vf/colibri_vf.c | 13 +++ configs/ls1021atwr_nor_lpuart_defconfig| 1 + configs/pcm052_defconfig | 1 + configs/vf610twr_defconfig | 1 + configs/vf610twr_nand_defconfig| 1 + drivers/serial/Kconfig | 6 ++ drivers/serial/serial_lpuart.c | 148 +++-- include/configs/colibri_vf.h | 6 +- include/configs/ls1021atwr.h | 1 + include/configs/pcm052.h | 6 +- include/configs/vf610twr.h | 6 +- 16 files changed, 180 insertions(+), 83 deletions(-) create mode 100644 arch/arm/include/asm/arch-ls102xa/serial.h create mode 100644 arch/arm/include/asm/arch-vf610/serial.h -- 2.7.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 03/13] drivers: pinctrl: Add pinctrl driver for Microchip PIC32 microcontroller
On 01/11/2016 10:28 PM, Simon Glass wrote:
> Hi,
>
> On 7 January 2016 at 23:46, Purna Chandra Mandal
> wrote:
>> On 01/08/2016 09:04 AM, Simon Glass wrote:
>>
>>> Hi Purna,
>>>
>>> On 4 January 2016 at 07:00, Purna Chandra Mandal
>>> wrote:
Signed-off-by: Purna Chandra Mandal
>>> Please add a commit message.
>> Ack. will add.
>>
---
Changes in v2:
- add routine to configure pin properties
drivers/pinctrl/Kconfig | 6 +
drivers/pinctrl/Makefile| 1 +
drivers/pinctrl/pinctrl_pic32.c | 284
3 files changed, 291 insertions(+)
create mode 100644 drivers/pinctrl/pinctrl_pic32.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 57e6142..a4acaf3 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -131,6 +131,12 @@ config PINCTRL_SANDBOX
actually does nothing but print debug messages when pinctrl
operations are invoked.
+config PIC32_PINCTRL
+ bool "Microchip PIC32 pin-control driver"
+ depends on DM && MACH_PIC32
+ help
+ Support pin multiplexing control on Microchip PIC32 SoCs.
>>> Please add a bit more detail here. What type of functions use pinmux?
>>> Does the pinmux work on a per-pin or per-function basis, or use
>>> groups? Try to add some useful info.
>> Ack. Will add more information here.
>> In PIC32 pin controller is combination of gpio-controller, pin mux and pin
>> config.
>> Remappable peripherals are assigned pins through per-pin based muxing logic.
>> And pin configuration are performed through port registers which are
>> shared along with gpio controller.
>>
+
endif
source "drivers/pinctrl/uniphier/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 70d25dc..b4f4650 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
obj-$(CONFIG_ARCH_UNIPHIER)+= uniphier/
+obj-$(CONFIG_PIC32_PINCTRL)+= pinctrl_pic32.o
diff --git a/drivers/pinctrl/pinctrl_pic32.c
b/drivers/pinctrl/pinctrl_pic32.c
new file mode 100644
index 000..043f589
--- /dev/null
+++ b/drivers/pinctrl/pinctrl_pic32.c
@@ -0,0 +1,284 @@
+/*
+ * Pinctrl driver for Microchip PIC32 SoCs
+ * Copyright (c) 2015 Microchip Technology Inc.
+ * Written by Purna Chandra Mandal
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Peripheral PORTA-PORTK / PORT0-PORT9 */
+enum {
+ PIC32_PORT_A = 0,
+ PIC32_PORT_B = 1,
+ PIC32_PORT_C = 2,
+ PIC32_PORT_D = 3,
+ PIC32_PORT_E = 4,
+ PIC32_PORT_F = 5,
+ PIC32_PORT_G = 6,
+ PIC32_PORT_H = 7,
+ PIC32_PORT_J = 8, /* no PORT_I */
+ PIC32_PORT_K = 9,
+ PIC32_PORT_MAX
+};
+
+/* Input pinmux reg offset */
+#define U1RXR 0x0068
+#define U2RXR 0x0070
+#define SDI1R 0x009c
+#define SDI2R 0x00a8
+
+/* Output pinmux reg offset */
+#define PPS_OUT(__port, __pin) (((__port) * 16 + (__pin)) << 2)
+
+/* Port config/control registers */
+struct pic32_reg_port {
+ struct pic32_reg_atomic ansel;
>>> What is pic32_reg_atomic? Can we use u32 instead?
>> For fast and atomic manipulation of registers h/w designers provided a
>> set of interfaces/registers {raw, clear, set, invert} for some of target
>> register.
>> 'struct pic32_reg_atomic' refers to this set as defined in [patch 01/13].
> OK, well it's up to you.
>
+ struct pic32_reg_atomic tris;
+ struct pic32_reg_atomic port;
+ struct pic32_reg_atomic lat;
+ struct pic32_reg_atomic odc;
+ struct pic32_reg_atomic cnpu;
+ struct pic32_reg_atomic cnpd;
+ struct pic32_reg_atomic cncon;
+};
+
+#define PIN_CONFIG_PIC32_DIGITAL (PIN_CONFIG_END + 1)
+#define PIN_CONFIG_PIC32_ANALOG(PIN_CONFIG_END + 2)
+
+struct pic32_pin_config {
+ u16 port;
+ u16 pin;
+ u32 flags;
>>> comments on this structure and members
>> ack. Will add.
>>
+};
+
+#define PIN_CONFIG(_prt, _pin, _cfg) \
+ {.port = (_prt), .pin = (_pin), .flags = (_cfg), }
+
+enum {
+ PERIPH_ID_UART1,
+ PERIPH_ID_UART2,
+ PERIPH_ID_ETH,
+ PERIPH_ID_USB,
+ PERIPH_ID_SDHCI,
+ PERIPH_ID_I2C1,
+ P
Re: [U-Boot] [PATCH v2 05/13] drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.
On 01/11/2016 10:27 PM, Simon Glass wrote: > Hi, > > On 4 January 2016 at 07:01, Purna Chandra Mandal > wrote: >> Signed-off-by: Paul Thacker >> Signed-off-by: Purna Chandra Mandal > Please add a commit message. Agreed, Will add. >> --- >> >> Changes in v2: >> - move ddr2 initialization from board/microchip/ to drivers/ddr/microchip >> >> arch/mips/mach-pic32/include/mach/ddr.h | 32 >> drivers/Makefile| 1 + >> drivers/ddr/microchip/Makefile | 6 + >> drivers/ddr/microchip/ddr2.c| 277 >> >> drivers/ddr/microchip/ddr2_regs.h | 151 + >> drivers/ddr/microchip/ddr2_timing.h | 65 >> 6 files changed, 532 insertions(+) >> create mode 100644 arch/mips/mach-pic32/include/mach/ddr.h >> create mode 100644 drivers/ddr/microchip/Makefile >> create mode 100644 drivers/ddr/microchip/ddr2.c >> create mode 100644 drivers/ddr/microchip/ddr2_regs.h >> create mode 100644 drivers/ddr/microchip/ddr2_timing.h >> > Regards, > Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 02/13] drivers: clk: Add clock driver for Microchip PIC32 Microcontroller.
On 01/11/2016 10:27 PM, Simon Glass wrote:
> Hi,
>
> On 4 January 2016 at 07:00, Purna Chandra Mandal
> wrote:
>> Signed-off-by: Purna Chandra Mandal
>>
> Commit message please.
Ack. Will add.
>> ---
>>
>> Changes in v2:
>> - add get clock rate for mpll clock
>>
>> .../clock/microchip,pic32-clock.txt| 28 ++
>> drivers/clk/Makefile | 1 +
>> drivers/clk/clk-pic32.c| 427
>> +
>> include/dt-bindings/clock/microchip,clock.h| 29 ++
>> 4 files changed, 485 insertions(+)
>> create mode 100644 doc/device-tree-bindings/clock/microchip,pic32-clock.txt
>> create mode 100644 drivers/clk/clk-pic32.c
>> create mode 100644 include/dt-bindings/clock/microchip,clock.h
>>
> Reviewed-by: Simon Glass
>
> nits below
>
>> diff --git a/doc/device-tree-bindings/clock/microchip,pic32-clock.txt
>> b/doc/device-tree-bindings/clock/microchip,pic32-clock.txt
>> new file mode 100644
>> index 000..d02b9d7
>> --- /dev/null
>> +++ b/doc/device-tree-bindings/clock/microchip,pic32-clock.txt
>> @@ -0,0 +1,28 @@
>> +* Microchip PIC32 Clock and Oscillator
>> +
>> +The PIC32 clock controller generates and supplies clock to various
>> +controllers within the SoC.
>> +
>> +Required Properties:
>> +
>> +- compatible: should be "microchip,pic32mzda_clk"
>> +- reg: physical base address of the controller and length of memory mapped
>> + region.
>> +- #clock-cells: should be 1.
>> +
>> +Example: Clock controller node:
>> +
>> + clock: clk@1f801200 {
>> + compatible = "microchip,pic32mzda_clk";
>> + reg = <0xbf801200 0x1000>;
>> + };
>> +
>> +Example: UART controller node that consumes the clock generated by the clock
>> + controller:
>> +
>> + uart1: serial@1f822000 {
>> + compatible = "microchip,pic32mzda-uart";
>> + reg = <0xbf822000 0x50>;
>> + interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&clock PB2CLK>;
>> + };
>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
>> index 4a6a4a8..3c84e08 100644
>> --- a/drivers/clk/Makefile
>> +++ b/drivers/clk/Makefile
>> @@ -9,3 +9,4 @@ obj-$(CONFIG_CLK) += clk-uclass.o
>> obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
>> obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
>> obj-$(CONFIG_SANDBOX) += clk_sandbox.o
>> +obj-$(CONFIG_MACH_PIC32) += clk-pic32.o
> As the other review mentions, should use underscore in filenames
> unless it is a uclass.
Agreed.
>> diff --git a/drivers/clk/clk-pic32.c b/drivers/clk/clk-pic32.c
>> new file mode 100644
>> index 000..70aac05
>> --- /dev/null
>> +++ b/drivers/clk/clk-pic32.c
>> @@ -0,0 +1,427 @@
>> +/*
>> + * Copyright (C) 2015 Purna Chandra Mandal
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + *
>> + */
>> +
>> +#include
>> +#include
>> +#include
> nit: clk.h should go above dm.h, below common.h
ack. If you could share *specific* reason behind this order (like dependencies)?
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
> Regards,
> Simon
___
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Re: [U-Boot] [PATCH v2 02/13] drivers: clk: Add clock driver for Microchip PIC32 Microcontroller.
On 01/11/2016 09:46 PM, Daniel Schwierzeck wrote:
> Am Montag, den 04.01.2016, 19:30 +0530 schrieb Purna Chandra Mandal:
>> Signed-off-by: Purna Chandra Mandal
>>
>> ---
>>
>> Changes in v2:
>> - add get clock rate for mpll clock
>>
>> .../clock/microchip,pic32-clock.txt| 28 ++
>> drivers/clk/Makefile | 1 +
>> drivers/clk/clk-pic32.c| 427
>> +
>> include/dt-bindings/clock/microchip,clock.h| 29 ++
>> 4 files changed, 485 insertions(+)
>> create mode 100644 doc/device-tree-bindings/clock/microchip,pic32
>> -clock.txt
>> create mode 100644 drivers/clk/clk-pic32.c
>> create mode 100644 include/dt-bindings/clock/microchip,clock.h
>>
>> diff --git a/doc/device-tree-bindings/clock/microchip,pic32-clock.txt
>> b/doc/device-tree-bindings/clock/microchip,pic32-clock.txt
>> new file mode 100644
>> index 000..d02b9d7
>> --- /dev/null
>> +++ b/doc/device-tree-bindings/clock/microchip,pic32-clock.txt
>> @@ -0,0 +1,28 @@
>> +* Microchip PIC32 Clock and Oscillator
>> +
>> +The PIC32 clock controller generates and supplies clock to various
>> +controllers within the SoC.
>> +
>> +Required Properties:
>> +
>> +- compatible: should be "microchip,pic32mzda_clk"
>> +- reg: physical base address of the controller and length of memory
>> mapped
>> + region.
>> +- #clock-cells: should be 1.
>> +
>> +Example: Clock controller node:
>> +
>> +clock: clk@1f801200 {
>> +compatible = "microchip,pic32mzda_clk";
>> +reg = <0xbf801200 0x1000>;
>> +};
>> +
>> +Example: UART controller node that consumes the clock generated by
>> the clock
>> + controller:
>> +
>> +uart1: serial@1f822000 {
>> +compatible = "microchip,pic32mzda-uart";
>> +reg = <0xbf822000 0x50>;
>> +interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
>> +clocks = <&clock PB2CLK>;
>> +};
>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
>> index 4a6a4a8..3c84e08 100644
>> --- a/drivers/clk/Makefile
>> +++ b/drivers/clk/Makefile
>> @@ -9,3 +9,4 @@ obj-$(CONFIG_CLK) += clk-uclass.o
>> obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
>> obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
>> obj-$(CONFIG_SANDBOX) += clk_sandbox.o
>> +obj-$(CONFIG_MACH_PIC32) += clk-pic32.o
>> diff --git a/drivers/clk/clk-pic32.c b/drivers/clk/clk-pic32.c
>> new file mode 100644
>> index 000..70aac05
>> --- /dev/null
>> +++ b/drivers/clk/clk-pic32.c
>> @@ -0,0 +1,427 @@
>> +/*
>> + * Copyright (C) 2015 Purna Chandra Mandal <
>> purna.man...@microchip.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + *
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
> I can't find wait_bit.h in mainline. Is there an unmerged patch which
> adds this file and you depend on? Could you point me to it? Thanks.
Yes, this is not on mainline. Based on review (from Marek Vesut)
to use wait_for_bit() for unbounded loops I have pulled the
under-review patch from [1].
[1] http://patchwork.ozlabs.org/patch/561185/
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +/* Primary oscillator */
>> +#define SYS_POSC_CLK_HZ 2400
>> +
>> +/* FRC clk rate */
>> +#define SYS_FRC_CLK_HZ 800
>> +
>> +/* Clock registers */
>> +#define OSCCON 0x
>> +#define OSCTUNE 0x0010
>> +#define SPLLCON 0x0020
>> +#define REFO1CON0x0080
>> +#define REFO1TRIM 0x0090
>> +#define PB1DIV 0x0140
>> +
>> +/* PLL */
>> +#define ICLK_MASK 0x0080
>> +#define PLLIDIV_MASK0x0007
>> +#define PLLODIV_MASK0x0007
>> +#define CUROSC_MASK 0x0007
>> +#define PLLMUL_MASK 0x007F
>> +#define FRCDIV_MASK 0x0007
>> +
>> +/* PBCLK */
>> +#define PBDIV_MASK 0x0007
>> +
>> +/* SYSCLK MUX */
>> +#define SCLK_SRC_FRC1 0
>> +#define SCLK_SRC_SPLL 1
>> +#define SCLK_SRC_POSC 2
>> +#define SCLK_SRC_FRC2 7
>> +
>> +/* Reference Oscillator Control Reg fields */
>> +#define REFO_SEL_MASK 0x0f
>> +#define REFO_SEL_SHIFT 0
>> +#define REFO_ACTIVE BIT(8)
>> +#define REFO_DIVSW_EN BIT(9)
>> +#define REFO_OE BIT(12)
>> +#define REFO_ON BIT(15)
>> +#define REFO_DIV_SHIFT 16
>> +#define REFO_DIV_MASK 0x7fff
>> +
>> +/* Reference Oscillator Trim Register Fields */
>> +#define REFO_TRIM_REG 0x10
>> +#define REFO_TRIM_MASK 0x1ff
>> +#define REFO_TRIM_SHIFT 23
>> +#define REFO_TRIM_MAX 511
>> +
>> +#define ROCLK_SRC_SCLK 0x0
>> +#define ROCLK_SRC_SPLL 0x7
>> +#define ROCLK_SRC_ROCLKI0x8
>> +
>> +/* Memory PLL */
>> +#define MPLL_IDIV 0x03
>> +#define MPLL_MULT 0x32
>> +#define MPLL_ODIV1 0x02
>> +#define MPLL_ODIV2 0x01
>> +#define MPLL_VREG_RDY BIT(23)
>> +#define MPLL_RDYBIT(31)
>> +#define M
Re: [U-Boot] [PATCH v6 8/8] x86: qemu: add documentaion for the fw_cfg interface
On Thu, Jan 7, 2016 at 5:32 PM, Miao Yan wrote: > Document the usage of 'qfw' command > > Signed-off-by: Miao Yan > Reviewed-by: Simon Glass > Reviewed-by: Bin Meng > --- applied to u-boot-x86/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 7/8] x86: qemu: remove cpu node in device tree
On Thu, Jan 7, 2016 at 5:32 PM, Miao Yan wrote: > Remove 'cpu' node in device tree for QEMU targets, and let U-Boot detect > and fix up those information at runtime. > > Signed-off-by: Miao Yan > Reviewed-by: Simon Glass > Reviewed-by: Bin Meng > --- applied to u-boot-x86/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 6/8] x86: qemu: fix cpu device in smp boot
On Thu, Jan 7, 2016 at 5:32 PM, Miao Yan wrote: > Currently, when booting with more that one CPU enabled, U-Boot scans > 'cpu' node in device tree and calculates CPU number. This does not scale > well as changing CPU number also requires modifying .dts and re-compiling > U-Boot. > > This patch uses fw_cfg interface provided by QEMU to detect online CPU > number at runtime, and dynamically adds 'cpu' device to U-Boot's driver > model. > > Signed-off-by: Miao Yan > Reviewed-by: Simon Glass > Reviewed-by: Bin Meng > Tested-by: Bin Meng > --- applied to u-boot-x86/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 2/8] x86: qemu: add fw_cfg support
On Tue, Jan 12, 2016 at 11:47 AM, Bin Meng wrote: > On Thu, Jan 7, 2016 at 5:32 PM, Miao Yan wrote: >> The QEMU fw_cfg interface allows the guest to retrieve various data >> information from QEMU. For example, APCI/SMBios tables, number of online >> cpus, kernel data and command line, etc. >> >> This patch adds support for QEMU fw_cfg interface. >> >> Signed-off-by: Miao Yan >> Reviewed-by: Simon Glass >> Reviewed-by: Bin Meng >> --- >> Changes in v6: >> - fix oneline comment >> - do not update bootargs when kernel cmdline only contains '\0' >> >> arch/x86/cpu/qemu/Makefile| 2 +- >> arch/x86/cpu/qemu/fw_cfg.c| 283 >> ++ >> arch/x86/cpu/qemu/qemu.c | 3 + >> arch/x86/include/asm/fw_cfg.h | 93 ++ >> 4 files changed, 380 insertions(+), 1 deletion(-) >> create mode 100644 arch/x86/cpu/qemu/fw_cfg.c >> create mode 100644 arch/x86/include/asm/fw_cfg.h >> > > Tested-by: Bin Meng applied to u-boot-x86/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 4/8] x86: fix a typo in function name
On Thu, Jan 7, 2016 at 5:32 PM, Miao Yan wrote: > Rename 'find_cpu_by_apid_id' to 'find_cpu_by_apic_id'. This should be a > typo. > > Signed-off-by: Miao Yan > Reviewed-by: Simon Glass > Reviewed-by: Bin Meng > --- applied to u-boot-x86/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 3/8] x86: qemu: add a cpu uclass driver for qemu target
On Tue, Jan 12, 2016 at 11:48 AM, Bin Meng wrote: > On Thu, Jan 7, 2016 at 5:32 PM, Miao Yan wrote: >> Add a cpu uclass driver for qemu. Previously, the qemu target gets cpu >> number from board dts files, which are manually created at compile time. >> This does not scale when more cpus are assigned to guest as the dts files >> must be modified as well. >> >> This patch adds a cpu uclass driver for qemu targets to directly read >> online cpu number from firmware. >> >> Signed-off-by: Miao Yan >> Reviewed-by: Bin Meng >> Reviewed-by: Simon Glass >> --- >> arch/x86/cpu/qemu/Makefile | 2 +- >> arch/x86/cpu/qemu/cpu.c | 57 >> >> arch/x86/dts/qemu-x86_i440fx.dts | 4 +-- >> arch/x86/dts/qemu-x86_q35.dts| 4 +-- >> 4 files changed, 62 insertions(+), 5 deletions(-) >> create mode 100644 arch/x86/cpu/qemu/cpu.c >> > > Tested-by: Bin Meng applied to u-boot-x86/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 5/8] x86: use actual CPU number for allocating memory
On Tue, Jan 12, 2016 at 11:48 AM, Bin Meng wrote: > On Thu, Jan 7, 2016 at 5:32 PM, Miao Yan wrote: >> Use actual CPU number, instead of maximum cpu configured, to allocate >> stack memory in 'load_sipi_vector' >> >> Signed-off-by: Miao Yan >> Reviewed-by: Simon Glass >> Reviewed-by: Bin Meng >> --- >> arch/x86/cpu/mp_init.c | 6 +++--- >> 1 file changed, 3 insertions(+), 3 deletions(-) >> > > Tested-by: Bin Meng applied to u-boot-x86/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 1/8] x86: adjust ramdisk load address
On Thu, Jan 7, 2016 at 5:31 PM, Miao Yan wrote: > By default, ramdisk load address is defined to 0200 in env string. > When loading bzImage to 0100 (default address), there's a chance that > the ramdisk header would be overwritten by the kernel. Thus increase the > gap and make ramdisk load at 0400 by default and also this patch > introduces a new configuration item CONFIG_RAMDISK_ADDR for this purpose > > Signed-off-by: Miao Yan > Reviewed-by: Bin Meng > Reviewed-by: Simon Glass > --- applied to u-boot-x86/next, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 0/8] x86: qemu: add fw_cfg interface support for qemu-x86 targets
Hi Miao, On Tue, Jan 12, 2016 at 10:04 AM, Miao Yan wrote: > Hi Bin, > > 2016-01-07 17:31 GMT+08:00 Miao Yan : >> The fw_cfg interface provided by QEMU allow guests to retrieve various >> information >> about the system, e.g. cpu number, variaous firmware data, kernel setup, >> etc. The >> fw_cfg interface can be accessed through 3 IO ports (on x86), using x86 >> in/out >> instructions. >> >> - 0x510: select configuration items to access >> - 0x511: reading this port will return data selected in 0x510 >> - 0x514: this can be used to detect if DMA interface is available >> >> If fw_cfg DMA interface is available, it can be used to accelerate >> accesses. >> >> This patchset adds the following supports for qemu-x86 targets: >> >> + the fw_cfg driver itself >> >> + add a U-Boot command 'fw' to support direct accessing kernel informtion >> from fw_cfg interface, this saves the time of loading them from hard >> disk or >> network again, through emulated devices. >> >> + use fw_cfg to get cpu number at runtime, so smp boot no longer relies on >> the cpu node hard-coded in dts files. >> >> Changes in v6: >> - fix oneline comment >> - do not update bootargs when kernel cmdline only contains '\0' >> >> Miao Yan (8): >> x86: adjust ramdisk load address >> x86: qemu: add fw_cfg support >> x86: qemu: add a cpu uclass driver for qemu target >> x86: fix a typo in function name >> x86: use actual CPU number for allocating memory >> x86: qemu: fix cpu device in smp boot >> x86: qemu: remove cpu node in device tree >> x86: qemu: add documentaion for the fw_cfg interface >> >> arch/x86/cpu/mp_init.c | 84 +++- >> arch/x86/cpu/qemu/Makefile | 2 +- >> arch/x86/cpu/qemu/cpu.c | 46 +++ >> arch/x86/cpu/qemu/fw_cfg.c | 283 >> +++ >> arch/x86/cpu/qemu/qemu.c | 3 + >> arch/x86/dts/qemu-x86_i440fx.dts | 9 +- >> arch/x86/dts/qemu-x86_q35.dts| 9 +- >> arch/x86/include/asm/fw_cfg.h| 93 + >> doc/README.x86 | 34 - >> include/configs/x86-common.h | 3 +- >> 10 files changed, 539 insertions(+), 27 deletions(-) >> create mode 100644 arch/x86/cpu/qemu/cpu.c >> create mode 100644 arch/x86/cpu/qemu/fw_cfg.c >> create mode 100644 arch/x86/include/asm/fw_cfg.h >> >> -- >> 1.9.1 >> > > Is v6 OK for integration ? Thanks. Yes, will be applied soon. Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 5/8] x86: use actual CPU number for allocating memory
On Thu, Jan 7, 2016 at 5:32 PM, Miao Yan wrote: > Use actual CPU number, instead of maximum cpu configured, to allocate > stack memory in 'load_sipi_vector' > > Signed-off-by: Miao Yan > Reviewed-by: Simon Glass > Reviewed-by: Bin Meng > --- > arch/x86/cpu/mp_init.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > Tested-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 3/8] x86: qemu: add a cpu uclass driver for qemu target
On Thu, Jan 7, 2016 at 5:32 PM, Miao Yan wrote: > Add a cpu uclass driver for qemu. Previously, the qemu target gets cpu > number from board dts files, which are manually created at compile time. > This does not scale when more cpus are assigned to guest as the dts files > must be modified as well. > > This patch adds a cpu uclass driver for qemu targets to directly read > online cpu number from firmware. > > Signed-off-by: Miao Yan > Reviewed-by: Bin Meng > Reviewed-by: Simon Glass > --- > arch/x86/cpu/qemu/Makefile | 2 +- > arch/x86/cpu/qemu/cpu.c | 57 > > arch/x86/dts/qemu-x86_i440fx.dts | 4 +-- > arch/x86/dts/qemu-x86_q35.dts| 4 +-- > 4 files changed, 62 insertions(+), 5 deletions(-) > create mode 100644 arch/x86/cpu/qemu/cpu.c > Tested-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 2/8] x86: qemu: add fw_cfg support
On Thu, Jan 7, 2016 at 5:32 PM, Miao Yan wrote: > The QEMU fw_cfg interface allows the guest to retrieve various data > information from QEMU. For example, APCI/SMBios tables, number of online > cpus, kernel data and command line, etc. > > This patch adds support for QEMU fw_cfg interface. > > Signed-off-by: Miao Yan > Reviewed-by: Simon Glass > Reviewed-by: Bin Meng > --- > Changes in v6: > - fix oneline comment > - do not update bootargs when kernel cmdline only contains '\0' > > arch/x86/cpu/qemu/Makefile| 2 +- > arch/x86/cpu/qemu/fw_cfg.c| 283 > ++ > arch/x86/cpu/qemu/qemu.c | 3 + > arch/x86/include/asm/fw_cfg.h | 93 ++ > 4 files changed, 380 insertions(+), 1 deletion(-) > create mode 100644 arch/x86/cpu/qemu/fw_cfg.c > create mode 100644 arch/x86/include/asm/fw_cfg.h > Tested-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch V3 3/3] armv8/ls1043aqds: add QSPI boot support
> -Original Message-
> From: Scott Wood [mailto:o...@buserror.net]
> Sent: Tuesday, January 12, 2016 1:47 AM
> To: Qianyu Gong ; u-boot@lists.denx.de
> Cc: b07...@freescale.com; b48...@freescale.com;
> wenbin.s...@freescale.com; Mingkai Hu
> Subject: Re: [U-Boot] [Patch V3 3/3] armv8/ls1043aqds: add QSPI boot support
>
> On Mon, 2016-01-11 at 10:17 +0800, Gong Qianyu wrote:
> > diff --git a/board/freescale/ls1043aqds/ls1043aqds.c
> > b/board/freescale/ls1043aqds/ls1043aqds.c
> > index d6696ca..770b79f 100644
> > --- a/board/freescale/ls1043aqds/ls1043aqds.c
> > +++ b/board/freescale/ls1043aqds/ls1043aqds.c
> > @@ -43,15 +43,19 @@ enum {
> >
> > int checkboard(void)
> > {
> > +#ifndef CONFIG_QSPI_BOOT
> > char buf[64];
> > #ifndef CONFIG_SD_BOOT
> > u8 sw;
> > #endif
> > +#endif
> >
> > puts("Board: LS1043AQDS, boot from ");
> >
> > #ifdef CONFIG_SD_BOOT
> > puts("SD\n");
> > +#elif defined(CONFIG_QSPI_BOOT)
> > + puts("QSPI\n");
> > #else
> > sw = QIXIS_READ(brdcfg[0]);
> > sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; @@ -68,12
> +72,15
> > @@ int checkboard(void)
> > printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
> #endif
> >
> > +#ifndef CONFIG_QSPI_BOOT
> > + /* For QSPI boot, here I2C is not ready yet. */
> > printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
> >QIXIS_READ(id), QIXIS_READ(arch));
> >
> > printf("FPGA: v%d (%s), build %d\n",
> >(int)QIXIS_READ(scver), qixis_read_tag(buf),
> >(int)qixis_read_minor());
> > +#endif
>
> Why isn't i2c ready? How is DDR inited without it?
>
> -Scott
Hi Scott,
The calling sequence in U-Boot is :
checkboard() -> init_func_i2c() -> dram_init()
So I2C is not ready in checkboard() but is ready for DDR initialization.
Regards,
Qianyu
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Re: [U-Boot] [PATCH v2 4/4] sunxi: Add suport for A83T based Banana-pi M3 Board
Hi,
On Tue, Jan 12, 2016 at 1:21 AM, Vishnu Patekar
wrote:
> Add dts and defconfig for Banana-pi M3 board.
>
> It has 2G LPDDR3, UART, ethernet, USB, HDMI, USB Sata, MIPI DSI,
> mic, AP6212 Wifi, etc on it.
> It is paired with AXP813 PMIC which is almost same as AXP818.
>
> Signed-off-by: Vishnu Patekar
> ---
> arch/arm/dts/Makefile| 3 +-
> arch/arm/dts/sun8i-a83t-bananapi-m3-v1.2.dts | 64
>
I'd prefer sun8i-a83t-sinovoip-bpi-m3.dts to match
sun6i-a31s-sinovoip-bpi-m2.dts
> board/sunxi/MAINTAINERS | 5 +++
> configs/Bananapi_m3_defconfig| 26 +++
And Sinovoip_BPI_M3_defconfig like Sinovoip_BPI_M2_defconfig already in U-boot.
> 4 files changed, 97 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/sun8i-a83t-bananapi-m3-v1.2.dts
> create mode 100644 configs/Bananapi_m3_defconfig
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 0bcd316..2ab0926 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -178,7 +178,8 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \
> sun8i-a33-q8-tablet.dtb \
> sun8i-a33-sinlinx-sina33.dtb
> dtb-$(CONFIG_MACH_SUN8I_A83T) += \
> - sun8i-a83t-allwinner-h8homlet-v2.dtb
> + sun8i-a83t-allwinner-h8homlet-v2.dtb \
> + sun8i-a83t-bananapi-m3-v1.2.dtb
> dtb-$(CONFIG_MACH_SUN8I_H3) += \
> sun8i-h3-orangepi-pc.dtb \
> sun8i-h3-orangepi-plus.dtb
> diff --git a/arch/arm/dts/sun8i-a83t-bananapi-m3-v1.2.dts
> b/arch/arm/dts/sun8i-a83t-bananapi-m3-v1.2.dts
> new file mode 100644
> index 000..91ff3a9
> --- /dev/null
> +++ b/arch/arm/dts/sun8i-a83t-bananapi-m3-v1.2.dts
> @@ -0,0 +1,64 @@
> +/*
> + * Copyright 2015 Vishnu Patekar
> + * Vishnu Patekar
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +#include "sun8i-a83t.dtsi"
> +
> +/ {
> + model = "Allwinner A83T BananaPi M3 Board v1.2";
> + compatible = "bananapi,m3v1.2", "allwinner,sun8i-a83t";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins_b>;
> + status = "okay";
> +};
> diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
> index 131c341..575847a 100644
> --- a/board/sunxi/MAINTAINERS
> +++ b/board/sunxi/MAINTAINERS
> @@ -84,6 +84,11 @@ M: Paul Kocialkowski
> S: Maintained
> F: configs/Ampe_A76_defconfig
>
> +BANANA PI M3 A83T BOARD
> +M: VishnuPatekar
> +S: Maintained
> +F: configs/Bananapi_m3_defconfig
> +
> COLOMBUS BOARD
> M: Maxime Ripard
> S: Maintained
> diff --git a/configs/Bananapi_m3_defconfig b/configs/Bananapi_m3_defconfig
> new file mode 100644
> index 000..36c5cde
> --- /dev/null
> +++ b/configs/Bananapi_m3_defconfig
> @@ -0,0 +1,26 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_SU
Re: [U-Boot] [PATCH v1 5/6] rockchip: kylin: Enable boot with android boot image
Hi Simon, On 2016-1-12 0:58, Simon Glass wrote: Hi Jeffy, On 8 January 2016 at 03:51, Jeffy Chen wrote: Hi Simon, On 2016-1-8 11:34, Simon Glass wrote: Hi Jeffy, On 4 January 2016 at 00:50, Jeffy Chen wrote: The android kernel is using appended dtb by default, and store ramdisk right after kernel & dtb. So we needs to relocate ramdisk, and use atags to pass params. Signed-off-by: Jeffy Chen --- include/configs/kylin_rk3036.h | 23 +++ 1 file changed, 23 insertions(+) Acked-by: Simon Glass What kernel version are you using? It's kernel v4.1 for android project: git fetch https://android.googlesource.com/platform/hardware/bsp/kernel/common/v4.1 refs/changes/03/188603/5 && git checkout FETCH_HEAD :) OK - just wondered why it needs ATAGs (CONFIG_SETUP_MEMORY_TAGS) - are there things that device tree does not support? I saw our guys used to detect ddr params in the loader, and pass memory areas and reserved areas to kernel... and kernel's device tree would only define a common memory node in the dtsi, which is not match the actually memory. used to Regards, Simon On 2016-1-8 11:34, Simon Glass wrote: Hi Jeffy, On 4 January 2016 at 00:50, Jeffy Chen wrote: The android kernel is using appended dtb by default, and store ramdisk right after kernel & dtb. So we needs to relocate ramdisk, and use atags to pass params. Signed-off-by: Jeffy Chen --- include/configs/kylin_rk3036.h | 23 +++ 1 file changed, 23 insertions(+) Acked-by: Simon Glass What kernel version are you using? Regards, Simon Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Newbie to u-boot needs help! Please help if you can
Hello I am making a bigeffort to try to acquire knowledge regarding embedded Linux. Myprimary reference is the book entitled 'Embedded Linux Primer, SecondEdition A Practical, Real-World Approach' by Christopher Hallinan,published 2010 I have reachedchapter 7, 'Bootloaders', and I am having a few problems with thischapter. In section 7.3 it starts to make mention of u-boot. Aftergit cloning and examining the latest u boot source tree, it isapparent that the description in the book about how to configure andbuild u-boot is not congruent the latest u-boot source tree. Cansomeone reply to this message, or point me to a(nother) mailing list(s),wikis or urls that would allow me to acquire a good understanding onhow configure and build u-boot as represented by the latest u-bootsource tree. Many thanks in advance ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] socfpga: Modify qts-filter args to allow input for bsp generated files and quartus project directories
The hps_isw_handoff and bsp/generated folders are typically not in the same
path. This patch adds support for specifying the different input directories
for the bsp and quartus projects.
Signed-off-by: Dalon Westergreen
Acked-by: Marek Vasut
---
Changes for v2:
- Add commit message
Changes for v3:
- Fix line length issues
---
arch/arm/mach-socfpga/qts-filter.sh | 74 +
1 file changed, 43 insertions(+), 31 deletions(-)
diff --git a/arch/arm/mach-socfpga/qts-filter.sh
b/arch/arm/mach-socfpga/qts-filter.sh
index c1640bc..b81a4e1 100755
--- a/arch/arm/mach-socfpga/qts-filter.sh
+++ b/arch/arm/mach-socfpga/qts-filter.sh
@@ -3,13 +3,15 @@
#
# Process iocsr_config_*.[ch]
# $1: SoC type
-# $2: Input directory
-# $3: Output directory
+# $2: Input handoff directory
+# $3: Input BSP Generated directory
+# $4: Output directory
#
process_iocsr_config() {
soc="$1"
- in_dir="$2"
- out_dir="$3"
+ in_qts_dir="$2"
+ in_bsp_dir="$3"
+ out_dir="$4"
(
cat << EOF
@@ -26,13 +28,13 @@ EOF
# Retrieve the scan chain lengths
grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' \
- ${in_dir}/generated/iocsr_config_${soc}.h | tr -d "()"
+ ${in_bsp_dir}/generated/iocsr_config_${soc}.h | tr -d "()"
echo ""
# Retrieve the scan chain config and zap the ad-hoc length encoding
sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}' \
- ${in_dir}/generated/iocsr_config_${soc}.c
+ ${in_bsp_dir}/generated/iocsr_config_${soc}.c
cat << EOF
@@ -49,8 +51,9 @@ EOF
#
process_pinmux_config() {
soc="$1"
- in_dir="$2"
- out_dir="$3"
+ in_qts_dir="$2"
+ in_bsp_dir="$3"
+ out_dir="$4"
(
cat << EOF
@@ -67,7 +70,7 @@ EOF
# Retrieve the pinmux config and zap the ad-hoc length encoding
sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned
long/const u8/};p;n;b next}' \
- ${in_dir}/generated/pinmux_config_${soc}.c
+ ${in_bsp_dir}/generated/pinmux_config_${soc}.c
cat << EOF
@@ -84,8 +87,9 @@ EOF
#
process_pll_config() {
soc="$1"
- in_dir="$2"
- out_dir="$3"
+ in_qts_dir="$2"
+ in_bsp_dir="$3"
+ out_dir="$4"
(
cat << EOF
@@ -102,7 +106,7 @@ EOF
# Retrieve the pll config and zap parenthesis
sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b
next}' \
- ${in_dir}/generated/pll_config.h
+ ${in_bsp_dir}/generated/pll_config.h
cat << EOF
@@ -126,8 +130,9 @@ grep_sdram_config() {
#
process_sdram_config() {
soc="$1"
- in_dir="$2"
- out_dir="$3"
+ in_qts_dir="$2"
+ in_bsp_dir="$3"
+ out_dir="$4"
(
cat << EOF
@@ -144,29 +149,32 @@ EOF
echo "/* SDRAM configuration */"
# Retrieve the sdram config, zap broken lines and zap parenthesis
- sed -n "/$/ {N;s/ \n/\t/};p"
${in_dir}/generated/sdram/sdram_config.h |
+ sed -n "/$/ {N;s/ \n/\t/};p"\
+ ${in_bsp_dir}/generated/sdram/sdram_config.h |
sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b
next}' |
sort -u | grep_sdram_config
echo ""
echo "/* Sequencer auto configuration */"
sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}"\
- ${in_dir}/hps_isw_handoff/*/sequencer_auto.h | sort -u |
grep_sdram_config
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto.h |
+ sort -u | grep_sdram_config
echo ""
echo "/* Sequencer defines configuration */"
sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \
- ${in_dir}/hps_isw_handoff/*/sequencer_defines.h | sort -u |
grep_sdram_config
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_defines.h |
+ sort -u | grep_sdram_config
echo ""
echo "/* Sequencer ac_rom_init configuration */"
sed -n '/^const.*\[/ !b; :next {/^const.*\[/
{N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
- ${in_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c
echo ""
echo "/* Sequencer inst_rom_init configuration */"
sed -n '/^const.*\[/ !b; :next {/^const.*\[/
{N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
- ${in_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c
cat << EOF
@@ -176,30 +184,34 @@ EOF
}
usage() {
- echo "$0 [soc_type] [input_dir] [output_dir]"
+ echo "$0 [soc_type] [input_qts_dir] [input_bsp_dir]
[U-Boot] [PATCH v4] socfpga: Modify qts-filter args to allow input for bsp generated files and quartus project directories
The hps_isw_handoff and bsp/generated folders are typically not in the same
path. This patch adds support for specifying the different input directories
for the bsp and quartus projects.
Signed-off-by: Dalon Westergreen
Acked-by: Marek Vasut
---
Changes for v2:
- Add commit message
Changes for v3:
- Fix line length issues
Changes for v4:
- Cleanup/clarify help messages
---
arch/arm/mach-socfpga/qts-filter.sh | 76 ++---
1 file changed, 45 insertions(+), 31 deletions(-)
diff --git a/arch/arm/mach-socfpga/qts-filter.sh
b/arch/arm/mach-socfpga/qts-filter.sh
index c1640bc..1adfbf7 100755
--- a/arch/arm/mach-socfpga/qts-filter.sh
+++ b/arch/arm/mach-socfpga/qts-filter.sh
@@ -3,13 +3,15 @@
#
# Process iocsr_config_*.[ch]
# $1: SoC type
-# $2: Input directory
-# $3: Output directory
+# $2: Input handoff directory
+# $3: Input BSP Generated directory
+# $4: Output directory
#
process_iocsr_config() {
soc="$1"
- in_dir="$2"
- out_dir="$3"
+ in_qts_dir="$2"
+ in_bsp_dir="$3"
+ out_dir="$4"
(
cat << EOF
@@ -26,13 +28,13 @@ EOF
# Retrieve the scan chain lengths
grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' \
- ${in_dir}/generated/iocsr_config_${soc}.h | tr -d "()"
+ ${in_bsp_dir}/generated/iocsr_config_${soc}.h | tr -d "()"
echo ""
# Retrieve the scan chain config and zap the ad-hoc length encoding
sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}' \
- ${in_dir}/generated/iocsr_config_${soc}.c
+ ${in_bsp_dir}/generated/iocsr_config_${soc}.c
cat << EOF
@@ -49,8 +51,9 @@ EOF
#
process_pinmux_config() {
soc="$1"
- in_dir="$2"
- out_dir="$3"
+ in_qts_dir="$2"
+ in_bsp_dir="$3"
+ out_dir="$4"
(
cat << EOF
@@ -67,7 +70,7 @@ EOF
# Retrieve the pinmux config and zap the ad-hoc length encoding
sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned
long/const u8/};p;n;b next}' \
- ${in_dir}/generated/pinmux_config_${soc}.c
+ ${in_bsp_dir}/generated/pinmux_config_${soc}.c
cat << EOF
@@ -84,8 +87,9 @@ EOF
#
process_pll_config() {
soc="$1"
- in_dir="$2"
- out_dir="$3"
+ in_qts_dir="$2"
+ in_bsp_dir="$3"
+ out_dir="$4"
(
cat << EOF
@@ -102,7 +106,7 @@ EOF
# Retrieve the pll config and zap parenthesis
sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b
next}' \
- ${in_dir}/generated/pll_config.h
+ ${in_bsp_dir}/generated/pll_config.h
cat << EOF
@@ -126,8 +130,9 @@ grep_sdram_config() {
#
process_sdram_config() {
soc="$1"
- in_dir="$2"
- out_dir="$3"
+ in_qts_dir="$2"
+ in_bsp_dir="$3"
+ out_dir="$4"
(
cat << EOF
@@ -144,29 +149,32 @@ EOF
echo "/* SDRAM configuration */"
# Retrieve the sdram config, zap broken lines and zap parenthesis
- sed -n "/$/ {N;s/ \n/\t/};p"
${in_dir}/generated/sdram/sdram_config.h |
+ sed -n "/$/ {N;s/ \n/\t/};p"\
+ ${in_bsp_dir}/generated/sdram/sdram_config.h |
sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b
next}' |
sort -u | grep_sdram_config
echo ""
echo "/* Sequencer auto configuration */"
sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}"\
- ${in_dir}/hps_isw_handoff/*/sequencer_auto.h | sort -u |
grep_sdram_config
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto.h |
+ sort -u | grep_sdram_config
echo ""
echo "/* Sequencer defines configuration */"
sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \
- ${in_dir}/hps_isw_handoff/*/sequencer_defines.h | sort -u |
grep_sdram_config
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_defines.h |
+ sort -u | grep_sdram_config
echo ""
echo "/* Sequencer ac_rom_init configuration */"
sed -n '/^const.*\[/ !b; :next {/^const.*\[/
{N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
- ${in_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c
echo ""
echo "/* Sequencer inst_rom_init configuration */"
sed -n '/^const.*\[/ !b; :next {/^const.*\[/
{N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
- ${in_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c
cat << EOF
@@ -176,30 +184,36 @@ EOF
}
usage() {
- echo "$0 [soc_type] [input_dir] [output_dir]"
+ ec
[U-Boot] [PATCH] socfpga: Modify qts-filter args to allow input for bsp generated files and quartus project directories
The hps_isw_handoff and bsp/generated folders are typically not in the same
path. This patch adds support for specifying the different input directories
for the bsp and quartus projects.
Signed-off-by: Dalon Westergreen
Acked-by: Marek Vasut
---
arch/arm/mach-socfpga/qts-filter.sh | 69 -
1 file changed, 38 insertions(+), 31 deletions(-)
diff --git a/arch/arm/mach-socfpga/qts-filter.sh
b/arch/arm/mach-socfpga/qts-filter.sh
index c1640bc..835ca2c 100755
--- a/arch/arm/mach-socfpga/qts-filter.sh
+++ b/arch/arm/mach-socfpga/qts-filter.sh
@@ -3,13 +3,15 @@
#
# Process iocsr_config_*.[ch]
# $1: SoC type
-# $2: Input directory
-# $3: Output directory
+# $2: Input handoff directory
+# $3: Input BSP Generated directory
+# $4: Output directory
#
process_iocsr_config() {
soc="$1"
- in_dir="$2"
- out_dir="$3"
+ in_qts_dir="$2"
+ in_bsp_dir="$3"
+ out_dir="$4"
(
cat << EOF
@@ -26,13 +28,13 @@ EOF
# Retrieve the scan chain lengths
grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' \
- ${in_dir}/generated/iocsr_config_${soc}.h | tr -d "()"
+ ${in_bsp_dir}/generated/iocsr_config_${soc}.h | tr -d "()"
echo ""
# Retrieve the scan chain config and zap the ad-hoc length encoding
sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}' \
- ${in_dir}/generated/iocsr_config_${soc}.c
+ ${in_bsp_dir}/generated/iocsr_config_${soc}.c
cat << EOF
@@ -49,8 +51,9 @@ EOF
#
process_pinmux_config() {
soc="$1"
- in_dir="$2"
- out_dir="$3"
+ in_qts_dir="$2"
+ in_bsp_dir="$3"
+ out_dir="$4"
(
cat << EOF
@@ -67,7 +70,7 @@ EOF
# Retrieve the pinmux config and zap the ad-hoc length encoding
sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned
long/const u8/};p;n;b next}' \
- ${in_dir}/generated/pinmux_config_${soc}.c
+ ${in_bsp_dir}/generated/pinmux_config_${soc}.c
cat << EOF
@@ -84,8 +87,9 @@ EOF
#
process_pll_config() {
soc="$1"
- in_dir="$2"
- out_dir="$3"
+ in_qts_dir="$2"
+ in_bsp_dir="$3"
+ out_dir="$4"
(
cat << EOF
@@ -102,7 +106,7 @@ EOF
# Retrieve the pll config and zap parenthesis
sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b
next}' \
- ${in_dir}/generated/pll_config.h
+ ${in_bsp_dir}/generated/pll_config.h
cat << EOF
@@ -126,8 +130,9 @@ grep_sdram_config() {
#
process_sdram_config() {
soc="$1"
- in_dir="$2"
- out_dir="$3"
+ in_qts_dir="$2"
+ in_bsp_dir="$3"
+ out_dir="$4"
(
cat << EOF
@@ -144,29 +149,29 @@ EOF
echo "/* SDRAM configuration */"
# Retrieve the sdram config, zap broken lines and zap parenthesis
- sed -n "/$/ {N;s/ \n/\t/};p"
${in_dir}/generated/sdram/sdram_config.h |
+ sed -n "/$/ {N;s/ \n/\t/};p"
${in_bsp_dir}/generated/sdram/sdram_config.h |
sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b
next}' |
sort -u | grep_sdram_config
echo ""
echo "/* Sequencer auto configuration */"
sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}"\
- ${in_dir}/hps_isw_handoff/*/sequencer_auto.h | sort -u |
grep_sdram_config
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto.h | sort -u |
grep_sdram_config
echo ""
echo "/* Sequencer defines configuration */"
sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \
- ${in_dir}/hps_isw_handoff/*/sequencer_defines.h | sort -u |
grep_sdram_config
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_defines.h | sort -u |
grep_sdram_config
echo ""
echo "/* Sequencer ac_rom_init configuration */"
sed -n '/^const.*\[/ !b; :next {/^const.*\[/
{N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
- ${in_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c
echo ""
echo "/* Sequencer inst_rom_init configuration */"
sed -n '/^const.*\[/ !b; :next {/^const.*\[/
{N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
- ${in_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c
cat << EOF
@@ -176,30 +181,32 @@ EOF
}
usage() {
- echo "$0 [soc_type] [input_dir] [output_dir]"
+ echo "$0 [soc_type] [input_qts_dir] [input_bsp_dir] [output_dir]"
echo "Process QTS-generated headers into U-Boot compatible ones."
echo ""
- echo " soc_type\t\tType of SoC,
[U-Boot] [PATCH v5] socfpga: Modify qts-filter args to allow input for bsp generated files and quartus project directories
The hps_isw_handoff and bsp/generated folders are typically not in the same
path.This patch adds support for specifying the different input directories for
the bsp and quartus projects.
Signed-off-by: Dalon Westergreen
Acked-by: Marek Vasut
Acked-by: Chin Liang See
---
Changes for v2:
- Add commit message
Changes for v3:
- Fix line length issues
Changes for v4:
- Cleanup/clarify help messages
Changes for v5:
- Fix line length issues
---
arch/arm/mach-socfpga/qts-filter.sh | 76 ++---
1 file changed, 45 insertions(+), 31 deletions(-)
diff --git a/arch/arm/mach-socfpga/qts-filter.sh
b/arch/arm/mach-socfpga/qts-filter.sh
index c1640bc..1adfbf7 100755
--- a/arch/arm/mach-socfpga/qts-filter.sh
+++ b/arch/arm/mach-socfpga/qts-filter.sh
@@ -3,13 +3,15 @@
#
# Process iocsr_config_*.[ch]
# $1: SoC type
-# $2: Input directory
-# $3: Output directory
+# $2: Input handoff directory
+# $3: Input BSP Generated directory
+# $4: Output directory
#
process_iocsr_config() {
soc="$1"
- in_dir="$2"
- out_dir="$3"
+ in_qts_dir="$2"
+ in_bsp_dir="$3"
+ out_dir="$4"
(
cat << EOF
@@ -26,13 +28,13 @@ EOF
# Retrieve the scan chain lengths
grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' \
- ${in_dir}/generated/iocsr_config_${soc}.h | tr -d "()"
+ ${in_bsp_dir}/generated/iocsr_config_${soc}.h | tr -d "()"
echo ""
# Retrieve the scan chain config and zap the ad-hoc length encoding
sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}' \
- ${in_dir}/generated/iocsr_config_${soc}.c
+ ${in_bsp_dir}/generated/iocsr_config_${soc}.c
cat << EOF
@@ -49,8 +51,9 @@ EOF
#
process_pinmux_config() {
soc="$1"
- in_dir="$2"
- out_dir="$3"
+ in_qts_dir="$2"
+ in_bsp_dir="$3"
+ out_dir="$4"
(
cat << EOF
@@ -67,7 +70,7 @@ EOF
# Retrieve the pinmux config and zap the ad-hoc length encoding
sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned
long/const u8/};p;n;b next}' \
- ${in_dir}/generated/pinmux_config_${soc}.c
+ ${in_bsp_dir}/generated/pinmux_config_${soc}.c
cat << EOF
@@ -84,8 +87,9 @@ EOF
#
process_pll_config() {
soc="$1"
- in_dir="$2"
- out_dir="$3"
+ in_qts_dir="$2"
+ in_bsp_dir="$3"
+ out_dir="$4"
(
cat << EOF
@@ -102,7 +106,7 @@ EOF
# Retrieve the pll config and zap parenthesis
sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b
next}' \
- ${in_dir}/generated/pll_config.h
+ ${in_bsp_dir}/generated/pll_config.h
cat << EOF
@@ -126,8 +130,9 @@ grep_sdram_config() {
#
process_sdram_config() {
soc="$1"
- in_dir="$2"
- out_dir="$3"
+ in_qts_dir="$2"
+ in_bsp_dir="$3"
+ out_dir="$4"
(
cat << EOF
@@ -144,29 +149,32 @@ EOF
echo "/* SDRAM configuration */"
# Retrieve the sdram config, zap broken lines and zap parenthesis
- sed -n "/$/ {N;s/ \n/\t/};p"
${in_dir}/generated/sdram/sdram_config.h |
+ sed -n "/$/ {N;s/ \n/\t/};p"\
+ ${in_bsp_dir}/generated/sdram/sdram_config.h |
sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b
next}' |
sort -u | grep_sdram_config
echo ""
echo "/* Sequencer auto configuration */"
sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}"\
- ${in_dir}/hps_isw_handoff/*/sequencer_auto.h | sort -u |
grep_sdram_config
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto.h |
+ sort -u | grep_sdram_config
echo ""
echo "/* Sequencer defines configuration */"
sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \
- ${in_dir}/hps_isw_handoff/*/sequencer_defines.h | sort -u |
grep_sdram_config
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_defines.h |
+ sort -u | grep_sdram_config
echo ""
echo "/* Sequencer ac_rom_init configuration */"
sed -n '/^const.*\[/ !b; :next {/^const.*\[/
{N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
- ${in_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c
echo ""
echo "/* Sequencer inst_rom_init configuration */"
sed -n '/^const.*\[/ !b; :next {/^const.*\[/
{N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
- ${in_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c
cat << EOF
@@ -176,30 +184,36 @@ EOF
}
usage()
[U-Boot] [PATCH] socfpga: Modify qts-filter args to allow input for bsp generated files and quartus project directories
Signed-off-by: Dalon Westergreen
---
arch/arm/mach-socfpga/qts-filter.sh | 69 -
1 file changed, 38 insertions(+), 31 deletions(-)
diff --git a/arch/arm/mach-socfpga/qts-filter.sh
b/arch/arm/mach-socfpga/qts-filter.sh
index c1640bc..835ca2c 100755
--- a/arch/arm/mach-socfpga/qts-filter.sh
+++ b/arch/arm/mach-socfpga/qts-filter.sh
@@ -3,13 +3,15 @@
#
# Process iocsr_config_*.[ch]
# $1: SoC type
-# $2: Input directory
-# $3: Output directory
+# $2: Input handoff directory
+# $3: Input BSP Generated directory
+# $4: Output directory
#
process_iocsr_config() {
soc="$1"
- in_dir="$2"
- out_dir="$3"
+ in_qts_dir="$2"
+ in_bsp_dir="$3"
+ out_dir="$4"
(
cat << EOF
@@ -26,13 +28,13 @@ EOF
# Retrieve the scan chain lengths
grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' \
- ${in_dir}/generated/iocsr_config_${soc}.h | tr -d "()"
+ ${in_bsp_dir}/generated/iocsr_config_${soc}.h | tr -d "()"
echo ""
# Retrieve the scan chain config and zap the ad-hoc length encoding
sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}' \
- ${in_dir}/generated/iocsr_config_${soc}.c
+ ${in_bsp_dir}/generated/iocsr_config_${soc}.c
cat << EOF
@@ -49,8 +51,9 @@ EOF
#
process_pinmux_config() {
soc="$1"
- in_dir="$2"
- out_dir="$3"
+ in_qts_dir="$2"
+ in_bsp_dir="$3"
+ out_dir="$4"
(
cat << EOF
@@ -67,7 +70,7 @@ EOF
# Retrieve the pinmux config and zap the ad-hoc length encoding
sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned
long/const u8/};p;n;b next}' \
- ${in_dir}/generated/pinmux_config_${soc}.c
+ ${in_bsp_dir}/generated/pinmux_config_${soc}.c
cat << EOF
@@ -84,8 +87,9 @@ EOF
#
process_pll_config() {
soc="$1"
- in_dir="$2"
- out_dir="$3"
+ in_qts_dir="$2"
+ in_bsp_dir="$3"
+ out_dir="$4"
(
cat << EOF
@@ -102,7 +106,7 @@ EOF
# Retrieve the pll config and zap parenthesis
sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b
next}' \
- ${in_dir}/generated/pll_config.h
+ ${in_bsp_dir}/generated/pll_config.h
cat << EOF
@@ -126,8 +130,9 @@ grep_sdram_config() {
#
process_sdram_config() {
soc="$1"
- in_dir="$2"
- out_dir="$3"
+ in_qts_dir="$2"
+ in_bsp_dir="$3"
+ out_dir="$4"
(
cat << EOF
@@ -144,29 +149,29 @@ EOF
echo "/* SDRAM configuration */"
# Retrieve the sdram config, zap broken lines and zap parenthesis
- sed -n "/$/ {N;s/ \n/\t/};p"
${in_dir}/generated/sdram/sdram_config.h |
+ sed -n "/$/ {N;s/ \n/\t/};p"
${in_bsp_dir}/generated/sdram/sdram_config.h |
sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b
next}' |
sort -u | grep_sdram_config
echo ""
echo "/* Sequencer auto configuration */"
sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}"\
- ${in_dir}/hps_isw_handoff/*/sequencer_auto.h | sort -u |
grep_sdram_config
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto.h | sort -u |
grep_sdram_config
echo ""
echo "/* Sequencer defines configuration */"
sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \
- ${in_dir}/hps_isw_handoff/*/sequencer_defines.h | sort -u |
grep_sdram_config
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_defines.h | sort -u |
grep_sdram_config
echo ""
echo "/* Sequencer ac_rom_init configuration */"
sed -n '/^const.*\[/ !b; :next {/^const.*\[/
{N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
- ${in_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c
echo ""
echo "/* Sequencer inst_rom_init configuration */"
sed -n '/^const.*\[/ !b; :next {/^const.*\[/
{N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
- ${in_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c
cat << EOF
@@ -176,30 +181,32 @@ EOF
}
usage() {
- echo "$0 [soc_type] [input_dir] [output_dir]"
+ echo "$0 [soc_type] [input_qts_dir] [input_bsp_dir] [output_dir]"
echo "Process QTS-generated headers into U-Boot compatible ones."
echo ""
- echo " soc_type\t\tType of SoC, either 'cyclone5' or 'arria5',"
- echo " input_dir\t\tDirectory with the QTS project."
- echo " output_dir\t\tDirectory to store the U-Boot compatible headers."
+ echo " soc_type - Type of So
Re: [U-Boot] [PATCH v6 0/8] x86: qemu: add fw_cfg interface support for qemu-x86 targets
Hi Bin, 2016-01-07 17:31 GMT+08:00 Miao Yan : > The fw_cfg interface provided by QEMU allow guests to retrieve various > information > about the system, e.g. cpu number, variaous firmware data, kernel setup, etc. > The > fw_cfg interface can be accessed through 3 IO ports (on x86), using x86 in/out > instructions. > > - 0x510: select configuration items to access > - 0x511: reading this port will return data selected in 0x510 > - 0x514: this can be used to detect if DMA interface is available > > If fw_cfg DMA interface is available, it can be used to accelerate > accesses. > > This patchset adds the following supports for qemu-x86 targets: > > + the fw_cfg driver itself > > + add a U-Boot command 'fw' to support direct accessing kernel informtion > from fw_cfg interface, this saves the time of loading them from hard disk > or > network again, through emulated devices. > > + use fw_cfg to get cpu number at runtime, so smp boot no longer relies on > the cpu node hard-coded in dts files. > > Changes in v6: > - fix oneline comment > - do not update bootargs when kernel cmdline only contains '\0' > > Miao Yan (8): > x86: adjust ramdisk load address > x86: qemu: add fw_cfg support > x86: qemu: add a cpu uclass driver for qemu target > x86: fix a typo in function name > x86: use actual CPU number for allocating memory > x86: qemu: fix cpu device in smp boot > x86: qemu: remove cpu node in device tree > x86: qemu: add documentaion for the fw_cfg interface > > arch/x86/cpu/mp_init.c | 84 +++- > arch/x86/cpu/qemu/Makefile | 2 +- > arch/x86/cpu/qemu/cpu.c | 46 +++ > arch/x86/cpu/qemu/fw_cfg.c | 283 > +++ > arch/x86/cpu/qemu/qemu.c | 3 + > arch/x86/dts/qemu-x86_i440fx.dts | 9 +- > arch/x86/dts/qemu-x86_q35.dts| 9 +- > arch/x86/include/asm/fw_cfg.h| 93 + > doc/README.x86 | 34 - > include/configs/x86-common.h | 3 +- > 10 files changed, 539 insertions(+), 27 deletions(-) > create mode 100644 arch/x86/cpu/qemu/cpu.c > create mode 100644 arch/x86/cpu/qemu/fw_cfg.c > create mode 100644 arch/x86/include/asm/fw_cfg.h > > -- > 1.9.1 > Is v6 OK for integration ? Thanks. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4] socfpga: Modify qts-filter args to allow input for bsp generated files and quartus project directories
On Tuesday, January 12, 2016 at 02:49:14 AM, Dalon Westergreen wrote:
> The hps_isw_handoff and bsp/generated folders are typically not in the same
> path. This patch adds support for specifying the different input
> directories for the bsp and quartus projects.
Still not aligned to 80 :-) But I am fine if you want me to fix it up by
hand, I can do that.
Note that in this reply, my mailer did the alignment automatically. Use
git commit --amend to append the patch in your git history and use for
example :set textwidth=80 in vim to activate automatic breaking of long
lines.
> Signed-off-by: Dalon Westergreen
> Acked-by: Marek Vasut
Also, Chin added his Acked-by, so you should add it here.
> ---
> Changes for v2:
> - Add commit message
> Changes for v3:
> - Fix line length issues
> Changes for v4:
> - Cleanup/clarify help messages
> ---
> arch/arm/mach-socfpga/qts-filter.sh | 76
> ++--- 1 file changed, 45 insertions(+), 31
> deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/qts-filter.sh
> b/arch/arm/mach-socfpga/qts-filter.sh index c1640bc..1adfbf7 100755
> --- a/arch/arm/mach-socfpga/qts-filter.sh
> +++ b/arch/arm/mach-socfpga/qts-filter.sh
> @@ -3,13 +3,15 @@
> #
> # Process iocsr_config_*.[ch]
> # $1:SoC type
> -# $2:Input directory
> -# $3:Output directory
> +# $2:Input handoff directory
> +# $3:Input BSP Generated directory
> +# $4:Output directory
> #
> process_iocsr_config() {
> soc="$1"
> - in_dir="$2"
> - out_dir="$3"
> + in_qts_dir="$2"
> + in_bsp_dir="$3"
> + out_dir="$4"
>
> (
> cat << EOF
> @@ -26,13 +28,13 @@ EOF
>
> # Retrieve the scan chain lengths
> grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' \
> - ${in_dir}/generated/iocsr_config_${soc}.h | tr -d "()"
> + ${in_bsp_dir}/generated/iocsr_config_${soc}.h | tr -d "()"
>
> echo ""
>
> # Retrieve the scan chain config and zap the ad-hoc length encoding
> sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}' \
> - ${in_dir}/generated/iocsr_config_${soc}.c
> + ${in_bsp_dir}/generated/iocsr_config_${soc}.c
>
> cat << EOF
>
> @@ -49,8 +51,9 @@ EOF
> #
> process_pinmux_config() {
> soc="$1"
> - in_dir="$2"
> - out_dir="$3"
> + in_qts_dir="$2"
> + in_bsp_dir="$3"
> + out_dir="$4"
>
> (
> cat << EOF
> @@ -67,7 +70,7 @@ EOF
>
> # Retrieve the pinmux config and zap the ad-hoc length encoding
> sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned
> long/const u8/};p;n;b next}' \
> - ${in_dir}/generated/pinmux_config_${soc}.c
> + ${in_bsp_dir}/generated/pinmux_config_${soc}.c
>
> cat << EOF
>
> @@ -84,8 +87,9 @@ EOF
> #
> process_pll_config() {
> soc="$1"
> - in_dir="$2"
> - out_dir="$3"
> + in_qts_dir="$2"
> + in_bsp_dir="$3"
> + out_dir="$4"
>
> (
> cat << EOF
> @@ -102,7 +106,7 @@ EOF
>
> # Retrieve the pll config and zap parenthesis
> sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b
> next}' \ -${in_dir}/generated/pll_config.h
> + ${in_bsp_dir}/generated/pll_config.h
>
> cat << EOF
>
> @@ -126,8 +130,9 @@ grep_sdram_config() {
> #
> process_sdram_config() {
> soc="$1"
> - in_dir="$2"
> - out_dir="$3"
> + in_qts_dir="$2"
> + in_bsp_dir="$3"
> + out_dir="$4"
>
> (
> cat << EOF
> @@ -144,29 +149,32 @@ EOF
>
> echo "/* SDRAM configuration */"
> # Retrieve the sdram config, zap broken lines and zap parenthesis
> - sed -n "/$/ {N;s/ \n/\t/};p"
> ${in_dir}/generated/sdram/sdram_config.h | + sed -n "/$/ {N;s/
> \n/\t/};p"\
> + ${in_bsp_dir}/generated/sdram/sdram_config.h |
> sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b
> next}' | sort -u | grep_sdram_config
>
> echo ""
> echo "/* Sequencer auto configuration */"
> sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}"\
> - ${in_dir}/hps_isw_handoff/*/sequencer_auto.h | sort -u |
> grep_sdram_config +
> ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto.h
|
> + sort -u | grep_sdram_config
>
> echo ""
> echo "/* Sequencer defines configuration */"
> sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \
> - ${in_dir}/hps_isw_handoff/*/sequencer_defines.h | sort -u |
> grep_sdram_config +
${in_qts_dir}/hps_isw_handoff/*/sequencer_defines.h |
> + sort -u | grep_sdram_config
>
> echo ""
> echo "/* Sequencer ac_rom_init configuration */"
> sed -n '/^const.*\[/ !b; :next {/^const.*\[/
> {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
> - ${in_dir}/hps_isw_ha
Re: [U-Boot] [PATCH v3] socfpga: Modify qts-filter args to allow input for bsp generated files and quartus project directories
On Tue, 2016-01-12 at 01:31 +0100, Marek Vasut wrote: > On Tuesday, January 12, 2016 at 01:26:58 AM, Chin Liang See wrote: > > On Mon, 2016-01-11 at 15:33 -0800, Dalon Westergreen wrote: > [...] > > btw. Completely off-topic, but is there any chance altera will > release the > algorithm to compute these magic values which are in the header files > from > the base values inserted into the HPS component in QSys ? I would not suggesting that as Qsys and Quartus are doing heavylifting tasks there. The value would depends on the options being choosed, device type, device revision (if any). They also being patched from time to time too. > I think we might > just put these values into OF and do the computation in U-Boot on-the > -fly. > This would also remove the need for this script. Slightly off topic, I am thinking to move all these generated files into DTS too. This will have some out of box experience as Arria10 SoC. But that might be challenging in term of resources. We might still stick with this script for good. Thanks Chin Liang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] socfpga: Modify qts-filter args to allow input for bsp generated files and quartus project directories
On Tuesday, January 12, 2016 at 01:26:58 AM, Chin Liang See wrote:
> On Mon, 2016-01-11 at 15:33 -0800, Dalon Westergreen wrote:
> > The hps_isw_handoff and bsp/generated folders are typically not in
> > the same path. This patch adds support for specifying the different
> > input directories for the bsp and quartus projects.
> >
> > Signed-off-by: Dalon Westergreen
> > Acked-by: Marek Vasut
> > ---
> >
> > Changes for v2:
> > - Add commit message
> >
> > Changes for v3:
> > - Fix line length issues
> >
> > ---
> >
> > arch/arm/mach-socfpga/qts-filter.sh | 74 +--
> >
> > --
> >
> > 1 file changed, 43 insertions(+), 31 deletions(-)
>
> Looks good to me with minor nickpicking on the help message.
>
> Acked-by: Chin Liang See
>
> Thanks
> Chin Liang
>
> > diff --git a/arch/arm/mach-socfpga/qts-filter.sh b/arch/arm/mach
> > -socfpga/qts-filter.sh
> > index c1640bc..b81a4e1 100755
> > --- a/arch/arm/mach-socfpga/qts-filter.sh
> > +++ b/arch/arm/mach-socfpga/qts-filter.sh
>
> [..]
>
> > @@ -176,30 +184,34 @@ EOF
> >
> > }
> >
> > usage() {
> >
> > - echo "$0 [soc_type] [input_dir] [output_dir]"
> > + echo "$0 [soc_type] [input_qts_dir] [input_bsp_dir]
> > [output_dir]"
> >
> > echo "Process QTS-generated headers into U-Boot compatible
> >
> > ones."
> >
> > echo ""
> >
> > - echo " soc_type\t\tType of SoC, either 'cyclone5' or
> > 'arria5',"
> > - echo " input_dir\t\tDirectory with the QTS project."
> > - echo " output_dir\t\tDirectory to store the U-Boot
> > compatible headers."
> > + echo " soc_type - Type of SoC, either 'cyclone5' or
> > 'arria5',"
> > + echo " input_qts_dir - Directory with compiled Quartus
> > project."
>
> We can put Directory where the Quartus project file is located.
Make sure to retain the "compiled" bit there, it's important as you cannot
extract these information from not-compiled quartus project.
> > + echo " input_bsp_dir - Directory with generated output
> > from"
> > + echo " the bsp-editor."
>
> We can put Directory where the bsp-editor file settings.bsp is located.
[...]
btw. Completely off-topic, but is there any chance altera will release the
algorithm to compute these magic values which are in the header files from
the base values inserted into the HPS component in QSys ? I think we might
just put these values into OF and do the computation in U-Boot on-the-fly.
This would also remove the need for this script.
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Re: [U-Boot] [PATCH v3] socfpga: Modify qts-filter args to allow input for bsp generated files and quartus project directories
On Mon, 2016-01-11 at 15:33 -0800, Dalon Westergreen wrote:
> The hps_isw_handoff and bsp/generated folders are typically not in
> the same path. This patch adds support for specifying the different
> input directories for the bsp and quartus projects.
>
> Signed-off-by: Dalon Westergreen
> Acked-by: Marek Vasut
> ---
> Changes for v2:
> - Add commit message
> Changes for v3:
> - Fix line length issues
> ---
> arch/arm/mach-socfpga/qts-filter.sh | 74 +--
> --
> 1 file changed, 43 insertions(+), 31 deletions(-)
>
Looks good to me with minor nickpicking on the help message.
Acked-by: Chin Liang See
Thanks
Chin Liang
> diff --git a/arch/arm/mach-socfpga/qts-filter.sh b/arch/arm/mach
> -socfpga/qts-filter.sh
> index c1640bc..b81a4e1 100755
> --- a/arch/arm/mach-socfpga/qts-filter.sh
> +++ b/arch/arm/mach-socfpga/qts-filter.sh
>
[..]
> @@ -176,30 +184,34 @@ EOF
> }
>
> usage() {
> - echo "$0 [soc_type] [input_dir] [output_dir]"
> + echo "$0 [soc_type] [input_qts_dir] [input_bsp_dir]
> [output_dir]"
> echo "Process QTS-generated headers into U-Boot compatible
> ones."
> echo ""
> - echo " soc_type\t\tType of SoC, either 'cyclone5' or
> 'arria5',"
> - echo " input_dir\t\tDirectory with the QTS project."
> - echo " output_dir\t\tDirectory to store the U-Boot
> compatible headers."
> + echo " soc_type - Type of SoC, either 'cyclone5' or
> 'arria5',"
> + echo " input_qts_dir - Directory with compiled Quartus
> project."
We can put Directory where the Quartus project file is located.
> + echo " input_bsp_dir - Directory with generated output
> from"
> + echo " the bsp-editor."
We can put Directory where the bsp-editor file settings.bsp is located.
> + echo " output_dir - Directory to store the U-Boot
> compatible headers."
> echo ""
> }
>
> soc="$1"
> -in_dir="$2"
> -out_dir="$3"
> +in_qts_dir="$2"
> +in_bsp_dir="$3"
> +out_dir="$4"
>
> -if [ "$#" -ne 3 ] ; then
> +if [ "$#" -ne 4 ] ; then
> usage
> exit 1
> fi
>
> -if [ ! -d "${in_dir}" -o ! -d "${out_dir}" -o -z "${soc}" ] ; then
> +if [ ! -d "${in_qts_dir}" -o ! -d "${in_bsp_dir}" -o \
> + ! -d "${out_dir}" -o -z "${soc}" ] ; then
> usage
> exit 3
> fi
>
> -process_iocsr_config "${soc}" "${in_dir}" "${out_dir}"
> -process_pinmux_config "${soc}" "${in_dir}" "${out_dir}"
> -process_pll_config"${soc}" "${in_dir}" "${out_dir}"
> -process_sdram_config "${soc}" "${in_dir}" "${out_dir}"
> +process_iocsr_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}"
> "${out_dir}"
> +process_pinmux_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}"
> "${out_dir}"
> +process_pll_config"${soc}" "${in_qts_dir}" "${in_bsp_dir}"
> "${out_dir}"
> +process_sdram_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}"
> "${out_dir}"
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Re: [U-Boot] [PATCH v3] socfpga: Modify qts-filter args to allow input for bsp generated files and quartus project directories
On Tuesday, January 12, 2016 at 12:33:18 AM, Dalon Westergreen wrote:
> The hps_isw_handoff and bsp/generated folders are typically not in the same
> path. This patch adds support for specifying the different input
> directories for the bsp and quartus projects.
The commit message is still not aligned to 80 ;-)
> Signed-off-by: Dalon Westergreen
> Acked-by: Marek Vasut
> ---
> Changes for v2:
> - Add commit message
> Changes for v3:
> - Fix line length issues
> ---
> arch/arm/mach-socfpga/qts-filter.sh | 74
> + 1 file changed, 43 insertions(+), 31
> deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/qts-filter.sh
> b/arch/arm/mach-socfpga/qts-filter.sh index c1640bc..b81a4e1 100755
> --- a/arch/arm/mach-socfpga/qts-filter.sh
> +++ b/arch/arm/mach-socfpga/qts-filter.sh
> @@ -3,13 +3,15 @@
> #
> # Process iocsr_config_*.[ch]
> # $1:SoC type
> -# $2:Input directory
> -# $3:Output directory
> +# $2:Input handoff directory
> +# $3:Input BSP Generated directory
> +# $4:Output directory
> #
> process_iocsr_config() {
> soc="$1"
> - in_dir="$2"
> - out_dir="$3"
> + in_qts_dir="$2"
> + in_bsp_dir="$3"
> + out_dir="$4"
>
> (
> cat << EOF
> @@ -26,13 +28,13 @@ EOF
>
> # Retrieve the scan chain lengths
> grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' \
> - ${in_dir}/generated/iocsr_config_${soc}.h | tr -d "()"
> + ${in_bsp_dir}/generated/iocsr_config_${soc}.h | tr -d "()"
>
> echo ""
>
> # Retrieve the scan chain config and zap the ad-hoc length encoding
> sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}' \
> - ${in_dir}/generated/iocsr_config_${soc}.c
> + ${in_bsp_dir}/generated/iocsr_config_${soc}.c
>
> cat << EOF
>
> @@ -49,8 +51,9 @@ EOF
> #
> process_pinmux_config() {
> soc="$1"
> - in_dir="$2"
> - out_dir="$3"
> + in_qts_dir="$2"
> + in_bsp_dir="$3"
> + out_dir="$4"
>
> (
> cat << EOF
> @@ -67,7 +70,7 @@ EOF
>
> # Retrieve the pinmux config and zap the ad-hoc length encoding
> sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned
> long/const u8/};p;n;b next}' \
> - ${in_dir}/generated/pinmux_config_${soc}.c
> + ${in_bsp_dir}/generated/pinmux_config_${soc}.c
>
> cat << EOF
>
> @@ -84,8 +87,9 @@ EOF
> #
> process_pll_config() {
> soc="$1"
> - in_dir="$2"
> - out_dir="$3"
> + in_qts_dir="$2"
> + in_bsp_dir="$3"
> + out_dir="$4"
>
> (
> cat << EOF
> @@ -102,7 +106,7 @@ EOF
>
> # Retrieve the pll config and zap parenthesis
> sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b
> next}' \ -${in_dir}/generated/pll_config.h
> + ${in_bsp_dir}/generated/pll_config.h
>
> cat << EOF
>
> @@ -126,8 +130,9 @@ grep_sdram_config() {
> #
> process_sdram_config() {
> soc="$1"
> - in_dir="$2"
> - out_dir="$3"
> + in_qts_dir="$2"
> + in_bsp_dir="$3"
> + out_dir="$4"
>
> (
> cat << EOF
> @@ -144,29 +149,32 @@ EOF
>
> echo "/* SDRAM configuration */"
> # Retrieve the sdram config, zap broken lines and zap parenthesis
> - sed -n "/$/ {N;s/ \n/\t/};p"
> ${in_dir}/generated/sdram/sdram_config.h | + sed -n "/$/ {N;s/
> \n/\t/};p"\
> + ${in_bsp_dir}/generated/sdram/sdram_config.h |
> sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b
> next}' | sort -u | grep_sdram_config
>
> echo ""
> echo "/* Sequencer auto configuration */"
> sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}"\
> - ${in_dir}/hps_isw_handoff/*/sequencer_auto.h | sort -u |
> grep_sdram_config +
> ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto.h
|
> + sort -u | grep_sdram_config
>
> echo ""
> echo "/* Sequencer defines configuration */"
> sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \
> - ${in_dir}/hps_isw_handoff/*/sequencer_defines.h | sort -u |
> grep_sdram_config +
${in_qts_dir}/hps_isw_handoff/*/sequencer_defines.h |
> + sort -u | grep_sdram_config
>
> echo ""
> echo "/* Sequencer ac_rom_init configuration */"
> sed -n '/^const.*\[/ !b; :next {/^const.*\[/
> {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
> - ${in_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c
> + ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c
>
> echo ""
> echo "/* Sequencer inst_rom_init configuration */"
> sed -n '/^const.*\[/ !b; :next {/^const.*\[/
> {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
> - ${in_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c
> +
Re: [U-Boot] [PATCH] socfpga: Modify qts-filter args to allow input for bsp generated files and quartus project directories
On Monday, January 11, 2016 at 11:51:10 PM, Dalon Westergreen wrote:
> The hps_isw_handoff and bsp/generated folders are typically not in the same
> path. This patch adds support for specifying the different input
> directories for the bsp and quartus projects.
Next time, please align to 80 chars .
Also the patch should be marked as patch V2, see the rules:
http://www.denx.de/wiki/U-Boot/Patches
But I can fix this. Let's give Dinh/Chin time to catch up and then I'll pick
it if they're fine with it.
> Signed-off-by: Dalon Westergreen
> Acked-by: Marek Vasut
> ---
> arch/arm/mach-socfpga/qts-filter.sh | 69
> - 1 file changed, 38 insertions(+), 31
> deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/qts-filter.sh
> b/arch/arm/mach-socfpga/qts-filter.sh index c1640bc..835ca2c 100755
> --- a/arch/arm/mach-socfpga/qts-filter.sh
> +++ b/arch/arm/mach-socfpga/qts-filter.sh
> @@ -3,13 +3,15 @@
> #
> # Process iocsr_config_*.[ch]
> # $1:SoC type
> -# $2:Input directory
> -# $3:Output directory
> +# $2:Input handoff directory
> +# $3:Input BSP Generated directory
> +# $4:Output directory
> #
> process_iocsr_config() {
> soc="$1"
> - in_dir="$2"
> - out_dir="$3"
> + in_qts_dir="$2"
> + in_bsp_dir="$3"
> + out_dir="$4"
>
> (
> cat << EOF
> @@ -26,13 +28,13 @@ EOF
>
> # Retrieve the scan chain lengths
> grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' \
> - ${in_dir}/generated/iocsr_config_${soc}.h | tr -d "()"
> + ${in_bsp_dir}/generated/iocsr_config_${soc}.h | tr -d "()"
>
> echo ""
>
> # Retrieve the scan chain config and zap the ad-hoc length encoding
> sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}' \
> - ${in_dir}/generated/iocsr_config_${soc}.c
> + ${in_bsp_dir}/generated/iocsr_config_${soc}.c
>
> cat << EOF
>
> @@ -49,8 +51,9 @@ EOF
> #
> process_pinmux_config() {
> soc="$1"
> - in_dir="$2"
> - out_dir="$3"
> + in_qts_dir="$2"
> + in_bsp_dir="$3"
> + out_dir="$4"
>
> (
> cat << EOF
> @@ -67,7 +70,7 @@ EOF
>
> # Retrieve the pinmux config and zap the ad-hoc length encoding
> sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned
> long/const u8/};p;n;b next}' \
> - ${in_dir}/generated/pinmux_config_${soc}.c
> + ${in_bsp_dir}/generated/pinmux_config_${soc}.c
>
> cat << EOF
>
> @@ -84,8 +87,9 @@ EOF
> #
> process_pll_config() {
> soc="$1"
> - in_dir="$2"
> - out_dir="$3"
> + in_qts_dir="$2"
> + in_bsp_dir="$3"
> + out_dir="$4"
>
> (
> cat << EOF
> @@ -102,7 +106,7 @@ EOF
>
> # Retrieve the pll config and zap parenthesis
> sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b
> next}' \ -${in_dir}/generated/pll_config.h
> + ${in_bsp_dir}/generated/pll_config.h
>
> cat << EOF
>
> @@ -126,8 +130,9 @@ grep_sdram_config() {
> #
> process_sdram_config() {
> soc="$1"
> - in_dir="$2"
> - out_dir="$3"
> + in_qts_dir="$2"
> + in_bsp_dir="$3"
> + out_dir="$4"
>
> (
> cat << EOF
> @@ -144,29 +149,29 @@ EOF
>
> echo "/* SDRAM configuration */"
> # Retrieve the sdram config, zap broken lines and zap parenthesis
> - sed -n "/$/ {N;s/ \n/\t/};p"
> ${in_dir}/generated/sdram/sdram_config.h | + sed -n "/$/ {N;s/
> \n/\t/};p" ${in_bsp_dir}/generated/sdram/sdram_config.h | sed -n
> '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' |
> sort -u | grep_sdram_config
>
> echo ""
> echo "/* Sequencer auto configuration */"
> sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}"\
> - ${in_dir}/hps_isw_handoff/*/sequencer_auto.h | sort -u |
> grep_sdram_config +
> ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto.h
|
> sort -u | grep_sdram_config
>
> echo ""
> echo "/* Sequencer defines configuration */"
> sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \
> - ${in_dir}/hps_isw_handoff/*/sequencer_defines.h | sort -u |
> grep_sdram_config +
${in_qts_dir}/hps_isw_handoff/*/sequencer_defines.h |
> sort -u | grep_sdram_config
>
> echo ""
> echo "/* Sequencer ac_rom_init configuration */"
> sed -n '/^const.*\[/ !b; :next {/^const.*\[/
> {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
> - ${in_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c
> + ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c
>
> echo ""
> echo "/* Sequencer inst_rom_init configuration */"
> sed -n '/^const.*\[/ !b; :next {/^const.*\[/
> {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
> - ${in_dir}/hps_isw_handoff/*/seque
Re: [U-Boot] [PATCH] socfpga: Modify qts-filter args to allow input for bsp generated files and quartus project directories
On Monday, January 11, 2016 at 11:28:37 PM, Dalon Westergreen wrote:
Please add a commit message explaining why this change is needed. I have no
comments about the patch, so just add my
Acked-by: Marek Vasut
when you repost. I will pick it for the next release.
Also, it's a good idea to CC Dinh and Chin.
> Signed-off-by: Dalon Westergreen
> ---
> arch/arm/mach-socfpga/qts-filter.sh | 69
> - 1 file changed, 38 insertions(+), 31
> deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/qts-filter.sh
> b/arch/arm/mach-socfpga/qts-filter.sh index c1640bc..835ca2c 100755
> --- a/arch/arm/mach-socfpga/qts-filter.sh
> +++ b/arch/arm/mach-socfpga/qts-filter.sh
> @@ -3,13 +3,15 @@
> #
> # Process iocsr_config_*.[ch]
> # $1:SoC type
> -# $2:Input directory
> -# $3:Output directory
> +# $2:Input handoff directory
> +# $3:Input BSP Generated directory
> +# $4:Output directory
> #
> process_iocsr_config() {
> soc="$1"
> - in_dir="$2"
> - out_dir="$3"
> + in_qts_dir="$2"
> + in_bsp_dir="$3"
> + out_dir="$4"
>
> (
> cat << EOF
> @@ -26,13 +28,13 @@ EOF
>
> # Retrieve the scan chain lengths
> grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' \
> - ${in_dir}/generated/iocsr_config_${soc}.h | tr -d "()"
> + ${in_bsp_dir}/generated/iocsr_config_${soc}.h | tr -d "()"
>
> echo ""
>
> # Retrieve the scan chain config and zap the ad-hoc length encoding
> sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}' \
> - ${in_dir}/generated/iocsr_config_${soc}.c
> + ${in_bsp_dir}/generated/iocsr_config_${soc}.c
>
> cat << EOF
>
> @@ -49,8 +51,9 @@ EOF
> #
> process_pinmux_config() {
> soc="$1"
> - in_dir="$2"
> - out_dir="$3"
> + in_qts_dir="$2"
> + in_bsp_dir="$3"
> + out_dir="$4"
>
> (
> cat << EOF
> @@ -67,7 +70,7 @@ EOF
>
> # Retrieve the pinmux config and zap the ad-hoc length encoding
> sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned
> long/const u8/};p;n;b next}' \
> - ${in_dir}/generated/pinmux_config_${soc}.c
> + ${in_bsp_dir}/generated/pinmux_config_${soc}.c
>
> cat << EOF
>
> @@ -84,8 +87,9 @@ EOF
> #
> process_pll_config() {
> soc="$1"
> - in_dir="$2"
> - out_dir="$3"
> + in_qts_dir="$2"
> + in_bsp_dir="$3"
> + out_dir="$4"
>
> (
> cat << EOF
> @@ -102,7 +106,7 @@ EOF
>
> # Retrieve the pll config and zap parenthesis
> sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b
> next}' \ -${in_dir}/generated/pll_config.h
> + ${in_bsp_dir}/generated/pll_config.h
>
> cat << EOF
>
> @@ -126,8 +130,9 @@ grep_sdram_config() {
> #
> process_sdram_config() {
> soc="$1"
> - in_dir="$2"
> - out_dir="$3"
> + in_qts_dir="$2"
> + in_bsp_dir="$3"
> + out_dir="$4"
>
> (
> cat << EOF
> @@ -144,29 +149,29 @@ EOF
>
> echo "/* SDRAM configuration */"
> # Retrieve the sdram config, zap broken lines and zap parenthesis
> - sed -n "/$/ {N;s/ \n/\t/};p"
> ${in_dir}/generated/sdram/sdram_config.h | + sed -n "/$/ {N;s/
> \n/\t/};p" ${in_bsp_dir}/generated/sdram/sdram_config.h | sed -n
> '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' |
> sort -u | grep_sdram_config
>
> echo ""
> echo "/* Sequencer auto configuration */"
> sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}"\
> - ${in_dir}/hps_isw_handoff/*/sequencer_auto.h | sort -u |
> grep_sdram_config +
> ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto.h
|
> sort -u | grep_sdram_config
>
> echo ""
> echo "/* Sequencer defines configuration */"
> sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \
> - ${in_dir}/hps_isw_handoff/*/sequencer_defines.h | sort -u |
> grep_sdram_config +
${in_qts_dir}/hps_isw_handoff/*/sequencer_defines.h |
> sort -u | grep_sdram_config
>
> echo ""
> echo "/* Sequencer ac_rom_init configuration */"
> sed -n '/^const.*\[/ !b; :next {/^const.*\[/
> {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
> - ${in_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c
> + ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c
>
> echo ""
> echo "/* Sequencer inst_rom_init configuration */"
> sed -n '/^const.*\[/ !b; :next {/^const.*\[/
> {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
> - ${in_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c
> + ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c
>
> cat << EOF
>
> @@ -176,30 +181,32 @@ EOF
> }
>
> usage() {
> - echo "$0 [soc_type] [input_dir] [output_di
Re: [U-Boot] [ANN] U-Boot v2016.01-rc4 released
On Mon, Jan 11, 2016 at 04:19:49PM -0200, Fabio Estevam wrote: > Hi Wolfgang, > > On Thu, Jan 7, 2016 at 2:43 PM, Wolfgang Denk wrote: > > > Sorry for the delay. I used the Xmas break to update our machines to > > FC23, and for some unclear reason the Inotify System Scheduler stopped > > running. I restarted it now, and all data should be up to date now. > > > > Sorry for causing and not noticing this problem. > > We still see http://git.denx.de/?p=u-boot.git;a=summary not in sync > with https://github.com/u-boot/u-boot/commits/master Yeah, it's still not working. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 09/16] ehci: Add support for Qualcomm EHCI
On Monday, January 11, 2016 at 10:39:46 PM, Mateusz Kulikowski wrote:
> On 06.01.2016 22:04, Marek Vasut wrote:
> > On Wednesday, January 06, 2016 at 07:21:21 PM, Mateusz Kulikowski wrote:
> >> This driver is able to reconfigure OTG controller into HOST mode.
> >> Board can add board-specific initialization as board_prepare_usb().
> >> It requires USB_ULPI_VIEWPORT enabled in board configuration.
> >>
> >> Signed-off-by: Mateusz Kulikowski
> >
> > [...]
> >
> >> +static int msm_init_after_reset(struct ehci_ctrl *dev)
> >> +{
> >> + struct msm_ehci_priv *p = container_of(dev, struct msm_ehci_priv,
> >> ctrl); + struct usb_ehci *ehci = p->ehci;
> >> +
> >> + /* select ULPI phy */
> >> + writel(0x8000, &ehci->portsc);
> >
> > Don't we have macro for this bit ?
>
> hmhm.. I need spoiler..
>
> Did you meant EHCI_PS_* series of #defines from ehci.h?
>
> This bit is not there (header was probably based on EHCI 1.0 spec, where
> this bit was reserved). Of course I can add it there and use here :)
More like include/usb/ehci-fsl.h , there's a bit for it.
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v1 16/16] board: Add Qualcomm Dragonboard 410C support
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
Hi,
On 11.01.2016 17:58, Simon Glass wrote:
> Hi,
>
> On 6 January 2016 at 11:21, Mateusz Kulikowski
> wrote:
>> This commit add support for 96Boards Dragonboard410C.
[...]
>> + usb_hub_reset_n_pm {
>> + gpios = <&pmic_gpios 2 0>;
>> + };
>> +
>> + usb_sw_sel_pm {
>> + gpios = <&pmic_gpios 3 0>;
>> + };
>> +
>> + key_vol_down {
>> + gpios = <&pmic_pon 1 0>;
>> + };
>> +
>> + key_power {
>> + gpios = <&pmic_pon 0 0>;
>> + };
>
> The above four nodes seems odd in that they don't have compatible
> strings. Is this how Linux does it? Also more normally the node name
> has hyphens rather than underscores.
In Linux nodes are childs of PMIC gpio periperhal (pmic_gpios in my case):
&pm8916_gpios {
usb_hub_reset_pm: usb_hub_reset_pm {
pinconf {
pins = "gpio3";
function = PMIC_GPIO_FUNC_NORMAL;
output-low;
};
};
(https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi)
I decided to move them away from PMIC, as they only use specific gpios.
To be honest they are just a references so I don't have to hardcode gpio
names/numbers in
board sources.
Is it ok if I keep it that way? Could you suggest better approach?
Regards,
Mateusz
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Re: [U-Boot] [PATCH v1 16/16] board: Add Qualcomm Dragonboard 410C support
-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 Hi, On 07.01.2016 11:23, Sjoerd Simons wrote: > On Wed, 2016-01-06 at 19:21 +0100, Mateusz Kulikowski wrote: >> This commit add support for 96Boards Dragonboard410C. >> >> diff --git a/include/configs/dragonboard410c.h >> b/include/configs/dragonboard410c.h >> new file mode 100644 >> index 000..91f0e02 >> --- /dev/null >> +++ b/include/configs/dragonboard410c.h >> @@ -0,0 +1,182 @@ >> +/* >> + * Board configuration file for Dragonboard 410C >> + * >> + * (C) Copyright 2015 Mateusz Kulikowski > om> >> + * >> + * SPDX-License-Identifier: GPL-2.0+ >> + */ >> + >> +#ifndef __CONFIGS_DRAGONBOARD410C_H >> +#define __CONFIGS_DRAGONBOARD410C_H >> + >> +#include >> +#include >> + >> +#define CONFIG_IDENT_STRING "\nQualcomm-DragonBoard >> 410C" >> + >> +#define CONFIG_MISC_INIT_R /* To stop autoboot */ >> + >> +/* Flat Device Tree Definitions */ >> +#define CONFIG_OF_LIBFDT >> + >> +/* Physical Memory Map */ >> +#define CONFIG_NR_DRAM_BANKS1 >> +#define PHYS_SDRAM_10x8000 >> +/* 1008 MB (the last ~30Mb are secured for TrustZone by ATF*/ >> +#define PHYS_SDRAM_1_SIZE 0x3da0 >> +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 >> +#define CONFIG_SYS_TEXT_BASE0x8008 >> +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BAS >> E + 0x7fff0) >> +#define CONFIG_SYS_LOAD_ADDR(CONFIG_SYS_SDRAM_BASE + >> 0x8) >> +#define CONFIG_SYS_BOOTM_LEN0x100 /* 16MB max >> kernel size */ >> + >> +/* UART */ >> +#define CONFIG_BAUDRATE 115200 >> + >> +/* Generic Timer Definitions */ >> +#define COUNTER_FREQUENCY 1900 >> + >> +/* This are needed to have proper mmc support */ >> +#define CONFIG_MMC >> +#define CONFIG_GENERIC_MMC >> +#define CONFIG_SDHCI >> + >> +#define CONFIG_SYS_LDSCRIPT "board/qualcomm/dragonboard410c/u- >> boot.lds" >> + >> +/* Fixup - in init code we switch from device to host mode, >> + * it has to be done after each HCD reset */ >> +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET >> + >> +#define CONFIG_USB_HOST_ETHER /* Enable USB Networking */ >> + >> +/* Support all possible USB ethernet dongles */ >> +#define CONFIG_USB_ETHER_DM9601 >> +#define CONFIG_USB_ETHER_ASIX >> +#define CONFIG_USB_ETHER_ASIX88179 >> +#define CONFIG_USB_ETHER_MCS7830 >> +#define CONFIG_USB_ETHER_SMSC95XX >> + >> +/* Libraries */ >> +#define CONFIG_MD5 >> + >> +/* Extra Commands */ >> +#define CONFIG_CMD_CACHE >> +#define CONFIG_CMD_DHCP >> +#define CONFIG_CMD_ENV >> +#define CONFIG_CMD_FAT /* FAT support >> */ >> +#define CONFIG_CMD_GPIO >> +#define CONFIG_CMD_GPT >> +#define CONFIG_CMD_MD5SUM >> +#define CONFIG_CMD_MEMINFO /* meminfo >> */ >> +#define CONFIG_CMD_MMC >> +/* Enable that for switching of boot partitions */ >> +/* Disabled by default as some sub-commands can brick eMMC */ >> +/*#define CONFIG_SUPPORT_EMMC_BOOT */ >> +#define CONFIG_CMD_PART >> +#define CONFIG_CMD_PING >> +#define CONFIG_CMD_REGINFO /* Register dump*/ >> +#define CONFIG_CMD_TFTP >> +#define CONFIG_CMD_TIMER >> +#define CONFIG_CMD_UNZIP >> +#define CONFIG_CMD_BOOTZ >> +#define CONFIG_CMD_BOOT > > Using config_distro_defaults would give you a nice set of default > commands to include. May make sense to use that and drop the > duplicates. Will do > > Also the 410C is 64 bit arm afaik, so i would hvae expected _CMD_BOOTI > rather then _CMD_BOOTZ Booti is there as well; I'll drop bootz for now (I think I added it very early, before I knew u-boot has different command for Images and forgot to remove it). Perhaps later I'll make option to boot 32bit images and then it may be helpful. But it's bigger task so let's forget about that for now :) > > >> + >> +/* Command line configuration */ >> +#define CONFIG_MENU >> +#define CONFIG_SYS_LONGHELP >> + >> +/* Partition table support */ >> +#define HAVE_BLOCK_DEVICE /* Needed for partition commands */ >> +#define CONFIG_DOS_PARTITION >> +#define CONFIG_EFI_PARTITION >> +#define CONFIG_PARTITION_UUIDS >> + >> +/* BOOTP options */ >> +#define CONFIG_BOOTP_BOOTFILESIZE >> + >> +/* Environment - Boot*/ >> +#define CONFIG_BOOTDELAY2 /* autoboot after 2 >> seconds */ >> + >> +#define CONFIG_NFSBOOTCOMMAND "" >> +#define CONFIG_BOOTCOMMAND "usb start && dhcp && tftp && usb stop && >> bootm" > > Any reason for a custom default bootcmd rather then > using config_distro_bootcmd ? (Especially for board like the 96boards > ones it seems quite useful to use a standardized boot sequence). Just personal preferences; Will adjust environment to hikey so we will have unification. Regards and thanks for hints, Mateusz -BEGIN PGP SIGNATURE- Version: GnuPG v2 iQEcBAEBCAAGBQJWlCNsAAoJELvtohmVtQzBcz4IAIoN+mFOf8KVx7dfi3VCVxvn D6W0qAT0DawbRraWeLlIGkTXD+BJzeCK4FNxjeTO0o/OTcAWxfY7hIlNanwEpsSd t2WBZeXGgruVIVwCc
Re: [U-Boot] [PATCH v1 10/16] drivers: Add SPMI bus uclass
-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 Hi Simon , On 11.01.2016 17:57, Simon Glass wrote: [...] >> @@ -0,0 +1,10 @@ >> +menu "SPMI support" >> + >> +config DM_SPMI > > Can we just use SPMI, or is that is use? We want to remove all the DM_ > options when everything is converted to driver model. So if you are > adding a new class you should be able to avoid the DM_ prefix. Sure, I thought it's mandatory :) [..] >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include > > http://www.denx.de/wiki/U-Boot/CodingStyle > > common.h > dm.h > errno.h > dm/... > spmi/... > linux/... Oops, this slipped - my bad Regards, Mateusz -BEGIN PGP SIGNATURE- Version: GnuPG v2 iQEcBAEBCAAGBQJWlCGaAAoJELvtohmVtQzB8HsH/2C5C6qWhUpBlXiyhXLBa7TG 6KWy+NwrGdadwi1IT/UiBbryM7O6YT+H/Ey7MIfC0VNyhPnSiMimCYH7RQoNtoYT lA5QUb1FAAvVbyypD9t0CRl32uORbG/2WocDdPbAjyTJp3/GldwZ0ZjeQo2uOedv zUmwEmMiylff7m2wjD4EhEJayyTF/8oVCaqH4OtlxwupIHMgekPNUBjtW5VfjPMP oldrwD2k2nbAj7Y91nxKPQiMgql4eOdXQCnwkW4ovz6wB1jb9/b8d42W75rhFoDu 2FRcP6NWR9XurMQIjtSz7O587UrGWrKm4ts7MjjhMMt4aPjDVNd+9CE+R8mEu3A= =gUUy -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 09/16] ehci: Add support for Qualcomm EHCI
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
On 06.01.2016 22:04, Marek Vasut wrote:
> On Wednesday, January 06, 2016 at 07:21:21 PM, Mateusz Kulikowski wrote:
>> This driver is able to reconfigure OTG controller into HOST mode.
>> Board can add board-specific initialization as board_prepare_usb().
>> It requires USB_ULPI_VIEWPORT enabled in board configuration.
>>
>> Signed-off-by: Mateusz Kulikowski
>
> [...]
>
>> +static int msm_init_after_reset(struct ehci_ctrl *dev)
>> +{
>> +struct msm_ehci_priv *p = container_of(dev, struct msm_ehci_priv, ctrl);
>> +struct usb_ehci *ehci = p->ehci;
>> +
>> +/* select ULPI phy */
>> +writel(0x8000, &ehci->portsc);
>
> Don't we have macro for this bit ?
hmhm.. I need spoiler..
Did you meant EHCI_PS_* series of #defines from ehci.h?
This bit is not there (header was probably based on EHCI 1.0 spec, where this
bit was reserved).
Of course I can add it there and use here :)
Regards,
Mateusz
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Re: [U-Boot] [PATCH v1 05/16] usb: ulpi: Add Kconfig options for ULPI
-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 On 08.01.2016 00:18, Simon Glass wrote: > Hi, > > On 7 January 2016 at 15:12, Mateusz Kulikowski [...] >>> On Wednesday, January 06, 2016 at 07:21:17 PM, Mateusz Kulikowski wrote: The following options can be now enabled via defconfig: - CONFIG_USB_ULPI - CONFIG_USB_ULPI_VIEWPORT - CONFIG_USB_ULPI_VIEWPORT_OMAP >> [...] >> +++ b/drivers/usb/ulpi/Kconfig @@ -0,0 +1,10 @@ +comment "ULPI drivers" + +config USB_ULPI +bool + +config USB_ULPI_VIEWPORT +bool + +config USB_ULPI_VIEWPORT_OMAP +bool >>> >>> Description of these options is missing. >> >> My intention here was to keep it away from "users". >> >> This options are not "optional" in any way. >> They are rather like CPU_something or VBAR_something, >> that is - they are required and should be selected by drivers that use them, >> but without this drivers, they are useless. > > Perhaps we don't need the options at all then? > > But there are lots of users in the tree. You should use the > moveconfig.py script to move them all to Kconfig. > >> >> But maybe I'm missing something :) >> If anyone insists on that - I'll make them visible and add description. > > Please add detailed help for all Kconfig options you add. Will add descriptions as big as I'm able to. Regards, Mateusz ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 02/16] gpio: Add support for Qualcomm gpio controller
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
On 11.01.2016 17:57, Simon Glass wrote:
> Hi,
>
> On 6 January 2016 at 11:21, Mateusz Kulikowski
> wrote:
[...]
>> +static int msm_gpio_get_function(struct udevice *dev, unsigned offset)
>> +{
>> + struct msm_gpio_bank *priv = dev_get_priv(dev);
>> +
>> + if (readl(priv->base + GPIO_CONFIG_OFF(offset)) & GPIO_OE_ENABLE)
>> + return GPIOF_OUTPUT;
>> + return GPIOF_INPUT;
>
> Can it ever be GPIOF_FUNCTION?
For now - not (at least not until I implement pin multiplexing).
This may change once I upgrade the code to replace LittleKernel/fastboot.
[...]
>> +{
>> + struct msm_gpio_bank *priv = dev_get_priv(dev);
>> +
>> + priv->base = dev_get_addr(dev);
>> + return priv->base == FDT_ADDR_T_NONE;
>
> Maybe you mean:
>
> return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
Yes I meant that :)
Regards,
Mateusz
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Re: [U-Boot] [PATCH] dm: test: usb: Update the USB tests so that they all pass
On Thu, Jan 07, 2016 at 10:23:42AM -0700, Simon Glass wrote: > Due to a limitation removed in an earlier patch, USB tests were not seeing > all the devices. Update the tests to pass now that all devices are visible. > > Signed-off-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] mx25pdk: Remove lowlevel_init.S file
From: Fabio Estevam
As the lowlevel_init function is empty we should better
remove this assembly file entirely and use a dummy C
function instead.
Signed-off-by: Fabio Estevam
---
board/freescale/mx25pdk/Makefile| 1 -
board/freescale/mx25pdk/lowlevel_init.S | 10 --
board/freescale/mx25pdk/mx25pdk.c | 3 +++
3 files changed, 3 insertions(+), 11 deletions(-)
delete mode 100644 board/freescale/mx25pdk/lowlevel_init.S
diff --git a/board/freescale/mx25pdk/Makefile b/board/freescale/mx25pdk/Makefile
index 0b288f2..02085b6 100644
--- a/board/freescale/mx25pdk/Makefile
+++ b/board/freescale/mx25pdk/Makefile
@@ -7,4 +7,3 @@
#
obj-y := mx25pdk.o
-obj-y += lowlevel_init.o
diff --git a/board/freescale/mx25pdk/lowlevel_init.S
b/board/freescale/mx25pdk/lowlevel_init.S
deleted file mode 100644
index 8c581b5..000
--- a/board/freescale/mx25pdk/lowlevel_init.S
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * Copyright (c) 2011 Freescale Semiconductor
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
- mov pc, lr
diff --git a/board/freescale/mx25pdk/mx25pdk.c
b/board/freescale/mx25pdk/mx25pdk.c
index 01dac72..788d3c3 100644
--- a/board/freescale/mx25pdk/mx25pdk.c
+++ b/board/freescale/mx25pdk/mx25pdk.c
@@ -186,3 +186,6 @@ int checkboard(void)
return 0;
}
+
+/* Lowlevel init isn't used on mx25pdk, so just provide a dummy one here */
+void lowlevel_init(void) {}
--
1.9.1
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Re: [U-Boot] [ANN] U-Boot v2016.01-rc4 released
Hi Wolfgang, On Thu, Jan 7, 2016 at 2:43 PM, Wolfgang Denk wrote: > Sorry for the delay. I used the Xmas break to update our machines to > FC23, and for some unclear reason the Inotify System Scheduler stopped > running. I restarted it now, and all data should be up to date now. > > Sorry for causing and not noticing this problem. We still see http://git.denx.de/?p=u-boot.git;a=summary not in sync with https://github.com/u-boot/u-boot/commits/master Regards, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] MAINTAINERS/mailmap: Update my email address
On Mon, 2016-01-11 at 14:19 +0100, Stefano Babic wrote: > Hi Fabio, > > On 11/01/2016 13:22, Fabio Estevam wrote: > > Update my email address to the NXP account. > > > > Signed-off-by: Fabio Estevam > > --- > > .mailmap | 2 +- > > board/freescale/mx25pdk/MAINTAINERS | 2 +- > > board/freescale/mx28evk/MAINTAINERS | 2 +- > > board/freescale/mx53ard/MAINTAINERS | 2 +- > > board/freescale/mx53smd/MAINTAINERS | 2 +- > > board/freescale/mx6qsabreauto/MAINTAINERS | 2 +- > > board/freescale/mx6sabresd/MAINTAINERS| 2 +- > > board/freescale/mx6slevk/MAINTAINERS | 2 +- > > board/freescale/mx6sxsabresd/MAINTAINERS | 2 +- > > board/solidrun/mx6cuboxi/MAINTAINERS | 2 +- > > board/udoo/MAINTAINERS| 2 +- > > board/wandboard/MAINTAINERS | 2 +- > > 12 files changed, 12 insertions(+), 12 deletions(-) > > > > diff --git a/.mailmap b/.mailmap > > index c7bb0ef..02dccfc 100644 > > --- a/.mailmap > > +++ b/.mailmap > > @@ -12,7 +12,7 @@ Allen Martin > > Andreas Bießmann > > Aneesh V > > Dirk Behme > > -Fabio Estevam > > +Fabio Estevam > > Thanks - I ask all other Freescalers whose name is in a MAINTAINERS > file. Should you update your e-mail address as well ? Maybe do we > replace any occurence ofFreescale with NXP ? Don't search/replace -- the local part may be different (e.g. I was scottw...@freescale.com but my NXP local part is scott.wood). The Freescale addresses still work. Also, I won't be using NXP's mail system for community interaction, so mine should be changed to o...@buserror.net. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] net: phy: genphy: Allow overwriting features
Hi Joe, On Mon, 2016-01-11 at 11:55 -0600, Joe Hershberger wrote: > Hi Alexey, > > On Mon, Jan 11, 2016 at 11:50 AM, Alexey Brodkin > wrote: > > Hi Joe, > > > > On Mon, 2016-01-11 at 10:54 -0600, Joe Hershberger wrote: > > > Hi Alexey, > > > > > > On Mon, Jan 11, 2016 at 3:45 AM, Alexey Brodkin > > > wrote: > > > > Hi Joe, > > > > > > > > On Wed, 2015-12-23 at 19:44 +0300, Alexey Brodkin wrote: > > > > > From: Sascha Hauer > > > > > > > > > > of_set_phy_supported allows overwiting hardware capabilities of > > > > > a phy with values from the devicetree. This does not work with > > > > > the genphy driver though because the genphys config_init function > > > > > will overwrite all values adjusted by of_set_phy_supported. Fix > > > > > this by initialising the genphy features in the phy_driver struct > > > > > and in config_init just limit the features to the ones the hardware > > > > > can actually support. The resulting features are a subset of the > > > > > devicetree specified features and the hardware features. > > > > > > > > > > This is a copy of the patch from Linux kernel, see > > > > > http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=c242a47238fa2a6a54af8a16e62b54e6e031 > > > > > d4bc > > > > > > > > > > Signed-off-by: Sascha Hauer > > > > > Signed-off-by: Alexey Brodkin > > > > > Cc: Joe Hershberger > > > > > --- > > > > > > > > Any chance for that one to be applied? > > > > > > I'll review when the merge window opens. > > > > > > > This patch is required to implement phy max > > > > speed limitation by subsequent patches. > > > > > > Any reason you did not send as a series if there are dependencies? > > > > I thought about putting some of those patches in one series initially but > > then > > decided to send them separately. > > > > Even though together they solve one particular problem (ability to > > set phy speed limit) they are a bit different by their nature. > > > > http://patchwork.ozlabs.org/patch/560608/, > > http://patchwork.ozlabs.org/patch/560634/ and > > http://patchwork.ozlabs.org/patch/560635/ are back-ports from Linux kernel > > and could be actually applied separately because they are not related to > > each other. > > > > Following two are really preparatory for implementing capping: > > http://patchwork.ozlabs.org/patch/560636/ > > http://patchwork.ozlabs.org/patch/560637/ > > > > ...in patch I actually forgot to send out... (will do it shortly). > > > > And finally http://patchwork.ozlabs.org/patch/560638/ really a plain fix > > for DW GMAC driver which may happen in case of phy force set lower than > > possible. So it will easily manifest if all above is applied. > > > > That said it was conscious decision but probably incorrect one. > > > > If you do think it all fits well in a series I'll re-send it that way. > > If there is no build or functionality breaking order dependency then > it's ok that they are not in a series. If there is any dependency like > that, then I would appreciate a series so that I know what order to > apply them without having to figure it out. Ok then I'll re-send them all as a series now. -Alexey ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] net: phy: genphy: Allow overwriting features
Hi Alexey, On Mon, Jan 11, 2016 at 11:50 AM, Alexey Brodkin wrote: > Hi Joe, > > On Mon, 2016-01-11 at 10:54 -0600, Joe Hershberger wrote: >> Hi Alexey, >> >> On Mon, Jan 11, 2016 at 3:45 AM, Alexey Brodkin >> wrote: >> > Hi Joe, >> > >> > On Wed, 2015-12-23 at 19:44 +0300, Alexey Brodkin wrote: >> > > From: Sascha Hauer >> > > >> > > of_set_phy_supported allows overwiting hardware capabilities of >> > > a phy with values from the devicetree. This does not work with >> > > the genphy driver though because the genphys config_init function >> > > will overwrite all values adjusted by of_set_phy_supported. Fix >> > > this by initialising the genphy features in the phy_driver struct >> > > and in config_init just limit the features to the ones the hardware >> > > can actually support. The resulting features are a subset of the >> > > devicetree specified features and the hardware features. >> > > >> > > This is a copy of the patch from Linux kernel, see >> > > http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=c242a47238fa2a6a54af8a16e62b54e6e031d4bc >> > > >> > > Signed-off-by: Sascha Hauer >> > > Signed-off-by: Alexey Brodkin >> > > Cc: Joe Hershberger >> > > --- >> > >> > Any chance for that one to be applied? >> >> I'll review when the merge window opens. >> >> > This patch is required to implement phy max >> > speed limitation by subsequent patches. >> >> Any reason you did not send as a series if there are dependencies? > > I thought about putting some of those patches in one series initially but then > decided to send them separately. > > Even though together they solve one particular problem (ability to > set phy speed limit) they are a bit different by their nature. > > http://patchwork.ozlabs.org/patch/560608/, > http://patchwork.ozlabs.org/patch/560634/ and > http://patchwork.ozlabs.org/patch/560635/ are back-ports from Linux kernel > and could be actually applied separately because they are not related to > each other. > > Following two are really preparatory for implementing capping: > http://patchwork.ozlabs.org/patch/560636/ > http://patchwork.ozlabs.org/patch/560637/ > > ...in patch I actually forgot to send out... (will do it shortly). > > And finally http://patchwork.ozlabs.org/patch/560638/ really a plain fix > for DW GMAC driver which may happen in case of phy force set lower than > possible. So it will easily manifest if all above is applied. > > That said it was conscious decision but probably incorrect one. > > If you do think it all fits well in a series I'll re-send it that way. If there is no build or functionality breaking order dependency then it's ok that they are not in a series. If there is any dependency like that, then I would appreciate a series so that I know what order to apply them without having to figure it out. Thanks, -Joe ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 0/9] MIPS: sync asm header files with linux-4.4
Am Montag, den 11.01.2016, 22:29 +0800 schrieb Wills Wang: > > On 01/11/2016 06:55 PM, Purna Chandra Mandal wrote: > > On 01/09/2016 10:02 PM, Daniel Schwierzeck wrote: > > > > > This patch series updates all MIPS asm header files containing > > > I/O code as well as processor, register and assembly definitions. > > > The source of the update are the MIPS asm header files of linux > > > -4.4. > > > > > > The main goal is to get a complete set of I/O accessors on MIPS > > > and > > > to support platform-specific address spaces and mappings. Also a > > > working ioremap() implementation will be added, which supports > > > platform-specific callbacks. Furthermore support for bit > > > manipulating > > > I/O accessors (clrbits_X, setbits_X, clrsetbits_X) will be added. > > > > > > The patch series is also available on git://git.denx.de/u-boot > > > -mips.git > > > in branch mips_io_v1 and based on next branch. > > > > > > @Wills > > > I changed map_physmem() and used the new and working ioremap() > > > function. > > > Thus you can discard your patch. > > > > > > @Wills, Purna > > > You can use now ioremap() directly in your drivers. You can also > > > use the > > > new bit manipulating I/O accessors as requested by Marek. Please > > > rebase > > > and test your patch series against this series, thanks. > > Thanks Daniel. > > Rebased my PIC32 patches on 'mips_io_v1' branch and tested > > functionality to work fine. > > Also updated drivers to use ioremap() (instead of pic32_ioremap()) > > and clrsetbits_le() > > wherever applicable. > > > Should we use these macros with the explicitly endianess in driver? > if > chip can > select big-endian and little-endian by hardware pin, i think driver > may > not work > properly, what's your idea? that depends on the SoC and the peripheral. Peripherals usually have a fixed endianess and the bus between CPU and peripheral converts the CPU endianess to peripheral one in hardware. In that case a driver should never swap. You could use the __raw_readX/__raw_writeX variants. Or you could implement this explicitely with readX/writeX resp. readX_be/writeX_be and make this configurable at compile time or runtime. For an example you could look at kernel commit 37786c7fee40771d13901de129af7e084ed48b55. If the bus does not convert the endianess, a driver must explicitely use I/O accessors according to the peripheral endianess. -- - Daniel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] net/designware: add support of max-speed device tree property
This property allows to specify fastest connection mode supported by
the MAC (as opposed to features of the phy).
There are situations when phy may handle faster modes than the
MAC (or even it's particular implementation or even due to CPU being too
slow).
This property is a standard one in Linux kernel these days and some
boards do already use it in their device tree descriptions.
Signed-off-by: Alexey Brodkin
Cc: Joe Hershberger
---
drivers/net/designware.c | 14 +-
drivers/net/designware.h | 1 +
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 39c7279..66dc701 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -406,7 +406,7 @@ static int _dw_free_pkt(struct dw_eth_dev *priv)
static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
{
struct phy_device *phydev;
- int mask = 0x;
+ int mask = 0x, ret;
#ifdef CONFIG_PHY_ADDR
mask = 1 << CONFIG_PHY_ADDR;
@@ -419,6 +419,11 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
phy_connect_dev(phydev, dev);
phydev->supported &= PHY_GBIT_FEATURES;
+ if (priv->max_speed) {
+ ret = phy_set_supported(phydev, priv->max_speed);
+ if (ret)
+ return ret;
+ }
phydev->advertising = phydev->supported;
priv->phydev = phydev;
@@ -601,6 +606,7 @@ static int designware_eth_probe(struct udevice *dev)
priv->mac_regs_p = (struct eth_mac_regs *)iobase;
priv->dma_regs_p = (struct eth_dma_regs *)(iobase + DW_DMA_BASE_OFFSET);
priv->interface = pdata->phy_interface;
+ priv->max_speed = pdata->max_speed;
dw_mdio_init(dev->name, priv->mac_regs_p);
priv->bus = miiphy_get_dev_by_name(dev->name);
@@ -635,6 +641,7 @@ static int designware_eth_ofdata_to_platdata(struct udevice
*dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
const char *phy_mode;
+ const fdt32_t *cell;
pdata->iobase = dev_get_addr(dev);
pdata->phy_interface = -1;
@@ -646,6 +653,11 @@ static int designware_eth_ofdata_to_platdata(struct
udevice *dev)
return -EINVAL;
}
+ pdata->max_speed = 0;
+ cell = fdt_getprop(gd->fdt_blob, dev->of_offset, "max-speed", NULL);
+ if (cell)
+ pdata->max_speed = fdt32_to_cpu(*cell);
+
return 0;
}
diff --git a/drivers/net/designware.h b/drivers/net/designware.h
index 4b9ec39..ed6344c 100644
--- a/drivers/net/designware.h
+++ b/drivers/net/designware.h
@@ -223,6 +223,7 @@ struct dw_eth_dev {
char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
u32 interface;
+ u32 max_speed;
u32 tx_currdescnum;
u32 rx_currdescnum;
--
2.4.3
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Re: [U-Boot] [PATCH] net: phy: genphy: Allow overwriting features
Hi Joe, On Mon, 2016-01-11 at 10:54 -0600, Joe Hershberger wrote: > Hi Alexey, > > On Mon, Jan 11, 2016 at 3:45 AM, Alexey Brodkin > wrote: > > Hi Joe, > > > > On Wed, 2015-12-23 at 19:44 +0300, Alexey Brodkin wrote: > > > From: Sascha Hauer > > > > > > of_set_phy_supported allows overwiting hardware capabilities of > > > a phy with values from the devicetree. This does not work with > > > the genphy driver though because the genphys config_init function > > > will overwrite all values adjusted by of_set_phy_supported. Fix > > > this by initialising the genphy features in the phy_driver struct > > > and in config_init just limit the features to the ones the hardware > > > can actually support. The resulting features are a subset of the > > > devicetree specified features and the hardware features. > > > > > > This is a copy of the patch from Linux kernel, see > > > http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=c242a47238fa2a6a54af8a16e62b54e6e031d4bc > > > > > > Signed-off-by: Sascha Hauer > > > Signed-off-by: Alexey Brodkin > > > Cc: Joe Hershberger > > > --- > > > > Any chance for that one to be applied? > > I'll review when the merge window opens. > > > This patch is required to implement phy max > > speed limitation by subsequent patches. > > Any reason you did not send as a series if there are dependencies? I thought about putting some of those patches in one series initially but then decided to send them separately. Even though together they solve one particular problem (ability to set phy speed limit) they are a bit different by their nature. http://patchwork.ozlabs.org/patch/560608/, http://patchwork.ozlabs.org/patch/560634/ and http://patchwork.ozlabs.org/patch/560635/ are back-ports from Linux kernel and could be actually applied separately because they are not related to each other. Following two are really preparatory for implementing capping: http://patchwork.ozlabs.org/patch/560636/ http://patchwork.ozlabs.org/patch/560637/ ...in patch I actually forgot to send out... (will do it shortly). And finally http://patchwork.ozlabs.org/patch/560638/ really a plain fix for DW GMAC driver which may happen in case of phy force set lower than possible. So it will easily manifest if all above is applied. That said it was conscious decision but probably incorrect one. If you do think it all fits well in a series I'll re-send it that way. -Alexey ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch V3 3/3] armv8/ls1043aqds: add QSPI boot support
On Mon, 2016-01-11 at 10:17 +0800, Gong Qianyu wrote:
> diff --git a/board/freescale/ls1043aqds/ls1043aqds.c
> b/board/freescale/ls1043aqds/ls1043aqds.c
> index d6696ca..770b79f 100644
> --- a/board/freescale/ls1043aqds/ls1043aqds.c
> +++ b/board/freescale/ls1043aqds/ls1043aqds.c
> @@ -43,15 +43,19 @@ enum {
>
> int checkboard(void)
> {
> +#ifndef CONFIG_QSPI_BOOT
> char buf[64];
> #ifndef CONFIG_SD_BOOT
> u8 sw;
> #endif
> +#endif
>
> puts("Board: LS1043AQDS, boot from ");
>
> #ifdef CONFIG_SD_BOOT
> puts("SD\n");
> +#elif defined(CONFIG_QSPI_BOOT)
> + puts("QSPI\n");
> #else
> sw = QIXIS_READ(brdcfg[0]);
> sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
> @@ -68,12 +72,15 @@ int checkboard(void)
> printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
> #endif
>
> +#ifndef CONFIG_QSPI_BOOT
> + /* For QSPI boot, here I2C is not ready yet. */
> printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
> QIXIS_READ(id), QIXIS_READ(arch));
>
> printf("FPGA: v%d (%s), build %d\n",
> (int)QIXIS_READ(scver), qixis_read_tag(buf),
> (int)qixis_read_minor());
> +#endif
Why isn't i2c ready? How is DDR inited without it?
-Scott
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[U-Boot] [PATCH v2 4/4] sunxi: Add suport for A83T based Banana-pi M3 Board
Add dts and defconfig for Banana-pi M3 board.
It has 2G LPDDR3, UART, ethernet, USB, HDMI, USB Sata, MIPI DSI,
mic, AP6212 Wifi, etc on it.
It is paired with AXP813 PMIC which is almost same as AXP818.
Signed-off-by: Vishnu Patekar
---
arch/arm/dts/Makefile| 3 +-
arch/arm/dts/sun8i-a83t-bananapi-m3-v1.2.dts | 64
board/sunxi/MAINTAINERS | 5 +++
configs/Bananapi_m3_defconfig| 26 +++
4 files changed, 97 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/sun8i-a83t-bananapi-m3-v1.2.dts
create mode 100644 configs/Bananapi_m3_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0bcd316..2ab0926 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -178,7 +178,8 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \
sun8i-a33-q8-tablet.dtb \
sun8i-a33-sinlinx-sina33.dtb
dtb-$(CONFIG_MACH_SUN8I_A83T) += \
- sun8i-a83t-allwinner-h8homlet-v2.dtb
+ sun8i-a83t-allwinner-h8homlet-v2.dtb \
+ sun8i-a83t-bananapi-m3-v1.2.dtb
dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h3-orangepi-pc.dtb \
sun8i-h3-orangepi-plus.dtb
diff --git a/arch/arm/dts/sun8i-a83t-bananapi-m3-v1.2.dts
b/arch/arm/dts/sun8i-a83t-bananapi-m3-v1.2.dts
new file mode 100644
index 000..91ff3a9
--- /dev/null
+++ b/arch/arm/dts/sun8i-a83t-bananapi-m3-v1.2.dts
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2015 Vishnu Patekar
+ * Vishnu Patekar
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a83t.dtsi"
+
+/ {
+ model = "Allwinner A83T BananaPi M3 Board v1.2";
+ compatible = "bananapi,m3v1.2", "allwinner,sun8i-a83t";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_b>;
+ status = "okay";
+};
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 131c341..575847a 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -84,6 +84,11 @@ M: Paul Kocialkowski
S: Maintained
F: configs/Ampe_A76_defconfig
+BANANA PI M3 A83T BOARD
+M: VishnuPatekar
+S: Maintained
+F: configs/Bananapi_m3_defconfig
+
COLOMBUS BOARD
M: Maxime Ripard
S: Maintained
diff --git a/configs/Bananapi_m3_defconfig b/configs/Bananapi_m3_defconfig
new file mode 100644
index 000..36c5cde
--- /dev/null
+++ b/configs/Bananapi_m3_defconfig
@@ -0,0 +1,26 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_A83T=y
+CONFIG_DRAM_CLK=480
+CONFIG_DRAM_ZQ=15355
+CONFIG_DRAM_ODT_EN=y
+CONFIG_DRAM_TYPE=7
+CONFIG_SYS_EXTRA_OPTIONS=""
+#CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
+#CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_AXP_GPIO=y
+#CONFIG_USB_MUSB_HOST=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-bananapi-m3-v1.2"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is
[U-Boot] [PATCH v2 3/4] sunxi: add support for LPDDR3 for A83T
Banana-pi M3 has LPDDR3 DRAM. this adds support for LPDDR3 for A83T.
Mostly the timing parameters are different from DDR3.
Signed-off-by: Vishnu Patekar
---
arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c| 54 ---
arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h | 5 +++
2 files changed, 54 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c
b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c
index 35b6c5e..7c46acd 100644
--- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c
@@ -131,10 +131,42 @@ static void auto_set_timing_para(struct dram_para *para)
/* Set work mode register */
mctl_set_cr(para);
/* Set mode register */
- writel(MCTL_MR0, &mctl_ctl->mr0);
- writel(MCTL_MR1, &mctl_ctl->mr1);
- writel(MCTL_MR2, &mctl_ctl->mr2);
- writel(MCTL_MR3, &mctl_ctl->mr3);
+ if (para->dram_type == DRAM_TYPE_DDR3) {
+ writel(MCTL_MR0, &mctl_ctl->mr0);
+ writel(MCTL_MR1, &mctl_ctl->mr1);
+ writel(MCTL_MR2, &mctl_ctl->mr2);
+ writel(MCTL_MR3, &mctl_ctl->mr3);
+ } else if (para->dram_type == DRAM_TYPE_LPDDR3) {
+ writel(MCTL_LPDDR3_MR0, &mctl_ctl->mr0);
+ writel(MCTL_LPDDR3_MR1, &mctl_ctl->mr1);
+ writel(MCTL_LPDDR3_MR2, &mctl_ctl->mr2);
+ writel(MCTL_LPDDR3_MR3, &mctl_ctl->mr3);
+
+ /* timing parameters for LPDDR3 */
+ tfaw = max(ns_to_t(50), 4);
+ trrd = max(ns_to_t(10), 2);
+ trcd = max(ns_to_t(24), 2);
+ trc = ns_to_t(70);
+ txp = max(ns_to_t(8), 2);
+ twtr = max(ns_to_t(8), 2);
+ trtp = max(ns_to_t(8), 2);
+ trp = max(ns_to_t(27), 2);
+ tras = ns_to_t(42);
+ trefi = ns_to_t(3900) / 32;
+ trfc = ns_to_t(210);
+ tmrw= 5;
+ tmrd= 5;
+ tckesr = 5;
+ tcwl= 3;/* CWL 8 */
+ t_rdata_en = 5;
+ tdinit0 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
+ tdinit1 = (100 * CONFIG_DRAM_CLK) / 1000 + 1; /* 100ns */
+ tdinit2 = (11 * CONFIG_DRAM_CLK) + 1; /* 200us */
+ tdinit3 = (1 * CONFIG_DRAM_CLK) + 1;/* 1us */
+ twtp= tcwl + 4 + twr + 1; /* CWL + BL/2 + tWR */
+ twr2rd = tcwl + 4 + 1 + twtr; /* WL + BL / 2 + tWTR */
+ trd2wr = tcl + 4 + 5 - tcwl + 1; /* RL + BL / 2 + 2 - WL */
+ }
/* Set dram timing */
reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0);
writel(reg_val, &mctl_ctl->dramtmg0);
@@ -289,6 +321,9 @@ static int mctl_channel_init(struct dram_para *para)
clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6));
clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7));
+ if (para->dram_type == DRAM_TYPE_LPDDR3)
+ clrsetbits_le32(&mctl_ctl->dxccr, (0x1 << 27) | (0x3<<6) ,
+ 0x1 << 31);
if (readl(&mctl_com->cr) & 0x1)
writel(0x0303, &mctl_ctl->odtmap);
else
@@ -299,7 +334,11 @@ static int mctl_channel_init(struct dram_para *para)
clrsetbits_le32(ZQnPR(0), 0x00ff, CONFIG_DRAM_ZQ & 0xff);
clrsetbits_le32(ZQnPR(1), 0x00ff, (CONFIG_DRAM_ZQ >> 8) & 0xff);
/* CA calibration */
- mctl_set_pir(0x0201f3 | 0x1<<10);
+
+ if (para->dram_type == DRAM_TYPE_DDR3)
+ mctl_set_pir(0x0201f3 | 0x1<<10);
+ else
+ mctl_set_pir(0x020173 | 0x1<<10);
/* DQS gate training */
if (mctl_train_dram(para) != 0) {
@@ -359,6 +398,7 @@ static void mctl_sys_init(struct dram_para *para)
clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
+ udelay(1000);
clrbits_le32(&ccm->dram_clk_cfg, 0x01<<31);
clock_set_pll5(CONFIG_DRAM_CLK * 100 * DRAM_CLK_MUL);
@@ -373,6 +413,10 @@ static void mctl_sys_init(struct dram_para *para)
setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
setbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE);
+ para->rank = 2;
+ para->bus_width = 16;
+ mctl_set_cr(para);
+
/* Set dram master access priority */
writel(0xe00f, &mctl_ctl->clken); /* normal */
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h
b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h
index 05b6a89..842ad3c 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h
@@ -198,6 +198,11 @@ struct sunxi_mctl_ctl_reg {
#define MCTL_MR2 0x18 /* CWL=8 */
#define MCTL
[U-Boot] [PATCH v2 2/4] sunxi: groundwork to support new dram type for A83T
Different A83T boards have different DRAM types. Banapi M3 has LPDDR3,
Allwinner Homlet v1.2 has DDR3.
This adds groundwork to support for new DRAM type for A83T.
Introduce CONFIG_DRAM_TYPE, It'll be 3 for DDR3 and 7 for LPDDR3, must
be set in respective board defconfig.
Signed-off-by: Vishnu Patekar
---
arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c| 11 ++-
arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h | 4 +++-
board/sunxi/Kconfig | 6 ++
3 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c
b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c
index 75e9746..35b6c5e 100644
--- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c
@@ -25,6 +25,7 @@ struct dram_para {
u8 rank;
u8 rows;
u8 bus_width;
+ u8 dram_type;
u16 page_size;
};
@@ -34,7 +35,7 @@ static void mctl_set_cr(struct dram_para *para)
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN |
- MCTL_CR_CHANNEL(1) | MCTL_CR_DDR3 |
+ MCTL_CR_CHANNEL(1) | MCTL_CR_DRAM_TYPE(para->dram_type) |
(para->seq ? MCTL_CR_SEQUENCE : 0) |
((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) |
MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |
@@ -86,6 +87,7 @@ static void auto_set_timing_para(struct dram_para *para)
{
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
u32 reg_val;
u8 tccd = 2;
@@ -393,6 +395,13 @@ unsigned long sunxi_dram_init(void)
.page_size = 2048,
};
+#if defined(CONFIG_MACH_SUN8I_A83T)
+#if (CONFIG_DRAM_TYPE == 3) || (CONFIG_DRAM_TYPE == 7)
+ para.dram_type = CONFIG_DRAM_TYPE;
+#else
+#error Unsupported DRAM type, Please set DRAM type (3:DDR3, 7:LPDDR3)
+#endif
+#endif
setbits_le32(SUNXI_PRCM_BASE + 0x1e0, 0x1 << 8);
writel(0, (SUNXI_PRCM_BASE + 0x1e8));
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h
b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h
index 2891b71..05b6a89 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h
@@ -186,7 +186,7 @@ struct sunxi_mctl_ctl_reg {
#define MCTL_CR_BUSW8 (0 << 12)
#define MCTL_CR_BUSW16 (1 << 12)
#define MCTL_CR_SEQUENCE (1 << 15)
-#define MCTL_CR_DDR3 (3 << 16)
+#define MCTL_CR_DRAM_TYPE(x) ((x) << 16)
#define MCTL_CR_CHANNEL_MASK (1 << 19)
#define MCTL_CR_CHANNEL(x) (((x) - 1) << 19)
#define MCTL_CR_UNKNOWN(0x4 << 20)
@@ -198,4 +198,6 @@ struct sunxi_mctl_ctl_reg {
#define MCTL_MR2 0x18 /* CWL=8 */
#define MCTL_MR3 0x0
+#define DRAM_TYPE_DDR3 3
+#define DRAM_TYPE_LPDDR3 7
#endif /* _SUNXI_DRAM_SUN8I_A83T_H */
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 9d67847..8007c28 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -92,6 +92,12 @@ config MACH_SUN8I
bool
default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 ||
MACH_SUN8I_A83T
+config DRAM_TYPE
+ int "sunxi dram type"
+ depends on MACH_SUN8I_A83T
+ default 3
+ ---help---
+ Set the dram type, 3: DDR3, 7: LPDDR3
config DRAM_CLK
int "sunxi dram clock speed"
--
1.9.1
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[U-Boot] [PATCH v2 1/4] sunxi: redundant code cleanup from a83t dram init
This removes the redundant lines of code from mctl_sys_init. Signed-off-by: Vishnu Patekar --- arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c | 5 - 1 file changed, 5 deletions(-) diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c index d757e40..75e9746 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c @@ -366,11 +366,6 @@ static void mctl_sys_init(struct dram_para *para) CCM_DRAMCLK_CFG_RST | CCM_DRAMCLK_CFG_UPD); mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); - setbits_le32(&ccm->ahb_reset0_cfg, 1 << 14); - setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); - setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); - setbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE); - setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 0/4] Add LPDDR3 support for A83T
This adds LPDDR3 support for A83T and support for Banana Pi M3 which has LPDDR3. These patches are based on u-boot-sunxi next branch. These patches tesed on Banana-pi M3. DCDC5 voltage is kept as 1.2V changes from v1 -> v2 1. introduce CONFIG_DRAM_TYPE for A83T default 3(DDR3), removed DRAM_TYPE from Obsolete SYS_EXTRA_OPTIONS. 2. Cleanup in seperate patch. 3. set rank 2, in mctl_sys_init. Vishnu Patekar (4): sunxi: redundant code cleanup from a83t dram init sunxi: groundwork to support new dram type for A83T sunxi: add support for LPDDR3 for A83T sunxi: Add suport for A83T based Banana-pi M3 Board arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c| 70 +++ arch/arm/dts/Makefile | 3 +- arch/arm/dts/sun8i-a83t-bananapi-m3-v1.2.dts | 64 + arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h | 9 ++- board/sunxi/Kconfig | 6 ++ board/sunxi/MAINTAINERS | 5 ++ configs/Bananapi_m3_defconfig | 26 + 7 files changed, 170 insertions(+), 13 deletions(-) create mode 100644 arch/arm/dts/sun8i-a83t-bananapi-m3-v1.2.dts create mode 100644 configs/Bananapi_m3_defconfig -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] MAINTAINERS/mailmap: Update my email address
Stefano, On 01/11/2016 05:20 AM, Stefano Babic wrote: > > Thanks - I ask all other Freescalers whose name is in a MAINTAINERS > file. Should you update your e-mail address as well ? Maybe do we > replace any occurence ofFreescale with NXP ? > I think all copyright and author information should be kept as is. What happened is in the history. We don't erase Freescale from the history. Maintainers' information should be updated. This is a chance to clean up as some people have left Freescale/NXP (removed recipients with invalid email addresses). York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] MAINTAINERS/mailmap: Update my email address
On 11/01/2016 18:06, York Sun wrote: > Stefano, > > On 01/11/2016 05:20 AM, Stefano Babic wrote: >> >> Thanks - I ask all other Freescalers whose name is in a MAINTAINERS >> file. Should you update your e-mail address as well ? Maybe do we >> replace any occurence ofFreescale with NXP ? >> > > I think all copyright and author information should be kept as is. Absolutely. I mean just MAINTAINERS files. > What happened > is in the history. We don't erase Freescale from the history. Maintainers' > information should be updated. This is a chance to clean up as some people > have > left Freescale/NXP (removed recipients with invalid email addresses). Right, this is what I mind. Stefano -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] curious if XTRN_DECLARE_GLOBAL_DATA_PTR is still of value
Hi Robert,
On 16 December 2015 at 05:02, Robert P. J. Day wrote:
>
> perusing the code related to the global data ptr and noticed in
> common/board_f.c:
>
> /*
> * Pointer to initial global data area
> *
> * Here we initialize it if needed.
> */
> #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
> #undef XTRN_DECLARE_GLOBAL_DATA_PTR
> #define XTRN_DECLARE_GLOBAL_DATA_PTR/* empty = allocate here */
> DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR);
> #else
> DECLARE_GLOBAL_DATA_PTR;
> #endif
>
> i was curious to see if anything took advantage of that and the only
> other place in the code that referred to that was in
> arch/powerpc/include/asm/global_data.h:
>
> #if 1
> #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")
> #else /* We could use plain global data, but the resulting code is bigger */
> #define XTRN_DECLARE_GLOBAL_DATA_PTRextern
> #define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \
> gd_t *gd
> #endif
>
> and given the "#if 1", it's pretty clear powerpc doesn't care about
> that, and that file common/board_f.c is the only place i can see in
> the entire code base that refers to CONFIG_SYS_INIT_GD_ADDR.
>
> so are people still taking advantage of this in some way?
Not that I know of. Looks like it could be cleaned up.
Regards,
Simon
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Re: [U-Boot] [PATCH V3 1/7] test/py: Implement pytest infrastructure
On 01/11/2016 03:45 AM, Michal Simek wrote: Hi Stephen, On 8.1.2016 19:13, Stephen Warren wrote: On 01/05/2016 03:58 PM, Stephen Warren wrote: This tool aims to test U-Boot by executing U-Boot shell commands using the console interface. A single top-level script exists to execute or attach to the U-Boot console, run the entire script of tests against it, and summarize the results. Advantages of this approach are: - Testing is performed in the same way a user or script would interact with U-Boot; there can be no disconnect. - There is no need to write or embed test-related code into U-Boot itself. It is asserted that writing test-related code in Python is simpler and more flexible that writing it all in C. - It is reasonably simple to interact with U-Boot in this way. A few simple tests are provided as examples. Soon, we should convert as many as possible of the other tests in test/* and test/cmd_ut.c too. The hook scripts, relay control utilities, and udev rules I use for my own HW setup are published at https://github.com/swarren/uboot-test-hooks. See README.md for more details! It looks like I need to send a v4 of this, since I renamed a Python class but forgot to update all users of it. I didn't notice this, since I had the old module lying around as a *.pyc file, so the old name worked:-( yep. I also have a couple of minor fixes to roll in that make the scripts work better under a continuous integration environment (which doesn't have a controlling TTY set when the scripts run, which need a minor tweak to the Spawn code). I have cherry picked 3 patches from your repo. 7813ccad9ed2 test/py: reset SIGHUP handler in child processes a2ccb34de3f5 test/py: fix ubspawn rename fallout 6dbcd7408f9e test/py: add a test for the sleep command sleep one is missing test for cmd_misc which enables that. There is still problem with handling special characters. For MB I have compilation error and %5e is shown instead of ^ For example: +make O=/home/monstr/data/disk/u-boot/build-microblaze-generic -s microblaze-generic_defconfig +make O=/home/monstr/data/disk/u-boot/build-microblaze-generic -s -j8 ../drivers/gpio/xilinx_gpio.c: In function 'xilinx_gpio_ofdata_to_platdata': ../drivers/gpio/xilinx_gpio.c:400:13: warning: assignment makes pointer from integer without a cast priv->regs = dev_get_addr(dev); %5e Ah yes. When I first wrote the code, the log file wasn't HTML format, but used ^ as a delimiter for some markup, so I escaped that character so that log data wouldn't corrupt the file format. When I switched to HTML, I forgot to remove that character from the escape list. I'll fold the fix into v4. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V3 1/7] test/py: Implement pytest infrastructure
On 01/11/2016 08:25 AM, Simon Glass wrote: Hi Stephen, On 8 January 2016 at 11:32, Michal Simek wrote: On 8.1.2016 19:13, Stephen Warren wrote: On 01/05/2016 03:58 PM, Stephen Warren wrote: This tool aims to test U-Boot by executing U-Boot shell commands using the console interface. A single top-level script exists to execute or attach to the U-Boot console, run the entire script of tests against it, and summarize the results. Advantages of this approach are: - Testing is performed in the same way a user or script would interact with U-Boot; there can be no disconnect. - There is no need to write or embed test-related code into U-Boot itself. It is asserted that writing test-related code in Python is simpler and more flexible that writing it all in C. - It is reasonably simple to interact with U-Boot in this way. A few simple tests are provided as examples. Soon, we should convert as many as possible of the other tests in test/* and test/cmd_ut.c too. The hook scripts, relay control utilities, and udev rules I use for my own HW setup are published at https://github.com/swarren/uboot-test-hooks. See README.md for more details! It looks like I need to send a v4 of this, since I renamed a Python class but forgot to update all users of it. I didn't notice this, since I had the old module lying around as a *.pyc file, so the old name worked:-( I also have a couple of minor fixes to roll in that make the scripts work better under a continuous integration environment (which doesn't have a controlling TTY set when the scripts run, which need a minor tweak to the Spawn code). I see this now. Do I need another dependency? /test/py/test.py --bd sandbox --build ... INTERNALERROR> from ubspawn import Spawn No, I renamed the ubspawn class (to u_boot_spawn) but forgot to update the users of the module to use the new name. My local testing didn't notice this since I still had the .pyc file present with the old name, but you evidently don't. I think something like the following should fix it for you before I post v4: sed -i 's/ubspawn/u_boot_spawn/' test/py/*.py ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
