[U-Boot] [PATCH v2 08/55] x86: ivybridge: Rename bd82x6x_init()

[Simon Glass]

Rename the existing bd82x6x_init() to bd82x6x_init_extra(). We will remove
this in a later patch.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Drop the init() method in the PCH
- Rename this commit from 'x86: ivybridge: Set up the PCH init'

 arch/x86/cpu/ivybridge/bd82x6x.c  | 2 +-
 arch/x86/cpu/ivybridge/cpu.c  | 8 
 arch/x86/cpu/ivybridge/pci.c  | 2 +-
 arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 2 +-
 4 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 72f2ed4..6556eeb 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -102,7 +102,7 @@ static int bd82x6x_probe(struct udevice *dev)
 }
 
 /* TODO(s...@chromium.org): Move this to the PCH init() method */
-int bd82x6x_init(void)
+int bd82x6x_init_extra(void)
 {
const void *blob = gd->fdt_blob;
int sata_node;
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 1e6f656..2a15fc0 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -211,6 +212,7 @@ int print_cpuinfo(void)
 {
enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE;
char processor_name[CPU_MAX_NAME_LEN];
+   struct udevice *dev;
const char *name;
uint32_t pm1_cnt;
uint16_t pm1_sts;
@@ -241,6 +243,12 @@ int print_cpuinfo(void)
}
 
/* Early chipset init required before RAM init can work */
+   ret = uclass_first_device(UCLASS_PCH, );
+   if (ret)
+   return ret;
+   if (!dev)
+   return -ENODEV;
+
sandybridge_early_init(SANDYBRIDGE_MOBILE);
 
/* Check PM1_STS[15] to see if we are waking from Sx */
diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c
index 5e90f30..8af99b4 100644
--- a/arch/x86/cpu/ivybridge/pci.c
+++ b/arch/x86/cpu/ivybridge/pci.c
@@ -26,7 +26,7 @@ static int pci_ivybridge_probe(struct udevice *bus)
if (!(gd->flags & GD_FLG_RELOC))
return 0;
post_code(0x50);
-   bd82x6x_init();
+   bd82x6x_init_extra();
post_code(0x51);
 
reg16 = 0xff;
diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h 
b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
index fcdf6e2..d76cb8d 100644
--- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
+++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
@@ -13,7 +13,7 @@ void bd82x6x_pci_init(pci_dev_t dev);
 void bd82x6x_usb_ehci_init(pci_dev_t dev);
 void bd82x6x_usb_xhci_init(pci_dev_t dev);
 int gma_func0_init(struct udevice *dev, const void *blob, int node);
-int bd82x6x_init(void);
+int bd82x6x_init_extra(void);
 
 /**
  * struct x86_cpu_priv - Information about a single CPU
-- 
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[U-Boot] [PATCH v2 03/55] dm: syscon: Allow finding devices by driver data

[Simon Glass]

We have a way to find a regmap by its syscon driver data value. Add the same
for syscon itself.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Add missing 'given' word

 drivers/core/syscon-uclass.c | 31 +++
 include/syscon.h | 14 ++
 test/dm/syscon.c | 17 +
 3 files changed, 50 insertions(+), 12 deletions(-)

diff --git a/drivers/core/syscon-uclass.c b/drivers/core/syscon-uclass.c
index 686c320..a0666d0 100644
--- a/drivers/core/syscon-uclass.c
+++ b/drivers/core/syscon-uclass.c
@@ -32,7 +32,7 @@ static int syscon_pre_probe(struct udevice *dev)
return regmap_init_mem(dev, >regmap);
 }
 
-struct regmap *syscon_get_regmap_by_driver_data(ulong driver_data)
+int syscon_get_by_driver_data(ulong driver_data, struct udevice **devp)
 {
struct udevice *dev;
struct uclass *uc;
@@ -40,22 +40,29 @@ struct regmap *syscon_get_regmap_by_driver_data(ulong 
driver_data)
 
ret = uclass_get(UCLASS_SYSCON, );
if (ret)
-   return ERR_PTR(ret);
+   return ret;
uclass_foreach_dev(dev, uc) {
if (dev->driver_data == driver_data) {
-   struct syscon_uc_info *priv;
-   int ret;
-
-   ret = device_probe(dev);
-   if (ret)
-   return ERR_PTR(ret);
-   priv = dev_get_uclass_priv(dev);
-
-   return priv->regmap;
+   *devp = dev;
+   return device_probe(dev);
}
}
 
-   return ERR_PTR(-ENODEV);
+   return -ENODEV;
+}
+
+struct regmap *syscon_get_regmap_by_driver_data(ulong driver_data)
+{
+   struct syscon_uc_info *priv;
+   struct udevice *dev;
+   int ret;
+
+   ret = syscon_get_by_driver_data(driver_data, );
+   if (ret)
+   return ERR_PTR(ret);
+   priv = dev_get_uclass_priv(dev);
+
+   return priv->regmap;
 }
 
 void *syscon_get_first_range(ulong driver_data)
diff --git a/include/syscon.h b/include/syscon.h
index c62ccd6..4593b6e 100644
--- a/include/syscon.h
+++ b/include/syscon.h
@@ -37,6 +37,20 @@ struct regmap *syscon_get_regmap(struct udevice *dev);
  *
  * Each system controller can be accessed by its driver data, which is
  * assumed to be unique through the scope of all system controllers that
+ * are in use. This function looks up the controller given this driver data.
+ *
+ * @driver_data:   Driver data value to look up
+ * @devp:  Returns the controller correponding to @driver_data
+ * @return 0 on success, -ENODEV if the ID was not found, or other -ve error
+ *code
+ */
+int syscon_get_by_driver_data(ulong driver_data, struct udevice **devp);
+
+/**
+ * syscon_get_regmap_by_driver_data() - Look up a controller by its ID
+ *
+ * Each system controller can be accessed by its driver data, which is
+ * assumed to be unique through the scope of all system controllers that
  * are in use. This function looks up the regmap given this driver data.
  *
  * @driver_data:   Driver data value to look up
diff --git a/test/dm/syscon.c b/test/dm/syscon.c
index 3642481..c40f5fc 100644
--- a/test/dm/syscon.c
+++ b/test/dm/syscon.c
@@ -29,3 +29,20 @@ static int dm_test_syscon_base(struct unit_test_state *uts)
return 0;
 }
 DM_TEST(dm_test_syscon_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test system controller finding */
+static int dm_test_syscon_by_driver_data(struct unit_test_state *uts)
+{
+   struct udevice *dev;
+
+   ut_assertok(syscon_get_by_driver_data(SYSCON0, ));
+   ut_asserteq(SYSCON0, dev->driver_data);
+
+   ut_assertok(syscon_get_by_driver_data(SYSCON1, ));
+   ut_asserteq(SYSCON1, dev->driver_data);
+
+   ut_asserteq(-ENODEV, syscon_get_by_driver_data(2, ));
+
+   return 0;
+}
+DM_TEST(dm_test_syscon_by_driver_data, DM_TESTF_SCAN_PDATA | 
DM_TESTF_SCAN_FDT);
-- 
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[U-Boot] [PATCH v2 07/55] x86: ivybridge: Move more init to the probe() function

[Simon Glass]

Move SPI and port80 init to lpc_early_init(), called from the LPC's probe()
method.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2: None

 arch/x86/cpu/ivybridge/cpu.c | 43 ---
 arch/x86/cpu/ivybridge/lpc.c | 43 +++
 2 files changed, 43 insertions(+), 43 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 4c6ffb2..1e6f656 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -30,26 +30,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static void enable_port80_on_lpc(struct pci_controller *hose, pci_dev_t dev)
-{
-   /* Enable port 80 POST on LPC */
-   pci_hose_write_config_dword(hose, dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
-   clrbits_le32(RCB_REG(GCS), 4);
-}
-
-/*
- * Enable Prefetching and Caching.
- */
-static void enable_spi_prefetch(struct pci_controller *hose, pci_dev_t dev)
-{
-   u8 reg8;
-
-   pci_hose_read_config_byte(hose, dev, 0xdc, );
-   reg8 &= ~(3 << 2);
-   reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
-   pci_hose_write_config_byte(hose, dev, 0xdc, reg8);
-}
-
 static int set_flex_ratio_to_tdp_nominal(void)
 {
msr_t flex_ratio, msr;
@@ -99,22 +79,6 @@ static int set_flex_ratio_to_tdp_nominal(void)
return -EINVAL;
 }
 
-static void set_spi_speed(void)
-{
-   u32 fdod;
-
-   /* Observe SPI Descriptor Component Section 0 */
-   writel(0x1000, RCB_REG(SPI_DESC_COMP0));
-
-   /* Extract the1 Write/Erase SPI Frequency from descriptor */
-   fdod = readl(RCB_REG(SPI_FREQ_WR_ERA));
-   fdod >>= 24;
-   fdod &= 7;
-
-   /* Set Software Sequence frequency to match */
-   clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod);
-}
-
 int arch_cpu_init(void)
 {
post_code(POST_CPU_INIT);
@@ -143,13 +107,6 @@ int arch_cpu_init_dm(void)
if (!dev)
return -ENODEV;
 
-   enable_spi_prefetch(hose, PCH_LPC_DEV);
-
-   /* This is already done in start.S, but let's do it in C */
-   enable_port80_on_lpc(hose, PCH_LPC_DEV);
-
-   set_spi_speed();
-
/*
 * We should do as little as possible before the serial console is
 * up. Perhaps this should move to later. Our next lot of init
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 9d089c7..9dad9e4 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -454,6 +454,42 @@ static void pch_fixups(pci_dev_t dev)
setbits_le32(RCB_REG(0x21a8), 0x3);
 }
 
+/*
+ * Enable Prefetching and Caching.
+ */
+static void enable_spi_prefetch(struct udevice *pch)
+{
+   u8 reg8;
+
+   dm_pci_read_config8(pch, 0xdc, );
+   reg8 &= ~(3 << 2);
+   reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+   dm_pci_write_config8(pch, 0xdc, reg8);
+}
+
+static void enable_port80_on_lpc(struct udevice *pch)
+{
+   /* Enable port 80 POST on LPC */
+   dm_pci_write_config32(pch, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
+   clrbits_le32(RCB_REG(GCS), 4);
+}
+
+static void set_spi_speed(void)
+{
+   u32 fdod;
+
+   /* Observe SPI Descriptor Component Section 0 */
+   writel(0x1000, RCB_REG(SPI_DESC_COMP0));
+
+   /* Extract the1 Write/Erase SPI Frequency from descriptor */
+   fdod = readl(RCB_REG(SPI_FREQ_WR_ERA));
+   fdod >>= 24;
+   fdod &= 7;
+
+   /* Set Software Sequence frequency to match */
+   clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod);
+}
+
 /**
  * lpc_early_init() - set up LPC serial ports and other early things
  *
@@ -492,6 +528,13 @@ static int lpc_early_init(struct udevice *dev)
dm_pci_write_config32(dev->parent, LPC_GENX_DEC(i), reg);
}
 
+   enable_spi_prefetch(dev->parent);
+
+   /* This is already done in start.S, but let's do it in C */
+   enable_port80_on_lpc(dev->parent);
+
+   set_spi_speed();
+
return 0;
 }
 
-- 
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[U-Boot] [PATCH v2 04/55] dm: pci: Convert bios_emu to use the driver model PCI API

[Simon Glass]

At present this BIOS emulator uses a bus/device/function number. Change
it to use a device if CONFIG_DM_PCI is enabled.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Drop unnecessary/incorrect non-DM code in dm_pci_run_vga_bios()

 drivers/bios_emulator/atibios.c | 109 ++--
 drivers/bios_emulator/bios.c|  39 ++
 drivers/pci/pci_rom.c   |   6 +--
 include/bios_emul.h |  19 ++-
 4 files changed, 165 insertions(+), 8 deletions(-)

diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c
index dec6230..7717246 100644
--- a/drivers/bios_emulator/atibios.c
+++ b/drivers/bios_emulator/atibios.c
@@ -226,11 +226,19 @@ This function executes the BIOS POST code on the 
controller. We assume that
 at this stage the controller has its I/O and memory space enabled and
 that all other controllers are in a disabled state.
 /
+#ifdef CONFIG_DM_PCI
+static void PCI_doBIOSPOST(struct udevice *pcidev, BE_VGAInfo *vga_info,
+  int vesa_mode, struct vbe_mode_info *mode_info)
+#else
 static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo *vga_info,
   int vesa_mode, struct vbe_mode_info *mode_info)
+#endif
 {
RMREGS regs;
RMSREGS sregs;
+#ifdef CONFIG_DM_PCI
+   pci_dev_t bdf;
+#endif
 
/* Determine the value to store in AX for BIOS POST. Per the PCI specs,
 AH must contain the bus and AL must contain the devfn, encoded as
@@ -238,9 +246,14 @@ static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo 
*vga_info,
 */
memset(, 0, sizeof(regs));
memset(, 0, sizeof(sregs));
+#ifdef CONFIG_DM_PCI
+   bdf = dm_pci_get_bdf(pcidev);
+   regs.x.ax = (int)PCI_BUS(bdf) << 8 |
+   (int)PCI_DEV(bdf) << 3 | (int)PCI_FUNC(bdf);
+#else
regs.x.ax = ((int)PCI_BUS(pcidev) << 8) |
((int)PCI_DEV(pcidev) << 3) | (int)PCI_FUNC(pcidev);
-
+#endif
/*Setup the X86 emulator for the VGA BIOS*/
BE_setVGA(vga_info);
 
@@ -281,15 +294,28 @@ NOTE: This function leaves the original memory aperture 
disabled by leaving
   it programmed to all 1's. It must be restored to the correct value
   later.
 /
+#ifdef CONFIG_DM_PCI
+static u32 PCI_findBIOSAddr(struct udevice *pcidev, int *bar)
+#else
 static u32 PCI_findBIOSAddr(pci_dev_t pcidev, int *bar)
+#endif
 {
u32 base, size;
 
for (*bar = 0x10; *bar <= 0x14; (*bar) += 4) {
+#ifdef CONFIG_DM_PCI
+   dm_pci_read_config32(pcidev, *bar, );
+#else
pci_read_config_dword(pcidev, *bar, );
+#endif
if (!(base & 0x1)) {
+#ifdef CONFIG_DM_PCI
+   dm_pci_write_config32(pcidev, *bar, 0x);
+   dm_pci_read_config32(pcidev, *bar, );
+#else
pci_write_config_dword(pcidev, *bar, 0x);
pci_read_config_dword(pcidev, *bar, );
+#endif
size = ~(size & ~0xFF) + 1;
if (size >= MAX_BIOSLEN)
return base & ~0xFF;
@@ -312,11 +338,19 @@ necessary).
 Anyway to fix this we change all I/O mapped base registers and
 chop off the top bits.
 /
+#ifdef CONFIG_DM_PCI
+static void PCI_fixupIObase(struct udevice *pcidev, int reg, u32 *base)
+#else
 static void PCI_fixupIObase(pci_dev_t pcidev, int reg, u32 * base)
+#endif
 {
if ((*base & 0x1) && (*base > 0xFFFE)) {
*base &= 0x;
+#ifdef CONFIG_DM_PCI
+   dm_pci_write_config32(pcidev, reg, *base);
+#else
pci_write_config_dword(pcidev, reg, *base);
+#endif
 
}
 }
@@ -331,18 +365,30 @@ Pointers to the mapped BIOS image
 REMARKS:
 Maps a pointer to the BIOS image on the graphics card on the PCI bus.
 /
+#ifdef CONFIG_DM_PCI
+void *PCI_mapBIOSImage(struct udevice *pcidev)
+#else
 void *PCI_mapBIOSImage(pci_dev_t pcidev)
+#endif
 {
u32 BIOSImageBus;
int BIOSImageBAR;
u8 *BIOSImage;
 
/*Save PCI BAR registers that might get changed*/
+#ifdef CONFIG_DM_PCI
+   dm_pci_read_config32(pcidev, PCI_ROM_ADDRESS, );
+   dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_0, );
+   dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_1, );
+   dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_2, );
+   dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_4, );
+#else
pci_read_config_dword(pcidev, PCI_ROM_ADDRESS, );
pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_0, );
pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_1, );
pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_2, 

[U-Boot] [PATCH v2 17/55] x86: ivybridge: Move GPIO init to the LPC init() method

[Simon Glass]

This init can happen in the driver also. Move it.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2: None

 arch/x86/cpu/ivybridge/cpu.c | 4 
 arch/x86/cpu/ivybridge/lpc.c | 3 +++
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index c3626c4..6d3f477 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -278,10 +278,6 @@ int print_cpuinfo(void)
 
gd->arch.pei_boot_mode = boot_mode;
 
-   /* TODO: Move this to the board or driver */
-   x86_pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
-   x86_pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10);
-
/* Print processor name */
name = cpu_get_name(processor_name);
printf("CPU:   %s\n", name);
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index c88733d..0d85de2 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -623,6 +623,9 @@ static int bd82x6x_lpc_early_init(struct udevice *dev)
setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */
outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08);/* halt timer */
 
+   dm_pci_write_config32(dev->parent, GPIO_BASE, DEFAULT_GPIOBASE | 1);
+   dm_pci_write_config32(dev->parent, GPIO_CNTL, 0x10);
+
return 0;
 }
 
-- 
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[U-Boot] [PATCH v2 32/55] x86: ivybridge: Use the SATA driver to do the init

[Simon Glass]

Instead of manually initing the device, probe the SATA device and move the
init there.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Update to use the disk uclass

 arch/x86/cpu/ivybridge/bd82x6x.c  | 13 +
 arch/x86/cpu/ivybridge/sata.c |  4 +++-
 arch/x86/include/asm/arch-ivybridge/bd82x6x.h |  1 -
 3 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 1fe2ce1..188b7da 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -22,7 +22,7 @@ static int bd82x6x_probe(struct udevice *dev)
 {
const void *blob = gd->fdt_blob;
struct pci_controller *hose;
-   int sata_node, gma_node;
+   int gma_node;
int ret;
 
if (!(gd->flags & GD_FLG_RELOC))
@@ -31,13 +31,10 @@ static int bd82x6x_probe(struct udevice *dev)
hose = pci_bus_to_hose(0);
lpc_enable(PCH_LPC_DEV);
lpc_init_extra(hose, PCH_LPC_DEV);
-   sata_node = fdtdec_next_compatible(blob, 0,
-  COMPAT_INTEL_PANTHERPOINT_AHCI);
-   if (sata_node < 0) {
-   debug("%s: Cannot find SATA node\n", __func__);
-   return -EINVAL;
-   }
-   bd82x6x_sata_init(PCH_SATA_DEV, blob, sata_node);
+
+   /* Cause the SATA device to do its init */
+   uclass_first_device(UCLASS_DISK, );
+
bd82x6x_usb_ehci_init(PCH_EHCI1_DEV);
bd82x6x_usb_ehci_init(PCH_EHCI2_DEV);
 
diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c
index c46ec3a..6314566 100644
--- a/arch/x86/cpu/ivybridge/sata.c
+++ b/arch/x86/cpu/ivybridge/sata.c
@@ -47,7 +47,7 @@ static void common_sata_init(pci_dev_t dev, unsigned int 
port_map)
x86_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183);
 }
 
-void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node)
+static void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node)
 {
unsigned int port_map, speed_support, port_tx;
struct pci_controller *hose = pci_bus_to_hose(0);
@@ -232,6 +232,8 @@ static int bd82x6x_sata_probe(struct udevice *dev)
 {
if (!(gd->flags & GD_FLG_RELOC))
bd82x6x_sata_enable(PCH_SATA_DEV, gd->fdt_blob, dev->of_offset);
+   else
+   bd82x6x_sata_init(PCH_SATA_DEV, gd->fdt_blob, dev->of_offset);
 
return 0;
 }
diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h 
b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
index 7a05c7e..bb3a6c9 100644
--- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
+++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
@@ -7,7 +7,6 @@
 #ifndef _ASM_ARCH_BD82X6X_H
 #define _ASM_ARCH_BD82X6X_H
 
-void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node);
 void bd82x6x_usb_ehci_init(pci_dev_t dev);
 void bd82x6x_usb_xhci_init(pci_dev_t dev);
 int gma_func0_init(struct udevice *dev, const void *blob, int node);
-- 
2.6.0.rc2.230.g3dd15c0

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[U-Boot] [PATCH v2 35/55] x86: ivybridge: Move LPC init into the LPC probe() method

[Simon Glass]

Drop the lpc_init_extra() function and just use the post-relocation LPC
probe() instead.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2:
- Update to use LPC probe() method instead of init()

 arch/x86/cpu/ivybridge/bd82x6x.c  |  4 
 arch/x86/cpu/ivybridge/lpc.c  | 17 +
 arch/x86/include/asm/arch-ivybridge/pch.h |  2 --
 3 files changed, 9 insertions(+), 14 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 9e7e30a..5cb4152 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -21,16 +21,12 @@
 static int bd82x6x_probe(struct udevice *dev)
 {
const void *blob = gd->fdt_blob;
-   struct pci_controller *hose;
int gma_node;
int ret;
 
if (!(gd->flags & GD_FLG_RELOC))
return 0;
 
-   hose = pci_bus_to_hose(0);
-   lpc_init_extra(hose, PCH_LPC_DEV);
-
/* Cause the SATA device to do its init */
uclass_first_device(UCLASS_DISK, );
 
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 44c4825..79224d9 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -538,7 +538,7 @@ static int lpc_early_init(struct udevice *dev)
return 0;
 }
 
-int lpc_init_extra(struct pci_controller *hose, pci_dev_t dev)
+static int lpc_init_extra(struct pci_controller *hose, pci_dev_t dev)
 {
const void *blob = gd->fdt_blob;
int node;
@@ -626,16 +626,17 @@ static int bd82x6x_lpc_probe(struct udevice *dev)
 {
int ret;
 
-   if (gd->flags & GD_FLG_RELOC)
-   return 0;
+   if (!(gd->flags & GD_FLG_RELOC)) {
+   ret = lpc_early_init(dev);
+   if (ret) {
+   debug("%s: lpc_early_init() failed\n", __func__);
+   return ret;
+   }
 
-   ret = lpc_early_init(dev);
-   if (ret) {
-   debug("%s: lpc_early_init() failed\n", __func__);
-   return ret;
+   return bd82x6x_lpc_early_init(dev);
}
 
-   return bd82x6x_lpc_early_init(dev);
+   return lpc_init_extra(pci_bus_to_hose(0), PCH_LPC_DEV);
 }
 
 static const struct udevice_id bd82x6x_lpc_ids[] = {
diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h 
b/arch/x86/include/asm/arch-ivybridge/pch.h
index 682a557..629a144 100644
--- a/arch/x86/include/asm/arch-ivybridge/pch.h
+++ b/arch/x86/include/asm/arch-ivybridge/pch.h
@@ -470,6 +470,4 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 
orvalue);
 #define   DMISCI_STS   (1 << 9)
 #define TCO2_STS   0x66
 
-int lpc_init_extra(struct pci_controller *hose, pci_dev_t dev);
-
 #endif
-- 
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[U-Boot] [PATCH v2 25/55] x86: Bring up northbridge, pch and lpc after the CPUs

[Simon Glass]

These devices currently need to be inited early in boot. Once we have the
init in the right places (with each device doing its own init and no
problems with ordering) we should be able to remove this. For now it is
needed to keep things working.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Add a comment as to why we are initing the devices again

 arch/x86/cpu/cpu.c | 20 ++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 3c812e9..6c3a748 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -709,8 +709,24 @@ static int x86_init_cpus(void)
 
 int cpu_init_r(void)
 {
-   if (ll_boot_init())
-   return x86_init_cpus();
+   struct udevice *dev;
+   int ret;
+
+   if (!ll_boot_init())
+   return 0;
+
+   ret = x86_init_cpus();
+   if (ret)
+   return ret;
+
+   /*
+* Set up the northbridge, PCH and LPC if available. Note that these
+* may have had some limited pre-relocation init if they were probed
+* before relocation, but this is post relocation.
+*/
+   uclass_first_device(UCLASS_NORTHBRIDGE, );
+   uclass_first_device(UCLASS_PCH, );
+   uclass_first_device(UCLASS_LPC, );
 
return 0;
 }
-- 
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[U-Boot] Board specific hook for performing pre-os tweaks

[Chris Packham]

Hi,

Is there any hook for performing board specific actions prior to
booting the OS. A quick google search turned up this thread from
2014[1]. But the eventual outcome seemed to be that the device model
will take care of restoring devices to their unused state, for
anything else there is arch_preboot_os() which may get renamed to drop
the arch_ part at some point.

Is using arch_preboot_os() still the best place to perform board
specific tweaks for the OS?

Thanks,
Chris
--
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/200283
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Re: [U-Boot] [PATCH 10/18] common: Move LCD and video memory reservation together

[Anatolij Gustschin]

On Tue,  5 Jan 2016 09:31:06 -0700
Simon Glass  wrote:

> These two functions are conceptually the same. Move them together in the
> pre-relocation init.
> 
> Signed-off-by: Simon Glass 
> ---
> 
>  common/board_f.c | 28 ++--
>  1 file changed, 14 insertions(+), 14 deletions(-)

Acked-by: Anatolij Gustschin 

--
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Re: [U-Boot] [PATCH 16/18] dm: video: test: Add tests for the video uclass

[Anatolij Gustschin]

On Tue,  5 Jan 2016 09:31:12 -0700
Simon Glass  wrote:

> Add tests that check that the video console is working correcty. Also check
> that text output produces the expected result. Test coverage includes
> character output, wrapping and scrolling.
> 
> Signed-off-by: Simon Glass 
> ---
> 
>  arch/sandbox/dts/test.dts   |   7 ++
>  drivers/video/sandbox_sdl.c |   9 ---
>  include/dm/test.h   |   8 ++
>  test/dm/Makefile|   1 +
>  test/dm/video.c | 190 
> 
>  5 files changed, 206 insertions(+), 9 deletions(-)
>  create mode 100644 test/dm/video.c
...
> +/*
> + * These tests use the standard sandbox frame buffer, the resolutino of which

s/resolutino/resolution/

Otherwise

Acked-by: Anatolij Gustschin 

--
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[U-Boot] [PATCH v2 02/55] dm: usb: Add a compatible string for PCI EHCI controller

[Simon Glass]

Add a compatible string to allow this to be specified in the device tree
if needed.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Add missing of_match member init so that ehci_pci_ids[] is used

 drivers/usb/host/ehci-pci.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index cda1c6d..f21a1fa 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -137,11 +137,17 @@ static int ehci_pci_remove(struct udevice *dev)
return 0;
 }
 
+static const struct udevice_id ehci_pci_ids[] = {
+   { .compatible = "ehci-pci" },
+   { }
+};
+
 U_BOOT_DRIVER(ehci_pci) = {
.name   = "ehci_pci",
.id = UCLASS_USB,
.probe = ehci_pci_probe,
.remove = ehci_pci_remove,
+   .of_match = ehci_pci_ids,
.ops= _usb_ops,
.platdata_auto_alloc_size = sizeof(struct usb_platdata),
.priv_auto_alloc_size = sizeof(struct ehci_pci_priv),
-- 
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[U-Boot] [PATCH v2 55/55] x86: fdt: Drop the unused compatible strings in fdtdec

[Simon Glass]

We have drivers for several more devices now, so drop the strings which are
no-longer used.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2:
- Drop bd82x6x_pci_init() function and associated DM-conversion patch
- Drop LPC init method an 'Add an init() method to the LPC uclass' patch

 arch/x86/cpu/ivybridge/lpc.c | 6 --
 include/fdtdec.h | 5 -
 lib/fdtdec.c | 5 -
 3 files changed, 16 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 9ab5ed3..deda2f5 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -491,8 +491,6 @@ static int lpc_early_init(struct udevice *dev)
 static int lpc_init_extra(struct udevice *dev)
 {
struct udevice *pch = dev->parent;
-   const void *blob = gd->fdt_blob;
-   int node;
 
debug("pch: lpc_init\n");
dm_pci_write_bar32(pch, 0, 0);
@@ -501,10 +499,6 @@ static int lpc_init_extra(struct udevice *dev)
dm_pci_write_bar32(pch, 3, 0x800);
dm_pci_write_bar32(pch, 4, 0x900);
 
-   node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH);
-   if (node < 0)
-   return -ENOENT;
-
/* Set the value for PCI command register. */
dm_pci_write_config16(pch, PCI_COMMAND, 0x000f);
 
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 27b350e..e545866 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -155,15 +155,10 @@ enum fdt_compat_id {
COMPAT_SAMSUNG_EXYNOS_SYSMMU,   /* Exynos sysmmu */
COMPAT_INTEL_MICROCODE, /* Intel microcode update */
COMPAT_MEMORY_SPD,  /* Memory SPD information */
-   COMPAT_INTEL_PANTHERPOINT_AHCI, /* Intel Pantherpoint AHCI */
-   COMPAT_INTEL_MODEL_206AX,   /* Intel Model 206AX CPU */
-   COMPAT_INTEL_GMA,   /* Intel Graphics Media Accelerator */
COMPAT_AMS_AS3722,  /* AMS AS3722 PMIC */
-   COMPAT_INTEL_ICH_SPI,   /* Intel ICH7/9 SPI controller */
COMPAT_INTEL_QRK_MRC,   /* Intel Quark MRC */
COMPAT_INTEL_X86_PINCTRL,   /* Intel ICH7/9 pin control */
COMPAT_SOCIONEXT_XHCI,  /* Socionext UniPhier xHCI */
-   COMPAT_INTEL_PCH,   /* Intel PCH */
COMPAT_INTEL_IRQ_ROUTER,/* Intel Interrupt Router */
COMPAT_ALTERA_SOCFPGA_DWMAC,/* SoCFPGA Ethernet controller */
COMPAT_ALTERA_SOCFPGA_DWMMC,/* SoCFPGA DWMMC controller */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index b50d105..3c05559 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -60,15 +60,10 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"),
COMPAT(INTEL_MICROCODE, "intel,microcode"),
COMPAT(MEMORY_SPD, "memory-spd"),
-   COMPAT(INTEL_PANTHERPOINT_AHCI, "intel,pantherpoint-ahci"),
-   COMPAT(INTEL_MODEL_206AX, "intel,model-206ax"),
-   COMPAT(INTEL_GMA, "intel,gma"),
COMPAT(AMS_AS3722, "ams,as3722"),
-   COMPAT(INTEL_ICH_SPI, "intel,ich-spi"),
COMPAT(INTEL_QRK_MRC, "intel,quark-mrc"),
COMPAT(INTEL_X86_PINCTRL, "intel,x86-pinctrl"),
COMPAT(SOCIONEXT_XHCI, "socionext,uniphier-xhci"),
-   COMPAT(COMPAT_INTEL_PCH, "intel,bd82x6x"),
COMPAT(COMPAT_INTEL_IRQ_ROUTER, "intel,irq-router"),
COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"),
COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
-- 
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[U-Boot] [PATCH v2 37/55] x86: ivybridge: Convert lpc init code to DM PCI API

[Simon Glass]

Adjust this code to use the driver model PCI API. This is all called through
lpc_init_extra().

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2: None

 arch/x86/cpu/ivybridge/lpc.c | 129 ++-
 1 file changed, 66 insertions(+), 63 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 79224d9..0cf55c5 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -24,13 +24,13 @@
 #define ENABLE_ACPI_MODE_IN_COREBOOT   0
 #define TEST_SMM_FLASH_LOCKDOWN0
 
-static int pch_enable_apic(pci_dev_t dev)
+static int pch_enable_apic(struct udevice *pch)
 {
u32 reg32;
int i;
 
/* Enable ACPI I/O and power management. Set SCI IRQ to IRQ9 */
-   x86_pci_write_config8(dev, ACPI_CNTL, 0x80);
+   dm_pci_write_config8(pch, ACPI_CNTL, 0x80);
 
writel(0, IO_APIC_INDEX);
writel(1 << 25, IO_APIC_DATA);
@@ -66,36 +66,36 @@ static int pch_enable_apic(pci_dev_t dev)
return 0;
 }
 
-static void pch_enable_serial_irqs(pci_dev_t dev)
+static void pch_enable_serial_irqs(struct udevice *pch)
 {
u32 value;
 
/* Set packet length and toggle silent mode bit for one frame. */
value = (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0);
 #ifdef CONFIG_SERIRQ_CONTINUOUS_MODE
-   x86_pci_write_config8(dev, SERIRQ_CNTL, value);
+   dm_pci_write_config8(pch, SERIRQ_CNTL, value);
 #else
-   x86_pci_write_config8(dev, SERIRQ_CNTL, value | (1 << 6));
+   dm_pci_write_config8(pch, SERIRQ_CNTL, value | (1 << 6));
 #endif
 }
 
-static int pch_pirq_init(const void *blob, int node, pci_dev_t dev)
+static int pch_pirq_init(struct udevice *pch)
 {
uint8_t route[8], *ptr;
 
-   if (fdtdec_get_byte_array(blob, node, "intel,pirq-routing", route,
- sizeof(route)))
+   if (fdtdec_get_byte_array(gd->fdt_blob, pch->of_offset,
+ "intel,pirq-routing", route, sizeof(route)))
return -EINVAL;
ptr = route;
-   x86_pci_write_config8(dev, PIRQA_ROUT, *ptr++);
-   x86_pci_write_config8(dev, PIRQB_ROUT, *ptr++);
-   x86_pci_write_config8(dev, PIRQC_ROUT, *ptr++);
-   x86_pci_write_config8(dev, PIRQD_ROUT, *ptr++);
+   dm_pci_write_config8(pch, PIRQA_ROUT, *ptr++);
+   dm_pci_write_config8(pch, PIRQB_ROUT, *ptr++);
+   dm_pci_write_config8(pch, PIRQC_ROUT, *ptr++);
+   dm_pci_write_config8(pch, PIRQD_ROUT, *ptr++);
 
-   x86_pci_write_config8(dev, PIRQE_ROUT, *ptr++);
-   x86_pci_write_config8(dev, PIRQF_ROUT, *ptr++);
-   x86_pci_write_config8(dev, PIRQG_ROUT, *ptr++);
-   x86_pci_write_config8(dev, PIRQH_ROUT, *ptr++);
+   dm_pci_write_config8(pch, PIRQE_ROUT, *ptr++);
+   dm_pci_write_config8(pch, PIRQF_ROUT, *ptr++);
+   dm_pci_write_config8(pch, PIRQG_ROUT, *ptr++);
+   dm_pci_write_config8(pch, PIRQH_ROUT, *ptr++);
 
/*
 * TODO(s...@chromium.org): U-Boot does not set up the interrupts
@@ -104,26 +104,28 @@ static int pch_pirq_init(const void *blob, int node, 
pci_dev_t dev)
return 0;
 }
 
-static int pch_gpi_routing(const void *blob, int node, pci_dev_t dev)
+static int pch_gpi_routing(struct udevice *pch)
 {
u8 route[16];
u32 reg;
int gpi;
 
-   if (fdtdec_get_byte_array(blob, node, "intel,gpi-routing", route,
- sizeof(route)))
+   if (fdtdec_get_byte_array(gd->fdt_blob, pch->of_offset,
+ "intel,gpi-routing", route, sizeof(route)))
return -EINVAL;
 
for (reg = 0, gpi = 0; gpi < ARRAY_SIZE(route); gpi++)
reg |= route[gpi] << (gpi * 2);
 
-   x86_pci_write_config32(dev, 0xb8, reg);
+   dm_pci_write_config32(pch, 0xb8, reg);
 
return 0;
 }
 
-static int pch_power_options(const void *blob, int node, pci_dev_t dev)
+static int pch_power_options(struct udevice *pch)
 {
+   const void *blob = gd->fdt_blob;
+   int node = pch->of_offset;
u8 reg8;
u16 reg16, pmbase;
u32 reg32;
@@ -142,7 +144,7 @@ static int pch_power_options(const void *blob, int node, 
pci_dev_t dev)
 */
pwr_on = MAINBOARD_POWER_ON;
 
-   reg16 = x86_pci_read_config16(dev, GEN_PMCON_3);
+   dm_pci_read_config16(pch, GEN_PMCON_3, );
reg16 &= 0xfffe;
switch (pwr_on) {
case MAINBOARD_POWER_OFF:
@@ -169,7 +171,7 @@ static int pch_power_options(const void *blob, int node, 
pci_dev_t dev)
 
reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */
 
-   x86_pci_write_config16(dev, GEN_PMCON_3, reg16);
+   dm_pci_write_config16(pch, GEN_PMCON_3, reg16);
debug("Set power %s after power failure.\n", state);
 
/* Set up NMI on errors. */
@@ -193,21 +195,22 @@ static int pch_power_options(const void 

[U-Boot] [PATCH v2 46/55] x86: ivybridge: Convert report_platform to DM PCI API

[Simon Glass]

Convert these functions to use the driver model PCI API.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2: None

 arch/x86/cpu/ivybridge/report_platform.c  | 11 ++-
 arch/x86/cpu/ivybridge/sdram.c|  2 +-
 arch/x86/include/asm/arch-ivybridge/sandybridge.h |  2 +-
 3 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/report_platform.c 
b/arch/x86/cpu/ivybridge/report_platform.c
index 4493870..c78322a 100644
--- a/arch/x86/cpu/ivybridge/report_platform.c
+++ b/arch/x86/cpu/ivybridge/report_platform.c
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 
 static void report_cpu_info(void)
 {
@@ -63,27 +64,27 @@ static struct {
{0x1E5F, "NM70"},
 };
 
-static void report_pch_info(void)
+static void report_pch_info(struct udevice *dev)
 {
const char *pch_type = "Unknown";
int i;
u16 dev_id;
uint8_t rev_id;
 
-   dev_id = x86_pci_read_config16(PCH_LPC_DEV, 2);
+   dm_pci_read_config16(dev, 2, _id);
for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
if (pch_table[i].dev_id == dev_id) {
pch_type = pch_table[i].dev_name;
break;
}
}
-   rev_id = x86_pci_read_config8(PCH_LPC_DEV, 8);
+   dm_pci_read_config8(dev, 8, _id);
debug("PCH type: %s, device id: %x, rev id %x\n", pch_type, dev_id,
  rev_id);
 }
 
-void report_platform_info(void)
+void report_platform_info(struct udevice *dev)
 {
report_cpu_info();
-   report_pch_info();
+   report_pch_info(dev);
 }
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index 696351b..3e5be4e 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -294,7 +294,7 @@ int sdram_initialise(struct udevice *dev, struct udevice 
*me_dev,
uint16_t done;
int ret;
 
-   report_platform_info();
+   report_platform_info(dev);
 
/* Wait for ME to be ready */
ret = intel_early_me_init(me_dev);
diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h 
b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
index af8a9f7..ce8d030 100644
--- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h
+++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
@@ -110,7 +110,7 @@
 
 int bridge_silicon_revision(void);
 
-void report_platform_info(void);
+void report_platform_info(struct udevice *dev);
 
 void sandybridge_early_init(int chipset_type);
 
-- 
2.6.0.rc2.230.g3dd15c0

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[U-Boot] [PATCH v2 26/55] x86: ivybridge: Move northbridge and PCH init into drivers

[Simon Glass]

Instead of calling the northbridge and PCH init from bd82x6x_init_extra()
when the PCI bus is probed, call it from the respective drivers. Also drop
the Northbridge init as it has no effect. The registers it touches appear to
be read-only.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 arch/x86/cpu/ivybridge/bd82x6x.c  | 42 ---
 arch/x86/cpu/ivybridge/northbridge.c  | 16 +++---
 arch/x86/include/asm/arch-ivybridge/bd82x6x.h |  1 -
 board/google/chromebook_link/link.c   |  8 -
 4 files changed, 12 insertions(+), 55 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 149c1d2..c5a5d4d 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -18,45 +18,6 @@
 
 #define BIOS_CTRL  0xdc
 
-void bd82x6x_pci_init(pci_dev_t dev)
-{
-   u16 reg16;
-   u8 reg8;
-
-   debug("bd82x6x PCI init.\n");
-   /* Enable Bus Master */
-   reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
-   reg16 |= PCI_COMMAND_MASTER;
-   x86_pci_write_config16(dev, PCI_COMMAND, reg16);
-
-   /* This device has no interrupt */
-   x86_pci_write_config8(dev, INTR, 0xff);
-
-   /* disable parity error response and SERR */
-   reg16 = x86_pci_read_config16(dev, BCTRL);
-   reg16 &= ~(1 << 0);
-   reg16 &= ~(1 << 1);
-   x86_pci_write_config16(dev, BCTRL, reg16);
-
-   /* Master Latency Count must be set to 0x04! */
-   reg8 = x86_pci_read_config8(dev, SMLT);
-   reg8 &= 0x07;
-   reg8 |= (0x04 << 3);
-   x86_pci_write_config8(dev, SMLT, reg8);
-
-   /* Will this improve throughput of bus masters? */
-   x86_pci_write_config8(dev, PCI_MIN_GNT, 0x06);
-
-   /* Clear errors in status registers */
-   reg16 = x86_pci_read_config16(dev, PSTS);
-   /* reg16 |= 0xf900; */
-   x86_pci_write_config16(dev, PSTS, reg16);
-
-   reg16 = x86_pci_read_config16(dev, SECSTS);
-   /* reg16 |= 0xf900; */
-   x86_pci_write_config16(dev, SECSTS, reg16);
-}
-
 static int bd82x6x_probe(struct udevice *dev)
 {
const void *blob = gd->fdt_blob;
@@ -108,10 +69,7 @@ int bd82x6x_init_extra(void)
return -EINVAL;
}
 
-   bd82x6x_pci_init(PCH_DEV);
bd82x6x_sata_enable(PCH_SATA_DEV, blob, sata_node);
-   northbridge_enable(PCH_DEV);
-   northbridge_init(PCH_DEV);
 
return 0;
 }
diff --git a/arch/x86/cpu/ivybridge/northbridge.c 
b/arch/x86/cpu/ivybridge/northbridge.c
index 6b00d31..2eed0af 100644
--- a/arch/x86/cpu/ivybridge/northbridge.c
+++ b/arch/x86/cpu/ivybridge/northbridge.c
@@ -197,15 +197,12 @@ static void sandybridge_setup_northbridge_bars(struct 
udevice *dev)
dm_pci_write_config8(dev, PAM6, 0x33);
 }
 
-static int bd82x6x_northbridge_probe(struct udevice *dev)
+static int bd82x6x_northbridge_early_init(struct udevice *dev)
 {
const int chipset_type = SANDYBRIDGE_MOBILE;
u32 capid0_a;
u8 reg8;
 
-   if (gd->flags & GD_FLG_RELOC)
-   return 0;
-
/* Device ID Override Enable should be done very early */
dm_pci_read_config32(dev, 0xe4, _a);
if (capid0_a & (1 << 10)) {
@@ -226,6 +223,17 @@ static int bd82x6x_northbridge_probe(struct udevice *dev)
return 0;
 }
 
+static int bd82x6x_northbridge_probe(struct udevice *dev)
+{
+   if (!(gd->flags & GD_FLG_RELOC))
+   return bd82x6x_northbridge_early_init(dev);
+
+   northbridge_enable(PCH_DEV);
+   northbridge_init(PCH_DEV);
+
+   return 0;
+}
+
 static const struct udevice_id bd82x6x_northbridge_ids[] = {
{ .compatible = "intel,bd82x6x-northbridge" },
{ }
diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h 
b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
index fc7fc6d..0f4fe47 100644
--- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
+++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
@@ -9,7 +9,6 @@
 
 void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node);
 void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node);
-void bd82x6x_pci_init(pci_dev_t dev);
 void bd82x6x_usb_ehci_init(pci_dev_t dev);
 void bd82x6x_usb_xhci_init(pci_dev_t dev);
 int gma_func0_init(struct udevice *dev, const void *blob, int node);
diff --git a/board/google/chromebook_link/link.c 
b/board/google/chromebook_link/link.c
index 1b97a8f..d12d742 100644
--- a/board/google/chromebook_link/link.c
+++ b/board/google/chromebook_link/link.c
@@ -14,14 +14,6 @@
 
 int arch_early_init_r(void)
 {
-   struct udevice *dev;
-   int ret;
-
-   /* Make sure the platform controller hub is up and running */
-   ret = uclass_get_device(UCLASS_PCH, 0, );
-   if (ret)
-   return ret;
-
return 0;
 }
 
-- 
2.6.0.rc2.230.g3dd15c0

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[U-Boot] [PATCH v2 53/55] x86: Set up a shared syscon numbering schema

[Simon Glass]

Each system controller can have a number to identify it. It can then be
accessed using syscon_get_by_driver_data(). Put this in a shared header
file and update the only current user.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2:
- Enable SYSCON and REGMAP for panther to avoid a build error

 arch/x86/cpu/ivybridge/early_me.c   | 3 ++-
 arch/x86/cpu/ivybridge/sdram.c  | 6 +++---
 arch/x86/include/asm/cpu.h  | 9 +
 configs/chromebox_panther_defconfig | 2 ++
 4 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/early_me.c 
b/arch/x86/cpu/ivybridge/early_me.c
index 612c910..f0d6899 100644
--- a/arch/x86/cpu/ivybridge/early_me.c
+++ b/arch/x86/cpu/ivybridge/early_me.c
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -189,7 +190,7 @@ int intel_early_me_init_done(struct udevice *dev, struct 
udevice *me_dev,
 }
 
 static const struct udevice_id ivybridge_syscon_ids[] = {
-   { .compatible = "intel,me", },
+   { .compatible = "intel,me", .data = X86_SYSCON_ME },
{ }
 };
 
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index 3e5be4e..e23c422 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -18,6 +18,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -739,11 +741,9 @@ int dram_init(void)
return ret;
if (!dev)
return -ENODEV;
-   ret = uclass_first_device(UCLASS_SYSCON, _dev);
+   ret = syscon_get_by_driver_data(X86_SYSCON_ME, _dev);
if (ret)
return ret;
-   if (!me_dev)
-   return -ENODEV;
debug("Boot mode %d\n", gd->arch.pei_boot_mode);
debug("mrc_input %p\n", pei_data.mrc_input);
pei_data.boot_mode = gd->arch.pei_boot_mode;
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index c70183c..76cdf47 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -45,6 +45,15 @@ enum {
GDT_BASE_HIGH_MASK  = 0xf,
 };
 
+/*
+ * System controllers in an x86 system. We mostly need to just find these and
+ * use them on PCI. At some point these might have their own uclass.
+ */
+enum {
+   X86_NONE,
+   X86_SYSCON_ME,  /* Intel Management Engine */
+};
+
 struct cpuid_result {
uint32_t eax;
uint32_t ebx;
diff --git a/configs/chromebox_panther_defconfig 
b/configs/chromebox_panther_defconfig
index 4b78292..bb6c5d4 100644
--- a/configs/chromebox_panther_defconfig
+++ b/configs/chromebox_panther_defconfig
@@ -16,6 +16,8 @@ CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_TPM=y
 CONFIG_CMD_TPM_TEST=y
 CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_CMD_CROS_EC=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_LPC=y
-- 
2.6.0.rc2.230.g3dd15c0

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[U-Boot] [PATCH v2 27/55] x86: ivybridge: Use driver model PCI API in bd82x6x.c

[Simon Glass]

Adjust most of the remaining functions in this file to use the driver model
PCI API. The one remaining function is bridge_silicon_revision() which will
need a little more work.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2:
- Drop northbridge_enable()

 arch/x86/cpu/ivybridge/northbridge.c  | 20 +++-
 arch/x86/include/asm/arch-ivybridge/sandybridge.h |  3 ---
 2 files changed, 7 insertions(+), 16 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/northbridge.c 
b/arch/x86/cpu/ivybridge/northbridge.c
index 2eed0af..d52eb39 100644
--- a/arch/x86/cpu/ivybridge/northbridge.c
+++ b/arch/x86/cpu/ivybridge/northbridge.c
@@ -48,15 +48,14 @@ int bridge_silicon_revision(void)
 static const int legacy_hole_base_k = 0xa / 1024;
 static const int legacy_hole_size_k = 384;
 
-static int get_pcie_bar(u32 *base, u32 *len)
+static int get_pcie_bar(struct udevice *dev, u32 *base, u32 *len)
 {
-   pci_dev_t dev = PCI_BDF(0, 0, 0);
u32 pciexbar_reg;
 
*base = 0;
*len = 0;
 
-   pciexbar_reg = x86_pci_read_config32(dev, PCIEXBAR);
+   dm_pci_read_config32(dev, PCIEXBAR, _reg);
 
if (!(pciexbar_reg & (1 << 0)))
return 0;
@@ -82,17 +81,17 @@ static int get_pcie_bar(u32 *base, u32 *len)
return 0;
 }
 
-static void add_fixed_resources(pci_dev_t dev, int index)
+static void add_fixed_resources(struct udevice *dev, int index)
 {
u32 pcie_config_base, pcie_config_size;
 
-   if (get_pcie_bar(_config_base, _config_size)) {
+   if (get_pcie_bar(dev, _config_base, _config_size)) {
debug("Adding PCIe config bar base=0x%08x size=0x%x\n",
  pcie_config_base, pcie_config_size);
}
 }
 
-static void northbridge_dmi_init(pci_dev_t dev)
+static void northbridge_dmi_init(struct udevice *dev)
 {
/* Clear error status bits */
writel(0x, DMIBAR_REG(0x1c4));
@@ -120,7 +119,7 @@ static void northbridge_dmi_init(pci_dev_t dev)
setbits_le32(DMIBAR_REG(0x88), (1 << 1) | (1 << 0));
 }
 
-void northbridge_init(pci_dev_t dev)
+static void northbridge_init(struct udevice *dev)
 {
u32 bridge_type;
 
@@ -168,10 +167,6 @@ void northbridge_init(pci_dev_t dev)
writel(0x0011, MCHBAR_REG(0x5500));
 }
 
-void northbridge_enable(pci_dev_t dev)
-{
-}
-
 static void sandybridge_setup_northbridge_bars(struct udevice *dev)
 {
/* Set up all hardcoded northbridge BARs */
@@ -228,8 +223,7 @@ static int bd82x6x_northbridge_probe(struct udevice *dev)
if (!(gd->flags & GD_FLG_RELOC))
return bd82x6x_northbridge_early_init(dev);
 
-   northbridge_enable(PCH_DEV);
-   northbridge_init(PCH_DEV);
+   northbridge_init(dev);
 
return 0;
 }
diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h 
b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
index c960525..af8a9f7 100644
--- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h
+++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
@@ -110,9 +110,6 @@
 
 int bridge_silicon_revision(void);
 
-void northbridge_enable(pci_dev_t dev);
-void northbridge_init(pci_dev_t dev);
-
 void report_platform_info(void);
 
 void sandybridge_early_init(int chipset_type);
-- 
2.6.0.rc2.230.g3dd15c0

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[U-Boot] [PATCH v2 43/55] x86: ivybridge: Convert sdram_initialise() to use DM PCI API

[Simon Glass]

Convert this function to use the the driver model PCI API. We just need
to pass in the northbridge device.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2: None

 arch/x86/cpu/ivybridge/sdram.c | 19 ++-
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index 5c1b788..6105cc0 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -283,9 +283,10 @@ static int recovery_mode_enabled(void)
 /**
  * Find the PEI executable in the ROM and execute it.
  *
- * @param pei_data: configuration data for UEFI PEI reference code
+ * @dev: Northbridge device
+ * @pei_data: configuration data for UEFI PEI reference code
  */
-int sdram_initialise(struct pei_data *pei_data)
+int sdram_initialise(struct udevice *dev, struct pei_data *pei_data)
 {
unsigned version;
const char *data;
@@ -374,7 +375,7 @@ int sdram_initialise(struct pei_data *pei_data)
 * Send ME init done for SandyBridge here.  This is done inside the
 * SystemAgent binary on IvyBridge
 */
-   done = x86_pci_read_config32(PCH_DEV, PCI_DEVICE_ID);
+   dm_pci_read_config16(dev, PCI_DEVICE_ID, );
done &= BASE_REV_MASK;
if (BASE_REV_SNB == done)
intel_early_me_init_done(ME_INIT_STATUS_SUCCESS);
@@ -732,12 +733,17 @@ int dram_init(void)
struct udevice *dev;
int ret;
 
+   ret = uclass_first_device(UCLASS_NORTHBRIDGE, );
+   if (ret)
+   return ret;
+   if (!dev)
+   return -ENODEV;
debug("Boot mode %d\n", gd->arch.pei_boot_mode);
debug("mrc_input %p\n", pei_data.mrc_input);
pei_data.boot_mode = gd->arch.pei_boot_mode;
ret = copy_spd(_data);
if (!ret)
-   ret = sdram_initialise(_data);
+   ret = sdram_initialise(dev, _data);
if (ret)
return ret;
 
@@ -748,11 +754,6 @@ int dram_init(void)
 
post_code(POST_DRAM);
 
-   ret = uclass_first_device(UCLASS_NORTHBRIDGE, );
-   if (ret)
-   return ret;
-   if (!dev)
-   return -ENODEV;
ret = sdram_find(dev);
if (ret)
return ret;
-- 
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[U-Boot] [PATCH v2 28/55] x86: ivybridge: Drop unnecessary northbridge setup

[Simon Glass]

This is done by default with PCI auto-config. Drop it.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Rename from 'Move northbridge setup to the northbridge driver'
- Drop this unnecessary init

 arch/x86/cpu/ivybridge/pci.c | 20 
 1 file changed, 20 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c
index 8af99b4..b081469 100644
--- a/arch/x86/cpu/ivybridge/pci.c
+++ b/arch/x86/cpu/ivybridge/pci.c
@@ -19,32 +19,12 @@
 
 static int pci_ivybridge_probe(struct udevice *bus)
 {
-   struct pci_controller *hose = dev_get_uclass_priv(bus);
-   pci_dev_t dev;
-   u16 reg16;
-
if (!(gd->flags & GD_FLG_RELOC))
return 0;
post_code(0x50);
bd82x6x_init_extra();
post_code(0x51);
 
-   reg16 = 0xff;
-   dev = PCH_DEV;
-   reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
-   reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-   x86_pci_write_config16(dev, PCI_COMMAND, reg16);
-
-   /*
-   * Clear non-reserved bits in status register.
-   */
-   pci_hose_write_config_word(hose, dev, PCI_STATUS, 0x);
-   pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
-   pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
-
-   pci_write_bar32(hose, dev, 0, 0xf000);
-   post_code(0x52);
-
return 0;
 }
 
-- 
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[U-Boot] [PATCH v2 42/55] x86: ivybridge: Convert dram_init() to use DM PCI API

[Simon Glass]

Convert the top part of the DRAM init to use the driver model PCI API.
Further work will complete the transformation.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2: None

 arch/x86/cpu/ivybridge/sdram.c | 39 +--
 1 file changed, 25 insertions(+), 14 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index 4372a5c..5c1b788 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -495,8 +495,10 @@ static int add_memory_area(struct memory_info *info,
  *
  * This is a bit complicated since on x86 there are system memory holes all
  * over the place. We create a list of available memory blocks
+ *
+ * @dev:   Northbridge device
  */
-static int sdram_find(pci_dev_t dev)
+static int sdram_find(struct udevice *dev)
 {
struct memory_info *info = >arch.meminfo;
uint32_t tseg_base, uma_size, tolud;
@@ -505,6 +507,7 @@ static int sdram_find(pci_dev_t dev)
uint64_t uma_memory_size;
unsigned long long tomk;
uint16_t ggc;
+   u32 val;
 
/* Total Memory 2GB example:
 *
@@ -533,24 +536,27 @@ static int sdram_find(pci_dev_t dev)
 */
 
/* Top of Upper Usable DRAM, including remap */
-   touud = x86_pci_read_config32(dev, TOUUD+4);
-   touud <<= 32;
-   touud |= x86_pci_read_config32(dev, TOUUD);
+   dm_pci_read_config32(dev, TOUUD + 4, );
+   touud = (uint64_t)val << 32;
+   dm_pci_read_config32(dev, TOUUD, );
+   touud |= val;
 
/* Top of Lower Usable DRAM */
-   tolud = x86_pci_read_config32(dev, TOLUD);
+   dm_pci_read_config32(dev, TOLUD, );
 
/* Top of Memory - does not account for any UMA */
-   tom = x86_pci_read_config32(dev, 0xa4);
-   tom <<= 32;
-   tom |= x86_pci_read_config32(dev, 0xa0);
+   dm_pci_read_config32(dev, 0xa4, );
+   tom = (uint64_t)val << 32;
+   dm_pci_read_config32(dev, 0xa0, );
+   tom |= val;
 
debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom);
 
/* ME UMA needs excluding if total memory <4GB */
-   me_base = x86_pci_read_config32(dev, 0x74);
-   me_base <<= 32;
-   me_base |= x86_pci_read_config32(dev, 0x70);
+   dm_pci_read_config32(dev, 0x74, );
+   me_base = (uint64_t)val << 32;
+   dm_pci_read_config32(dev, 0x70, );
+   me_base |= val;
 
debug("MEBASE %llx\n", me_base);
 
@@ -568,7 +574,7 @@ static int sdram_find(pci_dev_t dev)
}
 
/* Graphics memory comes next */
-   ggc = x86_pci_read_config16(dev, GGC);
+   dm_pci_read_config16(dev, GGC, );
if (!(ggc & 2)) {
debug("IGD decoded, subtracting ");
 
@@ -588,7 +594,7 @@ static int sdram_find(pci_dev_t dev)
}
 
/* Calculate TSEG size from its base which must be below GTT */
-   tseg_base = x86_pci_read_config32(dev, 0xb8);
+   dm_pci_read_config32(dev, 0xb8, _base);
uma_size = (uma_memory_base - tseg_base) >> 10;
tomk -= uma_size;
uma_memory_base = tomk * 1024ULL;
@@ -723,7 +729,7 @@ int dram_init(void)
{ 0, 4, 0x }, /* P13= Empty */
},
};
-   pci_dev_t dev = PCI_BDF(0, 0, 0);
+   struct udevice *dev;
int ret;
 
debug("Boot mode %d\n", gd->arch.pei_boot_mode);
@@ -742,6 +748,11 @@ int dram_init(void)
 
post_code(POST_DRAM);
 
+   ret = uclass_first_device(UCLASS_NORTHBRIDGE, );
+   if (ret)
+   return ret;
+   if (!dev)
+   return -ENODEV;
ret = sdram_find(dev);
if (ret)
return ret;
-- 
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[U-Boot] [PATCH v2 44/55] x86: chromebook_link: Enable the syscon uclass

[Simon Glass]

We will use a system controller to model the Intel Management Engine. Enable
this for link.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2: None

 configs/chromebook_link_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/chromebook_link_defconfig 
b/configs/chromebook_link_defconfig
index daa958e..f44bef7 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@@ -20,6 +20,8 @@ CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_TPM=y
 CONFIG_CMD_TPM_TEST=y
 CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_SYS_I2C_INTEL=y
 CONFIG_CMD_CROS_EC=y
-- 
2.6.0.rc2.230.g3dd15c0

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Re: [U-Boot] [PATCH 12/18] dm: video: Implement the bmp command for driver model

[Anatolij Gustschin]

On Tue,  5 Jan 2016 09:31:08 -0700
Simon Glass  wrote:

> This command can use the bitmap display code in the uclass. This is similar
> to the code in lcd.c and cfb_console.c. These other copies will go away when
> all boards are converted to use driver model for video.
> 
> Signed-off-by: Simon Glass 
> ---
> 
>  common/cmd_bmp.c  |  22 ++-
>  drivers/video/Makefile|   1 +
>  drivers/video/video_bmp.c | 353 
> ++
>  3 files changed, 375 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/video/video_bmp.c

Acked-by: Anatolij Gustschin 

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Re: [U-Boot] [PATCH 15/18] dm: video: sandbox: Convert sandbox to use driver model for video

[Anatolij Gustschin]

On Tue,  5 Jan 2016 09:31:11 -0700
Simon Glass  wrote:

> Now that driver model support is available, convert sandbox over to use it.
> We can remove a few of the special hooks that sandbox currently has.
> 
> Signed-off-by: Simon Glass 
> ---
> 
>  arch/sandbox/dts/sandbox.dts |  1 +
>  board/sandbox/sandbox.c  | 17 
>  common/lcd.c | 11 -
>  configs/sandbox_defconfig|  1 +
>  drivers/serial/sandbox.c |  5 +--
>  drivers/video/sandbox_sdl.c  | 95 
> ++--
>  include/configs/sandbox.h| 10 ++---
>  include/fdtdec.h |  1 -
>  lib/fdtdec.c |  1 -
>  9 files changed, 56 insertions(+), 86 deletions(-)

Acked-by: Anatolij Gustschin 

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[U-Boot] [PATCH v2 39/55] x86: i2c: Add a stub driver for Intel I2C/SMbus

[Simon Glass]

This is used on most Intel platforms. We don't have a driver for it yet, but
add a stub to handle the init. For now this targets ivybridge so we may want
to add a device tree binding and generalise it when other platforms are
supported.

Signed-off-by: Simon Glass 
Reviewed-by: Heiko Schocher 
Reviewed-by: Bin Meng 
---

Changes in v2:
- Expand the Kconfig help a little

 drivers/i2c/Kconfig |  9 +
 drivers/i2c/Makefile|  1 +
 drivers/i2c/intel_i2c.c | 51 +
 3 files changed, 61 insertions(+)
 create mode 100644 drivers/i2c/intel_i2c.c

diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 14adda2..46b83e7 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -58,6 +58,15 @@ config DM_I2C_GPIO
  bindings are supported.
  Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
 
+config SYS_I2C_INTEL
+   bool "Intel I2C/SMBUS driver"
+   depends on DM_I2C
+   help
+ Add support for the Intel SMBUS driver. So far this driver is just
+ a stub which perhaps some basic init. There is no implementation of
+ the I2C API meaning that any I2C operations will immediately fail
+ for now.
+
 config SYS_I2C_ROCKCHIP
bool "Rockchip I2C driver"
depends on DM_I2C
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 811ad9b..a2a956a 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
 obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
 obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
 obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
+obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o
 obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
 obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o
 obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
diff --git a/drivers/i2c/intel_i2c.c b/drivers/i2c/intel_i2c.c
new file mode 100644
index 000..1082d1a
--- /dev/null
+++ b/drivers/i2c/intel_i2c.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+int intel_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
+{
+   return -ENOSYS;
+}
+
+int intel_i2c_probe_chip(struct udevice *bus, uint chip_addr, uint chip_flags)
+{
+   return -ENOSYS;
+}
+
+int intel_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
+{
+   return 0;
+}
+
+static int intel_i2c_probe(struct udevice *dev)
+{
+   return 0;
+}
+
+static const struct dm_i2c_ops intel_i2c_ops = {
+   .xfer   = intel_i2c_xfer,
+   .probe_chip = intel_i2c_probe_chip,
+   .set_bus_speed  = intel_i2c_set_bus_speed,
+};
+
+static const struct udevice_id intel_i2c_ids[] = {
+   { .compatible = "intel,ich-i2c" },
+   { }
+};
+
+U_BOOT_DRIVER(intel_i2c) = {
+   .name   = "i2c_intel",
+   .id = UCLASS_I2C,
+   .of_match = intel_i2c_ids,
+   .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip),
+   .ops= _i2c_ops,
+   .probe  = intel_i2c_probe,
+};
-- 
2.6.0.rc2.230.g3dd15c0

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[U-Boot] [PATCH v2 33/55] x86: ivybridge: Use driver model PCI API in sata.c

[Simon Glass]

Adjust the functions in this file to use the driver model PCI API.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Drop unnecessary IRQ and command register init

 arch/x86/cpu/ivybridge/sata.c | 94 +--
 1 file changed, 45 insertions(+), 49 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c
index 6314566..21e11d1 100644
--- a/arch/x86/cpu/ivybridge/sata.c
+++ b/arch/x86/cpu/ivybridge/sata.c
@@ -15,42 +15,47 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static inline u32 sir_read(pci_dev_t dev, int idx)
+static inline u32 sir_read(struct udevice *dev, int idx)
 {
-   x86_pci_write_config32(dev, SATA_SIRI, idx);
-   return x86_pci_read_config32(dev, SATA_SIRD);
+   u32 data;
+
+   dm_pci_write_config32(dev, SATA_SIRI, idx);
+   dm_pci_read_config32(dev, SATA_SIRD, );
+
+   return data;
 }
 
-static inline void sir_write(pci_dev_t dev, int idx, u32 value)
+static inline void sir_write(struct udevice *dev, int idx, u32 value)
 {
-   x86_pci_write_config32(dev, SATA_SIRI, idx);
-   x86_pci_write_config32(dev, SATA_SIRD, value);
+   dm_pci_write_config32(dev, SATA_SIRI, idx);
+   dm_pci_write_config32(dev, SATA_SIRD, value);
 }
 
-static void common_sata_init(pci_dev_t dev, unsigned int port_map)
+static void common_sata_init(struct udevice *dev, unsigned int port_map)
 {
u32 reg32;
u16 reg16;
 
/* Set IDE I/O Configuration */
reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
-   x86_pci_write_config32(dev, IDE_CONFIG, reg32);
+   dm_pci_write_config32(dev, IDE_CONFIG, reg32);
 
/* Port enable */
-   reg16 = x86_pci_read_config16(dev, 0x92);
+   dm_pci_read_config16(dev, 0x92, );
reg16 &= ~0x3f;
reg16 |= port_map;
-   x86_pci_write_config16(dev, 0x92, reg16);
+   dm_pci_write_config16(dev, 0x92, reg16);
 
/* SATA Initialization register */
port_map &= 0xff;
-   x86_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183);
+   dm_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183);
 }
 
-static void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node)
+static void bd82x6x_sata_init(struct udevice *dev)
 {
unsigned int port_map, speed_support, port_tx;
-   struct pci_controller *hose = pci_bus_to_hose(0);
+   const void *blob = gd->fdt_blob;
+   int node = dev->of_offset;
const char *mode;
u32 reg32;
u16 reg16;
@@ -62,33 +67,27 @@ static void bd82x6x_sata_init(pci_dev_t dev, const void 
*blob, int node)
speed_support = fdtdec_get_int(blob, node,
   "sata_interface_speed_support", 0);
 
-   /* Enable BARs */
-   x86_pci_write_config16(dev, PCI_COMMAND, 0x0007);
-
mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
if (!mode || !strcmp(mode, "ahci")) {
u32 abar;
 
debug("SATA: Controller in AHCI mode\n");
 
-   /* Set Interrupt Line, Interrupt Pin is set by D31IP.PIP */
-   x86_pci_write_config8(dev, INTR_LN, 0x0a);
-
/* Set timings */
-   x86_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+   dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
IDE_PPE0 | IDE_IE0 | IDE_TIME0);
-   x86_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+   dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
 
/* Sync DMA */
-   x86_pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
-   x86_pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
+   dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
+   dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
 
common_sata_init(dev, 0x8000 | port_map);
 
/* Initialize AHCI memory-mapped space */
-   abar = pci_read_bar32(hose, dev, 5);
+   abar = dm_pci_read_bar32(dev, 5);
debug("ABAR: %08X\n", abar);
/* CAP (HBA Capabilities) : enable power management */
reg32 = readl(abar + 0x00);
@@ -116,59 +115,54 @@ static void bd82x6x_sata_init(pci_dev_t dev, const void 
*blob, int node)
debug("SATA: Controller in combined mode\n");
 
/* No AHCI: clear AHCI base */
-   pci_write_bar32(hose, dev, 5, 0x);
+   dm_pci_write_bar32(dev, 5, 0x);
/* And without AHCI BAR no memory decoding */
-   reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
+   dm_pci_read_config16(dev, PCI_COMMAND, );
reg16 &= ~PCI_COMMAND_MEMORY;
-   

[U-Boot] [PATCH v2 36/55] x86: ivybridge: Drop the special PCI driver

[Simon Glass]

There is nothing special about the ivybridge pci driver now, so just use
the generic one.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Drop the special compatible string in chromebook_link.dts

 arch/x86/cpu/ivybridge/Makefile  |  1 -
 arch/x86/cpu/ivybridge/pci.c | 46 
 arch/x86/dts/chromebook_link.dts |  2 +-
 3 files changed, 1 insertion(+), 48 deletions(-)
 delete mode 100644 arch/x86/cpu/ivybridge/pci.c

diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index bdbd3fa..259a5df 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -15,7 +15,6 @@ obj-y += model_206ax.o
 obj-y += microcode_intel.o
 obj-y += northbridge.o
 obj-y += pch.o
-obj-y += pci.o
 obj-y += report_platform.o
 obj-y += sata.o
 obj-y += sdram.o
diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c
deleted file mode 100644
index 5195002..000
--- a/arch/x86/cpu/ivybridge/pci.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- * (C) Copyright 2008,2009
- * Graeme Russ, 
- *
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, 
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-static int pci_ivybridge_probe(struct udevice *bus)
-{
-   if (!(gd->flags & GD_FLG_RELOC))
-   return 0;
-   post_code(0x50);
-   post_code(0x51);
-
-   return 0;
-}
-
-static const struct dm_pci_ops pci_ivybridge_ops = {
-   .read_config= pci_x86_read_config,
-   .write_config   = pci_x86_write_config,
-};
-
-static const struct udevice_id pci_ivybridge_ids[] = {
-   { .compatible = "intel,pci-ivybridge" },
-   { }
-};
-
-U_BOOT_DRIVER(pci_ivybridge_drv) = {
-   .name   = "pci_ivybridge",
-   .id = UCLASS_PCI,
-   .of_match   = pci_ivybridge_ids,
-   .ops= _ivybridge_ops,
-   .probe  = pci_ivybridge_probe,
-};
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index 022b04c..18305a3 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -193,7 +193,7 @@
};
 
pci {
-   compatible = "intel,pci-ivybridge", "pci-x86";
+   compatible = "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
-- 
2.6.0.rc2.230.g3dd15c0

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[U-Boot] [PATCH v2 15/55] x86: ivybridge: Move graphics init much later

[Simon Glass]

We don't need to init the graphics controller so early. Move it alongside
the other graphics setup, just before we run the ROM.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2: None

 arch/x86/cpu/ivybridge/cpu.c|  1 -
 arch/x86/cpu/ivybridge/early_init.c | 80 ++---
 arch/x86/cpu/ivybridge/gma.c| 73 +
 3 files changed, 76 insertions(+), 78 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 65eea1f..c3626c4 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -250,7 +250,6 @@ int print_cpuinfo(void)
return ret;
if (!dev)
return -ENODEV;
-   sandybridge_early_init(SANDYBRIDGE_MOBILE);
 
/* Check PM1_STS[15] to see if we are waking from Sx */
pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
diff --git a/arch/x86/cpu/ivybridge/early_init.c 
b/arch/x86/cpu/ivybridge/early_init.c
index 029f5ef..83ef7b7 100644
--- a/arch/x86/cpu/ivybridge/early_init.c
+++ b/arch/x86/cpu/ivybridge/early_init.c
@@ -53,83 +53,6 @@ static void sandybridge_setup_northbridge_bars(struct 
udevice *dev)
dm_pci_write_config8(dev, PAM6, 0x33);
 }
 
-static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev)
-{
-   u32 reg32;
-   u16 reg16;
-   u8 reg8;
-
-   reg16 = x86_pci_read_config16(video_dev, PCI_DEVICE_ID);
-   switch (reg16) {
-   case 0x0102: /* GT1 Desktop */
-   case 0x0106: /* GT1 Mobile */
-   case 0x010a: /* GT1 Server */
-   case 0x0112: /* GT2 Desktop */
-   case 0x0116: /* GT2 Mobile */
-   case 0x0122: /* GT2 Desktop >=1.3GHz */
-   case 0x0126: /* GT2 Mobile >=1.3GHz */
-   case 0x0156: /* IvyBridge */
-   case 0x0166: /* IvyBridge */
-   break;
-   default:
-   debug("Graphics not supported by this CPU/chipset\n");
-   return;
-   }
-
-   debug("Initialising Graphics\n");
-
-   /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
-   reg16 = x86_pci_read_config16(pch_dev, GGC);
-   reg16 &= ~0x00f8;
-   reg16 |= 1 << 3;
-   /* Program GTT memory by setting GGC[9:8] = 2MB */
-   reg16 &= ~0x0300;
-   reg16 |= 2 << 8;
-   /* Enable VGA decode */
-   reg16 &= ~0x0002;
-   x86_pci_write_config16(pch_dev, GGC, reg16);
-
-   /* Enable 256MB aperture */
-   reg8 = x86_pci_read_config8(video_dev, MSAC);
-   reg8 &= ~0x06;
-   reg8 |= 0x02;
-   x86_pci_write_config8(video_dev, MSAC, reg8);
-
-   /* Erratum workarounds */
-   reg32 = readl(MCHBAR_REG(0x5f00));
-   reg32 |= (1 << 9) | (1 << 10);
-   writel(reg32, MCHBAR_REG(0x5f00));
-
-   /* Enable SA Clock Gating */
-   reg32 = readl(MCHBAR_REG(0x5f00));
-   writel(reg32 | 1, MCHBAR_REG(0x5f00));
-
-   /* GPU RC6 workaround for sighting 366252 */
-   reg32 = readl(MCHBAR_REG(0x5d14));
-   reg32 |= (1 << 31);
-   writel(reg32, MCHBAR_REG(0x5d14));
-
-   /* VLW */
-   reg32 = readl(MCHBAR_REG(0x6120));
-   reg32 &= ~(1 << 0);
-   writel(reg32, MCHBAR_REG(0x6120));
-
-   reg32 = readl(MCHBAR_REG(0x5418));
-   reg32 |= (1 << 4) | (1 << 5);
-   writel(reg32, MCHBAR_REG(0x5418));
-}
-
-void sandybridge_early_init(int chipset_type)
-{
-   pci_dev_t pch_dev = PCH_DEV;
-   pci_dev_t video_dev = PCH_VIDEO_DEV;
-
-   /* Device Enable */
-   x86_pci_write_config32(pch_dev, DEVEN, DEVEN_HOST | DEVEN_IGD);
-
-   sandybridge_setup_graphics(pch_dev, video_dev);
-}
-
 static int bd82x6x_northbridge_probe(struct udevice *dev)
 {
const int chipset_type = SANDYBRIDGE_MOBILE;
@@ -155,6 +78,9 @@ static int bd82x6x_northbridge_probe(struct udevice *dev)
 
sandybridge_setup_northbridge_bars(dev);
 
+   /* Device Enable */
+   dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD);
+
return 0;
 }
 
diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c
index 85a09c6..1748f7f 100644
--- a/arch/x86/cpu/ivybridge/gma.c
+++ b/arch/x86/cpu/ivybridge/gma.c
@@ -8,6 +8,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -728,16 +729,88 @@ static int int15_handler(void)
return res;
 }
 
+void sandybridge_setup_graphics(struct udevice *dev, struct udevice *video_dev)
+{
+   u32 reg32;
+   u16 reg16;
+   u8 reg8;
+
+   dm_pci_read_config16(video_dev, PCI_DEVICE_ID, );
+   switch (reg16) {
+   case 0x0102: /* GT1 Desktop */
+   case 0x0106: /* GT1 Mobile */
+   case 0x010a: /* GT1 Server */
+   case 0x0112: /* GT2 Desktop */
+   case 0x0116: /* GT2 Mobile */
+   case 0x0122: /* GT2 Desktop >=1.3GHz */
+   case 0x0126: /* GT2 Mobile >=1.3GHz */
+   case 0x0156: /* IvyBridge */
+   case 0x0166: /* IvyBridge */
+   break;
+ 

Re: [U-Boot] [PATCH 13/18] dm: stdio: video: Plumb the video uclass into stdio

[Anatolij Gustschin]

On Tue,  5 Jan 2016 09:31:09 -0700
Simon Glass  wrote:

> Register video drivers with stdio so that they can be used for text output.
> This needs to be done explicitly for now. At some point we should be able to
> convert stdio itself to driver model and avoid this step.
> 
> Signed-off-by: Simon Glass 
> ---
> 
>  common/stdio.c | 19 +++
>  1 file changed, 15 insertions(+), 4 deletions(-)

Acked-by: Anatolij Gustschin 

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[U-Boot] [PATCH v2 01/55] dm: core: Display the error number when driver binding fails

[Simon Glass]

This is often -96 (-EPFNOSUPPORT) which indicates that the uclass is not
compiled in. Display the error number to make this easier to spot.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2:
- Fix -EEPFNOSUPPORT typo

 drivers/core/lists.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/core/lists.c b/drivers/core/lists.c
index a1c9478..c4fc216 100644
--- a/drivers/core/lists.c
+++ b/drivers/core/lists.c
@@ -172,7 +172,8 @@ int lists_bind_fdt(struct udevice *parent, const void 
*blob, int offset,
dm_dbg("   - found match at '%s'\n", entry->name);
ret = device_bind(parent, entry, name, NULL, offset, );
if (ret) {
-   dm_warn("Error binding driver '%s'\n", entry->name);
+   dm_warn("Error binding driver '%s': %d\n", entry->name,
+   ret);
return ret;
} else {
dev->driver_data = id->data;
-- 
2.6.0.rc2.230.g3dd15c0

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[U-Boot] [PATCH v2 00/55] dm: x86: Convert ivybridge code to use driver model

[Simon Glass]

At present ivybridge is the only x86 implementation that includes a
reasonably full board init. This means there is a lot more code than with
a board that uses FSP (even then we don't have memory init or graphics init
code).

This code does not use proper drivers for the devices and so its use of
driver model is limited. This series refactors the code to improve this. In
particular it drops use of the old x86_pci_...() API in favour of
dm_pci_...(). The latter requires that each PCI device has a driver.

A few very minor driver model improvements are added to support this. Also a
Northbridge uclass is added - this could instead be done with the syscon, so
comments are well as to which is best.

A small amount of additional work will be needed to remove use of the
x86_pci_...() in arch/x86, but this series represents the bulk of it.

Changes in v2:
- Fix -EEPFNOSUPPORT typo
- Add missing of_match member init so that ehci_pci_ids[] is used
- Add missing 'given' word
- Drop unnecessary/incorrect non-DM code in dm_pci_run_vga_bios()
- Drop unused 'gen-dec' device tree property
- Drop the init() method in the PCH
- Rename this commit from 'x86: ivybridge: Set up the PCH init'
- Drop unnecessary DECLARE_GLOBAL_DATA_PTR
- Drop explicit PCH probe
- Drop LPC init method
- Rename patch from 'Add an init() method for the bd82x6x LPC'
- Update to drop LPC init method and use probe() instead
- Fix 'baords' typo in the commit message
- Add a comment as to why we are initing the devices again
- Drop northbridge_enable()
- Rename from 'Move northbridge setup to the northbridge driver'
- Drop this unnecessary init
- Rename the AHCI uclass to DISK
- Update to use the disk uclass
- Update to use the disk uclass
- Drop unnecessary IRQ and command register init
- Update to use LPC probe() method instead of init()
- Drop the special compatible string in chromebook_link.dts
- Expand the Kconfig help a little
- Avoid needing the pch device to set up the USB bar
- Fix incorrect bits in bridge_silicon_revision() comment
- Rename from 'Convert EHCI init to use the DM PCI API'
- Drop this init
- Fix the USB PCI address in the device tree
- Enable SYSCON and REGMAP for panther to avoid a build error
- Drop bd82x6x_pci_init() function and associated DM-conversion patch
- Drop LPC init method an 'Add an init() method to the LPC uclass' patch

Simon Glass (55):
  dm: core: Display the error number when driver binding fails
  dm: usb: Add a compatible string for PCI EHCI controller
  dm: syscon: Allow finding devices by driver data
  dm: pci: Convert bios_emu to use the driver model PCI API
  x86: ivybridge: Set up the LPC device using driver model
  x86: ivybridge: Move lpc_early_init() to probe()
  x86: ivybridge: Move more init to the probe() function
  x86: ivybridge: Rename bd82x6x_init()
  dm: x86: Add a northbridge uclass
  x86: ivybridge: Add a driver for the bd82x6x northbridge
  x86: ivybridge: Move northbridge init into the probe() method
  x86: ivybridge: Move LPC and PCH init into northbridge probe()
  x86: ivybridge: Rename lpc_init() to lpc_init_extra()
  x86: ivybridge: Probe the LPC in CPU init
  x86: ivybridge: Move graphics init much later
  x86: ivybridge: Move sandybridge init to the lpc probe() method
  x86: ivybridge: Move GPIO init to the LPC init() method
  x86: ivybridge: Use common CPU init code
  x86: ivybridge: Move CPU init code into the driver
  x86: ivybridge: Set up the thermal target correctly
  x86: ivybridge: Drop the dead MTRR code
  x86: ivybridge: Move early init code into northbridge.c
  x86: Make x86_init_cpus() static
  x86: Don't show an error when the MRC cache is up to date
  x86: Bring up northbridge, pch and lpc after the CPUs
  x86: ivybridge: Move northbridge and PCH init into drivers
  x86: ivybridge: Use driver model PCI API in bd82x6x.c
  x86: ivybridge: Drop unnecessary northbridge setup
  ahci: Add a disk-controller uclass
  x86: ivybridge: Do the SATA init before relocation
  x86: ivybridge: Drop the unused bd82x6x_init_extra()
  x86: ivybridge: Use the SATA driver to do the init
  x86: ivybridge: Use driver model PCI API in sata.c
  x86: ivybridge: Move lpc_enable() into gma.c
  x86: ivybridge: Move LPC init into the LPC probe() method
  x86: ivybridge: Drop the special PCI driver
  x86: ivybridge: Convert lpc init code to DM PCI API
  x86: Enable DM_USB for link and panther
  x86: i2c: Add a stub driver for Intel I2C/SMbus
  x86: ivybridge: Use the I2C driver to perform SMbus init
  x86: ivybridge: Convert enable_usb_bar() to use DM PCI API
  x86: ivybridge: Convert dram_init() to use DM PCI API
  x86: ivybridge: Convert sdram_initialise() to use DM PCI API
  x86: chromebook_link: Enable the syscon uclass
  x86: ivybridge: Convert SDRAM init to use driver model
  x86: ivybridge: Convert report_platform to DM PCI API
  x86: ivybridge: Convert pch.c to use DM PCI API
  x86: ivybridge: Move code from pch.c to bd82x6x.c
  x86: ivybridge: Sort out the calls to bridge_silicon_revision()
 

[U-Boot] [PATCH v2 24/55] x86: Don't show an error when the MRC cache is up to date

[Simon Glass]

When the final MRC cache record is the same as the one we want to write, we
skip writing since there is no point. This is normal behaviour.

Avoiding printing an error when this happens.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2: None

 arch/x86/lib/mrccache.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c
index 53a1259..67bace4 100644
--- a/arch/x86/lib/mrccache.c
+++ b/arch/x86/lib/mrccache.c
@@ -243,8 +243,12 @@ int mrccache_save(void)
goto err_entry;
data  = (struct mrc_data_container *)gd->arch.mrc_output;
ret = mrccache_update(sf, , data);
-   if (!ret)
+   if (!ret) {
debug("Saved MRC data with checksum %04x\n", data->checksum);
+   } else if (ret == -EEXIST) {
+   debug("MRC data is the same as last time, skipping save\n");
+   ret = 0;
+   }
 
 err_entry:
if (ret)
-- 
2.6.0.rc2.230.g3dd15c0

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[U-Boot] [PATCH v2 31/55] x86: ivybridge: Drop the unused bd82x6x_init_extra()

[Simon Glass]

This function does nothing now so can be dropped.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2: None

 arch/x86/cpu/ivybridge/bd82x6x.c  | 16 
 arch/x86/cpu/ivybridge/pci.c  |  1 -
 arch/x86/include/asm/arch-ivybridge/bd82x6x.h |  1 -
 3 files changed, 18 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 8e98fa2..1fe2ce1 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -56,22 +56,6 @@ static int bd82x6x_probe(struct udevice *dev)
return 0;
 }
 
-/* TODO(s...@chromium.org): Move this to the PCH init() method */
-int bd82x6x_init_extra(void)
-{
-   const void *blob = gd->fdt_blob;
-   int sata_node;
-
-   sata_node = fdtdec_next_compatible(blob, 0,
-  COMPAT_INTEL_PANTHERPOINT_AHCI);
-   if (sata_node < 0) {
-   debug("%s: Cannot find SATA node\n", __func__);
-   return -EINVAL;
-   }
-
-   return 0;
-}
-
 static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep)
 {
u32 rcba;
diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c
index b081469..5195002 100644
--- a/arch/x86/cpu/ivybridge/pci.c
+++ b/arch/x86/cpu/ivybridge/pci.c
@@ -22,7 +22,6 @@ static int pci_ivybridge_probe(struct udevice *bus)
if (!(gd->flags & GD_FLG_RELOC))
return 0;
post_code(0x50);
-   bd82x6x_init_extra();
post_code(0x51);
 
return 0;
diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h 
b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
index faae5ff..7a05c7e 100644
--- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
+++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
@@ -11,6 +11,5 @@ void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int 
node);
 void bd82x6x_usb_ehci_init(pci_dev_t dev);
 void bd82x6x_usb_xhci_init(pci_dev_t dev);
 int gma_func0_init(struct udevice *dev, const void *blob, int node);
-int bd82x6x_init_extra(void);
 
 #endif
-- 
2.6.0.rc2.230.g3dd15c0

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[U-Boot] [PATCH v2 16/55] x86: ivybridge: Move sandybridge init to the lpc probe() method

[Simon Glass]

The watchdog can be reset later when probing the LPC after relocation.
Move it.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2:
- Update to drop LPC init method and use probe() instead

 arch/x86/cpu/ivybridge/early_init.c | 16 
 arch/x86/cpu/ivybridge/lpc.c| 19 ++-
 2 files changed, 18 insertions(+), 17 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/early_init.c 
b/arch/x86/cpu/ivybridge/early_init.c
index 83ef7b7..5b16abc 100644
--- a/arch/x86/cpu/ivybridge/early_init.c
+++ b/arch/x86/cpu/ivybridge/early_init.c
@@ -14,20 +14,6 @@
 #include 
 #include 
 
-static void sandybridge_setup_lpc_bars(pci_dev_t lpc_dev)
-{
-   /* Setting up Southbridge. In the northbridge code. */
-   debug("Setting up static southbridge registers\n");
-   x86_pci_write_config32(lpc_dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
-
-   x86_pci_write_config32(lpc_dev, PMBASE, DEFAULT_PMBASE | 1);
-   x86_pci_write_config8(lpc_dev, ACPI_CNTL, 0x80); /* Enable ACPI BAR */
-
-   debug("Disabling watchdog reboot\n");
-   setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */
-   outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08);/* halt timer */
-}
-
 static void sandybridge_setup_northbridge_bars(struct udevice *dev)
 {
/* Set up all hardcoded northbridge BARs */
@@ -74,8 +60,6 @@ static int bd82x6x_northbridge_probe(struct udevice *dev)
dm_pci_write_config8(dev, 0xf3, reg8);
}
 
-   sandybridge_setup_lpc_bars(PCH_LPC_DEV);
-
sandybridge_setup_northbridge_bars(dev);
 
/* Device Enable */
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 9f41f22..c88733d 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -609,6 +609,23 @@ void lpc_enable(pci_dev_t dev)
setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
 }
 
+static int bd82x6x_lpc_early_init(struct udevice *dev)
+{
+   /* Setting up Southbridge. In the northbridge code. */
+   debug("Setting up static southbridge registers\n");
+   dm_pci_write_config32(dev->parent, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
+   dm_pci_write_config32(dev->parent, PMBASE, DEFAULT_PMBASE | 1);
+
+   /* Enable ACPI BAR */
+   dm_pci_write_config8(dev->parent, ACPI_CNTL, 0x80);
+
+   debug("Disabling watchdog reboot\n");
+   setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */
+   outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08);/* halt timer */
+
+   return 0;
+}
+
 static int bd82x6x_lpc_probe(struct udevice *dev)
 {
int ret;
@@ -622,7 +639,7 @@ static int bd82x6x_lpc_probe(struct udevice *dev)
return ret;
}
 
-   return 0;
+   return bd82x6x_lpc_early_init(dev);
 }
 
 static const struct udevice_id bd82x6x_lpc_ids[] = {
-- 
2.6.0.rc2.230.g3dd15c0

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[U-Boot] [PATCH v2 10/55] x86: ivybridge: Add a driver for the bd82x6x northbridge

[Simon Glass]

Add a driver with an empty probe function where we can move init code in
follow-on patches.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2: None

 arch/x86/cpu/ivybridge/early_init.c | 18 ++
 arch/x86/dts/chromebook_link.dts|  7 +++
 2 files changed, 25 insertions(+)

diff --git a/arch/x86/cpu/ivybridge/early_init.c 
b/arch/x86/cpu/ivybridge/early_init.c
index 9ca008e..945ae2d 100644
--- a/arch/x86/cpu/ivybridge/early_init.c
+++ b/arch/x86/cpu/ivybridge/early_init.c
@@ -8,6 +8,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -145,3 +146,20 @@ void sandybridge_early_init(int chipset_type)
 
sandybridge_setup_graphics(pch_dev, video_dev);
 }
+
+static int bd82x6x_northbridge_probe(struct udevice *dev)
+{
+   return 0;
+}
+
+static const struct udevice_id bd82x6x_northbridge_ids[] = {
+   { .compatible = "intel,bd82x6x-northbridge" },
+   { }
+};
+
+U_BOOT_DRIVER(bd82x6x_northbridge_drv) = {
+   .name   = "bd82x6x_northbridge",
+   .id = UCLASS_NORTHBRIDGE,
+   .of_match   = bd82x6x_northbridge_ids,
+   .probe  = bd82x6x_northbridge_probe,
+};
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index f2db844..e2c722d 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -166,6 +166,13 @@
ranges = <0x0200 0x0 0xe000 0xe000 0 0x1000
0x4200 0x0 0xd000 0xd000 0 0x1000
0x0100 0x0 0x1000 0x1000 0 0xefff>;
+
+   northbridge@0,0 {
+   reg = <0x 0 0 0 0>;
+   compatible = "intel,bd82x6x-northbridge";
+   u-boot,dm-pre-reloc;
+   };
+
sata {
compatible = "intel,pantherpoint-ahci";
intel,sata-mode = "ahci";
-- 
2.6.0.rc2.230.g3dd15c0

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[U-Boot] [PATCH v2 06/55] x86: ivybridge: Move lpc_early_init() to probe()

[Simon Glass]

Move this code to the LPC's probe() method so that it will happen
automatically when the LPC is probed before relocation.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Drop unused 'gen-dec' device tree property

 arch/x86/cpu/ivybridge/cpu.c  |  9 -
 arch/x86/cpu/ivybridge/lpc.c  | 32 ---
 arch/x86/dts/chromebook_link.dts  |  3 +--
 arch/x86/include/asm/arch-ivybridge/pch.h | 10 --
 4 files changed, 26 insertions(+), 28 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 6ffc843..4c6ffb2 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -124,10 +124,8 @@ int arch_cpu_init(void)
 
 int arch_cpu_init_dm(void)
 {
-   const void *blob = gd->fdt_blob;
struct pci_controller *hose;
struct udevice *bus, *dev;
-   int node;
int ret;
 
post_code(0x70);
@@ -145,13 +143,6 @@ int arch_cpu_init_dm(void)
if (!dev)
return -ENODEV;
 
-   node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH);
-   if (node < 0)
-   return -ENOENT;
-   ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV);
-   if (ret)
-   return ret;
-
enable_spi_prefetch(hose, PCH_LPC_DEV);
 
/* This is already done in start.S, but let's do it in C */
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 51a4073..9d089c7 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -454,7 +454,13 @@ static void pch_fixups(pci_dev_t dev)
setbits_le32(RCB_REG(0x21a8), 0x3);
 }
 
-int lpc_early_init(const void *blob, int node, pci_dev_t dev)
+/**
+ * lpc_early_init() - set up LPC serial ports and other early things
+ *
+ * @dev:   LPC device
+ * @return 0 if OK, -ve on error
+ */
+static int lpc_early_init(struct udevice *dev)
 {
struct reg_info {
u32 base;
@@ -463,17 +469,18 @@ int lpc_early_init(const void *blob, int node, pci_dev_t 
dev)
int count;
int i;
 
-   count = fdtdec_get_int_array_count(blob, node, "intel,gen-dec",
-   (u32 *)values, sizeof(values) / sizeof(u32));
+   count = fdtdec_get_int_array_count(gd->fdt_blob, dev->of_offset,
+   "intel,gen-dec", (u32 *)values,
+   sizeof(values) / sizeof(u32));
if (count < 0)
return -EINVAL;
 
/* Set COM1/COM2 decode range */
-   x86_pci_write_config16(dev, LPC_IO_DEC, 0x0010);
+   dm_pci_write_config16(dev->parent, LPC_IO_DEC, 0x0010);
 
/* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
-   x86_pci_write_config16(dev, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
-  GAMEL_LPC_EN | COMA_LPC_EN);
+   dm_pci_write_config16(dev->parent, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
+ GAMEL_LPC_EN | COMA_LPC_EN);
 
/* Write all registers but use 0 if we run out of data */
count = count * sizeof(u32) / sizeof(values[0]);
@@ -482,7 +489,7 @@ int lpc_early_init(const void *blob, int node, pci_dev_t 
dev)
 
if (i < count)
reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16);
-   x86_pci_write_config32(dev, LPC_GENX_DEC(i), reg);
+   dm_pci_write_config32(dev->parent, LPC_GENX_DEC(i), reg);
}
 
return 0;
@@ -561,6 +568,17 @@ void lpc_enable(pci_dev_t dev)
 
 static int bd82x6x_lpc_probe(struct udevice *dev)
 {
+   int ret;
+
+   if (gd->flags & GD_FLG_RELOC)
+   return 0;
+
+   ret = lpc_early_init(dev);
+   if (ret) {
+   debug("%s: lpc_early_init() failed\n", __func__);
+   return ret;
+   }
+
return 0;
 }
 
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index d5c5bfd..f2db844 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -192,8 +192,6 @@
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
-   gen-dec = <0x800 0xfc 0x900 0xfc>;
-   intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
0x80 0x80 0x80 0x80>;
intel,gpi-routing = <0 0 0 0 0 0 0 2
@@ -224,6 +222,7 @@
#address-cells = <1>;
#size-cells = <0>;
u-boot,dm-pre-reloc;
+   intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
cros-ec@200 {
compatible = "google,cros-ec";
reg = <0x204 1 0x200 1 0x880 0x80>;
diff --git 

[U-Boot] [PATCH v2 09/55] dm: x86: Add a northbridge uclass

[Simon Glass]

Add a uclass for the northbridge / SDRAM controller found on some older
Intel chipsets.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2:
- Drop unnecessary DECLARE_GLOBAL_DATA_PTR

 arch/x86/lib/Makefile |  1 +
 arch/x86/lib/northbridge-uclass.c | 15 +++
 include/dm/uclass-id.h|  1 +
 3 files changed, 17 insertions(+)
 create mode 100644 arch/x86/lib/northbridge-uclass.c

diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 43792bc..d9fc296 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -19,6 +19,7 @@ obj-y += lpc-uclass.o
 obj-y  += mpspec.o
 obj-$(CONFIG_ENABLE_MRC_CACHE) += mrccache.o
 obj-y += cmd_mtrr.o
+obj-y  += northbridge-uclass.o
 obj-$(CONFIG_I8259_PIC) += i8259.o
 obj-$(CONFIG_I8254_TIMER) += i8254.o
 ifndef CONFIG_DM_PCI
diff --git a/arch/x86/lib/northbridge-uclass.c 
b/arch/x86/lib/northbridge-uclass.c
new file mode 100644
index 000..64b6257
--- /dev/null
+++ b/arch/x86/lib/northbridge-uclass.c
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+UCLASS_DRIVER(northbridge) = {
+   .id = UCLASS_NORTHBRIDGE,
+   .name   = "northbridge",
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index ef145af..4a6827b 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -46,6 +46,7 @@ enum uclass_id {
UCLASS_MMC, /* SD / MMC card or chip */
UCLASS_MOD_EXP, /* RSA Mod Exp device */
UCLASS_MTD, /* Memory Technology Device (MTD) device */
+   UCLASS_NORTHBRIDGE, /* Intel Northbridge / SDRAM controller */
UCLASS_PCH, /* x86 platform controller hub */
UCLASS_PCI, /* PCI bus */
UCLASS_PCI_GENERIC, /* Generic PCI bus device */
-- 
2.6.0.rc2.230.g3dd15c0

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[U-Boot] [PATCH v2 11/55] x86: ivybridge: Move northbridge init into the probe() method

[Simon Glass]

Now that we have a proper driver for the nortbridge, set it up in by probing
it, and move the early init code into the probe() method.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2: None

 arch/x86/cpu/ivybridge/cpu.c|  2 ++
 arch/x86/cpu/ivybridge/early_init.c | 33 +++--
 2 files changed, 21 insertions(+), 14 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 2a15fc0..f32b4a1 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -243,6 +243,8 @@ int print_cpuinfo(void)
}
 
/* Early chipset init required before RAM init can work */
+   uclass_first_device(UCLASS_NORTHBRIDGE, );
+
ret = uclass_first_device(UCLASS_PCH, );
if (ret)
return ret;
diff --git a/arch/x86/cpu/ivybridge/early_init.c 
b/arch/x86/cpu/ivybridge/early_init.c
index 945ae2d..c629f5b 100644
--- a/arch/x86/cpu/ivybridge/early_init.c
+++ b/arch/x86/cpu/ivybridge/early_init.c
@@ -123,20 +123,6 @@ void sandybridge_early_init(int chipset_type)
pci_dev_t pch_dev = PCH_DEV;
pci_dev_t video_dev = PCH_VIDEO_DEV;
pci_dev_t lpc_dev = PCH_LPC_DEV;
-   u32 capid0_a;
-   u8 reg8;
-
-   /* Device ID Override Enable should be done very early */
-   capid0_a = x86_pci_read_config32(pch_dev, 0xe4);
-   if (capid0_a & (1 << 10)) {
-   reg8 = x86_pci_read_config8(pch_dev, 0xf3);
-   reg8 &= ~7; /* Clear 2:0 */
-
-   if (chipset_type == SANDYBRIDGE_MOBILE)
-   reg8 |= 1; /* Set bit 0 */
-
-   x86_pci_write_config8(pch_dev, 0xf3, reg8);
-   }
 
/* Setup all BARs required for early PCIe and raminit */
sandybridge_setup_bars(pch_dev, lpc_dev);
@@ -149,6 +135,25 @@ void sandybridge_early_init(int chipset_type)
 
 static int bd82x6x_northbridge_probe(struct udevice *dev)
 {
+   const int chipset_type = SANDYBRIDGE_MOBILE;
+   u32 capid0_a;
+   u8 reg8;
+
+   if (gd->flags & GD_FLG_RELOC)
+   return 0;
+
+   /* Device ID Override Enable should be done very early */
+   dm_pci_read_config32(dev, 0xe4, _a);
+   if (capid0_a & (1 << 10)) {
+   dm_pci_read_config8(dev, 0xf3, );
+   reg8 &= ~7; /* Clear 2:0 */
+
+   if (chipset_type == SANDYBRIDGE_MOBILE)
+   reg8 |= 1; /* Set bit 0 */
+
+   dm_pci_write_config8(dev, 0xf3, reg8);
+   }
+
return 0;
 }
 
-- 
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[U-Boot] [PATCH v2 05/55] x86: ivybridge: Set up the LPC device using driver model

[Simon Glass]

Find the LPC device in arch_cpu_init_dm() as a first step to converting
this code to use driver model. Probing the LPC will probe its parent (the
PCH) automatically, so make sure that probing the PCH does nothing before
relocation.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 arch/x86/cpu/ivybridge/bd82x6x.c | 3 +++
 arch/x86/cpu/ivybridge/cpu.c | 6 +-
 arch/x86/cpu/ivybridge/lpc.c | 6 ++
 arch/x86/dts/chromebook_link.dts | 1 +
 4 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index c000aca..72f2ed4 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -65,6 +65,9 @@ static int bd82x6x_probe(struct udevice *dev)
int sata_node, gma_node;
int ret;
 
+   if (!(gd->flags & GD_FLG_RELOC))
+   return 0;
+
hose = pci_bus_to_hose(0);
lpc_enable(PCH_LPC_DEV);
lpc_init(hose, PCH_LPC_DEV);
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 343bfb4..6ffc843 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -126,7 +126,7 @@ int arch_cpu_init_dm(void)
 {
const void *blob = gd->fdt_blob;
struct pci_controller *hose;
-   struct udevice *bus;
+   struct udevice *bus, *dev;
int node;
int ret;
 
@@ -141,6 +141,10 @@ int arch_cpu_init_dm(void)
/* TODO(s...@chromium.org): Get rid of gd->hose */
gd->hose = hose;
 
+   ret = uclass_first_device(UCLASS_LPC, );
+   if (!dev)
+   return -ENODEV;
+
node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH);
if (node < 0)
return -ENOENT;
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index af5d4a8..51a4073 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -559,6 +559,11 @@ void lpc_enable(pci_dev_t dev)
setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
 }
 
+static int bd82x6x_lpc_probe(struct udevice *dev)
+{
+   return 0;
+}
+
 static const struct udevice_id bd82x6x_lpc_ids[] = {
{ .compatible = "intel,bd82x6x-lpc" },
{ }
@@ -568,4 +573,5 @@ U_BOOT_DRIVER(bd82x6x_lpc_drv) = {
.name   = "lpc",
.id = UCLASS_LPC,
.of_match   = bd82x6x_lpc_ids,
+   .probe  = bd82x6x_lpc_probe,
 };
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index a5c5dc1..d5c5bfd 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -223,6 +223,7 @@
compatible = "intel,bd82x6x-lpc";
#address-cells = <1>;
#size-cells = <0>;
+   u-boot,dm-pre-reloc;
cros-ec@200 {
compatible = "google,cros-ec";
reg = <0x204 1 0x200 1 0x880 0x80>;
-- 
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[U-Boot] [PATCH v2 40/55] x86: ivybridge: Use the I2C driver to perform SMbus init

[Simon Glass]

Move the init code into the I2C driver.

Signed-off-by: Simon Glass 
Reviewed-by: Heiko Schocher 
Reviewed-by: Bin Meng 
---

Changes in v2: None

 arch/x86/cpu/ivybridge/cpu.c  | 39 +++
 arch/x86/dts/chromebook_link.dts  |  6 ++
 configs/chromebook_link_defconfig |  2 ++
 drivers/i2c/intel_i2c.c   | 24 
 4 files changed, 35 insertions(+), 36 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 4cf2ba0..b9dda4c7 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -120,41 +120,6 @@ int arch_cpu_init_dm(void)
return 0;
 }
 
-static int enable_smbus(void)
-{
-   pci_dev_t dev;
-   uint16_t value;
-
-   /* Set the SMBus device statically. */
-   dev = PCI_BDF(0x0, 0x1f, 0x3);
-
-   /* Check to make sure we've got the right device. */
-   value = x86_pci_read_config16(dev, 0x0);
-   if (value != 0x8086) {
-   printf("SMBus controller not found\n");
-   return -ENOSYS;
-   }
-
-   /* Set SMBus I/O base. */
-   x86_pci_write_config32(dev, SMB_BASE,
-  SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
-
-   /* Set SMBus enable. */
-   x86_pci_write_config8(dev, HOSTC, HST_EN);
-
-   /* Set SMBus I/O space enable. */
-   x86_pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
-
-   /* Disable interrupt generation. */
-   outb(0, SMBUS_IO_BASE + SMBHSTCTL);
-
-   /* Clear any lingering errors, so transactions can run. */
-   outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-   debug("SMBus controller enabled\n");
-
-   return 0;
-}
-
 #define PCH_EHCI0_TEMP_BAR0 0xe800
 #define PCH_EHCI1_TEMP_BAR0 0xe8000400
 #define PCH_XHCI_TEMP_BAR0  0xe8001000
@@ -271,9 +236,11 @@ int print_cpuinfo(void)
post_code(POST_EARLY_INIT);
 
/* Enable SPD ROMs and DDR-III DRAM */
-   ret = enable_smbus();
+   ret = uclass_first_device(UCLASS_I2C, );
if (ret)
return ret;
+   if (!dev)
+   return -ENODEV;
 
/* Prepare USB controller early in S3 resume */
if (boot_mode == PEI_BOOT_RESUME)
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index 18305a3..54f2043 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -283,6 +283,12 @@
intel,sata-port-map = <1>;
intel,sata-port0-gen3-tx = <0x00880a7f>;
};
+
+   smbus: smbus@1f,3 {
+   compatible = "intel,ich-i2c";
+   reg = <0xfb00 0 0 0 0>;
+   u-boot,dm-pre-reloc;
+   };
};
 
tpm {
diff --git a/configs/chromebook_link_defconfig 
b/configs/chromebook_link_defconfig
index f367f81..daa958e 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@@ -1,5 +1,6 @@
 CONFIG_X86=y
 CONFIG_SYS_MALLOC_F_LEN=0x1800
+CONFIG_DM_I2C=y
 CONFIG_VENDOR_GOOGLE=y
 CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
 CONFIG_TARGET_CHROMEBOOK_LINK=y
@@ -20,6 +21,7 @@ CONFIG_CMD_TPM=y
 CONFIG_CMD_TPM_TEST=y
 CONFIG_OF_CONTROL=y
 CONFIG_CPU=y
+CONFIG_SYS_I2C_INTEL=y
 CONFIG_CMD_CROS_EC=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_LPC=y
diff --git a/drivers/i2c/intel_i2c.c b/drivers/i2c/intel_i2c.c
index 1082d1a..3d777ff 100644
--- a/drivers/i2c/intel_i2c.c
+++ b/drivers/i2c/intel_i2c.c
@@ -9,6 +9,7 @@
 #include 
 #include 
 #include 
+#include 
 
 int intel_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
 {
@@ -27,6 +28,29 @@ int intel_i2c_set_bus_speed(struct udevice *bus, unsigned 
int speed)
 
 static int intel_i2c_probe(struct udevice *dev)
 {
+   /*
+* So far this is just setup code for ivybridge SMbus. When we have
+* a full I2C driver this may need to be moved, generalised or made
+* dependant on a particular compatible string.
+*
+* Set SMBus I/O base
+*/
+   dm_pci_write_config32(dev, SMB_BASE,
+ SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
+
+   /* Set SMBus enable. */
+   dm_pci_write_config8(dev, HOSTC, HST_EN);
+
+   /* Set SMBus I/O space enable. */
+   dm_pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
+
+   /* Disable interrupt generation. */
+   outb(0, SMBUS_IO_BASE + SMBHSTCTL);
+
+   /* Clear any lingering errors, so transactions can run. */
+   outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+   debug("SMBus controller enabled\n");
+
return 0;
 }
 
-- 
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[U-Boot] [PATCH v2 47/55] x86: ivybridge: Convert pch.c to use DM PCI API

[Simon Glass]

Convert this file to use the driver model PCI API.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2: None

 arch/x86/cpu/ivybridge/lpc.c  | 10 
 arch/x86/cpu/ivybridge/pch.c  | 35 ++
 arch/x86/cpu/ivybridge/sata.c | 21 +++-
 arch/x86/include/asm/arch-ivybridge/pch.h | 42 +++
 4 files changed, 76 insertions(+), 32 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 0cf55c5..12e86cb 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -354,10 +354,10 @@ static void enable_clock_gating(struct udevice *pch)
reg16 |= (1 << 2) | (1 << 11);
dm_pci_write_config16(pch, GEN_PMCON_1, reg16);
 
-   pch_iobp_update(0xEB007F07, ~0UL, (1 << 31));
-   pch_iobp_update(0xEB004000, ~0UL, (1 << 7));
-   pch_iobp_update(0xEC007F07, ~0UL, (1 << 31));
-   pch_iobp_update(0xEC004000, ~0UL, (1 << 7));
+   pch_iobp_update(pch, 0xEB007F07, ~0UL, (1 << 31));
+   pch_iobp_update(pch, 0xEB004000, ~0UL, (1 << 7));
+   pch_iobp_update(pch, 0xEC007F07, ~0UL, (1 << 31));
+   pch_iobp_update(pch, 0xEC004000, ~0UL, (1 << 7));
 
reg32 = readl(RCB_REG(CG));
reg32 |= (1 << 31);
@@ -573,7 +573,7 @@ static int lpc_init_extra(struct udevice *dev)
pch_power_options(pch);
 
/* Initialize power management */
-   switch (pch_silicon_type()) {
+   switch (pch_silicon_type(pch)) {
case PCH_TYPE_CPT: /* CougarPoint */
cpt_pm_init(pch);
break;
diff --git a/arch/x86/cpu/ivybridge/pch.c b/arch/x86/cpu/ivybridge/pch.c
index bbab646..c7ce408 100644
--- a/arch/x86/cpu/ivybridge/pch.c
+++ b/arch/x86/cpu/ivybridge/pch.c
@@ -14,32 +14,34 @@
 static int pch_revision_id = -1;
 static int pch_type = -1;
 
-int pch_silicon_revision(void)
+int pch_silicon_revision(struct udevice *dev)
 {
-   pci_dev_t dev;
+   u8 val;
 
-   dev = PCH_LPC_DEV;
+   if (pch_revision_id < 0) {
+   dm_pci_read_config8(dev, PCI_REVISION_ID, );
+   pch_revision_id = val;
+   }
 
-   if (pch_revision_id < 0)
-   pch_revision_id = x86_pci_read_config8(dev, PCI_REVISION_ID);
return pch_revision_id;
 }
 
-int pch_silicon_type(void)
+int pch_silicon_type(struct udevice *dev)
 {
-   pci_dev_t dev;
+   u8 val;
 
-   dev = PCH_LPC_DEV;
+   if (pch_type < 0) {
+   dm_pci_read_config8(dev, PCI_DEVICE_ID + 1, );
+   pch_type = val;
+   }
 
-   if (pch_type < 0)
-   pch_type = x86_pci_read_config8(dev, PCI_DEVICE_ID + 1);
return pch_type;
 }
 
-int pch_silicon_supported(int type, int rev)
+int pch_silicon_supported(struct udevice *dev, int type, int rev)
 {
-   int cur_type = pch_silicon_type();
-   int cur_rev = pch_silicon_revision();
+   int cur_type = pch_silicon_type(dev);
+   int cur_rev = pch_silicon_revision(dev);
 
switch (type) {
case PCH_TYPE_CPT:
@@ -78,7 +80,8 @@ static inline int iobp_poll(void)
return 0;
 }
 
-void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
+void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue,
+u32 orvalue)
 {
u32 data;
 
@@ -86,7 +89,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
writel(address, RCB_REG(IOBPIRI));
 
/* READ OPCODE */
-   if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
+   if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0))
writel(IOBPS_RW_BX, RCB_REG(IOBPS));
else
writel(IOBPS_READ_AX, RCB_REG(IOBPS));
@@ -109,7 +112,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
data |= orvalue;
 
/* WRITE OPCODE */
-   if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
+   if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0))
writel(IOBPS_RW_BX, RCB_REG(IOBPS));
else
writel(IOBPS_WRITE_AX, RCB_REG(IOBPS));
diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c
index 21e11d1..a59d9ed 100644
--- a/arch/x86/cpu/ivybridge/sata.c
+++ b/arch/x86/cpu/ivybridge/sata.c
@@ -51,7 +51,7 @@ static void common_sata_init(struct udevice *dev, unsigned 
int port_map)
dm_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183);
 }
 
-static void bd82x6x_sata_init(struct udevice *dev)
+static void bd82x6x_sata_init(struct udevice *dev, struct udevice *pch)
 {
unsigned int port_map, speed_support, port_tx;
const void *blob = gd->fdt_blob;
@@ -170,11 +170,11 @@ static void bd82x6x_sata_init(struct udevice *dev)
/* Set Gen3 Transmitter settings if needed */
port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0);
if (port_tx)
-   

[U-Boot] [PATCH v2 19/55] x86: ivybridge: Move CPU init code into the driver

[Simon Glass]

Use the CPU driver's probe() method to perform the CPU init. This will happen
automatically when the first CPU is probed.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2: None

 arch/x86/cpu/ivybridge/bd82x6x.c  |  6 --
 arch/x86/cpu/ivybridge/model_206ax.c  |  5 -
 arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 15 ---
 3 files changed, 4 insertions(+), 22 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index c71596d..149c1d2 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -61,7 +61,6 @@ static int bd82x6x_probe(struct udevice *dev)
 {
const void *blob = gd->fdt_blob;
struct pci_controller *hose;
-   struct x86_cpu_priv *cpu;
int sata_node, gma_node;
int ret;
 
@@ -81,11 +80,6 @@ static int bd82x6x_probe(struct udevice *dev)
bd82x6x_usb_ehci_init(PCH_EHCI1_DEV);
bd82x6x_usb_ehci_init(PCH_EHCI2_DEV);
 
-   cpu = calloc(1, sizeof(*cpu));
-   if (!cpu)
-   return -ENOMEM;
-   model_206ax_init(cpu);
-
gma_node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_GMA);
if (gma_node < 0) {
debug("%s: Cannot find GMA node\n", __func__);
diff --git a/arch/x86/cpu/ivybridge/model_206ax.c 
b/arch/x86/cpu/ivybridge/model_206ax.c
index 9fa1226..6ab6ede 100644
--- a/arch/x86/cpu/ivybridge/model_206ax.c
+++ b/arch/x86/cpu/ivybridge/model_206ax.c
@@ -403,7 +403,7 @@ static void configure_mca(void)
 static unsigned ehci_debug_addr;
 #endif
 
-int model_206ax_init(struct x86_cpu_priv *cpu)
+static int model_206ax_init(void)
 {
int ret;
 
@@ -480,6 +480,9 @@ static int model_206ax_get_count(struct udevice *dev)
 
 static int cpu_x86_model_206ax_probe(struct udevice *dev)
 {
+   if (dev->seq == 0)
+   model_206ax_init();
+
return 0;
 }
 
diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h 
b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
index d76cb8d..fc7fc6d 100644
--- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
+++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
@@ -15,19 +15,4 @@ void bd82x6x_usb_xhci_init(pci_dev_t dev);
 int gma_func0_init(struct udevice *dev, const void *blob, int node);
 int bd82x6x_init_extra(void);
 
-/**
- * struct x86_cpu_priv - Information about a single CPU
- *
- * @apic_id: Advanced Programmable Interrupt Controller Identifier, which is
- * just a number representing the CPU core
- *
- * TODO: Move this to driver model once lifecycle is understood
- */
-struct x86_cpu_priv {
-   int apic_id;
-   int start_err;
-};
-
-int model_206ax_init(struct x86_cpu_priv *cpu);
-
 #endif
-- 
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[U-Boot] [PATCH v2 30/55] x86: ivybridge: Do the SATA init before relocation

[Simon Glass]

The SATA device needs to set itself up so that it appears correctly on the
PCI bus. The easiest way to do this is to set it up to probe before
relocation. This can do the early setup.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Update to use the disk uclass

 arch/x86/cpu/ivybridge/bd82x6x.c  |  2 --
 arch/x86/cpu/ivybridge/cpu.c  |  3 +++
 arch/x86/cpu/ivybridge/sata.c | 25 -
 arch/x86/dts/chromebook_link.dts  | 16 +---
 arch/x86/include/asm/arch-ivybridge/bd82x6x.h |  1 -
 5 files changed, 36 insertions(+), 11 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index c5a5d4d..8e98fa2 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -69,8 +69,6 @@ int bd82x6x_init_extra(void)
return -EINVAL;
}
 
-   bd82x6x_sata_enable(PCH_SATA_DEV, blob, sata_node);
-
return 0;
 }
 
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 6d3f477..4cf2ba0 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -251,6 +251,9 @@ int print_cpuinfo(void)
if (!dev)
return -ENODEV;
 
+   /* Cause the SATA device to do its early init */
+   uclass_first_device(UCLASS_DISK, );
+
/* Check PM1_STS[15] to see if we are waking from Sx */
pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
 
diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c
index e7bf03c..c46ec3a 100644
--- a/arch/x86/cpu/ivybridge/sata.c
+++ b/arch/x86/cpu/ivybridge/sata.c
@@ -6,12 +6,15 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
 #include 
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static inline u32 sir_read(pci_dev_t dev, int idx)
 {
x86_pci_write_config32(dev, SATA_SIRI, idx);
@@ -206,7 +209,7 @@ void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int 
node)
pch_iobp_update(0xea00408a, 0xfcff, 0x0100);
 }
 
-void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node)
+static void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node)
 {
unsigned port_map;
const char *mode;
@@ -224,3 +227,23 @@ void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, 
int node)
map |= (port_map ^ 0x3f) << 8;
x86_pci_write_config16(dev, 0x90, map);
 }
+
+static int bd82x6x_sata_probe(struct udevice *dev)
+{
+   if (!(gd->flags & GD_FLG_RELOC))
+   bd82x6x_sata_enable(PCH_SATA_DEV, gd->fdt_blob, dev->of_offset);
+
+   return 0;
+}
+
+static const struct udevice_id bd82x6x_ahci_ids[] = {
+   { .compatible = "intel,pantherpoint-ahci" },
+   { }
+};
+
+U_BOOT_DRIVER(ahci_ivybridge_drv) = {
+   .name   = "ahci_ivybridge",
+   .id = UCLASS_DISK,
+   .of_match   = bd82x6x_ahci_ids,
+   .probe  = bd82x6x_sata_probe,
+};
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index 3ed6662..022b04c 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -207,13 +207,6 @@
u-boot,dm-pre-reloc;
};
 
-   sata {
-   compatible = "intel,pantherpoint-ahci";
-   intel,sata-mode = "ahci";
-   intel,sata-port-map = <1>;
-   intel,sata-port0-gen3-tx = <0x00880a7f>;
-   };
-
gma {
compatible = "intel,gma";
intel,dp_hotplug = <0 0 0x06>;
@@ -281,6 +274,15 @@
};
};
};
+
+   sata@1f,2 {
+   compatible = "intel,pantherpoint-ahci";
+   reg = <0xfa00 0 0 0 0>;
+   u-boot,dm-pre-reloc;
+   intel,sata-mode = "ahci";
+   intel,sata-port-map = <1>;
+   intel,sata-port0-gen3-tx = <0x00880a7f>;
+   };
};
 
tpm {
diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h 
b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
index 0f4fe47..faae5ff 100644
--- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
+++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
@@ -8,7 +8,6 @@
 #define _ASM_ARCH_BD82X6X_H
 
 void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node);
-void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node);
 void bd82x6x_usb_ehci_init(pci_dev_t dev);
 void bd82x6x_usb_xhci_init(pci_dev_t dev);
 int gma_func0_init(struct udevice *dev, const void *blob, int node);
-- 
2.6.0.rc2.230.g3dd15c0

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[U-Boot] [PATCH v2 21/55] x86: ivybridge: Drop the dead MTRR code

[Simon Glass]

This is not used and MTRRs are set up elsewhere now. Drop it.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2: None

 arch/x86/cpu/ivybridge/model_206ax.c | 10 --
 1 file changed, 10 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/model_206ax.c 
b/arch/x86/cpu/ivybridge/model_206ax.c
index a217954..9654600 100644
--- a/arch/x86/cpu/ivybridge/model_206ax.c
+++ b/arch/x86/cpu/ivybridge/model_206ax.c
@@ -412,16 +412,6 @@ static int model_206ax_init(struct udevice *dev)
set_ehci_debug(0);
 #endif
 
-   /* Setup MTRRs based on physical address size */
-#if 0 /* TODO: Implement this */
-   struct cpuid_result cpuid_regs;
-
-   cpuid_regs = cpuid(0x8008);
-   x86_setup_fixed_mtrrs();
-   x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2);
-   x86_mtrr_check();
-#endif
-
 #if CONFIG_USBDEBUG
set_ehci_debug(ehci_debug_addr);
 #endif
-- 
2.6.0.rc2.230.g3dd15c0

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Re: [U-Boot] [PATCH v2 02/55] dm: usb: Add a compatible string for PCI EHCI controller

[Marek Vasut]

On Monday, January 18, 2016 at 12:11:07 AM, Simon Glass wrote:
> Add a compatible string to allow this to be specified in the device tree
> if needed.
> 
> Signed-off-by: Simon Glass 

Acked-by: Marek Vasut 

Best regards,
Marek Vasut
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Re: [U-Boot] x86: Bay Trail support with W83627DHG

[Bin Meng]

Hi Stefan,

On Mon, Jan 18, 2016 at 1:44 AM, Stefan Roese  wrote:
> Hi Bin,
>
> On 17.01.2016 03:35, Stefan Roese wrote:
>>
>> On 16.01.2016 15:08, Bin Meng wrote:
>>>
>>> On Fri, Jan 15, 2016 at 10:37 PM, Stefan Roese  wrote:

 Hi Simon, Hi Bin!

 I'm currently busy with porting U-Boot to a Bay Trail board.
 Equipped with an Intel Atom E3845 and additionally the
 Nuvoton / Winbond W83627DHG Super IO chip.

 My staring point for this port is the Minnowboard MAX, which
 works very well btw. I've used the same binaries as described
 in the README.x86 as on the MinnowMAX for this new Bay Trail
 board. But am not able yet to see any output on the DEBUG_UART.

 Bin, you already mentioned in a previous mail, that I need to
 enable the legacy UART in the Super IO chip for this. I've
 started adding a small driver for this, similar to the one
 you've introduced for the SMSC:
>>>
>>>
>>> Ah, looks I delivered inaccurate information before! I just remember
>>> BayTrail SoC integrates a legacy UART at I/O 0x3f8 and it is enabled
>>> by FSP by default. If you use a debug version of FSP (only gold4
>>> release provides a debug version FSP), you will se lots of useful
>>> debug information printed on the serial port (the one connected to the
>>> SoC legacy UART). But, why does your board have an additional Nuvoton
>>> / Winbond W83627DHG Super IO chip? I guess it's for other legacy
>>> peripherals like 8042 KBC, etc? We need figure out the serial port you
>>> are trying to enable is connected to which chip. If it is connected
>>> directly to BayTrail SoC, then you don't need program this W83627DHG.
>>
>>
>> It is connected to the Winbond UART. So we need to enable and use it.
>> But how can I disable the BayTrail internal legacy UART? So that the
>> Winbond one is really used?
>
>
> Okay. I was able to work around this problem with the included
> legacy UART in the Bay Trail Atom. By moving the IO base address
> of the Winbond COM1 from 0x3f8 to a different (unused) location.
> And then using this new address as the UART base address. U-Boot
> boots to the prompt with the "fixed" memory-down DDR parameters
> to the FSP in this configuration.

This is great!

>
> Still I would really like to disable the internal legacy UART
> and only use the Winbond UART(s) at the default address. Disabling
> the Bay Trail legacy UART by clearing the "UART_CONT.COM1EN" bit,
> as described in the "Intel AtomTM Processor E3800 Product Family
> Datasheet", does not seem to fix this problem. I need to double
> check this tomorrow though.
>
> Bin, Simon, do you have any ideas on how to disable this Atom
> legacy UART instead. It must be possible, as when booting into
> Linux with the original BIOS, the Winbond COM1 works just fine
> at 0x3f8.
>

I checked FSP VPD of BayTrial, looks Intel does not expose a config
option to enable/disable the legacy UART integrated into the SoC,
neither an option to move its I/O address, instead it enables the
legacy UART always and has a fixed address 0x3f8. Per my understanding
of the datasheet, I think you are right, "UART_CONT.COM1EN" bit should
be the key to enable/disable the legacy UART. But I suspect FSP turns
it on again during every call to the FSP API (like fsp_init(),
fsp_notify()).

You may try: after each call to fsp_init() and fsp_notify(), try
adding the codes to turn off the "UART_CONT.COM1EN" bit and see what's
going on there.

Regards,
Bin
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Re: [U-Boot] [PATCH] ARM: Disable "DISCARD" for secure section if CONFIG_ARMV7_SECURE_BASE isn't defined

[Dongsheng Wang]

Hi Tom,

Thanks for your review.

I will update this patch.

Regards,
-Dongsheng

> On Mon, Jan 11, 2016 at 02:51:39AM +, Dongsheng Wang wrote:
> > Hi Tom,
> >
> > Sorry for my late reply, and thanks for your reply.
> >
> > How about the following comments, following your suggestion I remove
> some redundant comments?
> >
> > If my understanding is wrong, please correct me, thanks:
> > #if defined(CONFIG_ARMV7_SECURE_BASE) &&
> defined(CONFIG_ARMV7_NONSEC)
> > /*
> >  * If CONFIG_ARMV7_SECURE_BASE is true, secure code will not
> >  * bundle with u-boot, and codes offset are fixed. Secure zone
> 
> code offsets
> 
> >  * only needs to be copied from loading address to
> 
> from the loading address
> 
> >  * CONFIG_ARMV7_SECURE_BASE, which is the linking and running
> >  * address for secure code.
> >  *
> >  * If undefine CONFIG_ARMV7_SECURE_BASE secure zone will be
> 
> If CONFIG_ARMV7_SECURE_BASE is undefined, the secure zone will be
> 
> >  * included in u-boot space, and some absolute address were
> > used
> 
> u-boot address space
> 
> >  * in secure code. Accompanied by u-boot relocation secure code
> >  * also need to relocate the absolute address.
> 
> in secure code.  The absolute addresses of the secure code also needs to be
> relocated along with the accompanying u-boot code.
> 
> >  *
> >  * So DISCARD is only for CONFIG_ARMV7_SECURE_BASE.
> >  */
> > /DISCARD/ : { *(.rel._secure*) } #endif
> 
> Otherwise looks good, thanks!
> 
> --
> Tom
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[U-Boot] [PATCH v2] Enable snooping on transactions from CAAM block

[Aneesh Bansal]

To enable snooping on CAAM transactions following programmign is done

1. Enable core snooping (CCI interface, Core is Slave5 on CCI)
This setting is also required for making the system coherent

2. CAAM IP lies behind SMMU3 in teh system. Configure SMMU3 to do teh following:
a) Program SCR to bypass transactions with stream ID other than taht of CAAM
b_ Program S2CR to change memroy attributes of transactions with CAAM's stream
ID (0x10) to cacheable.

Signed-off-by: Ruchika Gupta 
Signed-off-by: Nitesh Narayan Lal 
Signed-off-by: Aneesh Bansal 
---
Changes in v2:
Avoid mixing the use of u32 and uint32_t.
Using uint32_t at all places.

 arch/arm/include/asm/arch-ls102xa/config.h |  1 +
 .../include/asm/arch-ls102xa/ls102xa_stream_id.h   | 34 
 board/freescale/common/ls102xa_stream_id.c | 36 +-
 board/freescale/ls1021aqds/ls1021aqds.c|  4 +++
 board/freescale/ls1021atwr/ls1021atwr.c|  4 +++
 5 files changed, 78 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 
b/arch/arm/include/asm/arch-ls102xa/config.h
index f066480..f14ea2f 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -38,6 +38,7 @@
 #define CONFIG_SYS_LS102XA_XHCI_USB1_ADDR  (CONFIG_SYS_IMMR + 0x0210)
 #define CONFIG_SYS_LS102XA_USB1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
+#define CONFIG_SYS_SMMU3_ADDR  (CONFIG_SYS_IMMR + 0x30)
 
 #define CONFIG_SYS_FSL_SEC_OFFSET  0x0070
 #define CONFIG_SYS_LS102XA_USB1_OFFSET 0x0760
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h 
b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
index fa571b3..68e4e02 100644
--- a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
@@ -6,6 +6,39 @@
 
 #ifndef __FSL_LS102XA_STREAM_ID_H_
 #define __FSL_LS102XA_STREAM_ID_H_
+#define CONFIG_SMMU_NSCR_OFFSET0x400
+#define CONFIG_SMMU_SMR_OFFSET 0x800
+#define CONFIG_SMMU_S2CR_OFFSET0xc00
+
+#define SMMU_NSCR_CLIENTPD_SHIFT   0
+#define SMMU_NSCR_MTCFG_SHIFT  20
+
+#define SMR_SMR_VALID_SHIFT31
+#define SMR_ID_MASK0x7fff
+#define SMR_MASK_SHIFT 16
+
+#define S2CR_WACFG_SHIFT   22
+#define S2CR_WACFG_MASK0x3
+#define S2CR_WACFG_WRITE_ALLOCATE  0x2
+
+#define S2CR_RACFG_SHIFT   20
+#define S2CR_RACFG_MASK0x3
+#define S2CR_RACFG_READ_ALLOCATE   0x2
+
+#define S2CR_TYPE_SHIFT16
+#define S2CR_TYPE_MASK 0x3
+#define S2CR_TYPE_BYPASS   0x01
+
+#define S2CR_MEM_ATTR_SHIFT12
+#define S2CR_MEM_ATTR_MASK 0xf
+#define S2CR_MEM_ATTR_CACHEABLE0xa
+
+#define S2CR_MTCFG 0x0800
+
+#define S2CR_SHCFG_SHIFT   8
+#define S2CR_SHCFG_MASK0x3
+#define S2CR_SHCFG_OUTER_CACHEABLE 0x1
+#define S2CR_SHCFG_INNER_CACHEABLE 0x2
 
 #include 
 
@@ -71,4 +104,5 @@ struct smmu_stream_id {
 
 void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size);
 void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num);
+void ls1021x_config_smmu3(uint32_t liodn);
 #endif
diff --git a/board/freescale/common/ls102xa_stream_id.c 
b/board/freescale/common/ls102xa_stream_id.c
index f434269..9ae29b8 100644
--- a/board/freescale/common/ls102xa_stream_id.c
+++ b/board/freescale/common/ls102xa_stream_id.c
@@ -20,7 +20,7 @@ void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, 
uint32_t num)
 void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size)
 {
int i;
-   u32 liodn;
+   uint32_t liodn;
 
for (i = 0; i < size; i++) {
if (tbl[i].num_ids == 2)
@@ -31,3 +31,37 @@ void ls1021x_config_caam_stream_id(struct liodn_id_table 
*tbl, int size)
out_le32((uint32_t *)(tbl[i].reg_offset), liodn);
}
 }
+
+void ls1021x_config_smmu3(uint32_t liodn)
+{
+   uint32_t *addr;
+   uint32_t smr, s2cr, nscr;
+
+   addr = (uint32_t *)(CONFIG_SYS_SMMU3_ADDR + CONFIG_SMMU_NSCR_OFFSET);
+   /* SMMU NSCR configuration */
+   nscr = in_le32(addr);
+
+   nscr = nscr  & ~(1 << SMMU_NSCR_CLIENTPD_SHIFT |
+1 << SMMU_NSCR_MTCFG_SHIFT);
+   out_le32(addr, nscr);
+
+   /* SMMU SMR configuration */
+   addr = (uint32_t *)(CONFIG_SYS_SMMU3_ADDR + CONFIG_SMMU_SMR_OFFSET);
+
+   smr = 0;
+   smr = smr & (~(SMR_ID_MASK << SMR_MASK_SHIFT));
+   smr = smr | (1 << SMR_SMR_VALID_SHIFT) | liodn;
+
+   out_le32(addr, smr);
+
+   /* SMMU S2CR configuration */
+   addr = (uint32_t 

Re: [U-Boot] [PATCH v7 0/7] add support for atheros ath79 based SOCs

[Daniel Schwierzeck]

2016-01-17 6:49 GMT+01:00 Wills Wang :
>
>
> On 01/17/2016 03:05 AM, Marek Vasut wrote:
>>
>> On Saturday, January 16, 2016 at 07:13:46 PM, Wills Wang wrote:
>>>
>>> These series of patch add support for atheros ath79 based SOCs in u-boot,
>>> at the present moment it's just available for ar933x and qca953x chip.
>>>
>>> This patch serises is based on mips_io_v4 branch on u-boot-mips
>>> repository
>>> [1] and tested on ar933x and qca953x board.
>>>
>>> [1]
>>>
>>> http://git.denx.de/?p=u-boot/u-boot-mips.git;a=shortlog;h=refs/heads/mips_
>>> io_v4
>>
>> So if I didn't complain about this being sent as separate emails this
>> morning.
>> Please, do send your patches as a series, not as separate emails.
>
> How to send a patch series by patman?
>

If your git-sendmail config is correctly set up, patman automatically
sends the cover letter and then all patches as response to that cover
letter.

You have to enable mail threading in git-sendmail. Check that with:

$ git config --get sendemail.thread

To enable it globally:

$ git config --global sendemail.thread true

-- 
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[U-Boot] [PATCH v2 0/7] Determine Boot mode at run time

[Aneesh Bansal]

There are two phases in Secure Boot
1. ISBC: In BootROM, validate the BootLoader (U-Boot).
2. ESBC: In U-Boot, continuing the Chain of Trust by
 validating and booting LINUX.

For ESBC phase, there is no difference in SoC's based on ARM or PowerPC
cores.

But the exit conditions after ISBC phase i.e. entry conditions for
U-Boot are different for ARM and PowerPC.
PowerPC:

If Secure Boot is executed, a separate U-Boot target is required which
must be compiled with a diffrent Text Base as compared to Non-Secure Boot.
There are some LAW and TLB settings which are required specifically for
Secure Boot scenario.

ARM:

ARM based SoC's have a fixed memory map and exit conditions from BootROM
are same irrespective of boot mode (Secure or Non-Secure).

This patchset is aimed at removing the requirement for a separate Secure Boot
target for ARM based SoC's. 

Another Security Requirement for running CHAIN_OF_TRUST is that U-Boot 
environemnt
must not be picked from flash/external memory. This cannot be done based on 
bootmode
at run time in current U-Boot architecture. Once this dependency is resolved, 
no separate
SECURE_BOOT target will be required for ARM based SoC's.

Currently, the only code under CONFIG_SECURE_BOOT for ARM SoC's is defining
CONFIG_ENV_IS_NOWHERE

The patches have been tested on LS1043, LS1021, P3041 and T1024.

The patch set is dependent on following:
http://patchwork.ozlabs.org/patch/553826/

Aneesh Bansal (7):
  include/configs: make secure boot header file include uniform
  include/configs: move definition of CONFIG_CMD_BLOB
  SECURE_BOOT: split the secure boot functionality in two parts
  create function to determine boot mode
  enable chain of trust for ARM platforms
  enable chain of trust for PowerPC platforms
  SECURE_BOOT: change error handler for esbc_validate

 arch/arm/cpu/armv8/fsl-layerscape/soc.c|   4 +
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |   3 +
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h  |   2 +
 arch/arm/include/asm/fsl_secure_boot.h |  20 +++-
 arch/powerpc/cpu/mpc85xx/cpu_init.c|  12 +++
 arch/powerpc/include/asm/fsl_secure_boot.h |  47 ++---
 arch/powerpc/include/asm/immap_85xx.h  |   3 +
 board/freescale/common/Makefile|   1 +
 board/freescale/common/cmd_esbc_validate.c |   7 +-
 board/freescale/common/fsl_chain_of_trust.c|  70 +
 board/freescale/common/fsl_validate.c  |   7 ++
 board/freescale/ls1021aqds/ls1021aqds.c|   4 +
 board/freescale/ls1021atwr/ls1021atwr.c|   4 +
 include/config_fsl_chain_trust.h   | 101 ++
 include/config_fsl_secboot.h   | 116 -
 include/configs/B4860QDS.h |   4 -
 include/configs/BSC9132QDS.h   |   4 -
 include/configs/P1010RDB.h |   4 -
 include/configs/P2041RDB.h |   4 -
 include/configs/T102xQDS.h |  10 +-
 include/configs/T102xRDB.h |  10 +-
 include/configs/T1040QDS.h |   3 -
 include/configs/T104xRDB.h |   3 -
 include/configs/T208xQDS.h |   4 -
 include/configs/T208xRDB.h |   4 -
 include/configs/T4240QDS.h |   4 -
 include/configs/T4240RDB.h |   9 --
 include/configs/corenet_ds.h   |   4 -
 include/configs/ls1021aqds.h   |   5 +-
 include/configs/ls1021atwr.h   |   5 +-
 include/configs/ls1043a_common.h   |   8 ++
 include/configs/ls1043aqds.h   |   2 +
 include/configs/ls1043ardb.h   |   8 --
 include/fsl_validate.h |   2 +
 34 files changed, 295 insertions(+), 203 deletions(-)
 create mode 100644 board/freescale/common/fsl_chain_of_trust.c
 create mode 100644 include/config_fsl_chain_trust.h
 delete mode 100644 include/config_fsl_secboot.h

-- 
1.8.1.4

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[U-Boot] [PATCH v2 1/7] include/configs: make secure boot header file include uniform

[Aneesh Bansal]

The file fsl_secure_boot.h must be included in config file
for Secure Boot. This is not required to be protected by any
macro.
CONFIG_FSL_CAAM must be defined and CONFIG_CMD_HASH should be
turned on.
The above was missing in some config files and all files have been
made uniform in this respect.

Signed-off-by: Aneesh Bansal 
---
Changes in v2:
None (Changed the Sign-Off with New E-Mail ID)

 arch/arm/include/asm/fsl_secure_boot.h |  5 +
 include/configs/C29XPCIE.h |  4 
 include/configs/T102xQDS.h | 12 +++-
 include/configs/T102xRDB.h | 12 +++-
 include/configs/T1040QDS.h |  3 ++-
 include/configs/T104xRDB.h |  3 ++-
 include/configs/T208xQDS.h |  3 ++-
 include/configs/T208xRDB.h |  3 ++-
 include/configs/ls1021aqds.h   |  5 -
 include/configs/ls1021atwr.h   |  5 -
 include/configs/ls1043a_common.h   |  8 
 include/configs/ls1043aqds.h   |  2 ++
 include/configs/ls1043ardb.h   |  8 
 13 files changed, 57 insertions(+), 16 deletions(-)

diff --git a/arch/arm/include/asm/fsl_secure_boot.h 
b/arch/arm/include/asm/fsl_secure_boot.h
index 806302b..b29e71c 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -34,6 +34,11 @@
 #define CONFIG_FSL_ISBC_KEY_EXT
 #endif
 
+#ifdef CONFIG_LS1043A
+/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */
+#define CONFIG_ESBC_ADDR_64BIT
+#endif
+
 #ifndef CONFIG_FIT_SIGNATURE
 
 #define CONFIG_EXTRA_ENV \
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 16920c6..890dcbb 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -567,4 +567,8 @@
 
 #include 
 
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
index 951cbc4..fb41a7d 100644
--- a/include/configs/T102xQDS.h
+++ b/include/configs/T102xQDS.h
@@ -39,6 +39,8 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #endif
 
+#define CONFIG_FSL_CAAM/* Enable SEC/CAAM */
+
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg
@@ -936,8 +938,16 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
 
-#ifdef CONFIG_SECURE_BOOT
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
 #include 
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
 #endif
 
 #endif /* __T1024QDS_H */
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 4a0f5b2..113df37 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -33,6 +33,8 @@
 #define CONFIG_FSL_LAW /* Use common FSL init code */
 #define CONFIG_ENV_OVERWRITE
 
+#define CONFIG_FSL_CAAM/* Enable SEC/CAAM */
+
 /* support deep sleep */
 #ifdef CONFIG_PPC_T1024
 #define CONFIG_DEEP_SLEEP
@@ -948,8 +950,16 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
 
-#ifdef CONFIG_SECURE_BOOT
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
 #include 
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
 #endif
 
 #endif /* __T1024RDB_H */
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 9e151da..5fd93a1 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -835,8 +835,9 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
 
-#ifdef CONFIG_SECURE_BOOT
 #include 
+
+#ifdef CONFIG_SECURE_BOOT
 #define CONFIG_CMD_BLOB
 #endif
 
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index da65f56..eec2971 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -938,8 +938,9 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
 
 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
 
-#ifdef CONFIG_SECURE_BOOT
 #include 
+
+#ifdef CONFIG_SECURE_BOOT
 #define CONFIG_CMD_BLOB
 #endif
 
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index a0cecc6..019878a 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -933,8 +933,9 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
 
-#ifdef CONFIG_SECURE_BOOT
 #include 
+
+#ifdef CONFIG_SECURE_BOOT
 #define CONFIG_CMD_BLOB
 #undef CONFIG_CMD_USB
 #endif
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 312b0eb..3665b7d 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -889,8 +889,9 @@ unsigned long get_board_ddr_clk(void);
 
 

[U-Boot] [PATCH v2 4/7] create function to determine boot mode

[Aneesh Bansal]

A function is created to detrmine if the boot mode is secure
or non-secure for differnt SoC's.

Signed-off-by: Aneesh Bansal 
---
Changes in v2:
Corrected the macro for SB_EN bit in RCW.

 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  3 ++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h  |  2 +
 arch/powerpc/include/asm/immap_85xx.h  |  3 ++
 board/freescale/common/fsl_chain_of_trust.c| 53 ++
 4 files changed, 61 insertions(+)
 create mode 100644 board/freescale/common/fsl_chain_of_trust.c

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 21b803f..297ff35 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -218,6 +218,9 @@ struct ccsr_gur {
 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK   0x3f
 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK   0x
 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT  16
+#define RCW_SB_EN_REG_INDEX7
+#define RCW_SB_EN_MASK 0x0020
+
u8  res_140[0x200-0x140];
u32 scratchrw[4];  /* Scratch Read/Write */
u8  res_210[0x300-0x210];
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 89339fe..0a80772 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -120,6 +120,8 @@ struct ccsr_gur {
u32 brrl;   /* Boot release */
u8  res_0e8[0x100-0xe8];
u32 rcwsr[16];  /* Reset control word status */
+#define RCW_SB_EN_REG_INDEX7
+#define RCW_SB_EN_MASK 0x0020
u8  res_140[0x200-0x140];
u32 scratchrw[4];  /* Scratch Read/Write */
u8  res_210[0x300-0x210];
diff --git a/arch/powerpc/include/asm/immap_85xx.h 
b/arch/powerpc/include/asm/immap_85xx.h
index bc7e5f8..53ca6d9 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1749,6 +1749,8 @@ typedef struct ccsr_gur {
u32 brrl;   /* Boot release */
u8  res17[24];
u32 rcwsr[16];  /* Reset control word status */
+#define RCW_SB_EN_REG_INDEX7
+#define RCW_SB_EN_MASK 0x0020
 
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT   16
@@ -2193,6 +2195,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORDEVSR2_DDR_SPD_00x0008
 #define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT  3
 #endif
+#define MPC85xx_PORDEVSR2_SBC_MASK 0x1000
 /* The 8544 RM says this is bit 26, but it's really bit 24 */
 #define MPC85xx_PORDEVSR2_SEC_CFG  0x0080
u8  res1[8];
diff --git a/board/freescale/common/fsl_chain_of_trust.c 
b/board/freescale/common/fsl_chain_of_trust.c
new file mode 100644
index 000..ff67bd7
--- /dev/null
+++ b/board/freescale/common/fsl_chain_of_trust.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+#ifdef CONFIG_LS102XA
+#include 
+#endif
+
+#if defined(CONFIG_MPC85xx)
+#define CONFIG_DCFG_ADDR   CONFIG_SYS_MPC85xx_GUTS_ADDR
+#else
+#define CONFIG_DCFG_ADDR   CONFIG_SYS_FSL_GUTS_ADDR
+#endif
+
+#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
+#define gur_in32(a)   in_le32(a)
+#else
+#define gur_in32(a)   in_be32(a)
+#endif
+
+/* Check the Boot Mode. If Secure, return 1 else return 0 */
+int fsl_check_boot_mode_secure(void)
+{
+   uint32_t val;
+   struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+   struct ccsr_gur __iomem *gur = (void *)(CONFIG_DCFG_ADDR);
+
+   val = sfp_in32(_regs->ospr) & ITS_MASK;
+   if (val == ITS_MASK)
+   return 1;
+
+#if defined(CONFIG_FSL_CORENET) || !defined(CONFIG_MPC85xx)
+   /* For PBL based platforms check the SB_EN bit in RCWSR */
+   val = gur_in32(>rcwsr[RCW_SB_EN_REG_INDEX - 1]) & RCW_SB_EN_MASK;
+   if (val == RCW_SB_EN_MASK)
+   return 1;
+#endif
+
+#if defined(CONFIG_MPC85xx) && !defined(CONFIG_FSL_CORENET)
+   /* For Non-PBL Platforms, check the Device Status register 2*/
+   val = gur_in32(>pordevsr2) & MPC85xx_PORDEVSR2_SBC_MASK;
+   if (val != MPC85xx_PORDEVSR2_SBC_MASK)
+   return 1;
+
+#endif
+   return 0;
+}
-- 
1.8.1.4

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[U-Boot] [PATCH v2 3/7] SECURE_BOOT: split the secure boot functionality in two parts

[Aneesh Bansal]

There are two phases in Secure Boot
1. ISBC: In BootROM, validate the BootLoader (U-Boot).
2. ESBC: In U-Boot, continuing the Chain of Trust by
 validating and booting LINUX.

For ESBC phase, there is no difference in SoC's based on ARM or PowerPC
cores.

But the exit conditions after ISBC phase i.e. entry conditions for
U-Boot are different for ARM and PowerPC.
PowerPC:

If Secure Boot is executed, a separate U-Boot target is required which
must be compiled with a diffrent Text Base as compared to Non-Secure Boot.
There are some LAW and TLB settings which are required specifically for
Secure Boot scenario.

ARM:

ARM based SoC's have a fixed memory map and exit conditions from BootROM
are same irrespective of boot mode (Secure or Non-Secure).

Thus the current Secure Boot functionlity has been split into two parts:

CONFIG_CHAIN_OF_TRUST

This will have the following functionality as part of U-Boot:
1. Enable commands like esbc_validate, esbc_halt
2. Change the environment settings based on bootmode (determined at run time):
 - If bootmode is non-secure, no change
 - If bootmode is secure, set the following:
 - bootdelay = 0 (Don't give boot prompt)
 - bootcmd = Validate and execute the bootscript.

CONFIG_SECURE_BOOT
=
This is defined only for creating a different compile time target for secure 
boot.

Traditionally, both these functionalities were defined under CONFIG_SECURE_BOOT
This patch is aimed at removing the requirement for a separate Secure Boot 
target
for ARM based SoC's. CONFIG_CHAIN_OF_TRUST will be defined and boot mode will be
determine at run time.

Another Security Requirement for running CHAIN_OF_TRUST is that U-Boot 
environemnt
must not be picked from flash/external memory. This cannot be done based on 
bootmode
at run time in current U-Boot architecture. Once this dependency is resolved, 
no separate
SECURE_BOOT target will be required for ARM based SoC's.

Currently, the only code under CONFIG_SECURE_BOOT for ARM SoC's is defining
CONFIG_ENV_IS_NOWHERE

Signed-off-by: Aneesh Bansal 
---
Changes in v2:
CONFIG_ENV_IS_NOWHERE is defined for Secure Boot

 arch/arm/include/asm/fsl_secure_boot.h |  16 ++--
 arch/powerpc/include/asm/fsl_secure_boot.h |  41 +-
 include/config_fsl_chain_trust.h   | 101 +
 include/config_fsl_secboot.h   | 116 -
 4 files changed, 135 insertions(+), 139 deletions(-)
 create mode 100644 include/config_fsl_chain_trust.h
 delete mode 100644 include/config_fsl_secboot.h

diff --git a/arch/arm/include/asm/fsl_secure_boot.h 
b/arch/arm/include/asm/fsl_secure_boot.h
index 8491a72..0da0599 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -8,6 +8,14 @@
 #define __FSL_SECURE_BOOT_H
 
 #ifdef CONFIG_SECURE_BOOT
+
+#ifndef CONFIG_FIT_SIGNATURE
+#define CONFIG_CHAIN_OF_TRUST
+#endif
+
+#endif
+
+#ifdef CONFIG_CHAIN_OF_TRUST
 #define CONFIG_CMD_ESBC_VALIDATE
 #define CONFIG_CMD_BLOB
 #define CONFIG_FSL_SEC_MON
@@ -40,8 +48,6 @@
 #define CONFIG_ESBC_ADDR_64BIT
 #endif
 
-#ifndef CONFIG_FIT_SIGNATURE
-
 #define CONFIG_EXTRA_ENV \
"setenv fdt_high 0xcfff;"   \
"setenv initrd_high 0xcfff;"\
@@ -50,8 +56,6 @@
 /* The address needs to be modified according to NOR memory map */
 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0x600a
 
-#include 
-#endif
-#endif
-
+#include 
+#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
 #endif
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h 
b/arch/powerpc/include/asm/fsl_secure_boot.h
index 7d217a6..41058d1 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -9,19 +9,11 @@
 #include 
 
 #ifdef CONFIG_SECURE_BOOT
-#define CONFIG_CMD_ESBC_VALIDATE
-#define CONFIG_CMD_BLOB
-#define CONFIG_FSL_SEC_MON
-#define CONFIG_SHA_PROG_HW_ACCEL
-#define CONFIG_DM
-#define CONFIG_RSA
-#define CONFIG_RSA_FREESCALE_EXP
-#ifndef CONFIG_FSL_CAAM
-#define CONFIG_FSL_CAAM
-#endif
+
+#ifndef CONFIG_FIT_SIGNATURE
+#define CONFIG_CHAIN_OF_TRUST
 #endif
 
-#ifdef CONFIG_SECURE_BOOT
 #if defined(CONFIG_FSL_CORENET)
 #define CONFIG_SYS_PBI_FLASH_BASE  0xc000
 #elif defined(CONFIG_BSC9132QDS)
@@ -76,8 +68,25 @@
  */
 #define CONFIG_FSL_ISBC_KEY_EXT
 #endif
+#endif /* #ifdef CONFIG_SECURE_BOOT */
+
+#ifdef CONFIG_CHAIN_OF_TRUST
+
+#define CONFIG_CMD_ESBC_VALIDATE
+#define CONFIG_CMD_BLOB
+#define CONFIG_FSL_SEC_MON
+#define CONFIG_SHA_PROG_HW_ACCEL
+#define CONFIG_RSA
+#define CONFIG_RSA_FREESCALE_EXP
+
+#ifndef CONFIG_DM
+#define CONFIG_DM
+#endif
+
+#ifndef CONFIG_FSL_CAAM
+#define CONFIG_FSL_CAAM
+#endif
 
-#ifndef CONFIG_FIT_SIGNATURE
 /* If Boot Script is not on NOR and is required to be copied on RAM */
 #ifdef CONFIG_BOOTSCRIPT_COPY_RAM
 #define CONFIG_BS_HDR_ADDR_RAM 0x0001
@@ -105,10 +114,8 @@
 #define 

[U-Boot] [PATCH v2 7/7] SECURE_BOOT: change error handler for esbc_validate

[Aneesh Bansal]

In case of error while executing esbc_validate command, SNVS
transition and issue of reset is required only for secure-boot.
If boot mode is non-secure, this is not required.

Similarly, esbc_halt command which puts the core in Spin Loop
is applicable only for Secure Boot.

Signed-off-by: Aneesh Bansal 
---
Changes in v2:
None (Changed the Sign-Off with New E-Mail ID)

 board/freescale/common/cmd_esbc_validate.c | 7 ++-
 board/freescale/common/fsl_validate.c  | 7 +++
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/board/freescale/common/cmd_esbc_validate.c 
b/board/freescale/common/cmd_esbc_validate.c
index ca7c737..dfa3e21 100644
--- a/board/freescale/common/cmd_esbc_validate.c
+++ b/board/freescale/common/cmd_esbc_validate.c
@@ -11,6 +11,11 @@
 static int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
 {
+   if (fsl_check_boot_mode_secure() == 0) {
+   printf("Boot Mode is Non-Secure. Not entering spin loop.\n");
+   return 0;
+   }
+
printf("Core is entering spin loop.\n");
 loop:
goto loop;
@@ -64,6 +69,6 @@ U_BOOT_CMD(
 
 U_BOOT_CMD(
esbc_halt,  1,  0,  do_esbc_halt,
-   "Put the core in spin loop ",
+   "Put the core in spin loop (Secure Boot Only)",
""
 );
diff --git a/board/freescale/common/fsl_validate.c 
b/board/freescale/common/fsl_validate.c
index de40081..8fd6dd6 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -370,6 +370,13 @@ void fsl_secboot_handle_error(int error)
printf("ERROR :: %x :: %s\n", error, e->name);
}
 
+   /* If Boot Mode is secure, transition the SNVS state and issue
+* reset based on type of failure and ITS setting.
+* If Boot mode is non-secure, return from this function.
+*/
+   if (fsl_check_boot_mode_secure() == 0)
+   return;
+
switch (error) {
case ERROR_ESBC_CLIENT_HEADER_BARKER:
case ERROR_ESBC_CLIENT_HEADER_IMG_SIZE:
-- 
1.8.1.4

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[U-Boot] [PATCH v2 5/7] enable chain of trust for ARM platforms

[Aneesh Bansal]

Chain of Trust is enabled for ARM platforms (LS1021 and LS1043).
In board_late_init(), fsl_setenv_chain_of_trust() is called which
will perform the following:
- If boot mode is non-secure, return (No Change)
- If boot mode is secure, set the following environmet variables:
   bootdelay = 0 (To disable Boot Prompt)
   bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)

Signed-off-by: Aneesh Bansal 
---
Changes in v2:
Defconfigs for Secure Boot Target are not removed

 arch/arm/cpu/armv8/fsl-layerscape/soc.c |  4 
 board/freescale/common/Makefile |  1 +
 board/freescale/common/fsl_chain_of_trust.c | 17 +
 board/freescale/ls1021aqds/ls1021aqds.c |  4 
 board/freescale/ls1021atwr/ls1021atwr.c |  4 
 include/fsl_validate.h  |  2 ++
 6 files changed, 32 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 23d6b73..2f92b55 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -241,6 +242,9 @@ int board_late_init(void)
 #ifdef CONFIG_SCSI_AHCI_PLAT
sata_init();
 #endif
+#ifdef CONFIG_CHAIN_OF_TRUST
+   fsl_setenv_chain_of_trust();
+#endif
 
return 0;
 }
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 51d2814..be114ce 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -76,5 +76,6 @@ obj-$(CONFIG_LAYERSCAPE_NS_ACCESS)+= ns_access.o
 ifdef CONFIG_SECURE_BOOT
 obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o
 endif
+obj-$(CONFIG_CHAIN_OF_TRUST) += fsl_chain_of_trust.o
 
 endif
diff --git a/board/freescale/common/fsl_chain_of_trust.c 
b/board/freescale/common/fsl_chain_of_trust.c
index ff67bd7..ecfcc82 100644
--- a/board/freescale/common/fsl_chain_of_trust.c
+++ b/board/freescale/common/fsl_chain_of_trust.c
@@ -51,3 +51,20 @@ int fsl_check_boot_mode_secure(void)
 #endif
return 0;
 }
+
+int fsl_setenv_chain_of_trust(void)
+{
+   /* Check Boot Mode
+* If Boot Mode is Non-Secure, no changes are required
+*/
+   if (fsl_check_boot_mode_secure() == 0)
+   return 0;
+
+   /* If Boot mode is Secure, set the environment variables
+* bootdelay = 0 (To disable Boot Prompt)
+* bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
+*/
+   setenv("bootdelay", "0");
+   setenv("bootcmd", CONFIG_CHAIN_BOOT_CMD);
+   return 0;
+}
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c 
b/board/freescale/ls1021aqds/ls1021aqds.c
index ca1ea61..6e82232 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -22,6 +22,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "../common/sleep.h"
 #include "../common/qixis.h"
@@ -369,6 +370,9 @@ int board_late_init(void)
 #ifdef CONFIG_SCSI_AHCI_PLAT
ls1021a_sata_init();
 #endif
+#ifdef CONFIG_CHAIN_OF_TRUST
+   fsl_setenv_chain_of_trust();
+#endif
 
return 0;
 }
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c 
b/board/freescale/ls1021atwr/ls1021atwr.c
index ae62bca..054cc3d 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -30,6 +30,7 @@
 #ifdef CONFIG_U_QE
 #include "../../../drivers/qe/qe.h"
 #endif
+#include 
 
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -553,6 +554,9 @@ int board_late_init(void)
 #ifdef CONFIG_SCSI_AHCI_PLAT
ls1021a_sata_init();
 #endif
+#ifdef CONFIG_CHAIN_OF_TRUST
+   fsl_setenv_chain_of_trust();
+#endif
 
return 0;
 }
diff --git a/include/fsl_validate.h b/include/fsl_validate.h
index ad14867..83efcf4 100644
--- a/include/fsl_validate.h
+++ b/include/fsl_validate.h
@@ -205,4 +205,6 @@ int fsl_secboot_blob_encap(cmd_tbl_t *cmdtp, int flag, int 
argc,
 int fsl_secboot_blob_decap(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[]);
 
+int fsl_check_boot_mode_secure(void);
+int fsl_setenv_chain_of_trust(void);
 #endif
-- 
1.8.1.4

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[U-Boot] [PATCH v2 6/7] enable chain of trust for PowerPC platforms

[Aneesh Bansal]

Chain of Trust is enabled for PowerPC platforms for Secure Boot.
CONFIG_BOARD_LATE_INIT is defined.
In board_late_init(), fsl_setenv_chain_of_trust() is called which
will perform the following:
- If boot mode is non-secure, return (No Change)
- If boot mode is secure, set the following environmet variables:
   bootdelay = 0 (To disable Boot Prompt)
   bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)

Signed-off-by: Aneesh Bansal 
---
Changes in v2:
None (Changed the Sign-Off with New E-Mail ID)

 arch/powerpc/cpu/mpc85xx/cpu_init.c| 12 
 arch/powerpc/include/asm/fsl_secure_boot.h |  7 +++
 2 files changed, 19 insertions(+)

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c 
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 50bb86a..a797980 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -26,6 +26,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "mp.h"
 #ifdef CONFIG_FSL_CAAM
 #include 
@@ -1011,3 +1012,14 @@ void cpu_secondary_init_r(void)
qe_reset();
 #endif
 }
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_CHAIN_OF_TRUST
+   fsl_setenv_chain_of_trust();
+#endif
+
+   return 0;
+}
+#endif
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h 
b/arch/powerpc/include/asm/fsl_secure_boot.h
index 41058d1..c45cace 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -87,6 +87,13 @@
 #define CONFIG_FSL_CAAM
 #endif
 
+/* fsl_setenv_chain_of_trust() must be called from
+ * board_late_init()
+ */
+#ifndef CONFIG_BOARD_LATE_INIT
+#define CONFIG_BOARD_LATE_INIT
+#endif
+
 /* If Boot Script is not on NOR and is required to be copied on RAM */
 #ifdef CONFIG_BOOTSCRIPT_COPY_RAM
 #define CONFIG_BS_HDR_ADDR_RAM 0x0001
-- 
1.8.1.4

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[U-Boot] [PATCH v2 2/7] include/configs: move definition of CONFIG_CMD_BLOB

[Aneesh Bansal]

CONFIG_CMD_BLOB must be defined in case of Secure Boot.
It was earlier defined in all config files. The definition
has been moved to a common file which is included by all configs.

Signed-off-by: Aneesh Bansal 
---
Changes in v2:
None (Changed the Sign-Off with New E-Mail ID)

 arch/arm/include/asm/fsl_secure_boot.h | 1 +
 arch/powerpc/include/asm/fsl_secure_boot.h | 1 +
 include/configs/B4860QDS.h | 4 
 include/configs/BSC9132QDS.h   | 4 
 include/configs/C29XPCIE.h | 4 
 include/configs/P1010RDB.h | 4 
 include/configs/P2041RDB.h | 4 
 include/configs/T102xQDS.h | 4 
 include/configs/T102xRDB.h | 4 
 include/configs/T1040QDS.h | 4 
 include/configs/T104xRDB.h | 4 
 include/configs/T208xQDS.h | 5 -
 include/configs/T208xRDB.h | 5 -
 include/configs/T4240QDS.h | 4 
 include/configs/T4240RDB.h | 9 -
 include/configs/corenet_ds.h   | 4 
 include/configs/ls1021aqds.h   | 4 
 include/configs/ls1021atwr.h   | 4 
 18 files changed, 2 insertions(+), 71 deletions(-)

diff --git a/arch/arm/include/asm/fsl_secure_boot.h 
b/arch/arm/include/asm/fsl_secure_boot.h
index b29e71c..8491a72 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -9,6 +9,7 @@
 
 #ifdef CONFIG_SECURE_BOOT
 #define CONFIG_CMD_ESBC_VALIDATE
+#define CONFIG_CMD_BLOB
 #define CONFIG_FSL_SEC_MON
 #define CONFIG_SHA_PROG_HW_ACCEL
 #define CONFIG_RSA
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h 
b/arch/powerpc/include/asm/fsl_secure_boot.h
index 87415b1..7d217a6 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -10,6 +10,7 @@
 
 #ifdef CONFIG_SECURE_BOOT
 #define CONFIG_CMD_ESBC_VALIDATE
+#define CONFIG_CMD_BLOB
 #define CONFIG_FSL_SEC_MON
 #define CONFIG_SHA_PROG_HW_ACCEL
 #define CONFIG_DM
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 9fb5cee..bcbae50 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -924,8 +924,4 @@ unsigned long get_board_ddr_clk(void);
 
 #include 
 
-#ifdef CONFIG_SECURE_BOOT
-#define CONFIG_CMD_BLOB
-#endif
-
 #endif /* __CONFIG_H */
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index d0e5a25..89907dc 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -722,8 +722,4 @@ combinations. this should be removed later
 
 #include 
 
-#ifdef CONFIG_SECURE_BOOT
-#define CONFIG_CMD_BLOB
-#endif
-
 #endif /* __CONFIG_H */
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 890dcbb..16920c6 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -567,8 +567,4 @@
 
 #include 
 
-#ifdef CONFIG_SECURE_BOOT
-#define CONFIG_CMD_BLOB
-#endif
-
 #endif /* __CONFIG_H */
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index f9776c0..3c0faca 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -952,8 +952,4 @@ extern unsigned long get_sdram_size(void);
 
 #include 
 
-#ifdef CONFIG_SECURE_BOOT
-#define CONFIG_CMD_BLOB
-#endif
-
 #endif /* __CONFIG_H */
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index b2e51b5..f250e7f 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -756,8 +756,4 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 
 #include 
 
-#ifdef CONFIG_SECURE_BOOT
-#define CONFIG_CMD_BLOB
-#endif
-
 #endif /* __CONFIG_H */
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
index fb41a7d..e5df784 100644
--- a/include/configs/T102xQDS.h
+++ b/include/configs/T102xQDS.h
@@ -946,8 +946,4 @@ unsigned long get_board_ddr_clk(void);
 
 #include 
 
-#ifdef CONFIG_SECURE_BOOT
-#define CONFIG_CMD_BLOB
-#endif
-
 #endif /* __T1024QDS_H */
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 113df37..3cda3b1 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -958,8 +958,4 @@ unsigned long get_board_ddr_clk(void);
 
 #include 
 
-#ifdef CONFIG_SECURE_BOOT
-#define CONFIG_CMD_BLOB
-#endif
-
 #endif /* __T1024RDB_H */
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 5fd93a1..2e7892f 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -837,8 +837,4 @@ unsigned long get_board_ddr_clk(void);
 
 #include 
 
-#ifdef CONFIG_SECURE_BOOT
-#define CONFIG_CMD_BLOB
-#endif
-
 #endif /* __CONFIG_H */
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index eec2971..5fc3497 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -940,8 +940,4 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
 
 #include 
 
-#ifdef 

[U-Boot] [PATCH v3] powerpc/SECURE_BOOT: Add PAMU driver

[Aneesh Bansal]

PAMU driver basic support for usage in Secure Boot.
In secure boot PAMU is not in bypass mode. Hence to use
any peripheral (SEC Job ring in our case), PAMU has to be
configured.

The patch reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3.

The Header file pamu.h and few functions in driver have been derived
from Freescale Libos.

Signed-off-by: Ruchika Gupta 
Signed-off-by: Aneesh Bansal 
---
Changes in v3:
Replace the Debug printf() call with debug()
Merged the two commits into a single commit

Changes in v2:
Replace the Debug printf() call with debug()

 arch/powerpc/cpu/mpc85xx/cpu_init.c   |  18 +-
 arch/powerpc/cpu/mpc8xxx/Makefile |   1 +
 arch/powerpc/cpu/mpc8xxx/fsl_pamu.c   | 433 ++
 arch/powerpc/cpu/mpc8xxx/pamu_table.c |  55 +
 arch/powerpc/include/asm/fsl_pamu.h   | 169 +
 arch/powerpc/include/asm/immap_85xx.h |  19 +-
 drivers/crypto/fsl/jr.c   |  23 ++
 7 files changed, 709 insertions(+), 9 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
 create mode 100644 arch/powerpc/cpu/mpc8xxx/pamu_table.c
 create mode 100644 arch/powerpc/include/asm/fsl_pamu.h

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c 
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 13a7d0f..50bb86a 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -30,6 +30,10 @@
 #ifdef CONFIG_FSL_CAAM
 #include 
 #endif
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
+#include 
+#include 
+#endif
 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #include 
 #include 
@@ -425,8 +429,7 @@ void fsl_erratum_a007212_workaround(void)
 ulong cpu_init_f(void)
 {
extern void m8560_cpm_reset (void);
-#if defined(CONFIG_SYS_DCSRBAR_PHYS) || \
-   (defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET))
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
 #if defined(CONFIG_SECURE_BOOT)
@@ -458,12 +461,6 @@ ulong cpu_init_f(void)
 #if defined(CONFIG_SYS_CPC_REINIT_F)
disable_cpc_sram();
 #endif
-
-#if defined(CONFIG_FSL_CORENET)
-   /* Put PAMU in bypass mode */
-   out_be32(>pamubypenr, FSL_CORENET_PAMU_BYPASS);
-#endif
-
 #endif
 
 #ifdef CONFIG_CPM2
@@ -940,6 +937,11 @@ int cpu_init_r(void)
fman_enet_init();
 #endif
 
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
+   if (pamu_init() < 0)
+   fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
+#endif
+
 #ifdef CONFIG_FSL_CAAM
sec_init();
 #endif
diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile 
b/arch/powerpc/cpu/mpc8xxx/Makefile
index ac45e0e..c5592cd 100644
--- a/arch/powerpc/cpu/mpc8xxx/Makefile
+++ b/arch/powerpc/cpu/mpc8xxx/Makefile
@@ -24,5 +24,6 @@ obj-$(CONFIG_OF_LIBFDT) += fdt.o
 obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
 obj-$(CONFIG_SYS_SRIO) += srio.o
 obj-$(CONFIG_FSL_LAW) += law.o
+obj-$(CONFIG_FSL_CORENET) += fsl_pamu.o pamu_table.o
 
 endif
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c 
b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
new file mode 100644
index 000..8ad3b7c
--- /dev/null
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
@@ -0,0 +1,433 @@
+/*
+ * FSL PAMU driver
+ *
+ * Copyright 2012-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+struct paace *ppaact;
+struct paace *sec;
+unsigned long fspi;
+
+static inline int __ilog2_roundup_64(uint64_t val)
+{
+   if ((val & (val - 1)) == 0)
+   return __ilog2_u64(val);
+   else
+   return  __ilog2_u64(val) + 1;
+}
+
+
+static inline int count_lsb_zeroes(unsigned long val)
+{
+   return ffs(val) - 1;
+}
+
+static unsigned int map_addrspace_size_to_wse(uint64_t addrspace_size)
+{
+   /* window size is 2^(WSE+1) bytes */
+   return count_lsb_zeroes(addrspace_size >> PAMU_PAGE_SHIFT) +
+   PAMU_PAGE_SHIFT - 1;
+}
+
+static unsigned int map_subwindow_cnt_to_wce(uint32_t subwindow_cnt)
+{
+   /* window count is 2^(WCE+1) bytes */
+   return count_lsb_zeroes(subwindow_cnt) - 1;
+}
+
+static void pamu_setup_default_xfer_to_host_ppaace(struct paace *ppaace)
+{
+   set_bf(ppaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_PRIMARY);
+   set_bf(ppaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
+  PAACE_M_COHERENCE_REQ);
+}
+
+static void pamu_setup_default_xfer_to_host_spaace(struct paace *spaace)
+{
+   set_bf(spaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_SECONDARY);
+   set_bf(spaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
+  PAACE_M_COHERENCE_REQ);
+}
+
+/** Sets up PPAACE entry for specified liodn
+ *
+ * @param[in] liodn  Logical IO device number
+ * @param[in] win_addr   starting address of DSA window
+ * @param[in] win-size   size of DSA window
+ * @param[in] omiOperation mapping index -- if ~omi == 0 then omi
+

Re: [U-Boot] [PATCH v7 0/7] add support for atheros ath79 based SOCs

[Wills Wang]

On 01/17/2016 06:24 PM, Daniel Schwierzeck wrote:

2016-01-17 6:49 GMT+01:00 Wills Wang :


On 01/17/2016 03:05 AM, Marek Vasut wrote:

On Saturday, January 16, 2016 at 07:13:46 PM, Wills Wang wrote:

These series of patch add support for atheros ath79 based SOCs in u-boot,
at the present moment it's just available for ar933x and qca953x chip.

This patch serises is based on mips_io_v4 branch on u-boot-mips
repository
[1] and tested on ar933x and qca953x board.

[1]

http://git.denx.de/?p=u-boot/u-boot-mips.git;a=shortlog;h=refs/heads/mips_
io_v4

So if I didn't complain about this being sent as separate emails this
morning.
Please, do send your patches as a series, not as separate emails.

How to send a patch series by patman?


If your git-sendmail config is correctly set up, patman automatically
sends the cover letter and then all patches as response to that cover
letter.

You have to enable mail threading in git-sendmail. Check that with:

$ git config --get sendemail.thread

To enable it globally:

$ git config --global sendemail.thread true


Thanks, i will try it for the coming v8.

--
Best Regards
Wills

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[U-Boot] [PATCH 3/4] spi: omap3: Convert to DM

[Christophe Ricard]

Convert omap3_spi driver to DM and keep compatibility with previous
mode.

Signed-off-by: Christophe Ricard 
---

 drivers/spi/Kconfig |   6 +
 drivers/spi/omap3_spi.c | 439 ++--
 drivers/spi/omap3_spi.h |  14 +-
 3 files changed, 402 insertions(+), 57 deletions(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 2cdb110..b8c2498 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -155,6 +155,12 @@ config ZYNQ_QSPI
  Zynq QSPI IP core. This IP is used to connect the flash in
  4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel.
 
+config OMAP3_SPI
+   bool "McSPI driver for OMAP"
+   help
+ SPI master controller for OMAP24XX and later Multichannel SPI
+ (McSPI) modules.
+
 endif # if DM_SPI
 
 config FSL_ESPI
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index 95cdfa3..09fb1ef 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -11,10 +11,14 @@
  *
  * Modified by Ruslan Araslanov 
  *
+ * Copyright (c) 2016 Christophe Ricard 
+ * - Added support for DM_SPI
+ *
  * SPDX-License-Identifier:GPL-2.0+
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -22,9 +26,17 @@
 
 #define SPI_WAIT_TIMEOUT 10
 
+#ifdef CONFIG_DM_SPI
+static void spi_reset(struct udevice *dev)
+#else
 static void spi_reset(struct omap3_spi_slave *ds)
+#endif
 {
unsigned int tmp;
+#ifdef CONFIG_DM_SPI
+   struct omap3_spi_slave *ds = dev_get_priv(dev->parent);
+
+#endif
 
writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, >regs->sysconfig);
do {
@@ -39,20 +51,50 @@ static void spi_reset(struct omap3_spi_slave *ds)
writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, >regs->wakeupenable);
 }
 
+#ifdef CONFIG_DM_SPI
+static void omap3_spi_write_chconf(struct udevice *dev, int val)
+#else
 static void omap3_spi_write_chconf(struct omap3_spi_slave *ds, int val)
+#endif
 {
-   writel(val, >regs->channel[ds->slave.cs].chconf);
+   unsigned int cs;
+#ifdef CONFIG_DM_SPI
+   struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
+   struct omap3_spi_slave *ds = dev_get_priv(dev->parent);
+
+
+   cs = platdata->cs;
+#else
+   cs = ds->slave.cs;
+#endif
+
+   writel(val, >regs->channel[cs].chconf);
/* Flash post writes to make immediate effect */
-   readl(>regs->channel[ds->slave.cs].chconf);
+   readl(>regs->channel[cs].chconf);
 }
 
+#ifdef CONFIG_DM_SPI
+static void omap3_spi_set_enable(struct udevice *dev, int enable)
+#else
 static void omap3_spi_set_enable(struct omap3_spi_slave *ds, int enable)
+#endif
 {
-   writel(enable, >regs->channel[ds->slave.cs].chctrl);
+   unsigned int cs;
+#ifdef CONFIG_DM_SPI
+   struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
+   struct omap3_spi_slave *ds = dev_get_priv(dev->parent);
+
+   cs = platdata->cs;
+#else
+   cs = ds->slave.cs;
+#endif
+
+   writel(enable, >regs->channel[cs].chctrl);
/* Flash post writes to make immediate effect */
-   readl(>regs->channel[ds->slave.cs].chctrl);
+   readl(>regs->channel[cs].chctrl);
 }
 
+#ifndef CONFIG_DM_SPI
 void spi_init()
 {
/* do nothing */
@@ -138,10 +180,32 @@ void spi_free_slave(struct spi_slave *slave)
free(ds);
 }
 
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+   return 1;
+}
+#endif
+
+#ifdef CONFIG_DM_SPI
+static int omap3_spi_claim_bus(struct udevice *dev)
+#else
 int spi_claim_bus(struct spi_slave *slave)
+#endif
 {
-   struct omap3_spi_slave *ds = to_omap3_spi(slave);
+   unsigned int cs;
+   struct omap3_spi_slave *ds;
unsigned int conf, div = 0;
+#ifdef CONFIG_DM_SPI
+   struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
+   struct spi_slave *slave = dev_get_parent_priv(dev);
+
+   ds = dev_get_priv(dev->parent);
+   cs = platdata->cs;
+   ds->freq = slave->max_hz;
+#else
+   ds = to_omap3_spi(slave);
+   cs = ds->slave.cs;
+#endif
 
/* McSPI global module configuration */
 
@@ -149,7 +213,11 @@ int spi_claim_bus(struct spi_slave *slave)
 * setup when switching from (reset default) slave mode
 * to single-channel master mode
 */
+#ifdef CONFIG_DM_SPI
+   spi_reset(dev);
+#else
spi_reset(ds);
+#endif
conf = readl(>regs->modulctrl);
conf &= ~(OMAP3_MCSPI_MODULCTRL_STEST | OMAP3_MCSPI_MODULCTRL_MS);
conf |= OMAP3_MCSPI_MODULCTRL_SINGLE;
@@ -165,8 +233,7 @@ int spi_claim_bus(struct spi_slave *slave)
} else
div = 0xC;
 
-   conf = readl(>regs->channel[ds->slave.cs].chconf);
-
+   conf = readl(>regs->channel[cs].chconf);
/* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
 * REVISIT: this controller could support SPI_3WIRE mode.
 */
@@ 

[U-Boot] [PATCH 4/4] spi: omap3: Convert fully to DM_SPI

[Christophe Ricard]

For several reasons:
- code clarity
- DM trends in u-boot
...

It is better to make omap3_spi driver 100% DM_SPI based.

Signed-off-by: Christophe Ricard 
---

 drivers/spi/omap3_spi.c | 474 +++-
 drivers/spi/omap3_spi.h | 121 
 2 files changed, 102 insertions(+), 493 deletions(-)
 delete mode 100644 drivers/spi/omap3_spi.h

diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index 09fb1ef..8ea2cc5 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -22,22 +22,93 @@
 #include 
 #include 
 #include 
-#include "omap3_spi.h"
+
+#if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
+#define OMAP3_MCSPI1_BASE  0x48030100
+#define OMAP3_MCSPI2_BASE  0x481A0100
+#else
+#define OMAP3_MCSPI1_BASE  0x48098000
+#define OMAP3_MCSPI2_BASE  0x4809A000
+#define OMAP3_MCSPI3_BASE  0x480B8000
+#define OMAP3_MCSPI4_BASE  0x480BA000
+#endif
+
+#define OMAP3_MCSPI_MAX_FREQ   4800
+
+/* OMAP3 McSPI registers */
+struct mcspi_channel {
+   unsigned int chconf;/* 0x2C, 0x40, 0x54, 0x68 */
+   unsigned int chstat;/* 0x30, 0x44, 0x58, 0x6C */
+   unsigned int chctrl;/* 0x34, 0x48, 0x5C, 0x70 */
+   unsigned int tx;/* 0x38, 0x4C, 0x60, 0x74 */
+   unsigned int rx;/* 0x3C, 0x50, 0x64, 0x78 */
+};
+
+struct mcspi {
+   unsigned char res1[0x10];
+   unsigned int sysconfig; /* 0x10 */
+   unsigned int sysstatus; /* 0x14 */
+   unsigned int irqstatus; /* 0x18 */
+   unsigned int irqenable; /* 0x1C */
+   unsigned int wakeupenable;  /* 0x20 */
+   unsigned int syst;  /* 0x24 */
+   unsigned int modulctrl; /* 0x28 */
+   struct mcspi_channel channel[4]; /* channel0: 0x2C - 0x3C, bus 0 & 1 & 
2 & 3 */
+   /* channel1: 0x40 - 0x50, bus 0 & 1 */
+   /* channel2: 0x54 - 0x64, bus 0 & 1 */
+   /* channel3: 0x68 - 0x78, bus 0 */
+};
+
+/* per-register bitmasks */
+#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
+#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP (1 << 2)
+#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE (1 << 0)
+#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET (1 << 1)
+
+#define OMAP3_MCSPI_SYSSTATUS_RESETDONE (1 << 0)
+
+#define OMAP3_MCSPI_MODULCTRL_SINGLE   (1 << 0)
+#define OMAP3_MCSPI_MODULCTRL_MS   (1 << 2)
+#define OMAP3_MCSPI_MODULCTRL_STEST(1 << 3)
+
+#define OMAP3_MCSPI_CHCONF_PHA (1 << 0)
+#define OMAP3_MCSPI_CHCONF_POL (1 << 1)
+#define OMAP3_MCSPI_CHCONF_CLKD_MASK   (0x0f << 2)
+#define OMAP3_MCSPI_CHCONF_EPOL(1 << 6)
+#define OMAP3_MCSPI_CHCONF_WL_MASK (0x1f << 7)
+#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY (0x01 << 12)
+#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY (0x02 << 12)
+#define OMAP3_MCSPI_CHCONF_TRM_MASK(0x03 << 12)
+#define OMAP3_MCSPI_CHCONF_DMAW(1 << 14)
+#define OMAP3_MCSPI_CHCONF_DMAR(1 << 15)
+#define OMAP3_MCSPI_CHCONF_DPE0(1 << 16)
+#define OMAP3_MCSPI_CHCONF_DPE1(1 << 17)
+#define OMAP3_MCSPI_CHCONF_IS  (1 << 18)
+#define OMAP3_MCSPI_CHCONF_TURBO   (1 << 19)
+#define OMAP3_MCSPI_CHCONF_FORCE   (1 << 20)
+
+#define OMAP3_MCSPI_CHSTAT_RXS (1 << 0)
+#define OMAP3_MCSPI_CHSTAT_TXS (1 << 1)
+#define OMAP3_MCSPI_CHSTAT_EOT (1 << 2)
+
+#define OMAP3_MCSPI_CHCTRL_EN  (1 << 0)
+#define OMAP3_MCSPI_CHCTRL_DIS (0 << 0)
+
+#define OMAP3_MCSPI_WAKEUPENABLE_WKEN  (1 << 0)
+
+struct omap3_spi_slave {
+   struct mcspi *regs;
+   unsigned int freq;
+   unsigned int mode;
+};
 
 #define SPI_WAIT_TIMEOUT 10
 
-#ifdef CONFIG_DM_SPI
 static void spi_reset(struct udevice *dev)
-#else
-static void spi_reset(struct omap3_spi_slave *ds)
-#endif
 {
unsigned int tmp;
-#ifdef CONFIG_DM_SPI
struct omap3_spi_slave *ds = dev_get_priv(dev->parent);
 
-#endif
-
writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, >regs->sysconfig);
do {
tmp = readl(>regs->sysstatus);
@@ -51,161 +122,37 @@ static void spi_reset(struct omap3_spi_slave *ds)
writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, >regs->wakeupenable);
 }
 
-#ifdef CONFIG_DM_SPI
 static void omap3_spi_write_chconf(struct udevice *dev, int val)
-#else
-static void omap3_spi_write_chconf(struct omap3_spi_slave *ds, int val)
-#endif
 {
-   unsigned int cs;
-#ifdef CONFIG_DM_SPI
struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
struct omap3_spi_slave *ds = dev_get_priv(dev->parent);
-
-
-   cs = platdata->cs;
-#else
-   cs = ds->slave.cs;
-#endif
+   unsigned int cs = platdata->cs;
 
writel(val, >regs->channel[cs].chconf);
/* Flash post writes to make immediate effect */
readl(>regs->channel[cs].chconf);
 }
 

[U-Boot] [PATCH 0/4] Convert omap3-spi driver to Driver Model

[Christophe Ricard]

Hi Simon,

This patchset tries to convert the TI omap3_spi driver to Driver Model.
It has been tested on a TI BeagleBoard xM.

Best Regards
Christophe



Christophe Ricard (4):
  spi: omap3: Remove unused variable irqstatus in omap3_spi_txrx
  spi: spi-uclass: Set slave wordlen with SPI_DEFAULT_WORDLEN
  spi: omap3: Convert to DM
  spi: omap3: Convert fully to DM_SPI

 drivers/spi/Kconfig  |   6 +
 drivers/spi/omap3_spi.c  | 411 +++
 drivers/spi/omap3_spi.h  | 109 -
 drivers/spi/spi-uclass.c |   1 +
 4 files changed, 240 insertions(+), 287 deletions(-)
 delete mode 100644 drivers/spi/omap3_spi.h

-- 
2.5.0

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[U-Boot] [PATCH 1/4] spi: omap3: Remove unused variable irqstatus in omap3_spi_txrx

[Christophe Ricard]

Remove unused variable irqstatus in omap3_spi_txrx

Signed-off-by: Christophe Ricard 
---

 drivers/spi/omap3_spi.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index 85f9e85..95cdfa3 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -336,7 +336,6 @@ int omap3_spi_txrx(struct spi_slave *slave, unsigned int 
len,
struct omap3_spi_slave *ds = to_omap3_spi(slave);
ulong start;
int chconf = readl(>regs->channel[ds->slave.cs].chconf);
-   int irqstatus = readl(>regs->irqstatus);
int i=0;
 
/*Enable SPI channel*/
@@ -351,7 +350,6 @@ int omap3_spi_txrx(struct spi_slave *slave, unsigned int 
len,
/*Shift in and out 1 byte at time*/
for (i=0; i < len; i++){
/* Write: wait for TX empty (TXS == 1)*/
-   irqstatus |= (1<< (4*(ds->slave.bus)));
start = get_timer(0);
while (!(readl(>regs->channel[ds->slave.cs].chstat) &
 OMAP3_MCSPI_CHSTAT_TXS)) {
-- 
2.5.0

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[U-Boot] [PATCH 2/4] spi: spi-uclass: Set slave wordlen with SPI_DEFAULT_WORDLEN

[Christophe Ricard]

In some case wordlen may not be set. Use SPI_DEFAULT_WORDLEN as default.

Signed-off-by: Christophe Ricard 
---

 drivers/spi/spi-uclass.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index 677c020..5561f36 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -158,6 +158,7 @@ static int spi_child_pre_probe(struct udevice *dev)
slave->max_hz = plat->max_hz;
slave->mode = plat->mode;
slave->mode_rx = plat->mode_rx;
+   slave->wordlen = SPI_DEFAULT_WORDLEN;
 
return 0;
 }
-- 
2.5.0

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[U-Boot] [PATCH 3/5] i2c: omap24xx: Remove unused I2C_WAIT macro

[Christophe Ricard]

I2C_WAIT macro is not used in the code.
200 is bound to a fixed 10 Hz i2c speed based on an existing formula:
( 1000 / speed ) * 2 where speed = 100 000.

Signed-off-by: Christophe Ricard 
---

 drivers/i2c/omap24xx_i2c.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index d6e5fe9..48ca446 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -55,9 +55,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define I2C_TIMEOUT1000
 
-/* Absolutely safe for status update at 100 kHz I2C: */
-#define I2C_WAIT   200
-
 #ifdef CONFIG_DM_I2C
 struct omap24_i2c_bus {
int bus_num;
-- 
2.5.0

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[U-Boot] [PATCH 2/5] i2c: omap24xx: Fix waitdelay value for I2C HS

[Christophe Ricard]

After several testings and experiment, it appears that waitdelay calculation
formula was giving different behavior on the i2c status registers.

Experiment shows waitdelay needs to be extended at least 4 times to get
proper results.

Signed-off-by: Christophe Ricard 
---

 drivers/i2c/omap24xx_i2c.c | 18 --
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index f3a4d96..d6e5fe9 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -168,6 +168,13 @@ static int omap24_i2c_setspeed(struct udevice *adap, 
unsigned int speed)
scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
 
+#ifdef CONFIG_SYS_I2C
+   adap->speed = speed;
+   adap->waitdelay = (1000 / speed) * 8; /* wait for 20 
clkperiods */
+#else
+   i2c_bus->clock_frequency = speed;
+   i2c_bus->waitdelay = (1000 / speed) * 8; /* wait for 20 
clkperiods */
+#endif
} else {
/* Standard and fast speed */
psc = omap24_i2c_findpsc(, , speed);
@@ -175,15 +182,15 @@ static int omap24_i2c_setspeed(struct udevice *adap, 
unsigned int speed)
puts("Error : I2C initializing clock\n");
return -1;
}
-   }
 
 #ifdef CONFIG_SYS_I2C
-   adap->speed = speed;
-   adap->waitdelay = (1000 / speed) * 2; /* wait for 20 clkperiods */
+   adap->speed = speed;
+   adap->waitdelay = (1000 / speed) * 2; /* wait for 20 
clkperiods */
 #else
-   i2c_bus->clock_frequency = speed;
-   i2c_bus->waitdelay = (1000 / speed) * 2; /* wait for 20 clkperiods 
*/
+   i2c_bus->clock_frequency = speed;
+   i2c_bus->waitdelay = (1000 / speed) * 2; /* wait for 20 
clkperiods */
 #endif
+   }
 
writew(0, _base->con);
writew(psc, _base->psc);
@@ -467,7 +474,6 @@ static int omap24_i2c_read(struct udevice *adap, uchar 
chip, uint addr,
i2c_bus = dev_get_priv(adap);
i2c_base = i2c_bus->i2c_base;
 #endif
-
if (alen < 0) {
puts("I2C read: addr len < 0\n");
return 1;
-- 
2.5.0

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[U-Boot] [PATCH 5/5] i2c: omap24xx: Convert fully to DM_I2C

[Christophe Ricard]

For several reasons:
- code clarity
- DM trends in u-boot
...

It is better to make omap24xx_i2c driver 100% DM_I2C based.

Signed-off-by: Christophe Ricard 
---

 drivers/i2c/omap24xx_i2c.c | 447 +
 drivers/i2c/omap24xx_i2c.h | 154 
 2 files changed, 163 insertions(+), 438 deletions(-)
 delete mode 100644 drivers/i2c/omap24xx_i2c.h

diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index 774edaf..baccb89 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -49,31 +49,164 @@
 #include 
 #include 
 
-#include "omap24xx_i2c.h"
-
 DECLARE_GLOBAL_DATA_PTR;
 
+/* I2C masks */
+
+/* I2C Interrupt Enable Register (I2C_IE): */
+#define I2C_IE_GC_IE   (1 << 5)
+#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
+#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
+#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
+#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
+#define I2C_IE_AL_IE   (1 << 0) /* Arbitration lost interrupt enable */
+
+/* I2C Status Register (I2C_STAT): */
+
+#define I2C_STAT_SBD   (1 << 15) /* Single byte data */
+#define I2C_STAT_BB(1 << 12) /* Bus busy */
+#define I2C_STAT_ROVR  (1 << 11) /* Receive overrun */
+#define I2C_STAT_XUDF  (1 << 10) /* Transmit underflow */
+#define I2C_STAT_AAS   (1 << 9)  /* Address as slave */
+#define I2C_STAT_GC(1 << 5)
+#define I2C_STAT_XRDY  (1 << 4)  /* Transmit data ready */
+#define I2C_STAT_RRDY  (1 << 3)  /* Receive data ready */
+#define I2C_STAT_ARDY  (1 << 2)  /* Register access ready */
+#define I2C_STAT_NACK  (1 << 1)  /* No acknowledgment interrupt enable */
+#define I2C_STAT_AL(1 << 0)  /* Arbitration lost interrupt enable */
+
+/* I2C Interrupt Code Register (I2C_INTCODE): */
+
+#define I2C_INTCODE_MASK   7
+#define I2C_INTCODE_NONE   0
+#define I2C_INTCODE_AL 1   /* Arbitration lost */
+#define I2C_INTCODE_NAK2   /* No acknowledgement/general 
call */
+#define I2C_INTCODE_ARDY   3   /* Register access ready */
+#define I2C_INTCODE_RRDY   4   /* Rcv data ready */
+#define I2C_INTCODE_XRDY   5   /* Xmit data ready */
+
+/* I2C Buffer Configuration Register (I2C_BUF): */
+
+#define I2C_BUF_RDMA_EN(1 << 15) /* Receive DMA channel enable 
*/
+#define I2C_BUF_XDMA_EN(1 << 7)  /* Transmit DMA channel 
enable */
+
+/* I2C Configuration Register (I2C_CON): */
+
+#define I2C_CON_EN (1 << 15)  /* I2C module enable */
+#define I2C_CON_BE (1 << 14)  /* Big endian mode */
+#define I2C_CON_STB(1 << 11)  /* Start byte mode (master mode only) */
+#define I2C_CON_MST(1 << 10)  /* Master/slave mode */
+#define I2C_CON_TRX(1 << 9)   /* Transmitter/receiver mode */
+  /* (master mode only) */
+#define I2C_CON_XA (1 << 8)   /* Expand address */
+#define I2C_CON_STP(1 << 1)   /* Stop condition (master mode only) */
+#define I2C_CON_STT(1 << 0)   /* Start condition (master mode only) */
+
+/* I2C System Test Register (I2C_SYSTEST): */
+
+#define I2C_SYSTEST_ST_EN  (1 << 15) /* System test enable */
+#define I2C_SYSTEST_FREE   (1 << 14) /* Free running mode, on brkpoint) */
+#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
+#define I2C_SYSTEST_TMODE_SHIFT(12)  /* Test mode select */
+#define I2C_SYSTEST_SCL_I  (1 << 3)  /* SCL line sense input value */
+#define I2C_SYSTEST_SCL_O  (1 << 2)  /* SCL line drive output value */
+#define I2C_SYSTEST_SDA_I  (1 << 1)  /* SDA line sense input value */
+#define I2C_SYSTEST_SDA_O  (1 << 0)  /* SDA line drive output value */
+
+/* I2C System Status Register (I2C_SYSS): */
+
+#define I2C_SYSS_RDONE  (1 << 0)  /* Internel reset monitoring */
+
+#define I2C_SCLL_SCLL  0
+#define I2C_SCLL_SCLL_M0xFF
+#define I2C_SCLL_HSSCLL8
+#define I2C_SCLH_HSSCLL_M  0xFF
+#define I2C_SCLH_SCLH  0
+#define I2C_SCLH_SCLH_M0xFF
+#define I2C_SCLH_HSSCLH8
+#define I2C_SCLH_HSSCLH_M  0xFF
+
+#define OMAP_I2C_STANDARD  10
+#define OMAP_I2C_FAST_MODE 40
+#define OMAP_I2C_HIGH_SPEED340
+
+#define SYSTEM_CLOCK_121200
+#define SYSTEM_CLOCK_131300
+#define SYSTEM_CLOCK_192   1920
+#define SYSTEM_CLOCK_969600
+
+/* Use the reference value of 96MHz if not explicitly set by the board */
+#ifndef I2C_IP_CLK
+#define I2C_IP_CLK SYSTEM_CLOCK_96
+#endif
+
+/*
+ * The reference minimum clock for high speed is 19.2MHz.
+ * The linux 2.6.30 kernel uses this value.
+ * The reference minimum clock for fast mode is 9.6MHz
+ * The reference minimum clock for standard mode is 4MHz
+ * In TRM, the value of 12MHz is used.
+ */
+#ifndef 

[U-Boot] [PATCH 4/5] i2c: omap24xx: Fix high speed trimming calculation

[Christophe Ricard]

Work based on i2c-omap.c from linux kernel.

fsscll/fssclh and hsscll/hssclh was always negative in high speed.

i2c high speed frequency start after 400Khz.

Signed-off-by: Christophe Ricard 
---

 drivers/i2c/omap24xx_i2c.c | 17 +
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index 48ca446..774edaf 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -129,7 +129,9 @@ static int omap24_i2c_setspeed(struct udevice *adap, 
unsigned int speed)
i2c_base = i2c_bus->i2c_base;
 #endif
 
-   if (speed >= OMAP_I2C_HIGH_SPEED) {
+   if (speed > 40) {
+   unsigned long scl;
+
/* High speed */
psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
psc -= 1;
@@ -139,12 +141,11 @@ static int omap24_i2c_setspeed(struct udevice *adap, 
unsigned int speed)
}
 
/* For first phase of HS mode */
-   fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
+   scl = I2C_INTERNAL_SAMPLING_CLK / 40;
 
-   fssclh = fsscll;
+   fsscll = scl - (scl / 3) - 7;
+   fssclh = (scl / 3)  - 5;
 
-   fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
-   fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
if (((fsscll < 0) || (fssclh < 0)) ||
((fsscll > 255) || (fssclh > 255))) {
puts("Error : I2C initializing first phase clock\n");
@@ -152,10 +153,10 @@ static int omap24_i2c_setspeed(struct udevice *adap, 
unsigned int speed)
}
 
/* For second phase of HS mode */
-   hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
+   scl = I2C_IP_CLK / speed;
+   hsscll = scl - (scl / 3) - 7;
+   hssclh = (scl / 3) - 5;
 
-   hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
-   hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
if (((fsscll < 0) || (fssclh < 0)) ||
((fsscll > 255) || (fssclh > 255))) {
puts("Error : I2C initializing second phase clock\n");
-- 
2.5.0

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[U-Boot] [PATCH 1/5] i2c: omap24xx: Convert to DM

[Christophe Ricard]

Convert omap24xx_i2c driver to DM

Signed-off-by: Christophe Ricard 
---

 drivers/i2c/Kconfig|   8 ++
 drivers/i2c/omap24xx_i2c.c | 280 +++--
 2 files changed, 277 insertions(+), 11 deletions(-)

diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 14adda2..3498af1 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -58,6 +58,14 @@ config DM_I2C_GPIO
  bindings are supported.
  Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
 
+config SYS_I2C_OMAP24XX
+   bool "Texas Instrument OMAP I2C driver"
+   depends on DM_I2C
+   help
+ Enable support for the I2C interface on the Texas Instruments
+ OMAP1/2 family of processors. Like OMAP1510/1610/1710/5912 and 
OMAP242x.
+ For details see http://www.ti.com/omap.
+
 config SYS_I2C_ROCKCHIP
bool "Rockchip I2C driver"
depends on DM_I2C
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index 79a5c94..f3a4d96 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -36,13 +36,18 @@
  * Copyright (c) 2014 Hannes Schmelzer , B
  * - Added support for set_speed
  *
+ * Copyright (c) 2016 Christophe Ricard 
+ * - Added support for DM_I2C
+ *
  */
 
 #include 
 #include 
+#include 
 
 #include 
 #include 
+#include 
 
 #include "omap24xx_i2c.h"
 
@@ -53,10 +58,26 @@ DECLARE_GLOBAL_DATA_PTR;
 /* Absolutely safe for status update at 100 kHz I2C: */
 #define I2C_WAIT   200
 
+#ifdef CONFIG_DM_I2C
+struct omap24_i2c_bus {
+   int bus_num;
+   int waitdelay;
+   unsigned clock_frequency;
+   struct i2c *i2c_base;
+};
+#endif
+
+#ifdef CONFIG_SYS_I2C
 static int wait_for_bb(struct i2c_adapter *adap);
 static struct i2c *omap24_get_base(struct i2c_adapter *adap);
 static u16 wait_for_event(struct i2c_adapter *adap);
 static void flush_fifo(struct i2c_adapter *adap);
+#else
+static int wait_for_bb(struct udevice *dev);
+static u16 wait_for_event(struct udevice *dev);
+static void flush_fifo(struct udevice *dev);
+#endif
+
 static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
 {
unsigned int sampleclk, prescaler;
@@ -90,13 +111,27 @@ static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint 
speed)
}
return -1;
 }
+
+#ifdef CONFIG_SYS_I2C
 static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
+#else
+static int omap24_i2c_setspeed(struct udevice *adap, unsigned int speed)
+#endif
 {
-   struct i2c *i2c_base = omap24_get_base(adap);
+   struct i2c *i2c_base;
int psc, fsscll = 0, fssclh = 0;
int hsscll = 0, hssclh = 0;
u32 scll = 0, sclh = 0;
 
+#ifdef CONFIG_SYS_I2C
+   i2c_base = omap24_get_base(adap);
+#else
+   struct omap24_i2c_bus *i2c_bus;
+
+   i2c_bus = dev_get_priv(adap);
+   i2c_base = i2c_bus->i2c_base;
+#endif
+
if (speed >= OMAP_I2C_HIGH_SPEED) {
/* High speed */
psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
@@ -142,8 +177,14 @@ static uint omap24_i2c_setspeed(struct i2c_adapter *adap, 
uint speed)
}
}
 
+#ifdef CONFIG_SYS_I2C
adap->speed = speed;
adap->waitdelay = (1000 / speed) * 2; /* wait for 20 clkperiods */
+#else
+   i2c_bus->clock_frequency = speed;
+   i2c_bus->waitdelay = (1000 / speed) * 2; /* wait for 20 clkperiods 
*/
+#endif
+
writew(0, _base->con);
writew(psc, _base->psc);
writew(scll, _base->scll);
@@ -154,13 +195,26 @@ static uint omap24_i2c_setspeed(struct i2c_adapter *adap, 
uint speed)
return 0;
 }
 
+#ifdef CONFIG_SYS_I2C
 static void omap24_i2c_deblock(struct i2c_adapter *adap)
+#else
+static int omap24_i2c_deblock(struct udevice *adap)
+#endif
 {
-   struct i2c *i2c_base = omap24_get_base(adap);
+   struct i2c *i2c_base;
int i;
u16 systest;
u16 orgsystest;
 
+#ifdef CONFIG_SYS_I2C
+   i2c_base = omap24_get_base(adap);
+#else
+   struct omap24_i2c_bus *i2c_bus;
+
+   i2c_bus = dev_get_priv(adap);
+   i2c_base = i2c_bus->i2c_base;
+#endif
+
/* set test mode ST_EN = 1 */
orgsystest = readw(_base->systest);
systest = orgsystest;
@@ -198,14 +252,31 @@ static void omap24_i2c_deblock(struct i2c_adapter *adap)
 
/* restore original mode */
writew(orgsystest, _base->systest);
+
+#ifdef CONFIG_DM_I2C
+   return 0;
+#endif
 }
 
+#ifdef CONFIG_SYS_I2C
 static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
+#else
+static void omap24_i2c_init(struct udevice *adap, int speed, int slaveadd)
+#endif
 {
-   struct i2c *i2c_base = omap24_get_base(adap);
+   struct i2c *i2c_base;
int timeout = I2C_TIMEOUT;
int deblock = 1;
 
+#ifdef CONFIG_SYS_I2C
+   i2c_base = omap24_get_base(adap);
+#else
+   struct omap24_i2c_bus *i2c_bus;

[U-Boot] [PATCH 0/5] Convert omap24xx-i2c driver to Driver Model

[Christophe Ricard]

Hi Simon,

This patchset tries to convert the TI omap24xx_i2c driver to Driver Model.
It has been tested on a TI BeagleBoard xM.

Best Regards
Christophe



Christophe Ricard (5):
  i2c: omap24xx: Convert to DM
  i2c: omap24xx: Fix waitdelay value for I2C HS
  i2c: omap24xx: Remove unused I2C_WAIT macro
  i2c: omap24xx: Fix high speed trimming calculation
  i2c: omap24xx: Convert fully to DM_I2C

 drivers/i2c/Kconfig|   8 +
 drivers/i2c/omap24xx_i2c.c | 395 ++---
 drivers/i2c/omap24xx_i2c.h | 154 --
 3 files changed, 276 insertions(+), 281 deletions(-)
 delete mode 100644 drivers/i2c/omap24xx_i2c.h

-- 
2.5.0

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[U-Boot] Kconfig bug (optional choice deselected by following option)

[Mateusz Kulikowski]

-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256

Hi all,

I have found weird feature of Kconfig. 
If I misused something, please let me know - I found at least one place 
where the same error occurs.

Let's consider the following Kconfig (you can put it anywhere in the source 
tree):
<-- copy ->
menu "Testmenu"
choice
prompt "Problem to solve"
optional
default n
help
  Solve one of great world problems

config SOLVE_HUNGER
bool "Hunger"

config SOLVE_WARS
bool "Wars"

config CURE_CANCER
bool "Cancer"

endchoice

config TREES
default n
bool "Plant trees in garden" 
endmenu

config BLAH
default n
bool "Totally unrelated option"

<- paste --->

Now, select HUNGER important problem to solve; Warning - select it with space, 
_not_ enter + selection from list;
Then select either TREES or BLAH.

Weird thing is - SOLVE_HUNGER is unselected.

It doesn't happen when you select (anything) by entering selection menu (i.e. 
enter).
Even if you deselect option and then select it with space.

It happens both in menuconfig and nconfig.

It happens both in recent U-Boot b57843e6 and Linux kernel ece62678.

Unfortunately my knowledge of Kconfig is very limited so your help would be 
appreciated.

Best Regards,
Mateusz
-BEGIN PGP SIGNATURE-
Version: GnuPG v2

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[U-Boot] [PATCH 0/4] ARM: sheevaplug: misc fixes

[Peter Korsgaard]

Hi,

The following patch series fixes a number of issues I noticed while updating
a sheevaplug from 2013.10 to 2016.01:

Peter Korsgaard (4):
  ARM: sheevaplug: unbreak default environment
  ARM: sheevaplug: unbreak kernel bootargs / mtdparts command by dropping 
double mtdparts=
  ARM: sheevaplug: drop unneded 'usb start' from boot command
  ARM: sheevaplug: correct nand partition layout

--
Bye, Peter Korsgaard
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[U-Boot] [PATCH 4/4] ARM: sheevaplug: correct nand partition layout

[Peter Korsgaard]

Commit 1e3d640316 (ARM: sheevaplug: redefine MTDPARTS) changed the partition
layout (without any description why), but didn't change the offset/size to
load the kernel from or the root=/dev/mtdblockX in the bootargs.

The 3MB forseen for a kernel is furthermore too little. A 4.4 build of
mvebu_v5_defconfig is 3.6MB:

-rw-r--r-- 1 peko peko 3.6M Jan 16 20:24 uImage.kirkwood-sheevaplug

When device tree support for sheevaplug was added to the kernel in commit
ee514b381e (ARM: Kirkwood: Add dts files for Sheevaplug and eSATA
Sheevaplug) a default flash partition layout (used if mtdparts= isn't passed
on the command line / CONFIG_MTD_CMDLINE_PARTS isn't enabled) with 1MB for
u-boot / environment, 4MB for the kernel and the rest for the rootfs, so use
that layout here and adjust the kernel loading to match.

Signed-off-by: Peter Korsgaard 
---
 include/configs/sheevaplug.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
index c529636..f9fb9bc 100644
--- a/include/configs/sheevaplug.h
+++ b/include/configs/sheevaplug.h
@@ -64,12 +64,12 @@
 
 #define CONFIG_MTDPARTS\
"orion_nand:512K(uboot),"   \
-   "512K(env),1M(script),6M(kernel),"  \
-   "12M(ramdisk),4M(spare),-(rootfs)\0"
+   "512K(env),4M(kernel)," \
+   "-(rootfs)\0"
 
 #define CONFIG_EXTRA_ENV_SETTINGS  "x_bootargs=console"\
"=ttyS0,115200 mtdparts="CONFIG_MTDPARTS\
-   "x_bootcmd_kernel=nand read 0x640 0x10 0x30\0" \
+   "x_bootcmd_kernel=nand read 0x640 0x10 0x40\0" \
"x_bootcmd_usb=usb start\0" \
"x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
 
-- 
2.1.4

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[U-Boot] [PATCH 1/4] ARM: sheevaplug: unbreak default environment

[Peter Korsgaard]

Commit 1e3d640316 (ARM: sheevaplug: redefine MTDPARTS) changed the mtdparts
part of the default environment, but dropped the trailing zero termination -
So the definition of x_bootcmd_kernel becomes part of the x_bootargs
variable.

Fix it by reintroducing the zero termination.

Signed-off-by: Peter Korsgaard 
---
 include/configs/sheevaplug.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
index ebc3d64..7d773a8 100644
--- a/include/configs/sheevaplug.h
+++ b/include/configs/sheevaplug.h
@@ -65,7 +65,7 @@
 #define CONFIG_MTDPARTS\
"mtdparts=orion_nand:512K(uboot),"  \
"512K(env),1M(script),6M(kernel),"  \
-   "12M(ramdisk),4M(spare),-(rootfs)"
+   "12M(ramdisk),4M(spare),-(rootfs)\0"
 
 #define CONFIG_EXTRA_ENV_SETTINGS  "x_bootargs=console"\
"=ttyS0,115200 mtdparts="CONFIG_MTDPARTS\
-- 
2.1.4

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[U-Boot] [PATCH 2/4] ARM: sheevaplug: unbreak kernel bootargs / mtdparts command by dropping double mtdparts=

[Peter Korsgaard]

Commit 1e3d640316 (ARM: sheevaplug: redefine MTDPARTS) prepended mtdparts=
to the flash partition information in CONFIG_MTDPARTS, but it is used like
"mtdparts=" CONFIG_MTDPARTS - So we end up passing mtdparts=mtdparts=.. to
the kernel, confusing the cmdline partition parser.

Fix it by dropping the double 'mtdparts='.

Signed-off-by: Peter Korsgaard 
---
 include/configs/sheevaplug.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
index 7d773a8..8110f83 100644
--- a/include/configs/sheevaplug.h
+++ b/include/configs/sheevaplug.h
@@ -63,7 +63,7 @@
"${x_bootcmd_usb}; bootm 0x640;"
 
 #define CONFIG_MTDPARTS\
-   "mtdparts=orion_nand:512K(uboot),"  \
+   "orion_nand:512K(uboot),"   \
"512K(env),1M(script),6M(kernel),"  \
"12M(ramdisk),4M(spare),-(rootfs)\0"
 
-- 
2.1.4

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[U-Boot] [PATCH 3/4] ARM: sheevaplug: drop unneded 'usb start' from boot command

[Peter Korsgaard]

The default bootcommand executes x_bootcmd_usb AFTER loading a kernel from
nand and just before executing it, which only slows down boot without adding
any functionality - So drop it.

Signed-off-by: Peter Korsgaard 
---
 include/configs/sheevaplug.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
index 8110f83..c529636 100644
--- a/include/configs/sheevaplug.h
+++ b/include/configs/sheevaplug.h
@@ -60,7 +60,7 @@
  */
 #define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
"setenv bootargs ${x_bootargs} ${x_bootargs_root}; "\
-   "${x_bootcmd_usb}; bootm 0x640;"
+   "bootm 0x640;"
 
 #define CONFIG_MTDPARTS\
"orion_nand:512K(uboot),"   \
-- 
2.1.4

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Re: [U-Boot] x86: Bay Trail support with W83627DHG

[Stefan Roese]

Hi Bin,

On 17.01.2016 03:35, Stefan Roese wrote:

On 16.01.2016 15:08, Bin Meng wrote:

On Fri, Jan 15, 2016 at 10:37 PM, Stefan Roese  wrote:

Hi Simon, Hi Bin!

I'm currently busy with porting U-Boot to a Bay Trail board.
Equipped with an Intel Atom E3845 and additionally the
Nuvoton / Winbond W83627DHG Super IO chip.

My staring point for this port is the Minnowboard MAX, which
works very well btw. I've used the same binaries as described
in the README.x86 as on the MinnowMAX for this new Bay Trail
board. But am not able yet to see any output on the DEBUG_UART.

Bin, you already mentioned in a previous mail, that I need to
enable the legacy UART in the Super IO chip for this. I've
started adding a small driver for this, similar to the one
you've introduced for the SMSC:


Ah, looks I delivered inaccurate information before! I just remember
BayTrail SoC integrates a legacy UART at I/O 0x3f8 and it is enabled
by FSP by default. If you use a debug version of FSP (only gold4
release provides a debug version FSP), you will se lots of useful
debug information printed on the serial port (the one connected to the
SoC legacy UART). But, why does your board have an additional Nuvoton
/ Winbond W83627DHG Super IO chip? I guess it's for other legacy
peripherals like 8042 KBC, etc? We need figure out the serial port you
are trying to enable is connected to which chip. If it is connected
directly to BayTrail SoC, then you don't need program this W83627DHG.


It is connected to the Winbond UART. So we need to enable and use it.
But how can I disable the BayTrail internal legacy UART? So that the
Winbond one is really used?


Okay. I was able to work around this problem with the included
legacy UART in the Bay Trail Atom. By moving the IO base address
of the Winbond COM1 from 0x3f8 to a different (unused) location.
And then using this new address as the UART base address. U-Boot
boots to the prompt with the "fixed" memory-down DDR parameters
to the FSP in this configuration.

Still I would really like to disable the internal legacy UART
and only use the Winbond UART(s) at the default address. Disabling
the Bay Trail legacy UART by clearing the "UART_CONT.COM1EN" bit,
as described in the "Intel AtomTM Processor E3800 Product Family
Datasheet", does not seem to fix this problem. I need to double
check this tomorrow though.

Bin, Simon, do you have any ideas on how to disable this Atom
legacy UART instead. It must be possible, as when booting into
Linux with the original BIOS, the Winbond COM1 works just fine
at 0x3f8.

Thanks,
Stefan
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