[U-Boot] [PATCH v2 04/12] arm, am335x: add some missing GPIO register definitions

[Heiko Schocher]

add missing:
OMAP_GPIO_IRQSTATUS_SET_0 and OMAP_GPIO_IRQSTATUS_SET_1
registers.

Signed-off-by: Heiko Schocher 
Reviewed-by: Tom Rini 

---

Changes in v2:
- add Reviewed-by from Tom Rini

 arch/arm/include/asm/arch-am33xx/cpu.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h 
b/arch/arm/include/asm/arch-am33xx/cpu.h
index 112ac5e..e950b96 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -497,6 +497,8 @@ struct ctrl_stat {
 #define OMAP_GPIO_SYSSTATUS0x0114
 #define OMAP_GPIO_IRQSTATUS1   0x002c
 #define OMAP_GPIO_IRQSTATUS2   0x0030
+#define OMAP_GPIO_IRQSTATUS_SET_0  0x0034
+#define OMAP_GPIO_IRQSTATUS_SET_1  0x0038
 #define OMAP_GPIO_CTRL 0x0130
 #define OMAP_GPIO_OE   0x0134
 #define OMAP_GPIO_DATAIN   0x0138
-- 
2.5.5

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[U-Boot] [PATCH v2 10/12] armv7: omap-common: make SPL board_mmc_init() weak

[Heiko Schocher]

make this function weak, so board code can setup in SPL
MMC init with board special values.

Signed-off-by: Heiko Schocher 
---

Changes in v2: None

 arch/arm/cpu/armv7/omap-common/boot-common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c 
b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 0456263..8333b20 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -200,7 +200,7 @@ void spl_board_init(void)
 #endif
 }
 
-int board_mmc_init(bd_t *bis)
+__weak int board_mmc_init(bd_t *bis)
 {
switch (spl_boot_device()) {
case BOOT_DEVICE_MMC1:
-- 
2.5.5

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[U-Boot] [PATCH v2 12/12] am335x, shc: add support for the am335x based bosch shc board

[Heiko Schocher]

U-Boot SPL 2016.03-rc3-00019-g6dfb4c2-dirty (Mar 09 2016 - 07:40:06)
SHC C3-Sample
MPU reference clock runs at 6 MHz
Setting MPU clock to 594 MHz
Enabling Spread Spectrum of 18 permille for MPU
Trying to boot from MMC
reading u-boot.img
reading u-boot.img

U-Boot 2016.03-rc3-00019-g6dfb4c2-dirty (Mar 09 2016 - 07:05:35 +0100)

   Watchdog enabled
I2C:   ready
DRAM:  512 MiB
reloc off 1f783000
MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
Net:   cpsw
U-Boot#

Signed-off-by: Heiko Schocher 
---
This patch drops the following checkpatch warnings:

warning: please write a paragraph that describes the config symbol fully
  I wrote a help ... I do not understand, whats missing here...

warning: line over 80 characters
  On places where I think this does not disturb...

new patch in v2 "fs: move some defines to Kconfig" -> Patch:
http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/259522
not longer needed ...

Changes in v2:
- add comment from Tom Rini:
  remove command in board code
  remove CONS_INDEX as we have the console fix on uart1
- rebased to current mainline commit:
  4b6e1fda107e5244e80ebc41865650ac2873dc88
  Merge git://git.denx.de/u-boot-dm
- prevent need of patch
  http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/259522

 arch/arm/Kconfig   |   9 +
 board/bosch/shc/Kconfig|  87 
 board/bosch/shc/MAINTAINERS|  11 +
 board/bosch/shc/Makefile   |  10 +
 board/bosch/shc/README | 114 +
 board/bosch/shc/board.c| 648 +
 board/bosch/shc/board.h| 187 +
 board/bosch/shc/mux.c  | 261 
 configs/am335x_shc_defconfig   |  21 +
 configs/am335x_shc_ict_defconfig   |  21 +
 configs/am335x_shc_netboot_defconfig   |  21 +
 configs/am335x_shc_prompt_defconfig|  19 +
 configs/am335x_shc_sdboot_defconfig|  21 +
 configs/am335x_shc_sdboot_prompt_defconfig |  21 +
 include/configs/am335x_shc.h   | 340 +++
 15 files changed, 1791 insertions(+)
 create mode 100644 board/bosch/shc/Kconfig
 create mode 100644 board/bosch/shc/MAINTAINERS
 create mode 100644 board/bosch/shc/Makefile
 create mode 100644 board/bosch/shc/README
 create mode 100644 board/bosch/shc/board.c
 create mode 100644 board/bosch/shc/board.h
 create mode 100644 board/bosch/shc/mux.c
 create mode 100644 configs/am335x_shc_defconfig
 create mode 100644 configs/am335x_shc_ict_defconfig
 create mode 100644 configs/am335x_shc_netboot_defconfig
 create mode 100644 configs/am335x_shc_prompt_defconfig
 create mode 100644 configs/am335x_shc_sdboot_defconfig
 create mode 100644 configs/am335x_shc_sdboot_prompt_defconfig
 create mode 100644 include/configs/am335x_shc.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6b65d8e..0dcc151 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -374,6 +374,14 @@ config TARGET_AM335X_EVM
select DM_GPIO
select TI_I2C_BOARD_DETECT
 
+config TARGET_AM335X_SHC
+   bool "Support am335x based shc board from bosch"
+   select CPU_V7
+   select SUPPORT_SPL
+   select DM
+   select DM_SERIAL
+   select DM_GPIO
+
 config TARGET_AM335X_SL50
bool "Support am335x_sl50"
select CPU_V7
@@ -805,6 +813,7 @@ source "arch/arm/cpu/armv8/Kconfig"
 
 source "arch/arm/imx-common/Kconfig"
 
+source "board/bosch/shc/Kconfig"
 source "board/BuR/kwb/Kconfig"
 source "board/BuR/tseries/Kconfig"
 source "board/CarMediaLab/flea3/Kconfig"
diff --git a/board/bosch/shc/Kconfig b/board/bosch/shc/Kconfig
new file mode 100644
index 000..c71af11
--- /dev/null
+++ b/board/bosch/shc/Kconfig
@@ -0,0 +1,87 @@
+if TARGET_AM335X_SHC
+
+config SYS_BOARD
+   default "shc"
+
+config SYS_VENDOR
+   default "bosch"
+
+config SYS_SOC
+   default "am33xx"
+
+config SYS_CONFIG_NAME
+   default "am335x_shc"
+
+choice
+   prompt "enable different boot versions for the shc board"
+   default EMMC
+   help
+ Select the boot version of the shc board.
+
+config SHC_EMMC
+   bool "enable eMMC"
+   help
+ enable here the eMMC functionality on the bosch shc board.
+
+config SHC_ICT
+   bool "enable ICT"
+   help
+ enable here the ICT functionality on the bosch shc board
+
+config SHC_NETBOOT
+   bool "enable NETBOOT"
+   help
+ enable here the NETBOOT functionality on the bosch shc board
+
+config SHC_SDBOOT
+   bool "enable SDBOOT"
+   help
+ enable here the SDBOOT functionality on the bosch shc board
+
+endchoice
+
+choice
+   prompt "enable different board versions for the shc board"
+   default C3_SAMPLE
+   help
+ Select the board version of the shc board.
+
+config B_SAMPLE
+   bool "B Sample board version"
+   help
+ activate, if you want to build for the B sample version
+ of 

[U-Boot] [PATCH v2 11/12] doc, spl, am335x: update am335x-network

[Heiko Schocher]

on the shc board we see when booting in net boot mode,
that the ROM bootloader sends "AM335x ROM" as
vendor-class-identifier. U-Boots doc says "DM814x ROM".

So, add the info to the doc, that there is also
"AM335x ROM" possible.

Signed-off-by: Heiko Schocher 
Reviewed-by: Tom Rini 
---

Changes in v2:
- add Reviewed-by from Tom Rini

 doc/SPL/README.am335x-network | 4 
 1 file changed, 4 insertions(+)

diff --git a/doc/SPL/README.am335x-network b/doc/SPL/README.am335x-network
index 9b63791..e3cf93f 100644
--- a/doc/SPL/README.am335x-network
+++ b/doc/SPL/README.am335x-network
@@ -66,6 +66,10 @@ subnet 192.168.8.0 netmask 255.255.255.0 {
   }
 }
 
+  May the ROM bootloader sends another "vendor-class-identifier"
+  on the shc board with an AM335X it is:
+  "AM335x ROM"
+
   2. Setup TFTP server.
  Install TFTP server and put image files to it's root directory
 (likely /tftpboot or /var/lib/tftpboot or /srv/tftp). You will need
-- 
2.5.5

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[U-Boot] [PATCH v2 07/12] bootstage: call show_boot_progress also in SPL

[Heiko Schocher]

show_boot_progress() is now called from SPL also.

Signed-off-by: Heiko Schocher 
---

Changes in v2: None

 common/init/board_init.c | 5 +
 common/spl/spl.c | 5 +
 include/bootstage.h  | 6 +++---
 3 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/common/init/board_init.c b/common/init/board_init.c
index d17bb29..ef01a9a 100644
--- a/common/init/board_init.c
+++ b/common/init/board_init.c
@@ -146,3 +146,8 @@ void board_init_f_init_reserve(ulong base)
base += CONFIG_SYS_MALLOC_F_LEN;
 #endif
 }
+
+/*
+ * Board-specific Platform code can reimplement show_boot_progress () if needed
+ */
+__weak void show_boot_progress(int val) {}
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 93f9bd1..9994c1b 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -36,6 +36,11 @@ struct spl_image_info spl_image;
 static bd_t bdata __attribute__ ((section(".data")));
 
 /*
+ * Board-specific Platform code can reimplement show_boot_progress () if needed
+ */
+__weak void show_boot_progress(int val) {}
+
+/*
  * Default function to determine if u-boot or the OS should
  * be started. This implementation always returns 1.
  *
diff --git a/include/bootstage.h b/include/bootstage.h
index 9765360..4b929e2 100644
--- a/include/bootstage.h
+++ b/include/bootstage.h
@@ -212,7 +212,9 @@ enum bootstage_id {
  */
 ulong timer_get_boot_us(void);
 
-#if !defined(CONFIG_SPL_BUILD) && !defined(USE_HOSTCC)
+#if defined(USE_HOSTCC)
+#define show_boot_progress(val) do {} while (0)
+#else
 /*
  * Board code can implement show_boot_progress() if needed.
  *
@@ -220,8 +222,6 @@ ulong timer_get_boot_us(void);
  * has occurred.
  */
 void show_boot_progress(int val);
-#else
-#define show_boot_progress(val) do {} while (0)
 #endif
 
 #if defined(CONFIG_BOOTSTAGE) && !defined(CONFIG_SPL_BUILD) && \
-- 
2.5.5

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[U-Boot] [PATCH v2 03/12] power, tps65217: add some defines

[Heiko Schocher]

add the following defines, needed for the upcoming shc board
support:

Signed-off-by: Heiko Schocher 
Reviewed-by: Tom Rini 

---

Changes in v2:
- add Reviewed-by from Tom Rini

 include/power/tps65217.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/power/tps65217.h b/include/power/tps65217.h
index 93cbe36..69a49f7 100644
--- a/include/power/tps65217.h
+++ b/include/power/tps65217.h
@@ -65,7 +65,10 @@ enum {
 #define TPS65217_USB_INPUT_CUR_LIMIT_1300MA0x02
 #define TPS65217_USB_INPUT_CUR_LIMIT_1800MA0x03
 
+#define TPS65217_DCDC_VOLT_SEL_950MV   0x02
+#define TPS65217_DCDC_VOLT_SEL_1100MV  0x08
 #define TPS65217_DCDC_VOLT_SEL_1125MV  0x09
+#define TPS65217_DCDC_VOLT_SEL_1200MV  0x0c
 #define TPS65217_DCDC_VOLT_SEL_1275MV  0x0F
 #define TPS65217_DCDC_VOLT_SEL_1325MV  0x11
 
-- 
2.5.5

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[U-Boot] [PATCH v2 06/12] arm, am335x: Enable Spread Spectrum for the MPU

[Heiko Schocher]

Enable Spread Spectrum for the MPU by calculating the required
values and setting the registers accordingly.

Signed-off-by: Heiko Schocher 
Reviewed-by: Tom Rini 

---

Changes in v2:
- add Reviewed-by from Tom Rini

 arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 73 
 arch/arm/include/asm/arch-am33xx/clock.h |  1 +
 arch/arm/include/asm/arch-am33xx/cpu.h   |  3 +-
 3 files changed, 76 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c 
b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
index 92142c8..7b841b2 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
@@ -159,3 +159,76 @@ void enable_basic_clocks(void)
/* Select the Master osc 24 MHZ as Timer2 clock source */
writel(0x1, >clktimer2clk);
 }
+
+/*
+ * Enable Spread Spectrum for the MPU by calculating the required
+ * values and setting the registers accordingly.
+ * @param permille The spreading in permille (10th of a percent)
+ */
+void set_mpu_spreadspectrum(int permille)
+{
+   u32 multiplier_m;
+   u32 predivider_n;
+   u32 cm_clksel_dpll_mpu;
+   u32 cm_clkmode_dpll_mpu;
+   u32 ref_clock;
+   u32 pll_bandwidth;
+   u32 mod_freq_divider;
+   u32 exponent;
+   u32 mantissa;
+   u32 delta_m_step;
+
+   printf("Enabling Spread Spectrum of %d permille for MPU\n",
+  permille);
+
+   /* Read PLL parameter m and n */
+   cm_clksel_dpll_mpu = readl(>clkseldpllmpu);
+   multiplier_m = (cm_clksel_dpll_mpu >> 8) & 0x3FF;
+   predivider_n = cm_clksel_dpll_mpu & 0x7F;
+
+   /*
+* Calculate reference clock (clock after pre-divider),
+* its max. PLL bandwidth,
+* and resulting mod_freq_divider
+*/
+   ref_clock = V_OSCK / (predivider_n + 1);
+   pll_bandwidth = ref_clock / 70;
+   mod_freq_divider = ref_clock / (4 * pll_bandwidth);
+
+   /* Calculate Mantissa/Exponent */
+   exponent = 0;
+   mantissa = mod_freq_divider;
+   while ((mantissa > 127) && (exponent < 7)) {
+   exponent++;
+   mantissa /= 2;
+   }
+   if (mantissa > 127)
+   mantissa = 127;
+
+   mod_freq_divider = mantissa << exponent;
+
+   /*
+* Calculate Modulation steps
+* As we use Downspread only, the spread is twice the value of
+* permille, so Div2!
+* As it takes the value in percent, divide by ten!
+*/
+   delta_m_step = ((u32)((multiplier_m * permille) / 10 / 2)) << 18;
+   delta_m_step /= 100;
+   delta_m_step /= mod_freq_divider;
+   if (delta_m_step > 0xF)
+   delta_m_step = 0xF;
+
+   /* Setup Spread Spectrum */
+   writel(delta_m_step, >sscdeltamstepdllmpu);
+   writel((exponent << 8) | mantissa, >sscmodfreqdivdpllmpu);
+   cm_clkmode_dpll_mpu = readl(>clkmoddpllmpu);
+   /* clear all SSC flags */
+   cm_clkmode_dpll_mpu &= ~(0xF << CM_CLKMODE_DPLL_SSC_EN_SHIFT);
+   /* enable SSC with Downspread only */
+   cm_clkmode_dpll_mpu |=  CM_CLKMODE_DPLL_SSC_EN_MASK |
+   CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK;
+   writel(cm_clkmode_dpll_mpu, >clkmoddpllmpu);
+   while (!(readl(>clkmoddpllmpu) & 0x2000))
+   ;
+}
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h 
b/arch/arm/include/asm/arch-am33xx/clock.h
index 7c6be4c..acf3fd5 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -117,4 +117,5 @@ void enable_basic_clocks(void);
 void do_enable_clocks(u32 *const *, u32 *const *, u8);
 void do_disable_clocks(u32 *const *, u32 *const *, u8);
 
+void set_mpu_spreadspectrum(int permille);
 #endif
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h 
b/arch/arm/include/asm/arch-am33xx/cpu.h
index e950b96..62bca8c 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -99,7 +99,8 @@ struct cm_wkuppll {
unsigned int timer0clkctrl; /* offset 0x10 */
unsigned int resv2[3];
unsigned int idlestdpllmpu; /* offset 0x20 */
-   unsigned int resv3[2];
+   unsigned int sscdeltamstepdllmpu; /* off  0x24 */
+   unsigned int sscmodfreqdivdpllmpu; /* off 0x28 */
unsigned int clkseldpllmpu; /* offset 0x2c */
unsigned int resv4[1];
unsigned int idlestdpllddr; /* offset 0x34 */
-- 
2.5.5

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[U-Boot] [PATCH v2 09/12] mmc: omap_hsmmc: enable 8bit interface for eMMC for AM33xx

[Heiko Schocher]

Enable 8bit interface on HSMMC2 for am33xx to support 8bit eMMC chips.

Signed-off-by: Heiko Schocher 
Reviewed-by: Tom Rini 

---

Changes in v2:
- add Reviewed-by from Tom Rini

 drivers/mmc/omap_hsmmc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index be34057..d007b56 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -701,6 +701,7 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint 
f_max, int cd_gpio,
priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) || \
+   defined(CONFIG_AM33XX) || \
defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
defined(CONFIG_HSMMC2_8BIT)
/* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
-- 
2.5.5

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[U-Boot] [PATCH v2 08/12] mmc: revert mmc: Handle switch error status bit in MMC card status

[Heiko Schocher]

revert patch:
commit: 6b2221b008e0: mmc: Handle switch error status bit in MMC card status

to get eMMC working on shc board

Signed-off-by: Heiko Schocher 
---

Changes in v2: None

 drivers/mmc/mmc.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 74b3d68..a8267fd 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -155,8 +155,6 @@ int mmc_send_status(struct mmc *mmc, int timeout)
 #endif
return TIMEOUT;
}
-   if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR)
-   return SWITCH_ERR;
 
return 0;
 }
@@ -516,7 +514,7 @@ static int mmc_change_freq(struct mmc *mmc)
err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
 
if (err)
-   return err == SWITCH_ERR ? 0 : err;
+   return err;
 
/* Now check to see that it worked */
err = mmc_send_ext_csd(mmc, ext_csd);
-- 
2.5.5

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[U-Boot] [PATCH v2 05/12] am335x: add some missing CM_CLKMODE_DPLL_SSC macros

[Heiko Schocher]

add missing CM_CLKMODE_DPLL_SSC_ACK_MASK,
CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK and
CM_CLKMODE_DPLL_SSC_TYPE_MASK
defines. Used for enabling spread spectrum.

Signed-off-by: Heiko Schocher 
Reviewed-by: Tom Rini 

---

Changes in v2:
- add Reviewed-by from Tom Rini

 arch/arm/include/asm/arch-am33xx/clock.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/include/asm/arch-am33xx/clock.h 
b/arch/arm/include/asm/arch-am33xx/clock.h
index a6d2419..7c6be4c 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -44,6 +44,9 @@
 /* CM_CLKMODE_DPLL */
 #define CM_CLKMODE_DPLL_SSC_EN_SHIFT   12
 #define CM_CLKMODE_DPLL_SSC_EN_MASK(1 << 12)
+#define CM_CLKMODE_DPLL_SSC_ACK_MASK   (1 << 13)
+#define CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK(1 << 14)
+#define CM_CLKMODE_DPLL_SSC_TYPE_MASK  (1 << 15)
 #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
 #define CM_CLKMODE_DPLL_REGM4XEN_MASK  (1 << 11)
 #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT10
-- 
2.5.5

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[U-Boot] [PATCH v2 00/12] am335x: add support for the am335x based bosch shc board

[Heiko Schocher]

This series adds support for the am335x based shc board from bosch.
There are no real new things, only two points:

- This board enables/uses the Spread Spectrum functionallity for
  the MPU.

- some board defconfigs have a bootdelay, others not, so move first
  the CONFIG_BOOTDELAY into a Kconfig option with the great tool
  moveconfig.py from Masahiro!

- Also found a "bug" in test/py, while testing, added this patch into
  this series, as I test the hole series with tbot, which calls also
  test/py/test.py.

$ ./tools/buildman/buildman arm -s
boards.cfg is up to date. Nothing to do.
Summary of current source for 568 boards (8 threads, 1 job per thread)
(no errors to report)
$

Tried to move some *_PARTITION defines to Kconfig, but failed
with SPL sizes ... this needs more investigation. I do not need
patch
http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/259522
anymore, as I fixed the size problem for this board through config
option.

rebased to current mainline, and there is a bug, patch:
http://patchwork.ozlabs.org/patch/624267/
fixes it.

Changes in v2:
- add comment from Viresh:
  remove strange ifdef after deleting CONFIG_BOOTDELAY
  This may change behaviour, but as the define CONFIG_SPEAR_USBTTY
  is not defined in mainline code, I think, it does not break
  mainlined boards.
- add comment from Tom Rini:
  set default value from CONFIG_BOOTDELAY to 2 seconds.
- add Reviewed-by from Tom Rini
- add Reviewed-by from Tom Rini
- add Reviewed-by from Tom Rini
- add Reviewed-by from Tom Rini
- add Reviewed-by from Tom Rini
- add Reviewed-by from Tom Rini
- add comment from Tom Rini:
  remove command in board code
  remove CONS_INDEX as we have the console fix on uart1
- rebased to current mainline commit:
  4b6e1fda107e5244e80ebc41865650ac2873dc88
  Merge git://git.denx.de/u-boot-dm
- prevent need of patch
  http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/259522

Heiko Schocher (12):
  common: bootdelay: move CONFIG_BOOTDELAY into a Kconfig  option
  tests: py: disable main_signon check for printenv cmd
  power, tps65217: add some defines
  arm, am335x: add some missing GPIO register definitions
  am335x: add some missing CM_CLKMODE_DPLL_SSC macros
  arm, am335x: Enable Spread Spectrum for the MPU
  bootstage: call show_boot_progress also in SPL
  mmc: revert mmc: Handle switch error status bit in MMC card status
  mmc: omap_hsmmc: enable 8bit interface for eMMC for AM33xx
  armv7: omap-common: make SPL board_mmc_init() weak
  doc, spl, am335x: update am335x-network
  am335x, shc: add support for the am335x based bosch shc board

 arch/arm/Kconfig   |   9 +
 arch/arm/cpu/armv7/am33xx/clock_am33xx.c   |  73 +++
 arch/arm/cpu/armv7/omap-common/boot-common.c   |   2 +-
 arch/arm/include/asm/arch-am33xx/clock.h   |   4 +
 arch/arm/include/asm/arch-am33xx/cpu.h |   5 +-
 board/bosch/shc/Kconfig|  87 +++
 board/bosch/shc/MAINTAINERS|  11 +
 board/bosch/shc/Makefile   |  10 +
 board/bosch/shc/README | 114 
 board/bosch/shc/board.c| 648 +
 board/bosch/shc/board.h| 187 ++
 board/bosch/shc/mux.c  | 261 +
 common/Kconfig |   9 +
 common/init/board_init.c   |   5 +
 common/spl/spl.c   |   5 +
 configs/B4420QDS_NAND_defconfig|   1 +
 configs/B4420QDS_SPIFLASH_defconfig|   1 +
 configs/B4420QDS_defconfig |   1 +
 configs/B4860QDS_NAND_defconfig|   1 +
 configs/B4860QDS_SECURE_BOOT_defconfig |   1 +
 configs/B4860QDS_SPIFLASH_defconfig|   1 +
 configs/B4860QDS_SRIO_PCIE_BOOT_defconfig  |   1 +
 configs/B4860QDS_defconfig |   1 +
 configs/BSC9131RDB_NAND_SYSCLK100_defconfig|   1 +
 configs/BSC9131RDB_NAND_defconfig  |   1 +
 configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig|   1 +
 configs/BSC9131RDB_SPIFLASH_defconfig  |   1 +
 configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig |   1 +
 configs/BSC9132QDS_NAND_DDRCLK100_defconfig|   1 +
 configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig |   1 +
 configs/BSC9132QDS_NAND_DDRCLK133_defconfig|   1 +
 configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig  |   1 +
 configs/BSC9132QDS_NOR_DDRCLK100_defconfig |   1 +
 configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig  |   1 +
 configs/BSC9132QDS_NOR_DDRCLK133_defconfig |   1 +
 .../BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig   |   1 +
 configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig  |   1 +
 .../BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig   |   1 +
 configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig  |   1 +
 

[U-Boot] [PATCH v2 02/12] tests: py: disable main_signon check for printenv cmd

[Heiko Schocher]

if CONFIG_VERSION_VARIABLE is set, the U-Boot environment
contains a "vers" variable with the current U-Boot version
string. If now "printenv" is called, test/py fails as it
detects the main_sign string, which is in this case correct.

So check only the main_sign as an error, if CONFIG_VERSION_VARIABLE
is not set.

Signed-off-by: Heiko Schocher 
---

Changes in v2: None

 test/py/tests/test_env.py | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/test/py/tests/test_env.py b/test/py/tests/test_env.py
index c41aa5a..22a22d1 100644
--- a/test/py/tests/test_env.py
+++ b/test/py/tests/test_env.py
@@ -39,7 +39,11 @@ class StateTestEnv(object):
 Nothing.
 """
 
-response = self.u_boot_console.run_command('printenv')
+if self.u_boot_console.config.buildconfig['config_version_variable'] 
== 'y':
+with self.u_boot_console.disable_check('main_signon'):
+response = self.u_boot_console.run_command('printenv')
+else:
+response = self.u_boot_console.run_command('printenv')
 self.env = {}
 for l in response.splitlines():
 if not '=' in l:
-- 
2.5.5

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Re: [U-Boot] [PATCH] driver/ddr/fsl: Force enabling parity for A-009803

[Shengzhou Liu]

> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Monday, May 23, 2016 11:33 PM
> To: Shengzhou Liu ; u-boot@lists.denx.de
> Subject: Re: [PATCH] driver/ddr/fsl: Force enabling parity for A-009803
> Shengzhou,
> 
> My point is you should force ap=1. Do you mean if ERRATUM_A009803 is
> enabled, users are forced to use address parity? That doesn't sound right.
> We have been running UDIMM without address parity for a long time.
> 
> York
> 
York,
My understanding is that ERRATUM_A009803 may still happen whatever ap_en is 
enabled or disabled. 
To apply the workaround of A009803, it requires ap_en is enabled. Is your 
understanding that if we
disable ap_en, ERRATUM_A009803 will never happen?  The CE document doesn't 
explain clearly this.
In last mail, did you mean we should force ap_en = 0 in case of A-009803?

Shengzhou
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[U-Boot] [PATCH v6 7/8] spl: fit: Do not print selected dtb during fit load

[Lokesh Vutla]

No prints should be allowed during UART load.

Reviewed-by: Tom Rini 
Signed-off-by: Lokesh Vutla 
---
 common/spl/spl_fit.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index fc03a6b..f8783d4 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -67,9 +67,7 @@ static int spl_fit_select_fdt(const void *fdt, int images, 
int *fdt_offsetp)
 
*fdt_offsetp = fdt_getprop_u32(fdt, fdt_node, "data-offset");
len = fdt_getprop_u32(fdt, fdt_node, "data-size");
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
-   printf("FIT: Selected '%s'\n", name);
-#endif
+   debug("FIT: Selected '%s'\n", name);
 
return len;
}
-- 
2.8.2

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[U-Boot] [PATCH v6 8/8] spl: Add an option to load a FIT containing U-Boot from UART

[Lokesh Vutla]

This provides a way to load a FIT containing U-Boot and a selection of device
tree files from UART.

Reviewed-by: Tom Rini 
Signed-off-by: Lokesh Vutla 
---
 common/spl/spl_ymodem.c | 98 ++---
 1 file changed, 84 insertions(+), 14 deletions(-)

diff --git a/common/spl/spl_ymodem.c b/common/spl/spl_ymodem.c
index 4f26ea5..5402301 100644
--- a/common/spl/spl_ymodem.c
+++ b/common/spl/spl_ymodem.c
@@ -14,15 +14,60 @@
 #include 
 #include 
 #include 
+#include 
 
 #define BUF_SIZE 1024
 
+/*
+ * Information required to load image using ymodem.
+ *
+ * @image_read: Now of bytes read from the image.
+ * @buf: pointer to the previous read block.
+ */
+struct ymodem_fit_info {
+   int image_read;
+   char *buf;
+};
+
 static int getcymodem(void) {
if (tstc())
return (getc());
return -1;
 }
 
+static ulong ymodem_read_fit(struct spl_load_info *load, ulong offset,
+ulong size, void *addr)
+{
+   int res, err;
+   struct ymodem_fit_info *info = load->priv;
+   char *buf = info->buf;
+
+   while (info->image_read < offset) {
+   res = xyzModem_stream_read(buf, BUF_SIZE, );
+   if (res <= 0)
+   return res;
+   info->image_read += res;
+   }
+
+   if (info->image_read > offset) {
+   res = info->image_read - offset;
+   memcpy(addr, [BUF_SIZE - res], res);
+   addr = addr + res;
+   }
+
+   while (info->image_read < offset + size) {
+   res = xyzModem_stream_read(buf, BUF_SIZE, );
+   if (res <= 0)
+   return res;
+
+   memcpy(addr, buf, res);
+   info->image_read += res;
+   addr += res;
+   }
+
+   return size;
+}
+
 int spl_ymodem_load_image(void)
 {
int size = 0;
@@ -31,30 +76,55 @@ int spl_ymodem_load_image(void)
int ret;
connection_info_t info;
char buf[BUF_SIZE];
-   ulong store_addr = ~0;
ulong addr = 0;
 
info.mode = xyzModem_ymodem;
ret = xyzModem_stream_open(, );
+   if (ret) {
+   printf("spl: ymodem err - %s\n", xyzModem_error(err));
+   return ret;
+   }
+
+   res = xyzModem_stream_read(buf, BUF_SIZE, );
+   if (res <= 0)
+   goto end_stream;
+
+   if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+   image_get_magic((struct image_header *)buf) == FDT_MAGIC) {
+   struct spl_load_info load;
+   struct ymodem_fit_info info;
+
+   debug("Found FIT\n");
+   load.dev = NULL;
+   load.priv = (void *)
+   load.filename = NULL;
+   load.bl_len = 1;
+   info.buf = buf;
+   info.image_read = BUF_SIZE;
+   load.read = ymodem_read_fit;
+   ret =  spl_load_simple_fit(, 0, (void *)buf);
+   size = info.image_read;
 
-   if (!ret) {
-   while ((res =
-   xyzModem_stream_read(buf, BUF_SIZE, )) > 0) {
-   if (addr == 0) {
-   ret = spl_parse_image_header((struct 
image_header *)buf);
-   if (ret)
-   return ret;
-   }
-   store_addr = addr + spl_image.load_addr;
+   while ((res = xyzModem_stream_read(buf, BUF_SIZE, )) > 0)
+   size += res;
+   } else {
+   spl_parse_image_header((struct image_header *)buf);
+   ret = spl_parse_image_header((struct image_header *)buf);
+   if (ret)
+   return ret;
+   addr = spl_image.load_addr;
+   memcpy((void *)addr, buf, res);
+   size += res;
+   addr += res;
+
+   while ((res = xyzModem_stream_read(buf, BUF_SIZE, )) > 0) {
+   memcpy((void *)addr, buf, res);
size += res;
addr += res;
-   memcpy((char *)(store_addr), buf, res);
}
-   } else {
-   printf("spl: ymodem err - %s\n", xyzModem_error(err));
-   return ret;
}
 
+end_stream:
xyzModem_stream_close();
xyzModem_stream_terminate(false, );
 
-- 
2.8.2

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[U-Boot] [PATCH v6 6/8] spl: Support loading a FIT from NAND

[Lokesh Vutla]

Detect a FIT when loading from NAND and handle it using the
new FIT SPL support.

Reviewed-by: Tom Rini 
Signed-off-by: Lokesh Vutla 
---
 common/spl/spl_nand.c | 37 -
 1 file changed, 32 insertions(+), 5 deletions(-)

diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c
index bbd9546..86437b3 100644
--- a/common/spl/spl_nand.c
+++ b/common/spl/spl_nand.c
@@ -9,6 +9,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 #if defined(CONFIG_SPL_NAND_RAW_ONLY)
 int spl_nand_load_image(void)
@@ -24,6 +26,19 @@ int spl_nand_load_image(void)
return 0;
 }
 #else
+
+static ulong spl_nand_fit_read(struct spl_load_info *load, ulong offs,
+  ulong size, void *dst)
+{
+   int ret;
+
+   ret = nand_spl_load_image(offs, size, dst);
+   if (!ret)
+   return size;
+   else
+   return 0;
+}
+
 static int spl_nand_load_element(int offset, struct image_header *header)
 {
int err;
@@ -32,12 +47,24 @@ static int spl_nand_load_element(int offset, struct 
image_header *header)
if (err)
return err;
 
-   err = spl_parse_image_header(header);
-   if (err)
-   return err;
+   if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+   image_get_magic(header) == FDT_MAGIC) {
+   struct spl_load_info load;
 
-   return nand_spl_load_image(offset, spl_image.size,
-  (void *)(unsigned long)spl_image.load_addr);
+   debug("Found FIT\n");
+   load.dev = NULL;
+   load.priv = NULL;
+   load.filename = NULL;
+   load.bl_len = 1;
+   load.read = spl_nand_fit_read;
+   return spl_load_simple_fit(, offset, header);
+   } else {
+   err = spl_parse_image_header(header);
+   if (err)
+   return err;
+   return nand_spl_load_image(offset, spl_image.size,
+  (void *)spl_image.load_addr);
+   }
 }
 
 int spl_nand_load_image(void)
-- 
2.8.2

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[U-Boot] [PATCH v6 3/8] spl: Support loading a FIT from FAT FS

[Lokesh Vutla]

Detect a FIT when loading from a FAT File system and handle it using the
new FIT SPL support.

Tested-by: Michal Simek 
Reviewed-by: Simon Glass 
Reviewed-by: Tom Rini 
Signed-off-by: Lokesh Vutla 
---
 common/spl/spl_fat.c | 36 
 1 file changed, 32 insertions(+), 4 deletions(-)

diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c
index 5b0d969..db67618 100644
--- a/common/spl/spl_fat.c
+++ b/common/spl/spl_fat.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 
 static int fat_registered;
 
@@ -39,6 +40,20 @@ static int spl_register_fat_device(struct blk_desc 
*block_dev, int partition)
return err;
 }
 
+static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset,
+ ulong size, void *buf)
+{
+   loff_t actread;
+   int ret;
+   char *filename = (char *)load->filename;
+
+   ret = fat_read_file(filename, buf, file_offset, size, );
+   if (ret)
+   return ret;
+
+   return actread;
+}
+
 int spl_load_image_fat(struct blk_desc *block_dev,
int partition,
const char *filename)
@@ -57,11 +72,24 @@ int spl_load_image_fat(struct blk_desc *block_dev,
if (err <= 0)
goto end;
 
-   err = spl_parse_image_header(header);
-   if (err)
-   goto end;
+   if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+   image_get_magic(header) == FDT_MAGIC) {
+   struct spl_load_info load;
+
+   debug("Found FIT\n");
+   load.read = spl_fit_read;
+   load.bl_len = 1;
+   load.filename = (void *)filename;
+   load.priv = NULL;
 
-   err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0);
+   return spl_load_simple_fit(, 0, header);
+   } else {
+   err = spl_parse_image_header(header);
+   if (err)
+   goto end;
+
+   err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0);
+   }
 
 end:
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
-- 
2.8.2

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[U-Boot] [PATCH v6 4/8] spl: Support loading a FIT from SPI

[Lokesh Vutla]

Detect a FIT when loading from SPI and handle it using the
new FIT SPL support.

Reviewed-by: Tom Rini 
Signed-off-by: Lokesh Vutla 
---
 drivers/mtd/spi/spi_spl_load.c | 37 -
 1 file changed, 32 insertions(+), 5 deletions(-)

diff --git a/drivers/mtd/spi/spi_spl_load.c b/drivers/mtd/spi/spi_spl_load.c
index 46c98a9..bac1e85 100644
--- a/drivers/mtd/spi/spi_spl_load.c
+++ b/drivers/mtd/spi/spi_spl_load.c
@@ -48,6 +48,18 @@ static int spi_load_image_os(struct spi_flash *flash,
 }
 #endif
 
+static ulong spl_spi_fit_read(struct spl_load_info *load, ulong sector,
+ ulong count, void *buf)
+{
+   struct spi_flash *flash = load->dev;
+   ulong ret;
+
+   ret = spi_flash_read(flash, sector, count, buf);
+   if (!ret)
+   return count;
+   else
+   return 0;
+}
 /*
  * The main entry for SPI booting. It's necessary that SDRAM is already
  * configured and available since this code loads the main U-Boot image
@@ -85,11 +97,26 @@ int spl_spi_load_image(void)
if (err)
return err;
 
-   err = spl_parse_image_header(header);
-   if (err)
-   return err;
-   err = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS,
-  spl_image.size, (void *)spl_image.load_addr);
+   if (IS_ENABLED(CONFIG_SPL_LOAD_FIT)) {
+   struct spl_load_info load;
+
+   debug("Found FIT\n");
+   load.dev = flash;
+   load.priv = NULL;
+   load.filename = NULL;
+   load.bl_len = 1;
+   load.read = spl_spi_fit_read;
+   err = spl_load_simple_fit(,
+ CONFIG_SYS_SPI_U_BOOT_OFFS,
+ header);
+   } else {
+   err = spl_parse_image_header(header);
+   if (err)
+   return err;
+   err = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS,
+spl_image.size,
+(void *)spl_image.load_addr);
+   }
}
 
return err;
-- 
2.8.2

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[U-Boot] [PATCH v6 5/8] mtd: nand: am335x: spl: Fix copying of image

[Lokesh Vutla]

When offset is not aligned to page address, it is possible that extra offset
will be read from nand. Adjust the image such that first byte of the image
is at load address after the first page is read.

Reviewed-by: Tom Rini 
Signed-off-by: Lokesh Vutla 
---
 drivers/mtd/nand/am335x_spl_bch.c | 15 ++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/am335x_spl_bch.c 
b/drivers/mtd/nand/am335x_spl_bch.c
index bf8b2ee..31c7825 100644
--- a/drivers/mtd/nand/am335x_spl_bch.c
+++ b/drivers/mtd/nand/am335x_spl_bch.c
@@ -173,7 +173,7 @@ static int nand_read_page(int block, int page, void *dst)
 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
 {
unsigned int block, lastblock;
-   unsigned int page;
+   unsigned int page, page_offset;
 
/*
 * offs has to be aligned to a page address!
@@ -181,6 +181,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, 
void *dst)
block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
+   page_offset = offs % CONFIG_SYS_NAND_PAGE_SIZE;
 
while (block <= lastblock) {
if (!nand_is_bad_block(block)) {
@@ -189,6 +190,18 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, 
void *dst)
 */
while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
nand_read_page(block, page, dst);
+   /*
+* When offs is not aligned to page address the
+* extra offset is copied to dst as well. Copy
+* the image such that its first byte will be
+* at the dst.
+*/
+   if (unlikely(page_offset)) {
+   memmove(dst, dst + page_offset,
+   CONFIG_SYS_NAND_PAGE_SIZE);
+   dst = (void *)((int)dst - page_offset);
+   page_offset = 0;
+   }
dst += CONFIG_SYS_NAND_PAGE_SIZE;
page++;
}
-- 
2.8.2

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[U-Boot] [PATCH v6 2/8] spl: Allow to load a FIT containing U-Boot from FS

[Lokesh Vutla]

This provides a way to load a FIT containing U-Boot and a selection of device
tree files from a File system. Making sure that all the reads and writes
are aligned to their respective needs.

Tested-by: Michal Simek 
Reviewed-by: Simon Glass 
Reviewed-by: Tom Rini 
Signed-off-by: Lokesh Vutla 
---
 common/spl/spl_fit.c | 76 +---
 common/spl/spl_mmc.c |  1 +
 include/spl.h| 12 +
 3 files changed, 74 insertions(+), 15 deletions(-)

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index e5c7ea2..fc03a6b 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -87,6 +87,42 @@ static int spl_fit_select_fdt(const void *fdt, int images, 
int *fdt_offsetp)
return -ENOENT;
 }
 
+static int get_aligned_image_offset(struct spl_load_info *info, int offset)
+{
+   /*
+* If it is a FS read, get the first address before offset which is
+* aligned to ARCH_DMA_MINALIGN. If it is raw read return the
+* block number to which offset belongs.
+*/
+   if (info->filename)
+   return offset & ~(ARCH_DMA_MINALIGN - 1);
+
+   return offset / info->bl_len;
+}
+
+static int get_aligned_image_overhead(struct spl_load_info *info, int offset)
+{
+   /*
+* If it is a FS read, get the difference between the offset and
+* the first address before offset which is aligned to
+* ARCH_DMA_MINALIGN. If it is raw read return the offset within the
+* block.
+*/
+   if (info->filename)
+   return offset & (ARCH_DMA_MINALIGN - 1);
+
+   return offset % info->bl_len;
+}
+
+static int get_aligned_image_size(struct spl_load_info *info, int data_size,
+ int offset)
+{
+   if (info->filename)
+   return data_size + get_aligned_image_overhead(info, offset);
+
+   return (data_size + info->bl_len - 1) / info->bl_len;
+}
+
 int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit)
 {
int sectors;
@@ -96,7 +132,7 @@ int spl_load_simple_fit(struct spl_load_info *info, ulong 
sector, void *fit)
void *load_ptr;
int fdt_offset, fdt_len;
int data_offset, data_size;
-   int base_offset;
+   int base_offset, align_len;
int src_sector;
void *dst;
 
@@ -122,8 +158,10 @@ int spl_load_simple_fit(struct spl_load_info *info, ulong 
sector, void *fit)
 * In fact the FIT has its own load address, but we assume it cannot
 * be before CONFIG_SYS_TEXT_BASE.
 */
-   fit = (void *)(CONFIG_SYS_TEXT_BASE - size - info->bl_len);
-   sectors = (size + info->bl_len - 1) / info->bl_len;
+   align_len = ARCH_DMA_MINALIGN - 1;
+   fit = (void *)((CONFIG_SYS_TEXT_BASE - size - info->bl_len -
+   align_len) & ~align_len);
+   sectors = get_aligned_image_size(info, size, 0);
count = info->read(info, sector, sectors, fit);
debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu\n",
  sector, sectors, fit, count);
@@ -156,19 +194,23 @@ int spl_load_simple_fit(struct spl_load_info *info, ulong 
sector, void *fit)
 * byte will be at 'load'. This may mean we need to load it starting
 * before then, since we can only read whole blocks.
 */
-   sectors = (data_size + info->bl_len - 1) / info->bl_len;
data_offset += base_offset;
+   sectors = get_aligned_image_size(info, data_size, data_offset);
load_ptr = (void *)load;
debug("U-Boot size %x, data %p\n", data_size, load_ptr);
-   dst = load_ptr - (data_offset % info->bl_len);
+   dst = load_ptr;
 
/* Read the image */
-   src_sector = sector + data_offset / info->bl_len;
-   debug("image: data_offset=%x, dst=%p, src_sector=%x, sectors=%x\n",
- data_offset, dst, src_sector, sectors);
+   src_sector = sector + get_aligned_image_offset(info, data_offset);
+   debug("Aligned image read: dst=%p, src_sector=%x, sectors=%x\n",
+ dst, src_sector, sectors);
count = info->read(info, src_sector, sectors, dst);
if (count != sectors)
return -EIO;
+   debug("image: dst=%p, data_offset=%x, size=%x\n", dst, data_offset,
+ data_size);
+   memcpy(dst, dst + get_aligned_image_overhead(info, data_offset),
+  data_size);
 
/* Figure out which device tree the board wants to use */
fdt_len = spl_fit_select_fdt(fit, images, _offset);
@@ -178,14 +220,15 @@ int spl_load_simple_fit(struct spl_load_info *info, ulong 
sector, void *fit)
/*
 * Read the device tree and place it after the image. There may be
 * some extra data before it since we can only read entire blocks.
+* And also align the destination address to ARCH_DMA_MINALIGN.
 */
-  

[U-Boot] [PATCH v6 0/8] spl: Support loading FIT from various boot media

[Lokesh Vutla]

This series supports loading FIT from FS, nand, spi, uart.
It consolidates all the previously post FIT support patches and rebased on
top of mainline. Patch [1] and [2] got merged.

[1] http://patchwork.ozlabs.org/patch/618403/
[2] http://patchwork.ozlabs.org/patch/623919/

Verified all these boot modes on TI platforms.

Lokesh Vutla (8):
  spl: fit: Fix the number of bytes read when reading fdt from fit
  spl: Allow to load a FIT containing U-Boot from FS
  spl: Support loading a FIT from FAT FS
  spl: Support loading a FIT from SPI
  mtd: nand: am335x: spl: Fix copying of image
  spl: Support loading a FIT from NAND
  spl: fit: Do not print selected dtb during fit load
  spl: Add an option to load a FIT containing U-Boot from UART

 common/spl/spl_fat.c  | 36 --
 common/spl/spl_fit.c  | 79 ---
 common/spl/spl_mmc.c  |  1 +
 common/spl/spl_nand.c | 37 +--
 common/spl/spl_ymodem.c   | 98 +--
 drivers/mtd/nand/am335x_spl_bch.c | 15 +-
 drivers/mtd/spi/spi_spl_load.c| 37 +--
 include/spl.h | 12 +
 8 files changed, 269 insertions(+), 46 deletions(-)

-- 
2.8.2

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[U-Boot] [PATCH v6 1/8] spl: fit: Fix the number of bytes read when reading fdt from fit

[Lokesh Vutla]

sectors field is not being updated when reading fdt from fit image. Because of
this size_of(u-boot.bin) is being read when reading fdt. Fixing it by updating
the sectors field properly.

Tested-by: Michal Simek 
Reviewed-by: Simon Glass 
Reviewed-by: Tom Rini 
Signed-off-by: Lokesh Vutla 
---
 common/spl/spl_fit.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 26842ba..e5c7ea2 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -181,6 +181,7 @@ int spl_load_simple_fit(struct spl_load_info *info, ulong 
sector, void *fit)
 */
dst = load_ptr + data_size;
fdt_offset += base_offset;
+   sectors = (fdt_len + info->bl_len - 1) / info->bl_len;
count = info->read(info, sector + fdt_offset / info->bl_len, sectors,
   dst);
debug("fit read %x sectors to %x, dst %p, data_offset %x\n",
-- 
2.8.2

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Re: [U-Boot] [PATCH v5 02/12] spi: davinci_spi: Convert to driver to adapt to DM

[Vignesh R]

On 05/20/2016 08:54 PM, Simon Glass wrote:
> Hi Vignesh,
> 
> On 19 May 2016 at 23:01, Vignesh R  wrote:
>>
>> Convert davinci_spi driver so that it complies with SPI DM framework.
>>
>> Signed-off-by: Vignesh R 
>> Reviewed-by: Tom Rini 
>> ---
>>
>> v5: correct error message.
>>
>> v4: Check error returned by dev_map_physmem().
>>
>> v3: No changes
>>
>> v2: Add comments to struct davinci_spi_slave members.
>> Use dev_map_physmem() added by previous patch.
>>
>>  drivers/spi/davinci_spi.c | 329 
>> +-
>>  1 file changed, 240 insertions(+), 89 deletions(-)
> 
> Sorry I missed something below.
> [snip]
> 
>> +static int davinci_ofdata_to_platadata(struct udevice *bus)
>> +{
>> +   struct davinci_spi_slave *ds = dev_get_priv(bus);
>> +   const void *blob = gd->fdt_blob;
>> +   int node = bus->of_offset;
>> +
>> +   ds->regs = dev_map_physmem(bus, sizeof(struct davinci_spi_regs));
>> +   if (!ds->regs) {
>> +   printf("%s: could not map device address\n", __func__);
>> +   return -ENODEV;
> 
> -EINVAL
> 
> We use -ENODEV to say there is no device. Here, we have a device but
> the configuration is wrong.

Ok, I posted in v6 with above change.


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[U-Boot] [PATCH v6 02/12] spi: davinci_spi: Convert to driver to adapt to DM

[Vignesh R]

Convert davinci_spi driver so that it complies with SPI DM framework.

Signed-off-by: Vignesh R 
---

v6: Fix retval on dev_map_physmem() failure.

 drivers/spi/davinci_spi.c | 329 +-
 1 file changed, 240 insertions(+), 89 deletions(-)

diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
index 0bd4f88926f1..20aa99a451dc 100644
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 
 /* SPIGCR0 */
 #define SPIGCR0_SPIENA_MASK0x1
@@ -51,6 +52,7 @@
 /* SPIDEF */
 #define SPIDEF_CSDEF0_MASK BIT(0)
 
+#ifndef CONFIG_DM_SPI
 #define SPI0_BUS   0
 #define SPI0_BASE  CONFIG_SYS_SPI_BASE
 /*
@@ -83,6 +85,9 @@
 #define SPI2_NUM_CSCONFIG_SYS_SPI2_NUM_CS
 #define SPI2_BASE  CONFIG_SYS_SPI2_BASE
 #endif
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
 
 /* davinci spi register set */
 struct davinci_spi_regs {
@@ -114,16 +119,17 @@ struct davinci_spi_regs {
 
 /* davinci spi slave */
 struct davinci_spi_slave {
+#ifndef CONFIG_DM_SPI
struct spi_slave slave;
+#endif
struct davinci_spi_regs *regs;
-   unsigned int freq;
+   unsigned int freq; /* current SPI bus frequency */
+   unsigned int mode; /* current SPI mode used */
+   u8 num_cs; /* total no. of CS available */
+   u8 cur_cs; /* CS of current slave */
+   bool half_duplex;  /* true, if master is half-duplex only */
 };
 
-static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave)
-{
-   return container_of(slave, struct davinci_spi_slave, slave);
-}
-
 /*
  * This functions needs to act like a macro to avoid pipeline reloads in the
  * loops below. Use always_inline. This gains us about 160KiB/s and the bloat
@@ -144,15 +150,14 @@ static inline u32 davinci_spi_xfer_data(struct 
davinci_spi_slave *ds, u32 data)
return buf_reg_val;
 }
 
-static int davinci_spi_read(struct spi_slave *slave, unsigned int len,
+static int davinci_spi_read(struct davinci_spi_slave *ds, unsigned int len,
u8 *rxp, unsigned long flags)
 {
-   struct davinci_spi_slave *ds = to_davinci_spi(slave);
unsigned int data1_reg_val;
 
/* enable CS hold, CS[n] and clear the data bits */
data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
-(slave->cs << SPIDAT1_CSNR_SHIFT));
+(ds->cur_cs << SPIDAT1_CSNR_SHIFT));
 
/* wait till TXFULL is deasserted */
while (readl(>regs->buf) & SPIBUF_TXFULL_MASK)
@@ -175,15 +180,14 @@ static int davinci_spi_read(struct spi_slave *slave, 
unsigned int len,
return 0;
 }
 
-static int davinci_spi_write(struct spi_slave *slave, unsigned int len,
+static int davinci_spi_write(struct davinci_spi_slave *ds, unsigned int len,
 const u8 *txp, unsigned long flags)
 {
-   struct davinci_spi_slave *ds = to_davinci_spi(slave);
unsigned int data1_reg_val;
 
/* enable CS hold and clear the data bits */
data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
-(slave->cs << SPIDAT1_CSNR_SHIFT));
+(ds->cur_cs << SPIDAT1_CSNR_SHIFT));
 
/* wait till TXFULL is deasserted */
while (readl(>regs->buf) & SPIBUF_TXFULL_MASK)
@@ -209,16 +213,15 @@ static int davinci_spi_write(struct spi_slave *slave, 
unsigned int len,
return 0;
 }
 
-#ifndef CONFIG_SPI_HALF_DUPLEX
-static int davinci_spi_read_write(struct spi_slave *slave, unsigned int len,
- u8 *rxp, const u8 *txp, unsigned long flags)
+static int davinci_spi_read_write(struct davinci_spi_slave *ds, unsigned
+ int len, u8 *rxp, const u8 *txp,
+ unsigned long flags)
 {
-   struct davinci_spi_slave *ds = to_davinci_spi(slave);
unsigned int data1_reg_val;
 
/* enable CS hold and clear the data bits */
data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
-(slave->cs << SPIDAT1_CSNR_SHIFT));
+(ds->cur_cs << SPIDAT1_CSNR_SHIFT));
 
/* wait till TXFULL is deasserted */
while (readl(>regs->buf) & SPIBUF_TXFULL_MASK)
@@ -237,7 +240,115 @@ static int davinci_spi_read_write(struct spi_slave 
*slave, unsigned int len,
 
return 0;
 }
-#endif
+
+
+static int __davinci_spi_claim_bus(struct davinci_spi_slave *ds, int cs)
+{
+   unsigned int mode = 0, scalar;
+
+   /* Enable the SPI hardware */
+   writel(SPIGCR0_SPIRST_MASK, >regs->gcr0);
+   udelay(1000);
+   writel(SPIGCR0_SPIENA_MASK, >regs->gcr0);
+
+   /* Set master mode, powered up and not activated */
+   writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, >regs->gcr1);
+
+   /* CS, CLK, SIMO and SOMI are functional pins */
+   writel(((1 << cs) | 

Re: [U-Boot] [PATCH v2 00/25] exynos: video: Convert exynos LCD driver to use driver model

[Jaehoon Chung]

Hi All,

On 05/24/2016 05:18 AM, Simon Glass wrote:
> Hi Minkyu,
> 
> On 16 May 2016 at 22:38, Minkyu Kang  wrote:
>> Hi,
>>
>> On 17/05/16 13:22, Jaehoon Chung wrote:
>>> Hi Simon.
>>>
>>> On 05/15/2016 06:22 AM, Simon Glass wrote:
 Hi Jaehoon,

 On 13 May 2016 at 07:09, Jaehoon Chung  wrote:
> Hi Simon,
>
> On 05/09/2016 08:00 PM, Minkyu Kang wrote:
>> Hi Jaehoon,
>>
>> On 08/05/16 06:25, Simon Glass wrote:
>>> Hi,
>>>
>>> On 1 March 2016 at 18:51, Minkyu Kang  wrote:
 Hi,

 On 29/02/16 16:18, Jaehoon Chung wrote:
> Hi,
>
> On 02/29/2016 01:23 PM, Simon Glass wrote:
>> Hi,
>>
>> On 23 February 2016 at 05:04, Minkyu Kang  
>> wrote:
>>> Dear Simon Glass,
>>>
>>> On 23/02/16 15:42, Simon Glass wrote:
 Hi Minkyu,

 On 21 February 2016 at 21:08, Simon Glass  
 wrote:
>
> This series converts the exynos LCD driver to work with driver 
> model. Only
> the eDP display is converted - the MIPI display is left mostly 
> alone as I
> do not have a device to test with.
>
> The conversion involves some refactoring to simplify the code, 
> reduce the
> amount of global/static data and allow boards to be built without 
> LCD
> support.
>
> The series is tested with snow, spring, pit and pi. It disables 
> LCD on other
> exynos boards so that they will still build with these changes. 
> Further work
> will be needed (by someone with a board) to convert the others. I 
> am not
> sure when this series can be applied.
>
> The series also brings in device tree features from Linux v4.4. 
> It would be
> useful to do a full sync with the kernel on these files, but this 
> is really
> a job for the Samsung maintainer :-)
>
> The series is available at u-boot-dm/rkg-working.
>
> Changes in v2:
> - Rebase to master
> - Rebase to master
>

 What do you think we should do about applying this series?

>>>
>>> Although we have to do remaining work, I think applying is possible 
>>> without next work.
>>>
>>> Board maintainers, what do you think?
>>>
>>> Remaining Work:
>>> - MIPI display driver
>>> - s5pc210_universal
>>> - smdk5420
>>> - smdk5250
>>> - trats
>>> - trats2
>>>
>>> Thanks,
>>> Minkyu Kang.
>>
>> Well, no replies as yet. The main work requires is MIPI, but as I
>> don't have the hardware, I can't help with that. At least I have made
>> sure that everything builds OK.
>
> Sorry for late..I will check these patches on this week..Tomorrow is 
> holiday..
> So I can check from Wed.

 Thank you, Jaehoon.
>>>
>>> It has been a few months now - if you like I can apply these via the 
>>> -dm tree.
>
> Yep, I checked these..It needs to remain the future work.
> But it seems that it's not problem to apply at -dm repository.
> (I have checked with your patch on other boadrs.)
>
> I needs to check one more things..Could you wait until next Tuesday?
>

 Sure, it's been 3 months so another week won't matter :-)
>>>
>>> Sorry. I have checked more with these patches..We have to work too many 
>>> things in future for remaining work.
>>> But it seems those task are our role..If you and Minkyu are ok, you can 
>>> apply these at dm repository.
>>
>> I'm OK.
>> If you want, those can be merged to samsung tree.
> 
> Thanks, please go ahead!

Then I will work on remaining task with that branch..

Best Regards,
Jaehoon Chung

> 
>>
>>>
>>> I will make a plan to work. (Based on your repository.)
>>>
>>> Actually, i didn't follow a few month, so i'm looking for u-boot history. 
>>> Sorry. :(
>>> If you want to add my Reviewed-by tag, then you can add.
>>>
>>> In future work,
>>> Change to driver model for above targets. (trats2/trats...)
>>> MIPI display driver..(I will assign to my colleague for this task.)
> 
> Regards,
> Simon
> 
> 
> 

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Re: [U-Boot] [PATCH 00/21] tools: moveconfig: many fixes, improvements, code clean-ups

[Masahiro Yamada]

2016-05-24 7:13 GMT+09:00 Tom Rini :
> On Thu, May 19, 2016 at 03:51:48PM +0900, Masahiro Yamada wrote:
>
>> Masahiro Yamada (21):
>>   tools: moveconfig: fix --dry-run option
>>   tools: moveconfig: rename update_defconfig() to update_dotconfig()
>>   tools: moveconfig: remove redundant else: after sys.exit()
>>   tools: moveconfig: check directory relocation before compilers
>>   tools: moveconfig: check compilers before starting defconfig walk
>>   tools: moveconfig: exit with error message for not clean directory
>>   tools: moveconfig: increment number of processed files monotonically
>>   tools: moveconfig: do not rely on type and default value given by
>> users
>>   tools: moveconfig: drop code for handling type and default value
>>   tools: moveconfig: allow to give CONFIG names as argument directly
>>   tools: moveconfig: add --undef option to move CONFIGs with default y
>>   tools: moveconfig: compute file paths just once
>>   tools: moveconfig: move log output code out of Kconfig Parser class
>>   tools: moveconfig: display log atomically in more readable format
>>   tools: moveconfig: refactor code to go back to idle state
>>   tools: moveconfig: skip savedefconfig if .config was not updated
>>   tools: moveconfig: display log when savedefconfig occurs
>>   tools: moveconfig: report when CONFIGs are removed by savedefconfig
>>   tools: moveconfig: report when defconfig is updated
>>   tools: moveconfig: add --force-sync option
>>   tools: moveconfig: allow to run without any CONFIG specified
>>
>>  scripts/Makefile.autoconf |   3 +-
>>  tools/moveconfig.py   | 621 
>> +-
>>  2 files changed, 339 insertions(+), 285 deletions(-)
>
> Assuming no comments come up, please feel free to throw this into a
> branch in the uniphier repository for me to pick up, thanks!
>

OK, I will wait a few days more in case somebody
is interested in this series,
then apply it.



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Re: [U-Boot] [U-Boot, v2] ARM: fix ifdef in ARMv8 lowlevel_init() again

[Tom Rini]

On Fri, May 20, 2016 at 12:13:10PM +0900, Masahiro Yamada wrote:

> Commit 116611937faa ("ARM: fix ifdefs in ARMv8 lowlevel_init()")
> accidentally inverted the logic of CONFIG_ARMV8_MULTIENTRY.
> 
> Fixes: 116611937faa ("ARM: fix ifdefs in ARMv8 lowlevel_init()")
> Signed-off-by: Masahiro Yamada 
> Reviewed-by: Stephen Warren 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v2] omap3: Fix SPI registers on am33xx and am43xx

[Tom Rini]

On Thu, May 19, 2016 at 09:11:58AM +0200, Martin Hejnfelt wrote:

> When the base registers are read from device tree the base is not
> 0x48030100 as the driver expects, but 0x4803, resulting in
> non functioning SPI. To deal with this, use same idea as how this
> is done in the linux kernel (drivers/spi/spi-omap2-mcspi.c) and
> add a structure with a field that is used to shift the registers
> on these systems.
> 
> v2: Fixed commit subject line to correct cpu
> 
> Signed-off-by: Martin Hejnfelt 

Applied to u-boot/master, thanks!

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Re: [U-Boot] SPL: fat: Fix spl_parse_image_header() return value handling

[Tom Rini]

On Fri, May 20, 2016 at 01:45:24AM +0200, Marek Vasut wrote:

> The spl_parse_image_header() can return 0 and it is not an error.
> Only treat non-zero return value as an error.
> 
> Signed-off-by: Marek Vasut 
> Cc: Fabio Estevam 
> Cc: Peng Fan 
> Cc: Stefano Babic 
> Cc: Tom Rini 
> Reviewed-by: Fabio Estevam 
> Reviewed-by: Peng Fan 
> Reviewed-by: Stefano Babic 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] kbuild: fixdep: Check fstat(2) return value

[Tom Rini]

On Fri, May 13, 2016 at 10:54:04AM -0400, Tom Rini wrote:

> Coverity has recently added a check that will find when we don't check
> the return code from fstat(2).  Copy/paste the checking logic that
> print_deps() has with an appropriate re-wording of the perror() message.
> 
> [ Linux commit : 46fe94ad18aa7ce6b3dad8c035fb538942020f2b ]
> 
> Signed-off-by: Tom Rini 
> Signed-off-by: Michal Marek 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot,RFC] spl: Setup default value for OF_LIST

[Tom Rini]

On Wed, May 04, 2016 at 03:14:11PM +0200, Michal Simek wrote:

> OF_LIST can't remain empty that's why setup it up to default DTB.
> 
> If it is empty u-boot.img is created without FDT partition:
> For example:
>   ./tools/mkimage -f auto -A arm -T firmware -C none -O u-boot -a
> 0x800 -e 0 -n "U-Boot 2016.05-rc3 ..." -E -b  -d u-boot-nodtb.bin 
> u-boot.img
> Can't set 'timestamp' property for '' node (FDT_ERR_NOSPACE)
> FIT description: Firmware image with one or more FDT blobs
> Created: Wed May  4 15:02:52 2016
>  Image 0 (firmware@1)
>   Description:  U-Boot 2016.05-rc3-00080-gff2e12ae22a8-dirty for zynqmp
> board
>   Created:  Wed May  4 15:02:52 2016
>   Type: Firmware
>   Compression:  uncompressed
>   Data Size:unavailable
>   Architecture: ARM
>   Load Address: 0x0800
>  Default Configuration: 'conf@1'
>  Configuration 0 (conf@1)
>   Description:  unavailable
>   Kernel:   unavailable
> 
> And then image like this doesn't contain description and link to FDT and
> can't boot.
> 
> Signed-off-by: Michal Simek 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, 1/2] image-fit: Don't display an error in fit_set_timestamp()

[Tom Rini]

On Sun, May 01, 2016 at 01:55:37PM -0600, Simon Glass wrote:

> This function returns an error code and its caller may be able to fix the
> error. For example fit_handle_file() expands the device tree to fit if there
> is a lack of space.
> 
> In this case the caller does not want an error displayed. It is confusing,
> since it suggests that something is wrong, when it fact everything is fine.
> Drop the error.
> 
> Signed-off-by: Simon Glass 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH 00/21] tools: moveconfig: many fixes, improvements, code clean-ups

[Tom Rini]

On Thu, May 19, 2016 at 03:51:48PM +0900, Masahiro Yamada wrote:

> Masahiro Yamada (21):
>   tools: moveconfig: fix --dry-run option
>   tools: moveconfig: rename update_defconfig() to update_dotconfig()
>   tools: moveconfig: remove redundant else: after sys.exit()
>   tools: moveconfig: check directory relocation before compilers
>   tools: moveconfig: check compilers before starting defconfig walk
>   tools: moveconfig: exit with error message for not clean directory
>   tools: moveconfig: increment number of processed files monotonically
>   tools: moveconfig: do not rely on type and default value given by
> users
>   tools: moveconfig: drop code for handling type and default value
>   tools: moveconfig: allow to give CONFIG names as argument directly
>   tools: moveconfig: add --undef option to move CONFIGs with default y
>   tools: moveconfig: compute file paths just once
>   tools: moveconfig: move log output code out of Kconfig Parser class
>   tools: moveconfig: display log atomically in more readable format
>   tools: moveconfig: refactor code to go back to idle state
>   tools: moveconfig: skip savedefconfig if .config was not updated
>   tools: moveconfig: display log when savedefconfig occurs
>   tools: moveconfig: report when CONFIGs are removed by savedefconfig
>   tools: moveconfig: report when defconfig is updated
>   tools: moveconfig: add --force-sync option
>   tools: moveconfig: allow to run without any CONFIG specified
> 
>  scripts/Makefile.autoconf |   3 +-
>  tools/moveconfig.py   | 621 
> +-
>  2 files changed, 339 insertions(+), 285 deletions(-)

Assuming no comments come up, please feel free to throw this into a
branch in the uniphier repository for me to pick up, thanks!

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Re: [U-Boot] spl: fit: Print error message when FDT is not present

[Tom Rini]

On Wed, May 04, 2016 at 03:08:00PM +0200, Michal Simek wrote:

> When FDT is not present in the image user doesn't get any error what's
> wrong. Print error message if LIBCOMMON_SUPPORT is enabled.
> 
> Signed-off-by: Michal Simek 
> Seris-cc: uboot
> Reviewed-by: Tom Rini 
> Reviewed-by: Simon Glass 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot,2/2] mkimage: Add a quiet mode

[Tom Rini]

On Sun, May 01, 2016 at 01:55:38PM -0600, Simon Glass wrote:

> Some build systems want to be quiet unless there is a problem. At present
> mkimage displays quite a bit of information when generating a FIT file. Add
> a '-q' flag to silence this.
> 
> Signed-off-by: Simon Glass 
> Acked-by: Joe Hershberger 

Applied to u-boot/master, thanks!

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Re: [U-Boot] malloc: improve memalign fragmentation fix

[Tom Rini]

On Mon, Apr 25, 2016 at 03:55:42PM -0600, Stephen Warren wrote:

> From: Stephen Warren 
> 
> Commit 4f144a416469 "malloc: work around some memalign fragmentation
> issues" enhanced memalign() so that it can succeed in more cases where
> heap fragmentation is present. However, it did not solve as many cases
> as it could. This patch enhances the code to cover more cases.
> 
> The alignment code works by allocating more space than the user requests,
> then adjusting the returned pointer to achieve alignment. In general, one
> must allocate "alignment" bytes more than the user requested in order to
> guarantee that alignment is possible. This is what the original code does.
> The previous enhancement attempted a second allocation if the padded
> allocation failed, and succeeded if that allocation just happened to be
> aligned; a fluke that happened often in practice. There are still cases
> where this could fail, yet where it is still possible to honor the user's
> allocation request. In particular, if the heap contains a free region that
> is large enough for the user's request, and for leading padding to ensure
> alignment, but has no or little space for any trailing padding. In this
> case, we can make a third(!) allocation attempt after calculating exactly
> the size of the leading padding required to achieve alignment, which is
> the minimal over-allocation needed for the overall memalign() operation to
> succeed if the third and second allocations end up at the same location.
> 
> This patch isn't checkpatch-clean, since it conforms to the existing
> coding style in dlmalloc.c, which is different to the rest of U-Boot.
> 
> Signed-off-by: Stephen Warren 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH 12/12] eeprom: merge cmdline parsing of eeprom commands

[Tom Rini]

On Sat, Apr 16, 2016 at 05:55:13PM +0300, Nikita Kiryanov wrote:

> Merge the parsing of layout aware and layout unaware eeprom commands into
> one parsing function. With this change, layout aware commands now follow
> the eeprom read and eeprom write conventions of making i2c bus and i2c address
> parameters optional.
> 
> Cc: Heiko Schocher 
> Cc: Marek Vasut 
> Cc: Simon Glass 
> Cc: Igor Grinberg 
> Cc: Tom Rini 
> Signed-off-by: Nikita Kiryanov 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [GIT PULL] u-boot-mips/next

[Tom Rini]

On Sat, May 21, 2016 at 01:48:18AM +0200, Daniel Schwierzeck wrote:

> Hi Tom,
> 
> please pull the first batch of MIPS updates, thanks.
> 
> 
> The following changes since commit 4b6e1fda107e5244e80ebc41865650ac2873dc88:
> 
>   Merge git://git.denx.de/u-boot-dm (2016-05-17 13:58:27 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-mips.git master
> 
> for you to fetch changes up to 40ba13c98627055465709acd67872e381b42f928:
> 
>   malta: Support MIPS32r6 configurations (2016-05-21 01:36:39 +0200)
> 

Applied to u-boot/master, thanks!




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Re: [U-Boot] [PATCH 11/12] eeprom: use eeprom_execute_command for all eeprom functions

[Tom Rini]

On Sat, Apr 16, 2016 at 05:55:12PM +0300, Nikita Kiryanov wrote:

> Update eeprom_execute_command() and related code to accommodate both layout
> aware and layout unaware functions.
> 
> No functional changes.
> 
> Cc: Heiko Schocher 
> Cc: Marek Vasut 
> Cc: Simon Glass 
> Cc: Igor Grinberg 
> Cc: Tom Rini 
> Signed-off-by: Nikita Kiryanov 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH 10/12] eeprom: refactor i2c bus and devaddr parsing

[Tom Rini]

On Sat, Apr 16, 2016 at 05:55:11PM +0300, Nikita Kiryanov wrote:

> Introduce parse_i2c_bus_addr() to generalize the parsing of i2c bus number and
> i2c device address. This is done in preparation for merging layout aware and
> layout unaware command parsing into one function.
> 
> No functional changes.
> 
> Cc: Heiko Schocher 
> Cc: Marek Vasut 
> Cc: Simon Glass 
> Cc: Igor Grinberg 
> Cc: Tom Rini 
> Signed-off-by: Nikita Kiryanov 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH 09/12] arm: cm-t43: add support for eeprom layout comands

[Tom Rini]

On Sat, Apr 16, 2016 at 05:55:10PM +0300, Nikita Kiryanov wrote:

> Add support for EEPROM and EEPROM layout commands for CM-T43.
> 
> Cc: Igor Grinberg 
> Cc: Tom Rini 
> Signed-off-by: Nikita Kiryanov 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH 08/12] arm: cm-t35: add support for eeprom layout comands

[Tom Rini]

On Sat, Apr 16, 2016 at 05:55:09PM +0300, Nikita Kiryanov wrote:

> Add support for EEPROM and EEPROM layout commands for CM-T35.
> 
> Cc: Igor Grinberg 
> Cc: Tom Rini 
> Signed-off-by: Nikita Kiryanov 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH 06/12] arm: cm-t54: add support for eeprom layout comands

[Tom Rini]

On Sat, Apr 16, 2016 at 05:55:07PM +0300, Nikita Kiryanov wrote:

> Add support for EEPROM and EEPROM layout commands for CM-T54.
> 
> Cc: Igor Grinberg 
> Cc: Tom Rini 
> Signed-off-by: Nikita Kiryanov 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH 07/12] arm: cm-t3517: add support for eeprom layout comands

[Tom Rini]

On Sat, Apr 16, 2016 at 05:55:08PM +0300, Nikita Kiryanov wrote:

> Add support for EEPROM and EEPROM layout commands for CM-T3517.
> 
> Cc: Igor Grinberg 
> Cc: Tom Rini 
> Signed-off-by: Nikita Kiryanov 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH 02/12] cmd: eeprom: add support for layout aware commands

[Tom Rini]

On Sat, Apr 16, 2016 at 05:55:03PM +0300, Nikita Kiryanov wrote:

> Introduce the (optional) eeprom print and eeprom update commands.
> 
> These commands are eeprom layout aware:
> * The eeprom print command prints the contents of the eeprom in a human
>   readable way (eeprom layout fields, and data formatted to be fit for human
>   consumption).
> * The eeprom update command allows user to update eeprom fields by specifying
>   the field name, and providing the new data in a human readable format (same
>   format as displayed by the eeprom print command).
> * Both commands can either auto detect the layout, or be told which layout to
>   use.
> 
> New CONFIG options:
> CONFIG_CMD_EEPROM_LAYOUT - enables commands.
> CONFIG_EEPROM_LAYOUT_HELP_STRING - tells user what layout names are supported
> 
> Feature API:
> __weak int parse_layout_version(char *str)
>   - override to provide your own layout name parsing
> __weak void __eeprom_layout_assign(struct eeprom_layout *layout, int 
> layout_version);
>   - override to setup the layout metadata based on the version
> __weak int eeprom_layout_detect(unsigned char *data)
>   - override to provide your own algorithm for detecting layout version
> eeprom_field.c
>   - contains various printing and updating functions for common types of
> eeprom fields. Can be used for defining custom layouts.
> 
> Cc: Heiko Schocher 
> Cc: Marek Vasut 
> Cc: Simon Glass 
> Cc: Igor Grinberg 
> Cc: Tom Rini 
> Signed-off-by: Nikita Kiryanov 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH 03/12] compulab: add support for layout aware eeprom commands

[Tom Rini]

On Sat, Apr 16, 2016 at 05:55:04PM +0300, Nikita Kiryanov wrote:

> Add layout definitions and implement functions for field printing/updating,
> layout detection, layout assignment, and layout parsing.
> 
> Cc: Igor Grinberg 
> Cc: Tom Rini 
> Signed-off-by: Nikita Kiryanov 

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Re: [U-Boot] [PATCH 05/12] arm: cm-t335: add support for eeprom layout comands

[Tom Rini]

On Sat, Apr 16, 2016 at 05:55:06PM +0300, Nikita Kiryanov wrote:

> Add support for EEPROM and EEPROM layout commands for CM-T335.
> 
> Cc: Igor Grinberg 
> Cc: Tom Rini 
> Signed-off-by: Nikita Kiryanov 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH 04/12] arm: cm-fx6: add support for eeprom layout comands

[Tom Rini]

On Sat, Apr 16, 2016 at 05:55:05PM +0300, Nikita Kiryanov wrote:

> Add support for EEPROM and EEPROM layout commands for CM-FX6.
> 
> Cc: Igor Grinberg 
> Cc: Tom Rini 
> Signed-off-by: Nikita Kiryanov 

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Re: [U-Boot] [PATCH 01/12] cmd: eeprom: add bus switching support for all i2c drivers

[Tom Rini]

On Sat, Apr 16, 2016 at 05:55:02PM +0300, Nikita Kiryanov wrote:

> The i2c_init function is always provided when CONFIG_SYS_I2C is
> defined. No need to limit ourselves to just one supported I2C driver
> (soft_i2c). Update the #ifdef conditions to support bus switching for
> all I2C drivers.
> 
> Cc: Heiko Schocher 
> Cc: Marek Vasut 
> Cc: Igor Grinberg 
> Cc: Tom Rini 
> Signed-off-by: Nikita Kiryanov 

Applied to u-boot/master, thanks!

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Re: [U-Boot] Please pull u-boot-marvell/master

[Tom Rini]

On Fri, May 20, 2016 at 11:10:39AM +0200, Stefan Roese wrote:

> Hi Tom,
> 
> please pull those 2 patches.
> 
> Thanks,
> Stefan
> 
> The following changes since commit 4b6e1fda107e5244e80ebc41865650ac2873dc88:
> 
>   Merge git://git.denx.de/u-boot-dm (2016-05-17 13:58:27 -0400)
> 
> are available in the git repository at:
> 
>   git://www.denx.de/git/u-boot-marvell.git 
> 
> for you to fetch changes up to fbaf42724f372ee3fb0d7cd83107f5bae416028f:
> 
>   arm: mvebu: theadorable: Enable CONFIG_ZERO_BOOTDELAY_CHECK (2016-05-20 
> 11:08:16 +0200)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH v2 00/25] exynos: video: Convert exynos LCD driver to use driver model

[Simon Glass]

Hi Minkyu,

On 16 May 2016 at 22:38, Minkyu Kang  wrote:
> Hi,
>
> On 17/05/16 13:22, Jaehoon Chung wrote:
>> Hi Simon.
>>
>> On 05/15/2016 06:22 AM, Simon Glass wrote:
>>> Hi Jaehoon,
>>>
>>> On 13 May 2016 at 07:09, Jaehoon Chung  wrote:
 Hi Simon,

 On 05/09/2016 08:00 PM, Minkyu Kang wrote:
> Hi Jaehoon,
>
> On 08/05/16 06:25, Simon Glass wrote:
>> Hi,
>>
>> On 1 March 2016 at 18:51, Minkyu Kang  wrote:
>>> Hi,
>>>
>>> On 29/02/16 16:18, Jaehoon Chung wrote:
 Hi,

 On 02/29/2016 01:23 PM, Simon Glass wrote:
> Hi,
>
> On 23 February 2016 at 05:04, Minkyu Kang  
> wrote:
>> Dear Simon Glass,
>>
>> On 23/02/16 15:42, Simon Glass wrote:
>>> Hi Minkyu,
>>>
>>> On 21 February 2016 at 21:08, Simon Glass  wrote:

 This series converts the exynos LCD driver to work with driver 
 model. Only
 the eDP display is converted - the MIPI display is left mostly 
 alone as I
 do not have a device to test with.

 The conversion involves some refactoring to simplify the code, 
 reduce the
 amount of global/static data and allow boards to be built without 
 LCD
 support.

 The series is tested with snow, spring, pit and pi. It disables 
 LCD on other
 exynos boards so that they will still build with these changes. 
 Further work
 will be needed (by someone with a board) to convert the others. I 
 am not
 sure when this series can be applied.

 The series also brings in device tree features from Linux v4.4. It 
 would be
 useful to do a full sync with the kernel on these files, but this 
 is really
 a job for the Samsung maintainer :-)

 The series is available at u-boot-dm/rkg-working.

 Changes in v2:
 - Rebase to master
 - Rebase to master

>>>
>>> What do you think we should do about applying this series?
>>>
>>
>> Although we have to do remaining work, I think applying is possible 
>> without next work.
>>
>> Board maintainers, what do you think?
>>
>> Remaining Work:
>> - MIPI display driver
>> - s5pc210_universal
>> - smdk5420
>> - smdk5250
>> - trats
>> - trats2
>>
>> Thanks,
>> Minkyu Kang.
>
> Well, no replies as yet. The main work requires is MIPI, but as I
> don't have the hardware, I can't help with that. At least I have made
> sure that everything builds OK.

 Sorry for late..I will check these patches on this week..Tomorrow is 
 holiday..
 So I can check from Wed.
>>>
>>> Thank you, Jaehoon.
>>
>> It has been a few months now - if you like I can apply these via the -dm 
>> tree.

 Yep, I checked these..It needs to remain the future work.
 But it seems that it's not problem to apply at -dm repository.
 (I have checked with your patch on other boadrs.)

 I needs to check one more things..Could you wait until next Tuesday?

>>>
>>> Sure, it's been 3 months so another week won't matter :-)
>>
>> Sorry. I have checked more with these patches..We have to work too many 
>> things in future for remaining work.
>> But it seems those task are our role..If you and Minkyu are ok, you can 
>> apply these at dm repository.
>
> I'm OK.
> If you want, those can be merged to samsung tree.

Thanks, please go ahead!

>
>>
>> I will make a plan to work. (Based on your repository.)
>>
>> Actually, i didn't follow a few month, so i'm looking for u-boot history. 
>> Sorry. :(
>> If you want to add my Reviewed-by tag, then you can add.
>>
>> In future work,
>> Change to driver model for above targets. (trats2/trats...)
>> MIPI display driver..(I will assign to my colleague for this task.)

Regards,
Simon
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Re: [U-Boot] [PATCH] RFC: Secure boot to U-Boot proper from SPL

[Andreas Dannenberg]

Hi Teddy,

On Mon, May 23, 2016 at 01:53:35PM -0400, Teddy Reed wrote:
> 
> > On May 23, 2016, at 1:15 PM, Andreas Dannenberg  wrote:
> > 
> >> On Sun, May 08, 2016 at 06:13:50PM -0700, Teddy Reed wrote:
> >>> On Sun, May 1, 2016 at 11:12 AM, Teddy Reed 
> >>> wrote: I've been using the following patch for my configurations,
> >>> please excuse the top-posting. I think the only difference is
> >>> enabling the uclass mod_exp driver to initialize without needing
> >>> relocation.
> >> 
> >> If no one has any additional notes / requirements for enablement in
> >> SPL I can send my tiny bit of configuration changes as a patch.
> >> 
> >> I've tested the DM flag change for the RSA mod_exp driver class for
> >> both relocated (u-boot) and non-relocated (SPL) builds and found no
> >> issues. It would be awesome to get another set of eyes on the Makefile
> >> feature reorganization as I don't want this to include unneeded code
> >> into SPLs. :)
> > 
> > Hi Teddy,
> > I was just trying to work your patch into my U-Boot tree to experiment
> > with it some when I realized that it requires CONFIG_SPL_DM which is
> > something the platforms I work with don't currently support :(
> > 
> > I'll need to look further and see what I can do about it (using the
> > non-DM rsa_mod_exp_sw routine instead of rsa_mod_exp?) but generally
> > speaking it seems like that non-DM based authentication could be a
> > useful feature for SPL, since one big reason of using an SPL in the
> > first place is to have something that fits into the minimum amount of
> > on-chip RAM possible...
> 
> Definitely! My original goal was verified boot in SPL with a minimum
> set of configuration/code changes. I've been working in the code base
> for a few weeks now and absolutely agree that with a bit more code
> modifications the driver model requirement could removed.
> 
> I do love the concept of representing the EXP implementation as a
> uclass driver, but for highly constrained SPLs it's not the best.
> 
> I think it's a good idea to land the proposed minimum set of
> configuration changes required for verified boot in SPL. Then we can
> iterate together on removing the DM requirement. What do you think?

Yes I think what you have in your RFC is definitely a good starting
point and building this out with additional patches sounds like a
reasonable approach. But as you are preparing your actual initial patch
submission it'd be good to keep in the back of your mind to architect it
such that it can be build upon further... (I realize it's a bit of a
chicken-and-egg problem but I wanted to make that comment anways ha).
But I'm definitely going to further experiment with this and let you
know if there are relevant findings.

Since you seem to be spending quite a bit of energy on the auth stuff I
suppose there is another thing you probably ran into as well which is
related to how the public key gets embedded into the DTB file. When
using CONFIG_SPL_LOAD_FIT to build a FIT blob containing U-Boot and one
or several DTBs I think the mkimage-based process of embedding said
public key [1] doesn't really apply. So for now I "hacked" it by
embedding the public key manually directly in the DTS source files so
that U-Boot can access it but clearly this needs a better solution. I'm
thinking of an approach of where the U-Boot build process would consume
the public key (maybe specified via a CONFIG_xxx) and bake it directly
into DTB file(s) specified by CONFIG_OF_LIST during build before they
get bundled together into a FIT blob but I wonder if you might have
already had some thoughts on this topic.

Thanks and Regards,
Andreas

[1]
http://git.denx.de/?p=u-boot.git;a=blob;f=doc/uImage.FIT/beaglebone_vboot.txt;h=b4ab28542e50458e1d9eeda0add716426f08b076;hb=HEAD#l208
 

> The main reason I suggest multiple patches is because the decoupling
> may also affect non-SPL verified boots. :)
> 
> Take care!  -Teddy
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[U-Boot] [PATCH 3/4] ARM: DRA7: Consolidate voltage macros across different SoCs

[Suman Anna]

The voltage values for each voltage domain at an OPP is identical
across all the SoCs in the DRA7 family. The current code defines
one set of macros for DRA75x/DRA74x SoCs and another set for DRA72x
macros. Consolidate both these sets into a single set.

This is done so as to minimize the number of macros used when voltage
values will be added for other OPPs as well.

Signed-off-by: Suman Anna 
---
 arch/arm/cpu/armv7/omap5/hw_data.c  | 20 ++--
 arch/arm/include/asm/arch-omap5/clock.h | 19 ++-
 board/ti/am57xx/board.c | 10 +-
 3 files changed, 21 insertions(+), 28 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c 
b/arch/arm/cpu/armv7/omap5/hw_data.c
index 948461a..b0c83ad 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -365,34 +365,34 @@ struct vcores_data omap5430_volts_es2 = {
 };
 
 struct vcores_data dra752_volts = {
-   .mpu.value  = VDD_MPU_DRA752,
+   .mpu.value  = VDD_MPU_DRA7,
.mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr   = TPS659038_REG_ADDR_SMPS12,
.mpu.pmic   = ,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 
-   .eve.value  = VDD_EVE_DRA752,
+   .eve.value  = VDD_EVE_DRA7,
.eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr   = TPS659038_REG_ADDR_SMPS45,
.eve.pmic   = ,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 
-   .gpu.value  = VDD_GPU_DRA752,
+   .gpu.value  = VDD_GPU_DRA7,
.gpu.efuse.reg  = STD_FUSE_OPP_VMIN_GPU,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr   = TPS659038_REG_ADDR_SMPS6,
.gpu.pmic   = ,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 
-   .core.value = VDD_CORE_DRA752,
+   .core.value = VDD_CORE_DRA7,
.core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr  = TPS659038_REG_ADDR_SMPS7,
.core.pmic  = ,
 
-   .iva.value  = VDD_IVA_DRA752,
+   .iva.value  = VDD_IVA_DRA7,
.iva.efuse.reg  = STD_FUSE_OPP_VMIN_IVA,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr   = TPS659038_REG_ADDR_SMPS8,
@@ -401,14 +401,14 @@ struct vcores_data dra752_volts = {
 };
 
 struct vcores_data dra722_volts = {
-   .mpu.value  = VDD_MPU_DRA72x,
+   .mpu.value  = VDD_MPU_DRA7,
.mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr   = TPS65917_REG_ADDR_SMPS1,
.mpu.pmic   = ,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 
-   .core.value = VDD_CORE_DRA72x,
+   .core.value = VDD_CORE_DRA7,
.core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr  = TPS65917_REG_ADDR_SMPS2,
@@ -418,21 +418,21 @@ struct vcores_data dra722_volts = {
 * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
 * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
 */
-   .gpu.value  = VDD_GPU_DRA72x,
+   .gpu.value  = VDD_GPU_DRA7,
.gpu.efuse.reg  = STD_FUSE_OPP_VMIN_GPU,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr   = TPS65917_REG_ADDR_SMPS3,
.gpu.pmic   = ,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 
-   .eve.value  = VDD_EVE_DRA72x,
+   .eve.value  = VDD_EVE_DRA7,
.eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr   = TPS65917_REG_ADDR_SMPS3,
.eve.pmic   = ,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 
-   .iva.value  = VDD_IVA_DRA72x,
+   .iva.value  = VDD_IVA_DRA7,
.iva.efuse.reg  = STD_FUSE_OPP_VMIN_IVA,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr   = TPS65917_REG_ADDR_SMPS3,
diff --git a/arch/arm/include/asm/arch-omap5/clock.h 
b/arch/arm/include/asm/arch-omap5/clock.h
index a850043..8c121d6 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -239,19 +239,12 @@
 #define VDD_MPU_ES2_LOW 880
 #define VDD_MM_ES2_LOW 880
 
-/* DRA74x/75x voltage settings in mv for OPP_NOM per DM */
-#define VDD_MPU_DRA752 1150
-#define VDD_CORE_DRA7521150
-#define VDD_EVE_DRA752 1060
-#define VDD_GPU_DRA752 1060
-#define VDD_IVA_DRA752 1060
-
-/* DRA72x voltage settings in mv for OPP_NOM per DM */
-#define VDD_MPU_DRA72x 1150
-#define VDD_CORE_DRA72x1150
-#define VDD_EVE_DRA72x 1060
-#define VDD_GPU_DRA72x 1060
-#define 

[U-Boot] [PATCH 1/4] ARM: DRA7: Update/Correct MPU and CORE OPP_NOM voltage values

[Suman Anna]

The current OPP_NOM voltage values defined for the MPU and CORE
voltage domains are based on the initial DRA75x_74x_SR1.1_DM data
manual. As per this DM, the PMIC boot voltage can be set to either
1.10V or 1.15V for VD_MPU, and either 1.06V or 1.15V for VD_CORE.
While the current values are correct, the latter set of values
are the values that are common across all DRA75x, DRA72x SoCs and
for all current Silicon revisions. So, update both the MPU and CORE
OPP_NOM voltages to 1.15V.

The macros are also slightly reorganized so that both the MPU and
CORE voltage domain values are defined together.

Signed-off-by: Suman Anna 
---
 arch/arm/include/asm/arch-omap5/clock.h | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/arch-omap5/clock.h 
b/arch/arm/include/asm/arch-omap5/clock.h
index 38d50d6..9180c67 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -240,17 +240,17 @@
 #define VDD_MM_ES2_LOW 880
 
 /* DRA74x/75x voltage settings in mv for OPP_NOM per DM */
-#define VDD_MPU_DRA752 1100
+#define VDD_MPU_DRA752 1150
+#define VDD_CORE_DRA7521150
 #define VDD_EVE_DRA752 1060
 #define VDD_GPU_DRA752 1060
-#define VDD_CORE_DRA7521060
 #define VDD_IVA_DRA752 1060
 
 /* DRA72x voltage settings in mv for OPP_NOM per DM */
-#define VDD_MPU_DRA72x 1100
+#define VDD_MPU_DRA72x 1150
+#define VDD_CORE_DRA72x1150
 #define VDD_EVE_DRA72x 1060
 #define VDD_GPU_DRA72x 1060
-#define VDD_CORE_DRA72x1060
 #define VDD_IVA_DRA72x 1060
 
 /* Efuse register offsets for DRA7xx platform */
-- 
2.8.2

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[U-Boot] [PATCH 2/4] ARM: DRA7: Define common macros for efuse register offsets

[Suman Anna]

Define a set of common macros for the efuse register offsets
(different for each OPP) that are used to get the AVS Class 0
voltage values and ABB configuration values. Assign these
common macros to the register offsets for OPP_NOM by default
for all voltage domains. These common macros can then be
redefined properly to point to the OPP specific efuse register
offset based on the desired OPP to program a specific voltage
domain.

Signed-off-by: Suman Anna 
---
 arch/arm/cpu/armv7/omap5/hw_data.c  | 20 ++--
 arch/arm/include/asm/arch-omap5/clock.h |  7 +++
 board/ti/am57xx/board.c | 10 +-
 3 files changed, 22 insertions(+), 15 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c 
b/arch/arm/cpu/armv7/omap5/hw_data.c
index 88e8920..948461a 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -366,34 +366,34 @@ struct vcores_data omap5430_volts_es2 = {
 
 struct vcores_data dra752_volts = {
.mpu.value  = VDD_MPU_DRA752,
-   .mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU_NOM,
+   .mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr   = TPS659038_REG_ADDR_SMPS12,
.mpu.pmic   = ,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 
.eve.value  = VDD_EVE_DRA752,
-   .eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+   .eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr   = TPS659038_REG_ADDR_SMPS45,
.eve.pmic   = ,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 
.gpu.value  = VDD_GPU_DRA752,
-   .gpu.efuse.reg  = STD_FUSE_OPP_VMIN_GPU_NOM,
+   .gpu.efuse.reg  = STD_FUSE_OPP_VMIN_GPU,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr   = TPS659038_REG_ADDR_SMPS6,
.gpu.pmic   = ,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 
.core.value = VDD_CORE_DRA752,
-   .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
+   .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr  = TPS659038_REG_ADDR_SMPS7,
.core.pmic  = ,
 
.iva.value  = VDD_IVA_DRA752,
-   .iva.efuse.reg  = STD_FUSE_OPP_VMIN_IVA_NOM,
+   .iva.efuse.reg  = STD_FUSE_OPP_VMIN_IVA,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr   = TPS659038_REG_ADDR_SMPS8,
.iva.pmic   = ,
@@ -402,14 +402,14 @@ struct vcores_data dra752_volts = {
 
 struct vcores_data dra722_volts = {
.mpu.value  = VDD_MPU_DRA72x,
-   .mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU_NOM,
+   .mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr   = TPS65917_REG_ADDR_SMPS1,
.mpu.pmic   = ,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 
.core.value = VDD_CORE_DRA72x,
-   .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
+   .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr  = TPS65917_REG_ADDR_SMPS2,
.core.pmic  = ,
@@ -419,21 +419,21 @@ struct vcores_data dra722_volts = {
 * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
 */
.gpu.value  = VDD_GPU_DRA72x,
-   .gpu.efuse.reg  = STD_FUSE_OPP_VMIN_GPU_NOM,
+   .gpu.efuse.reg  = STD_FUSE_OPP_VMIN_GPU,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr   = TPS65917_REG_ADDR_SMPS3,
.gpu.pmic   = ,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 
.eve.value  = VDD_EVE_DRA72x,
-   .eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+   .eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr   = TPS65917_REG_ADDR_SMPS3,
.eve.pmic   = ,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 
.iva.value  = VDD_IVA_DRA72x,
-   .iva.efuse.reg  = STD_FUSE_OPP_VMIN_IVA_NOM,
+   .iva.efuse.reg  = STD_FUSE_OPP_VMIN_IVA,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr   = TPS65917_REG_ADDR_SMPS3,
.iva.pmic   = ,
diff --git a/arch/arm/include/asm/arch-omap5/clock.h 
b/arch/arm/include/asm/arch-omap5/clock.h
index 9180c67..a850043 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -283,6 +283,13 @@
 /* STD_FUSE_OPP_VMIN_MPU_4 */
 #define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28)
 
+/* Common Efuse register macros */
+#define STD_FUSE_OPP_VMIN_MPU  STD_FUSE_OPP_VMIN_MPU_NOM
+#define STD_FUSE_OPP_VMIN_CORE STD_FUSE_OPP_VMIN_CORE_NOM
+#define STD_FUSE_OPP_VMIN_DSPEVE   STD_FUSE_OPP_VMIN_DSPEVE_NOM
+#define 

[U-Boot] [PATCH 0/4] DRA7 Voltage macro consolidation

[Suman Anna]

Hi Tom,

The following series consolidates the current macros used
for Voltage configuration on DRA7/AM57xx platforms. This is a
preparatory series for a follow-up series that introduces
the ability to choose OPP configurations at boot time for
various voltage domains using Kconfigs. I will submit that
series once the "Support for boot image creation for TI secure
devices" series [1] gets merged.

Patches based on current u-boot master commit 4b6e1fd,
and a commit [2] to fix current SPL boot issues on DRA7
platforms.

regards
Suman

[1] http://marc.info/?l=u-boot=146370308317931=2
[2] https://patchwork.ozlabs.org/patch/624267/

Suman Anna (4):
  ARM: DRA7: Update/Correct MPU and CORE OPP_NOM voltage values
  ARM: DRA7: Define common macros for efuse register offsets
  ARM: DRA7: Consolidate voltage macros across different SoCs
  ARM: DRA7: Add macros for voltage values for all OPPs

 arch/arm/cpu/armv7/omap5/hw_data.c  | 40 +++---
 arch/arm/include/asm/arch-omap5/clock.h | 43 +++--
 board/ti/am57xx/board.c | 20 +++
 3 files changed, 60 insertions(+), 43 deletions(-)

-- 
2.8.2

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Re: [U-Boot] [PATCH] RFC: Secure boot to U-Boot proper from SPL

[Teddy Reed]

> On May 23, 2016, at 1:15 PM, Andreas Dannenberg  wrote:
> 
>> On Sun, May 08, 2016 at 06:13:50PM -0700, Teddy Reed wrote:
>>> On Sun, May 1, 2016 at 11:12 AM, Teddy Reed  wrote:
>>> I've been using the following patch for my configurations, please excuse 
>>> the top-posting. I think the only difference is enabling the uclass mod_exp 
>>> driver to initialize without needing relocation.
>> 
>> If no one has any additional notes / requirements for enablement in
>> SPL I can send my tiny bit of configuration changes as a patch.
>> 
>> I've tested the DM flag change for the RSA mod_exp driver class for
>> both relocated (u-boot) and non-relocated (SPL) builds and found no
>> issues. It would be awesome to get another set of eyes on the Makefile
>> feature reorganization as I don't want this to include unneeded code
>> into SPLs. :)
> 
> Hi Teddy,
> I was just trying to work your patch into my U-Boot tree to experiment
> with it some when I realized that it requires CONFIG_SPL_DM which is
> something the platforms I work with don't currently support :(
> 
> I'll need to look further and see what I can do about it (using the
> non-DM rsa_mod_exp_sw routine instead of rsa_mod_exp?) but generally
> speaking it seems like that non-DM based authentication could be a
> useful feature for SPL, since one big reason of using an SPL in the
> first place is to have something that fits into the minimum amount of
> on-chip RAM possible...

Definitely! My original goal was verified boot in SPL with a minimum set of 
configuration/code changes. I've been working in the code base for a few weeks 
now and absolutely agree that with a bit more code modifications the driver 
model requirement could removed.

I do love the concept of representing the EXP implementation as a uclass 
driver, but for highly constrained SPLs it's not the best.

I think it's a good idea to land the proposed minimum set of configuration 
changes required for verified boot in SPL. Then we can iterate together on 
removing the DM requirement. What do you think?
The main reason I suggest multiple patches is because the decoupling may also 
affect non-SPL verified boots. :)

Take care!
-Teddy

> 
> Thanks and Regards,
> 
> --
> Andreas Dannenberg
> Texas Instruments Inc
> 
>>> This allows a board to configure verified boot within the SPL using
>>> a FIT or FIT with external data. It also allows the SPL to perform
>>> signature verification without needing relocation.
>>> 
>>> The board configuration will need to add the following feature defines:
>>> CONFIG_SPL_CRYPTO_SUPPORT
>>> CONFIG_SPL_HASH_SUPPORT
>>> CONFIG_SPL_SHA256
>>> 
>>> In this example, SHA256 is the selected hashing algorithm.
>>> 
>>> And the following booleans:
>>> CONFIG_SPL=y
>>> CONFIG_SPL_DM=y
>>> CONFIG_SPL_LOAD_FIT=y
>>> CONFIG_SPL_FIT=y
>>> CONFIG_SPL_OF_CONTROL=y
>>> CONFIG_SPL_OF_LIBFDT=y
>>> CONFIG_SPL_FIT_SIGNATURE=y
>>> 
>>> Signed-off-by: Teddy Reed 
>>> ---
>>> Kconfig | 11 +++
>>> common/Makefile |  1 +
>>> drivers/Makefile|  1 +
>>> drivers/crypto/rsa_mod_exp/mod_exp_sw.c |  1 +
>>> lib/Makefile|  9 +
>>> lib/rsa/Kconfig |  3 +++
>>> lib/rsa/Makefile|  2 +-
>>> 7 files changed, 23 insertions(+), 5 deletions(-)
>>> 
>>> diff --git a/Kconfig b/Kconfig
>>> index f53759a..e73ad03 100644
>>> --- a/Kconfig
>>> +++ b/Kconfig
>>> @@ -183,6 +183,11 @@ config FIT
>>>  verified boot (secure boot using RSA). This option enables that
>>>  feature.
>>> 
>>> +config SPL_FIT
>>> +   bool "Support Flattened Image Tree within SPL"
>>> +   depends on FIT
>>> +   depends on SPL
>>> +
>>> config FIT_VERBOSE
>>>bool "Display verbose messages on FIT boot"
>>>depends on FIT
>>> @@ -205,6 +210,12 @@ config FIT_SIGNATURE
>>>  format support in this case, enable it using
>>>  CONFIG_IMAGE_FORMAT_LEGACY.
>>> 
>>> +config SPL_FIT_SIGNATURE
>>> +   bool "Enable signature verification of FIT firmware within SPL"
>>> +   depends on SPL_FIT
>>> +   depends on SPL_DM
>>> +   select SPL_RSA
>>> +
>>> config FIT_BEST_MATCH
>>>bool "Select the best match for the kernel device tree"
>>>depends on FIT
>>> diff --git a/common/Makefile b/common/Makefile
>>> index b23f312..271f633 100644
>>> --- a/common/Makefile
>>> +++ b/common/Makefile
>>> @@ -91,6 +91,7 @@ obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
>>> endif # !CONFIG_SPL_BUILD
>>> 
>>> ifdef CONFIG_SPL_BUILD
>>> +obj-$(CONFIG_SPL_HASH_SUPPORT) += hash.o
>>> obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
>>> obj-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o
>>> obj-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o
>>> diff --git a/drivers/Makefile b/drivers/Makefile
>>> index 6900097..456492f 100644
>>> --- a/drivers/Makefile
>>> +++ b/drivers/Makefile

[U-Boot] [PATCH 4/4] ARM: DRA7: Add macros for voltage values for all OPPs

[Suman Anna]

Define specific macros for the voltage values for all voltage
domains for all applicable OPPs - OPP_NOM, OPP_OD and OPP_HIGH.
No separate macros are defined for VD_MPU and VD_CORE at OPP_OD
and OPP_HIGH as these use the same values as OPP_NOM.

The current macros will be used as common macros that can be
redefined appropriately based on a selected OPP configuration
at build time.

Signed-off-by: Suman Anna 
---
 arch/arm/include/asm/arch-omap5/clock.h | 29 +++--
 1 file changed, 23 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/asm/arch-omap5/clock.h 
b/arch/arm/include/asm/arch-omap5/clock.h
index 8c121d6..551c927 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -240,11 +240,21 @@
 #define VDD_MM_ES2_LOW 880
 
 /* DRA74x/75x/72x voltage settings in mv for OPP_NOM per DM */
-#define VDD_MPU_DRA7   1150
-#define VDD_CORE_DRA7  1150
-#define VDD_EVE_DRA7   1060
-#define VDD_GPU_DRA7   1060
-#define VDD_IVA_DRA7   1060
+#define VDD_MPU_DRA7_NOM   1150
+#define VDD_CORE_DRA7_NOM  1150
+#define VDD_EVE_DRA7_NOM   1060
+#define VDD_GPU_DRA7_NOM   1060
+#define VDD_IVA_DRA7_NOM   1060
+
+/* DRA74x/75x/72x voltage settings in mv for OPP_OD per DM */
+#define VDD_EVE_DRA7_OD1150
+#define VDD_GPU_DRA7_OD1150
+#define VDD_IVA_DRA7_OD1150
+
+/* DRA74x/75x/72x voltage settings in mv for OPP_HIGH per DM */
+#define VDD_EVE_DRA7_HIGH  1250
+#define VDD_GPU_DRA7_HIGH  1250
+#define VDD_IVA_DRA7_HIGH  1250
 
 /* Efuse register offsets for DRA7xx platform */
 #define DRA752_EFUSE_BASE  0x4A002000
@@ -276,7 +286,14 @@
 /* STD_FUSE_OPP_VMIN_MPU_4 */
 #define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28)
 
-/* Common Efuse register macros */
+/* Common voltage and Efuse register macros */
+/* DRA74x/DRA75x/DRA72x */
+#define VDD_MPU_DRA7   VDD_MPU_DRA7_NOM
+#define VDD_CORE_DRA7  VDD_CORE_DRA7_NOM
+#define VDD_EVE_DRA7   VDD_EVE_DRA7_NOM
+#define VDD_GPU_DRA7   VDD_GPU_DRA7_NOM
+#define VDD_IVA_DRA7   VDD_IVA_DRA7_NOM
+
 #define STD_FUSE_OPP_VMIN_MPU  STD_FUSE_OPP_VMIN_MPU_NOM
 #define STD_FUSE_OPP_VMIN_CORE STD_FUSE_OPP_VMIN_CORE_NOM
 #define STD_FUSE_OPP_VMIN_DSPEVE   STD_FUSE_OPP_VMIN_DSPEVE_NOM
-- 
2.8.2

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[U-Boot] [PATCH] clk: convert API to match reset/mailbox style

[Stephen Warren]

From: Stephen Warren 

The following changes are made to the clock API:
* The concept of "clocks" and "peripheral clocks" are unified; each clock
  provider now implements a single set of clocks. This provides a simpler
  conceptual interface to clients, and better aligns with device tree
  clock bindings.
* Clocks are now identified with a single "struct clk", rather than
  requiring clients to store the clock provider device and clock identity
  values separately. For simple clock consumers, this isolates clients
  from internal details of the clock API.
* clk.h is split into clk_client.h and clk_uclass.h to make it obvious
  which parts are relevant to consumers and providers. This aligns with
  the recently added reset and mailbox APIs.
* clk_ops .of_xlate(), .request(), and .free() are added so providers
  can customize these operations if needed. This also aligns with the
  recently added reset and mailbox APIs.
* clk_disable() is added.
* All users of the current clock APIs are updated.
* Sandbox clock tests are updated to exercise clock lookup via DT, and
  clock enable/disable.
* rkclk_get_clk() is removed and replaced with standard APIs.

Buildman shows no clock-related errors for any board for which buildman
can download a toolchain.

test/py passes for sandbox (which invokes the dm clk test amongst
others).

Cc: Mateusz Kulikowski 
Cc: Daniel Schwierzeck 
Cc: Purna Chandra Mandal 
Cc: Masahiro Yamada 
Signed-off-by: Stephen Warren 
---
 arch/arm/include/asm/arch-rockchip/clock.h   |  12 --
 arch/arm/mach-rockchip/board.c   |  41 +-
 arch/arm/mach-rockchip/rk3288/sdram_rk3288.c |  17 ++-
 arch/arm/mach-snapdragon/clock-apq8016.c |  10 +-
 arch/arm/mach-zynq/clk.c |   1 -
 arch/mips/mach-pic32/cpu.c   |  47 +++---
 arch/sandbox/dts/test.dts|  17 ++-
 arch/sandbox/include/asm/clk.h   |  39 +
 arch/sandbox/include/asm/test.h  |   9 --
 board/microchip/pic32mzda/pic32mzda.c|  23 ++-
 cmd/clk.c|   2 +-
 drivers/clk/Makefile |   1 +
 drivers/clk/clk-uclass.c | 204 +++
 drivers/clk/clk_fixed_rate.c |  13 +-
 drivers/clk/clk_pic32.c  |  32 ++---
 drivers/clk/clk_rk3036.c |  83 +++
 drivers/clk/clk_rk3288.c | 141 --
 drivers/clk/clk_sandbox.c|  85 ++-
 drivers/clk/clk_sandbox_test.c   | 101 +
 drivers/clk/uniphier/clk-uniphier-core.c |  26 ++--
 drivers/clk/uniphier/clk-uniphier-mio.c  |   1 -
 drivers/gpio/rk_gpio.c   |   1 -
 drivers/i2c/rk_i2c.c |   8 +-
 drivers/mmc/msm_sdhci.c  |  15 +-
 drivers/mmc/rockchip_dw_mmc.c|   8 +-
 drivers/mmc/uniphier-sd.c|  17 +--
 drivers/serial/serial_msm.c  |  15 +-
 drivers/serial/serial_pic32.c|   9 +-
 drivers/spi/rk_spi.c |   8 +-
 drivers/usb/host/ehci-generic.c  |  16 +--
 drivers/video/rockchip/rk_edp.c  |  13 +-
 drivers/video/rockchip/rk_hdmi.c |  14 +-
 drivers/video/rockchip/rk_lvds.c |   1 -
 drivers/video/rockchip/rk_vop.c  |  13 +-
 include/clk.h| 132 -
 include/clk_client.h | 174 +++
 include/clk_uclass.h |  95 +
 test/dm/clk.c| 110 ++-
 38 files changed, 948 insertions(+), 606 deletions(-)
 create mode 100644 arch/sandbox/include/asm/clk.h
 create mode 100644 drivers/clk/clk_sandbox_test.c
 delete mode 100644 include/clk.h
 create mode 100644 include/clk_client.h
 create mode 100644 include/clk_uclass.h

diff --git a/arch/arm/include/asm/arch-rockchip/clock.h 
b/arch/arm/include/asm/arch-rockchip/clock.h
index d66b26f18ef3..317e5128ed2b 100644
--- a/arch/arm/include/asm/arch-rockchip/clock.h
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -62,18 +62,6 @@ static inline u32 clk_get_divisor(ulong input_rate, uint 
output_rate)
  */
 void *rockchip_get_cru(void);
 
-/**
- * rkclk_get_clk() - get a pointer to a given clock
- *
- * This is an internal function - use outside the clock subsystem indicates
- * that work is needed!
- *
- * @clk_id:Clock requested
- * @devp:  Returns a pointer to that clock
- * @return 0 if OK, -ve on error
- */
-int rkclk_get_clk(enum rk_clk_id clk_id, struct udevice **devp);
-
 struct rk3288_cru;
 struct rk3288_grf;
 
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index 

Re: [U-Boot] [PATCH] RFC: Secure boot to U-Boot proper from SPL

[Andreas Dannenberg]

On Sun, May 08, 2016 at 06:13:50PM -0700, Teddy Reed wrote:
> On Sun, May 1, 2016 at 11:12 AM, Teddy Reed  wrote:
> > I've been using the following patch for my configurations, please excuse 
> > the top-posting. I think the only difference is enabling the uclass mod_exp 
> > driver to initialize without needing relocation.
> >
> 
> If no one has any additional notes / requirements for enablement in
> SPL I can send my tiny bit of configuration changes as a patch.
> 
> I've tested the DM flag change for the RSA mod_exp driver class for
> both relocated (u-boot) and non-relocated (SPL) builds and found no
> issues. It would be awesome to get another set of eyes on the Makefile
> feature reorganization as I don't want this to include unneeded code
> into SPLs. :)

Hi Teddy,
I was just trying to work your patch into my U-Boot tree to experiment
with it some when I realized that it requires CONFIG_SPL_DM which is
something the platforms I work with don't currently support :(

I'll need to look further and see what I can do about it (using the
non-DM rsa_mod_exp_sw routine instead of rsa_mod_exp?) but generally
speaking it seems like that non-DM based authentication could be a
useful feature for SPL, since one big reason of using an SPL in the
first place is to have something that fits into the minimum amount of
on-chip RAM possible...

Thanks and Regards,

--
Andreas Dannenberg
Texas Instruments Inc

> > This allows a board to configure verified boot within the SPL using
> > a FIT or FIT with external data. It also allows the SPL to perform
> > signature verification without needing relocation.
> >
> > The board configuration will need to add the following feature defines:
> > CONFIG_SPL_CRYPTO_SUPPORT
> > CONFIG_SPL_HASH_SUPPORT
> > CONFIG_SPL_SHA256
> >
> > In this example, SHA256 is the selected hashing algorithm.
> >
> > And the following booleans:
> > CONFIG_SPL=y
> > CONFIG_SPL_DM=y
> > CONFIG_SPL_LOAD_FIT=y
> > CONFIG_SPL_FIT=y
> > CONFIG_SPL_OF_CONTROL=y
> > CONFIG_SPL_OF_LIBFDT=y
> > CONFIG_SPL_FIT_SIGNATURE=y
> >
> > Signed-off-by: Teddy Reed 
> > ---
> >  Kconfig | 11 +++
> >  common/Makefile |  1 +
> >  drivers/Makefile|  1 +
> >  drivers/crypto/rsa_mod_exp/mod_exp_sw.c |  1 +
> >  lib/Makefile|  9 +
> >  lib/rsa/Kconfig |  3 +++
> >  lib/rsa/Makefile|  2 +-
> >  7 files changed, 23 insertions(+), 5 deletions(-)
> >
> > diff --git a/Kconfig b/Kconfig
> > index f53759a..e73ad03 100644
> > --- a/Kconfig
> > +++ b/Kconfig
> > @@ -183,6 +183,11 @@ config FIT
> >   verified boot (secure boot using RSA). This option enables that
> >   feature.
> >
> > +config SPL_FIT
> > +   bool "Support Flattened Image Tree within SPL"
> > +   depends on FIT
> > +   depends on SPL
> > +
> >  config FIT_VERBOSE
> > bool "Display verbose messages on FIT boot"
> > depends on FIT
> > @@ -205,6 +210,12 @@ config FIT_SIGNATURE
> >   format support in this case, enable it using
> >   CONFIG_IMAGE_FORMAT_LEGACY.
> >
> > +config SPL_FIT_SIGNATURE
> > +   bool "Enable signature verification of FIT firmware within SPL"
> > +   depends on SPL_FIT
> > +   depends on SPL_DM
> > +   select SPL_RSA
> > +
> >  config FIT_BEST_MATCH
> > bool "Select the best match for the kernel device tree"
> > depends on FIT
> > diff --git a/common/Makefile b/common/Makefile
> > index b23f312..271f633 100644
> > --- a/common/Makefile
> > +++ b/common/Makefile
> > @@ -91,6 +91,7 @@ obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
> >  endif # !CONFIG_SPL_BUILD
> >
> >  ifdef CONFIG_SPL_BUILD
> > +obj-$(CONFIG_SPL_HASH_SUPPORT) += hash.o
> >  obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
> >  obj-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o
> >  obj-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o
> > diff --git a/drivers/Makefile b/drivers/Makefile
> > index 6900097..456492f 100644
> > --- a/drivers/Makefile
> > +++ b/drivers/Makefile
> > @@ -10,6 +10,7 @@ obj-$(CONFIG_$(SPL_)RAM)  += ram/
> >
> >  ifdef CONFIG_SPL_BUILD
> >
> > +obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
> >  obj-$(CONFIG_SPL_I2C_SUPPORT) += i2c/
> >  obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/
> >  obj-$(CONFIG_SPL_MMC_SUPPORT) += mmc/
> > diff --git a/drivers/crypto/rsa_mod_exp/mod_exp_sw.c 
> > b/drivers/crypto/rsa_mod_exp/mod_exp_sw.c
> > index dc6c064..56d7e89 100644
> > --- a/drivers/crypto/rsa_mod_exp/mod_exp_sw.c
> > +++ b/drivers/crypto/rsa_mod_exp/mod_exp_sw.c
> > @@ -32,6 +32,7 @@ U_BOOT_DRIVER(mod_exp_sw) = {
> > .name   = "mod_exp_sw",
> > .id = UCLASS_MOD_EXP,
> > .ops= _exp_ops_sw,
> > +   .flags  = DM_FLAG_PRE_RELOC,
> >  };
> >
> >  U_BOOT_DEVICE(mod_exp_sw) = {
> > diff --git a/lib/Makefile b/lib/Makefile
> > index 02dfa29..5c83e32 100644
> > --- 

Re: [U-Boot] [PATCH V2 01/15] imx-common: introduce simpler macros for runtime dection

[Stefano Babic]

Hi Peng,

On 23/05/2016 12:35, Peng Fan wrote:
> Introduce simpler macros for runtime cpu dection.
> 
> Signed-off-by: Peng Fan 
> Cc: Stefano Babic 
> ---
>  arch/arm/include/asm/imx-common/sys_proto.h | 8 
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm/include/asm/imx-common/sys_proto.h 
> b/arch/arm/include/asm/imx-common/sys_proto.h
> index 386c2dc..32f95b3 100644
> --- a/arch/arm/include/asm/imx-common/sys_proto.h
> +++ b/arch/arm/include/asm/imx-common/sys_proto.h
> @@ -24,7 +24,15 @@
>  #define is_cpu_type(cpu) (get_cpu_type() == cpu)
>  #define is_soc_type(soc) (get_soc_type() == soc)
>  
> +#define is_mx6() (is_soc_type(MXC_SOC_MX6))
> +#define is_mx7() (is_soc_type(MXC_SOC_MX7))
> +
>  #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || 
> is_cpu_type(MXC_CPU_MX6DP))
> +#define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
> +#define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || 
> is_cpu_type(MXC_CPU_MX6DL))
> +#define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX))
> +#define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
> +#define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
>  
>  u32 get_nr_cpus(void);
>  u32 get_cpu_rev(void);
> 

Acked-by: Stefano Babic 

Whole patchset set in my queue to be merged.

Regards,
Stefano


-- 
=
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
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Re: [U-Boot] Sharing code between Linux and bootloader (U-boot) ?

[Sebastian Frias]

Hi Tom,

On 05/21/2016 03:41 AM, Tom Rini wrote:
> On Fri, May 20, 2016 at 04:28:23PM +0200, Sebastian Frias wrote:
> 
>> Hi,
>>
>> Some bootloaders (like U-boot) support several HW devices: serial,
>> network, NAND, USB, etc. most of which are also supported by Linux.
>>
>> So the question is: is code shared? I mean, I understand that the
>> drivers need to talk to the appropriate API, and such API could be
>> different between Linux and U-boot.
>> But putting that aside, would it be naive to imagine that some "core"
>> functionality could be shared? Or would that part be so small it is
>> not worth the effort?
>>
>> Since many companies use both, U-boot and Linux, I would figure they
>> try their best to optimize engineering resources and share code,
>> right?
>> In that case, I also wonder how do they share DT descriptions that
>> right now are being stored in the Linux kernel tree.
>>
>> We'd like to share code/DT for obvious reasons, what would you guys
>> suggest?
> 
> So, in all cases, Linux is always the primary.  

For drivers and DT?

>In some cases in U-Boot
> we port drivers over (NAND is a good example here). 

>From your message, I get that first you write the driver for Linux and then 
>port to U-boot, is that right?
I would have thought that the opposite way could be easier, since the U-boot 
driver could be simpler (maybe no DMA) w.r.t the one in Linux.

> In other cases,
> things are similar enough that it's having done it in one place it's
> easy enough to do it again in the other.
> 

So, basically people just do it again, duplicating code?

Best regards,

Sebastian
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Re: [U-Boot] [PATCH v3 01/11] ARM: PSCI: change PSCI function IDs base and offsets

[Mark Rutland]

On Wed, May 18, 2016 at 05:10:24PM +0800, macro.wav...@gmail.com wrote:
> From: Wang Dongsheng 
> 
> According to PSCI specification v1.0, the PSCI functions should start from
> 0x8400 for SMC32, this patch changes this base value as well as other
> function offset values.

I agree that these are the correct valeus for PSCI 0.2, and we must use
those IDs for PSCI 0.2+.

However, this code is also used on platforms using PSCI 0.1, which did
not have well-defined IDs, and relied on them being described in the DT.
I fear that this may have the unintended sonequence of breaking those.

Does U-Boot patch the DT with the correct IDs per the PSCI 0.1 binding?
If so, then things are fine.

Thanks,
Mark.

> Signed-off-by: Wang Dongsheng 
> Signed-off-by: Hongbo Zhang 
> ---
>  arch/arm/include/asm/psci.h | 10 +-
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
> index 128a606..a4a19e3 100644
> --- a/arch/arm/include/asm/psci.h
> +++ b/arch/arm/include/asm/psci.h
> @@ -19,13 +19,13 @@
>  #define __ARM_PSCI_H__
>  
>  /* PSCI interface */
> -#define ARM_PSCI_FN_BASE 0x95c1ba5e
> +#define ARM_PSCI_FN_BASE 0x8400
>  #define ARM_PSCI_FN(n)   (ARM_PSCI_FN_BASE + (n))
>  
> -#define ARM_PSCI_FN_CPU_SUSPEND  ARM_PSCI_FN(0)
> -#define ARM_PSCI_FN_CPU_OFF  ARM_PSCI_FN(1)
> -#define ARM_PSCI_FN_CPU_ON   ARM_PSCI_FN(2)
> -#define ARM_PSCI_FN_MIGRATE  ARM_PSCI_FN(3)
> +#define ARM_PSCI_FN_CPU_SUSPEND  ARM_PSCI_FN(1)
> +#define ARM_PSCI_FN_CPU_OFF  ARM_PSCI_FN(2)
> +#define ARM_PSCI_FN_CPU_ON   ARM_PSCI_FN(3)
> +#define ARM_PSCI_FN_MIGRATE  ARM_PSCI_FN(5)
>  
>  #define ARM_PSCI_RET_SUCCESS 0
>  #define ARM_PSCI_RET_NI  (-1)
> -- 
> 2.1.4
> 
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Re: [U-Boot] [PATCH 1/3] SPL: Let spl_parse_image_header() return value

[Suman Anna]

On 05/20/2016 07:22 PM, Fabio Estevam wrote:
> On Fri, May 20, 2016 at 6:56 PM, Nishanth Menon  wrote:
>> Marek,
>>
>> Just forwarding report from Suman (in CC) reporting that as of u-boot
>> master 4b6e1fd "Merge git://git.denx.de/u-boot-dm"
>> It looks like BeagleBoard-X15, DRA7 platforms fail due to this commit.
>> Fail signature looks like the following:
>> ...
>> DRA752 ES2.0
>> Trying to boot from MMC1
>> reading args
>> spl_load_image_fat_os: error reading image args, err - -1
>> reading u-boot.img
>> spl_load_image_fat: error reading image u-boot.img, err - 0
>> Failed to mount ext2 filesystem...
>> spl_load_image_ext_os: ext4fs mount err - 0
>> Failed to mount ext2 filesystem...
>> spl_load_image_ext: ext4fs mount err - 0
> 
> Looks like this can be fixed with this patch from Marek:
> https://patchwork.ozlabs.org/patch/624267/

Thanks Fabio for pointing out the fix. I have verified that this patch
fixes the boot on both the above platforms.

regards
Suman

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[U-Boot] [PATCHv4 1/7] armv8: fsl-layerscape: add i/d-cache enable function to enable_caches

[Zhiqiang Hou]

From: Hou Zhiqiang 

This function assume that the d-cache and MMU has been enabled earlier,
so it just created MMU table in main memory. But the assumption is not
always correct, for example, the early setup is done in EL3, while
enable_caches() is called when the PE has turned into another EL.

Define the function mmu_setup() for fsl-layerscape to cover the weak
one.

Signed-off-by: Hou Zhiqiang 
---
V4:
 - no change

 arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 14 ++
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index d939900..672a453 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -425,15 +425,21 @@ int arch_cpu_init(void)
return 0;
 }
 
+void mmu_setup(void)
+{
+   final_mmu_setup();
+}
+
 /*
- * This function is called from lib/board.c.
- * It recreates MMU table in main memory. MMU and d-cache are enabled earlier.
- * There is no need to disable d-cache for this operation.
+ * This function is called from common/board_r.c.
+ * It recreates MMU table in main memory.
  */
 void enable_caches(void)
 {
-   final_mmu_setup();
+   mmu_setup();
__asm_invalidate_tlb_all();
+   icache_enable();
+   dcache_enable();
 }
 #endif
 
-- 
2.1.0.27.g96db324

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Re: [U-Boot] [PATCH v4 4/4] dm: test: Add GPIO open drain tests

[Simon Glass]

Hi Mario,

On 23 May 2016 at 01:08, Mario Six  wrote:
> Add some tests for the new open drain setting feature of the GPIO
> uclass, and extend the capabilities of the sandbox GPIO driver
> accordingly.
>
> Signed-off-by: Mario Six 
> ---
>
> v4:
> Patch added
>
> ---
>  drivers/gpio/sandbox.c | 35 +++
>  test/dm/gpio.c |  7 +++
>  2 files changed, 42 insertions(+)
>
> diff --git a/drivers/gpio/sandbox.c b/drivers/gpio/sandbox.c
> index a9b1efc..f6435a0 100644
> --- a/drivers/gpio/sandbox.c
> +++ b/drivers/gpio/sandbox.c
> @@ -15,6 +15,7 @@ DECLARE_GLOBAL_DATA_PTR;
>  /* Flags for each GPIO */
>  #define GPIOF_OUTPUT   (1 << 0)/* Currently set as an output */
>  #define GPIOF_HIGH (1 << 1)/* Currently set high */
> +#define GPIOF_ODR  (1 << 2)/* Currently set to open drain mode */
>
>  struct gpio_state {
> const char *label;  /* label given by requester */
> @@ -70,6 +71,16 @@ int sandbox_gpio_set_value(struct udevice *dev, unsigned 
> offset, int value)
> return set_gpio_flag(dev, offset, GPIOF_HIGH, value);
>  }
>
> +int sandbox_gpio_get_open_drain(struct udevice *dev, unsigned offset)
> +{
> +   return get_gpio_flag(dev, offset, GPIOF_ODR);
> +}
> +
> +int sandbox_gpio_set_open_drain(struct udevice *dev, unsigned offset, int 
> value)
> +{
> +   return set_gpio_flag(dev, offset, GPIOF_ODR, value);
> +}
> +
>  int sandbox_gpio_get_direction(struct udevice *dev, unsigned offset)
>  {
> return get_gpio_flag(dev, offset, GPIOF_OUTPUT);
> @@ -124,6 +135,28 @@ static int sb_gpio_set_value(struct udevice *dev, 
> unsigned offset, int value)
> return sandbox_gpio_set_value(dev, offset, value);
>  }
>
> +/* read GPIO ODR value of port 'offset' */
> +static int sb_gpio_get_open_drain(struct udevice *dev, unsigned offset)
> +{
> +   debug("%s: offset:%u\n", __func__, offset);
> +
> +   return sandbox_gpio_get_open_drain(dev, offset);
> +}
> +
> +/* write GPIO ODR value to port 'offset' */
> +static int sb_gpio_set_open_drain(struct udevice *dev, unsigned offset, int 
> value)
> +{
> +   debug("%s: offset:%u, value = %d\n", __func__, offset, value);
> +
> +   if (!sandbox_gpio_get_direction(dev, offset)) {
> +   printf("sandbox_gpio: error: set_open_drain on input gpio 
> %u\n",
> +  offset);
> +   return -1;
> +   }
> +
> +   return sandbox_gpio_set_open_drain(dev, offset, value);
> +}
> +
>  static int sb_gpio_get_function(struct udevice *dev, unsigned offset)
>  {
> if (get_gpio_flag(dev, offset, GPIOF_OUTPUT))
> @@ -154,6 +187,8 @@ static const struct dm_gpio_ops gpio_sandbox_ops = {
> .direction_output   = sb_gpio_direction_output,
> .get_value  = sb_gpio_get_value,
> .set_value  = sb_gpio_set_value,
> +   .get_open_drain = sb_gpio_get_open_drain,
> +   .set_open_drain = sb_gpio_set_open_drain,
> .get_function   = sb_gpio_get_function,
> .xlate  = sb_gpio_xlate,
>  };
> diff --git a/test/dm/gpio.c b/test/dm/gpio.c
> index 727db18..4779b5a 100644
> --- a/test/dm/gpio.c
> +++ b/test/dm/gpio.c
> @@ -75,6 +75,13 @@ static int dm_test_gpio(struct unit_test_state *uts)
> ut_assertok(ops->set_value(dev, offset, 1));
> ut_asserteq(1, ops->get_value(dev, offset));
>
> +   /* Make it an open drain output, and reset it */
> +   ut_asserteq(0, ops->get_open_drain(dev, offset));
> +   ut_assertok(ops->set_open_drain(dev, offset, 1));
> +   ut_asserteq(1, ops->get_open_drain(dev, offset));
> +   ut_assertok(ops->set_open_drain(dev, offset, 0));
> +   ut_asserteq(0, ops->get_open_drain(dev, offset));

Instead of reading back from the driver, you should call
sandbox_gpio_get_open_drain() here. The idea is to set the value
through the API, then check (via the back door sandbox functions) that
it happened.

> +
> /* Make it an input */
> ut_assertok(ops->direction_input(dev, offset));
> ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf)));
> --
> 2.7.0.GIT
>

Regards,
Simon
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Re: [U-Boot] [PATCH] ARM: OMAP4+: Fix DPLL programming sequence

[Nishanth Menon]

On 05/23/2016 03:01 AM, Lokesh Vutla wrote:
> All the output clock parameters of a DPLL needs to be programmed before
> locking the DPLL. But it is being configured after locking the DPLL which
> could potentially bypass DPLL. So fixing this sequence.
> 
> Reported-by: Richard Woodruff 
> Signed-off-by: Lokesh Vutla 
> ---
>  arch/arm/cpu/armv7/omap-common/clocks-common.c | 8 +---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c 
> b/arch/arm/cpu/armv7/omap-common/clocks-common.c
> index ef2ac98..2de9935 100644
> --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
> +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
> @@ -236,6 +236,8 @@ static void do_setup_dpll(u32 const base, const struct 
> dpll_params *params,
>   /* Dpll locked with ideal values for nominal opps. */
>   debug("\n %s Dpll already locked with ideal"
>   "nominal opp values", dpll);
> +
> + bypass_dpll(base);
>   goto setup_post_dividers;
>   }
>   }
> @@ -251,13 +253,13 @@ static void do_setup_dpll(u32 const base, const struct 
> dpll_params *params,
>  
>   writel(temp, _regs->cm_clksel_dpll);
>  
> +setup_post_dividers:
> + setup_post_dividers(base, params);
> +
>   /* Lock */
>   if (lock)
>   do_lock_dpll(base);
>  
> -setup_post_dividers:
> - setup_post_dividers(base, params);
> -
>   /* Wait till the DPLL locks */
>   if (lock)
>   wait_for_lock(base);
> 

LGTM
Reviewed-by: Nishanth Menon 

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Re: [U-Boot] [PATCH v4 1/4] dm: gpio: Add driver for MPC85XX GPIO controller

[Simon Glass]

On 23 May 2016 at 01:08, Mario Six  wrote:
>
> From: "mario@gdsys.cc" 
>
> This patch adds a driver for the built-in GPIO controller of the MPC85XX
> SoC (probably supporting other PowerQUICC III SoCs as well).
>
> Each GPIO bank is identified by its own entry in the device tree, i.e.
>
> gpio-controller@fc00 {
>   #gpio-cells = <2>;
>   compatible = "fsl,pq3-gpio";
>   reg = <0xfc00 0x100>
> }
>
> By default, each bank is assumed to have 32 GPIOs, but the ngpios
> setting is honored, so the number of GPIOs for each bank in configurable
> to match the actual GPIO count of the SoC (e.g. the 32/32/23 banks of
> the P1022 SoC).
>
> The usual functions of GPIO drivers (setting input/output mode and output
> value setting) are supported.
>
> The driver has been tested on MPC85XX, but it is likely that other
> PowerQUICC III devices will work as well.
>
> Signed-off-by: Mario Six 
> ---
>
> v4:
> None
>
> v3:
> - Added shadow for the GPDAT register, as suggested by Joakim Tjernlund
> - Switched to u32 for bit masks
> - Added some comments
>
> v2:
> - Added missing commit message
> - Improved the Kconfig description
> - Fixed and documented the mpc85xx_gpio_data members
> - Introduced GPIO_MASK macro to simplify the code
> - Fixed white space issues in function headers
> - Removed unnecessary empty line
> - Use fdtdec_get_addr_size_auto_noparent to read the register base data
>
> ---
>  arch/powerpc/include/asm/arch-mpc85xx/gpio.h |   2 +
>  arch/powerpc/include/asm/immap_85xx.h|   2 +
>  drivers/gpio/Kconfig |  25 
>  drivers/gpio/Makefile|   1 +
>  drivers/gpio/mpc85xx_gpio.c  | 187 
> +++
>  5 files changed, 217 insertions(+)
>  create mode 100644 drivers/gpio/mpc85xx_gpio.c

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH V2] Add a mailbox driver framework/uclass

[Simon Glass]

On 14 May 2016 at 13:33, Simon Glass  wrote:
> On 13 May 2016 at 15:50, Stephen Warren  wrote:
>> From: Stephen Warren 
>>
>> A mailbox is a hardware mechanism for transferring small message and/or
>> notifications between the CPU on which U-Boot runs and some other device
>> such as an auxilliary CPU running firmware or a hardware module.
>>
>> This patch defines a standard API that connects mailbox clients to mailbox
>> providers (drivers). Initially, DT is the only supported method for
>> connecting the two.
>>
>> The DT binding specification (mailbox.txt) was taken from Linux kernel
>> v4.5's Documentation/devicetree/bindings/mailbox/mailbox.txt.
>>
>> Signed-off-by: Stephen Warren 
>> ---
>> v2:
>> * Use timer_get_us() rather than get_ticks() and conversion code.
>> * Explicitly mention that mailbox messages are fixed size.
>> * Spell out IPC.
>> * Fix typos.
>>
>> I'll send a sandbox test for this as a separate patch.
>>
>>  doc/device-tree-bindings/mailbox/mailbox.txt |  32 ++
>>  drivers/Kconfig  |   2 +
>>  drivers/Makefile |   1 +
>>  drivers/mailbox/Kconfig  |  13 +++
>>  drivers/mailbox/Makefile |   5 +
>>  drivers/mailbox/mailbox-uclass.c | 145 
>> ++
>>  include/dm/uclass-id.h   |   1 +
>>  include/mailbox_client.h | 149 
>> +++
>>  include/mailbox_uclass.h |  83 +++
>>  9 files changed, 431 insertions(+)
>>  create mode 100644 doc/device-tree-bindings/mailbox/mailbox.txt
>>  create mode 100644 drivers/mailbox/Kconfig
>>  create mode 100644 drivers/mailbox/Makefile
>>  create mode 100644 drivers/mailbox/mailbox-uclass.c
>>  create mode 100644 include/mailbox_client.h
>>  create mode 100644 include/mailbox_uclass.h
>
> Acked-by: Simon Glass 

Applied to u-boot-dm, thanks!
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Re: [U-Boot] [PATCH v3 02/11] arm: rpi: Define CONFIG_TFTP_TSIZE to show tftp size info

[Simon Glass]

On 10 August 2015 at 21:58, Stephen Warren  wrote:
> On 08/07/2015 07:42 AM, Simon Glass wrote:
>> This shows a proper progress display and the total amount of data
>> transferred. Enable it for Raspberry Pi.
>
> Acked-by: Stephen Warren 

Applied to u-boot-dm.
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Re: [U-Boot] [PATCH] Rename reset to sysreset

[Simon Glass]

On 14 May 2016 at 15:23, Simon Glass  wrote:
> On 12 May 2016 at 12:03, Stephen Warren  wrote:
>> The current reset API implements a method to reset the entire system.
>> In the near future, I'd like to introduce code that implements the device
>> tree reset bindings; i.e. the equivalent of the Linux kernel's reset API.
>> This controls resets to individual HW blocks or external chips with reset
>> signals. It doesn't make sense to merge the two APIs into one since they
>> have different semantic purposes. Resolve the naming conflict by renaming
>> the existing reset API to sysreset instead, so the new reset API can be
>> called just reset.
>>
>> Signed-off-by: Stephen Warren 
>> ---
>>  arch/arm/lib/Makefile  |  2 +-
>>  arch/arm/mach-rockchip/rk3036/reset_rk3036.c   | 20 +++---
>>  arch/arm/mach-rockchip/rk3288/reset_rk3288.c   | 20 +++---
>>  arch/arm/mach-snapdragon/reset.c   | 18 ++---
>>  arch/sandbox/cpu/state.c   |  4 +-
>>  arch/sandbox/include/asm/state.h   |  6 +-
>>  configs/chromebook_jerry_defconfig |  2 +-
>>  configs/dragonboard410c_defconfig  |  2 +-
>>  configs/evb-rk3036_defconfig   |  2 +-
>>  configs/firefly-rk3288_defconfig   |  2 +-
>>  configs/kylin-rk3036_defconfig |  2 +-
>>  configs/rock2_defconfig|  2 +-
>>  configs/sandbox_defconfig  |  2 +-
>>  drivers/clk/clk_rk3036.c   |  2 +-
>>  drivers/clk/clk_rk3288.c   |  2 +-
>>  drivers/misc/Kconfig   | 10 +--
>>  drivers/misc/Makefile  |  4 +-
>>  drivers/misc/{reset-uclass.c => sysreset-uclass.c} | 32 -
>>  .../misc/{reset_sandbox.c => sysreset_sandbox.c}   | 61 +
>>  include/dm/uclass-id.h |  2 +-
>>  include/{reset.h => sysreset.h}| 42 ++--
>>  test/dm/Makefile   |  2 +-
>>  test/dm/{reset.c => sysreset.c}| 80 
>> +++---
>>  23 files changed, 161 insertions(+), 160 deletions(-)
>>  rename drivers/misc/{reset-uclass.c => sysreset-uclass.c} (55%)
>>  rename drivers/misc/{reset_sandbox.c => sysreset_sandbox.c} (46%)
>>  rename include/{reset.h => sysreset.h} (47%)
>>  rename test/dm/{reset.c => sysreset.c} (16%)
>
> Acked-by: Simon Glass 

Applied to u-boot-dm, thanks!
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Re: [U-Boot] [PATCH V2 2/2] sunxi: gpio: convert bind() to use driver data

[Simon Glass]

On 12 May 2016 at 20:42, Simon Glass  wrote:
> Hi Hans,
>
> On 12 May 2016 at 11:51, Hans de Goede  wrote:
>> Hi,
>>
>>
>> On 12-05-16 19:50, Stephen Warren wrote:
>>>
>>> On 05/12/2016 11:43 AM, Simon Glass wrote:

 Hi Stephen,

 On 11 May 2016 at 15:26, Stephen Warren  wrote:
>
> From: Stephen Warren 
>
> Now that the DM core sets driver_data before calling bind(), this driver
> can make use of driver_data to determine the set of child devices to
> create, rather than manually re-implementing the matching logic in code.
>>>
>>>
> diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
>>>
>>>
> +#define ID(_compat_, _soc_data_) \
> +   { .compatible = _compat_, .data = (ulong)_data_##_soc_data_
> }
> +
>   static const struct udevice_id sunxi_gpio_ids[] = {
> -   { .compatible = "allwinner,sun4i-a10-pinctrl" },
> -   { .compatible = "allwinner,sun5i-a10s-pinctrl" },
> -   { .compatible = "allwinner,sun5i-a13-pinctrl" },
>>>
>>> ...
>
> +   ID("allwinner,sun4i-a10-pinctrl",   a_all),
> +   ID("allwinner,sun5i-a10s-pinctrl",  a_all),


 I don't think the #define adds a lot of value - consider removing it
 an writing things out in full?
>>>
>>>
>>> I originally did that, but you either end up with lines over 80 columns
>>> which checkpatch complains about, or multiple lines per entry which makes it
>>> harder to read for such a large table. Still, I can convert it if you want.
>>
>>
>> I'm fine with keeping the ID define:
>>
>> Reviewed-by: Hans de Goede 
>>
>> Simon, I assume that you will upstream this one through your
>> tree ?
>
> Yes, thanks.
>
> Regards,
> Simon

Applied to u-boot-dm, thanks!
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Re: [U-Boot] [PATCH V2 1/2] dm: allow setting driver_data before/during bind

[Simon Glass]

On 12 May 2016 at 11:43, Simon Glass  wrote:
> On 11 May 2016 at 15:26, Stephen Warren  wrote:
>> From: Stephen Warren 
>>
>> This will allow a driver's bind function to use the driver data. One
>> example is the Tegra186 GPIO driver, which instantiates child devices
>> for each of its GPIO ports, yet supports two different HW instances each
>> with a different set of ports, and identified by the udevice_id .data
>> field.
>>
>> Signed-off-by: Stephen Warren 
>> ---
>> v2:
>> * Introduce a separate function for the new functionality, rather than
>> modifying device_bind().
>>
>> This patch is a dependency for the upcoming Tegra186 GPIO driver too.
>> ---
>>  doc/driver-model/README.txt  | 23 ++-
>>  drivers/core/device.c| 25 ++---
>>  drivers/core/lists.c |  4 ++--
>>  include/dm/device-internal.h | 24 
>>  4 files changed, 62 insertions(+), 14 deletions(-)
>
> Thanks.
>
> Acked-by: Simon Glass 

Applied to u-boot-dm, thanks!
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Re: [U-Boot] [PATCH] driver/ddr/fsl: Force enabling parity for A-009803

[York Sun]

On 05/23/2016 02:18 AM, Shengzhou Liu wrote:
>> -Original Message-
>> From: York Sun [mailto:york@nxp.com]
>> Sent: Friday, May 20, 2016 11:29 PM
>> To: Shengzhou Liu ; u-boot@lists.denx.de
>> Subject: Re: [PATCH] driver/ddr/fsl: Force enabling parity for A-009803
>>>
>>
>> Shengzhou,
>>
>> It looks backward. You should detect if the condition is right before
>> applying the workaround, not by forcing the condition.
>>
>> York
> 
> If ERRATUM_A009803 is defined, ap_en should always be enabled whatever user 
> configures parity=on in hwconfig.
> As ERRATUM_A009803 is enabled only in arch-fsl-layerscape/config.h for LS2 
> SoC, I don't think we need to check anything other.
> What condition do you mean? 
> 

Shengzhou,

My point is you should force ap=1. Do you mean if ERRATUM_A009803 is enabled,
users are forced to use address parity? That doesn't sound right. We have been
running UDIMM without address parity for a long time.

York


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[U-Boot] [PATCH 1/4] imx: ventana: config: remove redundant config

[Tim Harvey]

remove redundant define that exists in mx6_common.h

Signed-off-by: Tim Harvey 
---
 include/configs/gw_ventana.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index e11629c..8d689f1 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -52,9 +52,6 @@
 #define CONFIG_DM_THERMAL
 #endif
 
-/* GPIO */
-#define CONFIG_MXC_GPIO
-
 /* Thermal */
 #define CONFIG_IMX_THERMAL
 
-- 
1.9.1

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[U-Boot] [PATCH 0/4] Fix Gateworks Ventana build

[Tim Harvey]

The SPL has recently grown in size and causes a buid failure for the Gateworks
Ventana board. This series addresses this by removing a couple of features
not necessary for Ventana as well as one simple cleanup.

Tim Harvey (4):
  imx: ventana: config: remove redundant config
  imx: ventana: gsc: remove dependence on env
  imx: ventana: use EEPROM register for falcon boot mode
  imx: ventana: remove SPL_EXT_SUPPORT

 board/gateworks/gw_ventana/README   | 17 ++---
 board/gateworks/gw_ventana/gsc.c|  4 ++--
 board/gateworks/gw_ventana/gw_ventana_spl.c |  7 ++-
 include/configs/gw_ventana.h|  5 +
 4 files changed, 15 insertions(+), 18 deletions(-)

-- 
1.9.1

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[U-Boot] [PATCH 3/4] imx: ventana: use EEPROM register for falcon boot mode

[Tim Harvey]

NAND+MMC env support costs 12KB in the SPL which is fairly expensive just
for the ability to specify whether or not to boot to uboot or directly
to linux. The Ventana boards have plenty of EEPROM storage so we will use
a byte there to signify if we should boot to the bootloader or to the OS.

Signed-off-by: Tim Harvey 
---
 board/gateworks/gw_ventana/README   | 17 ++---
 board/gateworks/gw_ventana/gw_ventana_spl.c |  7 ++-
 include/configs/gw_ventana.h|  1 -
 3 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/board/gateworks/gw_ventana/README 
b/board/gateworks/gw_ventana/README
index 9418907..f3f8998 100644
--- a/board/gateworks/gw_ventana/README
+++ b/board/gateworks/gw_ventana/README
@@ -173,13 +173,8 @@ OS load time which defeats the purpose of Falcon mode in 
the first place.
 The SPL decides to boot either U-Boot (u-boot.img) or the OS (args + kernel)
 based on the return value of the spl_start_uboot() function. While often
 this can simply be the state of a GPIO based pushbutton or DIP switch, for
-Gateworks Ventana, we use the U-Boot environment 'boot_os' variable which if
-set to '1' will choose to boot the OS rather than U-Boot. While the choice
-of adding env support to the SPL adds a little bit of time to the boot
-process as well as (significant really) SPL code space this was deemed most
-flexible as within the large variety of Gateworks Ventana boards not all of
-them have a user pushbutton and that pushbutton may be configured as a hard
-reset per user configuration.
+Gateworks Ventana, we use an EEPROM register on i2c-0 at 0x50:0x00:
+set to '0' will choose to boot to U-Boot and otherwise it will boot to OS.
 
 To use Falcon mode it is required that you first 'prepare' the 'args' data
 that is stored on your boot medium along with the kernel (which can be any
@@ -235,8 +230,8 @@ using rootfs (ubi), kernel (uImage), and dtb from the 
network:
  # flash args (at 17MB)
  Ventana > nand erase.part args && nand write 1800 args 10
 
- # set boot_os env var to enable booting to Linux
- Ventana > setenv boot_os 1 && saveenv
+ # set i2c register 0x50:0x00=0 to boot to Linux
+ Ventana > i2c dev 0 && i2c mw 0x50 0x00.0 0 1
 
 Be sure to adjust 'bootargs' above to your OS needs (this will be different
 for various distros such as OpenWrt, Yocto, Android, etc). You can use the
@@ -309,8 +304,8 @@ out in U-Boot and use the following to enable Falcon mode:
  # write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)
  Ventana > mmc write 1800 0x800 0x800
 
- # set boot_os to enable falcon mode
- Ventana > setenv boot_os 1 && saveenv
+ # set i2c register 0x50:0x00=0 to boot to Linux
+ Ventana > i2c dev 0 && i2c mw 0x50 0x00.0 0 1
 
 Be sure to adjust 'bootargs' above to your OS needs (this will be different
 for various distros such as OpenWrt, Yocto, Android, etc). You can use the
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c 
b/board/gateworks/gw_ventana/gw_ventana_spl.c
index 0a6ad47..ed42b86 100644
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include "gsc.h"
@@ -560,7 +561,7 @@ void spl_board_init(void)
 /* return 1 if we wish to boot to uboot vs os (falcon mode) */
 int spl_start_uboot(void)
 {
-   int ret = 1;
+   unsigned char ret = 1;
 
debug("%s\n", __func__);
 #ifdef CONFIG_SPL_ENV_SUPPORT
@@ -569,6 +570,10 @@ int spl_start_uboot(void)
debug("boot_os=%s\n", getenv("boot_os"));
if (getenv_yesno("boot_os") == 1)
ret = 0;
+#else
+   /* use i2c-0:0x50:0x00 for falcon boot mode (0=linux, else uboot) */
+   i2c_set_bus_num(0);
+   gsc_i2c_read(0x50, 0x0, 1, , 1);
 #endif
debug("%s booting %s\n", __func__, ret ? "uboot" : "linux");
return ret;
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 8d689f1..c8d3cb8 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -18,7 +18,6 @@
 /* Falcon Mode */
 #define CONFIG_CMD_SPL
 #define CONFIG_SPL_OS_BOOT
-#define CONFIG_SPL_ENV_SUPPORT
 #define CONFIG_SYS_SPL_ARGS_ADDR   0x1800
 #define CONFIG_CMD_SPL_WRITE_SIZE  (128 * SZ_1K)
 
-- 
1.9.1

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[U-Boot] [PATCH 4/4] imx: ventana: remove SPL_EXT_SUPPORT

[Tim Harvey]

Remove SPL_EXT_SUPPORT to resolve build issue. It may be useful to bring
it back in the future after comparing its merits to storing the args/kernel
in fixed raw locations.

Signed-off-by: Tim Harvey 
---
 include/configs/gw_ventana.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index c8d3cb8..874bb04 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -32,6 +32,7 @@
 
 #include "imx6_spl.h"  /* common IMX6 SPL configuration */
 #include "mx6_common.h"
+#undef CONFIG_SPL_EXT_SUPPORT
 
 #define CONFIG_MACH_TYPE   4520   /* Gateworks Ventana Platform */
 
-- 
1.9.1

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[U-Boot] [PATCH 2/4] imx: ventana: gsc: remove dependence on env

[Tim Harvey]

remove dependence on getenv() by using global board info struct for model.

Signed-off-by: Tim Harvey 
---
 board/gateworks/gw_ventana/gsc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c
index 3febd12..4f26bfd 100644
--- a/board/gateworks/gw_ventana/gsc.c
+++ b/board/gateworks/gw_ventana/gsc.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 
+#include "ventana_eeprom.h"
 #include "gsc.h"
 
 /*
@@ -79,7 +80,6 @@ static void read_hwmon(const char *name, uint reg, uint size)
 
 int gsc_info(int verbose)
 {
-   const char *model = getenv("model");
unsigned char buf[16];
 
i2c_set_bus_num(0);
@@ -112,7 +112,7 @@ int gsc_info(int verbose)
read_hwmon("VDD_2P5",  GSC_HWMON_VDD_2P5, 3);
read_hwmon("VDD_1P8",  GSC_HWMON_VDD_1P8, 3);
read_hwmon("VDD_IO2",  GSC_HWMON_VDD_IO2, 3);
-   switch (model[3]) {
+   switch (ventana_info.model[3]) {
case '1': /* GW51xx */
read_hwmon("VDD_IO3",  GSC_HWMON_VDD_IO4, 3); /* -C rev */
break;
-- 
1.9.1

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[U-Boot] [u-boot][PATCH v2 1/4] ARM: OMAP5+: Provide enable/disable_usb_clocks() for CONFIG_USB_XHCI_OMAP

[Roger Quadros]

CONFIG_USB_XHCI_OMAP is enabled for host mode independent of CONFIG_USB_DWC3
which is meant for gadget mode only. We need enable/disbale_usb_clocks() for
host mode as well so provide for it.

Fixes: 09cc14f4bcbf ("ARM: AM43xx: Add functions to enable and disable USB 
clocks"
Signed-off-by: Roger Quadros 
---
 arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 2 +-
 arch/arm/cpu/armv7/omap5/hw_data.c   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c 
b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index 5c2a2ab..73ea955 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -160,7 +160,7 @@ void disable_edma3_clocks(void)
 }
 #endif
 
-#ifdef CONFIG_USB_DWC3
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 void enable_usb_clocks(int index)
 {
u32 *usbclkctrl = 0;
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c 
b/arch/arm/cpu/armv7/omap5/hw_data.c
index 88e8920..8734815 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -602,7 +602,7 @@ void disable_edma3_clocks(void)
 }
 #endif
 
-#ifdef CONFIG_USB_DWC3
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 void enable_usb_clocks(int index)
 {
u32 cm_l3init_usb_otg_ss_clkctrl = 0;
-- 
2.7.4

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[U-Boot] [u-boot][PATCH v2 4/4] usb: phy: omap_usb_phy: Fix USB3_PHY DPLL configuration

[Roger Quadros]

The index returned by get_sys_clk_index() is not exactly what we expect.
Let's not rely on that and use get_sys_clk_freq() instead.

This fixes missing USB3 devices in the Linux kernel when USB is started
in u-boot. It still doesn't fix missing USB3 devices in u-boot though.

Signed-off-by: Roger Quadros 
---
 drivers/usb/phy/omap_usb_phy.c | 56 +++---
 1 file changed, 41 insertions(+), 15 deletions(-)

diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c
index f9069c7..1993da1 100644
--- a/drivers/usb/phy/omap_usb_phy.c
+++ b/drivers/usb/phy/omap_usb_phy.c
@@ -23,7 +23,7 @@
 #include "../host/xhci.h"
 
 #ifdef CONFIG_OMAP_USB3PHY1_HOST
-struct usb_dpll_params {
+struct usb3_dpll_params {
u16 m;
u8  n;
u8  freq:3;
@@ -31,17 +31,39 @@ struct usb_dpll_params {
u32 mf;
 };
 
-#defineNUM_USB_CLKS6
+struct usb3_dpll_map {
+   unsigned long rate;
+   struct usb3_dpll_params params;
+   struct usb3_dpll_map *dpll_map;
+};
 
-static struct usb_dpll_params omap_usb3_dpll_params[NUM_USB_CLKS] = {
-   {1250, 5, 4, 20, 0},/* 12 MHz */
-   {3125, 20, 4, 20, 0},   /* 16.8 MHz */
-   {1172, 8, 4, 20, 65537},/* 19.2 MHz */
-   {1250, 12, 4, 20, 0},   /* 26 MHz */
-   {3125, 47, 4, 20, 92843},   /* 38.4 MHz */
-   {1000, 7, 4, 10, 0},/* 20 MHz */
+static struct usb3_dpll_map dpll_map_usb[] = {
+   {1200, {1250, 5, 4, 20, 0} },   /* 12 MHz */
+   {1680, {3125, 20, 4, 20, 0} },  /* 16.8 MHz */
+   {1920, {1172, 8, 4, 20, 65537} },   /* 19.2 MHz */
+   {2000, {1000, 7, 4, 10, 0} },   /* 20 MHz */
+   {2600, {1250, 12, 4, 20, 0} },  /* 26 MHz */
+   {3840, {3125, 47, 4, 20, 92843} },  /* 38.4 MHz */
+   { },/* Terminator */
 };
 
+static struct usb3_dpll_params *omap_usb3_get_dpll_params(void)
+{
+   unsigned long rate;
+   struct usb3_dpll_map *dpll_map = dpll_map_usb;
+
+   rate = get_sys_clk_freq();
+
+   for (; dpll_map->rate; dpll_map++) {
+   if (rate == dpll_map->rate)
+   return _map->params;
+   }
+
+   dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
+
+   return NULL;
+}
+
 static void omap_usb_dpll_relock(struct omap_usb3_phy *phy_regs)
 {
u32 val;
@@ -56,32 +78,36 @@ static void omap_usb_dpll_relock(struct omap_usb3_phy 
*phy_regs)
 
 static void omap_usb_dpll_lock(struct omap_usb3_phy *phy_regs)
 {
-   u32 clk_index = get_sys_clk_index();
+   struct usb3_dpll_params *dpll_params;
u32 val;
 
+   dpll_params = omap_usb3_get_dpll_params();
+   if (!dpll_params)
+   return;
+
val = readl(_regs->pll_config_1);
val &= ~PLL_REGN_MASK;
-   val |= omap_usb3_dpll_params[clk_index].n << PLL_REGN_SHIFT;
+   val |= dpll_params->n << PLL_REGN_SHIFT;
writel(val, _regs->pll_config_1);
 
val = readl(_regs->pll_config_2);
val &= ~PLL_SELFREQDCO_MASK;
-   val |= omap_usb3_dpll_params[clk_index].freq << PLL_SELFREQDCO_SHIFT;
+   val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
writel(val, _regs->pll_config_2);
 
val = readl(_regs->pll_config_1);
val &= ~PLL_REGM_MASK;
-   val |= omap_usb3_dpll_params[clk_index].m << PLL_REGM_SHIFT;
+   val |= dpll_params->m << PLL_REGM_SHIFT;
writel(val, _regs->pll_config_1);
 
val = readl(_regs->pll_config_4);
val &= ~PLL_REGM_F_MASK;
-   val |= omap_usb3_dpll_params[clk_index].mf << PLL_REGM_F_SHIFT;
+   val |= dpll_params->mf << PLL_REGM_F_SHIFT;
writel(val, _regs->pll_config_4);
 
val = readl(_regs->pll_config_3);
val &= ~PLL_SD_MASK;
-   val |= omap_usb3_dpll_params[clk_index].sd << PLL_SD_SHIFT;
+   val |= dpll_params->sd << PLL_SD_SHIFT;
writel(val, _regs->pll_config_3);
 
omap_usb_dpll_relock(phy_regs);
-- 
2.7.4

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[U-Boot] [u-boot][PATCH v2 2/4] ARM: AM57xx: AM43xx: Fix USB host

[Roger Quadros]

CONFIG_USB_XHCI_OMAP can be set for host mode without setting
CONFIG_USB_DWC3 which is meant for gadget mode only.
board_usb_init() was not being defined for CONFIG_USB_XHCI_OMAP
resulting in a data abort on usb start.

Define board_usb_init() for CONFIG_USB_XHCI_OMAP case. Move
gadget specific handling to within CONFIG_USB_DWC3.

Fixes: 6f1af1e358b7 ("board: ti: invoke clock API to enable and disable clocks")
Signed-off-by: Roger Quadros 
---
 board/ti/am43xx/board.c | 58 -
 board/ti/am57xx/board.c | 54 ++---
 2 files changed, 55 insertions(+), 57 deletions(-)

diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index d208d2f..1a3d70a 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -678,71 +678,71 @@ static struct ti_usb_phy_device usb_phy2_device = {
.index = 1,
 };
 
+int usb_gadget_handle_interrupts(int index)
+{
+   u32 status;
+
+   status = dwc3_omap_uboot_interrupt_status(index);
+   if (status)
+   dwc3_uboot_handle_interrupt(index);
+
+   return 0;
+}
+#endif /* CONFIG_USB_DWC3 */
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 int board_usb_init(int index, enum usb_init_type init)
 {
enable_usb_clocks(index);
+#ifdef CONFIG_USB_DWC3
switch (index) {
case 0:
if (init == USB_INIT_DEVICE) {
usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
-   } else {
-   usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
-   usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
+   dwc3_omap_uboot_init(_otg_ss1_glue);
+   ti_usb_phy_uboot_init(_phy1_device);
+   dwc3_uboot_init(_otg_ss1);
}
-
-   dwc3_omap_uboot_init(_otg_ss1_glue);
-   ti_usb_phy_uboot_init(_phy1_device);
-   dwc3_uboot_init(_otg_ss1);
break;
case 1:
if (init == USB_INIT_DEVICE) {
usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
-   } else {
-   usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
-   usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
+   ti_usb_phy_uboot_init(_phy2_device);
+   dwc3_omap_uboot_init(_otg_ss2_glue);
+   dwc3_uboot_init(_otg_ss2);
}
-
-   ti_usb_phy_uboot_init(_phy2_device);
-   dwc3_omap_uboot_init(_otg_ss2_glue);
-   dwc3_uboot_init(_otg_ss2);
break;
default:
printf("Invalid Controller Index\n");
}
+#endif
 
return 0;
 }
 
 int board_usb_cleanup(int index, enum usb_init_type init)
 {
+#ifdef CONFIG_USB_DWC3
switch (index) {
case 0:
case 1:
-   ti_usb_phy_uboot_exit(index);
-   dwc3_uboot_exit(index);
-   dwc3_omap_uboot_exit(index);
+   if (init == USB_INIT_DEVICE) {
+   ti_usb_phy_uboot_exit(index);
+   dwc3_uboot_exit(index);
+   dwc3_omap_uboot_exit(index);
+   }
break;
default:
printf("Invalid Controller Index\n");
}
+#endif
disable_usb_clocks(index);
 
return 0;
 }
-
-int usb_gadget_handle_interrupts(int index)
-{
-   u32 status;
-
-   status = dwc3_omap_uboot_interrupt_status(index);
-   if (status)
-   dwc3_uboot_handle_interrupt(index);
-
-   return 0;
-}
-#endif
+#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 
 #ifdef CONFIG_DRIVER_TI_CPSW
 
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 86b8f6e..c9165ac 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -439,6 +439,19 @@ static struct ti_usb_phy_device usb_phy2_device = {
.index = 1,
 };
 
+int usb_gadget_handle_interrupts(int index)
+{
+   u32 status;
+
+   status = dwc3_omap_uboot_interrupt_status(index);
+   if (status)
+   dwc3_uboot_handle_interrupt(index);
+
+   return 0;
+}
+#endif /* CONFIG_USB_DWC3 */
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 int board_usb_init(int index, enum usb_init_type init)
 {
enable_usb_clocks(index);
@@ -448,31 +461,23 @@ int board_usb_init(int index, enum usb_init_type init)
printf("port %d can't be used as device\n", index);
disable_usb_clocks(index);
return -EINVAL;
-   } else {
-   usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
-

[U-Boot] [u-boot][PATCH v2 0/4] am57xx: am43xx: get usb host working

[Roger Quadros]

Hi,

I was under the wrong impression earlier that CONFIG_USB_DWC3 is needed for
USB HOST operation, but it seems it is not so. Just CONFIG_XHCI_DWC3 and
CONFIG_XHCI_OMAP are sufficient to get USB host working.

So the real problem was that some offending commits didn't define
enable_usb_clocks() and board_usb_init for the XHCI host only case.

Patches 1 and 2 fix this and get USB host working on am57xx and am43xx.
NOTE: my am437xx is broken so I've only tested this on am57xx-evm.

The remaining 2 patches attempt to fix USB3 PHY to get Super-Speed
host functional but I haven't yet got Super-Speed working in u-boot.
Patch 4 does fix an issue with Kernel failing to detect Super-Speed devices.

cheers,
-roger

Roger Quadros (4):
  ARM: OMAP5+: Provide enable/disable_usb_clocks() for
CONFIG_USB_XHCI_OMAP
  ARM: AM57xx: AM43xx: Fix USB host
  dra7xx: Enable USB_PHY3 32KHz clock
  usb: phy: omap_usb_phy: Fix USB3_PHY DPLL configuration

 arch/arm/cpu/armv7/am33xx/clock_am43xx.c |  2 +-
 arch/arm/cpu/armv7/omap5/hw_data.c   | 16 +++--
 arch/arm/cpu/armv7/omap5/prcm-regs.c |  1 +
 arch/arm/include/asm/omap_common.h   |  1 +
 board/ti/am43xx/board.c  | 58 
 board/ti/am57xx/board.c  | 54 ++---
 drivers/usb/phy/omap_usb_phy.c   | 56 +-
 7 files changed, 112 insertions(+), 76 deletions(-)

-- 
2.7.4

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[U-Boot] [u-boot][PATCH v2 3/4] dra7xx: Enable USB_PHY3 32KHz clock

[Roger Quadros]

DRA7xx has a 32KHz PHY clock for USB_PHY3 that must be enabled
for USB1 instance in Super-Speed.

Signed-off-by: Roger Quadros 
---
 arch/arm/cpu/armv7/omap5/hw_data.c   | 14 --
 arch/arm/cpu/armv7/omap5/prcm-regs.c |  1 +
 arch/arm/include/asm/omap_common.h   |  1 +
 3 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c 
b/arch/arm/cpu/armv7/omap5/hw_data.c
index 8734815..fe59c25 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -614,9 +614,14 @@ void enable_usb_clocks(int index)
setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
 OPTFCLKEN_REFCLK960M);
 
-   /* Enable 32 KHz clock for dwc3 */
+   /* Enable 32 KHz clock for USB_PHY1 */
setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+   /* Enable 32 KHz clock for USB_PHY3 */
+   if (is_dra7xx())
+   setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
+USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
} else if (index == 1) {
cm_l3init_usb_otg_ss_clkctrl =
(*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
@@ -664,9 +669,14 @@ void disable_usb_clocks(int index)
clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
 OPTFCLKEN_REFCLK960M);
 
-   /* Disable 32 KHz clock for dwc3 */
+   /* Disable 32 KHz clock for USB_PHY1 */
clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+   /* Disable 32 KHz clock for USB_PHY3 */
+   if (is_dra7xx())
+   clrbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
+USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
} else if (index == 1) {
cm_l3init_usb_otg_ss_clkctrl =
(*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c 
b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 655e92b..b5f1d70 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -820,6 +820,7 @@ struct prcm_regs const dra7xx_prcm = {
.cm_clkmode_dpll_gmac   = 0x4a0052a8,
.cm_coreaon_usb_phy1_core_clkctrl   = 0x4a008640,
.cm_coreaon_usb_phy2_core_clkctrl   = 0x4a008688,
+   .cm_coreaon_usb_phy3_core_clkctrl   = 0x4a008698,
.cm_coreaon_l3init_60m_gfclk_clkctrl= 0x4a0086c0,
 
/* cm1.mpu */
diff --git a/arch/arm/include/asm/omap_common.h 
b/arch/arm/include/asm/omap_common.h
index 8fb05e1..7871adf 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -145,6 +145,7 @@ struct prcm_regs {
u32 cm_ssc_modfreqdiv_dpll_unipro;
u32 cm_coreaon_usb_phy1_core_clkctrl;
u32 cm_coreaon_usb_phy2_core_clkctrl;
+   u32 cm_coreaon_usb_phy3_core_clkctrl;
u32 cm_coreaon_l3init_60m_gfclk_clkctrl;
 
/* cm2.core */
-- 
2.7.4

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Re: [U-Boot] can the last traces of "bcopy" be removed?

[Michal Simek]

Hi,

2016-05-22 20:54 GMT+02:00 Robert P. J. Day :

>
>   just noticed that this is all that's left of "bcopy":
>
> $ grep -rw bcopy *
> arch/powerpc/lib/ppcstring.S:   .globl  bcopy
> arch/powerpc/lib/ppcstring.S:bcopy:
> arch/microblaze/include/asm/string.h:extern void bcopy (const char *, char
> *, int);
> include/linux/string.h:char *bcopy(const char *src, char *dest, int count);
> lib/string.c: * bcopy - Copy one area of memory to another
> lib/string.c: * memcpy() is the standard, bcopy() is a legacy BSD function.
> lib/string.c:char * bcopy(const char * src, char * dest, int count)
> $
>
> so, really, no actual usage, and even the microblaze string.h file
> contains:
>
> #if 0
> #define __HAVE_ARCH_BCOPY
> #define __HAVE_ARCH_MEMCPY
> #define __HAVE_ARCH_MEMSET
> #define __HAVE_ARCH_MEMMOVE
>
> extern void *memcpy (void *, const void *, __kernel_size_t);
> extern void bcopy (const char *, char *, int);
> extern void *memset (void *, int, __kernel_size_t);
> extern void *memmove (void *, const void *, __kernel_size_t);
> #endif
>
> so unless i'm misreading, can't bcopy() be tossed entirely while no
> one's using it and before anyone gets a chance to resurrect it? :-)



No problem to remove it. Please send the patch.

Thanks,
Michal
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Re: [U-Boot] [PATCH v1 12/12] am335x, shc: add support for the am335x based bosch shc board

[Heiko Schocher]

Hello Tom,

Am 20.05.2016 um 21:49 schrieb Tom Rini:

On Wed, May 18, 2016 at 04:18:38PM +0200, Heiko Schocher wrote:


U-Boot SPL 2016.03-rc3-00019-g6dfb4c2-dirty (Mar 09 2016 - 07:40:06)
SHC C3-Sample
MPU reference clock runs at 6 MHz
Setting MPU clock to 594 MHz
Enabling Spread Spectrum of 18 permille for MPU
Trying to boot from MMC
reading u-boot.img
reading u-boot.img

U-Boot 2016.03-rc3-00019-g6dfb4c2-dirty (Mar 09 2016 - 07:05:35 +0100)

Watchdog enabled
I2C:   ready
DRAM:  512 MiB
reloc off 1f783000
MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
Net:   cpsw
U-Boot#

Signed-off-by: Heiko Schocher 

---
This patch drops the following checkpatch warnings:

warning: please write a paragraph that describes the config symbol fully
   I wrote a help ... I do not understand, whats missing here...

warning: line over 80 characters
   On places where I think this does not disturb...

   Patch:
   http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/259522
   is needed for clean compiling.


We need to find some other way to solve this or move all of the
partition stuff to Kconfig as well so we can default some stuff on and
then turn it off in cases.


Ok ... hmm... moving to Kconfig seems the best option to me ...
tools/moveconfig is running ... moved
CONFIG_PARTITIONS
CONFIG_DOS_PARTITION
CONFIG_ISO_PARTITION
CONFIG_MAC_PARTITION
CONFIG_EFI_PARTITION

to Kconfig ... I add this patch to v2 ...

Hmm... rebased this patchset to current mainline and it fails working :-(

one error is fixed with patch:
http://patchwork.ozlabs.org/patch/624267/

but there is another mmc based error, as the board prints:

U-Boot SPL 2016.05-00135-g6202e44 (May 23 2016 - 14:54:16)
SHC
MPU reference clock runs at 6 MHz
Setting MPU clock to 594 MHz
Enabling Spread Spectrum of 18 permille for MPU
Trying to boot from MMC2
** Partition 1 not valid on device 1 **
spl_register_fat_device: fat register err - -1
spl_load_image_fat: error reading image u-boot.img, err - -1
spl: no partition table found
SPL: failed to boot from all boot devices

"git bisect" says:
$ git bisect bad
4b6e1fda107e5244e80ebc41865650ac2873dc88 is the first bad commit
$ git show 4b6e1fda107e5244e80ebc41865650ac2873dc88
commit 4b6e1fda107e5244e80ebc41865650ac2873dc88
Merge: 27bec5c 341392d
Author: Tom Rini 
Date:   Tue May 17 13:58:27 2016 -0400

Merge git://git.denx.de/u-boot-dm

Seems in SPL it fails detecting the eMMC ... any hints?


+config 
+   int "UART used for console"
+   range 1 6
+   default 1
+   help
+ The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
+ in documentation, etc) available to it. The SHC board uses UART1
+ for the console.


Can you really have console on the other locations?  On the AM335x EVM,
it was possible, and doubly so with people making RS232 capes for
Beaglebones.  That's why it's exposed there.


You are right, removed.


+int do_panic(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+   hang_bosch("u-boot: uImage not found", 4);
+
+   /*NOTREACHED*/
+   return 0;
+}
+
+U_BOOT_CMD(
+   panic, 1, 0,do_panic,
+   "Hang the CPU - Panic!",
+   ""
+);


No more commands in board directories, and we should be able to do this
generically.  In fact, we should already be able to make fail to boot
Linux fatal which I gather is what this is used for.


Yes, removed.

bye,
Heiko
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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[U-Boot] [PATCH 10/10] sunxi: Add PSCI implementation in C

[Chen-Yu Tsai]

To make the PSCI backend more maintainable and easier to port to newer
SoCs, rewrite the current PSCI implementation in C.

Some inline assembly bits are required to access coprocessor registers.
PSCI stack setup is the only part left completely in assembly. In theory
this part could be split out of psci_arch_init into a separate common
function, and psci_arch_init could be completely in C.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/cpu/armv7/sunxi/Makefile |   7 +-
 arch/arm/cpu/armv7/sunxi/psci.c   | 229 +
 arch/arm/cpu/armv7/sunxi/psci_head.S  |  61 
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 262 --
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 237 --
 5 files changed, 292 insertions(+), 504 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/sunxi/psci.c
 create mode 100644 arch/arm/cpu/armv7/sunxi/psci_head.S
 delete mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun6i.S
 delete mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun7i.S

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile 
b/arch/arm/cpu/armv7/sunxi/Makefile
index 4d2274a38ed1..c2085101685b 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -13,11 +13,8 @@ obj-$(CONFIG_MACH_SUN6I) += tzpc.o
 obj-$(CONFIG_MACH_SUN8I_H3)+= tzpc.o
 
 ifndef CONFIG_SPL_BUILD
-ifdef CONFIG_ARMV7_PSCI
-obj-$(CONFIG_MACH_SUN6I)   += psci_sun6i.o
-obj-$(CONFIG_MACH_SUN7I)   += psci_sun7i.o
-obj-$(CONFIG_MACH_SUN8I)   += psci_sun6i.o
-endif
+obj-$(CONFIG_ARMV7_PSCI)   += psci.o
+obj-$(CONFIG_ARMV7_PSCI)   += psci_head.o
 endif
 
 ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
new file mode 100644
index ..943061937f7c
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/psci.c
@@ -0,0 +1,229 @@
+/*
+ * Copyright (C) 2016
+ * Author: Chen-Yu Tsai 
+ *
+ * Based on assembly code by Marc Zyngier ,
+ * which was based on code by Carl van Schaik .
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define __secure   __attribute__ ((section ("._secure.text")))
+#define __irq  __attribute__ ((interrupt ("IRQ")))
+
+#defineGICD_BASE   (SUNXI_GIC400_BASE + GIC_DIST_OFFSET)
+#defineGICC_BASE   (SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15)
+
+static void __secure __mdelay(u32 ms)
+{
+   u32 reg = DIV_ROUND_UP(CONFIG_TIMER_CLK_FREQ, ms);
+
+   /* CNTP_TVAL */
+   asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (reg));
+   ISB;
+   /* CNTP_CTL */
+   asm volatile ("mcr p15, 0, %0, c14, c2, 1" : : "r" (3));
+
+   do {
+   ISB;
+   /* CNTP_CTL */
+   asm volatile ("mrc p15, 0, %0, c14, c2, 1" : "=r" (reg) : :
+"cc" );
+   } while (!(reg & BIT(2)));
+
+   /* CNTP_CTL */
+   asm volatile ("mcr p15, 0, %0, c14, c2, 1" : : "r" (0));
+}
+
+void __secure sunxi_cpu_power_off(u32 cpuid)
+{
+#ifdef CONFIG_SUNXI_GEN_SUN6I
+   struct sunxi_prcm_reg *prcm =
+   (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+#endif
+   struct sunxi_cpucfg_reg *cpucfg =
+   (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
+   u32 cpu = cpuid & 0x3;
+   u32 tmp __maybe_unused;
+
+   /* Wait for the core to enter WFI */
+   while (1) {
+   if (readl(>cpu[cpu].status) & BIT(2))
+   break;
+   __mdelay(1);
+   }
+
+   /* Assert reset on target CPU */
+   writel(0, >cpu[cpu].rst);
+
+   /* Lock CPU (Disable external debug access) */
+   clrbits_le32(>dbg_ctrl1, BIT(cpu));
+
+#ifdef CONFIG_MACH_SUN7I
+   /* Set power gating */
+   setbits_le32(>cpu1_pwroff, BIT(0));
+#else
+   /* Set power gating */
+   setbits_le32(>cpu_pwroff, BIT(cpu));
+#endif
+
+#ifdef CONFIG_MACH_SUN7I
+   /* Activate power clamp */
+   writel(0xff, >cpu1_pwr_clamp);
+#elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
+   /* Activate power clamp */
+   writel(0xff, >cpu_pwr_clamp[cpu]);
+#endif
+
+   /* Unlock CPU (Disable external debug access) */
+   setbits_le32(>dbg_ctrl1, BIT(cpu));
+}
+
+/*
+ * Although this is an FIQ handler, the FIQ is processed in monitor mode,
+ * which means there's no FIQ banked registers. This is the same as IRQ
+ * mode, so use the IRQ attribute to ask the compiler to handler entry
+ * and return.
+ */
+void __secure __irq psci_fiq_enter(void)
+{
+   u32 scr, reg, cpu;
+
+   /* Switch to secure mode */
+   asm volatile ("mrc p15, 0, %0, c1, c1, 0" : "=r" (scr) : : "cc");
+   reg = scr & ~(1 << 0);
+   asm volatile ("mcr p15, 0, %0, c1, c1, 0" : : "r" (reg) : "cc");
+  

[U-Boot] [PATCH 06/10] sunxi: Group cpu core related controls together

[Chen-Yu Tsai]

Instead of listing individual registers for controls to each processor
core, list them as an array of registers. This makes accessing controls
by core index easier.

Also rename "cpucfg_sun6i.h" (which was unused anyway) to the more generic
"cpucfg.h".

Signed-off-by: Chen-Yu Tsai 
---
 .../asm/arch-sunxi/{cpucfg_sun6i.h => cpucfg.h}| 31 +-
 arch/arm/include/asm/arch-sunxi/prcm.h |  6 ++---
 2 files changed, 14 insertions(+), 23 deletions(-)
 rename arch/arm/include/asm/arch-sunxi/{cpucfg_sun6i.h => cpucfg.h} (69%)

diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h 
b/arch/arm/include/asm/arch-sunxi/cpucfg.h
similarity index 69%
rename from arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h
rename to arch/arm/include/asm/arch-sunxi/cpucfg.h
index e2a29cb1818e..b9084b3968cd 100644
--- a/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpucfg.h
@@ -11,33 +11,26 @@
 
 #ifndef __ASSEMBLY__
 
+struct sunxi_cpucfg_cpu {
+   u32 rst;/* base + 0x0 */
+   u32 ctrl;   /* base + 0x4 */
+   u32 status; /* base + 0x8 */
+   u8 res[0x34];   /* base + 0xc */
+};
+
 struct sunxi_cpucfg_reg {
u8 res0[0x40];  /* 0x000 */
-   u32 cpu0_rst;   /* 0x040 */
-   u32 cpu0_ctrl;  /* 0x044 */
-   u32 cpu0_status;/* 0x048 */
-   u8 res1[0x34];  /* 0x04c */
-   u32 cpu1_rst;   /* 0x080 */
-   u32 cpu1_ctrl;  /* 0x084 */
-   u32 cpu1_status;/* 0x088 */
-   u8 res2[0x34];  /* 0x08c */
-   u32 cpu2_rst;   /* 0x0c0 */
-   u32 cpu2_ctrl;  /* 0x0c4 */
-   u32 cpu2_status;/* 0x0c8 */
-   u8 res3[0x34];  /* 0x0cc */
-   u32 cpu3_rst;   /* 0x100 */
-   u32 cpu3_ctrl;  /* 0x104 */
-   u32 cpu3_status;/* 0x108 */
-   u8 res4[0x78];  /* 0x10c */
+   struct sunxi_cpucfg_cpu cpu[4]; /* 0x040 */
+   u8 res1[0x44];  /* 0x140 */
u32 gen_ctrl;   /* 0x184 */
u32 l2_status;  /* 0x188 */
-   u8 res5[0x4];   /* 0x18c */
+   u8 res2[0x4];   /* 0x18c */
u32 event_in;   /* 0x190 */
-   u8 res6[0xc];   /* 0x194 */
+   u8 res3[0xc];   /* 0x194 */
u32 super_standy_flag;  /* 0x1a0 */
u32 priv0;  /* 0x1a4 */
u32 priv1;  /* 0x1a8 */
-   u8 res7[0x54];  /* 0x1ac */
+   u8 res4[0x54];  /* 0x1ac */
u32 idle_cnt0_low;  /* 0x200 */
u32 idle_cnt0_high; /* 0x204 */
u32 idle_cnt0_ctrl; /* 0x208 */
diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h 
b/arch/arm/include/asm/arch-sunxi/prcm.h
index 556c1af60058..2d69feb33c65 100644
--- a/arch/arm/include/asm/arch-sunxi/prcm.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -225,10 +225,8 @@ struct sunxi_prcm_reg {
u32 gpu_pwroff; /* 0x118 */
u8 res9[0x4];   /* 0x11c */
u32 vdd_pwr_reset;  /* 0x120 */
-   u8 res10[0x20]; /* 0x124 */
-   u32 cpu1_pwr_clamp; /* 0x144 */
-   u32 cpu2_pwr_clamp; /* 0x148 */
-   u32 cpu3_pwr_clamp; /* 0x14c */
+   u8 res10[0x1c]; /* 0x124 */
+   u32 cpu_pwr_clamp[4];   /* 0x140 but first one is actually unused */
u8 res11[0x30]; /* 0x150 */
u32 dram_pwr;   /* 0x180 */
u8 res12[0xc];  /* 0x184 */
-- 
2.8.1

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[U-Boot] [PATCH 07/10] sunxi: Add missing linux/types.h header for cpucfg.h

[Chen-Yu Tsai]

cpucfg.h includes a register definition for the CPUCFG register block.
The types used are u32 and u8, which are defined in linux/types.h.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/include/asm/arch-sunxi/cpucfg.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg.h 
b/arch/arm/include/asm/arch-sunxi/cpucfg.h
index b9084b3968cd..fc42035d70be 100644
--- a/arch/arm/include/asm/arch-sunxi/cpucfg.h
+++ b/arch/arm/include/asm/arch-sunxi/cpucfg.h
@@ -9,6 +9,8 @@
 #ifndef _SUNXI_CPUCFG_H
 #define _SUNXI_CPUCFG_H
 
+#include 
+
 #ifndef __ASSEMBLY__
 
 struct sunxi_cpucfg_cpu {
-- 
2.8.1

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[U-Boot] [PATCH 09/10] sunxi: Add base address for GIC

[Chen-Yu Tsai]

Instead of hardcoding the GIC addresses in the PSCI implementation,
provide a base address in the cpu header.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S   | 4 ++--
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S   | 4 ++--
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 2 ++
 3 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index 9752550dea35..95fdb0e58874 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -42,8 +42,8 @@
 
 #defineONE_MS  (CONFIG_TIMER_CLK_FREQ / 1000)
 #defineTEN_MS  (10 * ONE_MS)
-#defineGICD_BASE   0x1c81000
-#defineGICC_BASE   0x1c82000
+#defineGICD_BASE   (SUNXI_GIC400_BASE +  0x1000)
+#defineGICC_BASE   (SUNXI_GIC400_BASE +  0x2000)
 
 .globl psci_fiq_enter
 psci_fiq_enter:
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
index ac8ebf888a4a..87bbd725f0b3 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
@@ -42,8 +42,8 @@
 
 #defineONE_MS  (CONFIG_TIMER_CLK_FREQ / 1000)
 #defineTEN_MS  (10 * ONE_MS)
-#defineGICD_BASE   0x1c81000
-#defineGICC_BASE   0x1c82000
+#defineGICD_BASE   (SUNXI_GIC400_BASE +  0x1000)
+#defineGICC_BASE   (SUNXI_GIC400_BASE +  0x2000)
 
 .globl psci_fiq_enter
 psci_fiq_enter:
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h 
b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index 47e327e71f84..c5e9d88bab5c 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -143,6 +143,8 @@
 #define SUNXI_DRAM_PHY0_BASE   0x01c65000
 #define SUNXI_DRAM_PHY1_BASE   0x01c66000
 
+#define SUNXI_GIC400_BASE  0x01c8
+
 /* module sram */
 #define SUNXI_SRAM_C_BASE  0x01d0
 
-- 
2.8.1

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[U-Boot] [PATCH 00/10] sunxi: PSCI implementation rewrite in C

[Chen-Yu Tsai]

Hi everyone,

This series rewrites the Allwinner/sunxi PSCI implementation in C, to make
it easier to maintain and extend for the currently unsupported multi-cluster
SoCs. The SMP code in the BSP kernels are in C. Having the PSCI code in C
as well will make it easier to work on.

To be able to convert the platform bits to C, some common PSCI functions
have to be fixed up according to the ARM calling conventions. Function
declarations are also needed.

This series is based on sunxi/next. Parts of it will likely conflict with
the effort to support PSCI 1.0 on the Freescale LS102xA.

Patch 1 fixes up psci_get_cpu_stack_top.

Patch 2 fixes up the PSCI version of v7_flush_dcache_all.

Patch 3 adds function declarations for some of the common PSCI functions.

Patch 4 fixes issues with reserving memory for the secure section.

Patch 5 unifies the CPUCFG_BASE macro names for various sunxi platforms.

Patch 6 groups cpu core related controls together into one struct per core.
This makes it straightforward to access the controls by the cpu index.

Patch 7 adds a missing header to cpucfg.h

Patch 8 adds some missing fields to cpucfg, which were used in the assembly
code.

Patch 9 adds the base address for the GIC.

Patch 10 is the new PSCI implementation in C. Almost all of the code is
converted, with the exception of initial setup of the stack.


Regards
ChenYu


Chen-Yu Tsai (10):
  ARM: PSCI: use only r0 and r3 in psci_get_cpu_stack_top()
  ARM: PSCI: save and restore clobbered registers in v7_flush_dcache_all
  ARM: PSCI: export common PSCI function declarations for C code
  ARM: allocate extra space for PSCI stack in secure section during link
phase
  sunxi: Make CPUCFG_BASE macro names the same across families
  sunxi: Group cpu core related controls together
  sunxi: Add missing linux/types.h header for cpucfg.h
  sunxi: Add CPUCFG debug lock and sun7i cpu power controls
  sunxi: Add base address for GIC
  sunxi: Add PSCI implementation in C

 arch/arm/cpu/armv7/psci.S  |  20 +-
 arch/arm/cpu/armv7/sunxi/Makefile  |   7 +-
 arch/arm/cpu/armv7/sunxi/psci.c| 229 ++
 arch/arm/cpu/armv7/sunxi/psci_head.S   |  61 +
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S  | 262 -
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S  | 237 ---
 arch/arm/cpu/u-boot.lds|   3 +
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h|  17 +-
 .../asm/arch-sunxi/{cpucfg_sun6i.h => cpucfg.h}|  38 +--
 arch/arm/include/asm/arch-sunxi/prcm.h |   6 +-
 arch/arm/include/asm/psci.h|   8 +
 11 files changed, 350 insertions(+), 538 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/sunxi/psci.c
 create mode 100644 arch/arm/cpu/armv7/sunxi/psci_head.S
 delete mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun6i.S
 delete mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun7i.S
 rename arch/arm/include/asm/arch-sunxi/{cpucfg_sun6i.h => cpucfg.h} (69%)

-- 
2.8.1

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[U-Boot] [PATCH 05/10] sunxi: Make CPUCFG_BASE macro names the same across families

[Chen-Yu Tsai]

Use SUNXI_CPUCFG_BASE across all families. This makes writing common
PSCI code easier.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S   | 16 
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S   |  8 
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 15 +--
 3 files changed, 25 insertions(+), 14 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index 90b5bfd35947..9752550dea35 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -73,8 +73,8 @@ psci_fiq_enter:
lsr r9, r9, #10
and r9, r9, #0xf
 
-   movwr8, #(SUN6I_CPUCFG_BASE & 0x)
-   movtr8, #(SUN6I_CPUCFG_BASE >> 16)
+   movwr8, #(SUNXI_CPUCFG_BASE & 0x)
+   movtr8, #(SUNXI_CPUCFG_BASE >> 16)
 
@ Wait for the core to enter WFI
lsl r11, r9, #6 @ x64
@@ -114,8 +114,8 @@ psci_fiq_enter:
str r10, [r12, #0x140]
 #endif
 
-   movwr8, #(SUN6I_CPUCFG_BASE & 0x)
-   movtr8, #(SUN6I_CPUCFG_BASE >> 16)
+   movwr8, #(SUNXI_CPUCFG_BASE & 0x)
+   movtr8, #(SUNXI_CPUCFG_BASE >> 16)
 
@ Unlock CPU
ldr r10, [r8, #0x1e4]
@@ -139,8 +139,8 @@ psci_cpu_on:
str r2, [r0]@ store target PC at stack top
dsb
 
-   movwr0, #(SUN6I_CPUCFG_BASE & 0x)
-   movtr0, #(SUN6I_CPUCFG_BASE >> 16)
+   movwr0, #(SUNXI_CPUCFG_BASE & 0x)
+   movtr0, #(SUNXI_CPUCFG_BASE >> 16)
 
@ CPU mask
and r1, r1, #3  @ only care about first cluster
@@ -189,8 +189,8 @@ psci_cpu_on:
str r6, [r0, #0x100]
 
@ re-calculate CPU control register address
-   movwr0, #(SUN6I_CPUCFG_BASE & 0x)
-   movtr0, #(SUN6I_CPUCFG_BASE >> 16)
+   movwr0, #(SUNXI_CPUCFG_BASE & 0x)
+   movtr0, #(SUNXI_CPUCFG_BASE >> 16)
 
@ Deassert reset on target CPU
mov r6, #3
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
index e15d587f2901..ac8ebf888a4a 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
@@ -73,8 +73,8 @@ psci_fiq_enter:
lsr r9, r9, #10
and r9, r9, #0xf
 
-   movwr8, #(SUN7I_CPUCFG_BASE & 0x)
-   movtr8, #(SUN7I_CPUCFG_BASE >> 16)
+   movwr8, #(SUNXI_CPUCFG_BASE & 0x)
+   movtr8, #(SUNXI_CPUCFG_BASE >> 16)
 
@ Wait for the core to enter WFI
lsl r11, r9, #6 @ x64
@@ -128,8 +128,8 @@ psci_cpu_on:
str r2, [r0]@ store target PC at stack top
dsb
 
-   movwr0, #(SUN7I_CPUCFG_BASE & 0x)
-   movtr0, #(SUN7I_CPUCFG_BASE >> 16)
+   movwr0, #(SUNXI_CPUCFG_BASE & 0x)
+   movtr0, #(SUNXI_CPUCFG_BASE >> 16)
 
@ CPU mask
and r1, r1, #3  @ only care about first cluster
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h 
b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index 65c0441fe8a2..47e327e71f84 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -18,6 +18,10 @@
 #define SUNXI_SRAM_D_BASE  0x0001  /* 4 kiB */
 #define SUNXI_SRAM_B_BASE  0x0002  /* 64 kiB (secure) */
 
+#ifdef CONFIG_MACH_SUN8I_A83T
+#define SUNXI_CPUCFG_BASE  0x0170
+#endif
+
 #define SUNXI_SRAMC_BASE   0x01c0
 #define SUNXI_DRAMC_BASE   0x01c01000
 #define SUNXI_DMA_BASE 0x01c02000
@@ -94,7 +98,10 @@
 
 #define SUNXI_TP_BASE  0x01c25000
 #define SUNXI_PMU_BASE 0x01c25400
-#define SUN7I_CPUCFG_BASE  0x01c25c00
+
+#ifdef CONFIG_MACH_SUN7I
+#define SUNXI_CPUCFG_BASE  0x01c25c00
+#endif
 
 #define SUNXI_UART0_BASE   0x01c28000
 #define SUNXI_UART1_BASE   0x01c28400
@@ -148,7 +155,11 @@
 
 #define SUNXI_RTC_BASE 0x01f0
 #define SUNXI_PRCM_BASE0x01f01400
-#define SUN6I_CPUCFG_BASE  0x01f01c00
+
+#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN8I_A83T
+#define SUNXI_CPUCFG_BASE  0x01f01c00
+#endif
+
 #define SUNXI_R_TWI_BASE   0x01f02400
 #define SUNXI_R_UART_BASE  0x01f02800
 #define SUNXI_R_PIO_BASE   0x01f02c00
-- 
2.8.1

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[U-Boot] [PATCH 04/10] ARM: allocate extra space for PSCI stack in secure section during link phase

[Chen-Yu Tsai]

The PSCI implementation expects at most 2 pages worth of space reserved
at the end of the secure section for its stacks. This was not properly
marked and taken into consideration when reserving memory from the
kernel.

If one accesses PSCI after Linux has fully booted, the memory that should
have been reserved for the PSCI stacks may have been used by the kernel
or userspace, and would be corrupted. Observed after effects include the
system hanging or telinit core dumping when trying to reboot. It seems
the init process gets hit the most on my test bed.

This fix is only a stop gap. It would be better to rework the stack
allocation mechanism, maybe with proper usage of CONFIG_ macros and an
explicit symbol.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/cpu/u-boot.lds | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index cfab8b041234..c7f37b606ad5 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -67,6 +67,9 @@ SECTIONS
SIZEOF(.__secure_start) +
SIZEOF(.secure_text);
 
+   /* Align to page boundary and skip 2 pages */
+   . = (. & ~ 0xfff) + 0x2000;
+
__secure_end_lma = .;
.__secure_end : AT(__secure_end_lma) {
*(.__secure_end)
-- 
2.8.1

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[U-Boot] [PATCH 08/10] sunxi: Add CPUCFG debug lock and sun7i cpu power controls

[Chen-Yu Tsai]

CPUCFG has an unlisted debug control register, which is used to disable
external debug access.

Also, sun7i secondary core power controls are in CPUCFG, as there's no
separate PRCM block.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/include/asm/arch-sunxi/cpucfg.h | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg.h 
b/arch/arm/include/asm/arch-sunxi/cpucfg.h
index fc42035d70be..02afd8b4a09a 100644
--- a/arch/arm/include/asm/arch-sunxi/cpucfg.h
+++ b/arch/arm/include/asm/arch-sunxi/cpucfg.h
@@ -32,7 +32,12 @@ struct sunxi_cpucfg_reg {
u32 super_standy_flag;  /* 0x1a0 */
u32 priv0;  /* 0x1a4 */
u32 priv1;  /* 0x1a8 */
-   u8 res4[0x54];  /* 0x1ac */
+   u8 res4[0x4];   /* 0x1ac */
+   u32 cpu1_pwr_clamp; /* 0x1b0 sun7i only */
+   u32 cpu1_pwroff;/* 0x1b4 sun7i only */
+   u8 res5[0x2c];  /* 0x1b8 */
+   u32 dbg_ctrl1;  /* 0x1e4 */
+   u8 res6[0x18];  /* 0x1e8 */
u32 idle_cnt0_low;  /* 0x200 */
u32 idle_cnt0_high; /* 0x204 */
u32 idle_cnt0_ctrl; /* 0x208 */
-- 
2.8.1

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[U-Boot] [PATCH 02/10] ARM: PSCI: save and restore clobbered registers in v7_flush_dcache_all

[Chen-Yu Tsai]

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/cpu/armv7/psci.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index cdd001fe3fb0..ab408378fcae 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -110,6 +110,7 @@ ENDPROC(psci_get_cpu_id)
 
 /* Imported from Linux kernel */
 LENTRY(v7_flush_dcache_all)
+   stmfd   sp!, {r4-r5, r7, r9-r11, lr}
dmb @ ensure ordering with previous 
memory accesses
mrc p15, 1, r0, c0, c0, 1   @ read clidr
andsr3, r0, #0x700  @ extract loc from clidr
@@ -153,6 +154,7 @@ finished:
mcr p15, 2, r10, c0, c0, 0  @ select current cache level in 
cssr
dsb st
isb
+   ldmfd   sp!, {r4-r5, r7, r9-r11, lr}
bx  lr
 ENDPROC(v7_flush_dcache_all)
 
-- 
2.8.1

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[U-Boot] [PATCH 03/10] ARM: PSCI: export common PSCI function declarations for C code

[Chen-Yu Tsai]

Some common PSCI functions are written in assembly, but it should be
possible to use them from C code.

Add function declarations for C code to consume.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/include/asm/psci.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 128a606444fe..5db33562a299 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -33,6 +33,14 @@
 #define ARM_PSCI_RET_DENIED(-3)
 
 #ifndef __ASSEMBLY__
+#include 
+#include 
+
+void __section("._secure.text") psci_cpu_entry(void);
+u32 __section("._secure.text") psci_get_cpu_id(void);
+u32 __section("._secure.text") psci_get_cpu_stack_top(int cpu);
+void __section("._secure.text") psci_cpu_off_common(void);
+
 int psci_update_dt(void *fdt);
 void psci_board_init(void);
 #endif /* ! __ASSEMBLY__ */
-- 
2.8.1

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[U-Boot] [PATCH 01/10] ARM: PSCI: use only r0 and r3 in psci_get_cpu_stack_top()

[Chen-Yu Tsai]

For psci_get_cpu_stack_top() to be usable in C code, it must adhere to
the ARM calling conventions. Since it could be called when the stack
is still unavailable, and the entry code to linux also expects r1 and
r2 to remain unchanged, stick to r0 and r3.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/cpu/armv7/psci.S | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 87c0c0b6f5eb..cdd001fe3fb0 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -196,15 +196,15 @@ ENDPROC(psci_cpu_off_common)
 
 @ expects CPU ID in r0 and returns stack top in r0
 ENTRY(psci_get_cpu_stack_top)
-   mov r5, #0x400  @ 1kB of stack per CPU
-   mul r0, r0, r5
-
-   ldr r5, =psci_text_end  @ end of monitor text
-   add r5, r5, #0x2000 @ Skip two pages
-   lsr r5, r5, #12 @ Align to start of page
-   lsl r5, r5, #12
-   sub r5, r5, #4  @ reserve 1 word for target PC
-   sub r0, r5, r0  @ here's our stack!
+   mov r3, #0x400  @ 1kB of stack per CPU
+   mul r0, r0, r3
+
+   ldr r3, =psci_text_end  @ end of monitor text
+   add r3, r3, #0x2000 @ Skip two pages
+   lsr r3, r3, #12 @ Align to start of page
+   lsl r3, r3, #12
+   sub r3, r3, #4  @ reserve 1 word for target PC
+   sub r0, r3, r0  @ here's our stack!
 
bx  lr
 ENDPROC(psci_get_cpu_stack_top)
-- 
2.8.1

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[U-Boot] [PATCH 1/2] spi: zynqmp_qspi: Add QSPI driver support for ZynqMP

[Siva Durga Prasad Paladugu]

This adds QSPI driver support for ZynqMP platform
This driver supports all spi flash commands in
qspi single mode.

Signed-off-by: Siva Durga Prasad Paladugu 
---
 drivers/spi/Kconfig   |9 +
 drivers/spi/Makefile  |1 +
 drivers/spi/zynqmp_qspi.c |  704 +
 3 files changed, 714 insertions(+), 0 deletions(-)
 create mode 100644 drivers/spi/zynqmp_qspi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index f0258f8..25a98a6 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -155,6 +155,15 @@ config ZYNQ_QSPI
  Zynq QSPI IP core. This IP is used to connect the flash in
  4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel.
 
+config ZYNQMP_QSPI
+   bool "ZynqMP QSPI driver"
+   depends on ARCH_ZYNQMP
+   help
+ Enable the ZynqMP Quad-SPI (QSPI) driver. This driver can be
+ used to access the SPI NOR flash on platforms embedding this
+ ZynqMP QSPI IP core. This IP is used to connect the flash in
+ 4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel.
+
 config OMAP3_SPI
bool "McSPI driver for OMAP"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 3eca745..b47103f 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -51,3 +51,4 @@ obj-$(CONFIG_TI_QSPI) += ti_qspi.o
 obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
 obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
 obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o
+obj-$(CONFIG_ZYNQMP_QSPI) += zynqmp_qspi.o
diff --git a/drivers/spi/zynqmp_qspi.c b/drivers/spi/zynqmp_qspi.c
new file mode 100644
index 000..97ac7a0
--- /dev/null
+++ b/drivers/spi/zynqmp_qspi.c
@@ -0,0 +1,704 @@
+/*
+ * Xilinx ZynqMP Quad-SPI(QSPI) Controller Driver
+ *
+ * (C) Copyright 2016 Xilinx, Inc
+ * Siva Durga Prasad 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "../mtd/spi/sf_internal.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * QSPI Config Register bit Masks
+ */
+#define ZYNQMP_QSPI_CONFIG_STRT_MODE_MASK  BIT(29)
+#define ZYNQMP_QSPI_CONFIG_MODE_EN_MASKGENMASK(31, 30)
+#define ZYNQMP_QSPI_CONFIG_DMA_MODEBIT(31)
+#define ZYNQMP_QSPI_CONFIG_CPHA_MASK   BIT(2)
+#define ZYNQMP_QSPI_CONFIG_CPOL_MASK   BIT(1)
+#define ZYNQMP_QSPI_CONFIG_GFIFO_WP_HOLD   BIT(19)
+#define ZYNQMP_QSPI_CONFIG_BAUD_DIV_MASK   GENMASK(5, 3)
+#define ZYNQMP_QSPI_CONFIG_DFLT_BAUD_RATE_DIV  BIT(3)
+
+/*
+ * QSPI Interrupt Registers bit Masks
+ */
+#define ZYNQMP_QSPI_IXR_TXNFULL_MASK   BIT(2)
+#define ZYNQMP_QSPI_IXR_TXFULL_MASKBIT(3)
+#define ZYNQMP_QSPI_IXR_RXNEMTY_MASK   BIT(4)
+#define ZYNQMP_QSPI_IXR_GFEMTY_MASKBIT(7)
+#define ZYNQMP_QSPI_IXR_ALL_MASK   (ZYNQMP_QSPI_IXR_TXNFULL_MASK | \
+ZYNQMP_QSPI_IXR_RXNEMTY_MASK)
+#define ZYNQMP_QSPI_GFIFO_ALL_INT_MASK 0xFBE
+
+/*
+ * QSPI Enable Register bit Masks
+ */
+#define ZYNQMP_QSPI_ENABLE_ENABLE_MASK BIT(0)
+
+/*
+ * QSPI Generic FIFO register bit masks
+ */
+#define ZYNQMP_QSPI_GFIFO_LOW_BUS  BIT(14)
+#define ZYNQMP_QSPI_GFIFO_CS_LOWER BIT(12)
+#define ZYNQMP_QSPI_GFIFO_UP_BUS   BIT(15)
+#define ZYNQMP_QSPI_GFIFO_CS_UPPER BIT(13)
+#define ZYNQMP_QSPI_GFIFO_SPI_MODE_QSPIGENMASK(11, 10)
+#define ZYNQMP_QSPI_GFIFO_SPI_MODE_SPI BIT(10)
+#define ZYNQMP_QSPI_GFIFO_TX   BIT(16)
+#define ZYNQMP_QSPI_GFIFO_RX   BIT(17)
+#define ZYNQMP_QSPI_GFIFO_STRIPE_MASK  BIT(18)
+#define ZYNQMP_QSPI_GFIFO_IMD_MASK GENMASK(7, 0)
+#define ZYNQMP_QSPI_GFIFO_EXP_MASK BIT(9)
+#define ZYNQMP_QSPI_GFIFO_DATA_XFR_MASKBIT(8)
+
+#define ZYNQMP_QSPI_GFIFO_IMD_DATA_CS_ASSERT   5
+#define ZYNQMP_QSPI_GFIFO_IMD_DATA_CS_DEASSERT 5
+#define ZYNQMP_QSPI_GFIFO_EXP_INIT_VAL 8
+#define ZYNQMP_QSPI_GFIFO_IMD_MAX_DATA_LEN 255
+/*
+ * QSPI DMA Destination status register bit masks
+ */
+#define ZYNQMP_QSPI_DMA_DST_I_STS_DONE BIT(1)
+#define ZYNQMP_QSPI_DMA_DST_I_STS_MASK GENMASK(7, 1)
+
+/*
+ * QSPI Generic QSPI selection register bit mask
+ */
+#define ZYNQMP_QSPI_GQSPI_SELECT   BIT(0)
+
+#define ZYNQMP_QSPI_FIFO_THRESHOLD 1
+
+#define SPI_XFER_ON_BOTH   0
+#define SPI_XFER_ON_LOWER  1
+#define SPI_XFER_ON_UPPER  2
+
+#define ZYNQMP_QSPI_DMA_ALIGN  0x4
+#define ZYNQMP_QSPI_DMA_POLL_TIMEOUT   1000
+
+#define ZYNQMP_QSPI_GENERIC_BASEADDR_OFFSET0x100
+#define ZYNQMP_QSPI_GENERIC_DMABASE_OFFSET 0x800
+
+/* QSPI register offsets */
+struct zynqmp_qspi_regs {
+   u32 confr;  /* 0x00 */
+   u32 isr;/* 0x04 */
+   u32 ier;/* 0x08 */
+   u32 idisr;  /* 0x0C */
+   u32 imaskr; /* 0x10 */
+   u32 enbr;   /* 0x14 */
+   u32 dr;   

[U-Boot] [PATCH 2/2] spi: zynqmp_qspi: Add qspi driver support for ZynqMP boards

[Siva Durga Prasad Paladugu]

Added the qspi driver support for respective ZynqMP boards
ZCU102, ZCU102 RevB and DC1 boards.

Signed-off-by: Siva Durga Prasad Paladugu 
---
 configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig |4 
 configs/xilinx_zynqmp_zcu102_defconfig   |4 
 configs/xilinx_zynqmp_zcu102_revB_defconfig  |4 
 3 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig 
b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index cc08b03..164b156 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -3,6 +3,9 @@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm015_dc1"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_DM_I2C=y
 CONFIG_DM_GPIO=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_ZYNQMP_QSPI=y
 CONFIG_ZYNQMP_USB=y
 CONFIG_SYS_TEXT_BASE=0x800
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
@@ -28,6 +31,7 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_SF=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_I2C_CADENCE=y
diff --git a/configs/xilinx_zynqmp_zcu102_defconfig 
b/configs/xilinx_zynqmp_zcu102_defconfig
index 6f1cff8..64c032d 100644
--- a/configs/xilinx_zynqmp_zcu102_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_defconfig
@@ -2,6 +2,9 @@ CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_DM_GPIO=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_ZYNQMP_QSPI=y
 CONFIG_ZYNQMP_USB=y
 CONFIG_SYS_TEXT_BASE=0x800
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102"
@@ -27,6 +30,7 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_SF=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM_MMC=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig 
b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index a8982a0..39e341c 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -2,6 +2,9 @@ CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_DM_GPIO=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_ZYNQMP_QSPI=y
 CONFIG_ZYNQMP_USB=y
 CONFIG_SYS_TEXT_BASE=0x800
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB"
@@ -27,6 +30,7 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_SF=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM_MMC=y
-- 
1.7.1

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Re: [U-Boot] SPL: fat: Fix spl_parse_image_header() return value handling

[Heiko Schocher]

Hello Marek,

Am 20.05.2016 um 01:45 schrieb Marek Vasut:

The spl_parse_image_header() can return 0 and it is not an error.
Only treat non-zero return value as an error.

Signed-off-by: Marek Vasut 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Stefano Babic 
Cc: Tom Rini 
Reviewed-by: Fabio Estevam 
Reviewed-by: Peng Fan 
Reviewed-by: Stefano Babic 
Reviewed-by: Tom Rini 
---
  common/spl/spl_fat.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)


Thanks!

So:
Reviewed-by: Heiko Schocher 
Tested-by: Heiko Schocher 

bye,
Heiko
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