[U-Boot] [PATCH v3] sunxi: FEL - Add the ability to recognize and auto-import uEnv-style data

[Bernhard Nortmann]

The patch converts one of the "reserved" fields in the sunxi SPL
header to a fel_uEnv_length entry. When booting over USB ("FEL
mode"), this enables the sunxi-fel utility to pass the string
length of uEnv.txt compatible data; at the same time requesting
that this data be imported into the U-Boot environment.

If parse_spl_header() in the sunxi board.c encounters a non-zero
value in this header field, it will therefore call himport_r() to
merge the string (lines) passed via FEL into the default settings.
Environment vars can be changed this way even before U-Boot will
attempt to autoboot - specifically, this also allows overriding
"bootcmd".

With fel_script_addr set and a zero fel_uEnv_length, U-Boot is
safe to assume that data in .scr format (a mkimage-type script)
was passed at fel_script_addr, and will handle it using the
existing mechanism ("bootcmd_fel").

Signed-off-by: Bernhard Nortmann 
Acked-by: Siarhei Siamashka 

---
A corresponding proof-of-concept version of sunxi-fel is available
from my https://github.com/n1tehawk/sunxi-tools/tree/20160608_uEnv-magic
branch. I've picked up the suggestion to use a "#=uEnv" magic string
to request that a file be treated as uEnv.txt-style data.

For example, use your text editor to save a my.env file with

#=uEnv
myvar=world
bootcmd=echo "Hello $myvar."

and then test it with
./sunxi-fel uboot u-boot-sunxi-with-spl.bin write 0x4310 my.env

You should see U-Boot's autoboot print the corresponding message
and drop you to the prompt, proving that you have successfully
overwritten the "bootcmd".

Changes in v3:
- Dropped a surplus "return;" at the end of parse_spl_header()
- Have "FEL" in the subject line to clarify the scope
- Added "Acked-by" line

Changes in v2:
- Patch renamed to something more suitable (was "sunxi: Add the
  ability to pass (script) filesize in the SPL header")
- The data field is now named fel_uEnv_length, and comes with
  a corresponding description in spl.h
- Instead of simply passing file size, fel_uEnv_length is now
  associated with uEnv.txt format. The patch modifies U-Boot's
  sunxi parse_spl_header() to auto-import such data.

 arch/arm/include/asm/arch-sunxi/spl.h |  9 -
 board/sunxi/board.c   | 29 +
 2 files changed, 29 insertions(+), 9 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/spl.h 
b/arch/arm/include/asm/arch-sunxi/spl.h
index a0f33b0..a966a88 100644
--- a/arch/arm/include/asm/arch-sunxi/spl.h
+++ b/arch/arm/include/asm/arch-sunxi/spl.h
@@ -49,7 +49,14 @@ struct boot_file_head {
uint8_t spl_signature[4];
};
uint32_t fel_script_address;
-   uint32_t reserved1[3];
+   /*
+* If the fel_uEnv_length member below is set to a non-zero value,
+* it specifies the size (byte count) of data at fel_script_address.
+* At the same time this indicates that the data is in uEnv.txt
+* compatible format, ready to be imported via "env import -t".
+*/
+   uint32_t fel_uEnv_length;
+   uint32_t reserved1[2];
uint32_t boot_media;/* written here by the boot ROM */
uint32_t reserved2[5];  /* padding, align to 64 bytes */
 };
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index d09cf6d..b5a50f4 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -573,6 +573,7 @@ void get_board_serial(struct tag_serialnr *serialnr)
 
 #if !defined(CONFIG_SPL_BUILD)
 #include 
+#include 
 
 /*
  * Check the SPL header for the "sunxi" variant. If found: parse values
@@ -582,17 +583,29 @@ void get_board_serial(struct tag_serialnr *serialnr)
 static void parse_spl_header(const uint32_t spl_addr)
 {
struct boot_file_head *spl = (void *)(ulong)spl_addr;
-   if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) == 0) {
-   uint8_t spl_header_version = spl->spl_signature[3];
-   if (spl_header_version == SPL_HEADER_VERSION) {
-   if (spl->fel_script_address)
-   setenv_hex("fel_scriptaddr",
-  spl->fel_script_address);
-   return;
-   }
+   if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
+   return; /* signature mismatch, no usable header */
+
+   uint8_t spl_header_version = spl->spl_signature[3];
+   if (spl_header_version != SPL_HEADER_VERSION) {
printf("sunxi SPL version mismatch: expected %u, got %u\n",
   SPL_HEADER_VERSION, spl_header_version);
+   return;
+   }
+   if (!spl->fel_script_address)
+   return;
+
+   if (spl->fel_uEnv_length != 0) {
+   /*
+* data is expected in uEnv.txt compatible format, so "env
+* import -t" the string(s) at fel_script_address right away.
+*/
+   

Re: [U-Boot] [PATCH 2/8] x86: baytrail: Add 'reg' property in the pinctrl node

[Stefan Roese]

On 08.06.2016 14:07, Bin Meng wrote:

Without a 'reg' property, pinctrl driver probe routine fails in
its pre_probe() with a return value of -EINVAL.

Add 'reg' property for all BayTrail boards. Note for BayleyBay,
the pinctrl node is newly added.

Signed-off-by: Bin Meng 


Reviewed-by: Stefan Roese 

Thanks,
Stefan
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Re: [U-Boot] [PATCH 1/8] x86: ich6_gpio: Output return value of syscon_get_by_driver_data()

[Stefan Roese]

On 08.06.2016 14:07, Bin Meng wrote:

The call to syscon_get_by_driver_data() does not save its return value.
Print it out to aid debugging.

Signed-off-by: Bin Meng 


Reviewed-by: Stefan Roese 

Thanks,
Stefan
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Re: [U-Boot] [PATCH v2] tiny-printf: Correct the snprintf() implementation

[Stefan Roese]

On 09.06.2016 04:55, Simon Glass wrote:

This current code passes the variable arguments list to sprintf(). This is
not correct. Fix it by calling _vprintf() directly.

This makes firefly-rk3288 boot again.

Fixes: abeb272 ("tiny-printf: Support snprintf()")
Signed-off-by: Simon Glass 


Reviewed-by: Stefan Roese 

Thanks,
Stefan
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Re: [U-Boot] Továbbítás: u-boot

[Heiko Schocher]

Hello,

Am 08.06.2016 um 21:50 schrieb kri...@nmdps.net:

Küldve az én HTC-mről

- Továbbított üzenet -
Feladó: kri...@nmdps.net
Címzett: 
Tárgy: u-boot
Dátum: Sze, jún. 8, 2016 19:12

Dear developer,

I own a bananapi m2, on which u-boot does not boot up since commit
90b7fc924adfe7f1745dcf6a1dabb9e77aa762a7.

The console is repeating:

U-Boot 2016.05-00393-g90b7fc9 (Jun 08 2016 - 18:57:34 +0200) Allwinner
Technology

CPU:   Allwinner A31s (SUN6I)
Model: Sinovoip BPI-M2
DRAM:  1 GiB
MMC:   SUNXI SD/MMC: 0
*** Warning - bad CRC, using default environment

In:serial
Out:   serial
Err:   serial
Net:   data abort
pc : [<7ef5f6f4>]  lr : [<7ef80b94>]
reloc pc : [<4a0016f4>]lr : [<4a022b94>]


It seems its in the network init ...

Do you have the System.map file for the image? Then you can
look into it and find out, which function crashes @0x4a0016f4.

bye,
Heiko

sp : 7af36f80  ip :  fp : 0017
r10: 7efab5e8  r9 : 7af3dee8 r8 : 40a0
r7 : 7ef9ee0c  r6 :  r5 : 0001  r4 : 
r3 : 7ef80b70  r2 : 0001 r1 :   r0 : ea0e
Flags: nzCv  IRQs off  FIQs off  Mode SVC_32
Resetting CPU ...

resetting ...

U-Boot SPL 2016.05-00393-g90b7fc9 (Jun 08 2016 - 18:57:34)
DRAM: 1024 MiB
Trying to boot from MMC1


U-Boot 2016.05-00393-g90b7fc9 (Jun 08 2016 - 18:57:34 +0200) Allwinner
Technology

CPU:   Allwinner A31s (SUN6I)
Model: Sinovoip BPI-M2
DRAM:  1 GiB
MMC:   SUNXI SD/MMC: 0
*** Warning - bad CRC, using default environment

In:serial
Out:   serial
Err:   serial
Net:   data abort
pc : [<7ef5f6f4>]  lr : [<7ef80b94>]
reloc pc : [<4a0016f4>]lr : [<4a022b94>]
sp : 7af36f80  ip :  fp : 0017
r10: 7efab5e8  r9 : 7af3dee8 r8 : 40a0
r7 : 7ef9ee0c  r6 :  r5 : 0001  r4 : 
r3 : 7ef80b70  r2 : 0001 r1 :   r0 : ea0e
Flags: nzCv  IRQs off  FIQs off  Mode SVC_32
Resetting CPU ...

resetting ...

U-Boot SPL 2016.05-00393-g90b7fc9 (Jun 08 2016 - 18:57:34)
DRAM: 1024 MiB
Trying to boot from MMC1


U-Boot 2016.05-00393-g90b7fc9 (Jun 08 2016 - 18:57:34 +0200) Allwinner
Technology

CPU:   Allwinner A31s (SUN6I)
Model: Sinovoip BPI-M2
DRAM:  1 GiB
MMC:   SUNXI SD/MMC: 0
*** Warning - bad CRC, using default environment

In:serial
Out:   serial
Err:   serial
Net:   data abort
pc : [<7ef5f6f4>]  lr : [<7ef80b94>]
reloc pc : [<4a0016f4>]lr : [<4a022b94>]
sp : 7af36f80  ip :  fp : 0017
r10: 7efab5e8  r9 : 7af3dee8 r8 : 40a0
r7 : 7ef9ee0c  r6 :  r5 : 0001  r4 : 
r3 : 7ef80b70  r2 : 0001 r1 :   r0 : ea0e
Flags: nzCv  IRQs off  FIQs off  Mode SVC_32

and so on.

How could I help debugging, resolving this issue?

Regards,
Richard Kojedzinszky
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Re: [U-Boot] [PATCH] ti_armv7_common: env: Remove no longer needed mem_reserve

[Lokesh Vutla]

On Wednesday 08 June 2016 08:49 PM, Andrew F. Davis wrote:
> The kernel can now use DT to reserve memory carveouts and
> these areas are now the default for drivers that need reserved
> memory, so reserving more here is unneeded and any memory reserved
> this way will be wasted.
> 
> Signed-off-by: Andrew F. Davis 

Reviewed-by: Lokesh Vutla 

Thanks and regards,
Lokesh

> ---
>  include/configs/ti_armv7_keystone2.h | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/include/configs/ti_armv7_keystone2.h 
> b/include/configs/ti_armv7_keystone2.h
> index 2c9028c..d7baf33 100644
> --- a/include/configs/ti_armv7_keystone2.h
> +++ b/include/configs/ti_armv7_keystone2.h
> @@ -247,7 +247,6 @@
>   "tftp_root=/\0" \
>   "nfs_root=/export\0"\
>   "mem_lpae=1\0"  \
> - "mem_reserve=512M\0"\
>   "addr_ubi=0x8200\0" \
>   "addr_secdb_key=0xc00\0"\
>   "name_kern=zImage\0"\
> 
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Re: [U-Boot] [PATCH 1/3] drivers: usb: fsl: add USB ULPI init code

[Rajesh Bhagat]

> -Original Message-
> From: Marek Vasut [mailto:ma...@denx.de]
> Sent: Wednesday, June 08, 2016 7:29 PM
> To: Rajesh Bhagat ; u-boot@lists.denx.de
> Cc: Sriram Dash ; albert.u.b...@aribaud.net;
> prabha...@freescale.com; york sun ; Rajat Srivastava
> 
> Subject: Re: [PATCH 1/3] drivers: usb: fsl: add USB ULPI init code
> 
> On 06/08/2016 10:22 AM, Rajesh Bhagat wrote:
> > This adds the required code to set up a ULPI USB port, for new NXP USB
> > PHY used in QorIQ platforms.
> >
> > To use this both CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT have to
> > be set in the board configuration file.
> >
> > Signed-off-by: Rajesh Bhagat 
> > ---
> >  drivers/usb/host/ehci-fsl.c |   21 +
> >  1 files changed, 21 insertions(+), 0 deletions(-)
> >
> > diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
> > index a43d37d..897f453 100644
> > --- a/drivers/usb/host/ehci-fsl.c
> > +++ b/drivers/usb/host/ehci-fsl.c
> > @@ -16,6 +16,9 @@
> >  #include 
> >  #include 
> >  #include 
> > +#ifdef CONFIG_USB_ULPI
> > +#include 
> > +#endif
> >
> >  #include "ehci.h"
> >
> > @@ -50,6 +53,10 @@ int ehci_hcd_init(int index, enum usb_init_type init,
> > const char *phy_type = NULL;
> > size_t len;
> > char current_usb_controller[5];
> > +#ifdef CONFIG_USB_ULPI
> > +   int ret;
> > +   struct ulpi_viewport ulpi_vp;
> > +#endif
> >  #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
> > char usb_phy[5];
> >
> > @@ -126,6 +133,20 @@ int ehci_hcd_init(int index, enum usb_init_type init,
> > udelay(1000); /* delay required for PHY Clk to appear */
> > if (!usb_phy_clk_valid(ehci))
> > return -EINVAL;
> > +
> > +#ifdef CONFIG_USB_ULPI
> > +   ulpi_vp.viewport_addr = (u32)>ulpi_viewpoint;
> > +   ulpi_vp.port_num = 0;
> > +
> > +   ret = ulpi_init(_vp);
> > +   if (ret) {
> > +   puts("NXP ULPI viewport init failed\n");
> > +   return -1;

Hello Marek, 

> 
> return ret;
> 

Will take care in v2. 

Best Regards,
Rajesh Bhagat 

> > +   }
> > +
> > +   ulpi_set_vbus(_vp, 1, 1);
> > +   ulpi_set_vbus_indicator(_vp, 1, 1, 1); #endif
> > out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
> > }
> >
> >
> 
> 
> --
> Best regards,
> Marek Vasut
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Re: [U-Boot] [PATCH v3] common: usb_storage : Implement logic to calculate optimal usb maximum trasfer blocks

[Rajesh Bhagat]

> -Original Message-
> From: Marek Vasut [mailto:ma...@denx.de]
> Sent: Wednesday, June 08, 2016 7:25 PM
> To: Rajesh Bhagat ; u-boot@lists.denx.de
> Cc: s...@chromium.org; york sun ; Sriram Dash
> 
> Subject: Re: [PATCH v3] common: usb_storage : Implement logic to calculate 
> optimal
> usb maximum trasfer blocks
> 
> On 06/08/2016 06:09 AM, Rajesh Bhagat wrote:
> >
> >
> >> -Original Message-
> >> From: Marek Vasut [mailto:ma...@denx.de]
> >> Sent: Wednesday, June 08, 2016 8:38 AM
> >> To: Rajesh Bhagat ; u-boot@lists.denx.de
> >> Cc: s...@chromium.org; york sun ; Sriram Dash
> >> 
> >> Subject: Re: [PATCH v3] common: usb_storage : Implement logic to
> >> calculate optimal usb maximum trasfer blocks
> >>
> >> On 06/07/2016 11:29 AM, Rajesh Bhagat wrote:
> >>> Implements the logic to calculate the optimal usb maximum trasfer
> >>> blocks instead of sending USB_MAX_XFER_BLK blocks which is 65535 and
> >>> 20 in case of EHCI and other USB protocols respectively.
> >>>
> >>> It defines USB_MIN_XFER_BLK/USB_MAX_XFER_BLK trasfer blocks that
> >>> should be checked for success starting from minimum to maximum, and
> >>> rest of the read/write are performed with that optimal value. It
> >>> tries to increase/ decrease the blocks in follwing scenarios:
> >>>
> >>> 1.decrease blocks: when read/write for a particular number of blocks
> >>> fails.
> >>> 2. increase blocks: when read/write for a particular number of
> >>> blocks pass and amount left to trasfer is greater than current
> >>> number of blocks.
> >>>
> >>> Currently changes are done for EHCI where min = 4096 and max = 65535
> >>> is taken. And for other cases code is left unchanged by keeping min
> >>> = max = 20.
> >>>
> >>> Signed-off-by: Sriram Dash 
> >>> Signed-off-by: Rajesh Bhagat 
> >>> ---
> >>> Changes in v3:
> >>>  - Adds cur_xfer_blks in struct usb_device to retain values
> >>>  - Adds functions dec/inc_cur_xfer_blks to remove code duplication
> >>>  - Moves check from macro to calling functions
> >>>
> >>> Changes in v2:
> >>>  - Removes table to store blocks and use formula (1 << (12 + n)) - 1
> >>>  - Adds logic to start from minimum, go to maximum in each
> >>> read/write
> >>>
> >>>  common/usb_storage.c | 78
> >> 
> >>>  include/usb.h|  1 +
> >>>  2 files changed, 67 insertions(+), 12 deletions(-)
> >>>
> >>> diff --git a/common/usb_storage.c b/common/usb_storage.c index
> >>> 7e6e52d..e08dcd4 100644
> >>> --- a/common/usb_storage.c
> >>> +++ b/common/usb_storage.c
> >>> @@ -106,11 +106,40 @@ struct us_data {
> >>>   * enough free heap space left, but the SCSI READ(10) and WRITE(10)
> >>> commands
> >> are
> >>>   * limited to 65535 blocks.
> >>>   */
> >>> +#define USB_MIN_XFER_BLK 4095
> >>>  #define USB_MAX_XFER_BLK 65535
> >>>  #else
> >>> +#define USB_MIN_XFER_BLK 20
> >>>  #define USB_MAX_XFER_BLK 20
> >>>  #endif
> >>>
> >>> +#define GET_CUR_XFER_BLKS(blks)  (LOG2(blks / (USB_MIN_XFER_BLK +
> >> 1)))
> >>> +#define CALC_CUR_XFER_BLKS(pos)  ((1 << (12 + pos)) - 1)
> >>> +
> >>> +static int dec_cur_xfer_blks(int *pos, unsigned short *smallblks) {
> >>> + /* decrease the cur_xfer_blks */
> >>> + unsigned short size = (*pos > 0) ? CALC_CUR_XFER_BLKS(*pos - 1) :
> >>> +0;
> >>
> >
> > Hello Marek,
> >
> >> If someone passes null pointer into the function, it will fail.
> >> Also, you can refactor it to make it more readable:
> >>
> >> if (!pos)
> >>  return -EINVAL;
> >> if (size < USB_MIN_XFER_BLK)
> >>  return -EINVAL;
> >> ... do stuff ...
> >>
> >
> > Refactoring the code to return early in case of error conditions is
> > fine. But pos and smallblks can never be passed as NULL in these functions.
> 
Hello Marek,

> ... until an idiot comes around and does it.
> 

Ok, I will add the mentioned sanity checks in v4.

> >> I still don't understand why $pos isn't unsigned int, it should be.
> >>
> >
> > I believe keeping a variable as "int" provides a natural way of
> > checking for overflow conditions. We check can check if number has
> > become negative and take actions, which is not possible when number is 
> > taken as
> "unsigned int".
> 
> But the number here can never be negative, can it ?

Ok, I will change the variable to unsigned int in v4. 

> 
> >>> + if (size >= USB_MIN_XFER_BLK) {
> >>> + *smallblks = size;
> >>> + (*pos)--;
> >>> + return 0;
> >>> + }
> >>> + return -EINVAL;
> >>> +}
> >>> +
> >>> +static int inc_cur_xfer_blks(int *pos, unsigned short *smallblks,
> >>> +lbaint_t blks) {
> >>> + /* try to increase the cur_xfer_blks */
> >>> + unsigned short size = (*pos >= 0) ? CALC_CUR_XFER_BLKS(*pos + 1) :
> 0;
> >>> + if (size <= blks && size <= USB_MAX_XFER_BLK) {
> >>> + *smallblks = size;
> >>> + (*pos)++;
> >>> + return 0;
> 

[U-Boot] [PATCH v2] tiny-printf: Correct the snprintf() implementation

[Simon Glass]

This current code passes the variable arguments list to sprintf(). This is
not correct. Fix it by calling _vprintf() directly.

This makes firefly-rk3288 boot again.

Fixes: abeb272 ("tiny-printf: Support snprintf()")
Signed-off-by: Simon Glass 
---

Changes in v2:
- Correct the 'Fixes' line

 lib/tiny-printf.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index 5ea2555..3c65fc9 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -168,8 +168,10 @@ int snprintf(char *buf, size_t size, const char *fmt, ...)
int ret;
 
va_start(va, fmt);
-   ret = sprintf(buf, fmt, va);
+   outstr = buf;
+   ret = _vprintf(fmt, va, putc_outstr);
va_end(va);
+   *outstr = '\0';
 
return ret;
 }
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH] tiny-printf: Correct the snprintf() implementation

[Simon Glass]

This current code passes the variable arguments list to sprintf(). This is
not correct. Fix it by calling _vprintf() directly.

This makes firefly-rk3288 boot again.

Fixes: 5c411d8 tiny-printf: Support snprintf()
Signed-off-by: Simon Glass 
---

 lib/tiny-printf.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index 5ea2555..3c65fc9 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -168,8 +168,10 @@ int snprintf(char *buf, size_t size, const char *fmt, ...)
int ret;
 
va_start(va, fmt);
-   ret = sprintf(buf, fmt, va);
+   outstr = buf;
+   ret = _vprintf(fmt, va, putc_outstr);
va_end(va);
+   *outstr = '\0';
 
return ret;
 }
-- 
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Re: [U-Boot] [PATCH 3/6] mtd: nand: Add the sunxi NAND controller driver

[Scott Wood]

On Tue, 2016-06-07 at 07:41 +0200, Boris Brezillon wrote:
> On Mon, 06 Jun 2016 18:54:03 -0500
> Scott Wood  wrote:
> 
> > Of course the driver model
> > is probably the long-term solution.
> 
> Definitely, and talking about things that need to be reworked, do you
> know why u-boot is using its own MTD partition infrastructure instead
> of relying on mtdpart.c?

U-Boot's partition code predates the importation of the MTD code.

> That's really a pain when one wants to add a new feature (like
> definitions of partitions in the DT, or SLC mode on MLC NANDs) because
> he has to do it twice.

Defining partitions in the DT isn't such a great idea, at least on reference
boards, as it's configuration that users are likely to want to change.

> And that's not the only inconsistent part in the MTD/NAND layer IMO.
> MTD is providing a generic abstraction for all flashes, but nand_util
> is still directly accessing the NAND layer instead of going through the
> MTD abstraction.

As with partitions, that code predates the existence of the MTD abstraction in
U-Boot.

> By using the MTD abstraction everywhere (I mean for all flash devices),
> we could provide generic utils (flash erase, flash write), even if
> specific tools might be needed in a few cases.

There are a lot of special NANDisms being handled in that code (bad block
skipping, JFFS2 OOB cleanmarkers, etc), so I wonder what a generic version
would look like.

> Anyway, good to hear that you plan to switch to the driver model.

I don't plan to do much of anything with the NAND code -- I'm still acting as
custodian because nobody stepped up when I asked for volunteers to take it
over a couple years back, but it's pretty low on my priority list regarding
active development[1].  But if someone else wants to DM-ize a NAND driver I
have no problem with that. :-)

-Scott

[1] Linux syncs are an exception, as they're easier to do than to review,
especially since a patch only shows the end result rather than the process to
produce it.
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Re: [U-Boot] [PATCH v2 1/2] nand: nand torture: follow sync with linux v4.6

[Scott Wood]

On 06/07/2016 06:47 AM, Max Krummenacher wrote:
> follow parameter name change (nand to mtd) to fix compiler error.
> 
> Signed-off-by: Max Krummenacher 
> 
> ---
> 
> Changes in v2:
> - Patch v1 1/1 went into master, but Scott's patch series syncing
>   with kernel v4.6 introduced an additional compile time error.
> 
>  drivers/mtd/nand/nand_util.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c
> index 5bba66a..e8bcc34 100644
> --- a/drivers/mtd/nand/nand_util.c
> +++ b/drivers/mtd/nand/nand_util.c
> @@ -820,7 +820,7 @@ int nand_torture(struct mtd_info *mtd, loff_t offset)
>  {
>   u_char patterns[] = {0xa5, 0x5a, 0x00};
>   struct erase_info instr = {
> - .mtd = nand,
> + .mtd = mtd,
>   .addr = offset,
>   .len = mtd->erasesize,
>   };

This got missed because no boards enable CONFIG_CMD_NAND_TORTURE.  If
you use this option could you enable it in the relevant board?

Or maybe we need to add an "allyesconfig"-type build (user-tunable
options only) to buildman?  And/or some other test configs that add up
to decent build coverage of options that are only enabled by users.

-Scott

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Re: [U-Boot] [PATCH v2] sunxi: Add the ability to recognize and auto-import uEnv-style data

[Siarhei Siamashka]

Hi,

On Wed, 8 Jun 2016 22:13:50 +0200
Hans de Goede  wrote:

> Hi,
> 
> On 08-06-16 20:23, Bernhard Nortmann wrote:
> > The patch converts one of the "reserved" fields in the sunxi SPL
> > header to a fel_uEnv_length entry. When booting over USB ("FEL
> > mode"), this enables the sunxi-fel utility to pass the string
> > length of uEnv.txt compatible data; at the same time requesting
> > that this data be imported into the U-Boot environment.
> >
> > If parse_spl_header() in the sunxi board.c encounters a non-zero
> > value in this header field, it will therefore call himport_r() to
> > merge the string (lines) passed via FEL into the default settings.
> > Environment vars can be changed this way even before U-Boot will
> > attempt to autoboot - specifically, this also allows overriding
> > "bootcmd".
> >
> > With fel_script_addr set and a zero fel_uEnv_length, U-Boot is
> > safe to assume that data in .scr format (a mkimage-type script)
> > was passed at fel_script_addr, and will handle it using the
> > existing mechanism ("bootcmd_fel").
> >
> > Signed-off-by: Bernhard Nortmann   
> 
> This patch looks good to me.
> 
> Siarhei any comments from your side ? If not then I'll add this to
> u-boot-sunxi/next.

Yes, it also looks good to me:
Acked-by: Siarhei Siamashka 

The only nitpick is about the subject line. It does not mention
FEL and may be a bit misleading.


Regarding the uEnv.txt support in general, I tried to grep U-Boot
sources and found that it's use is very much inconsistent on
different platforms. For example, there seems to be some sort
of leftover junk in sunxi-common.h:

http://git.denx.de/?p=u-boot.git;a=blob;f=include/configs/sunxi-common.h;h=b33cfb86f82e0831f5d19b1e473205f65efb5a96;hb=b104b3dc1dd90cdbf67ccf3c51b06e4f1592fe91#l481

Hardcoding the partition number and the file system type is hardly
something that the users may reasonably expect.

It also might be a good idea to do more or less uniform handling of
the uEnv.txt for both FEL boot and normal SD card boot. If Bernhard
wants to improve the uEnv.txt support in general, then could this
be possibly addressed later (not in this patch)?

Still the "doc/README.distro" mentions boot.scr but has no references
to uEnv.txt (which seems to imply that the uEnv.txt is a second class
citizen).


> >
> > ---
> > A corresponding proof-of-concept version of sunxi-fel is available
> > from my https://github.com/n1tehawk/sunxi-tools/tree/20160608_uEnv-magic
> > branch. I've picked up the suggestion to use a "#=uEnv" magic string
> > to request that a file be treated as uEnv.txt-style data.
> >
> > For example, use your text editor to save a my.env file with
> >
> > #=uEnv
> > myvar=world
> > bootcmd=echo "Hello $myvar."
> >
> > and then test it with
> > ./sunxi-fel uboot u-boot-sunxi-with-spl.bin write 0x4310 my.env
> >
> > You should see U-Boot's autoboot print the corresponding message
> > and drop you to the prompt, proving that you have successfully
> > overwritten the "bootcmd".
> >
> > Changes in v2:
> > - Patch renamed to something more suitable (was "sunxi: Add the
> >   ability to pass (script) filesize in the SPL header")
> > - The data field is now named fel_uEnv_length, and comes with
> >   a corresponding description in spl.h
> > - Instead of simply passing file size, fel_uEnv_length is now
> >   associated with uEnv.txt format. The patch modifies U-Boot's
> >   sunxi parse_spl_header() to auto-import such data.
> >
> >  arch/arm/include/asm/arch-sunxi/spl.h |  9 -
> >  board/sunxi/board.c   | 30 ++
> >  2 files changed, 30 insertions(+), 9 deletions(-)
> >
> > diff --git a/arch/arm/include/asm/arch-sunxi/spl.h 
> > b/arch/arm/include/asm/arch-sunxi/spl.h
> > index a0f33b0..a966a88 100644
> > --- a/arch/arm/include/asm/arch-sunxi/spl.h
> > +++ b/arch/arm/include/asm/arch-sunxi/spl.h
> > @@ -49,7 +49,14 @@ struct boot_file_head {
> > uint8_t spl_signature[4];
> > };
> > uint32_t fel_script_address;
> > -   uint32_t reserved1[3];
> > +   /*
> > +* If the fel_uEnv_length member below is set to a non-zero value,
> > +* it specifies the size (byte count) of data at fel_script_address.
> > +* At the same time this indicates that the data is in uEnv.txt
> > +* compatible format, ready to be imported via "env import -t".
> > +*/
> > +   uint32_t fel_uEnv_length;
> > +   uint32_t reserved1[2];
> > uint32_t boot_media;/* written here by the boot ROM */
> > uint32_t reserved2[5];  /* padding, align to 64 bytes */
> >  };
> > diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> > index d09cf6d..fc57e60 100644
> > --- a/board/sunxi/board.c
> > +++ b/board/sunxi/board.c
> > @@ -573,6 +573,7 @@ void get_board_serial(struct tag_serialnr *serialnr)
> >
> >  #if !defined(CONFIG_SPL_BUILD)
> >  #include 
> > +#include 
> >
> >  /*
> >   * Check the SPL 

Re: [U-Boot] [PATCH v2 2/2] nand: extend nand torture

[Benoît Thébaudeau]

Hi Max,

On Tue, Jun 7, 2016 at 1:46 PM, Max Krummenacher  wrote:
> nand torture currently works on exactly one nand block which is specified
> by giving the byteoffset to the beginning of the block.
>
> Extend this by allowing for a second parameter specifying the byte size
> to be tested.
>
> e.g.
> ==> nand torture 100
>
> NAND torture: device 0 offset 0x100 size 0x2 (nand block size 0x2)
> passed 1, failed 0
>
> ==> nand torture 100 4
>
> NAND torture: device 0 offset 0x100 size 0x4 (nand block size 0x2)
> passed 2, failed 0
>
> Signed-off-by: Max Krummenacher 
>
> ---
>
> Changes in v2:
> - findings from Benoît:
>   - change interface to be offset/size
>   - change the output to include both 'size tested' and 'nand block size'
>   - updated doc/README.nand accordingly
>   - I did not implement the suggestion to move the code into the
> nand_torture() function. Likely one uses the extended functionality
> only during HW bringup interactively. If one would want to test
> multiple blocks from code one would also want to know the testresult
> of each individual block rather than only having a return parameter
> indicating a 'all good' or 'at least one block failed'.
>
>  cmd/nand.c  | 34 ++
>  doc/README.nand |  6 +-
>  2 files changed, 31 insertions(+), 9 deletions(-)
>
> diff --git a/cmd/nand.c b/cmd/nand.c
> index 583a18f..8ade5e2 100644
> --- a/cmd/nand.c
> +++ b/cmd/nand.c
> @@ -647,6 +647,8 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, 
> char * const argv[])
>
>  #ifdef CONFIG_CMD_NAND_TORTURE
> if (strcmp(cmd, "torture") == 0) {
> +   loff_t endoff;
> +   unsigned failed = 0, passed = 0;
> if (argc < 3)
> goto usage;
>
> @@ -654,13 +656,28 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int 
> argc, char * const argv[])
> puts("Offset is not a valid number\n");
> return 1;
> }
> -
> -   printf("\nNAND torture: device %d offset 0x%llx size 0x%x\n",
> -   dev, off, mtd->erasesize);
> -   ret = nand_torture(mtd, off);
> -   printf(" %s\n", ret ? "Failed" : "Passed");
> -
> -   return ret == 0 ? 0 : 1;
> +   size = mtd->erasesize;
> +   if (argc > 3)
> +   if (!str2off(argv[3], )) {
> +   puts("Size is not a valid number\n");
> +   return 1;
> +   }
> +   printf("\nNAND torture: device %d offset 0x%llx size 0x%llx 
> (nand block size 0x%x)\n",
> +  dev, off, size, mtd->erasesize);
> +
> +   endoff = off + size;
> +   while (off < endoff) {
> +   ret = nand_torture(mtd, off);
> +   if (ret) {
> +   failed++;
> +   printf(" off 0x%llx %s\n", off, "Failed");
> +   } else {
> +   passed++;
> +   }
> +   off += mtd->erasesize;
> +   }
> +   printf("passed %u, failed %u\n", passed, failed);
> +   return failed == 0 ? 0 : 1;

The given offset could also start anywhere, so it's better to
auto-align it like the size.

If the arguments extend beyond the end of the flash, then
nand_torture() will return an error at each iteration, so it's better
to break the loop or not to start it in this case.

It's better to print the range actually tortured than the arguments
from the user.

So what about the following?

@@ -647,6 +647,9 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int
argc, char * const argv[])

 #ifdef CONFIG_CMD_NAND_TORTURE
 if (strcmp(cmd, "torture") == 0) {
+loff_t endoff;
+unsigned int failed = 0, passed = 0;
+
 if (argc < 3)
 goto usage;

@@ -655,12 +658,36 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
 return 1;
 }

-printf("\nNAND torture: device %d offset 0x%llx size 0x%x\n",
-dev, off, mtd->erasesize);
-ret = nand_torture(mtd, off);
-printf(" %s\n", ret ? "Failed" : "Passed");
+size = mtd->erasesize;
+if (argc > 3 && !str2off(argv[3], )) {
+puts("Size is not a valid number\n");
+return 1;
+}

-return ret == 0 ? 0 : 1;
+endoff = off + size;
+if (endoff > mtd->size) {
+puts("Arguments beyond end of NAND\n");
+return 1;
+}
+
+off = round_down(off, mtd->erasesize);
+endoff = round_up(endoff, mtd->erasesize);
+size = endoff - off;
+printf("\nNAND torture: device %d offset 0x%llx size 

Re: [U-Boot] [PATCH 2/2] nand: extend nand torture

[Benoît Thébaudeau]

Hi Max,

On Tue, Jun 7, 2016 at 12:57 PM, Max Krummenacher  wrote:
> Hi Benoît,
>
> Thank you for your review.

You're welcome.

> I wanted to wait for Scott's patchseries to make it into master to
> allow for potential needed
> changes.

No problem.

> 2016-05-31 22:21 GMT+02:00 Benoît Thébaudeau 
> :
> ...
>>> Extend this by allowing for a second parameter specifying the byte offset
>>> to the last block to be tested.
>>>
>>
>> End offsets are always ambiguous because users can hesitate between
>> the offset of the first byte of the last block, the offset of the last
>> byte of the last block, and the offset of the first byte of the block
>> following the last one (if any). A byte size would probably be better
>> here, and it would also be more consistent with the other nand
>> commands.
>
> Ok. I will change the interface to use offset/size.

Good.

> ...
>>> NAND torture: device 0 offset 0x100 size 0x2
>>> passed 2, failed 0
>>>
>>
>> With more than one block to test, the printed size becomes ambiguous
>> here. It would be better to indicate that it is the erase size of the
>> block. The total test size could also be printed, either instead of
>> the erase size, or besides it.
>>
> Ok. I will change this to print test size and block size, e.g. like:
> NAND torture: device 0 offset 0x100 size 0x4 (nand block size 0x2)

Good.

> ...
>>> -   return ret == 0 ? 0 : 1;
>>> +   ret = nand_torture(nand, off);
>>> +   if (ret) {
> ...
>>
>> A size parameter could probably be added to nand_torture() instead of
>> handling the range in the command, so that the direct usages of
>> nand_torture() (in or out of tree) can also benefit from this
>> enhancement.
>
> I disagree here.
> Likely one uses the extended functionality only during HW bringup and
> only interactively. If one would want to test multiple blocks from code one
> would also want to know the testresult of each individual block rather
> than only having a return parameter indicating a 'all good' or
> 'at least one block failed'.
> Even here in the interactive 'nand torture' cmd the printf of a failed
> block in the loop
> is a usecase of this.

Makes sense. Agreed.

Best regards,
Benoît
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Re: [U-Boot] [PATCH v2] mx6: Add Phytec PCM058 i.MX6 Quad

[Fabio Estevam]

On Wed, Jun 8, 2016 at 5:50 AM, Stefano Babic  wrote:
> Add Phytec-i.MX6 SOM with NAND
>
>   Support:
>- 1GB RAM
>- Ethernet
>- SPI-NOR Flash
>- NAND (1024 MB)
>- external SD
>- UART
>
> Signed-off-by: Stefano Babic 

Reviewed-by: Fabio Estevam 
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[U-Boot] pull request: u-boot-uniphier/master

[Masahiro Yamada]

Hi Tom,

Here are some more UniPhier updates for -rc2.

- Add eMMC boot suuport for new ARMv8 SoCs
- Misc fixes

Please pull!


The following changes since commit b104b3dc1dd90cdbf67ccf3c51b06e4f1592fe91:

  Prepare v2016.07-rc1 (2016-06-06 17:43:54 -0400)

are available in the git repository at:

  git://git.denx.de/u-boot-uniphier.git master

for you to fetch changes up to 9c2f9b2da650907b928995350cc4e29480fb0f80:

  ARM: uniphier: insert dsb barrier to ensure visibility of store
(2016-06-09 08:19:13 +0900)


Masahiro Yamada (6):
  ARM: uniphier: support eMMC boot for PH1-LD11 and PH1-LD20
  ARM: uniphier: fix boot mode for PH1-LD11
  ARM: uniphier: check return code of setenv()
  ARM: uniphier: do not overwrite fdt_file environment
  ARM: uniphier: do not erase when updating U-Boot image in eMMC device
  ARM: uniphier: insert dsb barrier to ensure visibility of store

 arch/arm/mach-uniphier/arm64/smp_kick_cpus.c  |   4 +-
 arch/arm/mach-uniphier/board_late_init.c  |   7 +-
 arch/arm/mach-uniphier/boot-mode/Makefile |   4 ++
 arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c |  19 +-
 arch/arm/mach-uniphier/boot-mode/boot-mode.c  |  25 +++-
 arch/arm/mach-uniphier/boot-mode/spl_board.c  | 128
+
 include/configs/uniphier.h|   5 +-
 7 files changed, 181 insertions(+), 11 deletions(-)
 create mode 100644 arch/arm/mach-uniphier/boot-mode/spl_board.c


-- 
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Masahiro Yamada
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Re: [U-Boot] [PATCH v2] ARM: uniphier: insert dsb barrier to ensure visibility of store

[Masahiro Yamada]

2016-06-08 18:02 GMT+09:00 Masahiro Yamada :
> I noticed secondary CPUs sometimes fail to wake up, and the root
> cause is that the sev instruction wakes up slave CPUs before the
> preceding the register write is observed by them.
>
> The read-back of the accessed register does not guarantee the order.
> In order to ensure the order between the register write and the sev
> instruction, a dsb instruction should be executed prior to the sev.
>
> Signed-off-by: Masahiro Yamada 


Applied to u-boot-uniphier/master.


-- 
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Masahiro Yamada
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Re: [U-Boot] [PATCH 0/5] ARM: uniphier: some more UniPhier updates for v2016.07-rc2

[Masahiro Yamada]

2016-06-07 21:03 GMT+09:00 Masahiro Yamada :
>
>
>
> Masahiro Yamada (5):
>   ARM: uniphier: check return code of setenv()
>   ARM: uniphier: do not overwrite fdt_file environment
>   ARM: uniphier: do not overwrite bootmode environment
>   ARM: uniphier: do not erase when updating U-Boot image in eMMC device
>   ARM: uniphier: insert dsb barrier to ensure the visibility
>


Series, applied to u-boot-uniphier/master
except 3/5, 5/5.


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Re: [U-Boot] [PATCH 2/2] ARM: uniphier: fix boot mode for PH1-LD11

[Masahiro Yamada]

2016-06-04 22:39 GMT+09:00 Masahiro Yamada :
> This function is shared between PH1-LD11 and PH1-LD20.  The difference
> is the boot-mode latch for the USB boot mode.
>
> Signed-off-by: Masahiro Yamada 



Applied to u-boot-uniphier/master.


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Re: [U-Boot] [PATCH 1/2] ARM: uniphier: support eMMC boot for PH1-LD11 and PH1-LD20

[Masahiro Yamada]

2016-06-04 22:39 GMT+09:00 Masahiro Yamada :
> The Boot ROM on PH1-LD11/LD20 exports built-in APIs to load images
> from an eMMC device.  They are useful to reduce the memory footprint
> of SPL, rather than compiling the whole MMC framework.
>
> Signed-off-by: Masahiro Yamada 


Applied to u-boot-uniphier/master.


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Re: [U-Boot] [PATCH v2] sunxi: Add the ability to recognize and auto-import uEnv-style data

[Bernhard Nortmann]

Hi Hans!

Am 08.06.2016 um 22:13 schrieb Hans de Goede:

Hi,
[...]

This patch looks good to me.

Siarhei any comments from your side ? If not then I'll add this to
u-boot-sunxi/next.

Regards,

Hans


Thanks for looking into it. One small thing I only noticed after posting
the patch: The last "return;" at the end of parse_spl_header() is unneeded
and may safely be dropped.

Regards, B. Nortmann
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Re: [U-Boot] [PATCH] mx6qsabreauto: Avoid hardcoded RAM size

[Fabio Estevam]

Hi Vanessa,

On Wed, Jun 8, 2016 at 3:17 PM, Vanessa Maegima  wrote:
> Instead of passing the total RAM size via PHYS_SDRAM_SIZE option,
> we should better use imx_ddr_size() function, which automatically
> determines the RAM size.
>
> Signed-off-by: Vanessa Maegima 

Thanks for the patch:

Acked-by: Fabio Estevam 
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Re: [U-Boot] [PATCH] mx6sabresd: Allow LVDS backlight to be functional after a kernel reboot

[Fabio Estevam]

Hi Marco,

On Wed, Jun 8, 2016 at 3:05 PM, Marco Franchi  wrote:
> Currently the LVDS backlight does not work in U-Boot after a “reboot” comand
> in the kernel.
>
> This problem occurs because the kernel uses this pin in PWM mode and U-Boot
> does not configure the backlight pin as GPIO functionality.
>
> So fix the problem by explicitly configuring the backlight pin as GPIO in
> U-Boot.
>
> Signed-off-by: Marco Franchi 

Thanks for fixing this bug:

Tested-by: Fabio Estevam 
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Re: [U-Boot] [PATCH] mx6sabresd: Allow LVDS backlight to be functional after a kernel reboot

[Stefano Babic]

Hi Marco,

On 08/06/2016 20:05, Marco Franchi wrote:
> Currently the LVDS backlight does not work in U-Boot after a “reboot” comand
> in the kernel.
> 
> This problem occurs because the kernel uses this pin in PWM mode and U-Boot
> does not configure the backlight pin as GPIO functionality.
> 
> So fix the problem by explicitly configuring the backlight pin as GPIO in
> U-Boot.
> 
> Signed-off-by: Marco Franchi 
> ---
>  board/freescale/mx6sabresd/mx6sabresd.c | 18 --
>  1 file changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git a/board/freescale/mx6sabresd/mx6sabresd.c 
> b/board/freescale/mx6sabresd/mx6sabresd.c
> index 54ba36b..28c969d 100644
> --- a/board/freescale/mx6sabresd/mx6sabresd.c
> +++ b/board/freescale/mx6sabresd/mx6sabresd.c
> @@ -177,13 +177,27 @@ static iomux_v3_cfg_t const rgb_pads[] = {
>   MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL),
>   MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL),
>   MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const bl_pads[] = {
>   MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
>  };
>  
> +static void enable_backlight(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(bl_pads, ARRAY_SIZE(bl_pads));
> + gpio_direction_output(DISP0_PWR_EN, 1);
> +}
> +
>  static void enable_rgb(struct display_info_t const *dev)
>  {
>   imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads));
> - gpio_direction_output(DISP0_PWR_EN, 1);
> + enable_backlight();
> +}
> +
> +static void enable_lvds(struct display_info_t const *dev)
> +{
> + enable_backlight();
>  }
>  
>  static struct i2c_pads_info i2c_pad_info1 = {
> @@ -370,7 +384,7 @@ struct display_info_t const displays[] = {{
>   .addr   = 0,
>   .pixfmt = IPU_PIX_FMT_RGB666,
>   .detect = NULL,
> - .enable = NULL,
> + .enable = enable_lvds,
>   .mode   = {
>   .name   = "Hannstar-XGA",
>   .refresh= 60,
> 

Acked-by: Stefano Babic 

Best regards,
Stefano Babic


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[U-Boot] Továbbítás: u-boot

[kri...@nmdps.net]

Küldve az én HTC-mről

- Továbbított üzenet -
Feladó: kri...@nmdps.net
Címzett: 
Tárgy: u-boot
Dátum: Sze, jún. 8, 2016 19:12

Dear developer,

I own a bananapi m2, on which u-boot does not boot up since commit 
90b7fc924adfe7f1745dcf6a1dabb9e77aa762a7.

The console is repeating:

U-Boot 2016.05-00393-g90b7fc9 (Jun 08 2016 - 18:57:34 +0200) Allwinner 
Technology

CPU:   Allwinner A31s (SUN6I)
Model: Sinovoip BPI-M2
DRAM:  1 GiB
MMC:   SUNXI SD/MMC: 0
*** Warning - bad CRC, using default environment

In:serial
Out:   serial
Err:   serial
Net:   data abort
pc : [<7ef5f6f4>]  lr : [<7ef80b94>]
reloc pc : [<4a0016f4>]lr : [<4a022b94>]
sp : 7af36f80  ip :  fp : 0017
r10: 7efab5e8  r9 : 7af3dee8 r8 : 40a0
r7 : 7ef9ee0c  r6 :  r5 : 0001  r4 : 
r3 : 7ef80b70  r2 : 0001 r1 :   r0 : ea0e
Flags: nzCv  IRQs off  FIQs off  Mode SVC_32
Resetting CPU ...

resetting ...

U-Boot SPL 2016.05-00393-g90b7fc9 (Jun 08 2016 - 18:57:34)
DRAM: 1024 MiB
Trying to boot from MMC1


U-Boot 2016.05-00393-g90b7fc9 (Jun 08 2016 - 18:57:34 +0200) Allwinner 
Technology

CPU:   Allwinner A31s (SUN6I)
Model: Sinovoip BPI-M2
DRAM:  1 GiB
MMC:   SUNXI SD/MMC: 0
*** Warning - bad CRC, using default environment

In:serial
Out:   serial
Err:   serial
Net:   data abort
pc : [<7ef5f6f4>]  lr : [<7ef80b94>]
reloc pc : [<4a0016f4>]lr : [<4a022b94>]
sp : 7af36f80  ip :  fp : 0017
r10: 7efab5e8  r9 : 7af3dee8 r8 : 40a0
r7 : 7ef9ee0c  r6 :  r5 : 0001  r4 : 
r3 : 7ef80b70  r2 : 0001 r1 :   r0 : ea0e
Flags: nzCv  IRQs off  FIQs off  Mode SVC_32
Resetting CPU ...

resetting ...

U-Boot SPL 2016.05-00393-g90b7fc9 (Jun 08 2016 - 18:57:34)
DRAM: 1024 MiB
Trying to boot from MMC1


U-Boot 2016.05-00393-g90b7fc9 (Jun 08 2016 - 18:57:34 +0200) Allwinner 
Technology

CPU:   Allwinner A31s (SUN6I)
Model: Sinovoip BPI-M2
DRAM:  1 GiB
MMC:   SUNXI SD/MMC: 0
*** Warning - bad CRC, using default environment

In:serial
Out:   serial
Err:   serial
Net:   data abort
pc : [<7ef5f6f4>]  lr : [<7ef80b94>]
reloc pc : [<4a0016f4>]lr : [<4a022b94>]
sp : 7af36f80  ip :  fp : 0017
r10: 7efab5e8  r9 : 7af3dee8 r8 : 40a0
r7 : 7ef9ee0c  r6 :  r5 : 0001  r4 : 
r3 : 7ef80b70  r2 : 0001 r1 :   r0 : ea0e
Flags: nzCv  IRQs off  FIQs off  Mode SVC_32

and so on.

How could I help debugging, resolving this issue?

Regards,
Richard Kojedzinszky
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Re: [U-Boot] [PATCH v2] sunxi: Add the ability to recognize and auto-import uEnv-style data

[Hans de Goede]

Hi,

On 08-06-16 20:23, Bernhard Nortmann wrote:

The patch converts one of the "reserved" fields in the sunxi SPL
header to a fel_uEnv_length entry. When booting over USB ("FEL
mode"), this enables the sunxi-fel utility to pass the string
length of uEnv.txt compatible data; at the same time requesting
that this data be imported into the U-Boot environment.

If parse_spl_header() in the sunxi board.c encounters a non-zero
value in this header field, it will therefore call himport_r() to
merge the string (lines) passed via FEL into the default settings.
Environment vars can be changed this way even before U-Boot will
attempt to autoboot - specifically, this also allows overriding
"bootcmd".

With fel_script_addr set and a zero fel_uEnv_length, U-Boot is
safe to assume that data in .scr format (a mkimage-type script)
was passed at fel_script_addr, and will handle it using the
existing mechanism ("bootcmd_fel").

Signed-off-by: Bernhard Nortmann 


This patch looks good to me.

Siarhei any comments from your side ? If not then I'll add this to
u-boot-sunxi/next.

Regards,

Hans





---
A corresponding proof-of-concept version of sunxi-fel is available
from my https://github.com/n1tehawk/sunxi-tools/tree/20160608_uEnv-magic
branch. I've picked up the suggestion to use a "#=uEnv" magic string
to request that a file be treated as uEnv.txt-style data.

For example, use your text editor to save a my.env file with

#=uEnv
myvar=world
bootcmd=echo "Hello $myvar."

and then test it with
./sunxi-fel uboot u-boot-sunxi-with-spl.bin write 0x4310 my.env

You should see U-Boot's autoboot print the corresponding message
and drop you to the prompt, proving that you have successfully
overwritten the "bootcmd".

Changes in v2:
- Patch renamed to something more suitable (was "sunxi: Add the
  ability to pass (script) filesize in the SPL header")
- The data field is now named fel_uEnv_length, and comes with
  a corresponding description in spl.h
- Instead of simply passing file size, fel_uEnv_length is now
  associated with uEnv.txt format. The patch modifies U-Boot's
  sunxi parse_spl_header() to auto-import such data.

 arch/arm/include/asm/arch-sunxi/spl.h |  9 -
 board/sunxi/board.c   | 30 ++
 2 files changed, 30 insertions(+), 9 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/spl.h 
b/arch/arm/include/asm/arch-sunxi/spl.h
index a0f33b0..a966a88 100644
--- a/arch/arm/include/asm/arch-sunxi/spl.h
+++ b/arch/arm/include/asm/arch-sunxi/spl.h
@@ -49,7 +49,14 @@ struct boot_file_head {
uint8_t spl_signature[4];
};
uint32_t fel_script_address;
-   uint32_t reserved1[3];
+   /*
+* If the fel_uEnv_length member below is set to a non-zero value,
+* it specifies the size (byte count) of data at fel_script_address.
+* At the same time this indicates that the data is in uEnv.txt
+* compatible format, ready to be imported via "env import -t".
+*/
+   uint32_t fel_uEnv_length;
+   uint32_t reserved1[2];
uint32_t boot_media;/* written here by the boot ROM */
uint32_t reserved2[5];  /* padding, align to 64 bytes */
 };
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index d09cf6d..fc57e60 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -573,6 +573,7 @@ void get_board_serial(struct tag_serialnr *serialnr)

 #if !defined(CONFIG_SPL_BUILD)
 #include 
+#include 

 /*
  * Check the SPL header for the "sunxi" variant. If found: parse values
@@ -582,17 +583,30 @@ void get_board_serial(struct tag_serialnr *serialnr)
 static void parse_spl_header(const uint32_t spl_addr)
 {
struct boot_file_head *spl = (void *)(ulong)spl_addr;
-   if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) == 0) {
-   uint8_t spl_header_version = spl->spl_signature[3];
-   if (spl_header_version == SPL_HEADER_VERSION) {
-   if (spl->fel_script_address)
-   setenv_hex("fel_scriptaddr",
-  spl->fel_script_address);
-   return;
-   }
+   if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
+   return; /* signature mismatch, no usable header */
+
+   uint8_t spl_header_version = spl->spl_signature[3];
+   if (spl_header_version != SPL_HEADER_VERSION) {
printf("sunxi SPL version mismatch: expected %u, got %u\n",
   SPL_HEADER_VERSION, spl_header_version);
+   return;
+   }
+   if (!spl->fel_script_address)
+   return;
+
+   if (spl->fel_uEnv_length != 0) {
+   /*
+* data is expected in uEnv.txt compatible format, so "env
+* import -t" the string(s) at fel_script_address right away.
+*/
+   himport_r(_htab, (char 

[U-Boot] [PATCH] ARM: board: cm-fx6: fix mmc for old revisions of utilite

[Christopher Spinrath]

Old revisions of Utilite (based on cmfx6) do not have a dedicated
card detect pin. But the card is removable by the user and card
detection can be realized with polling (e.g. supported by Linux).

Add the broken-cd property to the mmc device tree instead of the
non-removable property to make card detection possible if polling
is supported.

Fixes: 41855186afd3 ("arm: mx6: cm-fx6: modify device tree for old revisions of 
utilite")
Signed-off-by: Christopher Spinrath 
---
 board/compulab/cm_fx6/cm_fx6.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
index a21e7b0..712057a 100644
--- a/board/compulab/cm_fx6/cm_fx6.c
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -610,7 +610,7 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_shrink_to_minimum(blob); /* Make room for new properties */
nodeoffset = fdt_path_offset(blob, USDHC3_PATH);
fdt_delprop(blob, nodeoffset, "cd-gpios");
-   fdt_find_and_setprop(blob, USDHC3_PATH, "non-removable",
+   fdt_find_and_setprop(blob, USDHC3_PATH, "broken-cd",
 NULL, 0, 1);
fdt_find_and_setprop(blob, USDHC3_PATH, "keep-power-in-suspend",
 NULL, 0, 1);
-- 
2.8.3

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[U-Boot] [PATCH] mx6sabresd: Allow LVDS backlight to be functional after a kernel reboot

[Marco Franchi]

Currently the LVDS backlight does not work in U-Boot after a “reboot” comand
in the kernel.

This problem occurs because the kernel uses this pin in PWM mode and U-Boot
does not configure the backlight pin as GPIO functionality.

So fix the problem by explicitly configuring the backlight pin as GPIO in
U-Boot.

Signed-off-by: Marco Franchi 
---
 board/freescale/mx6sabresd/mx6sabresd.c | 18 --
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/board/freescale/mx6sabresd/mx6sabresd.c 
b/board/freescale/mx6sabresd/mx6sabresd.c
index 54ba36b..28c969d 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -177,13 +177,27 @@ static iomux_v3_cfg_t const rgb_pads[] = {
MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const bl_pads[] = {
MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
+static void enable_backlight(void)
+{
+   imx_iomux_v3_setup_multiple_pads(bl_pads, ARRAY_SIZE(bl_pads));
+   gpio_direction_output(DISP0_PWR_EN, 1);
+}
+
 static void enable_rgb(struct display_info_t const *dev)
 {
imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads));
-   gpio_direction_output(DISP0_PWR_EN, 1);
+   enable_backlight();
+}
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+   enable_backlight();
 }
 
 static struct i2c_pads_info i2c_pad_info1 = {
@@ -370,7 +384,7 @@ struct display_info_t const displays[] = {{
.addr   = 0,
.pixfmt = IPU_PIX_FMT_RGB666,
.detect = NULL,
-   .enable = NULL,
+   .enable = enable_lvds,
.mode   = {
.name   = "Hannstar-XGA",
.refresh= 60,
-- 
2.7.4

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[U-Boot] [PATCH] mx6qsabreauto: Avoid hardcoded RAM size

[Vanessa Maegima]

Instead of passing the total RAM size via PHYS_SDRAM_SIZE option,
we should better use imx_ddr_size() function, which automatically
determines the RAM size.

Signed-off-by: Vanessa Maegima 
---
 board/freescale/mx6qsabreauto/mx6qsabreauto.c | 2 +-
 include/configs/mx6qsabreauto.h   | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c 
b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index d63a979..a3ed4cd 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -64,7 +64,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
 {
-   gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+   gd->ram_size = imx_ddr_size();
 
return 0;
 }
diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h
index 6039fc4..200e468 100644
--- a/include/configs/mx6qsabreauto.h
+++ b/include/configs/mx6qsabreauto.h
@@ -13,7 +13,6 @@
 #define CONFIG_MXC_UART_BASE   UART4_BASE
 #define CONFIG_CONSOLE_DEV "ttymxc3"
 #define CONFIG_MMCROOT "/dev/mmcblk0p2"
-#define PHYS_SDRAM_SIZE(2u * 1024 * 1024 * 1024)
 
 /* USB Configs */
 #define CONFIG_USB_EHCI
-- 
1.9.1

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Re: [U-Boot] [PATCH] mx6qsabreauto: Avoid hardcoded RAM size

[Stefano Babic]

Hi Vanessa,

On 08/06/2016 20:17, Vanessa Maegima wrote:
> Instead of passing the total RAM size via PHYS_SDRAM_SIZE option,
> we should better use imx_ddr_size() function, which automatically
> determines the RAM size.
> 
> Signed-off-by: Vanessa Maegima 
> ---
>  board/freescale/mx6qsabreauto/mx6qsabreauto.c | 2 +-
>  include/configs/mx6qsabreauto.h   | 1 -
>  2 files changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c 
> b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
> index d63a979..a3ed4cd 100644
> --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
> +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
> @@ -64,7 +64,7 @@ DECLARE_GLOBAL_DATA_PTR;
>  
>  int dram_init(void)
>  {
> - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
> + gd->ram_size = imx_ddr_size();
>  

Right - this board was not yet updated.

>   return 0;
>  }
> diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h
> index 6039fc4..200e468 100644
> --- a/include/configs/mx6qsabreauto.h
> +++ b/include/configs/mx6qsabreauto.h
> @@ -13,7 +13,6 @@
>  #define CONFIG_MXC_UART_BASE UART4_BASE
>  #define CONFIG_CONSOLE_DEV   "ttymxc3"
>  #define CONFIG_MMCROOT   "/dev/mmcblk0p2"
> -#define PHYS_SDRAM_SIZE  (2u * 1024 * 1024 * 1024)
>  
>  /* USB Configs */
>  #define CONFIG_USB_EHCI
> 

Acked-by: Stefano Babic 

Best regards,
Stefano Babic

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[U-Boot] [PATCH v2] sunxi: Add the ability to recognize and auto-import uEnv-style data

[Bernhard Nortmann]

The patch converts one of the "reserved" fields in the sunxi SPL
header to a fel_uEnv_length entry. When booting over USB ("FEL
mode"), this enables the sunxi-fel utility to pass the string
length of uEnv.txt compatible data; at the same time requesting
that this data be imported into the U-Boot environment.

If parse_spl_header() in the sunxi board.c encounters a non-zero
value in this header field, it will therefore call himport_r() to
merge the string (lines) passed via FEL into the default settings.
Environment vars can be changed this way even before U-Boot will
attempt to autoboot - specifically, this also allows overriding
"bootcmd".

With fel_script_addr set and a zero fel_uEnv_length, U-Boot is
safe to assume that data in .scr format (a mkimage-type script)
was passed at fel_script_addr, and will handle it using the
existing mechanism ("bootcmd_fel").

Signed-off-by: Bernhard Nortmann 

---
A corresponding proof-of-concept version of sunxi-fel is available
from my https://github.com/n1tehawk/sunxi-tools/tree/20160608_uEnv-magic
branch. I've picked up the suggestion to use a "#=uEnv" magic string
to request that a file be treated as uEnv.txt-style data.

For example, use your text editor to save a my.env file with

#=uEnv
myvar=world
bootcmd=echo "Hello $myvar."

and then test it with
./sunxi-fel uboot u-boot-sunxi-with-spl.bin write 0x4310 my.env

You should see U-Boot's autoboot print the corresponding message
and drop you to the prompt, proving that you have successfully
overwritten the "bootcmd".

Changes in v2:
- Patch renamed to something more suitable (was "sunxi: Add the
  ability to pass (script) filesize in the SPL header")
- The data field is now named fel_uEnv_length, and comes with
  a corresponding description in spl.h
- Instead of simply passing file size, fel_uEnv_length is now
  associated with uEnv.txt format. The patch modifies U-Boot's
  sunxi parse_spl_header() to auto-import such data.

 arch/arm/include/asm/arch-sunxi/spl.h |  9 -
 board/sunxi/board.c   | 30 ++
 2 files changed, 30 insertions(+), 9 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/spl.h 
b/arch/arm/include/asm/arch-sunxi/spl.h
index a0f33b0..a966a88 100644
--- a/arch/arm/include/asm/arch-sunxi/spl.h
+++ b/arch/arm/include/asm/arch-sunxi/spl.h
@@ -49,7 +49,14 @@ struct boot_file_head {
uint8_t spl_signature[4];
};
uint32_t fel_script_address;
-   uint32_t reserved1[3];
+   /*
+* If the fel_uEnv_length member below is set to a non-zero value,
+* it specifies the size (byte count) of data at fel_script_address.
+* At the same time this indicates that the data is in uEnv.txt
+* compatible format, ready to be imported via "env import -t".
+*/
+   uint32_t fel_uEnv_length;
+   uint32_t reserved1[2];
uint32_t boot_media;/* written here by the boot ROM */
uint32_t reserved2[5];  /* padding, align to 64 bytes */
 };
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index d09cf6d..fc57e60 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -573,6 +573,7 @@ void get_board_serial(struct tag_serialnr *serialnr)
 
 #if !defined(CONFIG_SPL_BUILD)
 #include 
+#include 
 
 /*
  * Check the SPL header for the "sunxi" variant. If found: parse values
@@ -582,17 +583,30 @@ void get_board_serial(struct tag_serialnr *serialnr)
 static void parse_spl_header(const uint32_t spl_addr)
 {
struct boot_file_head *spl = (void *)(ulong)spl_addr;
-   if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) == 0) {
-   uint8_t spl_header_version = spl->spl_signature[3];
-   if (spl_header_version == SPL_HEADER_VERSION) {
-   if (spl->fel_script_address)
-   setenv_hex("fel_scriptaddr",
-  spl->fel_script_address);
-   return;
-   }
+   if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
+   return; /* signature mismatch, no usable header */
+
+   uint8_t spl_header_version = spl->spl_signature[3];
+   if (spl_header_version != SPL_HEADER_VERSION) {
printf("sunxi SPL version mismatch: expected %u, got %u\n",
   SPL_HEADER_VERSION, spl_header_version);
+   return;
+   }
+   if (!spl->fel_script_address)
+   return;
+
+   if (spl->fel_uEnv_length != 0) {
+   /*
+* data is expected in uEnv.txt compatible format, so "env
+* import -t" the string(s) at fel_script_address right away.
+*/
+   himport_r(_htab, (char *)spl->fel_script_address,
+ spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
+   return;
}
+   /* otherwise assume .scr format (mkimage-type 

[U-Boot] [PATCH v2 2/6] mtd: nand: add common DT init code

[Boris Brezillon]

From: Brian Norris 

These are already-documented common bindings for NAND chips. Let's
handle them in nand_base.

If NAND controller drivers need to act on this data before bringing up
the NAND chip (e.g., fill out ECC callback functions, change HW modes,
etc.), then they can do so between calling nand_scan_ident() and
nand_scan_tail().

The original commit has been slightly reworked to use the fdtdec_xxx()
helpers (instead of the of_() ones).

Signed-off-by: Brian Norris 
Signed-off-by: Boris Brezillon 
Acked-by: Hans de Goede 
---
 drivers/mtd/nand/nand_base.c | 70 
 include/linux/mtd/nand.h |  3 ++
 2 files changed, 73 insertions(+)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 74c563c..c72ff86 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -29,6 +29,9 @@
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 #include 
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+#include 
+#endif
 #include 
 #include 
 #include 
@@ -3764,6 +3767,66 @@ ident_done:
return type;
 }
 
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+DECLARE_GLOBAL_DATA_PTR;
+
+static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node)
+{
+   int ret, ecc_mode = -1, ecc_strength, ecc_step;
+   const void *blob = gd->fdt_blob;
+   const char *str;
+
+   ret = fdtdec_get_int(blob, node, "nand-bus-width", -1);
+   if (ret == 16)
+   chip->options |= NAND_BUSWIDTH_16;
+
+   if (fdtdec_get_bool(blob, node, "nand-on-flash-bbt"))
+   chip->bbt_options |= NAND_BBT_USE_FLASH;
+
+   str = fdt_getprop(blob, node, "nand-ecc-mode", NULL);
+   if (str) {
+   if (!strcmp(str, "none"))
+   ecc_mode = NAND_ECC_NONE;
+   else if (!strcmp(str, "soft"))
+   ecc_mode = NAND_ECC_SOFT;
+   else if (!strcmp(str, "hw"))
+   ecc_mode = NAND_ECC_HW;
+   else if (!strcmp(str, "hw_syndrome"))
+   ecc_mode = NAND_ECC_HW_SYNDROME;
+   else if (!strcmp(str, "hw_oob_first"))
+   ecc_mode = NAND_ECC_HW_OOB_FIRST;
+   else if (!strcmp(str, "soft_bch"))
+   ecc_mode = NAND_ECC_SOFT_BCH;
+   }
+
+
+   ecc_strength = fdtdec_get_int(blob, node, "nand-ecc-strength", -1);
+   ecc_step = fdtdec_get_int(blob, node, "nand-ecc-step-size", -1);
+
+   if ((ecc_step >= 0 && !(ecc_strength >= 0)) ||
+   (!(ecc_step >= 0) && ecc_strength >= 0)) {
+   pr_err("must set both strength and step size in DT\n");
+   return -EINVAL;
+   }
+
+   if (ecc_mode >= 0)
+   chip->ecc.mode = ecc_mode;
+
+   if (ecc_strength >= 0)
+   chip->ecc.strength = ecc_strength;
+
+   if (ecc_step > 0)
+   chip->ecc.size = ecc_step;
+
+   return 0;
+}
+#else
+static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node)
+{
+   return 0;
+}
+#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
+
 /**
  * nand_scan_ident - [NAND Interface] Scan for the NAND device
  * @mtd: MTD device structure
@@ -3780,6 +3843,13 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips,
int i, nand_maf_id, nand_dev_id;
struct nand_chip *chip = mtd_to_nand(mtd);
struct nand_flash_dev *type;
+   int ret;
+
+   if (chip->flash_node) {
+   ret = nand_dt_init(mtd, chip, chip->flash_node);
+   if (ret)
+   return ret;
+   }
 
/* Set the default functions */
nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index b5a02c3..29aae43 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -590,6 +590,7 @@ struct nand_buffers {
  * flash device
  * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
  * flash device.
+ * @flash_node:[BOARDSPECIFIC] device node describing this 
instance
  * @read_byte: [REPLACEABLE] read one byte from the chip
  * @read_word: [REPLACEABLE] read one word from the chip
  * @write_byte:[REPLACEABLE] write a single byte to the chip 
on the
@@ -689,6 +690,8 @@ struct nand_chip {
void __iomem *IO_ADDR_R;
void __iomem *IO_ADDR_W;
 
+   int flash_node;
+
uint8_t (*read_byte)(struct mtd_info *mtd);
u16 (*read_word)(struct mtd_info *mtd);
void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
-- 
2.7.4

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[U-Boot] [PATCH v2 4/6] sun5i: Add NAND controller to the sun5i DTSI

[Boris Brezillon]

From: Maxime Ripard 

Add the NAND controller definition to sun5i.dtsi.

Signed-off-by: Maxime Ripard 
Signed-off-by: Boris Brezillon 
---
 arch/arm/dts/sun5i.dtsi | 49 +
 1 file changed, 49 insertions(+)

diff --git a/arch/arm/dts/sun5i.dtsi b/arch/arm/dts/sun5i.dtsi
index 59a9426..87e5353 100644
--- a/arch/arm/dts/sun5i.dtsi
+++ b/arch/arm/dts/sun5i.dtsi
@@ -356,6 +356,17 @@
#dma-cells = <2>;
};
 
+   nfc: nand@01c03000 {
+   compatible = "allwinner,sun4i-a10-nand";
+   reg = <0x01c03000 0x1000>;
+   interrupts = <37>;
+   clocks = <_gates 13>, <_clk>;
+   clock-names = "ahb", "mod";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
spi0: spi@01c05000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c05000 0x1000>;
@@ -548,6 +559,44 @@
allwinner,pull = ;
};
 
+   nand_pins_a: nand_base0@0 {
+   allwinner,pins = "PC0", "PC1", "PC2",
+   "PC5", "PC8", "PC9", "PC10",
+   "PC11", "PC12", "PC13", "PC14",
+   "PC15";
+   allwinner,function = "nand0";
+   allwinner,drive = <0>;
+   allwinner,pull = <0>;
+   };
+
+   nand_cs0_pins_a: nand_cs@0 {
+   allwinner,pins = "PC4";
+   allwinner,function = "nand0";
+   allwinner,drive = <0>;
+   allwinner,pull = <0>;
+   };
+
+   nand_cs1_pins_a: nand_cs@1 {
+   allwinner,pins = "PC3";
+   allwinner,function = "nand0";
+   allwinner,drive = <0>;
+   allwinner,pull = <0>;
+   };
+
+   nand_rb0_pins_a: nand_rb@0 {
+   allwinner,pins = "PC6";
+   allwinner,function = "nand0";
+   allwinner,drive = <0>;
+   allwinner,pull = <0>;
+   };
+
+   nand_rb1_pins_a: nand_rb@1 {
+   allwinner,pins = "PC7";
+   allwinner,function = "nand0";
+   allwinner,drive = <0>;
+   allwinner,pull = <0>;
+   };
+
uart3_pins_a: uart3@0 {
allwinner,pins = "PG9", "PG10";
allwinner,function = "uart3";
-- 
2.7.4

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[U-Boot] [PATCH v2 0/6] sunxi: Add NAND controller driver

[Boris Brezillon]

Hello,

This patch series is adding the normal sunxi NAND controller driver to
u-boot.

It's based on the Linux driver, with a few adaptions to make it work
in Linux.

It's based on Scott's series syncing the MTD/NAND frameworks with
Linux 4.6 [1].

Best Regards,

Boris

[1]https://patchwork.ozlabs.org/patch/627928/

Changes since v1:
- moved the sunxi_nand_init() prototype definition into include/nand.h
- added Hans Acked-by tags

Boris Brezillon (4):
  sunxi: Add missing macros to configure the NAND controller clk
  mtd: nand: Add the sunxi NAND controller driver
  mtd: nand: Add a full-id entry for the H27QCG8T2E5R‐BCF NAND
  sunxi: Enable NAND controller on the CHIP

Brian Norris (1):
  mtd: nand: add common DT init code

Maxime Ripard (1):
  sun5i: Add NAND controller to the sun5i DTSI

 arch/arm/dts/sun5i-a10s.dtsi  |   14 +
 arch/arm/dts/sun5i-a13-olinuxino.dts  |   15 +
 arch/arm/dts/sun5i-r8-chip.dts|   15 +
 arch/arm/dts/sun5i.dtsi   |   49 +
 arch/arm/include/asm/arch-sunxi/clock_sun4i.h |5 +
 board/sunxi/board.c   |5 +-
 drivers/mtd/nand/Kconfig  |8 +-
 drivers/mtd/nand/Makefile |1 +
 drivers/mtd/nand/nand_base.c  |   70 +
 drivers/mtd/nand/nand_ids.c   |4 +
 drivers/mtd/nand/sunxi_nand.c | 1845 +
 include/configs/sunxi-common.h|2 +
 include/fdtdec.h  |1 +
 include/linux/mtd/nand.h  |3 +
 include/nand.h|3 +
 lib/fdtdec.c  |1 +
 16 files changed, 2037 insertions(+), 4 deletions(-)
 create mode 100644 drivers/mtd/nand/sunxi_nand.c

-- 
2.7.4

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[U-Boot] [PATCH v2 3/6] mtd: nand: Add the sunxi NAND controller driver

[Boris Brezillon]

We already have an SPL driver for the sunxi NAND controller, now add
the normal/standard one.

The source has been copied from Linux 4.6 with a few changes to make
it work in u-boot.

Signed-off-by: Boris Brezillon 
Acked-by: Hans de Goede 
---
 board/sunxi/board.c|5 +-
 drivers/mtd/nand/Kconfig   |8 +-
 drivers/mtd/nand/Makefile  |1 +
 drivers/mtd/nand/sunxi_nand.c  | 1845 
 include/configs/sunxi-common.h |2 +
 include/fdtdec.h   |1 +
 include/nand.h |3 +
 lib/fdtdec.c   |1 +
 8 files changed, 1862 insertions(+), 4 deletions(-)
 create mode 100644 drivers/mtd/nand/sunxi_nand.c

diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 3cf3614..a0f4334 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -142,7 +142,7 @@ void dram_init_banksize(void)
 }
 #endif
 
-#if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_NAND_SUNXI)
 static void nand_pinmux_setup(void)
 {
unsigned int pin;
@@ -179,6 +179,9 @@ void board_nand_init(void)
 {
nand_pinmux_setup();
nand_clock_setup();
+#ifndef CONFIG_SPL_BUILD
+   sunxi_nand_init();
+#endif
 }
 #endif
 
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 8c46a2f..5ce7d6d 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -64,12 +64,14 @@ config NAND_PXA3XX
  PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
 
 config NAND_SUNXI
-   bool "Support for NAND on Allwinner SoCs in SPL"
+   bool "Support for NAND on Allwinner SoCs"
depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
select SYS_NAND_SELF_INIT
---help---
-   Enable support for NAND. This option allows SPL to read from
-   sunxi NAND using DMA transfers.
+   Enable support for NAND. This option enables the standard and
+   SPL drivers.
+   The SPL driver only supports reading from the NAND using DMA
+   transfers.
 
 config NAND_ARASAN
bool "Configure Arasan Nand"
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 837d397..1df9273 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -66,6 +66,7 @@ obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o
 obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
 obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o
 obj-$(CONFIG_NAND_PLAT) += nand_plat.o
+obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o
 
 else  # minimal SPL drivers
 
diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c
new file mode 100644
index 000..c4e2cd7
--- /dev/null
+++ b/drivers/mtd/nand/sunxi_nand.c
@@ -0,0 +1,1845 @@
+/*
+ * Copyright (C) 2013 Boris BREZILLON 
+ * Copyright (C) 2015 Roy Spliet 
+ *
+ * Derived from:
+ * https://github.com/yuq/sunxi-nfc-mtd
+ * Copyright (C) 2013 Qiang Yu 
+ *
+ * https://github.com/hno/Allwinner-Info
+ * Copyright (C) 2013 Henrik Nordström 
+ *
+ * Copyright (C) 2013 Dmitriy B. 
+ * Copyright (C) 2013 Sergey Lapin 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define NFC_REG_CTL0x
+#define NFC_REG_ST 0x0004
+#define NFC_REG_INT0x0008
+#define NFC_REG_TIMING_CTL 0x000C
+#define NFC_REG_TIMING_CFG 0x0010
+#define NFC_REG_ADDR_LOW   0x0014
+#define NFC_REG_ADDR_HIGH  0x0018
+#define NFC_REG_SECTOR_NUM 0x001C
+#define NFC_REG_CNT0x0020
+#define NFC_REG_CMD0x0024
+#define NFC_REG_RCMD_SET   0x0028
+#define NFC_REG_WCMD_SET   0x002C
+#define NFC_REG_IO_DATA0x0030
+#define NFC_REG_ECC_CTL0x0034
+#define NFC_REG_ECC_ST 0x0038
+#define NFC_REG_DEBUG  0x003C
+#define NFC_REG_ECC_ERR_CNT(x) ((0x0040 + (x)) & ~0x3)
+#define NFC_REG_USER_DATA(x)   (0x0050 + ((x) * 4))
+#define NFC_REG_SPARE_AREA 0x00A0
+#define NFC_REG_PAT_ID 0x00A4
+#define NFC_RAM0_BASE  0x0400
+#define NFC_RAM1_BASE  0x0800
+
+/* define bit use in NFC_CTL */
+#define NFC_EN BIT(0)
+#define NFC_RESET  BIT(1)
+#define 

[U-Boot] [PATCH v2 6/6] sunxi: Enable NAND controller on the CHIP

[Boris Brezillon]

Enable the NAND controller in the sun5i-r8-chip.dts.

Signed-off-by: Boris Brezillon 
Acked-by: Hans de Goede 
---
 arch/arm/dts/sun5i-a10s.dtsi | 14 ++
 arch/arm/dts/sun5i-a13-olinuxino.dts | 15 +++
 arch/arm/dts/sun5i-r8-chip.dts   | 15 +++
 3 files changed, 44 insertions(+)

diff --git a/arch/arm/dts/sun5i-a10s.dtsi b/arch/arm/dts/sun5i-a10s.dtsi
index bddd0de..a5f8855 100644
--- a/arch/arm/dts/sun5i-a10s.dtsi
+++ b/arch/arm/dts/sun5i-a10s.dtsi
@@ -241,6 +241,20 @@
allwinner,drive = ;
allwinner,pull = ;
};
+
+   nand_cs2_pins_a: nand_cs@2 {
+   allwinner,pins = "PC17";
+   allwinner,function = "nand0";
+   allwinner,drive = <0>;
+   allwinner,pull = <0>;
+   };
+
+   nand_cs3_pins_a: nand_cs@3 {
+   allwinner,pins = "PC18";
+   allwinner,function = "nand0";
+   allwinner,drive = <0>;
+   allwinner,pull = <0>;
+   };
 };
 
 _a {
diff --git a/arch/arm/dts/sun5i-a13-olinuxino.dts 
b/arch/arm/dts/sun5i-a13-olinuxino.dts
index b3c234c..30e069a 100644
--- a/arch/arm/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/dts/sun5i-a13-olinuxino.dts
@@ -155,6 +155,21 @@
status = "okay";
 };
 
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a _cs0_pins_a _rb0_pins_a>;
+   status = "okay";
+
+   nand@0 {
+   #address-cells = <2>;
+   #size-cells = <2>;
+   reg = <0>;
+   allwinner,rb = <0>;
+   nand-ecc-mode = "hw";
+   allwinner,randomize;
+   };
+};
+
  {
status = "okay";
 };
diff --git a/arch/arm/dts/sun5i-r8-chip.dts b/arch/arm/dts/sun5i-r8-chip.dts
index 6ad19e2..b1b62d5 100644
--- a/arch/arm/dts/sun5i-r8-chip.dts
+++ b/arch/arm/dts/sun5i-r8-chip.dts
@@ -142,6 +142,21 @@
status = "okay";
 };
 
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a _cs0_pins_a _rb0_pins_a>;
+   status = "okay";
+
+   nand@0 {
+   #address-cells = <2>;
+   #size-cells = <2>;
+   reg = <0>;
+   allwinner,rb = <0>;
+   nand-ecc-mode = "hw";
+   nand-on-flash-bbt;
+   };
+};
+
  {
status = "okay";
 };
-- 
2.7.4

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[U-Boot] [PATCH v2 1/6] sunxi: Add missing macros to configure the NAND controller clk

[Boris Brezillon]

We need some macros to manipulate the NAND controller clock.

Signed-off-by: Boris Brezillon 
Acked-by: Hans de Goede 
---
 arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h 
b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index 0088bb9..d1c5ad0 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -269,6 +269,11 @@ struct sunxi_ccm_reg {
 #define CCM_MBUS_CTRL_CLK_SRC_PLL5 0x2
 #define CCM_MBUS_CTRL_GATE (0x1 << 31)
 
+#define CCM_NAND_CTRL_M(x) ((x) - 1)
+#define CCM_NAND_CTRL_N(x) ((x) << 16)
+#define CCM_NAND_CTRL_OSCM24   (0x0 << 24)
+#define CCM_NAND_CTRL_PLL6 (0x1 << 24)
+#define CCM_NAND_CTRL_PLL5 (0x2 << 24)
 #define CCM_NAND_CTRL_ENABLE   (0x1 << 31)
 
 #define CCM_MMC_CTRL_M(x)  ((x) - 1)
-- 
2.7.4

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[U-Boot] [PATCH v2 5/6] mtd: nand: Add a full-id entry for the H27QCG8T2E5R‐BCF NAND

[Boris Brezillon]

Add a full-id entry for the H27QCG8T2E5R‐BCF NAND.

Signed-off-by: Boris Brezillon 
Acked-by: Hans de Goede 
---
 drivers/mtd/nand/nand_ids.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index 561d2cd..ce0a14e 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -62,6 +62,10 @@ struct nand_flash_dev nand_flash_ids[] = {
{ .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} },
  SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
  NAND_ECC_INFO(40, SZ_1K), 4 },
+   {"H27QCG8T2E5R‐BCF 64G 3.3V 8-bit",
+   { .id = {0xad, 0xde, 0x14, 0xa7, 0x42, 0x4a} },
+ SZ_16K, SZ_8K, SZ_4M, NAND_NEED_SCRAMBLING, 6, 1664,
+ NAND_ECC_INFO(56, SZ_1K), 1 },
 
LEGACY_ID_NAND("NAND 4MiB 5V 8-bit",   0x6B, 4, SZ_8K, SP_OPTIONS),
LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
-- 
2.7.4

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[U-Boot] [PATCH] common: cli_readline: Improve command line editing

[James Byrne]

This improves the cread_line() function so that it will correctly
process the 'Home', 'End', 'Delete' and arrow key escape sequences
produced by various terminal emulators. This makes command line editing
a more pleasant experience.

The previous code only supported the cursor keys and the 'Home' key, and
only for certain terminal emulator configurations. This adds support for
the 'End and 'Delete' keys, and recognises a wider range of escape
sequences. For example, the left arrow key can be 'ESC O D' instead of
'ESC [ D', and the 'Home' key can be 'ESC [ H', 'ESC O H', 'ESC 1 ~' or
'ESC 7 ~', depending on what terminal emulator you use and how it is
configured.

Signed-off-by: James Byrne 
---

 common/cli_readline.c | 108 --
 1 file changed, 78 insertions(+), 30 deletions(-)

diff --git a/common/cli_readline.c b/common/cli_readline.c
index c1476e4..0d4ad49 100644
--- a/common/cli_readline.c
+++ b/common/cli_readline.c
@@ -283,46 +283,94 @@ static int cread_line(const char *const prompt, char 
*buf, unsigned int *len,
 * handle standard linux xterm esc sequences for arrow key, etc.
 */
if (esc_len != 0) {
+   enum { ESC_REJECT, ESC_SAVE, ESC_CONVERTED } act;
+
if (esc_len == 1) {
-   if (ichar == '[') {
-   esc_save[esc_len] = ichar;
-   esc_len = 2;
+   if (ichar == '[' || ichar == 'O')
+   act = ESC_SAVE;
+   else
+   act = ESC_REJECT;
+   } else if (esc_len == 2) {
+   switch (ichar) {
+   case 'D':   /* <- key */
+   ichar = CTL_CH('b');
+   act = ESC_CONVERTED;
+   break;  /* pass off to ^B handler */
+   case 'C':   /* -> key */
+   ichar = CTL_CH('f');
+   act = ESC_CONVERTED;
+   break;  /* pass off to ^F handler */
+   case 'H':   /* Home key */
+   ichar = CTL_CH('a');
+   act = ESC_CONVERTED;
+   break;  /* pass off to ^A handler */
+   case 'F':   /* End key */
+   ichar = CTL_CH('e');
+   act = ESC_CONVERTED;
+   break;  /* pass off to ^E handler */
+   case 'A':   /* up arrow */
+   ichar = CTL_CH('p');
+   act = ESC_CONVERTED;
+   break;  /* pass off to ^P handler */
+   case 'B':   /* down arrow */
+   ichar = CTL_CH('n');
+   act = ESC_CONVERTED;
+   break;  /* pass off to ^N handler */
+   case '1':
+   case '3':
+   case '4':
+   case '7':
+   case '8':
+   if (esc_save[1] == '[') {
+   /* see if next character is ~ */
+   act = ESC_SAVE;
+   } else {
+   act = ESC_REJECT;
+   }
+   break;
+   default:
+   act = ESC_REJECT;
+   break;
+   }
+   } else if (esc_len == 3) {
+   if (ichar == '~') {
+   switch (esc_save[2]) {
+   case '3':   /* Delete key */
+   ichar = CTL_CH('d');
+   act = ESC_CONVERTED;
+   break;  /* pass to ^D handler */
+   case '1':   /* Home key */
+   case '7':
+   ichar = CTL_CH('a');
+   act = ESC_CONVERTED;
+   

Re: [U-Boot] u-boot on Minnowboard max

[vinoth eswaran]

Hello Mr.Bin,

 May I know what is the issue , if you could explain I can fix
this in my target and could provide the patch. I am stuck up with this
issue and couldn't able to proceed further.

 Thanks a lot:)


Mit Freundlichen Grüßen
VinothKumar
+49 1798909072


On Wed, Jun 8, 2016 at 7:00 AM, Bin Meng  wrote:
> Hi,
>
> On Tue, Jun 7, 2016 at 7:40 PM, vinoth eswaran  wrote:
>> Hello Mr.BIn,
>>
>>  I tested using the latest u-boot (u-boot-2016.07-rc1) with
>> CONFIG_GENERATE_ACPI_TABLE=y enabled. I am still facing the same
>> issue, the Linux kernel is not able to initialize the root file system
>> from the sd card. I have attached the logs for your reference.
>>
>> My Analysis:
>> [1.267312] sdhci-pci :00:12.0: failed to setup card detect
>> gpio -- this error message I am seeing with UEFI firmware also. So I
>> am assuming it is not the issue here.
>>
>> I have done some debugging of MMC initialisation and found that in
>> mmc_rescan function (drivers/mmc/core/core.c)
>>
>> host->ops->get_cd(host) returns 0
>>
>> and the condition is failed. So MMC is not getting intialized.  i
>> checked the return of
>>
>>  !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); and
>> here I am seeing that
>>
>> with U-boot version it is 1FA and bit AND with 0x0001 is zero
>> (condition fails)
>> with UEFI version it is 1FF and bit AND with 0x0001 is one
>> (condition succeeded)
>>
>>
>> Do you have any idea why this is happening, any input from your side
>> will help me
>>
>
> Issue identified. Working on a fix. Stay tuned.
>
>> Thanks a lot:)
>>
>>
>> Mit Freundlichen Grüßen
>> VinothKumar
>> +49 1798909072
>>
>
> Please stop top-posting. Thanks!
>
> Regards,
> Bin
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[U-Boot] [PATCH] ti_armv7_common: env: Remove no longer needed mem_reserve

[Andrew F. Davis]

The kernel can now use DT to reserve memory carveouts and
these areas are now the default for drivers that need reserved
memory, so reserving more here is unneeded and any memory reserved
this way will be wasted.

Signed-off-by: Andrew F. Davis 
---
 include/configs/ti_armv7_keystone2.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/include/configs/ti_armv7_keystone2.h 
b/include/configs/ti_armv7_keystone2.h
index 2c9028c..d7baf33 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -247,7 +247,6 @@
"tftp_root=/\0" \
"nfs_root=/export\0"\
"mem_lpae=1\0"  \
-   "mem_reserve=512M\0"\
"addr_ubi=0x8200\0" \
"addr_secdb_key=0xc00\0"\
"name_kern=zImage\0"\
-- 
2.8.3

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Re: [U-Boot] [PATCH 1/3] drivers: usb: fsl: add USB ULPI init code

[Marek Vasut]

On 06/08/2016 10:22 AM, Rajesh Bhagat wrote:
> This adds the required code to set up a ULPI USB port, for
> new NXP USB PHY used in QorIQ platforms.
> 
> To use this both CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT
> have to be set in the board configuration file.
> 
> Signed-off-by: Rajesh Bhagat 
> ---
>  drivers/usb/host/ehci-fsl.c |   21 +
>  1 files changed, 21 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
> index a43d37d..897f453 100644
> --- a/drivers/usb/host/ehci-fsl.c
> +++ b/drivers/usb/host/ehci-fsl.c
> @@ -16,6 +16,9 @@
>  #include 
>  #include 
>  #include 
> +#ifdef CONFIG_USB_ULPI
> +#include 
> +#endif
>  
>  #include "ehci.h"
>  
> @@ -50,6 +53,10 @@ int ehci_hcd_init(int index, enum usb_init_type init,
>   const char *phy_type = NULL;
>   size_t len;
>   char current_usb_controller[5];
> +#ifdef CONFIG_USB_ULPI
> + int ret;
> + struct ulpi_viewport ulpi_vp;
> +#endif
>  #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
>   char usb_phy[5];
>  
> @@ -126,6 +133,20 @@ int ehci_hcd_init(int index, enum usb_init_type init,
>   udelay(1000); /* delay required for PHY Clk to appear */
>   if (!usb_phy_clk_valid(ehci))
>   return -EINVAL;
> +
> +#ifdef CONFIG_USB_ULPI
> + ulpi_vp.viewport_addr = (u32)>ulpi_viewpoint;
> + ulpi_vp.port_num = 0;
> +
> + ret = ulpi_init(_vp);
> + if (ret) {
> + puts("NXP ULPI viewport init failed\n");
> + return -1;

return ret;

> + }
> +
> + ulpi_set_vbus(_vp, 1, 1);
> + ulpi_set_vbus_indicator(_vp, 1, 1, 1);
> +#endif
>   out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
>   }
>  
> 


-- 
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Re: [U-Boot] [PATCH v2 1/5] arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper

[Marek Vasut]

On 06/08/2016 06:12 AM, Sriram Dash wrote:
>> -Original Message-
>> From: Marek Vasut [mailto:ma...@denx.de]
>> Sent: Monday, June 06, 2016 6:21 PM
>> To: Sriram Dash ; u-boot@lists.denx.de
>> Cc: york sun ; albert.u.b...@aribaud.net; Rajesh Bhagat
>> 
>> Subject: Re: [PATCH v2 1/5] arm64: fsl-layerscape: add get_svr and IS_SVR_REV
>> helper
>>
>> On 06/06/2016 06:21 AM, Sriram Dash wrote:
 -Original Message-
 From: Marek Vasut [mailto:ma...@denx.de]
 Sent: Thursday, June 02, 2016 6:18 PM
 To: Sriram Dash ; u-boot@lists.denx.de
 Cc: york sun ; albert.u.b...@aribaud.net; Rajesh
 Bhagat 
 Subject: Re: [PATCH v2 1/5] arm64: fsl-layerscape: add get_svr and
 IS_SVR_REV helper

 On 06/02/2016 08:54 AM, Sriram Dash wrote:
> Signed-off-by: Sriram Dash 
> Signed-off-by: Rajesh Bhagat 
> ---
> Changes in v2:
>   - No update
>
>  arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 7 +++
>  arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 ++
> arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 3 +++
>  arch/arm/include/asm/arch-fsl-layerscape/soc.h | 2 ++
>  4 files changed, 14 insertions(+)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> index 9a5a6b5..9c575c1 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> @@ -528,6 +528,13 @@ u32 fsl_qoriq_core_to_type(unsigned int core)
>   return -1;  /* cannot identify the cluster */
>  }
>
> +uint get_svr(void)

 Should be u32 . The function should have some more recognizable name,
 fsl_get_svr() or such.

>>>
>>> Hello Marek,
>>>
>>> As done in PPC for all the Socs for FSL, in 
>>> arch/powerpc/cpu/mpc83xx/start.S ,
>> and ARM v7 LS1021, in arch/arm/cpu/armv7/ls102xa/cpu.c, this uint 
>> get_svr(void)
>> function finds the svr number for the SoC. Now, as i have to make the code 
>> generic
>> for PPC and ARM (in patch 3/5 namely make errata function common for PPC and
>> ARM), I am currently having the same name and return type used.
>>
>> You can rename it now.
>>
> 
> Somewhat I agree to the point. It is good to have u32 instead of 
> uint and the get_svr() function should have some more recognizable
> name. But, this function is already being used in many files and this
> would require for some uncalled 120 + changes for PPC and ARM v7,
> which is not in the scope of this patchset.
> Currently, I am focusing on the errata implementation, which I want
> to make generic, by having the same names across PPC, ARMv7 and
> ARMv8. So, I am planning to do this change at a later point of time.

I really dislike such function names, but OK, it's manged to spread
through the codebase too much.


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Re: [U-Boot] [PATCH v3] common: usb_storage : Implement logic to calculate optimal usb maximum trasfer blocks

[Marek Vasut]

On 06/08/2016 06:09 AM, Rajesh Bhagat wrote:
> 
> 
>> -Original Message-
>> From: Marek Vasut [mailto:ma...@denx.de]
>> Sent: Wednesday, June 08, 2016 8:38 AM
>> To: Rajesh Bhagat ; u-boot@lists.denx.de
>> Cc: s...@chromium.org; york sun ; Sriram Dash
>> 
>> Subject: Re: [PATCH v3] common: usb_storage : Implement logic to calculate 
>> optimal
>> usb maximum trasfer blocks
>>
>> On 06/07/2016 11:29 AM, Rajesh Bhagat wrote:
>>> Implements the logic to calculate the optimal usb maximum trasfer
>>> blocks instead of sending USB_MAX_XFER_BLK blocks which is 65535 and
>>> 20 in case of EHCI and other USB protocols respectively.
>>>
>>> It defines USB_MIN_XFER_BLK/USB_MAX_XFER_BLK trasfer blocks that
>>> should be checked for success starting from minimum to maximum, and
>>> rest of the read/write are performed with that optimal value. It tries
>>> to increase/ decrease the blocks in follwing scenarios:
>>>
>>> 1.decrease blocks: when read/write for a particular number of blocks
>>> fails.
>>> 2. increase blocks: when read/write for a particular number of blocks
>>> pass and amount left to trasfer is greater than current number of
>>> blocks.
>>>
>>> Currently changes are done for EHCI where min = 4096 and max = 65535
>>> is taken. And for other cases code is left unchanged by keeping min =
>>> max = 20.
>>>
>>> Signed-off-by: Sriram Dash 
>>> Signed-off-by: Rajesh Bhagat 
>>> ---
>>> Changes in v3:
>>>  - Adds cur_xfer_blks in struct usb_device to retain values
>>>  - Adds functions dec/inc_cur_xfer_blks to remove code duplication
>>>  - Moves check from macro to calling functions
>>>
>>> Changes in v2:
>>>  - Removes table to store blocks and use formula (1 << (12 + n)) - 1
>>>  - Adds logic to start from minimum, go to maximum in each read/write
>>>
>>>  common/usb_storage.c | 78
>> 
>>>  include/usb.h|  1 +
>>>  2 files changed, 67 insertions(+), 12 deletions(-)
>>>
>>> diff --git a/common/usb_storage.c b/common/usb_storage.c index
>>> 7e6e52d..e08dcd4 100644
>>> --- a/common/usb_storage.c
>>> +++ b/common/usb_storage.c
>>> @@ -106,11 +106,40 @@ struct us_data {
>>>   * enough free heap space left, but the SCSI READ(10) and WRITE(10) 
>>> commands
>> are
>>>   * limited to 65535 blocks.
>>>   */
>>> +#define USB_MIN_XFER_BLK   4095
>>>  #define USB_MAX_XFER_BLK   65535
>>>  #else
>>> +#define USB_MIN_XFER_BLK   20
>>>  #define USB_MAX_XFER_BLK   20
>>>  #endif
>>>
>>> +#define GET_CUR_XFER_BLKS(blks)(LOG2(blks / (USB_MIN_XFER_BLK +
>> 1)))
>>> +#define CALC_CUR_XFER_BLKS(pos)((1 << (12 + pos)) - 1)
>>> +
>>> +static int dec_cur_xfer_blks(int *pos, unsigned short *smallblks) {
>>> +   /* decrease the cur_xfer_blks */
>>> +   unsigned short size = (*pos > 0) ? CALC_CUR_XFER_BLKS(*pos - 1) : 0;
>>
> 
> Hello Marek, 
> 
>> If someone passes null pointer into the function, it will fail.
>> Also, you can refactor it to make it more readable:
>>
>> if (!pos)
>>  return -EINVAL;
>> if (size < USB_MIN_XFER_BLK)
>>  return -EINVAL;
>> ... do stuff ...
>>
> 
> Refactoring the code to return early in case of error conditions is fine. But 
> pos and smallblks can never be passed as NULL in these functions. 

... until an idiot comes around and does it.

>> I still don't understand why $pos isn't unsigned int, it should be.
>>
> 
> I believe keeping a variable as "int" provides a natural way of checking for 
> overflow conditions. We check can check if number has become negative and 
> take 
> actions, which is not possible when number is taken as "unsigned int".

But the number here can never be negative, can it ?

>>> +   if (size >= USB_MIN_XFER_BLK) {
>>> +   *smallblks = size;
>>> +   (*pos)--;
>>> +   return 0;
>>> +   }
>>> +   return -EINVAL;
>>> +}
>>> +
>>> +static int inc_cur_xfer_blks(int *pos, unsigned short *smallblks,
>>> +lbaint_t blks) {
>>> +   /* try to increase the cur_xfer_blks */
>>> +   unsigned short size = (*pos >= 0) ? CALC_CUR_XFER_BLKS(*pos + 1) : 0;
>>> +   if (size <= blks && size <= USB_MAX_XFER_BLK) {
>>> +   *smallblks = size;
>>> +   (*pos)++;
>>> +   return 0;
>>> +   }
>>> +   return -EINVAL;
>>> +}
>>> +
>>>  #ifndef CONFIG_BLK
>>>  static struct us_data usb_stor[USB_MAX_STOR_DEV];  #endif @@ -1117,7
>>> +1146,8 @@ static unsigned long usb_stor_read(struct blk_desc *block_dev,
>> lbaint_t blknr,
>>> unsigned short smallblks;
>>> struct usb_device *udev;
>>> struct us_data *ss;
>>> -   int retry;
>>> +   int retry, pos;
>>> +   bool retry_flag = false;
>>> ccb *srb = _ccb;
>>>  #ifdef CONFIG_BLK
>>> struct blk_desc *block_dev;
>>> @@ -1145,6 +1175,7 @@ static unsigned long usb_stor_read(struct blk_desc
>> *block_dev, lbaint_t blknr,
>>> buf_addr = (uintptr_t)buffer;
>>> start = blknr;
>>> blks = blkcnt;
>>> +   pos = 

Re: [U-Boot] [PATCH v2 2/4] usb: dwc3: Add helper functions to enable snooping and burst settings

[Marek Vasut]

On 06/08/2016 11:44 AM, Rajesh Bhagat wrote:
> 
> 
>> -Original Message-
>> From: Marek Vasut [mailto:ma...@denx.de]
>> Sent: Monday, June 06, 2016 6:24 PM
>> To: Rajat Srivastava ; u-boot@lists.denx.de
>> Cc: l.majew...@samsung.com; s...@chromium.org; albert.u.b...@aribaud.net;
>> prabha...@freescale.com; york sun ; Mingkai Hu
>> ; Rajesh Bhagat ;
>> michal.si...@xilinx.com; felipe.ba...@linux.intel.com
>> Subject: Re: [PATCH v2 2/4] usb: dwc3: Add helper functions to enable 
>> snooping and
>> burst settings
>>
>> On 06/06/2016 11:16 AM, Rajat Srivastava wrote:
>>> Adds helper functions to enable snooping and outstanding burst beat
>>> settings.
>>>
>>> Signed-off-by: Rajat Srivastava 
>>> Signed-off-by: Rajesh Bhagat 
>>> ---
>>> Changes in v2:
>>>  - Removes SoC specific flags and added helper functions
>>>
>>>  drivers/usb/dwc3/core.c | 45
>>> +
>>>  drivers/usb/dwc3/core.h |  7 +++
>>>  2 files changed, 52 insertions(+)
>>>
>>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index
>>> 85cc96a..0b3c596 100644
>>> --- a/drivers/usb/dwc3/core.c
>>> +++ b/drivers/usb/dwc3/core.c
>>> @@ -599,6 +599,51 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc)
>>>
>>>  #define DWC3_ALIGN_MASK(16 - 1)
>>>
>>> +void dwc3_core_incr_burst_enable(int index, int btype_incr_val,
>>> +int breq_limit)
>>> +{
>>> +   struct dwc3 *dwc;
>>> +   u32 reg;
>>> +
>>> +   list_for_each_entry(dwc, _list, list) {
>>
> 
> Hello Marek, 
> 
>> Why is this iterating over a list of all controllers ?
> 
> This function has to be called from Soc specific code to pass some register 
> settings. And dwc pointer 
> would not be available there. Hence, index is passed to determine dwc 
> pointer. 
> 
>> Should this be enabled on per-controller basis by some DT prop ?
>>
> 
> We are using dwc3 driver with non DT support. 

That's real unfortunate.

> Best Regards,
> Rajesh Bhagat 
> 
>  
>>> +   if (dwc->index != index)
>>> +   continue;
>>> +
>>> +   /*
>>> +* Change burst beat and outstanding pipelined
>>> +* transfers requests
>>> +*/
>>> +   reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
>>> +   reg = (reg & ~DWC3_INCR_BTYPE_MASK) | btype_incr_val;
>>> +   dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
>>> +
>>> +   reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG1);
>>> +   reg = (reg & ~DWC3_BREQ_LIMIT_MASK) | (breq_limit << 8);
>>> +   dwc3_writel(dwc->regs, DWC3_GSBUSCFG1, reg);
>>> +   break;
>>> +   }
>>> +}
>>> +
>>> +void dwc3_core_set_snooping(int index, bool snoop) {
>>> +   struct dwc3 *dwc;
>>> +   u32 reg;
>>> +
>>> +   list_for_each_entry(dwc, _list, list) {
>>> +   if (dwc->index != index)
>>> +   continue;
>>> +
>>> +   /* Enable/Disable snooping */
>>> +   reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
>>> +   if (snoop)
>>> +   reg = reg | DWC3_SNOOP_ENABLE;
>>> +   else
>>> +   reg = reg & ~DWC3_SNOOP_ENABLE;
>>> +   dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
>>> +   break;
>>> +   }
>>> +}
>>> +
>>>  /**
>>>   * dwc3_uboot_init - dwc3 core uboot initialization code
>>>   * @dwc3_dev: struct dwc3_device containing initialization data diff
>>> --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index
>>> 72d2fcd..455e7fa 100644
>>> --- a/drivers/usb/dwc3/core.h
>>> +++ b/drivers/usb/dwc3/core.h
>>> @@ -593,6 +593,13 @@ struct dwc3_hwparams {
>>>  /* HWPARAMS7 */
>>>  #define DWC3_RAM1_DEPTH(n) ((n) & 0x)
>>>
>>> +/* GSBUSCFG0 */
>>> +#define DWC3_SNOOP_ENABLE  (0x)
>>> +#define DWC3_INCR_BTYPE_MASK   (0xff)
>>> +
>>> +/* GSBUSCFG1 */
>>> +#define DWC3_BREQ_LIMIT_MASK   (0xf00)
>>> +
>>>  struct dwc3_request {
>>> struct usb_request  request;
>>> struct list_headlist;
>>>
>>
>>
>> --
>> Best regards,
>> Marek Vasut


-- 
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Re: [U-Boot] [RFC][PATCH] arm: rk: Drop SYS_MALLOC_F and SPL_SYS_MALLOC_SIMPLE

[Marek Vasut]

On 06/08/2016 06:44 AM, Simon Glass wrote:
> Hi Marek,
> 
> On 7 June 2016 at 20:02, Marek Vasut  wrote:
>> On 06/08/2016 04:43 AM, Simon Glass wrote:
>>> Hi Marek,
>>
>> Hi!
>>
>>> On 25 May 2016 at 05:26, Marek Vasut  wrote:
 On 05/25/2016 05:29 AM, Simon Glass wrote:
> Hi Marek,
>
> On 24 May 2016 at 18:15, Marek Vasut  wrote:
>> Both SYS_MALLOC_F and SPL_SYS_MALLOC_SIMPLE are generic config options,
>> drop them from the rockchip-specific Kconfig file.
>>
>> Signed-off-by: Marek Vasut 
>> Cc: Tom Rini 
>> Cc: Simon Glass 
>> ---
>>  arch/arm/mach-rockchip/Kconfig | 6 --
>>  1 file changed, 6 deletions(-)
>>
>> diff --git a/arch/arm/mach-rockchip/Kconfig 
>> b/arch/arm/mach-rockchip/Kconfig
>> index d3bddb7..5f6046a 100644
>> --- a/arch/arm/mach-rockchip/Kconfig
>> +++ b/arch/arm/mach-rockchip/Kconfig
>> @@ -17,12 +17,6 @@ config ROCKCHIP_RK3036
>>   and video codec support. Peripherals include Gigabit Ethernet,
>>   USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
>>
>> -config SYS_MALLOC_F
>> -   default y
>> -
>> -config SPL_SYS_MALLOC_SIMPLE
>> -   default y
>> -
>>  config SPL_DM
>> default y
>>
>> --
>> 2.7.0
>>
>
> Will these still be enabled some other way?

 That's why it's RFC, I believe the rockchip platforms would need to add
 those to their defconfig, right ?
>>>
>>> Well, Rockchip boards cannot work without these, which is why they default 
>>> to y.
>>
>> I understand that, but these Kconfig options are generic, so they
>> shouldn't be defined in the mach-rockchip/Kconfig file, but in some
>> generic Kconfig file and then selected by ARCH_ROCKCHIP symbol or in
>> some defconfig , right ?
> 
> They are not being defined, just their default value is being set.

Checking with git grep, they are defined in the top-level Kconfig.
I recall when I tried using those on mips, it complained about the
entries in mach-rockchip though. So why are the defaults selected
this way instead of using "select" in ARCH_ROCKCHIP symbol ? Isn't
that how it's usually done ?

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Re: [U-Boot] [PATCH v2] Make FIT support really optional

[Tom Rini]

On Wed, Jun 08, 2016 at 07:47:12AM +0200, Thomas Petazzoni wrote:
> Hello,
> 
> On Tue, 7 Jun 2016 21:18:17 -0300 (BRT), Carlos Santos wrote:
> 
> > There is already a configuration that makes FIT optional (CONFIG_FIT)
> > but it is partially broken because it does not really remove
> > FIT-related functionality from mkimage. That's the reason why it was
> > not possible to disable FIT in the Buildroot package. My patch aims
> > to fix that defect.
> 
> Ah, indeed, I forgot that the CONFIG_FIT option already existed. In
> this case, I agree that it should either exist and work, or not exist.

Here is the problem with host tools living along side configurable
binaries and sharing code.  With respect to mkimage, FIT support is
non-optional.  The only reason that FIT signature stuff is optional is
that it introduces too high of a set of dependencies for everyone else
to have installed to even compile mkimage which is in turn required by
the vast majority of targets.  If the failing message that we couldn't
run dtc is not clear enoguh, I am happy to take a patch to make the
problem and solution clearer.

I would go so far as to say that requiring bison and m4 (along with dtc)
to already be compiled in buildroot is not a step too far, but I'm an
OpenEmbedded guy so it's possible I'm just dependency-happy :)  Thanks!

-- 
Tom


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Re: [U-Boot] [PATCH v4 1/2] armv8: Support loading 32-bit OS in AArch32 execution state

[Alexander Graf]

On 06/08/2016 07:14 AM, Alison Wang wrote:

To support loading a 32-bit OS, the execution state will change from
AArch64 to AArch32 when jumping to kernel.

The architecture information will be got through checking FIT
image, then U-Boot will load 32-bit OS or 64-bit OS automatically.

Signed-off-by: Ebony Zhu 
Signed-off-by: Alison Wang 
Signed-off-by: Chenhui Zhao 
---
Changes in v4:
- Correct config ARM64_SUPPORT_AARCH32.
- Omit arch and ftaddr arguments.
- Rename "xreg5" to "tmp".
- Use xxx_RES1 to combine all RES1 fields in xxx register.
- Use an immediate cmp directly.
- Use #ifdef for CONFIG_ARM64_SUPPORT_AARCH32.

Changes in v3:
- Comments the functions and the arguments.
- Rename the real parameters.
- Use the macros instead of the magic values.
- Remove the redundant codes.
- Clean up all of the mess in boot_jump_linux().
- Add CONFIG_ARM64_SUPPORT_AARCH32 to detect for some ARM64 system doesn't 
support AArch32 state.

Changes in v2:
- armv8_switch_to_el2_aarch32() is removed. armv8_switch_to_el2_m is used
   to switch to AArch64 EL2 or AArch32 Hyp.
- armv8_switch_to_el1_aarch32() is removed. armv8_switch_to_el1_m is used
   to switch to AArch64 EL1 or AArch32 SVC.

  arch/arm/Kconfig|   6 ++
  arch/arm/cpu/armv8/start.S  |   1 +
  arch/arm/cpu/armv8/transition.S |   8 +-
  arch/arm/include/asm/macro.h| 172 ++--
  arch/arm/include/asm/system.h   | 111 +-
  arch/arm/lib/bootm.c|  19 -
  common/image-fit.c  |  19 -
  7 files changed, 284 insertions(+), 52 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 77eab66..9cf4acd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -91,6 +91,12 @@ config SYS_L2CACHE_OFF
  If SoC does not support L2CACHE or one do not want to enable
  L2CACHE, choose this option.
  
+config ARM64_SUPPORT_AARCH32

+   bool "ARM64 system support AArch32 execution state"
+   default y if ARM64 && !TARGET_THUNDERX_88XX
+   help
+ This ARM64 system supports AArch32 execution state.
+
  choice
prompt "Target select"
default TARGET_HIKEY
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index e933021..dd69501 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -234,6 +234,7 @@ WEAK(lowlevel_init)
/*
 * All slaves will enter EL2 and optionally EL1.
 */
+   ldr x3, =ES_TO_AARCH64
bl  armv8_switch_to_el2
  #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
bl  armv8_switch_to_el1
diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S
index 253a39b..e61b6ae 100644
--- a/arch/arm/cpu/armv8/transition.S
+++ b/arch/arm/cpu/armv8/transition.S
@@ -11,13 +11,13 @@
  #include 
  
  ENTRY(armv8_switch_to_el2)

-   switch_el x0, 1f, 0f, 0f
+   switch_el x4, 1f, 0f, 0f
  0:ret
-1: armv8_switch_to_el2_m x0
+1: armv8_switch_to_el2_m x0, x3, x4
  ENDPROC(armv8_switch_to_el2)
  
  ENTRY(armv8_switch_to_el1)

-   switch_el x0, 0f, 1f, 0f
+   switch_el x4, 0f, 1f, 0f
  0:ret
-1: armv8_switch_to_el1_m x0, x1
+1: armv8_switch_to_el1_m x0, x3, x4
  ENDPROC(armv8_switch_to_el1)
diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index 9bb0efa..109724f 100644
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -8,6 +8,9 @@
  
  #ifndef __ASM_ARM_MACRO_H__

  #define __ASM_ARM_MACRO_H__
+
+#include 
+
  #ifdef __ASSEMBLY__
  
  /*

@@ -135,13 +138,20 @@ lr.reqx30
  #endif
  .endm
  
-.macro armv8_switch_to_el2_m, xreg1

-   /* 64bit EL2 | HCE | SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1 */
-   mov \xreg1, #0x5b1
-   msr scr_el3, \xreg1
+/*
+ * Switch from EL3 to EL2 for ARMv8
+ * @ep: kernel entry point
+ * @flag:   The execution state flag for lower exception
+ *  level, ES_TO_AARCH64 or ES_TO_AARCH32
+ * @tmp:temporary register
+ *
+ * x1 is machine nr and x2 is ftaddr, they will be passed
+ * to the guest.
+ */
+.macro armv8_switch_to_el2_m, ep, flag, tmp
msr cptr_el3, xzr   /* Disable coprocessor traps to EL3 */
-   mov \xreg1, #0x33ff
-   msr cptr_el2, \xreg1/* Disable coprocessor traps to EL2 */
+   mov \tmp, #CPTR_EL2_RES1
+   msr cptr_el2, \tmp  /* Disable coprocessor traps to EL2 */
  
  	/* Initialize Generic Timers */

msr cntvoff_el2, xzr
@@ -152,45 +162,91 @@ lr.reqx30
 * and RES0 bits (31,30,27,26,24,21,20,17,15-13,10-6) +
 * EE,WXN,I,SA,C,A,M to 0
 */
-   mov \xreg1, #0x0830
-   movk\xreg1, #0x30C5, lsl #16
-   msr sctlr_el2, \xreg1
+   ldr \tmp, =(SCTLR_EL2_RES1 | SCTLR_EL2_EE_LE |\
+   SCTLR_EL2_WXN_DIS | SCTLR_EL2_ICACHE_DIS |\
+  

[U-Boot] [PATCH 6/8] x86: Enable regmap and syscon for coreboot and qemu-x86

[Bin Meng]

These are generic and should be turned on on coreboot and qemu-x86.

Signed-off-by: Bin Meng 
---

 configs/coreboot-x86_defconfig | 2 ++
 configs/qemu-x86_defconfig | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig
index 2fa11fd..b18d80d 100644
--- a/configs/coreboot-x86_defconfig
+++ b/configs/coreboot-x86_defconfig
@@ -24,6 +24,8 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index 45bb3ec..a03cff8 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -28,6 +28,8 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
-- 
2.7.4

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[U-Boot] [PATCH 7/8] x86: Probe pinctrl driver in cpu_init_r()

[Bin Meng]

At present pinctrl driver gets probed in ich6_gpio driver's probe
routine, which has two issues:

 - Pin's PADs only gets configured when GPIO driver is probed, which
   is not done by default. This leaves the board in a partially
   functional state as we must initialize PADs correctly to get
   perepherals fully working.
 - The probe routine of pinctrl driver is called multiple times, as
   normally there are multiple GPIO controllers. It should really
   be called just once.

Move the call to syscon_get_by_driver_data() from ich6_gpio driver
to cpu_init_r().

Signed-off-by: Bin Meng 

---

 arch/x86/cpu/cpu.c | 5 +
 drivers/gpio/intel_ich6_gpio.c | 7 ---
 2 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index e522ff3..269043d 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -24,6 +24,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -751,6 +752,10 @@ int cpu_init_r(void)
uclass_first_device(UCLASS_PCH, );
uclass_first_device(UCLASS_LPC, );
 
+   /* Set up pin control if available */
+   ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, );
+   debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret);
+
return 0;
 }
 
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 2d66d04..fd6181f 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -32,7 +32,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
@@ -113,12 +112,6 @@ static int ich6_gpio_probe(struct udevice *dev)
struct ich6_bank_platdata *plat = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct ich6_bank_priv *bank = dev_get_priv(dev);
-   struct udevice *pinctrl;
-   int ret;
-
-   /* Set up pin control if available */
-   ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, );
-   debug("%s, pinctrl=%p, ret=%d\n", __func__, pinctrl, ret);
 
uc_priv->gpio_count = GPIO_PER_BANK;
uc_priv->bank_name = plat->bank_name;
-- 
2.7.4

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[U-Boot] [PATCH 8/8] x86: broadwell: gpio: Remove the codes to set up pin control

[Bin Meng]

Now that we have set up pin control in cpu_init_r(), remove the
duplicated codes in the broadwell gpio driver.

Signed-off-by: Bin Meng 
---

 drivers/gpio/intel_broadwell_gpio.c | 7 ---
 1 file changed, 7 deletions(-)

diff --git a/drivers/gpio/intel_broadwell_gpio.c 
b/drivers/gpio/intel_broadwell_gpio.c
index 81ce446..8b50900 100644
--- a/drivers/gpio/intel_broadwell_gpio.c
+++ b/drivers/gpio/intel_broadwell_gpio.c
@@ -9,7 +9,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
@@ -119,12 +118,6 @@ static int broadwell_gpio_probe(struct udevice *dev)
struct broadwell_bank_platdata *plat = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct broadwell_bank_priv *priv = dev_get_priv(dev);
-   struct udevice *pinctrl;
-   int ret;
-
-   /* Set up pin control if available */
-   ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, );
-   debug("%s, pinctrl=%p, ret=%d\n", __func__, pinctrl, ret);
 
uc_priv->gpio_count = GPIO_PER_BANK;
uc_priv->bank_name = plat->bank_name;
-- 
2.7.4

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[U-Boot] [PATCH 0/8] x86: baytrail: Various fixes to pinctrl driver to enable SD in Linux

[Bin Meng]

This fixes several issues in the pinctrl driver, and add SD controller
card detect pin's PADs configuration to the device tree, so that
Linux kernel SDHC driver is able to identify an inserted SD card.

Testing was done on MinnowMax board, by booting Linux kernel and check
dmesg log to see if SD card was succesfully identified.

This series is available at u-boot-x86/pinctrl-fixes for testing.


Bin Meng (8):
  x86: ich6_gpio: Output return value of syscon_get_by_driver_data()
  x86: baytrail: Add 'reg' property in the pinctrl node
  x86: baytrail: Change fsp,emmc-boot-mode to "auto"
  x86: baytrail: Configure card detect pin of the SD controller
  x86: Update x86-pinctrl driver device-tree-bindings doc
  x86: Enable regmap and syscon for coreboot and qemu-x86
  x86: Probe pinctrl driver in cpu_init_r()
  x86: broadwell: gpio: Remove the codes to set up pin control

 arch/x86/cpu/cpu.c |  5 +
 arch/x86/dts/bayleybay.dts | 22 +-
 arch/x86/dts/conga-qeval20-qa3-e3845.dts   | 18 +-
 arch/x86/dts/minnowmax.dts | 18 +-
 configs/coreboot-x86_defconfig |  2 ++
 configs/qemu-x86_defconfig |  2 ++
 .../gpio/intel,x86-pinctrl.txt | 16 
 drivers/gpio/intel_broadwell_gpio.c|  7 ---
 drivers/gpio/intel_ich6_gpio.c |  5 -
 9 files changed, 72 insertions(+), 23 deletions(-)

-- 
2.7.4

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Re: [U-Boot] u-boot on Minnowboard max

[Bin Meng]

Hi,

On Wed, Jun 8, 2016 at 8:02 PM, vinoth eswaran  wrote:
> Hello Mr.Bin,
>
>  May I know what is the issue , if you could explain I can fix
> this in my target and could provide the patch. I am stuck up with this
> issue and couldn't able to proceed further.

I've just sent out a series that fixes this issue. Please try it out.

>
>  Thanks a lot:)
>

I've mentioned twice, please don't top-posting. Thanks.

>
> Mit Freundlichen Grüßen
> VinothKumar
> +49 1798909072
>

Regards,
Bin
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[U-Boot] [PATCH 5/8] x86: Update x86-pinctrl driver device-tree-bindings doc

[Bin Meng]

This updates the device-tree-bindings doc for x86-pinctrl driver:

 - clarify "gpio-offset" is required only when "mode-gpio" is set
 - correct property name "pull-strength"
 - use tab instead of space at several places

Signed-off-by: Bin Meng 
---

 doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt 
b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
index 22d3bec..8c3a84c 100644
--- a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
+++ b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
@@ -9,7 +9,7 @@ The PINCTRL master node requires the following properties:
 Pin nodes must be children of the pinctrl master node and can
 contain the following properties:
 - pad-offset   - (required) offset in the IOBASE for the pin to configure
-- gpio-offset  - (required) 2 cells
+- gpio-offset  - (required only when 'mode-gpio' is set) 2 cells
- offset in the GPIOBASE for the pin to configure
- the bit shift in this register (4 = bit 4)
 - mode-gpio- (optional) standalone property to force the pin into GPIO mode
@@ -18,16 +18,16 @@ contain the following properties:
 in case of 'mode-gpio' property set:
 - output-value - (optional) this set the default output value of the GPIO
 - direction- (optional) this set the direction of the gpio
-- pull-str - (optional) this set the pull strength of the pin
+- pull-strength- (optional) this set the pull strength of the pin
 - pull-assign  - (optional) this set the pull assignement (up/down) of the pin
-- invert- (optional) this input pin is inverted
+- invert   - (optional) this input pin is inverted
 
 Example:
 
 pin_usb_host_en0@0 {
-gpio-offset = <0x80 8>;
-pad-offset = <0x260>;
-mode-gpio;
-output-value = <1>;
-direction = ;
+   gpio-offset = <0x80 8>;
+   pad-offset = <0x260>;
+   mode-gpio;
+   output-value = <1>;
+   direction = ;
 };
-- 
2.7.4

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[U-Boot] [PATCH 2/8] x86: baytrail: Add 'reg' property in the pinctrl node

[Bin Meng]

Without a 'reg' property, pinctrl driver probe routine fails in
its pre_probe() with a return value of -EINVAL.

Add 'reg' property for all BayTrail boards. Note for BayleyBay,
the pinctrl node is newly added.

Signed-off-by: Bin Meng 
---

 arch/x86/dts/bayleybay.dts   | 5 +
 arch/x86/dts/conga-qeval20-qa3-e3845.dts | 1 +
 arch/x86/dts/minnowmax.dts   | 1 +
 3 files changed, 7 insertions(+)

diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index 4a50d86..536049b 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -65,6 +65,11 @@
};
};
 
+   pch_pinctrl {
+   compatible = "intel,x86-pinctrl";
+   reg = <0 0>;
+   };
+
pci {
compatible = "pci-x86";
#address-cells = <3>;
diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts 
b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
index 1a4ecaa..7e69ba4 100644
--- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts
+++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
@@ -30,6 +30,7 @@
 
pch_pinctrl {
compatible = "intel,x86-pinctrl";
+   reg = <0 0>;
};
 
chosen {
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 936455b..fda170c 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -29,6 +29,7 @@
 
pch_pinctrl {
compatible = "intel,x86-pinctrl";
+   reg = <0 0>;
 
/* GPIO E0 */
soc_gpio_s5_0@0 {
-- 
2.7.4

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[U-Boot] [PATCH 3/8] x86: baytrail: Change fsp, emmc-boot-mode to "auto"

[Bin Meng]

At present all BayTrail boards configure fsp,emmc-boot-mode to 2,
which means "eMMC 4.1" per FSP documentation. However, eMMC 4.1
only shows up on some early stepping silicon of BayTrail SoC.
Newer stepping SoC integrates an eMMC 4.5 controller. Intel FSP
provides a config option fsp,emmc-boot-mode which tells FSP which
eMMC controller it initializes. Instead of hardcoded to 2, now
we change it to 1 which means "auto".

With this change, MinnowMax board (with a D0 stepping BayTrail SoC)
can see the eMMC 4.5 controller at PCI address 00.17.00 via U-Boot
'pci' command.

Signed-off-by: Bin Meng 
---

 arch/x86/dts/bayleybay.dts   | 2 +-
 arch/x86/dts/conga-qeval20-qa3-e3845.dts | 2 +-
 arch/x86/dts/minnowmax.dts   | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index 536049b..1c2f671 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -218,7 +218,7 @@
fsp,mrc-init-mmio-size = <0x800>;
fsp,mrc-init-spd-addr1 = <0xa0>;
fsp,mrc-init-spd-addr2 = <0xa2>;
-   fsp,emmc-boot-mode = <2>;
+   fsp,emmc-boot-mode = <1>;
fsp,enable-sdio;
fsp,enable-sdcard;
fsp,enable-hsuart1;
diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts 
b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
index 7e69ba4..1e14c8b 100644
--- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts
+++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
@@ -218,7 +218,7 @@
fsp,mrc-init-mmio-size = <0x800>;
fsp,mrc-init-spd-addr1 = <0xa0>;
fsp,mrc-init-spd-addr2 = <0xa2>;
-   fsp,emmc-boot-mode = <2>;
+   fsp,emmc-boot-mode = <1>;
fsp,enable-sdio;
fsp,enable-sdcard;
fsp,enable-hsuart1;
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index fda170c..ba96e36 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -247,7 +247,7 @@
fsp,mrc-init-mmio-size = <0x800>;
fsp,mrc-init-spd-addr1 = <0xa0>;
fsp,mrc-init-spd-addr2 = <0xa2>;
-   fsp,emmc-boot-mode = <2>;
+   fsp,emmc-boot-mode = <1>;
fsp,enable-sdio;
fsp,enable-sdcard;
fsp,enable-hsuart1;
-- 
2.7.4

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[U-Boot] [PATCH 1/8] x86: ich6_gpio: Output return value of syscon_get_by_driver_data()

[Bin Meng]

The call to syscon_get_by_driver_data() does not save its return value.
Print it out to aid debugging.

Signed-off-by: Bin Meng 
---

 drivers/gpio/intel_ich6_gpio.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index b7e379a..2d66d04 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -114,9 +114,11 @@ static int ich6_gpio_probe(struct udevice *dev)
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct ich6_bank_priv *bank = dev_get_priv(dev);
struct udevice *pinctrl;
+   int ret;
 
/* Set up pin control if available */
-   syscon_get_by_driver_data(X86_SYSCON_PINCONF, );
+   ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, );
+   debug("%s, pinctrl=%p, ret=%d\n", __func__, pinctrl, ret);
 
uc_priv->gpio_count = GPIO_PER_BANK;
uc_priv->bank_name = plat->bank_name;
-- 
2.7.4

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[U-Boot] [PATCH 4/8] x86: baytrail: Configure card detect pin of the SD controller

[Bin Meng]

As of today, the latest version FSP (gold4) for BayTrail misses the
PAD configuration of the SD controller's Card Detect signal. The
default PAD value for the CD pin sets the pin to work in GPIO mode,
which causes card detect status cannot be reflected by the Present
State register in the SD controller (bit 16 & bit 18 are always zero).

Add a configuration for this pin in the pinctrl node.

Note I've checked the PAD configuration for all the pins in all the
3 controllers (eMMC/SDIO/SD). Only this SDMMC3_CD_B pin does not get
initialized to correct mode by FSP. With fsp,emmc-boot-mode set to
2 (eMMC 4.1), eMMC pins are initialized to func 1, but if we set
fsp,emmc-boot-mode to 1 (auto), those pins are initialized to func 3
which is correct according to datasheet.

Signed-off-by: Bin Meng 
---

 arch/x86/dts/bayleybay.dts   | 15 +++
 arch/x86/dts/conga-qeval20-qa3-e3845.dts | 15 +++
 arch/x86/dts/minnowmax.dts   | 15 +++
 3 files changed, 45 insertions(+)

diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index 1c2f671..c8907ce 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -68,6 +68,21 @@
pch_pinctrl {
compatible = "intel,x86-pinctrl";
reg = <0 0>;
+
+   /*
+* As of today, the latest version FSP (gold4) for BayTrail
+* misses the PAD configuration of the SD controller's Card
+* Detect signal. The default PAD value for the CD pin sets
+* the pin to work in GPIO mode, which causes card detect
+* status cannot be reflected by the Present State register
+* in the SD controller (bit 16 & bit 18 are always zero).
+*
+* Configure this pin to function 1 (SD controller).
+*/
+   sdmmc3_cd@0 {
+   pad-offset = <0x3a0>;
+   mode-func = <1>;
+   };
};
 
pci {
diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts 
b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
index 1e14c8b..fba089d 100644
--- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts
+++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
@@ -31,6 +31,21 @@
pch_pinctrl {
compatible = "intel,x86-pinctrl";
reg = <0 0>;
+
+   /*
+* As of today, the latest version FSP (gold4) for BayTrail
+* misses the PAD configuration of the SD controller's Card
+* Detect signal. The default PAD value for the CD pin sets
+* the pin to work in GPIO mode, which causes card detect
+* status cannot be reflected by the Present State register
+* in the SD controller (bit 16 & bit 18 are always zero).
+*
+* Configure this pin to function 1 (SD controller).
+*/
+   sdmmc3_cd@0 {
+   pad-offset = <0x3a0>;
+   mode-func = <1>;
+   };
};
 
chosen {
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index ba96e36..1a8a8cc 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -73,6 +73,21 @@
output-value = <1>;
direction = ;
};
+
+   /*
+* As of today, the latest version FSP (gold4) for BayTrail
+* misses the PAD configuration of the SD controller's Card
+* Detect signal. The default PAD value for the CD pin sets
+* the pin to work in GPIO mode, which causes card detect
+* status cannot be reflected by the Present State register
+* in the SD controller (bit 16 & bit 18 are always zero).
+*
+* Configure this pin to function 1 (SD controller).
+*/
+   sdmmc3_cd@0 {
+   pad-offset = <0x3a0>;
+   mode-func = <1>;
+   };
};
 
chosen {
-- 
2.7.4

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Re: [U-Boot] [PATCH v2] sunxi: Support booting from SPI flash

[boobwrt]

Hello

Nice to see new entry to boot.
I would like to know if sdcard wired in spi mode can working with this spi boot 
support.
Why put sdcard in spi when i have an sdcard slot? :)
Just to solder it for bypass crappy sdcard socket pin contact then boot from 
usb.
microsd was cheap in 512mb size or less.

Is there limitation in chip memory selection?
Anyway thank for new support 
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[U-Boot] U-BOOT for I960 Board

[Vincent Poret]

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Re: [U-Boot] [linux-sunxi] Re: [PATCH v2] sunxi: Support booting from SPI flash

[Siarhei Siamashka]

Hello,

On Wed, 8 Jun 2016 02:56:41 -0700 (PDT)
boob...@gmail.com wrote:

> Hello
> 
> Nice to see new entry to boot.
> I would like to know if sdcard wired in spi mode can working with
> this spi boot support.

No, it can't. The SPI protocol used by the SD card is different
from the SPI protocol used by the SPI flash chips. The SPI is just
an underlying bus to send and receive data, but the higher level
protocols are incompatible.

> Why put sdcard in spi when i have an sdcard slot? :)
> Just to solder it for bypass crappy sdcard socket pin contact

You can still solder the SD card instead of plugging it into
the SD card slot.

In fact, that's how it is usually done with eMMC. And you can even
buy some development boards with eMMC instead of experimenting
with this stuff yourself.

> then boot from usb.
> microsd was cheap in 512mb size or less.

The price difference between the Orange Pi PC and the Orange Pi PC Plus
boards is not very big:

http://www.aliexpress.com/store/product/Orange-Pi-PC-linux-and-android-mini-PC-Beyond-Raspberry-Pi-2/1553371_32448079125.html
http://www.aliexpress.com/store/product/Orange-Pi-PC-Plus-ubuntu-linux-and-android-mini-PC-Beyond-Raspberry-Pi-2/1553371_32668618847.html

For extra 4.45 EUR you get a 8GB eMMC and also some sort of WiFi.
And the eMMC is also much faster than a regular SD card, so it's
not a very bad deal.

> Is there limitation in chip memory selection?

Any SPI flash chip should be supported if it uses the right voltage
(compatible with 3.3V) and supports the Read Data Bytes command (the
opcode 0x03, followed by a 24-bit address). You can always check the
datasheet.

A suitable SPI flash chip, which seems to cost only 4 cents, is
sold here:

http://www.aliexpress.com/item/W25Q16BVSSIG-W25Q16BVSIG-2MB-SOP8/32660083443.html

But I have no idea if this particular seller is trustworthy. One can
still easily find similar chips for around 10 cents in other places.

The SPI flash is cheaper than the eMMC if we look at the absolute
price. But the price per megabyte is an entirely different story.

For U-Boot you would need a 1 MiB (8 Mbit) chip, just check the
size of the u-boot-sunxi-with-spl.bin file and ensure a bit of
extra headroom.

> Anyway thank for new support 

Thanks.

-- 
Regards,
Sierž
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[U-Boot] [PATCH v6 04/10] armv8: ls2080aqds: disable IFC NOR & QIXIS when QSPI enable

[Yuan Yao]

From: Yuan Yao 

When QSPI is enabled, NOR flash and QIXIS can't be accessed
through IFC due to pin mux.
So enable I2C QIXIS access and I2C early init to read the
sysclk and ddrclk.

Signed-off-by: Yuan Yao 
---
Changed in v5:
Use I2C to read the clocks instead of the hard-coded clocks. 
---
 board/freescale/ls2080aqds/ls2080aqds.c |  3 +++
 include/configs/ls2080aqds.h| 10 ++
 2 files changed, 13 insertions(+)

diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index d7acb48..19bb4c6 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -219,6 +219,9 @@ int board_init(void)
 
 int board_early_init_f(void)
 {
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+   i2c_early_init_f();
+#endif
fsl_lsch3_early_init_f();
 #ifdef CONFIG_FSL_QSPI
/* input clk: 1/2 platform clk, output: input/20 */
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 4b27114..ccc987c 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -17,6 +17,16 @@ unsigned long get_board_ddr_clk(void);
 #endif
 
 #define CONFIG_SYS_FSL_CLK
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_EARLY_INIT
+#define CONFIG_SYS_I2C_IFDR_DIV0x7e
+#endif
+
+#define CONFIG_SYS_I2C_FPGA_ADDR   0x66
 #define CONFIG_SYS_CLK_FREQget_board_sys_clk()
 #define CONFIG_DDR_CLK_FREQget_board_ddr_clk()
 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v6 06/10] dm: dts: ls2080aqds: Add QSPI dts node

[Yuan Yao]

From: Yuan Yao 

Add QSPI controller and slave dts node for LS2080AQDS board.

Signed-off-by: Yuan Yao 
---
 arch/arm/dts/fsl-ls2080a-qds.dts | 14 ++
 arch/arm/dts/fsl-ls2080a.dtsi| 10 ++
 2 files changed, 24 insertions(+)

diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts
index 547ec27..0a7f1ff 100644
--- a/arch/arm/dts/fsl-ls2080a-qds.dts
+++ b/arch/arm/dts/fsl-ls2080a-qds.dts
@@ -15,6 +15,7 @@
compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
 
aliases {
+   spi0 = 
spi1 = 
};
 };
@@ -51,3 +52,16 @@
reg = <2>;
};
 };
+
+ {
+   bus-num = <0>;
+   status = "okay";
+
+   qflash0: s25fs256s@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   };
+};
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index a5c579c..68ed133 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -126,4 +126,14 @@
interrupts = <0 26 0x4>; /* Level high type */
num-cs = <6>;
};
+
+   qspi: quadspi@155 {
+   compatible = "fsl,vf610-qspi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0 0x20c 0x0 0x1>,
+   <0x0 0x2000 0x0 0x1000>;
+   reg-names = "QuadSPI", "QuadSPI-memory";
+   num-cs = <4>;
+   };
 };
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v6 09/10] ls2080aqds_nand_defconfig: Enable QSPI & its dependence

[Yuan Yao]

From: Yuan Yao 

The Freescale QSPI driver has been converted to Driver Model.
This patch enable FSL_QSPI and its dependence options, DM, DM_SPI,
OF_CONTROL and so on.

Signed-off-by: Yuan Yao 
---
Changed in v6:
Add CONFIG_CMD_SF in defconfig.
---
 configs/ls2080aqds_nand_defconfig | 9 +
 1 file changed, 9 insertions(+)

diff --git a/configs/ls2080aqds_nand_defconfig 
b/configs/ls2080aqds_nand_defconfig
index 1302313..d567878 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -6,6 +6,14 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_DISABLE_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
@@ -18,6 +26,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v6 07/10] armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND boot

[Yuan Yao]

From: Yuan Yao 

In order to access QSPI flash we must asserted ISO allowing
the DUT to access the full IFC domain.
But deasserted the unused ISO will allowing maximum performance.

Signed-off-by: Yuan Yao 
---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++
 board/freescale/ls2080aqds/ls2080aqds.c| 9 +
 include/configs/ls2080aqds.h   | 6 ++
 3 files changed, 17 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index bfff2ec..7c47cc8 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -128,6 +128,8 @@
 #define DCFG_PORSR1_RCW_SRC_NOR0x12f0
 #define DCFG_RCWSR13   0x130
 #define DCFG_RCWSR13_DSPI  (0 << 8)
+#define DCFG_RCWSR15   0x138
+#define DCFG_RCWSR15_IFCGRPABASE_QSPI  0x3
 
 #define DCFG_DCSR_BASE 0X70010ULL
 #define DCFG_DCSR_PORCR1   0x000
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index 19bb4c6..8bdcb04 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -208,6 +208,15 @@ int board_init(void)
else
config_board_mux(MUX_TYPE_SDHC);
 
+#if defined(CONFIG_NAND) && defined(CONFIG_FSL_QSPI)
+   val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
+
+   if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
+   QIXIS_WRITE(brdcfg[9],
+   (QIXIS_READ(brdcfg[9]) & 0xf8) |
+FSL_QIXIS_BRDCFG9_QSPI);
+#endif
+
 #ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)_environment[0];
 #endif
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 8e193a6..7152c2b 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -303,6 +303,12 @@ unsigned long get_board_ddr_clk(void);
 #define FSL_QSPI_FLASH_SIZE(1 << 26) /* 64MB */
 #define FSL_QSPI_FLASH_NUM 4
 #endif
+/*
+ * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
+ * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
+ * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
+ */
+#define FSL_QIXIS_BRDCFG9_QSPI 0x1
 
 #endif
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v6 10/10] armv8: ls2080aqds: Enable QSPI boot support

[Yuan Yao]

From: Yuan Yao 

This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.

Signed-off-by: Yuan Yao 
---
Changed in v6:
Add CONFIG_CMD_SF in defconfig.
Changed in v4:
Merged the below patch into one:
board: freescale: ls2080aqds: Enable early I2C access for QSPI boot
Changed in v3:
1, Rebase to lastest code.
2, Give up to change the sequence for "show_board_info" in 
"init_sequence_f".
---
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |  4 
 board/freescale/ls2080aqds/ls2080aqds.c|  2 ++
 configs/ls2080aqds_qspi_defconfig  | 28 ++
 include/configs/ls2080a_common.h   |  2 ++
 include/configs/ls2080aqds.h   | 10 +
 5 files changed, 46 insertions(+)
 create mode 100644 configs/ls2080aqds_qspi_defconfig

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h 
b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 702b9fa..f07a49a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -121,6 +121,8 @@ static const struct sys_mmu_table early_mmu_table[] = {
  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
+   { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+ CONFIG_SYS_FSL_QSPI_SIZE1,  MT_NORMAL, PTE_BLOCK_NON_SHARE},
/* For IFC Region #1, only the first 4MB is cache-enabled */
{ CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
  CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PTE_BLOCK_NON_SHARE },
@@ -175,6 +177,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
+   { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+ CONFIG_SYS_FSL_QSPI_SIZE1,  MT_NORMAL, PTE_BLOCK_NON_SHARE},
{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
  CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE,
  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index 8bdcb04..23ebcc1 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -81,6 +81,8 @@ int checkboard(void)
puts("PromJet\n");
else if (sw == 0x9)
puts("NAND\n");
+   else if (sw == 0xf)
+   puts("QSPI\n");
else if (sw == 0x15)
printf("IFCCard\n");
else
diff --git a/configs/ls2080aqds_qspi_defconfig 
b/configs/ls2080aqds_qspi_defconfig
new file mode 100644
index 000..194d280
--- /dev/null
+++ b/configs/ls2080aqds_qspi_defconfig
@@ -0,0 +1,28 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080AQDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT,LS2080A"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index eab410e..71f830a 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -29,11 +29,13 @@
 #define CONFIG_FSL_CAAM/* Enable SEC/CAAM */
 
 /* Link Definitions */
+#ifndef CONFIG_QSPI_BOOT
 #ifdef CONFIG_SPL
 #define CONFIG_SYS_TEXT_BASE   0x8040
 #else
 #define CONFIG_SYS_TEXT_BASE   0x3010
 #endif
+#endif
 
 #ifdef CONFIG_EMU
 #define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 55d6c27..5dfba7a 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -172,11 +172,13 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_LBMAP_DFLTBANK   0x00
 #define QIXIS_LBMAP_ALTBANK0x04
 #define QIXIS_LBMAP_NAND   0x09
+#define QIXIS_LBMAP_QSPI   0x0f
 #define QIXIS_RST_CTL_RESET0x31
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE   0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START  0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE  0x08
 #define QIXIS_RCW_SRC_NAND 0x107
+#define QIXIS_RCW_SRC_QSPI 0x62
 #defineQIXIS_RST_FORCE_MEM 0x01

[U-Boot] [PATCH v6 08/10] configs: ls2080a: Increase load image len in NAND boot

[Yuan Yao]

From: Yuan Yao 

Freescale QSPI and DSPI driver have been converted to Driver Mode.
This converting bring dtb file for u-boot and this increase the size
of u-boot image.
LS2080A nand boot use SPL framework.
This patch increase the size of image load from NAND to RAM in SPL.

Signed-off-by: Yuan Yao 
---
 include/configs/ls2080a_common.h | 2 +-
 include/configs/ls2080aqds.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 48b1e15..eab410e 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -283,7 +283,7 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_NAND_U_BOOT_DST
 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0010
 #define CONFIG_SYS_SPL_MALLOC_START0x8020
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (640 * 1024)
 
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)  /* Increase max gunzip size */
 
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 7152c2b..55d6c27 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -237,7 +237,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_ENV_SIZE0x2000
 #define CONFIG_SPL_PAD_TO  0x2
 #define CONFIG_SYS_NAND_U_BOOT_OFFS(256 * 1024)
-#define CONFIG_SYS_NAND_U_BOOT_SIZE(512 * 1024)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE(640 * 1024)
 #else
 #define CONFIG_SYS_CSPR0_EXT   CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0   CONFIG_SYS_NOR0_CSPR_EARLY
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v6 05/10] configs: ls2080aqds: Enable QSPI flash support

[Yuan Yao]

From: Yuan Yao 

Enable QSPI flash related configure options.

Signed-off-by: Yuan Yao 
---
Changed in v6:
remove CONFIG_CMD_SF.
---
 include/configs/ls2080aqds.h | 15 ++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index ccc987c..8e193a6 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -289,8 +289,21 @@ unsigned long get_board_ddr_clk(void);
 #define I2C_MUX_CH_DEFAULT  0x8
 
 /* SPI */
-#ifdef CONFIG_FSL_DSPI
+#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
 #define CONFIG_SPI_FLASH
+
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_EON
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE(1 << 26) /* 64MB */
+#define FSL_QSPI_FLASH_NUM 4
+#endif
+
 #endif
 
 /*
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v6 03/10] configs: ls2080a_common: Remove duplicate NOR configs

[Yuan Yao]

From: Yuan Yao 

The NOR flash related configure options also appear in ls2080aqds.h and
ls2080ardb.h, and the two files all have included ls2080a_common.h.
This patch remove the duplicated options in ls2080a_common.h.

Signed-off-by: Yuan Yao 
---
 include/configs/ls2080a_common.h | 7 ---
 include/configs/ls2080a_simu.h   | 7 +++
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index c78aeb5..48b1e15 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -138,13 +138,6 @@
 #define CONFIG_SYS_FLASH1_BASE_PHYS0xC000
 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY  0x800
 
-#ifndef CONFIG_SYS_NO_FLASH
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#endif
-
 #ifndef __ASSEMBLY__
 unsigned long long get_qixis_addr(void);
 #endif
diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h
index 7563aaf..7f245b5 100644
--- a/include/configs/ls2080a_simu.h
+++ b/include/configs/ls2080a_simu.h
@@ -30,6 +30,13 @@
 #define CONFIG_SYS_NOR0_CSPR_EXT   (0x0)
 #define CONFIG_SYS_NOR_AMASK   IFC_AMASK(128*1024*1024)
 
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#endif
+
 /*
  * NOR Flash Timing Params
  */
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v6 02/10] armv8: ls2080aqds: Select QSPI CLK div via SCFG

[Yuan Yao]

From: Yuan Yao 

QSPI module output SCLK divisor value is configured through SCFG.

Signed-off-by: Yuan Yao 
---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
 board/freescale/ls2080aqds/ls2080aqds.c| 5 +
 2 files changed, 6 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 65b3357..bfff2ec 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -139,6 +139,7 @@
 /* Supplemental Configuration */
 #define SCFG_BASE  0x01fc
 #define SCFG_USB3PRM1CR0x000
+#define SCFG_QSPICLKCTLR   0x10
 
 #define TP_ITYP_AV 0x0001  /* Initiator available */
 #define TP_ITYP_TYPE(x)(((x) & 0x6) >> 1)  /* Initiator Type */
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index b3bd40a..d7acb48 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -26,6 +26,7 @@
 
 #define PIN_MUX_SEL_SDHC   0x00
 #define PIN_MUX_SEL_DSPI   0x0a
+#define SCFG_QSPICLKCTRL_DIV_20(5 << 27)
 
 #define SET_SDHC_MUX_SEL(reg, value)   ((reg & 0xf0) | value)
 
@@ -219,6 +220,10 @@ int board_init(void)
 int board_early_init_f(void)
 {
fsl_lsch3_early_init_f();
+#ifdef CONFIG_FSL_QSPI
+   /* input clk: 1/2 platform clk, output: input/20 */
+   out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
+#endif
return 0;
 }
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v6 01/10] drivers: i2c: mxc: Add early init

[Yuan Yao]

From: Yuan Yao 

Add early i2c init function with conservative divider when the exact
clock rate is not available.

Signed-off-by: Yuan Yao 
---
New add in v3.
---
 drivers/i2c/i2c_core.c |  5 +
 drivers/i2c/mxc_i2c.c  | 27 +++
 include/i2c.h  |  3 +++
 3 files changed, 35 insertions(+)

diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c
index 41cc3b8..16b1aba 100644
--- a/drivers/i2c/i2c_core.c
+++ b/drivers/i2c/i2c_core.c
@@ -233,6 +233,11 @@ __weak void i2c_init_board(void)
 {
 }
 
+/* implement possible for i2c specific early i2c init */
+__weak void i2c_early_init_f(void)
+{
+}
+
 /*
  * i2c_init_all():
  *
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 445fa21..f340208 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -32,6 +32,14 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define IMX_I2C_REGSHIFT   2
 #define VF610_I2C_REGSHIFT 0
+
+#define I2C_EARLY_INIT_INDEX   0
+#ifdef CONFIG_SYS_I2C_IFDR_DIV
+#define I2C_IFDR_DIV_CONSERVATIVE  CONFIG_SYS_I2C_IFDR_DIV
+#else
+#define I2C_IFDR_DIV_CONSERVATIVE  0x7e
+#endif
+
 /* Register index */
 #define IADR   0
 #define IFDR   1
@@ -660,6 +668,25 @@ void bus_i2c_init(int index, int speed, int unused,
 }
 
 /*
+ * Early init I2C for prepare read the clk through I2C.
+ */
+void i2c_early_init_f(void)
+{
+   ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
+   bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
+   & I2C_QUIRK_FLAG ? true : false;
+   int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
+
+   /* Set I2C divider value */
+   writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
+   /* Reset module */
+   writeb(I2CR_IDIS, base + (I2CR << reg_shift));
+   writeb(0, base + (I2SR << reg_shift));
+   /* Enable I2C */
+   writeb(I2CR_IEN, base + (I2CR << reg_shift));
+}
+
+/*
  * Init I2C Bus
  */
 static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
diff --git a/include/i2c.h b/include/i2c.h
index 1f5ae45..d500445 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -701,6 +701,9 @@ extern struct i2c_bus_hose  i2c_bus[];
  * Initialization, must be called once on start up, may be called
  * repeatedly to change the speed and slave addresses.
  */
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+void i2c_early_init_f(void);
+#endif
 void i2c_init(int speed, int slaveaddr);
 void i2c_init_board(void);
 #ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v6 00/10] armv8: ls2080aqds: Enable QSPI boot support

[Yuan Yao]

From: Yuan Yao 

This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.

Yuan Yao (10):
  drivers: i2c: mxc: Add early init
  armv8: ls2080aqds: Select QSPI CLK div via SCFG
  configs: ls2080a_common: Remove duplicate NOR configs
  armv8: ls2080aqds: disable IFC NOR & QIXIS when QSPI enable
  configs: ls2080aqds: Enable QSPI flash support
Changed in v6.
  dm: dts: ls2080aqds: Add QSPI dts node
  armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND boot
  configs: ls2080a: Increase load image len in NAND boot
  ls2080aqds_nand_defconfig: Enable QSPI & its dependence
Changed in v6.
  armv8: ls2080aqds: Enable QSPI boot support
Changed in v6.

 arch/arm/dts/fsl-ls2080a-qds.dts   | 14 +++
 arch/arm/dts/fsl-ls2080a.dtsi  | 10 +
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |  4 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  3 ++
 board/freescale/ls2080aqds/ls2080aqds.c| 19 ++
 configs/ls2080aqds_nand_defconfig  |  8 
 configs/ls2080aqds_qspi_defconfig  | 27 ++
 drivers/i2c/i2c_core.c |  5 +++
 drivers/i2c/mxc_i2c.c  | 27 ++
 include/configs/ls2080a_common.h   | 11 ++
 include/configs/ls2080a_simu.h |  7 
 include/configs/ls2080aqds.h   | 43 +-
 include/i2c.h  |  3 ++
 13 files changed, 171 insertions(+), 10 deletions(-)
 create mode 100644 configs/ls2080aqds_qspi_defconfig

-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v5 09/10] ls2080aqds_nand_defconfig: Enable QSPI & its dependence

[Yuan Yao]

From: Yuan Yao 

The Freescale QSPI driver has been converted to Driver Model.
This patch enable FSL_QSPI and its dependence options, DM, DM_SPI,
OF_CONTROL and so on.

Signed-off-by: Yuan Yao 
---
 configs/ls2080aqds_nand_defconfig | 8 
 1 file changed, 8 insertions(+)

diff --git a/configs/ls2080aqds_nand_defconfig 
b/configs/ls2080aqds_nand_defconfig
index 1302313..32f35cc 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -6,6 +6,14 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_DISABLE_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v5 08/10] configs: ls2080a: Increase load image len in NAND boot

[Yuan Yao]

From: Yuan Yao 

Freescale QSPI and DSPI driver have been converted to Driver Mode.
This converting bring dtb file for u-boot and this increase the size
of u-boot image.
LS2080A nand boot use SPL framework.
This patch increase the size of image load from NAND to RAM in SPL.

Signed-off-by: Yuan Yao 
---
 include/configs/ls2080a_common.h | 2 +-
 include/configs/ls2080aqds.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 48b1e15..eab410e 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -283,7 +283,7 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_NAND_U_BOOT_DST
 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0010
 #define CONFIG_SYS_SPL_MALLOC_START0x8020
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (640 * 1024)
 
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)  /* Increase max gunzip size */
 
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 13e18db..b28cf36 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -237,7 +237,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_ENV_SIZE0x2000
 #define CONFIG_SPL_PAD_TO  0x2
 #define CONFIG_SYS_NAND_U_BOOT_OFFS(256 * 1024)
-#define CONFIG_SYS_NAND_U_BOOT_SIZE(512 * 1024)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE(640 * 1024)
 #else
 #define CONFIG_SYS_CSPR0_EXT   CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0   CONFIG_SYS_NOR0_CSPR_EARLY
-- 
2.1.0.27.g96db324

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Re: [U-Boot] [PATCH v3 01/12] common: bootdelay: move CONFIG_BOOTDELAY into a Kconfig option

[Igor Grinberg]

Hi Heiko,

On 06/07/2016 09:31 AM, Heiko Schocher wrote:
> move CONFIG_BOOTDELAY into a Kconfig option. Used for this
> purpose the moveconfig.py tool in tools.

That's great! Finally, someone did this long long patch!
It has been sitting in my queue for about a year... and I never
had the time to rework it.

> 
> Signed-off-by: Heiko Schocher 
> 
> Reviewed-by: Tom Rini 

Acked-by: Igor Grinberg 

Thanks!

-- 
Regards,
Igor.
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Re: [U-Boot] [PATCH v3 09/12] mmc: omap_hsmmc: enable 8bit interface for eMMC for AM33xx

[Igor Grinberg]

Hi Heiko,

On 06/07/2016 09:31 AM, Heiko Schocher wrote:
> Enable 8bit interface on HSMMC2 for am33xx to support 8bit eMMC chips.
> 
> Signed-off-by: Heiko Schocher 
> Reviewed-by: Tom Rini 
> 
> ---
> 
> Changes in v3: None
> Changes in v2:
> - add Reviewed-by from Tom Rini
> 
>  drivers/mmc/omap_hsmmc.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
> index be34057..d007b56 100644
> --- a/drivers/mmc/omap_hsmmc.c
> +++ b/drivers/mmc/omap_hsmmc.c
> @@ -701,6 +701,7 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, 
> uint f_max, int cd_gpio,
>   priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
>  #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
>   defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) || \
> + defined(CONFIG_AM33XX) || \
>   defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
>   defined(CONFIG_HSMMC2_8BIT)

Don't you find the above habit terrible - adding more and more SoCs
to the ifdef...

Don't get me wrong, I'm not trying to prevent this patch - please merge it.
But I think, we should do something about the above (and I can see also other
cases in the same function).

>   /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
> 

-- 
Regards,
Igor.
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Re: [U-Boot] [PATCH v2 2/4] usb: dwc3: Add helper functions to enable snooping and burst settings

[Rajesh Bhagat]

> -Original Message-
> From: Marek Vasut [mailto:ma...@denx.de]
> Sent: Monday, June 06, 2016 6:24 PM
> To: Rajat Srivastava ; u-boot@lists.denx.de
> Cc: l.majew...@samsung.com; s...@chromium.org; albert.u.b...@aribaud.net;
> prabha...@freescale.com; york sun ; Mingkai Hu
> ; Rajesh Bhagat ;
> michal.si...@xilinx.com; felipe.ba...@linux.intel.com
> Subject: Re: [PATCH v2 2/4] usb: dwc3: Add helper functions to enable 
> snooping and
> burst settings
> 
> On 06/06/2016 11:16 AM, Rajat Srivastava wrote:
> > Adds helper functions to enable snooping and outstanding burst beat
> > settings.
> >
> > Signed-off-by: Rajat Srivastava 
> > Signed-off-by: Rajesh Bhagat 
> > ---
> > Changes in v2:
> >  - Removes SoC specific flags and added helper functions
> >
> >  drivers/usb/dwc3/core.c | 45
> > +
> >  drivers/usb/dwc3/core.h |  7 +++
> >  2 files changed, 52 insertions(+)
> >
> > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index
> > 85cc96a..0b3c596 100644
> > --- a/drivers/usb/dwc3/core.c
> > +++ b/drivers/usb/dwc3/core.c
> > @@ -599,6 +599,51 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc)
> >
> >  #define DWC3_ALIGN_MASK(16 - 1)
> >
> > +void dwc3_core_incr_burst_enable(int index, int btype_incr_val,
> > +int breq_limit)
> > +{
> > +   struct dwc3 *dwc;
> > +   u32 reg;
> > +
> > +   list_for_each_entry(dwc, _list, list) {
> 

Hello Marek, 

> Why is this iterating over a list of all controllers ?

This function has to be called from Soc specific code to pass some register 
settings. And dwc pointer 
would not be available there. Hence, index is passed to determine dwc pointer. 

> Should this be enabled on per-controller basis by some DT prop ?
>

We are using dwc3 driver with non DT support. 

Best Regards,
Rajesh Bhagat 

 
> > +   if (dwc->index != index)
> > +   continue;
> > +
> > +   /*
> > +* Change burst beat and outstanding pipelined
> > +* transfers requests
> > +*/
> > +   reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
> > +   reg = (reg & ~DWC3_INCR_BTYPE_MASK) | btype_incr_val;
> > +   dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
> > +
> > +   reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG1);
> > +   reg = (reg & ~DWC3_BREQ_LIMIT_MASK) | (breq_limit << 8);
> > +   dwc3_writel(dwc->regs, DWC3_GSBUSCFG1, reg);
> > +   break;
> > +   }
> > +}
> > +
> > +void dwc3_core_set_snooping(int index, bool snoop) {
> > +   struct dwc3 *dwc;
> > +   u32 reg;
> > +
> > +   list_for_each_entry(dwc, _list, list) {
> > +   if (dwc->index != index)
> > +   continue;
> > +
> > +   /* Enable/Disable snooping */
> > +   reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
> > +   if (snoop)
> > +   reg = reg | DWC3_SNOOP_ENABLE;
> > +   else
> > +   reg = reg & ~DWC3_SNOOP_ENABLE;
> > +   dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
> > +   break;
> > +   }
> > +}
> > +
> >  /**
> >   * dwc3_uboot_init - dwc3 core uboot initialization code
> >   * @dwc3_dev: struct dwc3_device containing initialization data diff
> > --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index
> > 72d2fcd..455e7fa 100644
> > --- a/drivers/usb/dwc3/core.h
> > +++ b/drivers/usb/dwc3/core.h
> > @@ -593,6 +593,13 @@ struct dwc3_hwparams {
> >  /* HWPARAMS7 */
> >  #define DWC3_RAM1_DEPTH(n) ((n) & 0x)
> >
> > +/* GSBUSCFG0 */
> > +#define DWC3_SNOOP_ENABLE  (0x)
> > +#define DWC3_INCR_BTYPE_MASK   (0xff)
> > +
> > +/* GSBUSCFG1 */
> > +#define DWC3_BREQ_LIMIT_MASK   (0xf00)
> > +
> >  struct dwc3_request {
> > struct usb_request  request;
> > struct list_headlist;
> >
> 
> 
> --
> Best regards,
> Marek Vasut
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[U-Boot] [PATCH v5 10/10] armv8: ls2080aqds: Enable QSPI boot support

[Yuan Yao]

From: Yuan Yao 

This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.

Signed-off-by: Yuan Yao 
---
Changed in v4:
Merged the below patch into one:
board: freescale: ls2080aqds: Enable early I2C access for QSPI boot
Changed in v3:
1, Rebase to lastest code.
2, Give up to change the sequence for "show_board_info" in 
"init_sequence_f".
---
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |  4 
 board/freescale/ls2080aqds/ls2080aqds.c|  2 ++
 configs/ls2080aqds_qspi_defconfig  | 27 ++
 include/configs/ls2080a_common.h   |  2 ++
 include/configs/ls2080aqds.h   | 10 ++
 5 files changed, 45 insertions(+)
 create mode 100644 configs/ls2080aqds_qspi_defconfig

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h 
b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 702b9fa..f07a49a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -121,6 +121,8 @@ static const struct sys_mmu_table early_mmu_table[] = {
  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
+   { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+ CONFIG_SYS_FSL_QSPI_SIZE1,  MT_NORMAL, PTE_BLOCK_NON_SHARE},
/* For IFC Region #1, only the first 4MB is cache-enabled */
{ CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
  CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PTE_BLOCK_NON_SHARE },
@@ -175,6 +177,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
+   { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+ CONFIG_SYS_FSL_QSPI_SIZE1,  MT_NORMAL, PTE_BLOCK_NON_SHARE},
{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
  CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE,
  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index 8bdcb04..23ebcc1 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -81,6 +81,8 @@ int checkboard(void)
puts("PromJet\n");
else if (sw == 0x9)
puts("NAND\n");
+   else if (sw == 0xf)
+   puts("QSPI\n");
else if (sw == 0x15)
printf("IFCCard\n");
else
diff --git a/configs/ls2080aqds_qspi_defconfig 
b/configs/ls2080aqds_qspi_defconfig
new file mode 100644
index 000..40a2cd9
--- /dev/null
+++ b/configs/ls2080aqds_qspi_defconfig
@@ -0,0 +1,27 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080AQDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT,LS2080A"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index eab410e..71f830a 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -29,11 +29,13 @@
 #define CONFIG_FSL_CAAM/* Enable SEC/CAAM */
 
 /* Link Definitions */
+#ifndef CONFIG_QSPI_BOOT
 #ifdef CONFIG_SPL
 #define CONFIG_SYS_TEXT_BASE   0x8040
 #else
 #define CONFIG_SYS_TEXT_BASE   0x3010
 #endif
+#endif
 
 #ifdef CONFIG_EMU
 #define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index b28cf36..97afda6 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -172,11 +172,13 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_LBMAP_DFLTBANK   0x00
 #define QIXIS_LBMAP_ALTBANK0x04
 #define QIXIS_LBMAP_NAND   0x09
+#define QIXIS_LBMAP_QSPI   0x0f
 #define QIXIS_RST_CTL_RESET0x31
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE   0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START  0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE  0x08
 #define QIXIS_RCW_SRC_NAND 0x107
+#define QIXIS_RCW_SRC_QSPI 0x62
 #defineQIXIS_RST_FORCE_MEM 0x01
 
 #define CONFIG_SYS_CSPR3_EXT   (0x0)
@@ -267,11 +269,19 @@ unsigned 

[U-Boot] [PATCH v5 06/10] dm: dts: ls2080aqds: Add QSPI dts node

[Yuan Yao]

From: Yuan Yao 

Add QSPI controller and slave dts node for LS2080AQDS board.

Signed-off-by: Yuan Yao 
---
 arch/arm/dts/fsl-ls2080a-qds.dts | 14 ++
 arch/arm/dts/fsl-ls2080a.dtsi| 10 ++
 2 files changed, 24 insertions(+)

diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts
index 547ec27..0a7f1ff 100644
--- a/arch/arm/dts/fsl-ls2080a-qds.dts
+++ b/arch/arm/dts/fsl-ls2080a-qds.dts
@@ -15,6 +15,7 @@
compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
 
aliases {
+   spi0 = 
spi1 = 
};
 };
@@ -51,3 +52,16 @@
reg = <2>;
};
 };
+
+ {
+   bus-num = <0>;
+   status = "okay";
+
+   qflash0: s25fs256s@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   };
+};
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index a5c579c..68ed133 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -126,4 +126,14 @@
interrupts = <0 26 0x4>; /* Level high type */
num-cs = <6>;
};
+
+   qspi: quadspi@155 {
+   compatible = "fsl,vf610-qspi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0 0x20c 0x0 0x1>,
+   <0x0 0x2000 0x0 0x1000>;
+   reg-names = "QuadSPI", "QuadSPI-memory";
+   num-cs = <4>;
+   };
 };
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v5 07/10] armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND boot

[Yuan Yao]

From: Yuan Yao 

In order to access QSPI flash we must asserted ISO allowing
the DUT to access the full IFC domain.
But deasserted the unused ISO will allowing maximum performance.

Signed-off-by: Yuan Yao 
---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++
 board/freescale/ls2080aqds/ls2080aqds.c| 9 +
 include/configs/ls2080aqds.h   | 6 ++
 3 files changed, 17 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index bfff2ec..7c47cc8 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -128,6 +128,8 @@
 #define DCFG_PORSR1_RCW_SRC_NOR0x12f0
 #define DCFG_RCWSR13   0x130
 #define DCFG_RCWSR13_DSPI  (0 << 8)
+#define DCFG_RCWSR15   0x138
+#define DCFG_RCWSR15_IFCGRPABASE_QSPI  0x3
 
 #define DCFG_DCSR_BASE 0X70010ULL
 #define DCFG_DCSR_PORCR1   0x000
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index 19bb4c6..8bdcb04 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -208,6 +208,15 @@ int board_init(void)
else
config_board_mux(MUX_TYPE_SDHC);
 
+#if defined(CONFIG_NAND) && defined(CONFIG_FSL_QSPI)
+   val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
+
+   if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
+   QIXIS_WRITE(brdcfg[9],
+   (QIXIS_READ(brdcfg[9]) & 0xf8) |
+FSL_QIXIS_BRDCFG9_QSPI);
+#endif
+
 #ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)_environment[0];
 #endif
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index f917484..13e18db 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -304,6 +304,12 @@ unsigned long get_board_ddr_clk(void);
 #define FSL_QSPI_FLASH_SIZE(1 << 26) /* 64MB */
 #define FSL_QSPI_FLASH_NUM 4
 #endif
+/*
+ * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
+ * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
+ * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
+ */
+#define FSL_QIXIS_BRDCFG9_QSPI 0x1
 #endif
 
 /*
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v5 04/10] armv8: ls2080aqds: disable IFC NOR & QIXIS when QSPI enable

[Yuan Yao]

From: Yuan Yao 

When QSPI is enabled, NOR flash and QIXIS can't be accessed
through IFC due to pin mux.
So enable I2C QIXIS access and I2C early init to read the
sysclk and ddrclk.

Signed-off-by: Yuan Yao 
---
Changed in v5:
Use I2C to read the clocks instead of the hard-coded clocks. 
---
 board/freescale/ls2080aqds/ls2080aqds.c |  3 +++
 include/configs/ls2080aqds.h| 10 ++
 2 files changed, 13 insertions(+)

diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index d7acb48..19bb4c6 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -219,6 +219,9 @@ int board_init(void)
 
 int board_early_init_f(void)
 {
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+   i2c_early_init_f();
+#endif
fsl_lsch3_early_init_f();
 #ifdef CONFIG_FSL_QSPI
/* input clk: 1/2 platform clk, output: input/20 */
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 4b27114..99b0551 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -17,6 +17,16 @@ unsigned long get_board_ddr_clk(void);
 #endif
 
 #define CONFIG_SYS_FSL_CLK
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_FPGA_ADDR   0x66
+#define CONFIG_SYS_I2C_EARLY_INIT
+#define CONFIG_SYS_I2C_IFDR_DIV0x7e
+#endif
+
 #define CONFIG_SYS_CLK_FREQget_board_sys_clk()
 #define CONFIG_DDR_CLK_FREQget_board_ddr_clk()
 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v5 01/10] drivers: i2c: mxc: Add early init

[Yuan Yao]

From: Yuan Yao 

Add early i2c init function with conservative divider when the exact
clock rate is not available.

Signed-off-by: Yuan Yao 
---
New add in v3.
---
 drivers/i2c/i2c_core.c |  5 +
 drivers/i2c/mxc_i2c.c  | 27 +++
 include/i2c.h  |  3 +++
 3 files changed, 35 insertions(+)

diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c
index 41cc3b8..16b1aba 100644
--- a/drivers/i2c/i2c_core.c
+++ b/drivers/i2c/i2c_core.c
@@ -233,6 +233,11 @@ __weak void i2c_init_board(void)
 {
 }
 
+/* implement possible for i2c specific early i2c init */
+__weak void i2c_early_init_f(void)
+{
+}
+
 /*
  * i2c_init_all():
  *
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 445fa21..f340208 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -32,6 +32,14 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define IMX_I2C_REGSHIFT   2
 #define VF610_I2C_REGSHIFT 0
+
+#define I2C_EARLY_INIT_INDEX   0
+#ifdef CONFIG_SYS_I2C_IFDR_DIV
+#define I2C_IFDR_DIV_CONSERVATIVE  CONFIG_SYS_I2C_IFDR_DIV
+#else
+#define I2C_IFDR_DIV_CONSERVATIVE  0x7e
+#endif
+
 /* Register index */
 #define IADR   0
 #define IFDR   1
@@ -660,6 +668,25 @@ void bus_i2c_init(int index, int speed, int unused,
 }
 
 /*
+ * Early init I2C for prepare read the clk through I2C.
+ */
+void i2c_early_init_f(void)
+{
+   ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
+   bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
+   & I2C_QUIRK_FLAG ? true : false;
+   int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
+
+   /* Set I2C divider value */
+   writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
+   /* Reset module */
+   writeb(I2CR_IDIS, base + (I2CR << reg_shift));
+   writeb(0, base + (I2SR << reg_shift));
+   /* Enable I2C */
+   writeb(I2CR_IEN, base + (I2CR << reg_shift));
+}
+
+/*
  * Init I2C Bus
  */
 static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
diff --git a/include/i2c.h b/include/i2c.h
index 1f5ae45..d500445 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -701,6 +701,9 @@ extern struct i2c_bus_hose  i2c_bus[];
  * Initialization, must be called once on start up, may be called
  * repeatedly to change the speed and slave addresses.
  */
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+void i2c_early_init_f(void);
+#endif
 void i2c_init(int speed, int slaveaddr);
 void i2c_init_board(void);
 #ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v5 05/10] configs: ls2080aqds: Enable QSPI flash support

[Yuan Yao]

From: Yuan Yao 

Enable QSPI flash related configure options.

Signed-off-by: Yuan Yao 
---
 include/configs/ls2080aqds.h | 15 ++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 99b0551..f917484 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -289,8 +289,21 @@ unsigned long get_board_ddr_clk(void);
 #define I2C_MUX_CH_DEFAULT  0x8
 
 /* SPI */
-#ifdef CONFIG_FSL_DSPI
+#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
 #define CONFIG_SPI_FLASH
+#define CONFIG_CMD_SF
+
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_EON
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE(1 << 26) /* 64MB */
+#define FSL_QSPI_FLASH_NUM 4
+#endif
 #endif
 
 /*
-- 
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[U-Boot] [PATCH v5 00/10] armv8: ls2080aqds: Enable QSPI boot support

[Yuan Yao]

From: Yuan Yao 

This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.

Yuan Yao (10):
  drivers: i2c: mxc: Add early init
  armv8: ls2080aqds: Select QSPI CLK div via SCFG
  configs: ls2080a_common: Remove duplicate NOR configs
  armv8: ls2080aqds: disable IFC NOR & QIXIS when QSPI enable
Changed in v5.
  configs: ls2080aqds: Enable QSPI flash support
  dm: dts: ls2080aqds: Add QSPI dts node
  armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND boot
  configs: ls2080a: Increase load image len in NAND boot
  ls2080aqds_nand_defconfig: Enable QSPI & its dependence
  armv8: ls2080aqds: Enable QSPI boot support

 arch/arm/dts/fsl-ls2080a-qds.dts   | 14 +++
 arch/arm/dts/fsl-ls2080a.dtsi  | 10 +
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |  4 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  3 ++
 board/freescale/ls2080aqds/ls2080aqds.c| 19 ++
 configs/ls2080aqds_nand_defconfig  |  8 
 configs/ls2080aqds_qspi_defconfig  | 27 ++
 drivers/i2c/i2c_core.c |  5 +++
 drivers/i2c/mxc_i2c.c  | 27 ++
 include/configs/ls2080a_common.h   | 11 ++
 include/configs/ls2080a_simu.h |  7 
 include/configs/ls2080aqds.h   | 43 +-
 include/i2c.h  |  3 ++
 13 files changed, 171 insertions(+), 10 deletions(-)
 create mode 100644 configs/ls2080aqds_qspi_defconfig

-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v5 02/10] armv8: ls2080aqds: Select QSPI CLK div via SCFG

[Yuan Yao]

From: Yuan Yao 

QSPI module output SCLK divisor value is configured through SCFG.

Signed-off-by: Yuan Yao 
---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
 board/freescale/ls2080aqds/ls2080aqds.c| 5 +
 2 files changed, 6 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 65b3357..bfff2ec 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -139,6 +139,7 @@
 /* Supplemental Configuration */
 #define SCFG_BASE  0x01fc
 #define SCFG_USB3PRM1CR0x000
+#define SCFG_QSPICLKCTLR   0x10
 
 #define TP_ITYP_AV 0x0001  /* Initiator available */
 #define TP_ITYP_TYPE(x)(((x) & 0x6) >> 1)  /* Initiator Type */
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index b3bd40a..d7acb48 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -26,6 +26,7 @@
 
 #define PIN_MUX_SEL_SDHC   0x00
 #define PIN_MUX_SEL_DSPI   0x0a
+#define SCFG_QSPICLKCTRL_DIV_20(5 << 27)
 
 #define SET_SDHC_MUX_SEL(reg, value)   ((reg & 0xf0) | value)
 
@@ -219,6 +220,10 @@ int board_init(void)
 int board_early_init_f(void)
 {
fsl_lsch3_early_init_f();
+#ifdef CONFIG_FSL_QSPI
+   /* input clk: 1/2 platform clk, output: input/20 */
+   out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
+#endif
return 0;
 }
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v5 03/10] configs: ls2080a_common: Remove duplicate NOR configs

[Yuan Yao]

From: Yuan Yao 

The NOR flash related configure options also appear in ls2080aqds.h and
ls2080ardb.h, and the two files all have included ls2080a_common.h.
This patch remove the duplicated options in ls2080a_common.h.

Signed-off-by: Yuan Yao 
---
 include/configs/ls2080a_common.h | 7 ---
 include/configs/ls2080a_simu.h   | 7 +++
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index c78aeb5..48b1e15 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -138,13 +138,6 @@
 #define CONFIG_SYS_FLASH1_BASE_PHYS0xC000
 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY  0x800
 
-#ifndef CONFIG_SYS_NO_FLASH
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#endif
-
 #ifndef __ASSEMBLY__
 unsigned long long get_qixis_addr(void);
 #endif
diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h
index 7563aaf..7f245b5 100644
--- a/include/configs/ls2080a_simu.h
+++ b/include/configs/ls2080a_simu.h
@@ -30,6 +30,13 @@
 #define CONFIG_SYS_NOR0_CSPR_EXT   (0x0)
 #define CONFIG_SYS_NOR_AMASK   IFC_AMASK(128*1024*1024)
 
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#endif
+
 /*
  * NOR Flash Timing Params
  */
-- 
2.1.0.27.g96db324

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Re: [U-Boot] [PATCH 0/3] This series adds support for fastboot related to USB.

[Lukasz Majewski]

Hi Marek, Eddie,

> On 06/07/2016 03:28 AM, Eddie Cai wrote:
> > Hi Lukasz
> > 
> > I guess you missed this mail thread. So send it again. Can you help
> > to review this patch set?
> 
> Hi,
> 
> please rebase the series and repost. Keep me on CC

I'm currently out of office. I will review those patches ASAP when I
will come back.

> 
> > 2016-01-18 14:24 GMT+08:00 Eddie Cai :
> >> Hi Lukasz
> >>
> >> Have you back to office? Much appreciate if you can review Frank's
> >> patch.
> >>
> >> Thanks
> >> Eddie
> >>
> >> 2015-12-30 17:14 GMT+08:00 Lukasz Majewski :
> >>> Hi Frank
> >>>
>   [PATCH 1/3] Modified the check condition for max packet size of
>  ep_in in high speed
> 
>   [PATCH 2/3] Fixed the error that the last packet transmission
>  could not be terminated
> 
>   [PATCH 3/3] Add usb phy control to support fastboot for rk3036
> 
>   Tested on RK3036 SDK board, it works Okay.
> >>>
> >>> I'm out of office till the beginning of Jan 2016.
> >>>
> >>> I will review and read your logs (with the max packet problem)
> >>> when I come back.
> >>>
> 
>   board/evb_rk3036/evb_rk3036/evb_rk3036.c   |   30
>  + drivers/usb/gadget/Makefile
>  |1 + drivers/usb/gadget/dwc2_udc_otg.c  |4 +--
>   drivers/usb/gadget/dwc2_udc_otg_regs.h |5 +++
>   drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c |2 +-
>   drivers/usb/gadget/rk_otg_phy.c|   48
>  
>  include/configs/rk3036_common.h|   20  7
>  files changed, 107 insertions(+), 3 deletions(-) create mode
>  100644 drivers/usb/gadget/rk_otg_phy.c
> 
> >>>
> >>> Best regards,
> >>> Lukasz Majewski
> >>>
> >>> ___
> >>> U-Boot mailing list
> >>> U-Boot@lists.denx.de
> >>> http://lists.denx.de/mailman/listinfo/u-boot
> >>>
> 
> 



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[U-Boot] UBI issues with DM355 and Micron NAND flash

[Andy Pont]

Hello,

I am working on an update to a Linux configuration for a custom TI DM355
based hardware platform which uses a Micron MT29F4G08ABADAWP NAND flash
device and U-Boot 2013.07 (which I can't change).  The boards have been
deployed in the field over a number of years using the NAND flash to store
the Linux kernel and a CramFS partition and all works well with the
following settings in the board config file:

#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NAND_CS  2
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_PAGE_2K
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_NAND_BASE_LIST   { 0x0200, }
#define CONFIG_SYS_MAX_NAND_DEVICE  1
#define CONFIG_SYS_NAND_MAX_CHIPS   1

As part of the update we are moving to a UBI root file system and this is
where problems are starting.  As an initial test I am using the following
commands in U-Boot to create the UBI partition:

U-Boot> nand erase.part rootfs
U-Boot> ubi part rootfs

All appears to be well but if I reset the hardware and then rerun the "ubi
part rootfs" command then I am bombarded with errors of the following type
which never seem to end but just change in the PEB being referenced:

UBI error: ubi_io_read: error -74 while reading 64 bytes from PEB 0:0, read
64 bytes
UBI error: ubi_io_read: error -74 while reading 512 bytes from PEB 0:512,
read 512 bytes
UBI error: ubi_io_read: error -74 while reading 64 bytes from PEB 1:0, read
64 bytes
UBI error: ubi_io_read: error -74 while reading 512 bytes from PEB 1:512,
read 512 bytes

The datasheet for the flash device says that in 8-bit mode a page size is
2048 + 64 bytes and as far as I can tell doesn't mention subpages and so I
am confused by the output from the "ubi part rootfs" command that states
that there are 512 byte sub-pages available:

UBI: physical eraseblock size:  131072 bytes (128 KiB)
UBI: logical eraseblock size:   129024 bytes
UBI: smallest flash I/O unit:   2048
UBI: sub-page size: 512
UBI: VID header offset: 512 (aligned 512)
UBI: data offset:   2048

I have had a look through the source but can't find anyway to disable
sub-page support or to tell it that a sub-page is the same size as the
smallest flash I/O unit.  Then again, I could be looking in completely the
wrong place.

Any thoughts...

Andy.


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[U-Boot] [PATCH v2] ARM: uniphier: insert dsb barrier to ensure visibility of store

[Masahiro Yamada]

I noticed secondary CPUs sometimes fail to wake up, and the root
cause is that the sev instruction wakes up slave CPUs before the
preceding the register write is observed by them.

The read-back of the accessed register does not guarantee the order.
In order to ensure the order between the register write and the sev
instruction, a dsb instruction should be executed prior to the sev.

Signed-off-by: Masahiro Yamada 
---

Changes in v2:
  - Use "dsb ishst" instead of "dsb sy"

 arch/arm/mach-uniphier/arm64/smp_kick_cpus.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c 
b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
index 64412e0..5971ad2 100644
--- a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
+++ b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
@@ -21,11 +21,11 @@ void uniphier_smp_kick_all_cpus(void)
rom_boot_rsv0 = map_sysmem(UNIPHIER_SMPCTRL_ROM_RSV0, SZ_8);
 
writeq((u64)uniphier_secondary_startup, rom_boot_rsv0);
-   readq(rom_boot_rsv0);   /* relax */
 
unmap_sysmem(rom_boot_rsv0);
 
uniphier_smp_setup();
 
-   asm("sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */
+   asm("dsbishst\n" /* Ensure the write to ROM_RSV0 is visible */
+   "sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */
 }
-- 
1.9.1

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[U-Boot] [PATCH 00/31] RFC: dm: Add support for compiled-in platform data

[Simon Glass]

This series provides a way to compile in the contents of a device tree as C
code into U-Boot. It is intended to deal with extremely tight environments
where there is not enough space for the ~3KB device tree code overhead.
Examples include SPL where there is only 16KB of available RAM yet a full
MMC stack is required.

To provide a reasonable test environment, SPL support is added to sandbox,
through a new 'sandbox_spl' target. A new tool 'dtoc' converts device tree
data to C code (and structure definitions).

More work is needed before this feature is ready for use, but this series
contains enough to attract initial comments and testing.


Simon Glass (31):
  sandbox: Don't print a warning for CONFIG_I2C_COMPAT
  README: Remove CONFIG_SYS_MALLOC_F_LEN comment
  spl: Drop include of i2c.h
  Makefile: Allow the SPL final link rule to be overridden
  sandbox: Allow chaining from SPL to U-Boot proper
  sandbox: Support building an SPL image
  sandbox: Correct header file order in cpu.c
  sandbox: Add some missing headers in cpu.c
  sandbox: Don't use PCI in SPL
  sandbox: Don't include the main loop in SPL
  sandbox: Add basic SPL implementation
  sandbox: Don't use IDE and iotrace in SPL
  sandbox: serial: Don't sync video in SPL
  sandbox: Add a new sandbox_spl board
  sandbox: Add a test device that uses of-platdata
  dm: spl: Don't set up device tree with of-platdata
  dm: Makefile: Build of-platdata before SPL
  dm: core: Don't use device tree with of-platdata
  dm: regmap: Add a dummy implementation for of-platdata
  dm: syscon: Add support for of-platdata
  dm: sandbox: Add a simple driver to test of-platdata
  dm: Add a header that provides access to the of-platdata structs
  dm: clk: Add support for of-platdata
  dm: serial: Add support for of-platdata
  dm: Don't include fdtdec functions when of-platdata is enabled
  dm: Add an option to enable the of-platdata feature
  dm: Add a README for of-platdata
  dm: Add a library to provide simple device-tree access
  dm: Add a tool to generate C code from a device tree
  dm: Makefile: Build of-platdata files when the feature is enabled
  dm: Add a more efficient libfdt library

 Makefile|   5 +-
 README  |   3 -
 arch/sandbox/Kconfig|   7 +-
 arch/sandbox/config.mk  |   5 +
 arch/sandbox/cpu/Makefile   |   1 +
 arch/sandbox/cpu/cpu.c  |   6 +-
 arch/sandbox/cpu/os.c   |  51 ++
 arch/sandbox/cpu/spl.c  |  60 +++
 arch/sandbox/cpu/start.c|   2 +
 arch/sandbox/cpu/u-boot-spl.lds |  24 +++
 arch/sandbox/dts/sandbox.dts|  13 ++
 arch/sandbox/include/asm/spl.h  |  23 +++
 arch/sandbox/lib/Makefile   |   2 +
 board/sandbox/MAINTAINERS   |   7 +
 common/spl/spl.c|   3 +-
 configs/sandbox_spl_defconfig   | 177 +++
 doc/driver-model/of-plat.txt| 266 +
 drivers/clk/clk-uclass.c|  20 +++
 drivers/clk/clk_fixed_rate.c|   2 +
 drivers/core/device.c   |   2 +-
 drivers/core/lists.c|   2 +-
 drivers/core/regmap.c   |   9 +
 drivers/core/root.c |   4 +-
 drivers/core/syscon-uclass.c|  13 ++
 drivers/misc/Makefile   |   5 +
 drivers/misc/spltest_sandbox.c  |  28 +++
 drivers/serial/sandbox.c|   2 +
 drivers/serial/serial-uclass.c  |   8 +-
 dts/Kconfig |  21 +++
 include/clk.h   |   4 +
 include/configs/sandbox.h   |   4 +
 include/configs/sandbox_spl.h   |  20 +++
 include/dt-structs.h|  19 +++
 include/os.h|  25 +++
 include/regmap.h|   3 +
 include/syscon.h|   6 +
 lib/Makefile|   5 +-
 lib/libfdt/libfdt.swig  |  81 +
 lib/libfdt/setup.py |  38 +
 lib/libfdt/test_libfdt.py   |  14 ++
 scripts/Makefile.host   |   9 +-
 scripts/Makefile.spl|  45 -
 tools/Makefile  |  11 ++
 tools/dtoc/.gitignore   |   1 +
 tools/dtoc/dtoc |   1 +
 tools/dtoc/dtoc.py  | 365 
 tools/dtoc/fdt.py   | 174 +++
 tools/dtoc/fdt_fallback.py  | 207 +++
 tools/dtoc/fdt_util.py  |  71 
 49 files changed, 1849 insertions(+), 25 deletions(-)
 create mode 100644 arch/sandbox/cpu/spl.c
 create mode 100644 arch/sandbox/cpu/u-boot-spl.lds
 create mode 100644 arch/sandbox/include/asm/spl.h
 create mode 100644 configs/sandbox_spl_defconfig
 create mode 100644 doc/driver-model/of-plat.txt
 create mode 100644 drivers/misc/spltest_sandbox.c
 create mode 100644 include/configs/sandbox_spl.h
 create mode 100644 include/dt-structs.h
 create mode 100644 lib/libfdt/libfdt.swig
 create mode 100644 lib/libfdt/setup.py
 create mode 100644 lib/libfdt/test_libfdt.py
 create mode 100644 tools/dtoc/.gitignore
 create mode 12 

[U-Boot] [PATCH v4] armv8/ls2080a: configure PMU's PCTBENR to enable WDT

[Yunhui Cui]

From: Yunhui Cui 

The SP805-WDT module on LS2080A and LS2085A, requires configuration
of PMU's PCTBENR register to enable watchdog counter decrement and
reset signal generation. In order not to affect the sp805wdt driver
frame, we enable the watchdog clk in advance.

Signed-off-by: Yunhui Cui 
---
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 15 +++
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h |  1 +
 2 files changed, 16 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index d939900..1ac1067 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -639,6 +639,10 @@ int timer_init(void)
 #ifdef CONFIG_FSL_LSCH3
u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
 #endif
+#ifdef CONFIG_LS2080A
+   u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
+   u32 pmu_val;
+#endif
 #ifdef COUNTER_FREQUENCY_REAL
unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
 
@@ -653,6 +657,17 @@ int timer_init(void)
out_le32(cltbenr, 0xf);
 #endif
 
+#ifdef CONFIG_LS2080A
+/*
+ * In certain Layerscape SoCs, the clock for each core's
+ * has an enable bit in the PMU Physical Core Time Base Enable
+ * Register (PCTBENR), which allows the watchdog to operate.
+ */
+pmu_val = in_le32(pctbenr);
+pmu_val |= 0xff;
+out_le32(pctbenr, pmu_val);
+#endif
+
/* Enable clock for timer
 * This is a global setting.
 */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 1d3b336..ba3b94d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -26,6 +26,7 @@
 #define CONFIG_SYS_FSL_TIMER_ADDR  0x023d
 #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
 0x18A0)
+#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
 
 #define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B8)
 #define CONFIG_SYS_FSL_WRIOP1_MDIO1(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v5] armv8/ls2080a: configure PMU's PCTBENR to enable WDT

[Yunhui Cui]

From: Yunhui Cui 

The SP805-WDT module on LS2080A and LS2085A, requires configuration
of PMU's PCTBENR register to enable watchdog counter decrement and
reset signal generation. In order not to affect the sp805wdt driver
frame, we enable the watchdog clk in advance.

Signed-off-by: Yunhui Cui 
---
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 12 
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h |  1 +
 2 files changed, 13 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index d939900..79eb4dc 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -639,6 +639,9 @@ int timer_init(void)
 #ifdef CONFIG_FSL_LSCH3
u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
 #endif
+#ifdef CONFIG_LS2080A
+   u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
+#endif
 #ifdef COUNTER_FREQUENCY_REAL
unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
 
@@ -653,6 +656,15 @@ int timer_init(void)
out_le32(cltbenr, 0xf);
 #endif
 
+#ifdef CONFIG_LS2080A
+   /*
+* In certain Layerscape SoCs, the clock for each core's
+* has an enable bit in the PMU Physical Core Time Base Enable
+* Register (PCTBENR), which allows the watchdog to operate.
+*/
+   setbits_le32(pctbenr, 0xff);
+#endif
+
/* Enable clock for timer
 * This is a global setting.
 */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 1d3b336..8121939 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -26,6 +26,7 @@
 #define CONFIG_SYS_FSL_TIMER_ADDR  0x023d
 #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
 0x18A0)
+#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
 
 #define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B8)
 #define CONFIG_SYS_FSL_WRIOP1_MDIO1(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
-- 
2.1.0.27.g96db324

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Re: [U-Boot] u-boot on Minnowboard max

[vinoth eswaran]

Hello Mr.BIn,

 I tested using the latest u-boot (u-boot-2016.07-rc1) with
CONFIG_GENERATE_ACPI_TABLE=y enabled. I am still facing the same
issue, the Linux kernel is not able to initialize the root file system
from the sd card. I have attached the logs for your reference.

My Analysis:
[1.267312] sdhci-pci :00:12.0: failed to setup card detect
gpio -- this error message I am seeing with UEFI firmware also. So I
am assuming it is not the issue here.

I have done some debugging of MMC initialisation and found that in
mmc_rescan function (drivers/mmc/core/core.c)

host->ops->get_cd(host) returns 0

and the condition is failed. So MMC is not getting intialized.  i
checked the return of

 !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); and
here I am seeing that

with U-boot version it is 1FA and bit AND with 0x0001 is zero
(condition fails)
with UEFI version it is 1FF and bit AND with 0x0001 is one
(condition succeeded)


Do you have any idea why this is happening, any input from your side
will help me

Thanks a lot:)


Mit Freundlichen Grüßen
VinothKumar
+49 1798909072


On Tue, Jun 7, 2016 at 11:43 AM, Bin Meng  wrote:
> Hi,
>
> On Tue, Jun 7, 2016 at 2:09 PM, vinoth eswaran  wrote:
>> Hello Mr.Bin,
>>
>
> Please keep the ML in the loop, also avoid top-posting, and always use
> plain text.
>
>>  I have attached the start up logs for your reference, I have added some
>> debug messages also and I have disabled the SDIO (0f15) by removing it from
>> u-boot , so please ignore that.
>>
>> bootcmd=fatload mmc 0:1 0100 bzImage; zboot 0100
>>
>> I am not passing any commnd line from u-boot.
>>
>> Since I have builded a customised Linux kernel I have the command line added
>> in one of the .scc files.
>>
>> Kernel command line: root=/dev/mmcblk0p2 rootwait rootfstype=ext4
>> console=ttyS0,115200 console=tty0
>>
>> My View:
>>
>> By UEFI SDHCI is on ACPI
>>
>>  mmc0: SDHCI controller on ACPI [80860F16:00] using ADMA
>>
>> and by u-boot SDHCI is on PCI
>>
>>  mmc0: SDHCI controller on PCI [:00:12.0] using ADMA
>>
>> and I think that something is missing in U-boot or Linux , so it is unable
>> to initialize SD card. It will be great , if u give me some inputs to fix
>> this issue.
>>
>
> Just some initial investigation based on your log. It looks Linux kernel 
> prints:
>
> [1.267312] sdhci-pci :00:12.0: failed to setup card detect gpio
>
> where it calls mmc_gpiod_request_cd() in drivers/mmc/host/sdhci-pci-core.c:
>
> mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx,
>  slot->cd_override_level, 0, NULL)) {
> dev_warn(>dev, "failed to setup card detect gpio\n");
> slot->cd_idx = -1;
> }
>
> I did not have time to debug this, but based on the API name it looks
> to me this mmc_gpiod_request_cd() has something to do with GPIO where
> the Linux SDHC driver requests a card detect signal from a GPIO pin.
>
> On BayTrail, GPIO driver in Linux only works with ACPI as it cannot be
> discovered via PCI, so U-Boot must ship with an ACPI table, which is
> already supported in the latest mainline. Please do the same testing
> with the latest U-Boot to see if the problem still exists.
>
> Regards,
> Bin


U-Boot 2016.07-rc1 (Jun 07 2016 - 13:20:16 +0200)

CPU: x86_64, vendor Intel, device 30679h
DRAM:  2 GiB
MMC:   ValleyView SDHCI: 0, ValleyView SDHCI: 1
SF: Detected W25Q64CV with page size 256 Bytes, erase size 4 KiB, total 8 MiB
*** Warning - bad CRC, using default environment

Video: 1280x1024x16
Model: Intel Minnowboard Max
SCSI:  SATA link 0 timeout.
SATA link 1 timeout.
AHCI 0001.0300 32 slots 2 ports 3 Gbps 0x3 impl SATA mode
flags: 64bit ncq stag pm led clo pio slum part sxs 
scanning bus for devices...
Found 0 device(s).
Net:   
Warning: eth_rtl8169 using MAC address from ROM
eth0: eth_rtl8169
Hit any key to stop autoboot:  0 
reading bzImage
6399552 bytes read in 140 ms (43.6 MiB/s)
Valid Boot Flag
Setup Size = 0x3e00
Magic signature found
Using boot protocol version 2.0d
Linux kernel version 4.4.6-ina (vies7605@eso9265) #1 SMP Tue Jun 7 11:01:38 
CEST 2016
Building boot_params at 0x0009
Loading bzImage at address 10 (6383680 bytes)
Magic signature found
Kernel command line: ""

Starting kernel ...

Timer summary in microseconds:
   MarkElapsed  Stage
  0  0  reset
  2,347,210  2,347,210  id=64
  2,363,146 15,936  id=65
  2,370,143  6,997  main_loop
  4,794,855  2,424,712  start_kernel

Accumulated time:
   464,790  ahci
 1,743,341  vesa display
[0.00] Linux Kernel start_kernel start 
[0.00] Initializing cgroup subsys cpuset
[0.00] Initializing cgroup subsys cpu
[0.00] Initializing cgroup subsys cpuacct
[0.00] Linux version 4.4.6-ina (vies7605@eso9265) (gcc version 5.3.0 
(GCC) ) #1 SMP Tue Jun 7 11:01:38 CEST 2016
[0.00] 

[U-Boot] [PATCH] arm: dra7xx: Assign omap_vcores based on board type

[Keerthy]

Currently omap_vcores which holds pmic data is being assigned based
on the SoC type. PMIC is not a part of SoC. It is logical to
to assign omap_vcores based on board type. Hence over ride the
vcores_init function and assign omap_vcores based on the board type.

Reported-by: Nishanth Menon 
Signed-off-by: Keerthy 
---

Boot tested on both dra7-evm and dra72-evm.

 arch/arm/cpu/armv7/omap5/hw_data.c | 78 
 board/ti/dra7xx/evm.c  | 91 ++
 2 files changed, 91 insertions(+), 78 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c 
b/arch/arm/cpu/armv7/omap5/hw_data.c
index a517b13..65f43d6 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -364,82 +364,6 @@ struct vcores_data omap5430_volts_es2 = {
.mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK,
 };
 
-struct vcores_data dra752_volts = {
-   .mpu.value  = VDD_MPU_DRA7,
-   .mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU,
-   .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-   .mpu.addr   = TPS659038_REG_ADDR_SMPS12,
-   .mpu.pmic   = ,
-   .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
-
-   .eve.value  = VDD_EVE_DRA7,
-   .eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE,
-   .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-   .eve.addr   = TPS659038_REG_ADDR_SMPS45,
-   .eve.pmic   = ,
-   .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
-
-   .gpu.value  = VDD_GPU_DRA7,
-   .gpu.efuse.reg  = STD_FUSE_OPP_VMIN_GPU,
-   .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-   .gpu.addr   = TPS659038_REG_ADDR_SMPS6,
-   .gpu.pmic   = ,
-   .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
-
-   .core.value = VDD_CORE_DRA7,
-   .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
-   .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-   .core.addr  = TPS659038_REG_ADDR_SMPS7,
-   .core.pmic  = ,
-
-   .iva.value  = VDD_IVA_DRA7,
-   .iva.efuse.reg  = STD_FUSE_OPP_VMIN_IVA,
-   .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-   .iva.addr   = TPS659038_REG_ADDR_SMPS8,
-   .iva.pmic   = ,
-   .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
-};
-
-struct vcores_data dra722_volts = {
-   .mpu.value  = VDD_MPU_DRA7,
-   .mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU,
-   .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-   .mpu.addr   = TPS65917_REG_ADDR_SMPS1,
-   .mpu.pmic   = ,
-   .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
-
-   .core.value = VDD_CORE_DRA7,
-   .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
-   .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-   .core.addr  = TPS65917_REG_ADDR_SMPS2,
-   .core.pmic  = ,
-
-   /*
-* The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
-* designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
-*/
-   .gpu.value  = VDD_GPU_DRA7,
-   .gpu.efuse.reg  = STD_FUSE_OPP_VMIN_GPU,
-   .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-   .gpu.addr   = TPS65917_REG_ADDR_SMPS3,
-   .gpu.pmic   = ,
-   .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
-
-   .eve.value  = VDD_EVE_DRA7,
-   .eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE,
-   .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-   .eve.addr   = TPS65917_REG_ADDR_SMPS3,
-   .eve.pmic   = ,
-   .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
-
-   .iva.value  = VDD_IVA_DRA7,
-   .iva.efuse.reg  = STD_FUSE_OPP_VMIN_IVA,
-   .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-   .iva.addr   = TPS65917_REG_ADDR_SMPS3,
-   .iva.pmic   = ,
-   .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
-};
-
 /*
  * Enable essential clock domains, modules and
  * do some additional special settings needed
@@ -804,7 +728,6 @@ void __weak hw_data_init(void)
case DRA752_ES2_0:
*prcm = _prcm;
*dplls_data = _dplls;
-   *omap_vcores = _volts;
*ctrl = _ctrl;
break;
 
@@ -812,7 +735,6 @@ void __weak hw_data_init(void)
case DRA722_ES2_0:
*prcm = _prcm;
*dplls_data = _dplls;
-   *omap_vcores = _volts;
*ctrl = _ctrl;
break;
 
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 8c916a3..c5f7190 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -310,6 +310,82 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs 
**dmm_lisa_regs)
}
 }
 
+struct vcores_data dra752_volts = {
+   .mpu.value  = VDD_MPU_DRA7,
+   .mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU,
+   .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+   .mpu.addr   = TPS659038_REG_ADDR_SMPS12,
+   .mpu.pmic   = ,
+   .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+
+   .eve.value  = 

[U-Boot] [PATCH v2] mx6: Add Phytec PCM058 i.MX6 Quad

[Stefano Babic]

Add Phytec-i.MX6 SOM with NAND

  Support:
   - 1GB RAM
   - Ethernet
   - SPI-NOR Flash
   - NAND (1024 MB)
   - external SD
   - UART

Signed-off-by: Stefano Babic 
---

Changes in v2:
- set DDR strauctures as static
- improve README
- drop references to mira
- remove #if 1

 arch/arm/cpu/armv7/mx6/Kconfig  |   5 +
 board/phytec/pcm058/Kconfig |  12 +
 board/phytec/pcm058/MAINTAINERS |   6 +
 board/phytec/pcm058/Makefile|   9 +
 board/phytec/pcm058/README  |  35 +++
 board/phytec/pcm058/pcm058.c| 582 
 configs/pcm058_defconfig|  33 +++
 include/configs/pcm058.h| 140 ++
 8 files changed, 822 insertions(+)
 create mode 100644 board/phytec/pcm058/Kconfig
 create mode 100644 board/phytec/pcm058/MAINTAINERS
 create mode 100644 board/phytec/pcm058/Makefile
 create mode 100644 board/phytec/pcm058/README
 create mode 100644 board/phytec/pcm058/pcm058.c
 create mode 100644 configs/pcm058_defconfig
 create mode 100644 include/configs/pcm058.h

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 663f970..7d22e32 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -148,6 +148,10 @@ config TARGET_PLATINUM_TITANIUM
bool "platinum-titanium"
select SUPPORT_SPL
 
+config TARGET_PCM058
+   bool "Phytec PCM058 i.MX6 Quad"
+   select SUPPORT_SPL
+
 config TARGET_SECOMX6
bool "secomx6 boards"
 
@@ -200,6 +204,7 @@ source "board/freescale/mx6slevk/Kconfig"
 source "board/freescale/mx6sxsabresd/Kconfig"
 source "board/freescale/mx6sxsabreauto/Kconfig"
 source "board/freescale/mx6ul_14x14_evk/Kconfig"
+source "board/phytec/pcm058/Kconfig"
 source "board/gateworks/gw_ventana/Kconfig"
 source "board/kosagi/novena/Kconfig"
 source "board/seco/Kconfig"
diff --git a/board/phytec/pcm058/Kconfig b/board/phytec/pcm058/Kconfig
new file mode 100644
index 000..d099275
--- /dev/null
+++ b/board/phytec/pcm058/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PCM058
+
+config SYS_BOARD
+   default "pcm058"
+
+config SYS_VENDOR
+   default "phytec"
+
+config SYS_CONFIG_NAME
+   default "pcm058"
+
+endif
diff --git a/board/phytec/pcm058/MAINTAINERS b/board/phytec/pcm058/MAINTAINERS
new file mode 100644
index 000..b0ca402
--- /dev/null
+++ b/board/phytec/pcm058/MAINTAINERS
@@ -0,0 +1,6 @@
+PHYTEC PHYBOARD MIRA
+M: Stefano Babic 
+S: Maintained
+F: board/phytec/pcm058/
+F: include/configs/pcm058.h
+F: configs/pcm058_defconfig
diff --git a/board/phytec/pcm058/Makefile b/board/phytec/pcm058/Makefile
new file mode 100644
index 000..97733b1
--- /dev/null
+++ b/board/phytec/pcm058/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski 
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := pcm058.o
diff --git a/board/phytec/pcm058/README b/board/phytec/pcm058/README
new file mode 100644
index 000..3327135
--- /dev/null
+++ b/board/phytec/pcm058/README
@@ -0,0 +1,35 @@
+Board information
+-
+
+The SBC produced by Phytec has a SOM based on a i.MX6Q.
+The SOM is sold in two versions, with eMMC or with NAND. Support
+here is for the SOM with NAND.
+The evaluation board "phyBoard-Mira" is thought to be used
+together with the SOM.
+
+More information on the board can be found on manufacturer's
+website:
+
+http://www.phytec.de/produkt/single-board-computer/phyboard-mira/
+http://www.phytec.de/fileadmin/user_upload/images/content/1.Products/SOMs/phyCORE-i.MX6/L-808e_1.pdf
+
+Building U-Boot
+---
+
+$ make pcm058_defconfig
+$ make
+
+This generates the artifacts SPL and u-boot.img.
+The SOM can boot from NAND or from SD-Card, having the SPI-NOR
+as second option.
+The dip switch "DIP-1" on the board let choose between
+NAND and SD.
+
+DIP-1 set to off:  Boot first from NAND, then try SPI
+DIP-1 set to on:   Boot first from SD, then try SPI
+
+The bootloader was tested with DIP-1 set to on. If a SD-card
+is present, then the RBL tries to load SPL from the SD Card, if not,
+RBL loads from SPI-NOR. The SPL tries then to load from the same
+device where SPL was loaded (SD or SPI). Booting from NAND is
+not supported.
diff --git a/board/phytec/pcm058/pcm058.c b/board/phytec/pcm058/pcm058.c
new file mode 100644
index 000..0ba4a2e
--- /dev/null
+++ b/board/phytec/pcm058/pcm058.c
@@ -0,0 +1,582 @@
+/*
+ * Copyright (C) 2016 Stefano Babic 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * Please note: there are two version of the board
+ * one with NAND and the other with eMMC.
+ * Both NAND and eMMC cannot be set because they share the
+ * same pins (SD4)
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 

[U-Boot] [PATCH 0/3] Add USB EHCI support for ls1012aqds

[Rajesh Bhagat]

Adds USB EHCI support for ls1012qds by adding the support 
for NXP ULPI PHY and adding the support it configuration
files. Also enables, USB2 IP in ns access defines. 

Rajesh Bhagat (3):
  drivers: usb: fsl: add USB ULPI init code
  config: ls1012aqds: Add USB EHCI support for ls1012aqds
  armv8: ls1012a: Added CSU assignment for USB2

 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |1 +
 .../include/asm/arch-fsl-layerscape/ns_access.h|2 +
 drivers/usb/host/ehci-fsl.c|   21 
 include/configs/ls1012aqds.h   |5 
 include/usb/ehci-ci.h  |2 +-
 5 files changed, 30 insertions(+), 1 deletions(-)

-- 
1.7.7.4

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[U-Boot] [PATCH 2/3] config: ls1012aqds: Add USB EHCI support for ls1012aqds

[Rajesh Bhagat]

Add USB EHCI support for ls1012aqds platform

Signed-off-by: Rajat Srivastava 
Signed-off-by: Rajesh Bhagat 
---
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |1 +
 include/configs/ls1012aqds.h   |5 +
 include/usb/ehci-ci.h  |2 +-
 3 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 0c87c2f..b1637da 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -34,6 +34,7 @@
 #define CONFIG_SYS_XHCI_USB1_ADDR  (CONFIG_SYS_IMMR + 0x01f0)
 #define CONFIG_SYS_XHCI_USB2_ADDR  (CONFIG_SYS_IMMR + 0x0200)
 #define CONFIG_SYS_XHCI_USB3_ADDR  (CONFIG_SYS_IMMR + 0x0210)
+#define CONFIG_SYS_EHCI_USB1_ADDR  (CONFIG_SYS_IMMR + 0x0760)
 #define CONFIG_SYS_PCIE1_ADDR  (CONFIG_SYS_IMMR + 0x240)
 #define CONFIG_SYS_PCIE2_ADDR  (CONFIG_SYS_IMMR + 0x250)
 #define CONFIG_SYS_PCIE3_ADDR  (CONFIG_SYS_IMMR + 0x260)
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
index fcf402c..482a6d7 100644
--- a/include/configs/ls1012aqds.h
+++ b/include/configs/ls1012aqds.h
@@ -117,6 +117,8 @@
 #ifdef CONFIG_HAS_FSL_DR_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_ULPI
+#define CONFIG_USB_ULPI_VIEWPORT
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #endif
 
@@ -127,6 +129,9 @@
 #define CONFIG_USB_XHCI_FSL
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS  2
+#endif
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
 #define CONFIG_USB_STORAGE
 #endif
 
diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h
index 882aed4..38d557c 100644
--- a/include/usb/ehci-ci.h
+++ b/include/usb/ehci-ci.h
@@ -159,7 +159,7 @@
 #elif defined(CONFIG_MPC512X)
 #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
 #define CONFIG_SYS_FSL_USB2_ADDR   0
-#elif defined(CONFIG_LS102XA)
+#elif defined(CONFIG_LS102XA) || defined(CONFIG_LS1012A)
 #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR
 #define CONFIG_SYS_FSL_USB2_ADDR0
 #endif
-- 
1.7.7.4

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[U-Boot] [PATCH 1/3] drivers: usb: fsl: add USB ULPI init code

[Rajesh Bhagat]

This adds the required code to set up a ULPI USB port, for
new NXP USB PHY used in QorIQ platforms.

To use this both CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT
have to be set in the board configuration file.

Signed-off-by: Rajesh Bhagat 
---
 drivers/usb/host/ehci-fsl.c |   21 +
 1 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index a43d37d..897f453 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -16,6 +16,9 @@
 #include 
 #include 
 #include 
+#ifdef CONFIG_USB_ULPI
+#include 
+#endif
 
 #include "ehci.h"
 
@@ -50,6 +53,10 @@ int ehci_hcd_init(int index, enum usb_init_type init,
const char *phy_type = NULL;
size_t len;
char current_usb_controller[5];
+#ifdef CONFIG_USB_ULPI
+   int ret;
+   struct ulpi_viewport ulpi_vp;
+#endif
 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
char usb_phy[5];
 
@@ -126,6 +133,20 @@ int ehci_hcd_init(int index, enum usb_init_type init,
udelay(1000); /* delay required for PHY Clk to appear */
if (!usb_phy_clk_valid(ehci))
return -EINVAL;
+
+#ifdef CONFIG_USB_ULPI
+   ulpi_vp.viewport_addr = (u32)>ulpi_viewpoint;
+   ulpi_vp.port_num = 0;
+
+   ret = ulpi_init(_vp);
+   if (ret) {
+   puts("NXP ULPI viewport init failed\n");
+   return -1;
+   }
+
+   ulpi_set_vbus(_vp, 1, 1);
+   ulpi_set_vbus_indicator(_vp, 1, 1, 1);
+#endif
out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
}
 
-- 
1.7.7.4

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[U-Boot] [PATCH 3/3] armv8: ls1012a: Added CSU assignment for USB2

[Rajesh Bhagat]

Access settings for USB2 IP is added through CSU register.

Added CSU ID for USB2, reg: CSL23_REG[8:0]

Signed-off-by: Rajesh Bhagat 
---
 .../include/asm/arch-fsl-layerscape/ns_access.h|2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h 
b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
index db76066..b7da381 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
@@ -38,6 +38,7 @@ enum csu_cslx_ind {
CSU_CSLX_ESDHC,
CSU_CSLX_IFC = 45,
CSU_CSLX_I2C1,
+   CSU_CSLX_USB_2,
CSU_CSLX_I2C3 = 48,
CSU_CSLX_I2C2,
CSU_CSLX_DUART2 = 50,
@@ -117,6 +118,7 @@ static struct csu_ns_dev ns_dev[] = {
 {CSU_CSLX_ESDHC, CSU_ALL_RW},
 {CSU_CSLX_IFC, CSU_ALL_RW},
 {CSU_CSLX_I2C1, CSU_ALL_RW},
+{CSU_CSLX_USB_2, CSU_ALL_RW},
 {CSU_CSLX_I2C3, CSU_ALL_RW},
 {CSU_CSLX_I2C2, CSU_ALL_RW},
 {CSU_CSLX_DUART2, CSU_ALL_RW},
-- 
1.7.7.4

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